diff options
author | bibo,mao <bibo.mao@intel.com> | 2006-06-26 07:57:25 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-26 13:48:17 -0400 |
commit | 2b28592b07223d7fc0691ce3fe57d495dc9cbe3a (patch) | |
tree | ca5c7939d8b23fb40714784fa4a5040ddcd8a7d1 | |
parent | a813ce432f27c4f5011c7b5ac9d2bbbfeb41d9a7 (diff) |
[PATCH] x86_64: x86_86 msi miss one entry handler
In x86_64 architecture, if device driver with msi function
gets 0xee vector by assign_irq_vector() function, system will
crash if this interrupt happens. It is because 0xee interrupt
entry is empty. This patch modifies this. This patch is based
on 2.6.17-rc6.
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
-rw-r--r-- | arch/x86_64/kernel/i8259.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/x86_64/kernel/i8259.c b/arch/x86_64/kernel/i8259.c index 5ecd34ab8c2b..9b1a4e147321 100644 --- a/arch/x86_64/kernel/i8259.c +++ b/arch/x86_64/kernel/i8259.c | |||
@@ -44,11 +44,11 @@ | |||
44 | BI(x,8) BI(x,9) BI(x,a) BI(x,b) \ | 44 | BI(x,8) BI(x,9) BI(x,a) BI(x,b) \ |
45 | BI(x,c) BI(x,d) BI(x,e) BI(x,f) | 45 | BI(x,c) BI(x,d) BI(x,e) BI(x,f) |
46 | 46 | ||
47 | #define BUILD_14_IRQS(x) \ | 47 | #define BUILD_15_IRQS(x) \ |
48 | BI(x,0) BI(x,1) BI(x,2) BI(x,3) \ | 48 | BI(x,0) BI(x,1) BI(x,2) BI(x,3) \ |
49 | BI(x,4) BI(x,5) BI(x,6) BI(x,7) \ | 49 | BI(x,4) BI(x,5) BI(x,6) BI(x,7) \ |
50 | BI(x,8) BI(x,9) BI(x,a) BI(x,b) \ | 50 | BI(x,8) BI(x,9) BI(x,a) BI(x,b) \ |
51 | BI(x,c) BI(x,d) | 51 | BI(x,c) BI(x,d) BI(x,e) |
52 | 52 | ||
53 | /* | 53 | /* |
54 | * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts: | 54 | * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts: |
@@ -73,13 +73,13 @@ BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb) | |||
73 | BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) | 73 | BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) |
74 | 74 | ||
75 | #ifdef CONFIG_PCI_MSI | 75 | #ifdef CONFIG_PCI_MSI |
76 | BUILD_14_IRQS(0xe) | 76 | BUILD_15_IRQS(0xe) |
77 | #endif | 77 | #endif |
78 | 78 | ||
79 | #endif | 79 | #endif |
80 | 80 | ||
81 | #undef BUILD_16_IRQS | 81 | #undef BUILD_16_IRQS |
82 | #undef BUILD_14_IRQS | 82 | #undef BUILD_15_IRQS |
83 | #undef BI | 83 | #undef BI |
84 | 84 | ||
85 | 85 | ||
@@ -92,11 +92,11 @@ BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) | |||
92 | IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \ | 92 | IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \ |
93 | IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f) | 93 | IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f) |
94 | 94 | ||
95 | #define IRQLIST_14(x) \ | 95 | #define IRQLIST_15(x) \ |
96 | IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \ | 96 | IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \ |
97 | IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \ | 97 | IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \ |
98 | IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \ | 98 | IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \ |
99 | IRQ(x,c), IRQ(x,d) | 99 | IRQ(x,c), IRQ(x,d), IRQ(x,e) |
100 | 100 | ||
101 | void (*interrupt[NR_IRQS])(void) = { | 101 | void (*interrupt[NR_IRQS])(void) = { |
102 | IRQLIST_16(0x0), | 102 | IRQLIST_16(0x0), |
@@ -108,7 +108,7 @@ void (*interrupt[NR_IRQS])(void) = { | |||
108 | IRQLIST_16(0xc), IRQLIST_16(0xd) | 108 | IRQLIST_16(0xc), IRQLIST_16(0xd) |
109 | 109 | ||
110 | #ifdef CONFIG_PCI_MSI | 110 | #ifdef CONFIG_PCI_MSI |
111 | , IRQLIST_14(0xe) | 111 | , IRQLIST_15(0xe) |
112 | #endif | 112 | #endif |
113 | 113 | ||
114 | #endif | 114 | #endif |