diff options
author | Vasanthakumar Thiagarajan <vasanth@atheros.com> | 2009-01-02 05:05:46 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2009-01-29 15:59:46 -0500 |
commit | c97c92d92715ea4ea2d7cf00957e8a014439bdd8 (patch) | |
tree | a55e53c304358ebe9987fe73c69ec7ad4b885fe3 | |
parent | 7d969204882882585336b0fa19ad4587d8fb15a2 (diff) |
ath9k: Enable Bluetooth Coexistence support
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r-- | drivers/net/wireless/ath9k/ath9k.h | 5 | ||||
-rw-r--r-- | drivers/net/wireless/ath9k/hw.c | 33 | ||||
-rw-r--r-- | drivers/net/wireless/ath9k/main.c | 9 | ||||
-rw-r--r-- | drivers/net/wireless/ath9k/reg.h | 10 |
4 files changed, 55 insertions, 2 deletions
diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h index adcd34249a8b..f2ad62536bf8 100644 --- a/drivers/net/wireless/ath9k/ath9k.h +++ b/drivers/net/wireless/ath9k/ath9k.h | |||
@@ -198,6 +198,7 @@ enum ath9k_hw_caps { | |||
198 | ATH9K_HW_CAP_AUTOSLEEP = BIT(19), | 198 | ATH9K_HW_CAP_AUTOSLEEP = BIT(19), |
199 | ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20), | 199 | ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20), |
200 | ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21), | 200 | ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21), |
201 | ATH9K_HW_CAP_BT_COEX = BIT(22) | ||
201 | }; | 202 | }; |
202 | 203 | ||
203 | enum ath9k_capability_type { | 204 | enum ath9k_capability_type { |
@@ -752,6 +753,7 @@ struct ath9k_node_stats { | |||
752 | #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 | 753 | #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 |
753 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 | 754 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 |
754 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 | 755 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 |
756 | #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 | ||
755 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 | 757 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 |
756 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 | 758 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 |
757 | 759 | ||
@@ -801,6 +803,8 @@ struct ath_hal { | |||
801 | u16 ah_rfsilent; | 803 | u16 ah_rfsilent; |
802 | u32 ah_rfkill_gpio; | 804 | u32 ah_rfkill_gpio; |
803 | u32 ah_rfkill_polarity; | 805 | u32 ah_rfkill_polarity; |
806 | u32 ah_btactive_gpio; | ||
807 | u32 ah_wlanactive_gpio; | ||
804 | 808 | ||
805 | #ifndef ATH_NF_PER_CHAN | 809 | #ifndef ATH_NF_PER_CHAN |
806 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; | 810 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; |
@@ -1050,5 +1054,6 @@ void ath9k_hw_rxena(struct ath_hal *ah); | |||
1050 | void ath9k_hw_startpcureceive(struct ath_hal *ah); | 1054 | void ath9k_hw_startpcureceive(struct ath_hal *ah); |
1051 | void ath9k_hw_stoppcurecv(struct ath_hal *ah); | 1055 | void ath9k_hw_stoppcurecv(struct ath_hal *ah); |
1052 | bool ath9k_hw_stopdmarecv(struct ath_hal *ah); | 1056 | bool ath9k_hw_stopdmarecv(struct ath_hal *ah); |
1057 | void ath9k_hw_btcoex_enable(struct ath_hal *ah); | ||
1053 | 1058 | ||
1054 | #endif | 1059 | #endif |
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index 19144caa7977..3c026e6b2453 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c | |||
@@ -3341,6 +3341,12 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah) | |||
3341 | pCap->num_antcfg_2ghz = | 3341 | pCap->num_antcfg_2ghz = |
3342 | ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); | 3342 | ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); |
3343 | 3343 | ||
3344 | if (AR_SREV_9280_10_OR_LATER(ah)) { | ||
3345 | pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX; | ||
3346 | ah->ah_btactive_gpio = 6; | ||
3347 | ah->ah_wlanactive_gpio = 5; | ||
3348 | } | ||
3349 | |||
3344 | return true; | 3350 | return true; |
3345 | } | 3351 | } |
3346 | 3352 | ||
@@ -3836,3 +3842,30 @@ void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode) | |||
3836 | 3842 | ||
3837 | REG_WRITE(ah, AR_2040_MODE, macmode); | 3843 | REG_WRITE(ah, AR_2040_MODE, macmode); |
3838 | } | 3844 | } |
3845 | |||
3846 | /***************************/ | ||
3847 | /* Bluetooth Coexistence */ | ||
3848 | /***************************/ | ||
3849 | |||
3850 | void ath9k_hw_btcoex_enable(struct ath_hal *ah) | ||
3851 | { | ||
3852 | /* connect bt_active to baseband */ | ||
3853 | REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL, | ||
3854 | (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | | ||
3855 | AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF)); | ||
3856 | |||
3857 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, | ||
3858 | AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); | ||
3859 | |||
3860 | /* Set input mux for bt_active to gpio pin */ | ||
3861 | REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1, | ||
3862 | AR_GPIO_INPUT_MUX1_BT_ACTIVE, | ||
3863 | ah->ah_btactive_gpio); | ||
3864 | |||
3865 | /* Configure the desired gpio port for input */ | ||
3866 | ath9k_hw_cfg_gpio_input(ah, ah->ah_btactive_gpio); | ||
3867 | |||
3868 | /* Configure the desired GPIO port for TX_FRAME output */ | ||
3869 | ath9k_hw_cfg_output(ah, ah->ah_wlanactive_gpio, | ||
3870 | AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); | ||
3871 | } | ||
diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c index 9c1fb96acc5b..8929b02aa22d 100644 --- a/drivers/net/wireless/ath9k/main.c +++ b/drivers/net/wireless/ath9k/main.c | |||
@@ -431,12 +431,14 @@ static void ath_ani_calibrate(unsigned long data) | |||
431 | /* | 431 | /* |
432 | * Update tx/rx chainmask. For legacy association, | 432 | * Update tx/rx chainmask. For legacy association, |
433 | * hard code chainmask to 1x1, for 11n association, use | 433 | * hard code chainmask to 1x1, for 11n association, use |
434 | * the chainmask configuration. | 434 | * the chainmask configuration, for bt coexistence, use |
435 | * the chainmask configuration even in legacy mode. | ||
435 | */ | 436 | */ |
436 | static void ath_update_chainmask(struct ath_softc *sc, int is_ht) | 437 | static void ath_update_chainmask(struct ath_softc *sc, int is_ht) |
437 | { | 438 | { |
438 | sc->sc_flags |= SC_OP_CHAINMASK_UPDATE; | 439 | sc->sc_flags |= SC_OP_CHAINMASK_UPDATE; |
439 | if (is_ht) { | 440 | if (is_ht || |
441 | (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) { | ||
440 | sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask; | 442 | sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask; |
441 | sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask; | 443 | sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask; |
442 | } else { | 444 | } else { |
@@ -1519,6 +1521,9 @@ static int ath_init(u16 devid, struct ath_softc *sc) | |||
1519 | sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; | 1521 | sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; |
1520 | } | 1522 | } |
1521 | 1523 | ||
1524 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX) | ||
1525 | ath9k_hw_btcoex_enable(sc->sc_ah); | ||
1526 | |||
1522 | return 0; | 1527 | return 0; |
1523 | bad2: | 1528 | bad2: |
1524 | /* cleanup tx queues */ | 1529 | /* cleanup tx queues */ |
diff --git a/drivers/net/wireless/ath9k/reg.h b/drivers/net/wireless/ath9k/reg.h index 8cc9beff5ec1..9a615224e4f7 100644 --- a/drivers/net/wireless/ath9k/reg.h +++ b/drivers/net/wireless/ath9k/reg.h | |||
@@ -897,14 +897,24 @@ enum { | |||
897 | #define AR_GPIO_INTR_POL_VAL_S 0 | 897 | #define AR_GPIO_INTR_POL_VAL_S 0 |
898 | 898 | ||
899 | #define AR_GPIO_INPUT_EN_VAL 0x4054 | 899 | #define AR_GPIO_INPUT_EN_VAL 0x4054 |
900 | #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 | ||
901 | #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2 | ||
902 | #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 | ||
903 | #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S 3 | ||
904 | #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 | ||
905 | #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4 | ||
900 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 | 906 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 |
901 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 | 907 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 |
908 | #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 | ||
909 | #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12 | ||
902 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 | 910 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 |
903 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 | 911 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 |
904 | #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 | 912 | #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 |
905 | #define AR_GPIO_JTAG_DISABLE 0x00020000 | 913 | #define AR_GPIO_JTAG_DISABLE 0x00020000 |
906 | 914 | ||
907 | #define AR_GPIO_INPUT_MUX1 0x4058 | 915 | #define AR_GPIO_INPUT_MUX1 0x4058 |
916 | #define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 | ||
917 | #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 | ||
908 | 918 | ||
909 | #define AR_GPIO_INPUT_MUX2 0x405c | 919 | #define AR_GPIO_INPUT_MUX2 0x405c |
910 | #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f | 920 | #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f |