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authorLinus Torvalds <torvalds@g5.osdl.org>2005-12-14 02:08:24 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2005-12-14 02:08:24 -0500
commitacd9b7b4e08a3f0f48afa922d8e371414cf2d3b2 (patch)
tree663d7edaf98f220623a09a45ff33a1131f8bb727
parent2edc2689f8183dd21c45621a01580b340ac420ba (diff)
parent6921d201f77e14848df2eaa597e26525f468abea (diff)
Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/tg3-2.6
-rw-r--r--drivers/net/tg3.c66
-rw-r--r--drivers/net/tg3.h7
2 files changed, 64 insertions, 9 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 47bd4a394420..a23ed28a72b8 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -68,8 +68,8 @@
68 68
69#define DRV_MODULE_NAME "tg3" 69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": " 70#define PFX DRV_MODULE_NAME ": "
71#define DRV_MODULE_VERSION "3.44" 71#define DRV_MODULE_VERSION "3.45"
72#define DRV_MODULE_RELDATE "Dec 6, 2005" 72#define DRV_MODULE_RELDATE "Dec 13, 2005"
73 73
74#define TG3_DEF_MAC_MODE 0 74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0 75#define TG3_DEF_RX_MODE 0
@@ -1025,7 +1025,9 @@ static void tg3_frob_aux_power(struct tg3 *tp)
1025 1025
1026 1026
1027 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 || 1027 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1028 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) { 1028 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1029 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1030 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1029 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || 1031 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1030 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { 1032 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1031 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | 1033 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
@@ -1105,6 +1107,8 @@ static int tg3_setup_phy(struct tg3 *, int);
1105 1107
1106static void tg3_write_sig_post_reset(struct tg3 *, int); 1108static void tg3_write_sig_post_reset(struct tg3 *, int);
1107static int tg3_halt_cpu(struct tg3 *, u32); 1109static int tg3_halt_cpu(struct tg3 *, u32);
1110static int tg3_nvram_lock(struct tg3 *);
1111static void tg3_nvram_unlock(struct tg3 *);
1108 1112
1109static int tg3_set_power_state(struct tg3 *tp, int state) 1113static int tg3_set_power_state(struct tg3 *tp, int state)
1110{ 1114{
@@ -1179,6 +1183,21 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
1179 tg3_setup_phy(tp, 0); 1183 tg3_setup_phy(tp, 0);
1180 } 1184 }
1181 1185
1186 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1187 int i;
1188 u32 val;
1189
1190 for (i = 0; i < 200; i++) {
1191 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1192 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1193 break;
1194 msleep(1);
1195 }
1196 }
1197 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1198 WOL_DRV_STATE_SHUTDOWN |
1199 WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1200
1182 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps); 1201 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1183 1202
1184 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) { 1203 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
@@ -1268,6 +1287,17 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
1268 } 1287 }
1269 } 1288 }
1270 1289
1290 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1291 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1292 /* Turn off the PHY */
1293 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1294 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1295 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1296 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1297 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1298 }
1299 }
1300
1271 tg3_frob_aux_power(tp); 1301 tg3_frob_aux_power(tp);
1272 1302
1273 /* Workaround for unstable PLL clock */ 1303 /* Workaround for unstable PLL clock */
@@ -1277,8 +1307,12 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
1277 1307
1278 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); 1308 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1279 tw32(0x7d00, val); 1309 tw32(0x7d00, val);
1280 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) 1310 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1311 tg3_nvram_lock(tp);
1281 tg3_halt_cpu(tp, RX_CPU_BASE); 1312 tg3_halt_cpu(tp, RX_CPU_BASE);
1313 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR0);
1314 tg3_nvram_unlock(tp);
1315 }
1282 } 1316 }
1283 1317
1284 /* Finally, set the new power state. */ 1318 /* Finally, set the new power state. */
@@ -1812,7 +1846,7 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1812 } 1846 }
1813 } 1847 }
1814relink: 1848relink:
1815 if (current_link_up == 0) { 1849 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1816 u32 tmp; 1850 u32 tmp;
1817 1851
1818 tg3_phy_copper_begin(tp); 1852 tg3_phy_copper_begin(tp);
@@ -8533,6 +8567,7 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
8533 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { 8567 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
8534 tp->tg3_flags |= TG3_FLAG_NVRAM; 8568 tp->tg3_flags |= TG3_FLAG_NVRAM;
8535 8569
8570 tg3_nvram_lock(tp);
8536 tg3_enable_nvram_access(tp); 8571 tg3_enable_nvram_access(tp);
8537 8572
8538 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) 8573 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
@@ -8543,6 +8578,7 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
8543 tg3_get_nvram_size(tp); 8578 tg3_get_nvram_size(tp);
8544 8579
8545 tg3_disable_nvram_access(tp); 8580 tg3_disable_nvram_access(tp);
8581 tg3_nvram_unlock(tp);
8546 8582
8547 } else { 8583 } else {
8548 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED); 8584 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
@@ -8640,10 +8676,10 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
8640 if (ret == 0) 8676 if (ret == 0)
8641 *val = swab32(tr32(NVRAM_RDDATA)); 8677 *val = swab32(tr32(NVRAM_RDDATA));
8642 8678
8643 tg3_nvram_unlock(tp);
8644
8645 tg3_disable_nvram_access(tp); 8679 tg3_disable_nvram_access(tp);
8646 8680
8681 tg3_nvram_unlock(tp);
8682
8647 return ret; 8683 return ret;
8648} 8684}
8649 8685
@@ -8728,6 +8764,10 @@ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
8728 8764
8729 offset = offset + (pagesize - page_off); 8765 offset = offset + (pagesize - page_off);
8730 8766
8767 /* Nvram lock released by tg3_nvram_read() above,
8768 * so need to get it again.
8769 */
8770 tg3_nvram_lock(tp);
8731 tg3_enable_nvram_access(tp); 8771 tg3_enable_nvram_access(tp);
8732 8772
8733 /* 8773 /*
@@ -10437,8 +10477,13 @@ static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
10437 break; 10477 break;
10438 pci_dev_put(peer); 10478 pci_dev_put(peer);
10439 } 10479 }
10440 if (!peer || peer == tp->pdev) 10480 /* 5704 can be configured in single-port mode, set peer to
10441 BUG(); 10481 * tp->pdev in that case.
10482 */
10483 if (!peer) {
10484 peer = tp->pdev;
10485 return peer;
10486 }
10442 10487
10443 /* 10488 /*
10444 * We don't need to keep the refcount elevated; there's no way 10489 * We don't need to keep the refcount elevated; there's no way
@@ -10820,12 +10865,14 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
10820 10865
10821 tg3_full_lock(tp, 0); 10866 tg3_full_lock(tp, 0);
10822 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 10867 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10868 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
10823 tg3_full_unlock(tp); 10869 tg3_full_unlock(tp);
10824 10870
10825 err = tg3_set_power_state(tp, pci_choose_state(pdev, state)); 10871 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
10826 if (err) { 10872 if (err) {
10827 tg3_full_lock(tp, 0); 10873 tg3_full_lock(tp, 0);
10828 10874
10875 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10829 tg3_init_hw(tp); 10876 tg3_init_hw(tp);
10830 10877
10831 tp->timer.expires = jiffies + tp->timer_offset; 10878 tp->timer.expires = jiffies + tp->timer_offset;
@@ -10859,6 +10906,7 @@ static int tg3_resume(struct pci_dev *pdev)
10859 10906
10860 tg3_full_lock(tp, 0); 10907 tg3_full_lock(tp, 0);
10861 10908
10909 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10862 tg3_init_hw(tp); 10910 tg3_init_hw(tp);
10863 10911
10864 tp->timer.expires = jiffies + tp->timer_offset; 10912 tp->timer.expires = jiffies + tp->timer_offset;
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index fb7e2a5f4a08..94dbcf3537ec 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1529,6 +1529,12 @@
1529#define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14 1529#define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
1530#define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18 1530#define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
1531 1531
1532#define NIC_SRAM_WOL_MBOX 0x00000d30
1533#define WOL_SIGNATURE 0x474c0000
1534#define WOL_DRV_STATE_SHUTDOWN 0x00000001
1535#define WOL_DRV_WOL 0x00000002
1536#define WOL_SET_MAGIC_PKT 0x00000004
1537
1532#define NIC_SRAM_DATA_CFG_2 0x00000d38 1538#define NIC_SRAM_DATA_CFG_2 0x00000d38
1533 1539
1534#define SHASTA_EXT_LED_MODE_MASK 0x00018000 1540#define SHASTA_EXT_LED_MODE_MASK 0x00018000
@@ -1565,6 +1571,7 @@
1565#define MII_TG3_EXT_CTRL 0x10 /* Extended control register */ 1571#define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
1566#define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001 1572#define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
1567#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002 1573#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
1574#define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
1568#define MII_TG3_EXT_CTRL_TBI 0x8000 1575#define MII_TG3_EXT_CTRL_TBI 0x8000
1569 1576
1570#define MII_TG3_EXT_STAT 0x11 /* Extended status register */ 1577#define MII_TG3_EXT_STAT 0x11 /* Extended status register */