diff options
author | Guillaume Thouvenin <guillaume.thouvenin@ext.bull.net> | 2008-09-12 07:50:25 -0400 |
---|---|---|
committer | Avi Kivity <avi@qumranet.com> | 2008-10-15 04:16:14 -0400 |
commit | 9c9fddd0e784346a6d0ce82ed20d9ad21f3c8a2c (patch) | |
tree | c1bb4964cf454611ff2fafae8a57f464e78a1872 | |
parent | defed7ed926eca9f178a632df05baa866abe754e (diff) |
KVM: x86 emulator: Add DstAcc operand type
Add DstAcc operand type. That means that there are 4 bits now for
DstMask.
"In the good old days cpus would have only one register that was able to
fully participate in arithmetic operations, typically called A for
Accumulator. The x86 retains this tradition by having special, shorter
encodings for the A register (like the cmp opcode), and even some
instructions that only operate on A (like mul).
SrcAcc and DstAcc would accommodate these instructions by decoding A
into the corresponding 'struct operand'."
-- Avi Kivity
Signed-off-by: Guillaume Thouvenin <guillaume.thouvenin@ext.bull.net>
Signed-off-by: Avi Kivity <avi@qumranet.com>
-rw-r--r-- | arch/x86/kvm/x86_emulate.c | 50 |
1 files changed, 34 insertions, 16 deletions
diff --git a/arch/x86/kvm/x86_emulate.c b/arch/x86/kvm/x86_emulate.c index 0c120c4c9c0f..4390ec8c47a6 100644 --- a/arch/x86/kvm/x86_emulate.c +++ b/arch/x86/kvm/x86_emulate.c | |||
@@ -47,25 +47,26 @@ | |||
47 | #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */ | 47 | #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */ |
48 | #define DstReg (2<<1) /* Register operand. */ | 48 | #define DstReg (2<<1) /* Register operand. */ |
49 | #define DstMem (3<<1) /* Memory operand. */ | 49 | #define DstMem (3<<1) /* Memory operand. */ |
50 | #define DstMask (3<<1) | 50 | #define DstAcc (4<<1) /* Destination Accumulator */ |
51 | #define DstMask (7<<1) | ||
51 | /* Source operand type. */ | 52 | /* Source operand type. */ |
52 | #define SrcNone (0<<3) /* No source operand. */ | 53 | #define SrcNone (0<<4) /* No source operand. */ |
53 | #define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */ | 54 | #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */ |
54 | #define SrcReg (1<<3) /* Register operand. */ | 55 | #define SrcReg (1<<4) /* Register operand. */ |
55 | #define SrcMem (2<<3) /* Memory operand. */ | 56 | #define SrcMem (2<<4) /* Memory operand. */ |
56 | #define SrcMem16 (3<<3) /* Memory operand (16-bit). */ | 57 | #define SrcMem16 (3<<4) /* Memory operand (16-bit). */ |
57 | #define SrcMem32 (4<<3) /* Memory operand (32-bit). */ | 58 | #define SrcMem32 (4<<4) /* Memory operand (32-bit). */ |
58 | #define SrcImm (5<<3) /* Immediate operand. */ | 59 | #define SrcImm (5<<4) /* Immediate operand. */ |
59 | #define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */ | 60 | #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */ |
60 | #define SrcMask (7<<3) | 61 | #define SrcMask (7<<4) |
61 | /* Generic ModRM decode. */ | 62 | /* Generic ModRM decode. */ |
62 | #define ModRM (1<<6) | 63 | #define ModRM (1<<7) |
63 | /* Destination is only written; never read. */ | 64 | /* Destination is only written; never read. */ |
64 | #define Mov (1<<7) | 65 | #define Mov (1<<8) |
65 | #define BitOp (1<<8) | 66 | #define BitOp (1<<9) |
66 | #define MemAbs (1<<9) /* Memory operand is absolute displacement */ | 67 | #define MemAbs (1<<10) /* Memory operand is absolute displacement */ |
67 | #define String (1<<10) /* String instruction (rep capable) */ | 68 | #define String (1<<12) /* String instruction (rep capable) */ |
68 | #define Stack (1<<11) /* Stack instruction (push/pop) */ | 69 | #define Stack (1<<13) /* Stack instruction (push/pop) */ |
69 | #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */ | 70 | #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */ |
70 | #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */ | 71 | #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */ |
71 | #define GroupMask 0xff /* Group number stored in bits 0:7 */ | 72 | #define GroupMask 0xff /* Group number stored in bits 0:7 */ |
@@ -1060,6 +1061,23 @@ done_prefixes: | |||
1060 | } | 1061 | } |
1061 | c->dst.type = OP_MEM; | 1062 | c->dst.type = OP_MEM; |
1062 | break; | 1063 | break; |
1064 | case DstAcc: | ||
1065 | c->dst.type = OP_REG; | ||
1066 | c->dst.bytes = c->op_bytes; | ||
1067 | c->dst.ptr = &c->regs[VCPU_REGS_RAX]; | ||
1068 | switch (c->op_bytes) { | ||
1069 | case 1: | ||
1070 | c->dst.val = *(u8 *)c->dst.ptr; | ||
1071 | break; | ||
1072 | case 2: | ||
1073 | c->dst.val = *(u16 *)c->dst.ptr; | ||
1074 | break; | ||
1075 | case 4: | ||
1076 | c->dst.val = *(u32 *)c->dst.ptr; | ||
1077 | break; | ||
1078 | } | ||
1079 | c->dst.orig_val = c->dst.val; | ||
1080 | break; | ||
1063 | } | 1081 | } |
1064 | 1082 | ||
1065 | if (c->rip_relative) | 1083 | if (c->rip_relative) |