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authorPhil Sutter <n0-1@freewrt.org>2009-01-15 00:50:12 -0500
committerDavid S. Miller <davem@davemloft.net>2009-01-15 11:28:20 -0500
commit60d3f9827ca455e7272681d67a37137c328d7012 (patch)
tree19858fc9cb3d98ad2650a7f6bebf8e5d52166ad0
parent4676f63d4c1e2e3530e42cb39bf88a1c1d4d78a5 (diff)
korina: do tx at the right position
Triggering TX before the write to the DMA status mask register leads to transferring packets with maximum payload no matter what the actual packet size is. While here, also trigger RX scheduling after writing the DMA status mask register, like it was in the original driver before it was sent upstream. Signed-off-by: Phil Sutter <n0-1@freewrt.org> Acked-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/korina.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/net/korina.c b/drivers/net/korina.c
index 7aa05f81fe9e..dced5e71463a 100644
--- a/drivers/net/korina.c
+++ b/drivers/net/korina.c
@@ -330,13 +330,13 @@ static irqreturn_t korina_rx_dma_interrupt(int irq, void *dev_id)
330 330
331 dmas = readl(&lp->rx_dma_regs->dmas); 331 dmas = readl(&lp->rx_dma_regs->dmas);
332 if (dmas & (DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR)) { 332 if (dmas & (DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR)) {
333 netif_rx_schedule(&lp->napi);
334
335 dmasm = readl(&lp->rx_dma_regs->dmasm); 333 dmasm = readl(&lp->rx_dma_regs->dmasm);
336 writel(dmasm | (DMA_STAT_DONE | 334 writel(dmasm | (DMA_STAT_DONE |
337 DMA_STAT_HALT | DMA_STAT_ERR), 335 DMA_STAT_HALT | DMA_STAT_ERR),
338 &lp->rx_dma_regs->dmasm); 336 &lp->rx_dma_regs->dmasm);
339 337
338 netif_rx_schedule(&lp->napi);
339
340 if (dmas & DMA_STAT_ERR) 340 if (dmas & DMA_STAT_ERR)
341 printk(KERN_ERR DRV_NAME "%s: DMA error\n", dev->name); 341 printk(KERN_ERR DRV_NAME "%s: DMA error\n", dev->name);
342 342
@@ -623,12 +623,12 @@ korina_tx_dma_interrupt(int irq, void *dev_id)
623 dmas = readl(&lp->tx_dma_regs->dmas); 623 dmas = readl(&lp->tx_dma_regs->dmas);
624 624
625 if (dmas & (DMA_STAT_FINI | DMA_STAT_ERR)) { 625 if (dmas & (DMA_STAT_FINI | DMA_STAT_ERR)) {
626 korina_tx(dev);
627
628 dmasm = readl(&lp->tx_dma_regs->dmasm); 626 dmasm = readl(&lp->tx_dma_regs->dmasm);
629 writel(dmasm | (DMA_STAT_FINI | DMA_STAT_ERR), 627 writel(dmasm | (DMA_STAT_FINI | DMA_STAT_ERR),
630 &lp->tx_dma_regs->dmasm); 628 &lp->tx_dma_regs->dmasm);
631 629
630 korina_tx(dev);
631
632 if (lp->tx_chain_status == desc_filled && 632 if (lp->tx_chain_status == desc_filled &&
633 (readl(&(lp->tx_dma_regs->dmandptr)) == 0)) { 633 (readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
634 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), 634 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]),