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authorMichael Buesch <mb@bu3sch.de>2008-01-09 10:13:56 -0500
committerDavid S. Miller <davem@davemloft.net>2008-01-28 18:09:31 -0500
commit424047e6c684bef2872bd7af7d0e3961c6503981 (patch)
tree9607f4bd1647bd7b453a117fb6a37eebae8634ab
parent9081728b5f08f8137973c70e172c47ccb0dd33c9 (diff)
b43: Add N-PHY register definitions
This patch adds all register definitions for the N-PHY. This adds two new files: nphy.h and nphy.c No functional changes to existing code. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat
-rw-r--r--drivers/net/wireless/b43/Makefile1
-rw-r--r--drivers/net/wireless/b43/nphy.c34
-rw-r--r--drivers/net/wireless/b43/nphy.h706
-rw-r--r--drivers/net/wireless/b43/phy.c24
-rw-r--r--drivers/net/wireless/b43/phy.h7
5 files changed, 760 insertions, 12 deletions
diff --git a/drivers/net/wireless/b43/Makefile b/drivers/net/wireless/b43/Makefile
index 1e11ca8022a9..2002b8e7feb0 100644
--- a/drivers/net/wireless/b43/Makefile
+++ b/drivers/net/wireless/b43/Makefile
@@ -1,6 +1,7 @@
1b43-y += main.o 1b43-y += main.o
2b43-y += tables.o 2b43-y += tables.o
3b43-y += phy.o 3b43-y += phy.o
4b43-y += nphy.o
4b43-y += sysfs.o 5b43-y += sysfs.o
5b43-y += xmit.o 6b43-y += xmit.o
6b43-y += lo.o 7b43-y += lo.o
diff --git a/drivers/net/wireless/b43/nphy.c b/drivers/net/wireless/b43/nphy.c
new file mode 100644
index 000000000000..6d92545b1fae
--- /dev/null
+++ b/drivers/net/wireless/b43/nphy.c
@@ -0,0 +1,34 @@
1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
25#include "b43.h"
26#include "nphy.h"
27
28
29int b43_phy_initn(struct b43_wldev *dev)
30{
31 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
32
33 return -EOPNOTSUPP;
34}
diff --git a/drivers/net/wireless/b43/nphy.h b/drivers/net/wireless/b43/nphy.h
new file mode 100644
index 000000000000..11be7ff0ce0b
--- /dev/null
+++ b/drivers/net/wireless/b43/nphy.h
@@ -0,0 +1,706 @@
1#ifndef B43_NPHY_H_
2#define B43_NPHY_H_
3
4#include "phy.h"
5
6
7/* N-PHY registers. */
8
9#define B43_NPHY_BBCFG B43_PHY_N(0x001) /* BB config */
10#define B43_NPHY_BBCFG_RSTCCA 0x4000 /* Reset CCA */
11#define B43_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */
12#define B43_NPHY_CHANNEL B43_PHY_N(0x005) /* Channel */
13#define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */
14#define B43_NPHY_BANDCTL B43_PHY_N(0x009) /* Band control */
15#define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
16#define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
17#define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
18#define B43_NPHY_BIST_STAT0 B43_PHY_N(0x00E) /* Built-in self test status 0 */
19#define B43_NPHY_BIST_STAT1 B43_PHY_N(0x00F) /* Built-in self test status 1 */
20
21#define B43_NPHY_C1_DESPWR B43_PHY_N(0x018) /* Core 1 desired power */
22#define B43_NPHY_C1_CCK_DESPWR B43_PHY_N(0x019) /* Core 1 CCK desired power */
23#define B43_NPHY_C1_BCLIPBKOFF B43_PHY_N(0x01A) /* Core 1 barely clip backoff */
24#define B43_NPHY_C1_CCK_BCLIPBKOFF B43_PHY_N(0x01B) /* Core 1 CCK barely clip backoff */
25#define B43_NPHY_C1_CGAINI B43_PHY_N(0x01C) /* Core 1 compute gain info */
26#define B43_NPHY_C1_CGAINI_GAINBKOFF 0x001F /* Gain backoff */
27#define B43_NPHY_C1_CGAINI_CLIPGBKOFF 0x03E0 /* Clip gain backoff */
28#define B43_NPHY_C1_CGAINI_GAINSTEP 0x1C00 /* Gain step */
29#define B43_NPHY_C1_CGAINI_CL2DETECT 0x2000 /* Clip 2 detect mask */
30#define B43_NPHY_C1_CCK_CGAINI B43_PHY_N(0x01D) /* Core 1 CCK compute gain info */
31#define B43_NPHY_C1_CCK_CGAINI_GAINBKOFF 0x001F /* Gain backoff */
32#define B43_NPHY_C1_CCK_CGAINI_CLIPGBKOFF 0x01E0 /* CCK barely clip gain backoff */
33#define B43_NPHY_C1_MINMAX_GAIN B43_PHY_N(0x01E) /* Core 1 min/max gain */
34#define B43_NPHY_C1_MINGAIN 0x00FF /* Minimum gain */
35#define B43_NPHY_C1_MINGAIN_SHIFT 0
36#define B43_NPHY_C1_MAXGAIN 0xFF00 /* Maximum gain */
37#define B43_NPHY_C1_MAXGAIN_SHIFT 8
38#define B43_NPHY_C1_CCK_MINMAX_GAIN B43_PHY_N(0x01F) /* Core 1 CCK min/max gain */
39#define B43_NPHY_C1_CCK_MINGAIN 0x00FF /* Minimum gain */
40#define B43_NPHY_C1_CCK_MINGAIN_SHIFT 0
41#define B43_NPHY_C1_CCK_MAXGAIN 0xFF00 /* Maximum gain */
42#define B43_NPHY_C1_CCK_MAXGAIN_SHIFT 8
43#define B43_NPHY_C1_INITGAIN B43_PHY_N(0x020) /* Core 1 initial gain code */
44#define B43_NPHY_C1_INITGAIN_EXTLNA 0x0001 /* External LNA index */
45#define B43_NPHY_C1_INITGAIN_LNA 0x0006 /* LNA index */
46#define B43_NPHY_C1_INITGAIN_LNAIDX_SHIFT 1
47#define B43_NPHY_C1_INITGAIN_HPVGA1 0x0078 /* HPVGA1 index */
48#define B43_NPHY_C1_INITGAIN_HPVGA1_SHIFT 3
49#define B43_NPHY_C1_INITGAIN_HPVGA2 0x0F80 /* HPVGA2 index */
50#define B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT 7
51#define B43_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */
52#define B43_NPHY_C1_INITGAIN_TRTX 0x2000 /* TR TX index */
53#define B43_NPHY_C1_CLIP1_HIGAIN B43_PHY_N(0x021) /* Core 1 clip1 high gain code */
54#define B43_NPHY_C1_CLIP1_MEDGAIN B43_PHY_N(0x022) /* Core 1 clip1 medium gain code */
55#define B43_NPHY_C1_CLIP1_LOGAIN B43_PHY_N(0x023) /* Core 1 clip1 low gain code */
56#define B43_NPHY_C1_CLIP2_GAIN B43_PHY_N(0x024) /* Core 1 clip2 gain code */
57#define B43_NPHY_C1_FILTERGAIN B43_PHY_N(0x025) /* Core 1 filter gain */
58#define B43_NPHY_C1_LPF_QHPF_BW B43_PHY_N(0x026) /* Core 1 LPF Q HP F bandwidth */
59#define B43_NPHY_C1_CLIPWBTHRES B43_PHY_N(0x027) /* Core 1 clip wideband threshold */
60#define B43_NPHY_C1_CLIPWBTHRES_CLIP2 0x003F /* Clip 2 */
61#define B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT 0
62#define B43_NPHY_C1_CLIPWBTHRES_CLIP1 0x0FC0 /* Clip 1 */
63#define B43_NPHY_C1_CLIPWBTHRES_CLIP1_SHIFT 6
64#define B43_NPHY_C1_W1THRES B43_PHY_N(0x028) /* Core 1 W1 threshold */
65#define B43_NPHY_C1_EDTHRES B43_PHY_N(0x029) /* Core 1 ED threshold */
66#define B43_NPHY_C1_SMSIGTHRES B43_PHY_N(0x02A) /* Core 1 small sig threshold */
67#define B43_NPHY_C1_NBCLIPTHRES B43_PHY_N(0x02B) /* Core 1 NB clip threshold */
68#define B43_NPHY_C1_CLIP1THRES B43_PHY_N(0x02C) /* Core 1 clip1 threshold */
69#define B43_NPHY_C1_CLIP2THRES B43_PHY_N(0x02D) /* Core 1 clip2 threshold */
70
71#define B43_NPHY_C2_DESPWR B43_PHY_N(0x018 + 22) /* Core 2 desired power */
72#define B43_NPHY_C2_CCK_DESPWR B43_PHY_N(0x019 + 22) /* Core 2 CCK desired power */
73#define B43_NPHY_C2_BCLIPBKOFF B43_PHY_N(0x01A + 22) /* Core 2 barely clip backoff */
74#define B43_NPHY_C2_CCK_BCLIPBKOFF B43_PHY_N(0x01B + 22) /* Core 2 CCK barely clip backoff */
75#define B43_NPHY_C2_CGAINI B43_PHY_N(0x01C + 22) /* Core 2 compute gain info */
76#define B43_NPHY_C2_CGAINI_GAINBKOFF 0x001F /* Gain backoff */
77#define B43_NPHY_C2_CGAINI_CLIPGBKOFF 0x03E0 /* Clip gain backoff */
78#define B43_NPHY_C2_CGAINI_GAINSTEP 0x1C00 /* Gain step */
79#define B43_NPHY_C2_CGAINI_CL2DETECT 0x2000 /* Clip 2 detect mask */
80#define B43_NPHY_C2_CCK_CGAINI B43_PHY_N(0x01D + 22) /* Core 2 CCK compute gain info */
81#define B43_NPHY_C2_CCK_CGAINI_GAINBKOFF 0x001F /* Gain backoff */
82#define B43_NPHY_C2_CCK_CGAINI_CLIPGBKOFF 0x01E0 /* CCK barely clip gain backoff */
83#define B43_NPHY_C2_MINMAX_GAIN B43_PHY_N(0x01E + 22) /* Core 2 min/max gain */
84#define B43_NPHY_C2_MINGAIN 0x00FF /* Minimum gain */
85#define B43_NPHY_C2_MINGAIN_SHIFT 0
86#define B43_NPHY_C2_MAXGAIN 0xFF00 /* Maximum gain */
87#define B43_NPHY_C2_MAXGAIN_SHIFT 8
88#define B43_NPHY_C2_CCK_MINMAX_GAIN B43_PHY_N(0x01F + 22) /* Core 2 CCK min/max gain */
89#define B43_NPHY_C2_CCK_MINGAIN 0x00FF /* Minimum gain */
90#define B43_NPHY_C2_CCK_MINGAIN_SHIFT 0
91#define B43_NPHY_C2_CCK_MAXGAIN 0xFF00 /* Maximum gain */
92#define B43_NPHY_C2_CCK_MAXGAIN_SHIFT 8
93#define B43_NPHY_C2_INITGAIN B43_PHY_N(0x020 + 22) /* Core 2 initial gain code */
94#define B43_NPHY_C2_INITGAIN_EXTLNA 0x0001 /* External LNA index */
95#define B43_NPHY_C2_INITGAIN_LNA 0x0006 /* LNA index */
96#define B43_NPHY_C2_INITGAIN_LNAIDX_SHIFT 1
97#define B43_NPHY_C2_INITGAIN_HPVGA1 0x0078 /* HPVGA1 index */
98#define B43_NPHY_C2_INITGAIN_HPVGA1_SHIFT 3
99#define B43_NPHY_C2_INITGAIN_HPVGA2 0x0F80 /* HPVGA2 index */
100#define B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT 7
101#define B43_NPHY_C2_INITGAIN_TRRX 0x1000 /* TR RX index */
102#define B43_NPHY_C2_INITGAIN_TRTX 0x2000 /* TR TX index */
103#define B43_NPHY_C2_CLIP1_HIGAIN B43_PHY_N(0x021 + 22) /* Core 2 clip1 high gain code */
104#define B43_NPHY_C2_CLIP1_MEDGAIN B43_PHY_N(0x022 + 22) /* Core 2 clip1 medium gain code */
105#define B43_NPHY_C2_CLIP1_LOGAIN B43_PHY_N(0x023 + 22) /* Core 2 clip1 low gain code */
106#define B43_NPHY_C2_CLIP2_GAIN B43_PHY_N(0x024 + 22) /* Core 2 clip2 gain code */
107#define B43_NPHY_C2_FILTERGAIN B43_PHY_N(0x025 + 22) /* Core 2 filter gain */
108#define B43_NPHY_C2_LPF_QHPF_BW B43_PHY_N(0x026 + 22) /* Core 2 LPF Q HP F bandwidth */
109#define B43_NPHY_C2_CLIPWBTHRES B43_PHY_N(0x027 + 22) /* Core 2 clip wideband threshold */
110#define B43_NPHY_C2_CLIPWBTHRES_CLIP2 0x003F /* Clip 2 */
111#define B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT 0
112#define B43_NPHY_C2_CLIPWBTHRES_CLIP1 0x0FC0 /* Clip 1 */
113#define B43_NPHY_C2_CLIPWBTHRES_CLIP1_SHIFT 6
114#define B43_NPHY_C2_W1THRES B43_PHY_N(0x028 + 22) /* Core 2 W1 threshold */
115#define B43_NPHY_C2_EDTHRES B43_PHY_N(0x029 + 22) /* Core 2 ED threshold */
116#define B43_NPHY_C2_SMSIGTHRES B43_PHY_N(0x02A + 22) /* Core 2 small sig threshold */
117#define B43_NPHY_C2_NBCLIPTHRES B43_PHY_N(0x02B + 22) /* Core 2 NB clip threshold */
118#define B43_NPHY_C2_CLIP1THRES B43_PHY_N(0x02C + 22) /* Core 2 clip1 threshold */
119#define B43_NPHY_C2_CLIP2THRES B43_PHY_N(0x02D + 22) /* Core 2 clip2 threshold */
120
121#define B43_NPHY_CRS_THRES1 B43_PHY_N(0x044) /* CRS threshold 1 */
122#define B43_NPHY_CRS_THRES2 B43_PHY_N(0x045) /* CRS threshold 2 */
123#define B43_NPHY_CRS_THRES3 B43_PHY_N(0x046) /* CRS threshold 3 */
124#define B43_NPHY_CRSCTL B43_PHY_N(0x047) /* CRS control */
125#define B43_NPHY_DCFADDR B43_PHY_N(0x048) /* DC filter address */
126#define B43_NPHY_RXF20_NUM0 B43_PHY_N(0x049) /* RX filter 20 numerator 0 */
127#define B43_NPHY_RXF20_NUM1 B43_PHY_N(0x04A) /* RX filter 20 numerator 1 */
128#define B43_NPHY_RXF20_NUM2 B43_PHY_N(0x04B) /* RX filter 20 numerator 2 */
129#define B43_NPHY_RXF20_DENOM0 B43_PHY_N(0x04C) /* RX filter 20 denominator 0 */
130#define B43_NPHY_RXF20_DENOM1 B43_PHY_N(0x04D) /* RX filter 20 denominator 1 */
131#define B43_NPHY_RXF20_NUM10 B43_PHY_N(0x04E) /* RX filter 20 numerator 10 */
132#define B43_NPHY_RXF20_NUM11 B43_PHY_N(0x04F) /* RX filter 20 numerator 11 */
133#define B43_NPHY_RXF20_NUM12 B43_PHY_N(0x050) /* RX filter 20 numerator 12 */
134#define B43_NPHY_RXF20_DENOM10 B43_PHY_N(0x051) /* RX filter 20 denominator 10 */
135#define B43_NPHY_RXF20_DENOM11 B43_PHY_N(0x052) /* RX filter 20 denominator 11 */
136#define B43_NPHY_RXF40_NUM0 B43_PHY_N(0x053) /* RX filter 40 numerator 0 */
137#define B43_NPHY_RXF40_NUM1 B43_PHY_N(0x054) /* RX filter 40 numerator 1 */
138#define B43_NPHY_RXF40_NUM2 B43_PHY_N(0x055) /* RX filter 40 numerator 2 */
139#define B43_NPHY_RXF40_DENOM0 B43_PHY_N(0x056) /* RX filter 40 denominator 0 */
140#define B43_NPHY_RXF40_DENOM1 B43_PHY_N(0x057) /* RX filter 40 denominator 1 */
141#define B43_NPHY_RXF40_NUM10 B43_PHY_N(0x058) /* RX filter 40 numerator 10 */
142#define B43_NPHY_RXF40_NUM11 B43_PHY_N(0x059) /* RX filter 40 numerator 11 */
143#define B43_NPHY_RXF40_NUM12 B43_PHY_N(0x05A) /* RX filter 40 numerator 12 */
144#define B43_NPHY_RXF40_DENOM10 B43_PHY_N(0x05B) /* RX filter 40 denominator 10 */
145#define B43_NPHY_RXF40_DENOM11 B43_PHY_N(0x05C) /* RX filter 40 denominator 11 */
146#define B43_NPHY_PPROC_RSTLEN B43_PHY_N(0x060) /* Packet processing reset length */
147#define B43_NPHY_INITCARR_DLEN B43_PHY_N(0x061) /* Initial carrier detection length */
148#define B43_NPHY_CLIP1CARR_DLEN B43_PHY_N(0x062) /* Clip1 carrier detection length */
149#define B43_NPHY_CLIP2CARR_DLEN B43_PHY_N(0x063) /* Clip2 carrier detection length */
150#define B43_NPHY_INITGAIN_SLEN B43_PHY_N(0x064) /* Initial gain settle length */
151#define B43_NPHY_CLIP1GAIN_SLEN B43_PHY_N(0x065) /* Clip1 gain settle length */
152#define B43_NPHY_CLIP2GAIN_SLEN B43_PHY_N(0x066) /* Clip2 gain settle length */
153#define B43_NPHY_PACKGAIN_SLEN B43_PHY_N(0x067) /* Packet gain settle length */
154#define B43_NPHY_CARRSRC_TLEN B43_PHY_N(0x068) /* Carrier search timeout length */
155#define B43_NPHY_TISRC_TLEN B43_PHY_N(0x069) /* Timing search timeout length */
156#define B43_NPHY_ENDROP_TLEN B43_PHY_N(0x06A) /* Energy drop timeout length */
157#define B43_NPHY_CLIP1_NBDWELL_LEN B43_PHY_N(0x06B) /* Clip1 NB dwell length */
158#define B43_NPHY_CLIP2_NBDWELL_LEN B43_PHY_N(0x06C) /* Clip2 NB dwell length */
159#define B43_NPHY_W1CLIP1_DWELL_LEN B43_PHY_N(0x06D) /* W1 clip1 dwell length */
160#define B43_NPHY_W1CLIP2_DWELL_LEN B43_PHY_N(0x06E) /* W1 clip2 dwell length */
161#define B43_NPHY_W2CLIP1_DWELL_LEN B43_PHY_N(0x06F) /* W2 clip1 dwell length */
162#define B43_NPHY_PLOAD_CSENSE_EXTLEN B43_PHY_N(0x070) /* Payload carrier sense extension length */
163#define B43_NPHY_EDROP_CSENSE_EXTLEN B43_PHY_N(0x071) /* Energy drop carrier sense extension length */
164#define B43_NPHY_TABLE_ADDR B43_PHY_N(0x072) /* Table address */
165#define B43_NPHY_TABLE_DATALO B43_PHY_N(0x073) /* Table data low */
166#define B43_NPHY_TABLE_DATAHI B43_PHY_N(0x074) /* Table data high */
167#define B43_NPHY_WWISE_LENIDX B43_PHY_N(0x075) /* WWiSE length index */
168#define B43_NPHY_TGNSYNC_LENIDX B43_PHY_N(0x076) /* TGNsync length index */
169#define B43_NPHY_TXMACIF_HOLDOFF B43_PHY_N(0x077) /* TX MAC IF Hold off */
170#define B43_NPHY_RFCTL_CMD B43_PHY_N(0x078) /* RF control (command) */
171#define B43_NPHY_RFCTL_CMD_START 0x0001 /* Start sequence */
172#define B43_NPHY_RFCTL_CMD_RXTX 0x0002 /* RX/TX */
173#define B43_NPHY_RFCTL_CMD_CORESEL 0x0038 /* Core select */
174#define B43_NPHY_RFCTL_CMD_CORESEL_SHIFT 3
175#define B43_NPHY_RFCTL_CMD_PORFORCE 0x0040 /* POR force */
176#define B43_NPHY_RFCTL_CMD_OEPORFORCE 0x0080 /* OE POR force */
177#define B43_NPHY_RFCTL_CMD_RXEN 0x0100 /* RX enable */
178#define B43_NPHY_RFCTL_CMD_TXEN 0x0200 /* TX enable */
179#define B43_NPHY_RFCTL_CMD_CHIP0PU 0x0400 /* Chip0 PU */
180#define B43_NPHY_RFCTL_CMD_SEQENCORE 0xF000 /* Seq en core */
181#define B43_NPHY_RFCTL_CMD_SEQENCORE_SHIFT 12
182#define B43_NPHY_RFCTL_RSSIO1 B43_PHY_N(0x07A) /* RF control (RSSI others 1) */
183#define B43_NPHY_RFCTL_RSSIO1_RXPD 0x0001 /* RX PD */
184#define B43_NPHY_RFCTL_RSSIO1_TXPD 0x0002 /* TX PD */
185#define B43_NPHY_RFCTL_RSSIO1_PAPD 0x0004 /* PA PD */
186#define B43_NPHY_RFCTL_RSSIO1_RSSICTL 0x0030 /* RSSI control */
187#define B43_NPHY_RFCTL_RSSIO1_LPFBW 0x00C0 /* LPF bandwidth */
188#define B43_NPHY_RFCTL_RSSIO1_HPFBWHI 0x0100 /* HPF bandwidth high */
189#define B43_NPHY_RFCTL_RSSIO1_HIQDISCO 0x0200 /* HIQ dis core */
190#define B43_NPHY_RFCTL_RXG1 B43_PHY_N(0x07B) /* RF control (RX gain 1) */
191#define B43_NPHY_RFCTL_TXG1 B43_PHY_N(0x07C) /* RF control (TX gain 1) */
192#define B43_NPHY_RFCTL_RSSIO2 B43_PHY_N(0x07D) /* RF control (RSSI others 2) */
193#define B43_NPHY_RFCTL_RSSIO2_RXPD 0x0001 /* RX PD */
194#define B43_NPHY_RFCTL_RSSIO2_TXPD 0x0002 /* TX PD */
195#define B43_NPHY_RFCTL_RSSIO2_PAPD 0x0004 /* PA PD */
196#define B43_NPHY_RFCTL_RSSIO2_RSSICTL 0x0030 /* RSSI control */
197#define B43_NPHY_RFCTL_RSSIO2_LPFBW 0x00C0 /* LPF bandwidth */
198#define B43_NPHY_RFCTL_RSSIO2_HPFBWHI 0x0100 /* HPF bandwidth high */
199#define B43_NPHY_RFCTL_RSSIO2_HIQDISCO 0x0200 /* HIQ dis core */
200#define B43_NPHY_RFCTL_RXG2 B43_PHY_N(0x07E) /* RF control (RX gain 2) */
201#define B43_NPHY_RFCTL_TXG2 B43_PHY_N(0x07F) /* RF control (TX gain 2) */
202#define B43_NPHY_RFCTL_RSSIO3 B43_PHY_N(0x080) /* RF control (RSSI others 3) */
203#define B43_NPHY_RFCTL_RSSIO3_RXPD 0x0001 /* RX PD */
204#define B43_NPHY_RFCTL_RSSIO3_TXPD 0x0002 /* TX PD */
205#define B43_NPHY_RFCTL_RSSIO3_PAPD 0x0004 /* PA PD */
206#define B43_NPHY_RFCTL_RSSIO3_RSSICTL 0x0030 /* RSSI control */
207#define B43_NPHY_RFCTL_RSSIO3_LPFBW 0x00C0 /* LPF bandwidth */
208#define B43_NPHY_RFCTL_RSSIO3_HPFBWHI 0x0100 /* HPF bandwidth high */
209#define B43_NPHY_RFCTL_RSSIO3_HIQDISCO 0x0200 /* HIQ dis core */
210#define B43_NPHY_RFCTL_RXG3 B43_PHY_N(0x081) /* RF control (RX gain 3) */
211#define B43_NPHY_RFCTL_TXG3 B43_PHY_N(0x082) /* RF control (TX gain 3) */
212#define B43_NPHY_RFCTL_RSSIO4 B43_PHY_N(0x083) /* RF control (RSSI others 4) */
213#define B43_NPHY_RFCTL_RSSIO4_RXPD 0x0001 /* RX PD */
214#define B43_NPHY_RFCTL_RSSIO4_TXPD 0x0002 /* TX PD */
215#define B43_NPHY_RFCTL_RSSIO4_PAPD 0x0004 /* PA PD */
216#define B43_NPHY_RFCTL_RSSIO4_RSSICTL 0x0030 /* RSSI control */
217#define B43_NPHY_RFCTL_RSSIO4_LPFBW 0x00C0 /* LPF bandwidth */
218#define B43_NPHY_RFCTL_RSSIO4_HPFBWHI 0x0100 /* HPF bandwidth high */
219#define B43_NPHY_RFCTL_RSSIO4_HIQDISCO 0x0200 /* HIQ dis core */
220#define B43_NPHY_RFCTL_RXG4 B43_PHY_N(0x084) /* RF control (RX gain 4) */
221#define B43_NPHY_RFCTL_TXG4 B43_PHY_N(0x085) /* RF control (TX gain 4) */
222#define B43_NPHY_C1_TXIQ_COMP_OFF B43_PHY_N(0x087) /* Core 1 TX I/Q comp offset */
223#define B43_NPHY_C2_TXIQ_COMP_OFF B43_PHY_N(0x088) /* Core 2 TX I/Q comp offset */
224#define B43_NPHY_C1_TXCTL B43_PHY_N(0x08B) /* Core 1 TX control */
225#define B43_NPHY_C2_TXCTL B43_PHY_N(0x08C) /* Core 2 TX control */
226#define B43_NPHY_SCRAM_SIGCTL B43_PHY_N(0x090) /* Scran signal control */
227#define B43_NPHY_SCRAM_SIGCTL_INITST 0x007F /* Initial state value */
228#define B43_NPHY_SCRAM_SIGCTL_INITST_SHIFT 0
229#define B43_NPHY_SCRAM_SIGCTL_SCM 0x0080 /* Scram control mode */
230#define B43_NPHY_SCRAM_SIGCTL_SICE 0x0100 /* Scram index control enable */
231#define B43_NPHY_SCRAM_SIGCTL_START 0xFE00 /* Scram start bit */
232#define B43_NPHY_SCRAM_SIGCTL_START_SHIFT 9
233#define B43_NPHY_RFCTL_INTC1 B43_PHY_N(0x091) /* RF control (intc 1) */
234#define B43_NPHY_RFCTL_INTC2 B43_PHY_N(0x092) /* RF control (intc 2) */
235#define B43_NPHY_RFCTL_INTC3 B43_PHY_N(0x093) /* RF control (intc 3) */
236#define B43_NPHY_RFCTL_INTC4 B43_PHY_N(0x094) /* RF control (intc 4) */
237#define B43_NPHY_NRDTO_WWISE B43_PHY_N(0x095) /* # datatones WWiSE */
238#define B43_NPHY_NRDTO_TGNSYNC B43_PHY_N(0x096) /* # datatones TGNsync */
239#define B43_NPHY_SIGFMOD_WWISE B43_PHY_N(0x097) /* Signal field mod WWiSE */
240#define B43_NPHY_LEG_SIGFMOD_11N B43_PHY_N(0x098) /* Legacy signal field mod 11n */
241#define B43_NPHY_HT_SIGFMOD_11N B43_PHY_N(0x099) /* HT signal field mod 11n */
242#define B43_NPHY_C1_RXIQ_COMPA0 B43_PHY_N(0x09A) /* Core 1 RX I/Q comp A0 */
243#define B43_NPHY_C1_RXIQ_COMPB0 B43_PHY_N(0x09B) /* Core 1 RX I/Q comp B0 */
244#define B43_NPHY_C2_RXIQ_COMPA1 B43_PHY_N(0x09C) /* Core 2 RX I/Q comp A1 */
245#define B43_NPHY_C2_RXIQ_COMPB1 B43_PHY_N(0x09D) /* Core 2 RX I/Q comp B1 */
246#define B43_NPHY_RXCTL B43_PHY_N(0x0A0) /* RX control */
247#define B43_NPHY_RXCTL_BSELU20 0x0010 /* Band select upper 20 */
248#define B43_NPHY_RXCTL_RIFSEN 0x0080 /* RIFS enable */
249#define B43_NPHY_RFSEQMODE B43_PHY_N(0x0A1) /* RF seq mode */
250#define B43_NPHY_RFSEQMODE_CAOVER 0x0001 /* Core active override */
251#define B43_NPHY_RFSEQMODE_TROVER 0x0002 /* Trigger override */
252#define B43_NPHY_RFSEQCA B43_PHY_N(0x0A2) /* RF seq core active */
253#define B43_NPHY_RFSEQCA_TXEN 0x000F /* TX enable */
254#define B43_NPHY_RFSEQCA_TXEN_SHIFT 0
255#define B43_NPHY_RFSEQCA_RXEN 0x00F0 /* RX enable */
256#define B43_NPHY_RFSEQCA_RXEN_SHIFT 4
257#define B43_NPHY_RFSEQCA_TXDIS 0x0F00 /* TX disable */
258#define B43_NPHY_RFSEQCA_TXDIS_SHIFT 8
259#define B43_NPHY_RFSEQCA_RXDIS 0xF000 /* RX disable */
260#define B43_NPHY_RFSEQCA_RXDIS_SHIFT 12
261#define B43_NPHY_RFSEQTR B43_PHY_N(0x0A3) /* RF seq trigger */
262#define B43_NPHY_RFSEQTR_RX2TX 0x0001 /* RX2TX */
263#define B43_NPHY_RFSEQTR_TX2RX 0x0002 /* TX2RX */
264#define B43_NPHY_RFSEQTR_UPGH 0x0004 /* Update gain H */
265#define B43_NPHY_RFSEQTR_UPGL 0x0008 /* Update gain L */
266#define B43_NPHY_RFSEQTR_UPGU 0x0010 /* Update gain U */
267#define B43_NPHY_RFSEQTR_RST2RX 0x0020 /* Reset to RX */
268#define B43_NPHY_RFSEQST B43_PHY_N(0x0A4) /* RF seq status. Values same as trigger. */
269#define B43_NPHY_AFECTL_OVER B43_PHY_N(0x0A5) /* AFE control override */
270#define B43_NPHY_AFECTL_C1 B43_PHY_N(0x0A6) /* AFE control core 1 */
271#define B43_NPHY_AFECTL_C2 B43_PHY_N(0x0A7) /* AFE control core 2 */
272#define B43_NPHY_AFECTL_C3 B43_PHY_N(0x0A8) /* AFE control core 3 */
273#define B43_NPHY_AFECTL_C4 B43_PHY_N(0x0A9) /* AFE control core 4 */
274#define B43_NPHY_AFECTL_DACGAIN1 B43_PHY_N(0x0AA) /* AFE control DAC gain 1 */
275#define B43_NPHY_AFECTL_DACGAIN2 B43_PHY_N(0x0AB) /* AFE control DAC gain 2 */
276#define B43_NPHY_AFECTL_DACGAIN3 B43_PHY_N(0x0AC) /* AFE control DAC gain 3 */
277#define B43_NPHY_AFECTL_DACGAIN4 B43_PHY_N(0x0AD) /* AFE control DAC gain 4 */
278#define B43_NPHY_STR_ADDR1 B43_PHY_N(0x0AE) /* STR address 1 */
279#define B43_NPHY_STR_ADDR2 B43_PHY_N(0x0AF) /* STR address 2 */
280#define B43_NPHY_CLASSCTL B43_PHY_N(0x0B0) /* Classifier control */
281#define B43_NPHY_CLASSCTL_CCKEN 0x0001 /* CCK enable */
282#define B43_NPHY_CLASSCTL_OFDMEN 0x0002 /* OFDM enable */
283#define B43_NPHY_CLASSCTL_WAITEDEN 0x0004 /* Waited enable */
284#define B43_NPHY_IQFLIP B43_PHY_N(0x0B1) /* I/Q flip */
285#define B43_NPHY_IQFLIP_ADC1 0x0001 /* ADC1 */
286#define B43_NPHY_IQFLIP_ADC2 0x0010 /* ADC2 */
287#define B43_NPHY_SISO_SNR_THRES B43_PHY_N(0x0B2) /* SISO SNR threshold */
288#define B43_NPHY_SIGMA_N_MULT B43_PHY_N(0x0B3) /* Sigma N multiplier */
289#define B43_NPHY_TXMACDELAY B43_PHY_N(0x0B4) /* TX MAC delay */
290#define B43_NPHY_TXFRAMEDELAY B43_PHY_N(0x0B5) /* TX frame delay */
291#define B43_NPHY_MLPARM B43_PHY_N(0x0B6) /* ML parameters */
292#define B43_NPHY_MLCTL B43_PHY_N(0x0B7) /* ML control */
293#define B43_NPHY_WWISE_20NCYCDAT B43_PHY_N(0x0B8) /* WWiSE 20 N cyc data */
294#define B43_NPHY_WWISE_40NCYCDAT B43_PHY_N(0x0B9) /* WWiSE 40 N cyc data */
295#define B43_NPHY_TGNSYNC_20NCYCDAT B43_PHY_N(0x0BA) /* TGNsync 20 N cyc data */
296#define B43_NPHY_TGNSYNC_40NCYCDAT B43_PHY_N(0x0BB) /* TGNsync 40 N cyc data */
297#define B43_NPHY_INITSWIZP B43_PHY_N(0x0BC) /* Initial swizzle pattern */
298#define B43_NPHY_TXTAILCNT B43_PHY_N(0x0BD) /* TX tail count value */
299#define B43_NPHY_BPHY_CTL1 B43_PHY_N(0x0BE) /* B PHY control 1 */
300#define B43_NPHY_BPHY_CTL2 B43_PHY_N(0x0BF) /* B PHY control 2 */
301#define B43_NPHY_BPHY_CTL2_LUT 0x001F /* LUT index */
302#define B43_NPHY_BPHY_CTL2_LUT_SHIFT 0
303#define B43_NPHY_BPHY_CTL2_MACDEL 0x7FE0 /* MAC delay */
304#define B43_NPHY_BPHY_CTL2_MACDEL_SHIFT 5
305#define B43_NPHY_IQLOCAL_CMD B43_PHY_N(0x0C0) /* I/Q LO cal command */
306#define B43_NPHY_IQLOCAL_CMD_EN 0x8000
307#define B43_NPHY_IQLOCAL_CMDNNUM B43_PHY_N(0x0C1) /* I/Q LO cal command N num */
308#define B43_NPHY_IQLOCAL_CMDGCTL B43_PHY_N(0x0C2) /* I/Q LO cal command G control */
309#define B43_NPHY_SAMP_CMD B43_PHY_N(0x0C3) /* Sample command */
310#define B43_NPHY_SAMP_CMD_STOP 0x0002 /* Stop */
311#define B43_NPHY_SAMP_LOOPCNT B43_PHY_N(0x0C4) /* Sample loop count */
312#define B43_NPHY_SAMP_WAITCNT B43_PHY_N(0x0C5) /* Sample wait count */
313#define B43_NPHY_SAMP_DEPCNT B43_PHY_N(0x0C6) /* Sample depth count */
314#define B43_NPHY_SAMP_STAT B43_PHY_N(0x0C7) /* Sample status */
315#define B43_NPHY_GPIO_LOOEN B43_PHY_N(0x0C8) /* GPIO low out enable */
316#define B43_NPHY_GPIO_HIOEN B43_PHY_N(0x0C9) /* GPIO high out enable */
317#define B43_NPHY_GPIO_SEL B43_PHY_N(0x0CA) /* GPIO select */
318#define B43_NPHY_GPIO_CLKCTL B43_PHY_N(0x0CB) /* GPIO clock control */
319#define B43_NPHY_TXF_20CO_AS0 B43_PHY_N(0x0CC) /* TX filter 20 coeff A stage 0 */
320#define B43_NPHY_TXF_20CO_AS1 B43_PHY_N(0x0CD) /* TX filter 20 coeff A stage 1 */
321#define B43_NPHY_TXF_20CO_AS2 B43_PHY_N(0x0CE) /* TX filter 20 coeff A stage 2 */
322#define B43_NPHY_TXF_20CO_B32S0 B43_PHY_N(0x0CF) /* TX filter 20 coeff B32 stage 0 */
323#define B43_NPHY_TXF_20CO_B1S0 B43_PHY_N(0x0D0) /* TX filter 20 coeff B1 stage 0 */
324#define B43_NPHY_TXF_20CO_B32S1 B43_PHY_N(0x0D1) /* TX filter 20 coeff B32 stage 1 */
325#define B43_NPHY_TXF_20CO_B1S1 B43_PHY_N(0x0D2) /* TX filter 20 coeff B1 stage 1 */
326#define B43_NPHY_TXF_20CO_B32S2 B43_PHY_N(0x0D3) /* TX filter 20 coeff B32 stage 2 */
327#define B43_NPHY_TXF_20CO_B1S2 B43_PHY_N(0x0D4) /* TX filter 20 coeff B1 stage 2 */
328#define B43_NPHY_SIGFLDTOL B43_PHY_N(0x0D5) /* Signal fld tolerance */
329#define B43_NPHY_TXSERFLD B43_PHY_N(0x0D6) /* TX service field */
330#define B43_NPHY_AFESEQ_RX2TX_PUD B43_PHY_N(0x0D7) /* AFE seq RX2TX power up/down delay */
331#define B43_NPHY_AFESEQ_TX2RX_PUD B43_PHY_N(0x0D8) /* AFE seq TX2RX power up/down delay */
332#define B43_NPHY_TGNSYNC_SCRAMI0 B43_PHY_N(0x0D9) /* TGNsync scram init 0 */
333#define B43_NPHY_TGNSYNC_SCRAMI1 B43_PHY_N(0x0DA) /* TGNsync scram init 1 */
334#define B43_NPHY_INITSWIZPATTLEG B43_PHY_N(0x0DB) /* Initial swizzle pattern leg */
335#define B43_NPHY_BPHY_CTL3 B43_PHY_N(0x0DC) /* B PHY control 3 */
336#define B43_NPHY_BPHY_CTL3_SCALE 0x00FF /* Scale */
337#define B43_NPHY_BPHY_CTL3_SCALE_SHIFT 0
338#define B43_NPHY_BPHY_CTL3_FSC 0xFF00 /* Frame start count value */
339#define B43_NPHY_BPHY_CTL3_FSC_SHIFT 8
340#define B43_NPHY_BPHY_CTL4 B43_PHY_N(0x0DD) /* B PHY control 4 */
341#define B43_NPHY_C1_TXBBMULT B43_PHY_N(0x0DE) /* Core 1 TX BB multiplier */
342#define B43_NPHY_C2_TXBBMULT B43_PHY_N(0x0DF) /* Core 2 TX BB multiplier */
343#define B43_NPHY_TXF_40CO_AS0 B43_PHY_N(0x0E1) /* TX filter 40 coeff A stage 0 */
344#define B43_NPHY_TXF_40CO_AS1 B43_PHY_N(0x0E2) /* TX filter 40 coeff A stage 1 */
345#define B43_NPHY_TXF_40CO_AS2 B43_PHY_N(0x0E3) /* TX filter 40 coeff A stage 2 */
346#define B43_NPHY_TXF_40CO_B32S0 B43_PHY_N(0x0E4) /* TX filter 40 coeff B32 stage 0 */
347#define B43_NPHY_TXF_40CO_B1S0 B43_PHY_N(0x0E5) /* TX filter 40 coeff B1 stage 0 */
348#define B43_NPHY_TXF_40CO_B32S1 B43_PHY_N(0x0E6) /* TX filter 40 coeff B32 stage 1 */
349#define B43_NPHY_TXF_40CO_B1S1 B43_PHY_N(0x0E7) /* TX filter 40 coeff B1 stage 1 */
350#define B43_NPHY_TXF_40CO_B32S2 B43_PHY_N(0x0E8) /* TX filter 40 coeff B32 stage 2 */
351#define B43_NPHY_TXF_40CO_B1S2 B43_PHY_N(0x0E9) /* TX filter 40 coeff B1 stage 2 */
352#define B43_NPHY_BIST_STAT2 B43_PHY_N(0x0EA) /* BIST status 2 */
353#define B43_NPHY_BIST_STAT3 B43_PHY_N(0x0EB) /* BIST status 3 */
354#define B43_NPHY_RFCTL_OVER B43_PHY_N(0x0EC) /* RF control override */
355#define B43_NPHY_MIMOCFG B43_PHY_N(0x0ED) /* MIMO config */
356#define B43_NPHY_MIMOCFG_GFMIX 0x0004 /* Greenfield or mixed mode */
357#define B43_NPHY_MIMOCFG_AUTO 0x0100 /* Greenfield/mixed mode auto */
358#define B43_NPHY_RADAR_BLNKCTL B43_PHY_N(0x0EE) /* Radar blank control */
359#define B43_NPHY_A0RADAR_FIFOCTL B43_PHY_N(0x0EF) /* Antenna 0 radar FIFO control */
360#define B43_NPHY_A1RADAR_FIFOCTL B43_PHY_N(0x0F0) /* Antenna 1 radar FIFO control */
361#define B43_NPHY_A0RADAR_FIFODAT B43_PHY_N(0x0F1) /* Antenna 0 radar FIFO data */
362#define B43_NPHY_A1RADAR_FIFODAT B43_PHY_N(0x0F2) /* Antenna 1 radar FIFO data */
363#define B43_NPHY_RADAR_THRES0 B43_PHY_N(0x0F3) /* Radar threshold 0 */
364#define B43_NPHY_RADAR_THRES1 B43_PHY_N(0x0F4) /* Radar threshold 1 */
365#define B43_NPHY_RADAR_THRES0R B43_PHY_N(0x0F5) /* Radar threshold 0R */
366#define B43_NPHY_RADAR_THRES1R B43_PHY_N(0x0F6) /* Radar threshold 1R */
367#define B43_NPHY_CSEN_20IN40_DLEN B43_PHY_N(0x0F7) /* Carrier sense 20 in 40 dwell length */
368#define B43_NPHY_RFCTL_LUT_TRSW_LO1 B43_PHY_N(0x0F8) /* RF control LUT TRSW lower 1 */
369#define B43_NPHY_RFCTL_LUT_TRSW_UP1 B43_PHY_N(0x0F9) /* RF control LUT TRSW upper 1 */
370#define B43_NPHY_RFCTL_LUT_TRSW_LO2 B43_PHY_N(0x0FA) /* RF control LUT TRSW lower 2 */
371#define B43_NPHY_RFCTL_LUT_TRSW_UP2 B43_PHY_N(0x0FB) /* RF control LUT TRSW upper 2 */
372#define B43_NPHY_RFCTL_LUT_TRSW_LO3 B43_PHY_N(0x0FC) /* RF control LUT TRSW lower 3 */
373#define B43_NPHY_RFCTL_LUT_TRSW_UP3 B43_PHY_N(0x0FD) /* RF control LUT TRSW upper 3 */
374#define B43_NPHY_RFCTL_LUT_TRSW_LO4 B43_PHY_N(0x0FE) /* RF control LUT TRSW lower 4 */
375#define B43_NPHY_RFCTL_LUT_TRSW_UP4 B43_PHY_N(0x0FF) /* RF control LUT TRSW upper 4 */
376#define B43_NPHY_RFCTL_LUT_LNAPA1 B43_PHY_N(0x100) /* RF control LUT LNA PA 1 */
377#define B43_NPHY_RFCTL_LUT_LNAPA2 B43_PHY_N(0x101) /* RF control LUT LNA PA 2 */
378#define B43_NPHY_RFCTL_LUT_LNAPA3 B43_PHY_N(0x102) /* RF control LUT LNA PA 3 */
379#define B43_NPHY_RFCTL_LUT_LNAPA4 B43_PHY_N(0x103) /* RF control LUT LNA PA 4 */
380#define B43_NPHY_TGNSYNC_CRCM0 B43_PHY_N(0x104) /* TGNsync CRC mask 0 */
381#define B43_NPHY_TGNSYNC_CRCM1 B43_PHY_N(0x105) /* TGNsync CRC mask 1 */
382#define B43_NPHY_TGNSYNC_CRCM2 B43_PHY_N(0x106) /* TGNsync CRC mask 2 */
383#define B43_NPHY_TGNSYNC_CRCM3 B43_PHY_N(0x107) /* TGNsync CRC mask 3 */
384#define B43_NPHY_TGNSYNC_CRCM4 B43_PHY_N(0x108) /* TGNsync CRC mask 4 */
385#define B43_NPHY_CRCPOLY B43_PHY_N(0x109) /* CRC polynomial */
386#define B43_NPHY_SIGCNT B43_PHY_N(0x10A) /* # sig count */
387#define B43_NPHY_SIGSTARTBIT_CTL B43_PHY_N(0x10B) /* Sig start bit control */
388#define B43_NPHY_CRCPOLY_ORDER B43_PHY_N(0x10C) /* CRC polynomial order */
389#define B43_NPHY_RFCTL_CST0 B43_PHY_N(0x10D) /* RF control core swap table 0 */
390#define B43_NPHY_RFCTL_CST1 B43_PHY_N(0x10E) /* RF control core swap table 1 */
391#define B43_NPHY_RFCTL_CST2O B43_PHY_N(0x10F) /* RF control core swap table 2 + others */
392#define B43_NPHY_BPHY_CTL5 B43_PHY_N(0x111) /* B PHY control 5 */
393#define B43_NPHY_RFSEQ_LPFBW B43_PHY_N(0x112) /* RF seq LPF bandwidth */
394#define B43_NPHY_TSSIBIAS1 B43_PHY_N(0x114) /* TSSI bias val 1 */
395#define B43_NPHY_TSSIBIAS2 B43_PHY_N(0x115) /* TSSI bias val 2 */
396#define B43_NPHY_TSSIBIAS_BIAS 0x00FF /* Bias */
397#define B43_NPHY_TSSIBIAS_BIAS_SHIFT 0
398#define B43_NPHY_TSSIBIAS_VAL 0xFF00 /* Value */
399#define B43_NPHY_TSSIBIAS_VAL_SHIFT 8
400#define B43_NPHY_ESTPWR1 B43_PHY_N(0x118) /* Estimated power 1 */
401#define B43_NPHY_ESTPWR2 B43_PHY_N(0x119) /* Estimated power 2 */
402#define B43_NPHY_ESTPWR_PWR 0x00FF /* Estimated power */
403#define B43_NPHY_ESTPWR_PWR_SHIFT 0
404#define B43_NPHY_ESTPWR_VALID 0x0100 /* Estimated power valid */
405#define B43_NPHY_TSSI_MAXTXFDT B43_PHY_N(0x11C) /* TSSI max TX frame delay time */
406#define B43_NPHY_TSSI_MAXTXFDT_VAL 0x00FF /* max TX frame delay time */
407#define B43_NPHY_TSSI_MAXTXFDT_VAL_SHIFT 0
408#define B43_NPHY_TSSI_MAXTDT B43_PHY_N(0x11D) /* TSSI max TSSI delay time */
409#define B43_NPHY_TSSI_MAXTDT_VAL 0x00FF /* max TSSI delay time */
410#define B43_NPHY_TSSI_MAXTDT_VAL_SHIFT 0
411#define B43_NPHY_ITSSI1 B43_PHY_N(0x11E) /* TSSI idle 1 */
412#define B43_NPHY_ITSSI2 B43_PHY_N(0x11F) /* TSSI idle 2 */
413#define B43_NPHY_ITSSI_VAL 0x00FF /* Idle TSSI */
414#define B43_NPHY_ITSSI_VAL_SHIFT 0
415#define B43_NPHY_TSSIMODE B43_PHY_N(0x122) /* TSSI mode */
416#define B43_NPHY_TSSIMODE_EN 0x0001 /* TSSI enable */
417#define B43_NPHY_TSSIMODE_PDEN 0x0002 /* Power det enable */
418#define B43_NPHY_RXMACIFM B43_PHY_N(0x123) /* RX Macif mode */
419#define B43_NPHY_CRSIT_COCNT_LO B43_PHY_N(0x124) /* CRS idle time CRS-on count (low) */
420#define B43_NPHY_CRSIT_COCNT_HI B43_PHY_N(0x125) /* CRS idle time CRS-on count (high) */
421#define B43_NPHY_CRSIT_MTCNT_LO B43_PHY_N(0x126) /* CRS idle time measure time count (low) */
422#define B43_NPHY_CRSIT_MTCNT_HI B43_PHY_N(0x127) /* CRS idle time measure time count (high) */
423#define B43_NPHY_SAMTWC B43_PHY_N(0x128) /* Sample tail wait count */
424#define B43_NPHY_IQEST_CMD B43_PHY_N(0x129) /* I/Q estimate command */
425#define B43_NPHY_IQEST_CMD_START 0x0001 /* Start */
426#define B43_NPHY_IQEST_CMD_MODE 0x0002 /* Mode */
427#define B43_NPHY_IQEST_WT B43_PHY_N(0x12A) /* I/Q estimate wait time */
428#define B43_NPHY_IQEST_WT_VAL 0x00FF /* Wait time */
429#define B43_NPHY_IQEST_WT_VAL_SHIFT 0
430#define B43_NPHY_IQEST_SAMCNT B43_PHY_N(0x12B) /* I/Q estimate sample count */
431#define B43_NPHY_IQEST_IQACC_LO0 B43_PHY_N(0x12C) /* I/Q estimate I/Q acc lo 0 */
432#define B43_NPHY_IQEST_IQACC_HI0 B43_PHY_N(0x12D) /* I/Q estimate I/Q acc hi 0 */
433#define B43_NPHY_IQEST_IPACC_LO0 B43_PHY_N(0x12E) /* I/Q estimate I power acc lo 0 */
434#define B43_NPHY_IQEST_IPACC_HI0 B43_PHY_N(0x12F) /* I/Q estimate I power acc hi 0 */
435#define B43_NPHY_IQEST_QPACC_LO0 B43_PHY_N(0x130) /* I/Q estimate Q power acc lo 0 */
436#define B43_NPHY_IQEST_QPACC_HI0 B43_PHY_N(0x131) /* I/Q estimate Q power acc hi 0 */
437#define B43_NPHY_IQEST_IQACC_LO1 B43_PHY_N(0x134) /* I/Q estimate I/Q acc lo 1 */
438#define B43_NPHY_IQEST_IQACC_HI1 B43_PHY_N(0x135) /* I/Q estimate I/Q acc hi 1 */
439#define B43_NPHY_IQEST_IPACC_LO1 B43_PHY_N(0x136) /* I/Q estimate I power acc lo 1 */
440#define B43_NPHY_IQEST_IPACC_HI1 B43_PHY_N(0x137) /* I/Q estimate I power acc hi 1 */
441#define B43_NPHY_IQEST_QPACC_LO1 B43_PHY_N(0x138) /* I/Q estimate Q power acc lo 1 */
442#define B43_NPHY_IQEST_QPACC_HI1 B43_PHY_N(0x139) /* I/Q estimate Q power acc hi 1 */
443#define B43_NPHY_MIMO_CRSTXEXT B43_PHY_N(0x13A) /* MIMO PHY CRS TX extension */
444#define B43_NPHY_PWRDET1 B43_PHY_N(0x13B) /* Power det 1 */
445#define B43_NPHY_PWRDET2 B43_PHY_N(0x13C) /* Power det 2 */
446#define B43_NPHY_MAXRSSI_DTIME B43_PHY_N(0x13F) /* RSSI max RSSI delay time */
447#define B43_NPHY_PIL_DW0 B43_PHY_N(0x141) /* Pilot data weight 0 */
448#define B43_NPHY_PIL_DW1 B43_PHY_N(0x142) /* Pilot data weight 1 */
449#define B43_NPHY_PIL_DW2 B43_PHY_N(0x143) /* Pilot data weight 2 */
450#define B43_NPHY_PIL_DW_BPSK 0x000F /* BPSK */
451#define B43_NPHY_PIL_DW_BPSK_SHIFT 0
452#define B43_NPHY_PIL_DW_QPSK 0x00F0 /* QPSK */
453#define B43_NPHY_PIL_DW_QPSK_SHIFT 4
454#define B43_NPHY_PIL_DW_16QAM 0x0F00 /* 16-QAM */
455#define B43_NPHY_PIL_DW_16QAM_SHIFT 8
456#define B43_NPHY_PIL_DW_64QAM 0xF000 /* 64-QAM */
457#define B43_NPHY_PIL_DW_64QAM_SHIFT 12
458#define B43_NPHY_FMDEM_CFG B43_PHY_N(0x144) /* FM demodulation config */
459#define B43_NPHY_PHASETR_A0 B43_PHY_N(0x145) /* Phase track alpha 0 */
460#define B43_NPHY_PHASETR_A1 B43_PHY_N(0x146) /* Phase track alpha 1 */
461#define B43_NPHY_PHASETR_A2 B43_PHY_N(0x147) /* Phase track alpha 2 */
462#define B43_NPHY_PHASETR_B0 B43_PHY_N(0x148) /* Phase track beta 0 */
463#define B43_NPHY_PHASETR_B1 B43_PHY_N(0x149) /* Phase track beta 1 */
464#define B43_NPHY_PHASETR_B2 B43_PHY_N(0x14A) /* Phase track beta 2 */
465#define B43_NPHY_PHASETR_CHG0 B43_PHY_N(0x14B) /* Phase track change 0 */
466#define B43_NPHY_PHASETR_CHG1 B43_PHY_N(0x14C) /* Phase track change 1 */
467#define B43_NPHY_PHASETW_OFF B43_PHY_N(0x14D) /* Phase track offset */
468#define B43_NPHY_RFCTL_DBG B43_PHY_N(0x14E) /* RF control debug */
469#define B43_NPHY_CCK_SHIFTB_REF B43_PHY_N(0x150) /* CCK shiftbits reference var */
470#define B43_NPHY_OVER_DGAIN0 B43_PHY_N(0x152) /* Override digital gain 0 */
471#define B43_NPHY_OVER_DGAIN1 B43_PHY_N(0x153) /* Override digital gain 1 */
472#define B43_NPHY_OVER_DGAIN_FDGV 0x0007 /* Force digital gain value */
473#define B43_NPHY_OVER_DGAIN_FDGV_SHIFT 0
474#define B43_NPHY_OVER_DGAIN_FDGEN 0x0008 /* Force digital gain enable */
475#define B43_NPHY_OVER_DGAIN_CCKDGECV 0xFF00 /* CCK digital gain enable count value */
476#define B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT 8
477#define B43_NPHY_BIST_STAT4 B43_PHY_N(0x156) /* BIST status 4 */
478#define B43_NPHY_RADAR_MAL B43_PHY_N(0x157) /* Radar MA length */
479#define B43_NPHY_RADAR_SRCCTL B43_PHY_N(0x158) /* Radar search control */
480#define B43_NPHY_VLD_DTSIG B43_PHY_N(0x159) /* VLD data tones sig */
481#define B43_NPHY_VLD_DTDAT B43_PHY_N(0x15A) /* VLD data tones data */
482#define B43_NPHY_C1_BPHY_RXIQCA0 B43_PHY_N(0x15B) /* Core 1 B PHY RX I/Q comp A0 */
483#define B43_NPHY_C1_BPHY_RXIQCB0 B43_PHY_N(0x15C) /* Core 1 B PHY RX I/Q comp B0 */
484#define B43_NPHY_C2_BPHY_RXIQCA1 B43_PHY_N(0x15D) /* Core 2 B PHY RX I/Q comp A1 */
485#define B43_NPHY_C2_BPHY_RXIQCB1 B43_PHY_N(0x15E) /* Core 2 B PHY RX I/Q comp B1 */
486#define B43_NPHY_FREQGAIN0 B43_PHY_N(0x160) /* Frequency gain 0 */
487#define B43_NPHY_FREQGAIN1 B43_PHY_N(0x161) /* Frequency gain 1 */
488#define B43_NPHY_FREQGAIN2 B43_PHY_N(0x162) /* Frequency gain 2 */
489#define B43_NPHY_FREQGAIN3 B43_PHY_N(0x163) /* Frequency gain 3 */
490#define B43_NPHY_FREQGAIN4 B43_PHY_N(0x164) /* Frequency gain 4 */
491#define B43_NPHY_FREQGAIN5 B43_PHY_N(0x165) /* Frequency gain 5 */
492#define B43_NPHY_FREQGAIN6 B43_PHY_N(0x166) /* Frequency gain 6 */
493#define B43_NPHY_FREQGAIN7 B43_PHY_N(0x167) /* Frequency gain 7 */
494#define B43_NPHY_FREQGAIN_BYPASS B43_PHY_N(0x168) /* Frequency gain bypass */
495#define B43_NPHY_TRLOSS B43_PHY_N(0x169) /* TR loss value */
496#define B43_NPHY_C1_ADCCLIP B43_PHY_N(0x16A) /* Core 1 ADC clip */
497#define B43_NPHY_C2_ADCCLIP B43_PHY_N(0x16B) /* Core 2 ADC clip */
498#define B43_NPHY_LTRN_OFFGAIN B43_PHY_N(0x16F) /* LTRN offset gain */
499#define B43_NPHY_LTRN_OFF B43_PHY_N(0x170) /* LTRN offset */
500#define B43_NPHY_NRDATAT_WWISE20SIG B43_PHY_N(0x171) /* # data tones WWiSE 20 sig */
501#define B43_NPHY_NRDATAT_WWISE40SIG B43_PHY_N(0x172) /* # data tones WWiSE 40 sig */
502#define B43_NPHY_NRDATAT_TGNSYNC20SIG B43_PHY_N(0x173) /* # data tones TGNsync 20 sig */
503#define B43_NPHY_NRDATAT_TGNSYNC40SIG B43_PHY_N(0x174) /* # data tones TGNsync 40 sig */
504#define B43_NPHY_WWISE_CRCM0 B43_PHY_N(0x175) /* WWiSE CRC mask 0 */
505#define B43_NPHY_WWISE_CRCM1 B43_PHY_N(0x176) /* WWiSE CRC mask 1 */
506#define B43_NPHY_WWISE_CRCM2 B43_PHY_N(0x177) /* WWiSE CRC mask 2 */
507#define B43_NPHY_WWISE_CRCM3 B43_PHY_N(0x178) /* WWiSE CRC mask 3 */
508#define B43_NPHY_WWISE_CRCM4 B43_PHY_N(0x179) /* WWiSE CRC mask 4 */
509#define B43_NPHY_CHANEST_CDDSH B43_PHY_N(0x17A) /* Channel estimate CDD shift */
510#define B43_NPHY_HTAGC_WCNT B43_PHY_N(0x17B) /* HT ADC wait counters */
511#define B43_NPHY_SQPARM B43_PHY_N(0x17C) /* SQ params */
512#define B43_NPHY_MCSDUP6M B43_PHY_N(0x17D) /* MCS dup 6M */
513#define B43_NPHY_NDATAT_DUP40 B43_PHY_N(0x17E) /* # data tones dup 40 */
514#define B43_NPHY_DUP40_TGNSYNC_CYCD B43_PHY_N(0x17F) /* Dup40 TGNsync cycle data */
515#define B43_NPHY_DUP40_GFBL B43_PHY_N(0x180) /* Dup40 GF format BL address */
516#define B43_NPHY_DUP40_BL B43_PHY_N(0x181) /* Dup40 format BL address */
517#define B43_NPHY_LEGDUP_FTA B43_PHY_N(0x182) /* Legacy dup frm table address */
518#define B43_NPHY_PACPROC_DBG B43_PHY_N(0x183) /* Packet processing debug */
519#define B43_NPHY_PIL_CYC1 B43_PHY_N(0x184) /* Pilot cycle counter 1 */
520#define B43_NPHY_PIL_CYC2 B43_PHY_N(0x185) /* Pilot cycle counter 2 */
521#define B43_NPHY_TXF_20CO_S0A1 B43_PHY_N(0x186) /* TX filter 20 coeff stage 0 A1 */
522#define B43_NPHY_TXF_20CO_S0A2 B43_PHY_N(0x187) /* TX filter 20 coeff stage 0 A2 */
523#define B43_NPHY_TXF_20CO_S1A1 B43_PHY_N(0x188) /* TX filter 20 coeff stage 1 A1 */
524#define B43_NPHY_TXF_20CO_S1A2 B43_PHY_N(0x189) /* TX filter 20 coeff stage 1 A2 */
525#define B43_NPHY_TXF_20CO_S2A1 B43_PHY_N(0x18A) /* TX filter 20 coeff stage 2 A1 */
526#define B43_NPHY_TXF_20CO_S2A2 B43_PHY_N(0x18B) /* TX filter 20 coeff stage 2 A2 */
527#define B43_NPHY_TXF_20CO_S0B1 B43_PHY_N(0x18C) /* TX filter 20 coeff stage 0 B1 */
528#define B43_NPHY_TXF_20CO_S0B2 B43_PHY_N(0x18D) /* TX filter 20 coeff stage 0 B2 */
529#define B43_NPHY_TXF_20CO_S0B3 B43_PHY_N(0x18E) /* TX filter 20 coeff stage 0 B3 */
530#define B43_NPHY_TXF_20CO_S1B1 B43_PHY_N(0x18F) /* TX filter 20 coeff stage 1 B1 */
531#define B43_NPHY_TXF_20CO_S1B2 B43_PHY_N(0x190) /* TX filter 20 coeff stage 1 B2 */
532#define B43_NPHY_TXF_20CO_S1B3 B43_PHY_N(0x191) /* TX filter 20 coeff stage 1 B3 */
533#define B43_NPHY_TXF_20CO_S2B1 B43_PHY_N(0x192) /* TX filter 20 coeff stage 2 B1 */
534#define B43_NPHY_TXF_20CO_S2B2 B43_PHY_N(0x193) /* TX filter 20 coeff stage 2 B2 */
535#define B43_NPHY_TXF_20CO_S2B3 B43_PHY_N(0x194) /* TX filter 20 coeff stage 2 B3 */
536#define B43_NPHY_TXF_40CO_S0A1 B43_PHY_N(0x195) /* TX filter 40 coeff stage 0 A1 */
537#define B43_NPHY_TXF_40CO_S0A2 B43_PHY_N(0x196) /* TX filter 40 coeff stage 0 A2 */
538#define B43_NPHY_TXF_40CO_S1A1 B43_PHY_N(0x197) /* TX filter 40 coeff stage 1 A1 */
539#define B43_NPHY_TXF_40CO_S1A2 B43_PHY_N(0x198) /* TX filter 40 coeff stage 1 A2 */
540#define B43_NPHY_TXF_40CO_S2A1 B43_PHY_N(0x199) /* TX filter 40 coeff stage 2 A1 */
541#define B43_NPHY_TXF_40CO_S2A2 B43_PHY_N(0x19A) /* TX filter 40 coeff stage 2 A2 */
542#define B43_NPHY_TXF_40CO_S0B1 B43_PHY_N(0x19B) /* TX filter 40 coeff stage 0 B1 */
543#define B43_NPHY_TXF_40CO_S0B2 B43_PHY_N(0x19C) /* TX filter 40 coeff stage 0 B2 */
544#define B43_NPHY_TXF_40CO_S0B3 B43_PHY_N(0x19D) /* TX filter 40 coeff stage 0 B3 */
545#define B43_NPHY_TXF_40CO_S1B1 B43_PHY_N(0x19E) /* TX filter 40 coeff stage 1 B1 */
546#define B43_NPHY_TXF_40CO_S1B2 B43_PHY_N(0x19F) /* TX filter 40 coeff stage 1 B2 */
547#define B43_NPHY_TXF_40CO_S1B3 B43_PHY_N(0x1A0) /* TX filter 40 coeff stage 1 B3 */
548#define B43_NPHY_TXF_40CO_S2B1 B43_PHY_N(0x1A1) /* TX filter 40 coeff stage 2 B1 */
549#define B43_NPHY_TXF_40CO_S2B2 B43_PHY_N(0x1A2) /* TX filter 40 coeff stage 2 B2 */
550#define B43_NPHY_TXF_40CO_S2B3 B43_PHY_N(0x1A3) /* TX filter 40 coeff stage 2 B3 */
551#define B43_NPHY_RSSIMC_0I_RSSI_X B43_PHY_N(0x1A4) /* RSSI multiplication coefficient 0 I RSSI X */
552#define B43_NPHY_RSSIMC_0I_RSSI_Y B43_PHY_N(0x1A5) /* RSSI multiplication coefficient 0 I RSSI Y */
553#define B43_NPHY_RSSIMC_0I_RSSI_Z B43_PHY_N(0x1A6) /* RSSI multiplication coefficient 0 I RSSI Z */
554#define B43_NPHY_RSSIMC_0I_TBD B43_PHY_N(0x1A7) /* RSSI multiplication coefficient 0 I TBD */
555#define B43_NPHY_RSSIMC_0I_PWRDET B43_PHY_N(0x1A8) /* RSSI multiplication coefficient 0 I power det */
556#define B43_NPHY_RSSIMC_0I_TSSI B43_PHY_N(0x1A9) /* RSSI multiplication coefficient 0 I TSSI */
557#define B43_NPHY_RSSIMC_0Q_RSSI_X B43_PHY_N(0x1AA) /* RSSI multiplication coefficient 0 Q RSSI X */
558#define B43_NPHY_RSSIMC_0Q_RSSI_Y B43_PHY_N(0x1AB) /* RSSI multiplication coefficient 0 Q RSSI Y */
559#define B43_NPHY_RSSIMC_0Q_RSSI_Z B43_PHY_N(0x1AC) /* RSSI multiplication coefficient 0 Q RSSI Z */
560#define B43_NPHY_RSSIMC_0Q_TBD B43_PHY_N(0x1AD) /* RSSI multiplication coefficient 0 Q TBD */
561#define B43_NPHY_RSSIMC_0Q_PWRDET B43_PHY_N(0x1AE) /* RSSI multiplication coefficient 0 Q power det */
562#define B43_NPHY_RSSIMC_0Q_TSSI B43_PHY_N(0x1AF) /* RSSI multiplication coefficient 0 Q TSSI */
563#define B43_NPHY_RSSIMC_1I_RSSI_X B43_PHY_N(0x1B0) /* RSSI multiplication coefficient 1 I RSSI X */
564#define B43_NPHY_RSSIMC_1I_RSSI_Y B43_PHY_N(0x1B1) /* RSSI multiplication coefficient 1 I RSSI Y */
565#define B43_NPHY_RSSIMC_1I_RSSI_Z B43_PHY_N(0x1B2) /* RSSI multiplication coefficient 1 I RSSI Z */
566#define B43_NPHY_RSSIMC_1I_TBD B43_PHY_N(0x1B3) /* RSSI multiplication coefficient 1 I TBD */
567#define B43_NPHY_RSSIMC_1I_PWRDET B43_PHY_N(0x1B4) /* RSSI multiplication coefficient 1 I power det */
568#define B43_NPHY_RSSIMC_1I_TSSI B43_PHY_N(0x1B5) /* RSSI multiplication coefficient 1 I TSSI */
569#define B43_NPHY_RSSIMC_1Q_RSSI_X B43_PHY_N(0x1B6) /* RSSI multiplication coefficient 1 Q RSSI X */
570#define B43_NPHY_RSSIMC_1Q_RSSI_Y B43_PHY_N(0x1B7) /* RSSI multiplication coefficient 1 Q RSSI Y */
571#define B43_NPHY_RSSIMC_1Q_RSSI_Z B43_PHY_N(0x1B8) /* RSSI multiplication coefficient 1 Q RSSI Z */
572#define B43_NPHY_RSSIMC_1Q_TBD B43_PHY_N(0x1B9) /* RSSI multiplication coefficient 1 Q TBD */
573#define B43_NPHY_RSSIMC_1Q_PWRDET B43_PHY_N(0x1BA) /* RSSI multiplication coefficient 1 Q power det */
574#define B43_NPHY_RSSIMC_1Q_TSSI B43_PHY_N(0x1BB) /* RSSI multiplication coefficient 1 Q TSSI */
575#define B43_NPHY_SAMC_WCNT B43_PHY_N(0x1BC) /* Sample collect wait counter */
576#define B43_NPHY_PTHROUGH_CNT B43_PHY_N(0x1BD) /* Pass-through counter */
577#define B43_NPHY_LTRN_OFF_G20L B43_PHY_N(0x1C4) /* LTRN offset gain 20L */
578#define B43_NPHY_LTRN_OFF_20L B43_PHY_N(0x1C5) /* LTRN offset 20L */
579#define B43_NPHY_LTRN_OFF_G20U B43_PHY_N(0x1C6) /* LTRN offset gain 20U */
580#define B43_NPHY_LTRN_OFF_20U B43_PHY_N(0x1C7) /* LTRN offset 20U */
581#define B43_NPHY_DSSSCCK_GAINSL B43_PHY_N(0x1C8) /* DSSS/CCK gain settle length */
582#define B43_NPHY_GPIO_LOOUT B43_PHY_N(0x1C9) /* GPIO low out */
583#define B43_NPHY_GPIO_HIOUT B43_PHY_N(0x1CA) /* GPIO high out */
584#define B43_NPHY_CRS_CHECK B43_PHY_N(0x1CB) /* CRS check */
585#define B43_NPHY_ML_LOGSS_RAT B43_PHY_N(0x1CC) /* ML/logss ratio */
586#define B43_NPHY_DUPSCALE B43_PHY_N(0x1CD) /* Dup scale */
587#define B43_NPHY_BW1A B43_PHY_N(0x1CE) /* BW 1A */
588#define B43_NPHY_BW2 B43_PHY_N(0x1CF) /* BW 2 */
589#define B43_NPHY_BW3 B43_PHY_N(0x1D0) /* BW 3 */
590#define B43_NPHY_BW4 B43_PHY_N(0x1D1) /* BW 4 */
591#define B43_NPHY_BW5 B43_PHY_N(0x1D2) /* BW 5 */
592#define B43_NPHY_BW6 B43_PHY_N(0x1D3) /* BW 6 */
593#define B43_NPHY_COALEN0 B43_PHY_N(0x1D4) /* Coarse length 0 */
594#define B43_NPHY_COALEN1 B43_PHY_N(0x1D5) /* Coarse length 1 */
595#define B43_NPHY_CRSTHRES_1U B43_PHY_N(0x1D6) /* CRS threshold 1 U */
596#define B43_NPHY_CRSTHRES_2U B43_PHY_N(0x1D7) /* CRS threshold 2 U */
597#define B43_NPHY_CRSTHRES_3U B43_PHY_N(0x1D8) /* CRS threshold 3 U */
598#define B43_NPHY_CRSCTL_U B43_PHY_N(0x1D9) /* CRS control U */
599#define B43_NPHY_CRSTHRES_1L B43_PHY_N(0x1DA) /* CRS threshold 1 L */
600#define B43_NPHY_CRSTHRES_2L B43_PHY_N(0x1DB) /* CRS threshold 2 L */
601#define B43_NPHY_CRSTHRES_3L B43_PHY_N(0x1DC) /* CRS threshold 3 L */
602#define B43_NPHY_CRSCTL_L B43_PHY_N(0x1DD) /* CRS control L */
603#define B43_NPHY_STRA_1U B43_PHY_N(0x1DE) /* STR address 1 U */
604#define B43_NPHY_STRA_2U B43_PHY_N(0x1DF) /* STR address 2 U */
605#define B43_NPHY_STRA_1L B43_PHY_N(0x1E0) /* STR address 1 L */
606#define B43_NPHY_STRA_2L B43_PHY_N(0x1E1) /* STR address 2 L */
607#define B43_NPHY_CRSCHECK1 B43_PHY_N(0x1E2) /* CRS check 1 */
608#define B43_NPHY_CRSCHECK2 B43_PHY_N(0x1E3) /* CRS check 2 */
609#define B43_NPHY_CRSCHECK3 B43_PHY_N(0x1E4) /* CRS check 3 */
610#define B43_NPHY_JMPSTP0 B43_PHY_N(0x1E5) /* Jump step 0 */
611#define B43_NPHY_JMPSTP1 B43_PHY_N(0x1E6) /* Jump step 1 */
612#define B43_NPHY_TXPCTL_CMD B43_PHY_N(0x1E7) /* TX power control command */
613#define B43_NPHY_TXPCTL_CMD_INIT 0x007F /* Init */
614#define B43_NPHY_TXPCTL_CMD_INIT_SHIFT 0
615#define B43_NPHY_TXPCTL_CMD_COEFF 0x2000 /* Power control coefficients */
616#define B43_NPHY_TXPCTL_CMD_HWPCTLEN 0x4000 /* Hardware TX power control enable */
617#define B43_NPHY_TXPCTL_CMD_PCTLEN 0x8000 /* TX power control enable */
618#define B43_NPHY_TXPCTL_N B43_PHY_N(0x1E8) /* TX power control N num */
619#define B43_NPHY_TXPCTL_N_TSSID 0x00FF /* N TSSI delay */
620#define B43_NPHY_TXPCTL_N_TSSID_SHIFT 0
621#define B43_NPHY_TXPCTL_N_NPTIL2 0x0700 /* N PT integer log2 */
622#define B43_NPHY_TXPCTL_N_NPTIL2_SHIFT 8
623#define B43_NPHY_TXPCTL_ITSSI B43_PHY_N(0x1E9) /* TX power control idle TSSI */
624#define B43_NPHY_TXPCTL_ITSSI_0 0x003F /* Idle TSSI 0 */
625#define B43_NPHY_TXPCTL_ITSSI_0_SHIFT 0
626#define B43_NPHY_TXPCTL_ITSSI_1 0x3F00 /* Idle TSSI 1 */
627#define B43_NPHY_TXPCTL_ITSSI_1_SHIFT 8
628#define B43_NPHY_TXPCTL_ITSSI_BINF 0x8000 /* Raw TSSI offset bin format */
629#define B43_NPHY_TXPCTL_TPWR B43_PHY_N(0x1EA) /* TX power control target power */
630#define B43_NPHY_TXPCTL_TPWR_0 0x00FF /* Power 0 */
631#define B43_NPHY_TXPCTL_TPWR_0_SHIFT 0
632#define B43_NPHY_TXPCTL_TPWR_1 0xFF00 /* Power 1 */
633#define B43_NPHY_TXPCTL_TPWR_1_SHIFT 8
634#define B43_NPHY_TXPCTL_BIDX B43_PHY_N(0x1EB) /* TX power control base index */
635#define B43_NPHY_TXPCTL_BIDX_0 0x007F /* uC base index 0 */
636#define B43_NPHY_TXPCTL_BIDX_0_SHIFT 0
637#define B43_NPHY_TXPCTL_BIDX_1 0x7F00 /* uC base index 1 */
638#define B43_NPHY_TXPCTL_BIDX_1_SHIFT 8
639#define B43_NPHY_TXPCTL_BIDX_LOAD 0x8000 /* Load base index */
640#define B43_NPHY_TXPCTL_PIDX B43_PHY_N(0x1EC) /* TX power control power index */
641#define B43_NPHY_TXPCTL_PIDX_0 0x007F /* uC power index 0 */
642#define B43_NPHY_TXPCTL_PIDX_0_SHIFT 0
643#define B43_NPHY_TXPCTL_PIDX_1 0x7F00 /* uC power index 1 */
644#define B43_NPHY_TXPCTL_PIDX_1_SHIFT 8
645#define B43_NPHY_C1_TXPCTL_STAT B43_PHY_N(0x1ED) /* Core 1 TX power control status */
646#define B43_NPHY_C2_TXPCTL_STAT B43_PHY_N(0x1EE) /* Core 2 TX power control status */
647#define B43_NPHY_TXPCTL_STAT_EST 0x00FF /* Estimated power */
648#define B43_NPHY_TXPCTL_STAT_EST_SHIFT 0
649#define B43_NPHY_TXPCTL_STAT_BIDX 0x7F00 /* Base index */
650#define B43_NPHY_TXPCTL_STAT_BIDX_SHIFT 8
651#define B43_NPHY_TXPCTL_STAT_ESTVALID 0x8000 /* Estimated power valid */
652#define B43_NPHY_SMALLSGS_LEN B43_PHY_N(0x1EF) /* Small sig gain settle length */
653#define B43_NPHY_PHYSTAT_GAIN0 B43_PHY_N(0x1F0) /* PHY stats gain info 0 */
654#define B43_NPHY_PHYSTAT_GAIN1 B43_PHY_N(0x1F1) /* PHY stats gain info 1 */
655#define B43_NPHY_PHYSTAT_FREQEST B43_PHY_N(0x1F2) /* PHY stats frequency estimate */
656#define B43_NPHY_PHYSTAT_ADVRET B43_PHY_N(0x1F3) /* PHY stats ADV retard */
657#define B43_NPHY_PHYLB_MODE B43_PHY_N(0x1F4) /* PHY loopback mode */
658#define B43_NPHY_TONE_MIDX20_1 B43_PHY_N(0x1F5) /* Tone map index 20/1 */
659#define B43_NPHY_TONE_MIDX20_2 B43_PHY_N(0x1F6) /* Tone map index 20/2 */
660#define B43_NPHY_TONE_MIDX20_3 B43_PHY_N(0x1F7) /* Tone map index 20/3 */
661#define B43_NPHY_TONE_MIDX40_1 B43_PHY_N(0x1F8) /* Tone map index 40/1 */
662#define B43_NPHY_TONE_MIDX40_2 B43_PHY_N(0x1F9) /* Tone map index 40/2 */
663#define B43_NPHY_TONE_MIDX40_3 B43_PHY_N(0x1FA) /* Tone map index 40/3 */
664#define B43_NPHY_TONE_MIDX40_4 B43_PHY_N(0x1FB) /* Tone map index 40/4 */
665#define B43_NPHY_PILTONE_MIDX1 B43_PHY_N(0x1FC) /* Pilot tone map index 1 */
666#define B43_NPHY_PILTONE_MIDX2 B43_PHY_N(0x1FD) /* Pilot tone map index 2 */
667#define B43_NPHY_PILTONE_MIDX3 B43_PHY_N(0x1FE) /* Pilot tone map index 3 */
668#define B43_NPHY_TXRIFS_FRDEL B43_PHY_N(0x1FF) /* TX RIFS frame delay */
669#define B43_NPHY_AFESEQ_RX2TX_PUD_40M B43_PHY_N(0x200) /* AFE seq rx2tx power up/down delay 40M */
670#define B43_NPHY_AFESEQ_TX2RX_PUD_40M B43_PHY_N(0x201) /* AFE seq tx2rx power up/down delay 40M */
671#define B43_NPHY_AFESEQ_RX2TX_PUD_20M B43_PHY_N(0x202) /* AFE seq rx2tx power up/down delay 20M */
672#define B43_NPHY_AFESEQ_TX2RX_PUD_20M B43_PHY_N(0x203) /* AFE seq tx2rx power up/down delay 20M */
673#define B43_NPHY_RX_SIGCTL B43_PHY_N(0x204) /* RX signal control */
674#define B43_NPHY_RXPIL_CYCNT0 B43_PHY_N(0x205) /* RX pilot cycle counter 0 */
675#define B43_NPHY_RXPIL_CYCNT1 B43_PHY_N(0x206) /* RX pilot cycle counter 1 */
676#define B43_NPHY_RXPIL_CYCNT2 B43_PHY_N(0x207) /* RX pilot cycle counter 2 */
677#define B43_NPHY_AFESEQ_RX2TX_PUD_10M B43_PHY_N(0x208) /* AFE seq rx2tx power up/down delay 10M */
678#define B43_NPHY_AFESEQ_TX2RX_PUD_10M B43_PHY_N(0x209) /* AFE seq tx2rx power up/down delay 10M */
679#define B43_NPHY_DSSSCCK_CRSEXTL B43_PHY_N(0x20A) /* DSSS/CCK CRS extension length */
680#define B43_NPHY_ML_LOGSS_RATSLOPE B43_PHY_N(0x20B) /* ML/logss ratio slope */
681#define B43_NPHY_RIFS_SRCTL B43_PHY_N(0x20C) /* RIFS search timeout length */
682#define B43_NPHY_TXREALFD B43_PHY_N(0x20D) /* TX real frame delay */
683#define B43_NPHY_HPANT_SWTHRES B43_PHY_N(0x20E) /* High power antenna switch threshold */
684#define B43_NPHY_EDCRS_ASSTHRES0 B43_PHY_N(0x210) /* ED CRS assert threshold 0 */
685#define B43_NPHY_EDCRS_ASSTHRES1 B43_PHY_N(0x211) /* ED CRS assert threshold 1 */
686#define B43_NPHY_EDCRS_DEASSTHRES0 B43_PHY_N(0x212) /* ED CRS deassert threshold 0 */
687#define B43_NPHY_EDCRS_DEASSTHRES1 B43_PHY_N(0x213) /* ED CRS deassert threshold 1 */
688#define B43_NPHY_STR_WTIME20U B43_PHY_N(0x214) /* STR wait time 20U */
689#define B43_NPHY_STR_WTIME20L B43_PHY_N(0x215) /* STR wait time 20L */
690#define B43_NPHY_TONE_MIDX657M B43_PHY_N(0x216) /* Tone map index 657M */
691#define B43_NPHY_HTSIGTONES B43_PHY_N(0x217) /* HT signal tones */
692#define B43_NPHY_RSSI1 B43_PHY_N(0x219) /* RSSI value 1 */
693#define B43_NPHY_RSSI2 B43_PHY_N(0x21A) /* RSSI value 2 */
694#define B43_NPHY_CHAN_ESTHANG B43_PHY_N(0x21D) /* Channel estimate hang */
695#define B43_NPHY_FINERX2_CGC B43_PHY_N(0x221) /* Fine RX 2 clock gate control */
696#define B43_NPHY_FINERX2_CGC_DECGC 0x0008 /* Decode gated clocks */
697#define B43_NPHY_TXPCTL_INIT B43_PHY_N(0x222) /* TX power controll init */
698#define B43_NPHY_TXPCTL_INIT_PIDXI1 0x00FF /* Power index init 1 */
699#define B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0
700
701
702struct b43_wldev;
703
704int b43_phy_initn(struct b43_wldev *dev);
705
706#endif /* B43_NPHY_H_ */
diff --git a/drivers/net/wireless/b43/phy.c b/drivers/net/wireless/b43/phy.c
index facc01c25f90..b544f7ff14f8 100644
--- a/drivers/net/wireless/b43/phy.c
+++ b/drivers/net/wireless/b43/phy.c
@@ -31,6 +31,7 @@
31 31
32#include "b43.h" 32#include "b43.h"
33#include "phy.h" 33#include "phy.h"
34#include "nphy.h"
34#include "main.h" 35#include "main.h"
35#include "tables.h" 36#include "tables.h"
36#include "lo.h" 37#include "lo.h"
@@ -1974,41 +1975,44 @@ int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev)
1974int b43_phy_init(struct b43_wldev *dev) 1975int b43_phy_init(struct b43_wldev *dev)
1975{ 1976{
1976 struct b43_phy *phy = &dev->phy; 1977 struct b43_phy *phy = &dev->phy;
1977 int err = -ENODEV; 1978 bool unsupported = 0;
1979 int err = 0;
1978 1980
1979 switch (phy->type) { 1981 switch (phy->type) {
1980 case B43_PHYTYPE_A: 1982 case B43_PHYTYPE_A:
1981 if (phy->rev == 2 || phy->rev == 3) { 1983 if (phy->rev == 2 || phy->rev == 3)
1982 b43_phy_inita(dev); 1984 b43_phy_inita(dev);
1983 err = 0; 1985 else
1984 } 1986 unsupported = 1;
1985 break; 1987 break;
1986 case B43_PHYTYPE_B: 1988 case B43_PHYTYPE_B:
1987 switch (phy->rev) { 1989 switch (phy->rev) {
1988 case 2: 1990 case 2:
1989 b43_phy_initb2(dev); 1991 b43_phy_initb2(dev);
1990 err = 0;
1991 break; 1992 break;
1992 case 4: 1993 case 4:
1993 b43_phy_initb4(dev); 1994 b43_phy_initb4(dev);
1994 err = 0;
1995 break; 1995 break;
1996 case 5: 1996 case 5:
1997 b43_phy_initb5(dev); 1997 b43_phy_initb5(dev);
1998 err = 0;
1999 break; 1998 break;
2000 case 6: 1999 case 6:
2001 b43_phy_initb6(dev); 2000 b43_phy_initb6(dev);
2002 err = 0;
2003 break; 2001 break;
2002 default:
2003 unsupported = 1;
2004 } 2004 }
2005 break; 2005 break;
2006 case B43_PHYTYPE_G: 2006 case B43_PHYTYPE_G:
2007 b43_phy_initg(dev); 2007 b43_phy_initg(dev);
2008 err = 0;
2009 break; 2008 break;
2009 case B43_PHYTYPE_N:
2010 err = b43_phy_initn(dev);
2011 break;
2012 default:
2013 unsupported = 1;
2010 } 2014 }
2011 if (err) 2015 if (unsupported)
2012 b43err(dev->wl, "Unknown PHYTYPE found\n"); 2016 b43err(dev->wl, "Unknown PHYTYPE found\n");
2013 2017
2014 return err; 2018 return err;
diff --git a/drivers/net/wireless/b43/phy.h b/drivers/net/wireless/b43/phy.h
index 3525f5652460..5d09fb13b899 100644
--- a/drivers/net/wireless/b43/phy.h
+++ b/drivers/net/wireless/b43/phy.h
@@ -9,11 +9,14 @@ struct b43_phy;
9/*** PHY Registers ***/ 9/*** PHY Registers ***/
10 10
11/* Routing */ 11/* Routing */
12#define B43_PHYROUTE_OFDM_GPHY 0x400 12#define B43_PHYROUTE_OFDM_GPHY 0x0400 /* OFDM register routing for G-PHYs */
13#define B43_PHYROUTE_EXT_GPHY 0x800 13#define B43_PHYROUTE_EXT_GPHY 0x0800 /* Extended G-PHY registers */
14#define B43_PHYROUTE_N_BMODE 0x3000 /* N-PHY BMODE registers */
14 15
15/* Base registers. */ 16/* Base registers. */
16#define B43_PHY_BASE(reg) (reg) 17#define B43_PHY_BASE(reg) (reg)
18/* N-PHY registers. */
19#define B43_PHY_N(reg) (reg)
17/* OFDM (A) registers of a G-PHY */ 20/* OFDM (A) registers of a G-PHY */
18#define B43_PHY_OFDM(reg) ((reg) | B43_PHYROUTE_OFDM_GPHY) 21#define B43_PHY_OFDM(reg) ((reg) | B43_PHYROUTE_OFDM_GPHY)
19/* Extended G-PHY registers */ 22/* Extended G-PHY registers */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 04:07:21 -0500