[MIPS] Fix timer/performance interrupt detection

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 4 insertions, 4 deletions

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index b1233644fcca..3ea7863c4519 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1372,12 +1372,12 @@ void __init per_cpu_trap_init(void)
          */
         if (cpu_has_mips_r2) {
                 cp0_compare_irq = (read_c0_intctl () >> 29) & 7;
-                cp0_perfcount_irq = -1;
-        } else {
-                cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
                 cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7;
-                if (cp0_perfcount_irq != cp0_compare_irq)
+                if (cp0_perfcount_irq == cp0_compare_irq)
                         cp0_perfcount_irq = -1;
+        } else {
+                cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
+                cp0_perfcount_irq = -1;
         }
 
 #ifdef CONFIG_MIPS_MT_SMTC