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authorSascha Hauer <s.hauer@pengutronix.de>2010-02-10 05:11:37 -0500
committerSascha Hauer <s.hauer@pengutronix.de>2010-02-10 05:11:37 -0500
commitfed9b63ca5aa999e618140cc1cc6bd73f212ec9b (patch)
tree1dc078e208d879a65f8cc2515e0817a109272d59
parentd2831d1f543489ef97a20e6e65f625e195b521bf (diff)
parent3d48e1d0e8701d004ce7e1dd66088f42e429d079 (diff)
Merge branch 'mx51-baseport-sascha' of git://kernel.ubuntu.com/amitk/mx51-upstream into mxc-master
Diffstat
-rw-r--r--MAINTAINERS6
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/configs/mx51_defconfig1286
-rw-r--r--arch/arm/mach-mx5/Kconfig18
-rw-r--r--arch/arm/mach-mx5/Makefile9
-rw-r--r--arch/arm/mach-mx5/Makefile.boot3
-rw-r--r--arch/arm/mach-mx5/board-mx51_babbage.c98
-rw-r--r--arch/arm/mach-mx5/clock-mx51.c825
-rw-r--r--arch/arm/mach-mx5/cpu.c47
-rw-r--r--arch/arm/mach-mx5/crm_regs.h583
-rw-r--r--arch/arm/mach-mx5/devices.c96
-rw-r--r--arch/arm/mach-mx5/devices.h4
-rw-r--r--arch/arm/mach-mx5/mm.c89
-rw-r--r--arch/arm/plat-mxc/Kconfig16
-rw-r--r--arch/arm/plat-mxc/Makefile3
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S9
-rw-r--r--arch/arm/plat-mxc/include/mach/entry-macro.S34
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx51.h326
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v3.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/irqs.h9
-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/mx51.h454
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h13
-rw-r--r--arch/arm/plat-mxc/include/mach/timex.h2
-rw-r--r--arch/arm/plat-mxc/time.c41
-rw-r--r--arch/arm/plat-mxc/tzic.c172
28 files changed, 4144 insertions, 20 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 66f5f7dab285..6a1773d62e52 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -663,6 +663,12 @@ T: git://git.pengutronix.de/git/imx/linux-2.6.git
663F: arch/arm/mach-mx*/ 663F: arch/arm/mach-mx*/
664F: arch/arm/plat-mxc/ 664F: arch/arm/plat-mxc/
665 665
666ARM/FREESCALE IMX51
667M: Amit Kucheria <amit.kucheria@canonical.com>
668L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
669S: Maintained
670F: arch/arm/mach-mx5/
671
666ARM/GLOMATION GESBC9312SX MACHINE SUPPORT 672ARM/GLOMATION GESBC9312SX MACHINE SUPPORT
667M: Lennert Buytenhek <kernel@wantstofly.org> 673M: Lennert Buytenhek <kernel@wantstofly.org>
668L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 674L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index e9da08483b3c..056daf8b68a5 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -146,6 +146,7 @@ machine-$(CONFIG_ARCH_MX1) := mx1
146machine-$(CONFIG_ARCH_MX2) := mx2 146machine-$(CONFIG_ARCH_MX2) := mx2
147machine-$(CONFIG_ARCH_MX25) := mx25 147machine-$(CONFIG_ARCH_MX25) := mx25
148machine-$(CONFIG_ARCH_MX3) := mx3 148machine-$(CONFIG_ARCH_MX3) := mx3
149machine-$(CONFIG_ARCH_MX5) := mx5
149machine-$(CONFIG_ARCH_NETX) := netx 150machine-$(CONFIG_ARCH_NETX) := netx
150machine-$(CONFIG_ARCH_NOMADIK) := nomadik 151machine-$(CONFIG_ARCH_NOMADIK) := nomadik
151machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx 152machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx
diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig
new file mode 100644
index 000000000000..c88e9527a8ec
--- /dev/null
+++ b/arch/arm/configs/mx51_defconfig
@@ -0,0 +1,1286 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.33-rc6
4# Tue Feb 2 15:20:48 2010
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_GENERIC_HARDIRQS=y
12CONFIG_STACKTRACE_SUPPORT=y
13CONFIG_HAVE_LATENCYTOP_SUPPORT=y
14CONFIG_LOCKDEP_SUPPORT=y
15CONFIG_TRACE_IRQFLAGS_SUPPORT=y
16CONFIG_HARDIRQS_SW_RESEND=y
17CONFIG_GENERIC_IRQ_PROBE=y
18CONFIG_RWSEM_GENERIC_SPINLOCK=y
19CONFIG_GENERIC_HWEIGHT=y
20CONFIG_GENERIC_CALIBRATE_DELAY=y
21CONFIG_ARCH_MTD_XIP=y
22CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
23CONFIG_VECTORS_BASE=0xffff0000
24CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
25CONFIG_CONSTRUCTORS=y
26
27#
28# General setup
29#
30CONFIG_EXPERIMENTAL=y
31CONFIG_BROKEN_ON_SMP=y
32CONFIG_INIT_ENV_ARG_LIMIT=32
33CONFIG_LOCALVERSION=""
34# CONFIG_LOCALVERSION_AUTO is not set
35CONFIG_HAVE_KERNEL_GZIP=y
36CONFIG_HAVE_KERNEL_LZO=y
37CONFIG_KERNEL_GZIP=y
38# CONFIG_KERNEL_BZIP2 is not set
39# CONFIG_KERNEL_LZMA is not set
40# CONFIG_KERNEL_LZO is not set
41CONFIG_SWAP=y
42CONFIG_SYSVIPC=y
43CONFIG_SYSVIPC_SYSCTL=y
44# CONFIG_POSIX_MQUEUE is not set
45# CONFIG_BSD_PROCESS_ACCT is not set
46# CONFIG_TASKSTATS is not set
47# CONFIG_AUDIT is not set
48
49#
50# RCU Subsystem
51#
52CONFIG_TREE_RCU=y
53# CONFIG_TREE_PREEMPT_RCU is not set
54# CONFIG_TINY_RCU is not set
55# CONFIG_RCU_TRACE is not set
56CONFIG_RCU_FANOUT=32
57# CONFIG_RCU_FANOUT_EXACT is not set
58# CONFIG_TREE_RCU_TRACE is not set
59# CONFIG_IKCONFIG is not set
60CONFIG_LOG_BUF_SHIFT=18
61# CONFIG_GROUP_SCHED is not set
62# CONFIG_CGROUPS is not set
63# CONFIG_SYSFS_DEPRECATED_V2 is not set
64CONFIG_RELAY=y
65# CONFIG_NAMESPACES is not set
66# CONFIG_BLK_DEV_INITRD is not set
67CONFIG_CC_OPTIMIZE_FOR_SIZE=y
68CONFIG_SYSCTL=y
69CONFIG_ANON_INODES=y
70CONFIG_EMBEDDED=y
71CONFIG_UID16=y
72CONFIG_SYSCTL_SYSCALL=y
73CONFIG_KALLSYMS=y
74# CONFIG_KALLSYMS_ALL is not set
75# CONFIG_KALLSYMS_EXTRA_PASS is not set
76CONFIG_HOTPLUG=y
77CONFIG_PRINTK=y
78CONFIG_BUG=y
79CONFIG_ELF_CORE=y
80CONFIG_BASE_FULL=y
81CONFIG_FUTEX=y
82CONFIG_EPOLL=y
83CONFIG_SIGNALFD=y
84CONFIG_TIMERFD=y
85CONFIG_EVENTFD=y
86CONFIG_SHMEM=y
87CONFIG_AIO=y
88
89#
90# Kernel Performance Events And Counters
91#
92CONFIG_VM_EVENT_COUNTERS=y
93# CONFIG_SLUB_DEBUG is not set
94# CONFIG_COMPAT_BRK is not set
95# CONFIG_SLAB is not set
96CONFIG_SLUB=y
97# CONFIG_SLOB is not set
98# CONFIG_PROFILING is not set
99CONFIG_HAVE_OPROFILE=y
100# CONFIG_KPROBES is not set
101CONFIG_HAVE_KPROBES=y
102CONFIG_HAVE_KRETPROBES=y
103CONFIG_HAVE_CLK=y
104
105#
106# GCOV-based kernel profiling
107#
108# CONFIG_GCOV_KERNEL is not set
109# CONFIG_SLOW_WORK is not set
110CONFIG_HAVE_GENERIC_DMA_COHERENT=y
111CONFIG_RT_MUTEXES=y
112CONFIG_BASE_SMALL=0
113CONFIG_MODULES=y
114# CONFIG_MODULE_FORCE_LOAD is not set
115CONFIG_MODULE_UNLOAD=y
116# CONFIG_MODULE_FORCE_UNLOAD is not set
117CONFIG_MODVERSIONS=y
118CONFIG_MODULE_SRCVERSION_ALL=y
119CONFIG_BLOCK=y
120# CONFIG_LBDAF is not set
121# CONFIG_BLK_DEV_BSG is not set
122# CONFIG_BLK_DEV_INTEGRITY is not set
123
124#
125# IO Schedulers
126#
127CONFIG_IOSCHED_NOOP=y
128CONFIG_IOSCHED_DEADLINE=y
129CONFIG_IOSCHED_CFQ=y
130# CONFIG_DEFAULT_DEADLINE is not set
131CONFIG_DEFAULT_CFQ=y
132# CONFIG_DEFAULT_NOOP is not set
133CONFIG_DEFAULT_IOSCHED="cfq"
134# CONFIG_INLINE_SPIN_TRYLOCK is not set
135# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
136# CONFIG_INLINE_SPIN_LOCK is not set
137# CONFIG_INLINE_SPIN_LOCK_BH is not set
138# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
139# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
140CONFIG_INLINE_SPIN_UNLOCK=y
141# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
142CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
143# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
144# CONFIG_INLINE_READ_TRYLOCK is not set
145# CONFIG_INLINE_READ_LOCK is not set
146# CONFIG_INLINE_READ_LOCK_BH is not set
147# CONFIG_INLINE_READ_LOCK_IRQ is not set
148# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
149CONFIG_INLINE_READ_UNLOCK=y
150# CONFIG_INLINE_READ_UNLOCK_BH is not set
151CONFIG_INLINE_READ_UNLOCK_IRQ=y
152# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
153# CONFIG_INLINE_WRITE_TRYLOCK is not set
154# CONFIG_INLINE_WRITE_LOCK is not set
155# CONFIG_INLINE_WRITE_LOCK_BH is not set
156# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
157# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
158CONFIG_INLINE_WRITE_UNLOCK=y
159# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
160CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
161# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
162# CONFIG_MUTEX_SPIN_ON_OWNER is not set
163CONFIG_FREEZER=y
164
165#
166# System Type
167#
168CONFIG_MMU=y
169# CONFIG_ARCH_AAEC2000 is not set
170# CONFIG_ARCH_INTEGRATOR is not set
171# CONFIG_ARCH_REALVIEW is not set
172# CONFIG_ARCH_VERSATILE is not set
173# CONFIG_ARCH_AT91 is not set
174# CONFIG_ARCH_CLPS711X is not set
175# CONFIG_ARCH_GEMINI is not set
176# CONFIG_ARCH_EBSA110 is not set
177# CONFIG_ARCH_EP93XX is not set
178# CONFIG_ARCH_FOOTBRIDGE is not set
179CONFIG_ARCH_MXC=y
180# CONFIG_ARCH_STMP3XXX is not set
181# CONFIG_ARCH_NETX is not set
182# CONFIG_ARCH_H720X is not set
183# CONFIG_ARCH_NOMADIK is not set
184# CONFIG_ARCH_IOP13XX is not set
185# CONFIG_ARCH_IOP32X is not set
186# CONFIG_ARCH_IOP33X is not set
187# CONFIG_ARCH_IXP23XX is not set
188# CONFIG_ARCH_IXP2000 is not set
189# CONFIG_ARCH_IXP4XX is not set
190# CONFIG_ARCH_L7200 is not set
191# CONFIG_ARCH_DOVE is not set
192# CONFIG_ARCH_KIRKWOOD is not set
193# CONFIG_ARCH_LOKI is not set
194# CONFIG_ARCH_MV78XX0 is not set
195# CONFIG_ARCH_ORION5X is not set
196# CONFIG_ARCH_MMP is not set
197# CONFIG_ARCH_KS8695 is not set
198# CONFIG_ARCH_NS9XXX is not set
199# CONFIG_ARCH_W90X900 is not set
200# CONFIG_ARCH_PNX4008 is not set
201# CONFIG_ARCH_PXA is not set
202# CONFIG_ARCH_MSM is not set
203# CONFIG_ARCH_RPC is not set
204# CONFIG_ARCH_SA1100 is not set
205# CONFIG_ARCH_S3C2410 is not set
206# CONFIG_ARCH_S3C64XX is not set
207# CONFIG_ARCH_S5PC1XX is not set
208# CONFIG_ARCH_SHARK is not set
209# CONFIG_ARCH_LH7A40X is not set
210# CONFIG_ARCH_U300 is not set
211# CONFIG_ARCH_DAVINCI is not set
212# CONFIG_ARCH_OMAP is not set
213# CONFIG_ARCH_BCMRING is not set
214# CONFIG_ARCH_U8500 is not set
215
216#
217# Freescale MXC Implementations
218#
219# CONFIG_ARCH_MX1 is not set
220# CONFIG_ARCH_MX2 is not set
221# CONFIG_ARCH_MX25 is not set
222# CONFIG_ARCH_MX3 is not set
223# CONFIG_ARCH_MXC91231 is not set
224CONFIG_ARCH_MX5=y
225CONFIG_ARCH_MX51=y
226
227#
228# MX5 platforms:
229#
230CONFIG_MACH_MX51_BABBAGE=y
231# CONFIG_MXC_IRQ_PRIOR is not set
232CONFIG_MXC_TZIC=y
233# CONFIG_MXC_PWM is not set
234CONFIG_ARCH_MXC_IOMUX_V3=y
235
236#
237# Processor Type
238#
239CONFIG_CPU_32v6K=y
240CONFIG_CPU_V7=y
241CONFIG_CPU_32v7=y
242CONFIG_CPU_ABRT_EV7=y
243CONFIG_CPU_PABRT_V7=y
244CONFIG_CPU_CACHE_V7=y
245CONFIG_CPU_CACHE_VIPT=y
246CONFIG_CPU_COPY_V6=y
247CONFIG_CPU_TLB_V7=y
248CONFIG_CPU_HAS_ASID=y
249CONFIG_CPU_CP15=y
250CONFIG_CPU_CP15_MMU=y
251
252#
253# Processor Features
254#
255CONFIG_ARM_THUMB=y
256# CONFIG_ARM_THUMBEE is not set
257# CONFIG_CPU_ICACHE_DISABLE is not set
258# CONFIG_CPU_DCACHE_DISABLE is not set
259# CONFIG_CPU_BPREDICT_DISABLE is not set
260CONFIG_HAS_TLS_REG=y
261CONFIG_ARM_L1_CACHE_SHIFT=5
262# CONFIG_ARM_ERRATA_430973 is not set
263# CONFIG_ARM_ERRATA_458693 is not set
264# CONFIG_ARM_ERRATA_460075 is not set
265CONFIG_COMMON_CLKDEV=y
266
267#
268# Bus support
269#
270# CONFIG_PCI_SYSCALL is not set
271# CONFIG_ARCH_SUPPORTS_MSI is not set
272# CONFIG_PCCARD is not set
273
274#
275# Kernel Features
276#
277CONFIG_TICK_ONESHOT=y
278CONFIG_NO_HZ=y
279CONFIG_HIGH_RES_TIMERS=y
280CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
281CONFIG_VMSPLIT_3G=y
282# CONFIG_VMSPLIT_2G is not set
283# CONFIG_VMSPLIT_1G is not set
284CONFIG_PAGE_OFFSET=0xC0000000
285# CONFIG_PREEMPT_NONE is not set
286CONFIG_PREEMPT_VOLUNTARY=y
287# CONFIG_PREEMPT is not set
288CONFIG_HZ=100
289# CONFIG_THUMB2_KERNEL is not set
290CONFIG_AEABI=y
291# CONFIG_OABI_COMPAT is not set
292# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
293# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
294# CONFIG_HIGHMEM is not set
295CONFIG_SELECT_MEMORY_MODEL=y
296CONFIG_FLATMEM_MANUAL=y
297# CONFIG_DISCONTIGMEM_MANUAL is not set
298# CONFIG_SPARSEMEM_MANUAL is not set
299CONFIG_FLATMEM=y
300CONFIG_FLAT_NODE_MEM_MAP=y
301CONFIG_PAGEFLAGS_EXTENDED=y
302CONFIG_SPLIT_PTLOCK_CPUS=4
303# CONFIG_PHYS_ADDR_T_64BIT is not set
304CONFIG_ZONE_DMA_FLAG=0
305CONFIG_VIRT_TO_BUS=y
306# CONFIG_KSM is not set
307CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
308CONFIG_ALIGNMENT_TRAP=y
309# CONFIG_UACCESS_WITH_MEMCPY is not set
310
311#
312# Boot options
313#
314CONFIG_ZBOOT_ROM_TEXT=0
315CONFIG_ZBOOT_ROM_BSS=0
316CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/nfs nfsroot=192.168.0.101:/shared/nfs ip=dhcp"
317# CONFIG_XIP_KERNEL is not set
318# CONFIG_KEXEC is not set
319
320#
321# CPU Power Management
322#
323# CONFIG_CPU_IDLE is not set
324
325#
326# Floating point emulation
327#
328
329#
330# At least one emulation must be selected
331#
332CONFIG_VFP=y
333CONFIG_VFPv3=y
334CONFIG_NEON=y
335
336#
337# Userspace binary formats
338#
339CONFIG_BINFMT_ELF=y
340# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
341CONFIG_HAVE_AOUT=y
342# CONFIG_BINFMT_AOUT is not set
343CONFIG_BINFMT_MISC=m
344
345#
346# Power management options
347#
348CONFIG_PM=y
349CONFIG_PM_DEBUG=y
350# CONFIG_PM_VERBOSE is not set
351CONFIG_CAN_PM_TRACE=y
352CONFIG_PM_SLEEP=y
353CONFIG_SUSPEND=y
354CONFIG_PM_TEST_SUSPEND=y
355CONFIG_SUSPEND_FREEZER=y
356# CONFIG_APM_EMULATION is not set
357# CONFIG_PM_RUNTIME is not set
358CONFIG_ARCH_SUSPEND_POSSIBLE=y
359CONFIG_NET=y
360
361#
362# Networking options
363#
364CONFIG_PACKET=y
365CONFIG_PACKET_MMAP=y
366CONFIG_UNIX=y
367# CONFIG_NET_KEY is not set
368CONFIG_INET=y
369# CONFIG_IP_MULTICAST is not set
370# CONFIG_IP_ADVANCED_ROUTER is not set
371CONFIG_IP_FIB_HASH=y
372CONFIG_IP_PNP=y
373CONFIG_IP_PNP_DHCP=y
374# CONFIG_IP_PNP_BOOTP is not set
375# CONFIG_IP_PNP_RARP is not set
376# CONFIG_NET_IPIP is not set
377# CONFIG_NET_IPGRE is not set
378# CONFIG_ARPD is not set
379# CONFIG_SYN_COOKIES is not set
380# CONFIG_INET_AH is not set
381# CONFIG_INET_ESP is not set
382# CONFIG_INET_IPCOMP is not set
383# CONFIG_INET_XFRM_TUNNEL is not set
384# CONFIG_INET_TUNNEL is not set
385# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
386# CONFIG_INET_XFRM_MODE_TUNNEL is not set
387# CONFIG_INET_XFRM_MODE_BEET is not set
388# CONFIG_INET_LRO is not set
389CONFIG_INET_DIAG=y
390CONFIG_INET_TCP_DIAG=y
391# CONFIG_TCP_CONG_ADVANCED is not set
392CONFIG_TCP_CONG_CUBIC=y
393CONFIG_DEFAULT_TCP_CONG="cubic"
394# CONFIG_TCP_MD5SIG is not set
395# CONFIG_IPV6 is not set
396# CONFIG_NETWORK_SECMARK is not set
397# CONFIG_NETFILTER is not set
398# CONFIG_IP_DCCP is not set
399# CONFIG_IP_SCTP is not set
400# CONFIG_RDS is not set
401# CONFIG_TIPC is not set
402# CONFIG_ATM is not set
403# CONFIG_BRIDGE is not set
404# CONFIG_NET_DSA is not set
405# CONFIG_VLAN_8021Q is not set
406# CONFIG_DECNET is not set
407# CONFIG_LLC2 is not set
408# CONFIG_IPX is not set
409# CONFIG_ATALK is not set
410# CONFIG_X25 is not set
411# CONFIG_LAPB is not set
412# CONFIG_ECONET is not set
413# CONFIG_WAN_ROUTER is not set
414# CONFIG_PHONET is not set
415# CONFIG_IEEE802154 is not set
416# CONFIG_NET_SCHED is not set
417# CONFIG_DCB is not set
418
419#
420# Network testing
421#
422# CONFIG_NET_PKTGEN is not set
423# CONFIG_HAMRADIO is not set
424# CONFIG_CAN is not set
425# CONFIG_IRDA is not set
426# CONFIG_BT is not set
427# CONFIG_AF_RXRPC is not set
428# CONFIG_WIRELESS is not set
429# CONFIG_WIMAX is not set
430# CONFIG_RFKILL is not set
431# CONFIG_NET_9P is not set
432
433#
434# Device Drivers
435#
436
437#
438# Generic Driver Options
439#
440CONFIG_UEVENT_HELPER_PATH=""
441# CONFIG_STANDALONE is not set
442CONFIG_PREVENT_FIRMWARE_BUILD=y
443CONFIG_FW_LOADER=y
444CONFIG_FIRMWARE_IN_KERNEL=y
445CONFIG_EXTRA_FIRMWARE=""
446# CONFIG_DEBUG_DRIVER is not set
447# CONFIG_DEBUG_DEVRES is not set
448# CONFIG_SYS_HYPERVISOR is not set
449CONFIG_CONNECTOR=y
450CONFIG_PROC_EVENTS=y
451# CONFIG_MTD is not set
452# CONFIG_PARPORT is not set
453CONFIG_BLK_DEV=y
454# CONFIG_BLK_DEV_COW_COMMON is not set
455CONFIG_BLK_DEV_LOOP=y
456# CONFIG_BLK_DEV_CRYPTOLOOP is not set
457# CONFIG_BLK_DEV_DRBD is not set
458# CONFIG_BLK_DEV_NBD is not set
459CONFIG_BLK_DEV_RAM=y
460CONFIG_BLK_DEV_RAM_COUNT=16
461CONFIG_BLK_DEV_RAM_SIZE=65536
462# CONFIG_BLK_DEV_XIP is not set
463# CONFIG_CDROM_PKTCDVD is not set
464# CONFIG_ATA_OVER_ETH is not set
465# CONFIG_MG_DISK is not set
466# CONFIG_MISC_DEVICES is not set
467CONFIG_HAVE_IDE=y
468# CONFIG_IDE is not set
469
470#
471# SCSI device support
472#
473# CONFIG_RAID_ATTRS is not set
474CONFIG_SCSI=y
475CONFIG_SCSI_DMA=y
476# CONFIG_SCSI_TGT is not set
477# CONFIG_SCSI_NETLINK is not set
478# CONFIG_SCSI_PROC_FS is not set
479
480#
481# SCSI support type (disk, tape, CD-ROM)
482#
483CONFIG_BLK_DEV_SD=y
484# CONFIG_CHR_DEV_ST is not set
485# CONFIG_CHR_DEV_OSST is not set
486# CONFIG_BLK_DEV_SR is not set
487# CONFIG_CHR_DEV_SG is not set
488# CONFIG_CHR_DEV_SCH is not set
489CONFIG_SCSI_MULTI_LUN=y
490CONFIG_SCSI_CONSTANTS=y
491CONFIG_SCSI_LOGGING=y
492CONFIG_SCSI_SCAN_ASYNC=y
493CONFIG_SCSI_WAIT_SCAN=m
494
495#
496# SCSI Transports
497#
498# CONFIG_SCSI_SPI_ATTRS is not set
499# CONFIG_SCSI_FC_ATTRS is not set
500# CONFIG_SCSI_ISCSI_ATTRS is not set
501# CONFIG_SCSI_SAS_LIBSAS is not set
502# CONFIG_SCSI_SRP_ATTRS is not set
503# CONFIG_SCSI_LOWLEVEL is not set
504# CONFIG_SCSI_DH is not set
505# CONFIG_SCSI_OSD_INITIATOR is not set
506CONFIG_ATA=m
507# CONFIG_ATA_NONSTANDARD is not set
508CONFIG_ATA_VERBOSE_ERROR=y
509CONFIG_SATA_PMP=y
510CONFIG_ATA_SFF=y
511# CONFIG_SATA_MV is not set
512# CONFIG_PATA_PLATFORM is not set
513# CONFIG_MD is not set
514CONFIG_NETDEVICES=y
515# CONFIG_DUMMY is not set
516# CONFIG_BONDING is not set
517# CONFIG_MACVLAN is not set
518# CONFIG_EQUALIZER is not set
519# CONFIG_TUN is not set
520# CONFIG_VETH is not set
521CONFIG_PHYLIB=y
522
523#
524# MII PHY device drivers
525#
526CONFIG_MARVELL_PHY=y
527CONFIG_DAVICOM_PHY=y
528CONFIG_QSEMI_PHY=y
529CONFIG_LXT_PHY=y
530CONFIG_CICADA_PHY=y
531CONFIG_VITESSE_PHY=y
532CONFIG_SMSC_PHY=y
533CONFIG_BROADCOM_PHY=y
534CONFIG_ICPLUS_PHY=y
535CONFIG_REALTEK_PHY=y
536CONFIG_NATIONAL_PHY=y
537CONFIG_STE10XP=y
538CONFIG_LSI_ET1011C_PHY=y
539CONFIG_FIXED_PHY=y
540CONFIG_MDIO_BITBANG=y
541CONFIG_MDIO_GPIO=y
542CONFIG_NET_ETHERNET=y
543CONFIG_MII=m
544# CONFIG_AX88796 is not set
545# CONFIG_SMC91X is not set
546# CONFIG_DM9000 is not set
547# CONFIG_ETHOC is not set
548# CONFIG_SMC911X is not set
549# CONFIG_SMSC911X is not set
550# CONFIG_DNET is not set
551# CONFIG_IBM_NEW_EMAC_ZMII is not set
552# CONFIG_IBM_NEW_EMAC_RGMII is not set
553# CONFIG_IBM_NEW_EMAC_TAH is not set
554# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
555# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
556# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
557# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
558# CONFIG_B44 is not set
559# CONFIG_KS8842 is not set
560# CONFIG_KS8851_MLL is not set
561CONFIG_FEC=y
562# CONFIG_FEC2 is not set
563# CONFIG_NETDEV_1000 is not set
564# CONFIG_NETDEV_10000 is not set
565# CONFIG_WLAN is not set
566
567#
568# Enable WiMAX (Networking options) to see the WiMAX drivers
569#
570# CONFIG_WAN is not set
571# CONFIG_PPP is not set
572# CONFIG_SLIP is not set
573# CONFIG_NETCONSOLE is not set
574# CONFIG_NETPOLL is not set
575# CONFIG_NET_POLL_CONTROLLER is not set
576# CONFIG_ISDN is not set
577# CONFIG_PHONE is not set
578
579#
580# Input device support
581#
582CONFIG_INPUT=y
583CONFIG_INPUT_FF_MEMLESS=m
584# CONFIG_INPUT_POLLDEV is not set
585# CONFIG_INPUT_SPARSEKMAP is not set
586
587#
588# Userland interfaces
589#
590CONFIG_INPUT_MOUSEDEV=y
591# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
592CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
593CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
594# CONFIG_INPUT_JOYDEV is not set
595CONFIG_INPUT_EVDEV=y
596CONFIG_INPUT_EVBUG=m
597
598#
599# Input Device Drivers
600#
601CONFIG_INPUT_KEYBOARD=y
602# CONFIG_KEYBOARD_ADP5588 is not set
603CONFIG_KEYBOARD_ATKBD=y
604# CONFIG_QT2160 is not set
605# CONFIG_KEYBOARD_LKKBD is not set
606# CONFIG_KEYBOARD_GPIO is not set
607# CONFIG_KEYBOARD_MATRIX is not set
608# CONFIG_KEYBOARD_LM8323 is not set
609# CONFIG_KEYBOARD_MAX7359 is not set
610# CONFIG_KEYBOARD_NEWTON is not set
611# CONFIG_KEYBOARD_OPENCORES is not set
612# CONFIG_KEYBOARD_STOWAWAY is not set
613# CONFIG_KEYBOARD_SUNKBD is not set
614# CONFIG_KEYBOARD_XTKBD is not set
615CONFIG_INPUT_MOUSE=y
616CONFIG_MOUSE_PS2=m
617CONFIG_MOUSE_PS2_ALPS=y
618CONFIG_MOUSE_PS2_LOGIPS2PP=y
619CONFIG_MOUSE_PS2_SYNAPTICS=y
620CONFIG_MOUSE_PS2_TRACKPOINT=y
621CONFIG_MOUSE_PS2_ELANTECH=y
622# CONFIG_MOUSE_PS2_SENTELIC is not set
623# CONFIG_MOUSE_PS2_TOUCHKIT is not set
624# CONFIG_MOUSE_SERIAL is not set
625# CONFIG_MOUSE_VSXXXAA is not set
626# CONFIG_MOUSE_GPIO is not set
627# CONFIG_MOUSE_SYNAPTICS_I2C is not set
628# CONFIG_INPUT_JOYSTICK is not set
629# CONFIG_INPUT_TABLET is not set
630# CONFIG_INPUT_TOUCHSCREEN is not set
631# CONFIG_INPUT_MISC is not set
632
633#
634# Hardware I/O ports
635#
636CONFIG_SERIO=y
637CONFIG_SERIO_SERPORT=m
638CONFIG_SERIO_LIBPS2=y
639# CONFIG_SERIO_RAW is not set
640# CONFIG_SERIO_ALTERA_PS2 is not set
641# CONFIG_GAMEPORT is not set
642
643#
644# Character devices
645#
646CONFIG_VT=y
647CONFIG_CONSOLE_TRANSLATIONS=y
648CONFIG_VT_CONSOLE=y
649CONFIG_HW_CONSOLE=y
650CONFIG_VT_HW_CONSOLE_BINDING=y
651# CONFIG_DEVKMEM is not set
652# CONFIG_SERIAL_NONSTANDARD is not set
653
654#
655# Serial drivers
656#
657# CONFIG_SERIAL_8250 is not set
658
659#
660# Non-8250 serial port support
661#
662CONFIG_SERIAL_IMX=y
663CONFIG_SERIAL_IMX_CONSOLE=y
664CONFIG_SERIAL_CORE=y
665CONFIG_SERIAL_CORE_CONSOLE=y
666CONFIG_UNIX98_PTYS=y
667# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
668# CONFIG_LEGACY_PTYS is not set
669# CONFIG_IPMI_HANDLER is not set
670CONFIG_HW_RANDOM=y
671# CONFIG_HW_RANDOM_TIMERIOMEM is not set
672# CONFIG_R3964 is not set
673# CONFIG_RAW_DRIVER is not set
674# CONFIG_TCG_TPM is not set
675CONFIG_I2C=y
676CONFIG_I2C_BOARDINFO=y
677# CONFIG_I2C_COMPAT is not set
678CONFIG_I2C_CHARDEV=m
679# CONFIG_I2C_HELPER_AUTO is not set
680
681#
682# I2C Algorithms
683#
684CONFIG_I2C_ALGOBIT=m
685CONFIG_I2C_ALGOPCF=m
686CONFIG_I2C_ALGOPCA=m
687
688#
689# I2C Hardware Bus support
690#
691
692#
693# I2C system bus drivers (mostly embedded / system-on-chip)
694#
695# CONFIG_I2C_DESIGNWARE is not set
696# CONFIG_I2C_GPIO is not set
697# CONFIG_I2C_IMX is not set
698# CONFIG_I2C_OCORES is not set
699# CONFIG_I2C_SIMTEC is not set
700
701#
702# External I2C/SMBus adapter drivers
703#
704# CONFIG_I2C_PARPORT_LIGHT is not set
705# CONFIG_I2C_TAOS_EVM is not set
706
707#
708# Other I2C/SMBus bus drivers
709#
710# CONFIG_I2C_PCA_PLATFORM is not set
711# CONFIG_I2C_STUB is not set
712
713#
714# Miscellaneous I2C Chip support
715#
716# CONFIG_SENSORS_TSL2550 is not set
717# CONFIG_I2C_DEBUG_CORE is not set
718# CONFIG_I2C_DEBUG_ALGO is not set
719# CONFIG_I2C_DEBUG_BUS is not set
720# CONFIG_I2C_DEBUG_CHIP is not set
721# CONFIG_SPI is not set
722
723#
724# PPS support
725#
726# CONFIG_PPS is not set
727CONFIG_ARCH_REQUIRE_GPIOLIB=y
728CONFIG_GPIOLIB=y
729# CONFIG_DEBUG_GPIO is not set
730CONFIG_GPIO_SYSFS=y
731
732#
733# Memory mapped GPIO expanders:
734#
735
736#
737# I2C GPIO expanders:
738#
739# CONFIG_GPIO_MAX732X is not set
740# CONFIG_GPIO_PCA953X is not set
741# CONFIG_GPIO_PCF857X is not set
742# CONFIG_GPIO_ADP5588 is not set
743
744#
745# PCI GPIO expanders:
746#
747
748#
749# SPI GPIO expanders:
750#
751
752#
753# AC97 GPIO expanders:
754#
755# CONFIG_W1 is not set
756# CONFIG_POWER_SUPPLY is not set
757# CONFIG_HWMON is not set
758# CONFIG_THERMAL is not set
759# CONFIG_WATCHDOG is not set
760CONFIG_SSB_POSSIBLE=y
761
762#
763# Sonics Silicon Backplane
764#
765# CONFIG_SSB is not set
766
767#
768# Multifunction device drivers
769#
770# CONFIG_MFD_CORE is not set
771# CONFIG_MFD_SM501 is not set
772# CONFIG_MFD_ASIC3 is not set
773# CONFIG_HTC_EGPIO is not set
774# CONFIG_HTC_PASIC3 is not set
775# CONFIG_TPS65010 is not set
776# CONFIG_TWL4030_CORE is not set
777# CONFIG_MFD_TMIO is not set
778# CONFIG_MFD_T7L66XB is not set
779# CONFIG_MFD_TC6387XB is not set
780# CONFIG_MFD_TC6393XB is not set
781# CONFIG_PMIC_DA903X is not set
782# CONFIG_PMIC_ADP5520 is not set
783# CONFIG_MFD_WM8400 is not set
784# CONFIG_MFD_WM831X is not set
785# CONFIG_MFD_WM8350_I2C is not set
786# CONFIG_MFD_PCF50633 is not set
787# CONFIG_AB3100_CORE is not set
788# CONFIG_MFD_88PM8607 is not set
789# CONFIG_REGULATOR is not set
790# CONFIG_MEDIA_SUPPORT is not set
791
792#
793# Graphics support
794#
795# CONFIG_VGASTATE is not set
796# CONFIG_VIDEO_OUTPUT_CONTROL is not set
797# CONFIG_FB is not set
798# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
799
800#
801# Display device support
802#
803# CONFIG_DISPLAY_SUPPORT is not set
804
805#
806# Console display driver support
807#
808# CONFIG_VGA_CONSOLE is not set
809CONFIG_DUMMY_CONSOLE=y
810# CONFIG_SOUND is not set
811# CONFIG_HID_SUPPORT is not set
812# CONFIG_USB_SUPPORT is not set
813CONFIG_MMC=y
814# CONFIG_MMC_DEBUG is not set
815# CONFIG_MMC_UNSAFE_RESUME is not set
816
817#
818# MMC/SD/SDIO Card Drivers
819#
820CONFIG_MMC_BLOCK=m
821CONFIG_MMC_BLOCK_BOUNCE=y
822# CONFIG_SDIO_UART is not set
823# CONFIG_MMC_TEST is not set
824
825#
826# MMC/SD/SDIO Host Controller Drivers
827#
828CONFIG_MMC_SDHCI=m
829# CONFIG_MMC_SDHCI_PLTFM is not set
830# CONFIG_MMC_AT91 is not set
831# CONFIG_MMC_ATMELMCI is not set
832# CONFIG_MMC_MXC is not set
833# CONFIG_MEMSTICK is not set
834CONFIG_NEW_LEDS=y
835CONFIG_LEDS_CLASS=m
836
837#
838# LED drivers
839#
840# CONFIG_LEDS_PCA9532 is not set
841# CONFIG_LEDS_GPIO is not set
842# CONFIG_LEDS_LP3944 is not set
843# CONFIG_LEDS_PCA955X is not set
844# CONFIG_LEDS_BD2802 is not set
845# CONFIG_LEDS_LT3593 is not set
846
847#
848# LED Triggers
849#
850# CONFIG_LEDS_TRIGGERS is not set
851# CONFIG_ACCESSIBILITY is not set
852CONFIG_RTC_LIB=y
853CONFIG_RTC_CLASS=y
854CONFIG_RTC_HCTOSYS=y
855CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
856# CONFIG_RTC_DEBUG is not set
857
858#
859# RTC interfaces
860#
861CONFIG_RTC_INTF_SYSFS=y
862CONFIG_RTC_INTF_PROC=y
863CONFIG_RTC_INTF_DEV=y
864CONFIG_RTC_INTF_DEV_UIE_EMUL=y
865# CONFIG_RTC_DRV_TEST is not set
866
867#
868# I2C RTC drivers
869#
870# CONFIG_RTC_DRV_DS1307 is not set
871# CONFIG_RTC_DRV_DS1374 is not set
872# CONFIG_RTC_DRV_DS1672 is not set
873# CONFIG_RTC_DRV_MAX6900 is not set
874# CONFIG_RTC_DRV_RS5C372 is not set
875# CONFIG_RTC_DRV_ISL1208 is not set
876# CONFIG_RTC_DRV_X1205 is not set
877# CONFIG_RTC_DRV_PCF8563 is not set
878# CONFIG_RTC_DRV_PCF8583 is not set
879# CONFIG_RTC_DRV_M41T80 is not set
880# CONFIG_RTC_DRV_BQ32K is not set
881# CONFIG_RTC_DRV_S35390A is not set
882# CONFIG_RTC_DRV_FM3130 is not set
883# CONFIG_RTC_DRV_RX8581 is not set
884# CONFIG_RTC_DRV_RX8025 is not set
885
886#
887# SPI RTC drivers
888#
889
890#
891# Platform RTC drivers
892#
893# CONFIG_RTC_DRV_CMOS is not set
894# CONFIG_RTC_DRV_DS1286 is not set
895# CONFIG_RTC_DRV_DS1511 is not set
896# CONFIG_RTC_DRV_DS1553 is not set
897# CONFIG_RTC_DRV_DS1742 is not set
898# CONFIG_RTC_DRV_STK17TA8 is not set
899# CONFIG_RTC_DRV_M48T86 is not set
900# CONFIG_RTC_DRV_M48T35 is not set
901# CONFIG_RTC_DRV_M48T59 is not set
902# CONFIG_RTC_DRV_MSM6242 is not set
903# CONFIG_RTC_MXC is not set
904# CONFIG_RTC_DRV_BQ4802 is not set
905# CONFIG_RTC_DRV_RP5C01 is not set
906# CONFIG_RTC_DRV_V3020 is not set
907
908#
909# on-CPU RTC drivers
910#
911# CONFIG_DMADEVICES is not set
912# CONFIG_AUXDISPLAY is not set
913# CONFIG_UIO is not set
914
915#
916# TI VLYNQ
917#
918# CONFIG_STAGING is not set
919
920#
921# File systems
922#
923CONFIG_EXT2_FS=y
924CONFIG_EXT2_FS_XATTR=y
925CONFIG_EXT2_FS_POSIX_ACL=y
926CONFIG_EXT2_FS_SECURITY=y
927# CONFIG_EXT2_FS_XIP is not set
928CONFIG_EXT3_FS=y
929CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
930CONFIG_EXT3_FS_XATTR=y
931CONFIG_EXT3_FS_POSIX_ACL=y
932CONFIG_EXT3_FS_SECURITY=y
933CONFIG_EXT4_FS=y
934CONFIG_EXT4_FS_XATTR=y
935CONFIG_EXT4_FS_POSIX_ACL=y
936CONFIG_EXT4_FS_SECURITY=y
937# CONFIG_EXT4_DEBUG is not set
938CONFIG_JBD=y
939# CONFIG_JBD_DEBUG is not set
940CONFIG_JBD2=y
941# CONFIG_JBD2_DEBUG is not set
942CONFIG_FS_MBCACHE=y
943# CONFIG_REISERFS_FS is not set
944# CONFIG_JFS_FS is not set
945CONFIG_FS_POSIX_ACL=y
946# CONFIG_XFS_FS is not set
947# CONFIG_OCFS2_FS is not set
948# CONFIG_BTRFS_FS is not set
949# CONFIG_NILFS2_FS is not set
950CONFIG_FILE_LOCKING=y
951CONFIG_FSNOTIFY=y
952CONFIG_DNOTIFY=y
953CONFIG_INOTIFY=y
954CONFIG_INOTIFY_USER=y
955CONFIG_QUOTA=y
956CONFIG_QUOTA_NETLINK_INTERFACE=y
957# CONFIG_PRINT_QUOTA_WARNING is not set
958# CONFIG_QFMT_V1 is not set
959# CONFIG_QFMT_V2 is not set
960CONFIG_QUOTACTL=y
961CONFIG_AUTOFS_FS=y
962CONFIG_AUTOFS4_FS=y
963CONFIG_FUSE_FS=y
964# CONFIG_CUSE is not set
965
966#
967# Caches
968#
969# CONFIG_FSCACHE is not set
970
971#
972# CD-ROM/DVD Filesystems
973#
974CONFIG_ISO9660_FS=m
975CONFIG_JOLIET=y
976CONFIG_ZISOFS=y
977CONFIG_UDF_FS=m
978CONFIG_UDF_NLS=y
979
980#
981# DOS/FAT/NT Filesystems
982#
983CONFIG_FAT_FS=y
984CONFIG_MSDOS_FS=m
985CONFIG_VFAT_FS=y
986CONFIG_FAT_DEFAULT_CODEPAGE=437
987CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
988# CONFIG_NTFS_FS is not set
989
990#
991# Pseudo filesystems
992#
993CONFIG_PROC_FS=y
994CONFIG_PROC_SYSCTL=y
995CONFIG_PROC_PAGE_MONITOR=y
996CONFIG_SYSFS=y
997# CONFIG_TMPFS is not set
998# CONFIG_HUGETLB_PAGE is not set
999CONFIG_CONFIGFS_FS=m
1000CONFIG_MISC_FILESYSTEMS=y
1001# CONFIG_ADFS_FS is not set
1002# CONFIG_AFFS_FS is not set
1003# CONFIG_ECRYPT_FS is not set
1004# CONFIG_HFS_FS is not set
1005# CONFIG_HFSPLUS_FS is not set
1006# CONFIG_BEFS_FS is not set
1007# CONFIG_BFS_FS is not set
1008# CONFIG_EFS_FS is not set
1009# CONFIG_CRAMFS is not set
1010# CONFIG_SQUASHFS is not set
1011# CONFIG_VXFS_FS is not set
1012# CONFIG_MINIX_FS is not set
1013# CONFIG_OMFS_FS is not set
1014# CONFIG_HPFS_FS is not set
1015# CONFIG_QNX4FS_FS is not set
1016# CONFIG_ROMFS_FS is not set
1017# CONFIG_SYSV_FS is not set
1018# CONFIG_UFS_FS is not set
1019CONFIG_NETWORK_FILESYSTEMS=y
1020CONFIG_NFS_FS=y
1021CONFIG_NFS_V3=y
1022CONFIG_NFS_V3_ACL=y
1023CONFIG_NFS_V4=y
1024# CONFIG_NFS_V4_1 is not set
1025CONFIG_ROOT_NFS=y
1026# CONFIG_NFSD is not set
1027CONFIG_LOCKD=y
1028CONFIG_LOCKD_V4=y
1029CONFIG_NFS_ACL_SUPPORT=y
1030CONFIG_NFS_COMMON=y
1031CONFIG_SUNRPC=y
1032CONFIG_SUNRPC_GSS=y
1033CONFIG_RPCSEC_GSS_KRB5=y
1034# CONFIG_RPCSEC_GSS_SPKM3 is not set
1035# CONFIG_SMB_FS is not set
1036# CONFIG_CIFS is not set
1037# CONFIG_NCP_FS is not set
1038# CONFIG_CODA_FS is not set
1039# CONFIG_AFS_FS is not set
1040
1041#
1042# Partition Types
1043#
1044# CONFIG_PARTITION_ADVANCED is not set
1045CONFIG_MSDOS_PARTITION=y
1046CONFIG_NLS=y
1047CONFIG_NLS_DEFAULT="cp437"
1048CONFIG_NLS_CODEPAGE_437=y
1049# CONFIG_NLS_CODEPAGE_737 is not set
1050# CONFIG_NLS_CODEPAGE_775 is not set
1051# CONFIG_NLS_CODEPAGE_850 is not set
1052# CONFIG_NLS_CODEPAGE_852 is not set
1053# CONFIG_NLS_CODEPAGE_855 is not set
1054# CONFIG_NLS_CODEPAGE_857 is not set
1055# CONFIG_NLS_CODEPAGE_860 is not set
1056# CONFIG_NLS_CODEPAGE_861 is not set
1057# CONFIG_NLS_CODEPAGE_862 is not set
1058# CONFIG_NLS_CODEPAGE_863 is not set
1059# CONFIG_NLS_CODEPAGE_864 is not set
1060# CONFIG_NLS_CODEPAGE_865 is not set
1061# CONFIG_NLS_CODEPAGE_866 is not set
1062# CONFIG_NLS_CODEPAGE_869 is not set
1063# CONFIG_NLS_CODEPAGE_936 is not set
1064# CONFIG_NLS_CODEPAGE_950 is not set
1065# CONFIG_NLS_CODEPAGE_932 is not set
1066# CONFIG_NLS_CODEPAGE_949 is not set
1067# CONFIG_NLS_CODEPAGE_874 is not set
1068# CONFIG_NLS_ISO8859_8 is not set
1069# CONFIG_NLS_CODEPAGE_1250 is not set
1070# CONFIG_NLS_CODEPAGE_1251 is not set
1071CONFIG_NLS_ASCII=y
1072CONFIG_NLS_ISO8859_1=m
1073# CONFIG_NLS_ISO8859_2 is not set
1074# CONFIG_NLS_ISO8859_3 is not set
1075# CONFIG_NLS_ISO8859_4 is not set
1076# CONFIG_NLS_ISO8859_5 is not set
1077# CONFIG_NLS_ISO8859_6 is not set
1078# CONFIG_NLS_ISO8859_7 is not set
1079# CONFIG_NLS_ISO8859_9 is not set
1080# CONFIG_NLS_ISO8859_13 is not set
1081# CONFIG_NLS_ISO8859_14 is not set
1082CONFIG_NLS_ISO8859_15=m
1083# CONFIG_NLS_KOI8_R is not set
1084# CONFIG_NLS_KOI8_U is not set
1085CONFIG_NLS_UTF8=y
1086# CONFIG_DLM is not set
1087
1088#
1089# Kernel hacking
1090#
1091# CONFIG_PRINTK_TIME is not set
1092CONFIG_ENABLE_WARN_DEPRECATED=y
1093CONFIG_ENABLE_MUST_CHECK=y
1094CONFIG_FRAME_WARN=1024
1095CONFIG_MAGIC_SYSRQ=y
1096# CONFIG_STRIP_ASM_SYMS is not set
1097# CONFIG_UNUSED_SYMBOLS is not set
1098CONFIG_DEBUG_FS=y
1099# CONFIG_HEADERS_CHECK is not set
1100CONFIG_DEBUG_KERNEL=y
1101# CONFIG_DEBUG_SHIRQ is not set
1102# CONFIG_DETECT_SOFTLOCKUP is not set
1103# CONFIG_DETECT_HUNG_TASK is not set
1104# CONFIG_SCHED_DEBUG is not set
1105# CONFIG_SCHEDSTATS is not set
1106# CONFIG_TIMER_STATS is not set
1107# CONFIG_DEBUG_OBJECTS is not set
1108# CONFIG_DEBUG_KMEMLEAK is not set
1109# CONFIG_DEBUG_RT_MUTEXES is not set
1110# CONFIG_RT_MUTEX_TESTER is not set
1111# CONFIG_DEBUG_SPINLOCK is not set
1112# CONFIG_DEBUG_MUTEXES is not set
1113# CONFIG_DEBUG_LOCK_ALLOC is not set
1114# CONFIG_PROVE_LOCKING is not set
1115# CONFIG_LOCK_STAT is not set
1116# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1117# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1118# CONFIG_DEBUG_KOBJECT is not set
1119# CONFIG_DEBUG_BUGVERBOSE is not set
1120# CONFIG_DEBUG_INFO is not set
1121# CONFIG_DEBUG_VM is not set
1122# CONFIG_DEBUG_WRITECOUNT is not set
1123# CONFIG_DEBUG_MEMORY_INIT is not set
1124# CONFIG_DEBUG_LIST is not set
1125# CONFIG_DEBUG_SG is not set
1126# CONFIG_DEBUG_NOTIFIERS is not set
1127# CONFIG_DEBUG_CREDENTIALS is not set
1128CONFIG_FRAME_POINTER=y
1129# CONFIG_BOOT_PRINTK_DELAY is not set
1130# CONFIG_RCU_TORTURE_TEST is not set
1131# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1132# CONFIG_BACKTRACE_SELF_TEST is not set
1133# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1134# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
1135# CONFIG_FAULT_INJECTION is not set
1136# CONFIG_LATENCYTOP is not set
1137# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1138# CONFIG_PAGE_POISONING is not set
1139CONFIG_HAVE_FUNCTION_TRACER=y
1140CONFIG_TRACING_SUPPORT=y
1141# CONFIG_FTRACE is not set
1142# CONFIG_DYNAMIC_DEBUG is not set
1143# CONFIG_SAMPLES is not set
1144CONFIG_HAVE_ARCH_KGDB=y
1145# CONFIG_KGDB is not set
1146# CONFIG_ARM_UNWIND is not set
1147# CONFIG_DEBUG_USER is not set
1148# CONFIG_DEBUG_ERRORS is not set
1149# CONFIG_DEBUG_STACK_USAGE is not set
1150CONFIG_DEBUG_LL=y
1151CONFIG_EARLY_PRINTK=y
1152# CONFIG_DEBUG_ICEDCC is not set
1153# CONFIG_OC_ETM is not set
1154
1155#
1156# Security options
1157#
1158CONFIG_KEYS=y
1159# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
1160# CONFIG_SECURITY is not set
1161CONFIG_SECURITYFS=y
1162# CONFIG_DEFAULT_SECURITY_SELINUX is not set
1163# CONFIG_DEFAULT_SECURITY_SMACK is not set
1164# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1165CONFIG_DEFAULT_SECURITY_DAC=y
1166CONFIG_DEFAULT_SECURITY=""
1167CONFIG_CRYPTO=y
1168
1169#
1170# Crypto core or helper
1171#
1172CONFIG_CRYPTO_ALGAPI=y
1173CONFIG_CRYPTO_ALGAPI2=y
1174CONFIG_CRYPTO_AEAD2=y
1175CONFIG_CRYPTO_BLKCIPHER=y
1176CONFIG_CRYPTO_BLKCIPHER2=y
1177CONFIG_CRYPTO_HASH=y
1178CONFIG_CRYPTO_HASH2=y
1179CONFIG_CRYPTO_RNG2=y
1180CONFIG_CRYPTO_PCOMP=y
1181CONFIG_CRYPTO_MANAGER=y
1182CONFIG_CRYPTO_MANAGER2=y
1183# CONFIG_CRYPTO_GF128MUL is not set
1184# CONFIG_CRYPTO_NULL is not set
1185CONFIG_CRYPTO_WORKQUEUE=y
1186# CONFIG_CRYPTO_CRYPTD is not set
1187# CONFIG_CRYPTO_AUTHENC is not set
1188# CONFIG_CRYPTO_TEST is not set
1189
1190#
1191# Authenticated Encryption with Associated Data
1192#
1193# CONFIG_CRYPTO_CCM is not set
1194# CONFIG_CRYPTO_GCM is not set
1195# CONFIG_CRYPTO_SEQIV is not set
1196
1197#
1198# Block modes
1199#
1200CONFIG_CRYPTO_CBC=y
1201# CONFIG_CRYPTO_CTR is not set
1202# CONFIG_CRYPTO_CTS is not set
1203# CONFIG_CRYPTO_ECB is not set
1204# CONFIG_CRYPTO_LRW is not set
1205# CONFIG_CRYPTO_PCBC is not set
1206# CONFIG_CRYPTO_XTS is not set
1207
1208#
1209# Hash modes
1210#
1211# CONFIG_CRYPTO_HMAC is not set
1212# CONFIG_CRYPTO_XCBC is not set
1213# CONFIG_CRYPTO_VMAC is not set
1214
1215#
1216# Digest
1217#
1218CONFIG_CRYPTO_CRC32C=m
1219# CONFIG_CRYPTO_GHASH is not set
1220# CONFIG_CRYPTO_MD4 is not set
1221CONFIG_CRYPTO_MD5=y
1222# CONFIG_CRYPTO_MICHAEL_MIC is not set
1223# CONFIG_CRYPTO_RMD128 is not set
1224# CONFIG_CRYPTO_RMD160 is not set
1225# CONFIG_CRYPTO_RMD256 is not set
1226# CONFIG_CRYPTO_RMD320 is not set
1227# CONFIG_CRYPTO_SHA1 is not set
1228# CONFIG_CRYPTO_SHA256 is not set
1229# CONFIG_CRYPTO_SHA512 is not set
1230# CONFIG_CRYPTO_TGR192 is not set
1231# CONFIG_CRYPTO_WP512 is not set
1232
1233#
1234# Ciphers
1235#
1236# CONFIG_CRYPTO_AES is not set
1237# CONFIG_CRYPTO_ANUBIS is not set
1238# CONFIG_CRYPTO_ARC4 is not set
1239# CONFIG_CRYPTO_BLOWFISH is not set
1240# CONFIG_CRYPTO_CAMELLIA is not set
1241# CONFIG_CRYPTO_CAST5 is not set
1242# CONFIG_CRYPTO_CAST6 is not set
1243CONFIG_CRYPTO_DES=y
1244# CONFIG_CRYPTO_FCRYPT is not set
1245# CONFIG_CRYPTO_KHAZAD is not set
1246# CONFIG_CRYPTO_SALSA20 is not set
1247# CONFIG_CRYPTO_SEED is not set
1248# CONFIG_CRYPTO_SERPENT is not set
1249# CONFIG_CRYPTO_TEA is not set
1250# CONFIG_CRYPTO_TWOFISH is not set
1251
1252#
1253# Compression
1254#
1255CONFIG_CRYPTO_DEFLATE=y
1256# CONFIG_CRYPTO_ZLIB is not set
1257CONFIG_CRYPTO_LZO=y
1258
1259#
1260# Random Number Generation
1261#
1262# CONFIG_CRYPTO_ANSI_CPRNG is not set
1263# CONFIG_CRYPTO_HW is not set
1264# CONFIG_BINARY_PRINTF is not set
1265
1266#
1267# Library routines
1268#
1269CONFIG_BITREVERSE=y
1270CONFIG_RATIONAL=y
1271CONFIG_GENERIC_FIND_LAST_BIT=y
1272CONFIG_CRC_CCITT=m
1273CONFIG_CRC16=y
1274CONFIG_CRC_T10DIF=y
1275CONFIG_CRC_ITU_T=m
1276CONFIG_CRC32=y
1277CONFIG_CRC7=m
1278CONFIG_LIBCRC32C=m
1279CONFIG_ZLIB_INFLATE=y
1280CONFIG_ZLIB_DEFLATE=y
1281CONFIG_LZO_COMPRESS=y
1282CONFIG_LZO_DECOMPRESS=y
1283CONFIG_HAS_IOMEM=y
1284CONFIG_HAS_IOPORT=y
1285CONFIG_HAS_DMA=y
1286CONFIG_NLATTR=y
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
new file mode 100644
index 000000000000..1576d51e676c
--- /dev/null
+++ b/arch/arm/mach-mx5/Kconfig
@@ -0,0 +1,18 @@
1if ARCH_MX5
2
3config ARCH_MX51
4 bool
5 default y
6 select MXC_TZIC
7 select ARCH_MXC_IOMUX_V3
8
9comment "MX5 platforms:"
10
11config MACH_MX51_BABBAGE
12 bool "Support MX51 BABBAGE platforms"
13 help
14 Include support for MX51 Babbage platform, also known as MX51EVK in
15 u-boot. This includes specific configurations for the board and its
16 peripherals.
17
18endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
new file mode 100644
index 000000000000..bf23f869ef51
--- /dev/null
+++ b/arch/arm/mach-mx5/Makefile
@@ -0,0 +1,9 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6obj-y := cpu.o mm.o clock-mx51.o devices.o
7
8obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
9
diff --git a/arch/arm/mach-mx5/Makefile.boot b/arch/arm/mach-mx5/Makefile.boot
new file mode 100644
index 000000000000..9939a19d99a1
--- /dev/null
+++ b/arch/arm/mach-mx5/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x90008000
2params_phys-y := 0x90000100
3initrd_phys-y := 0x90800000
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
new file mode 100644
index 000000000000..d5ccb5f4f39c
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -0,0 +1,98 @@
1/*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/init.h>
14#include <linux/platform_device.h>
15
16#include <mach/common.h>
17#include <mach/hardware.h>
18#include <mach/imx-uart.h>
19#include <mach/iomux-mx51.h>
20
21#include <asm/irq.h>
22#include <asm/setup.h>
23#include <asm/mach-types.h>
24#include <asm/mach/arch.h>
25#include <asm/mach/time.h>
26
27#include "devices.h"
28
29static struct platform_device *devices[] __initdata = {
30 &mxc_fec_device,
31};
32
33static struct pad_desc mx51babbage_pads[] = {
34 /* UART1 */
35 MX51_PAD_UART1_RXD__UART1_RXD,
36 MX51_PAD_UART1_TXD__UART1_TXD,
37 MX51_PAD_UART1_RTS__UART1_RTS,
38 MX51_PAD_UART1_CTS__UART1_CTS,
39
40 /* UART2 */
41 MX51_PAD_UART2_RXD__UART2_RXD,
42 MX51_PAD_UART2_TXD__UART2_TXD,
43
44 /* UART3 */
45 MX51_PAD_EIM_D25__UART3_RXD,
46 MX51_PAD_EIM_D26__UART3_TXD,
47 MX51_PAD_EIM_D27__UART3_RTS,
48 MX51_PAD_EIM_D24__UART3_CTS,
49};
50
51/* Serial ports */
52#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
53static struct imxuart_platform_data uart_pdata = {
54 .flags = IMXUART_HAVE_RTSCTS,
55};
56
57static inline void mxc_init_imx_uart(void)
58{
59 mxc_register_device(&mxc_uart_device0, &uart_pdata);
60 mxc_register_device(&mxc_uart_device1, &uart_pdata);
61 mxc_register_device(&mxc_uart_device2, &uart_pdata);
62}
63#else /* !SERIAL_IMX */
64static inline void mxc_init_imx_uart(void)
65{
66}
67#endif /* SERIAL_IMX */
68
69/*
70 * Board specific initialization.
71 */
72static void __init mxc_board_init(void)
73{
74 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
75 ARRAY_SIZE(mx51babbage_pads));
76 mxc_init_imx_uart();
77 platform_add_devices(devices, ARRAY_SIZE(devices));
78}
79
80static void __init mx51_babbage_timer_init(void)
81{
82 mx51_clocks_init(32768, 24000000, 22579200, 24576000);
83}
84
85static struct sys_timer mxc_timer = {
86 .init = mx51_babbage_timer_init,
87};
88
89MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
90 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
91 .phys_io = MX51_AIPS1_BASE_ADDR,
92 .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
93 .boot_params = PHYS_OFFSET + 0x100,
94 .map_io = mx51_map_io,
95 .init_irq = mx51_init_irq,
96 .init_machine = mxc_board_init,
97 .timer = &mxc_timer,
98MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
new file mode 100644
index 000000000000..be90c03101cd
--- /dev/null
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -0,0 +1,825 @@
1/*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/mm.h>
14#include <linux/delay.h>
15#include <linux/clk.h>
16#include <linux/io.h>
17
18#include <asm/clkdev.h>
19
20#include <mach/hardware.h>
21#include <mach/common.h>
22#include <mach/clock.h>
23
24#include "crm_regs.h"
25
26/* External clock values passed-in by the board code */
27static unsigned long external_high_reference, external_low_reference;
28static unsigned long oscillator_reference, ckih2_reference;
29
30static struct clk osc_clk;
31static struct clk pll1_main_clk;
32static struct clk pll1_sw_clk;
33static struct clk pll2_sw_clk;
34static struct clk pll3_sw_clk;
35static struct clk lp_apm_clk;
36static struct clk periph_apm_clk;
37static struct clk ahb_clk;
38static struct clk ipg_clk;
39
40#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
41
42static int _clk_ccgr_enable(struct clk *clk)
43{
44 u32 reg;
45
46 reg = __raw_readl(clk->enable_reg);
47 reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift;
48 __raw_writel(reg, clk->enable_reg);
49
50 return 0;
51}
52
53static void _clk_ccgr_disable(struct clk *clk)
54{
55 u32 reg;
56 reg = __raw_readl(clk->enable_reg);
57 reg &= ~(MXC_CCM_CCGRx_MOD_OFF << clk->enable_shift);
58 __raw_writel(reg, clk->enable_reg);
59
60}
61
62static void _clk_ccgr_disable_inwait(struct clk *clk)
63{
64 u32 reg;
65
66 reg = __raw_readl(clk->enable_reg);
67 reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
68 reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift;
69 __raw_writel(reg, clk->enable_reg);
70}
71
72/*
73 * For the 4-to-1 muxed input clock
74 */
75static inline u32 _get_mux(struct clk *parent, struct clk *m0,
76 struct clk *m1, struct clk *m2, struct clk *m3)
77{
78 if (parent == m0)
79 return 0;
80 else if (parent == m1)
81 return 1;
82 else if (parent == m2)
83 return 2;
84 else if (parent == m3)
85 return 3;
86 else
87 BUG();
88
89 return -EINVAL;
90}
91
92static inline void __iomem *_get_pll_base(struct clk *pll)
93{
94 if (pll == &pll1_main_clk)
95 return MX51_DPLL1_BASE;
96 else if (pll == &pll2_sw_clk)
97 return MX51_DPLL2_BASE;
98 else if (pll == &pll3_sw_clk)
99 return MX51_DPLL3_BASE;
100 else
101 BUG();
102
103 return NULL;
104}
105
106static unsigned long clk_pll_get_rate(struct clk *clk)
107{
108 long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
109 unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
110 void __iomem *pllbase;
111 s64 temp;
112 unsigned long parent_rate;
113
114 parent_rate = clk_get_rate(clk->parent);
115
116 pllbase = _get_pll_base(clk);
117
118 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
119 pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
120 dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
121
122 if (pll_hfsm == 0) {
123 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
124 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
125 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
126 } else {
127 dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
128 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
129 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
130 }
131 pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
132 mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
133 mfi = (mfi <= 5) ? 5 : mfi;
134 mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
135 mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
136 /* Sign extend to 32-bits */
137 if (mfn >= 0x04000000) {
138 mfn |= 0xFC000000;
139 mfn_abs = -mfn;
140 }
141
142 ref_clk = 2 * parent_rate;
143 if (dbl != 0)
144 ref_clk *= 2;
145
146 ref_clk /= (pdf + 1);
147 temp = (u64) ref_clk * mfn_abs;
148 do_div(temp, mfd + 1);
149 if (mfn < 0)
150 temp = -temp;
151 temp = (ref_clk * mfi) + temp;
152
153 return temp;
154}
155
156static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
157{
158 u32 reg;
159 void __iomem *pllbase;
160
161 long mfi, pdf, mfn, mfd = 999999;
162 s64 temp64;
163 unsigned long quad_parent_rate;
164 unsigned long pll_hfsm, dp_ctl;
165 unsigned long parent_rate;
166
167 parent_rate = clk_get_rate(clk->parent);
168
169 pllbase = _get_pll_base(clk);
170
171 quad_parent_rate = 4 * parent_rate;
172 pdf = mfi = -1;
173 while (++pdf < 16 && mfi < 5)
174 mfi = rate * (pdf+1) / quad_parent_rate;
175 if (mfi > 15)
176 return -EINVAL;
177 pdf--;
178
179 temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
180 do_div(temp64, quad_parent_rate/1000000);
181 mfn = (long)temp64;
182
183 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
184 /* use dpdck0_2 */
185 __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
186 pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
187 if (pll_hfsm == 0) {
188 reg = mfi << 4 | pdf;
189 __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
190 __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
191 __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
192 } else {
193 reg = mfi << 4 | pdf;
194 __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
195 __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
196 __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
197 }
198
199 return 0;
200}
201
202static int _clk_pll_enable(struct clk *clk)
203{
204 u32 reg;
205 void __iomem *pllbase;
206 int i = 0;
207
208 pllbase = _get_pll_base(clk);
209 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
210 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
211
212 /* Wait for lock */
213 do {
214 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
215 if (reg & MXC_PLL_DP_CTL_LRF)
216 break;
217
218 udelay(1);
219 } while (++i < MAX_DPLL_WAIT_TRIES);
220
221 if (i == MAX_DPLL_WAIT_TRIES) {
222 pr_err("MX5: pll locking failed\n");
223 return -EINVAL;
224 }
225
226 return 0;
227}
228
229static void _clk_pll_disable(struct clk *clk)
230{
231 u32 reg;
232 void __iomem *pllbase;
233
234 pllbase = _get_pll_base(clk);
235 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
236 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
237}
238
239static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
240{
241 u32 reg, step;
242
243 reg = __raw_readl(MXC_CCM_CCSR);
244
245 /* When switching from pll_main_clk to a bypass clock, first select a
246 * multiplexed clock in 'step_sel', then shift the glitchless mux
247 * 'pll1_sw_clk_sel'.
248 *
249 * When switching back, do it in reverse order
250 */
251 if (parent == &pll1_main_clk) {
252 /* Switch to pll1_main_clk */
253 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
254 __raw_writel(reg, MXC_CCM_CCSR);
255 /* step_clk mux switched to lp_apm, to save power. */
256 reg = __raw_readl(MXC_CCM_CCSR);
257 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
258 reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM <<
259 MXC_CCM_CCSR_STEP_SEL_OFFSET);
260 } else {
261 if (parent == &lp_apm_clk) {
262 step = MXC_CCM_CCSR_STEP_SEL_LP_APM;
263 } else if (parent == &pll2_sw_clk) {
264 step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED;
265 } else if (parent == &pll3_sw_clk) {
266 step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED;
267 } else
268 return -EINVAL;
269
270 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
271 reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET);
272
273 __raw_writel(reg, MXC_CCM_CCSR);
274 /* Switch to step_clk */
275 reg = __raw_readl(MXC_CCM_CCSR);
276 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
277 }
278 __raw_writel(reg, MXC_CCM_CCSR);
279 return 0;
280}
281
282static unsigned long clk_pll1_sw_get_rate(struct clk *clk)
283{
284 u32 reg, div;
285 unsigned long parent_rate;
286
287 parent_rate = clk_get_rate(clk->parent);
288
289 reg = __raw_readl(MXC_CCM_CCSR);
290
291 if (clk->parent == &pll2_sw_clk) {
292 div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
293 MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
294 } else if (clk->parent == &pll3_sw_clk) {
295 div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
296 MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
297 } else
298 div = 1;
299 return parent_rate / div;
300}
301
302static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
303{
304 u32 reg;
305
306 reg = __raw_readl(MXC_CCM_CCSR);
307
308 if (parent == &pll2_sw_clk)
309 reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
310 else
311 reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
312
313 __raw_writel(reg, MXC_CCM_CCSR);
314 return 0;
315}
316
317static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
318{
319 u32 reg;
320
321 if (parent == &osc_clk)
322 reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
323 else
324 return -EINVAL;
325
326 __raw_writel(reg, MXC_CCM_CCSR);
327
328 return 0;
329}
330
331static unsigned long clk_arm_get_rate(struct clk *clk)
332{
333 u32 cacrr, div;
334 unsigned long parent_rate;
335
336 parent_rate = clk_get_rate(clk->parent);
337 cacrr = __raw_readl(MXC_CCM_CACRR);
338 div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
339
340 return parent_rate / div;
341}
342
343static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
344{
345 u32 reg, mux;
346 int i = 0;
347
348 mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
349
350 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
351 reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
352 __raw_writel(reg, MXC_CCM_CBCMR);
353
354 /* Wait for lock */
355 do {
356 reg = __raw_readl(MXC_CCM_CDHIPR);
357 if (!(reg & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY))
358 break;
359
360 udelay(1);
361 } while (++i < MAX_DPLL_WAIT_TRIES);
362
363 if (i == MAX_DPLL_WAIT_TRIES) {
364 pr_err("MX5: Set parent for periph_apm clock failed\n");
365 return -EINVAL;
366 }
367
368 return 0;
369}
370
371static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
372{
373 u32 reg;
374
375 reg = __raw_readl(MXC_CCM_CBCDR);
376
377 if (parent == &pll2_sw_clk)
378 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
379 else if (parent == &periph_apm_clk)
380 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
381 else
382 return -EINVAL;
383
384 __raw_writel(reg, MXC_CCM_CBCDR);
385
386 return 0;
387}
388
389static struct clk main_bus_clk = {
390 .parent = &pll2_sw_clk,
391 .set_parent = _clk_main_bus_set_parent,
392};
393
394static unsigned long clk_ahb_get_rate(struct clk *clk)
395{
396 u32 reg, div;
397 unsigned long parent_rate;
398
399 parent_rate = clk_get_rate(clk->parent);
400
401 reg = __raw_readl(MXC_CCM_CBCDR);
402 div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
403 MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
404 return parent_rate / div;
405}
406
407
408static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
409{
410 u32 reg, div;
411 unsigned long parent_rate;
412 int i = 0;
413
414 parent_rate = clk_get_rate(clk->parent);
415
416 div = parent_rate / rate;
417 if (div > 8 || div < 1 || ((parent_rate / div) != rate))
418 return -EINVAL;
419
420 reg = __raw_readl(MXC_CCM_CBCDR);
421 reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
422 reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
423 __raw_writel(reg, MXC_CCM_CBCDR);
424
425 /* Wait for lock */
426 do {
427 reg = __raw_readl(MXC_CCM_CDHIPR);
428 if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY))
429 break;
430
431 udelay(1);
432 } while (++i < MAX_DPLL_WAIT_TRIES);
433
434 if (i == MAX_DPLL_WAIT_TRIES) {
435 pr_err("MX5: clk_ahb_set_rate failed\n");
436 return -EINVAL;
437 }
438
439 return 0;
440}
441
442static unsigned long _clk_ahb_round_rate(struct clk *clk,
443 unsigned long rate)
444{
445 u32 div;
446 unsigned long parent_rate;
447
448 parent_rate = clk_get_rate(clk->parent);
449
450 div = parent_rate / rate;
451 if (div > 8)
452 div = 8;
453 else if (div == 0)
454 div++;
455 return parent_rate / div;
456}
457
458
459static int _clk_max_enable(struct clk *clk)
460{
461 u32 reg;
462
463 _clk_ccgr_enable(clk);
464
465 /* Handshake with MAX when LPM is entered. */
466 reg = __raw_readl(MXC_CCM_CLPCR);
467 reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
468 __raw_writel(reg, MXC_CCM_CLPCR);
469
470 return 0;
471}
472
473static void _clk_max_disable(struct clk *clk)
474{
475 u32 reg;
476
477 _clk_ccgr_disable_inwait(clk);
478
479 /* No Handshake with MAX when LPM is entered as its disabled. */
480 reg = __raw_readl(MXC_CCM_CLPCR);
481 reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
482 __raw_writel(reg, MXC_CCM_CLPCR);
483}
484
485static unsigned long clk_ipg_get_rate(struct clk *clk)
486{
487 u32 reg, div;
488 unsigned long parent_rate;
489
490 parent_rate = clk_get_rate(clk->parent);
491
492 reg = __raw_readl(MXC_CCM_CBCDR);
493 div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
494 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
495
496 return parent_rate / div;
497}
498
499static unsigned long clk_ipg_per_get_rate(struct clk *clk)
500{
501 u32 reg, prediv1, prediv2, podf;
502 unsigned long parent_rate;
503
504 parent_rate = clk_get_rate(clk->parent);
505
506 if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
507 /* the main_bus_clk is the one before the DVFS engine */
508 reg = __raw_readl(MXC_CCM_CBCDR);
509 prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
510 MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
511 prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
512 MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
513 podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
514 MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
515 return parent_rate / (prediv1 * prediv2 * podf);
516 } else if (clk->parent == &ipg_clk)
517 return parent_rate;
518 else
519 BUG();
520}
521
522static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
523{
524 u32 reg;
525
526 reg = __raw_readl(MXC_CCM_CBCMR);
527
528 reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
529 reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
530
531 if (parent == &ipg_clk)
532 reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
533 else if (parent == &lp_apm_clk)
534 reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
535 else if (parent != &main_bus_clk)
536 return -EINVAL;
537
538 __raw_writel(reg, MXC_CCM_CBCMR);
539
540 return 0;
541}
542
543static unsigned long clk_uart_get_rate(struct clk *clk)
544{
545 u32 reg, prediv, podf;
546 unsigned long parent_rate;
547
548 parent_rate = clk_get_rate(clk->parent);
549
550 reg = __raw_readl(MXC_CCM_CSCDR1);
551 prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
552 MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
553 podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
554 MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
555
556 return parent_rate / (prediv * podf);
557}
558
559static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
560{
561 u32 reg, mux;
562
563 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
564 &lp_apm_clk);
565 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK;
566 reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
567 __raw_writel(reg, MXC_CCM_CSCMR1);
568
569 return 0;
570}
571
572static unsigned long get_high_reference_clock_rate(struct clk *clk)
573{
574 return external_high_reference;
575}
576
577static unsigned long get_low_reference_clock_rate(struct clk *clk)
578{
579 return external_low_reference;
580}
581
582static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
583{
584 return oscillator_reference;
585}
586
587static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
588{
589 return ckih2_reference;
590}
591
592/* External high frequency clock */
593static struct clk ckih_clk = {
594 .get_rate = get_high_reference_clock_rate,
595};
596
597static struct clk ckih2_clk = {
598 .get_rate = get_ckih2_reference_clock_rate,
599};
600
601static struct clk osc_clk = {
602 .get_rate = get_oscillator_reference_clock_rate,
603};
604
605/* External low frequency (32kHz) clock */
606static struct clk ckil_clk = {
607 .get_rate = get_low_reference_clock_rate,
608};
609
610static struct clk pll1_main_clk = {
611 .parent = &osc_clk,
612 .get_rate = clk_pll_get_rate,
613 .enable = _clk_pll_enable,
614 .disable = _clk_pll_disable,
615};
616
617/* Clock tree block diagram (WIP):
618 * CCM: Clock Controller Module
619 *
620 * PLL output -> |
621 * | CCM Switcher -> CCM_CLK_ROOT_GEN ->
622 * PLL bypass -> |
623 *
624 */
625
626/* PLL1 SW supplies to ARM core */
627static struct clk pll1_sw_clk = {
628 .parent = &pll1_main_clk,
629 .set_parent = _clk_pll1_sw_set_parent,
630 .get_rate = clk_pll1_sw_get_rate,
631};
632
633/* PLL2 SW supplies to AXI/AHB/IP buses */
634static struct clk pll2_sw_clk = {
635 .parent = &osc_clk,
636 .get_rate = clk_pll_get_rate,
637 .set_rate = _clk_pll_set_rate,
638 .set_parent = _clk_pll2_sw_set_parent,
639 .enable = _clk_pll_enable,
640 .disable = _clk_pll_disable,
641};
642
643/* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
644static struct clk pll3_sw_clk = {
645 .parent = &osc_clk,
646 .set_rate = _clk_pll_set_rate,
647 .get_rate = clk_pll_get_rate,
648 .enable = _clk_pll_enable,
649 .disable = _clk_pll_disable,
650};
651
652/* Low-power Audio Playback Mode clock */
653static struct clk lp_apm_clk = {
654 .parent = &osc_clk,
655 .set_parent = _clk_lp_apm_set_parent,
656};
657
658static struct clk periph_apm_clk = {
659 .parent = &pll1_sw_clk,
660 .set_parent = _clk_periph_apm_set_parent,
661};
662
663static struct clk cpu_clk = {
664 .parent = &pll1_sw_clk,
665 .get_rate = clk_arm_get_rate,
666};
667
668static struct clk ahb_clk = {
669 .parent = &main_bus_clk,
670 .get_rate = clk_ahb_get_rate,
671 .set_rate = _clk_ahb_set_rate,
672 .round_rate = _clk_ahb_round_rate,
673};
674
675/* Main IP interface clock for access to registers */
676static struct clk ipg_clk = {
677 .parent = &ahb_clk,
678 .get_rate = clk_ipg_get_rate,
679};
680
681static struct clk ipg_perclk = {
682 .parent = &lp_apm_clk,
683 .get_rate = clk_ipg_per_get_rate,
684 .set_parent = _clk_ipg_per_set_parent,
685};
686
687static struct clk uart_root_clk = {
688 .parent = &pll2_sw_clk,
689 .get_rate = clk_uart_get_rate,
690 .set_parent = _clk_uart_set_parent,
691};
692
693static struct clk ahb_max_clk = {
694 .parent = &ahb_clk,
695 .enable_reg = MXC_CCM_CCGR0,
696 .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
697 .enable = _clk_max_enable,
698 .disable = _clk_max_disable,
699};
700
701static struct clk aips_tz1_clk = {
702 .parent = &ahb_clk,
703 .secondary = &ahb_max_clk,
704 .enable_reg = MXC_CCM_CCGR0,
705 .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
706 .enable = _clk_ccgr_enable,
707 .disable = _clk_ccgr_disable_inwait,
708};
709
710static struct clk aips_tz2_clk = {
711 .parent = &ahb_clk,
712 .secondary = &ahb_max_clk,
713 .enable_reg = MXC_CCM_CCGR0,
714 .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
715 .enable = _clk_ccgr_enable,
716 .disable = _clk_ccgr_disable_inwait,
717};
718
719static struct clk gpt_32k_clk = {
720 .id = 0,
721 .parent = &ckil_clk,
722};
723
724#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \
725 static struct clk name = { \
726 .id = i, \
727 .enable_reg = er, \
728 .enable_shift = es, \
729 .get_rate = gr, \
730 .set_rate = sr, \
731 .enable = _clk_ccgr_enable, \
732 .disable = _clk_ccgr_disable, \
733 .parent = p, \
734 .secondary = s, \
735 }
736
737/* DEFINE_CLOCK(name, id, enable_reg, enable_shift,
738 get_rate, set_rate, parent, secondary); */
739
740/* Shared peripheral bus arbiter */
741DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
742 NULL, NULL, &ipg_clk, NULL);
743
744/* UART */
745DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
746 NULL, NULL, &uart_root_clk, NULL);
747DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
748 NULL, NULL, &uart_root_clk, NULL);
749DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
750 NULL, NULL, &uart_root_clk, NULL);
751DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
752 NULL, NULL, &ipg_clk, &aips_tz1_clk);
753DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
754 NULL, NULL, &ipg_clk, &aips_tz1_clk);
755DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
756 NULL, NULL, &ipg_clk, &spba_clk);
757
758/* GPT */
759DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
760 NULL, NULL, &ipg_perclk, NULL);
761DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
762 NULL, NULL, &ipg_clk, NULL);
763
764/* FEC */
765DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
766 NULL, NULL, &ipg_clk, NULL);
767
768#define _REGISTER_CLOCK(d, n, c) \
769 { \
770 .dev_id = d, \
771 .con_id = n, \
772 .clk = &c, \
773 },
774
775static struct clk_lookup lookups[] = {
776 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
777 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
778 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
779 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
780 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
781};
782
783static void clk_tree_init(void)
784{
785 u32 reg;
786
787 ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
788
789 /*
790 * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
791 * 8MHz, its derived from lp_apm.
792 *
793 * FIXME: Verify if true for all boards
794 */
795 reg = __raw_readl(MXC_CCM_CBCDR);
796 reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
797 reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
798 reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
799 reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
800 __raw_writel(reg, MXC_CCM_CBCDR);
801}
802
803int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
804 unsigned long ckih1, unsigned long ckih2)
805{
806 int i;
807
808 external_low_reference = ckil;
809 external_high_reference = ckih1;
810 ckih2_reference = ckih2;
811 oscillator_reference = osc;
812
813 for (i = 0; i < ARRAY_SIZE(lookups); i++)
814 clkdev_add(&lookups[i]);
815
816 clk_tree_init();
817
818 clk_enable(&cpu_clk);
819 clk_enable(&main_bus_clk);
820
821 /* System timer */
822 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
823 MX51_MXC_INT_GPT);
824 return 0;
825}
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
new file mode 100644
index 000000000000..41c769f08c4d
--- /dev/null
+++ b/arch/arm/mach-mx5/cpu.c
@@ -0,0 +1,47 @@
1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * This file contains the CPU initialization code.
12 */
13
14#include <linux/types.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <mach/hardware.h>
18#include <asm/io.h>
19
20static int __init post_cpu_init(void)
21{
22 unsigned int reg;
23 void __iomem *base;
24
25 if (!cpu_is_mx51())
26 return 0;
27
28 base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
29 __raw_writel(0x0, base + 0x40);
30 __raw_writel(0x0, base + 0x44);
31 __raw_writel(0x0, base + 0x48);
32 __raw_writel(0x0, base + 0x4C);
33 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
34 __raw_writel(reg, base + 0x50);
35
36 base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
37 __raw_writel(0x0, base + 0x40);
38 __raw_writel(0x0, base + 0x44);
39 __raw_writel(0x0, base + 0x48);
40 __raw_writel(0x0, base + 0x4C);
41 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
42 __raw_writel(reg, base + 0x50);
43
44 return 0;
45}
46
47postcore_initcall(post_cpu_init);
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
new file mode 100644
index 000000000000..c776b9af0624
--- /dev/null
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -0,0 +1,583 @@
1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
12#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
13
14#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
15#define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
16#define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
17#define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
18#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
19#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
20
21/* PLL Register Offsets */
22#define MXC_PLL_DP_CTL 0x00
23#define MXC_PLL_DP_CONFIG 0x04
24#define MXC_PLL_DP_OP 0x08
25#define MXC_PLL_DP_MFD 0x0C
26#define MXC_PLL_DP_MFN 0x10
27#define MXC_PLL_DP_MFNMINUS 0x14
28#define MXC_PLL_DP_MFNPLUS 0x18
29#define MXC_PLL_DP_HFS_OP 0x1C
30#define MXC_PLL_DP_HFS_MFD 0x20
31#define MXC_PLL_DP_HFS_MFN 0x24
32#define MXC_PLL_DP_MFN_TOGC 0x28
33#define MXC_PLL_DP_DESTAT 0x2c
34
35/* PLL Register Bit definitions */
36#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
37#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
38#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
39#define MXC_PLL_DP_CTL_ADE 0x800
40#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
41#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
42#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
43#define MXC_PLL_DP_CTL_HFSM 0x80
44#define MXC_PLL_DP_CTL_PRE 0x40
45#define MXC_PLL_DP_CTL_UPEN 0x20
46#define MXC_PLL_DP_CTL_RST 0x10
47#define MXC_PLL_DP_CTL_RCP 0x8
48#define MXC_PLL_DP_CTL_PLM 0x4
49#define MXC_PLL_DP_CTL_BRM0 0x2
50#define MXC_PLL_DP_CTL_LRF 0x1
51
52#define MXC_PLL_DP_CONFIG_BIST 0x8
53#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
54#define MXC_PLL_DP_CONFIG_AREN 0x2
55#define MXC_PLL_DP_CONFIG_LDREQ 0x1
56
57#define MXC_PLL_DP_OP_MFI_OFFSET 4
58#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
59#define MXC_PLL_DP_OP_PDF_OFFSET 0
60#define MXC_PLL_DP_OP_PDF_MASK 0xF
61
62#define MXC_PLL_DP_MFD_OFFSET 0
63#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
64
65#define MXC_PLL_DP_MFN_OFFSET 0x0
66#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
67
68#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
69#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
70#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
71#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
72
73#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
74#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
75
76/* Register addresses of CCM*/
77#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00)
78#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04)
79#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08)
80#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C)
81#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10)
82#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14)
83#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18)
84#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C)
85#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20)
86#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24)
87#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28)
88#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C)
89#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30)
90#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34)
91#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38)
92#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C)
93#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40)
94#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44)
95#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48)
96#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C)
97#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50)
98#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54)
99#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58)
100#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C)
101#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60)
102#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64)
103#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68)
104#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C)
105#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70)
106#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74)
107#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78)
108#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C)
109#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80)
110#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84)
111
112/* Define the bits in register CCR */
113#define MXC_CCM_CCR_COSC_EN (1 << 12)
114#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11)
115#define MXC_CCM_CCR_CAMP2_EN (1 << 10)
116#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
117#define MXC_CCM_CCR_FPM_EN (1 << 8)
118#define MXC_CCM_CCR_OSCNT_OFFSET (0)
119#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
120
121/* Define the bits in register CCDR */
122#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
123#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
124#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
125
126/* Define the bits in register CSR */
127#define MXC_CCM_CSR_COSR_READY (1 << 5)
128#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
129#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
130#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
131#define MXC_CCM_CSR_FPM_READY (1 << 1)
132#define MXC_CCM_CSR_REF_EN_B (1 << 0)
133
134/* Define the bits in register CCSR */
135#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9)
136#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
137#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
138#define MXC_CCM_CCSR_STEP_SEL_LP_APM 0
139#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */
140#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
141#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
142#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
143#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
144#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
145#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
146#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk,
147 1: step_clk */
148#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
149#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
150
151/* Define the bits in register CACRR */
152#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
153#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
154
155/* Define the bits in register CBCDR */
156#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
157#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
158#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30)
159#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30)
160#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27)
161#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
162#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
163#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
164#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
165#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
166#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
167#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
168#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
169#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
170#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
171#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
172#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
173#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
174#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
175#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
176#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
177#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
178#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
179#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
180
181/* Define the bits in register CBCMR */
182#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
183#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
184#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
185#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
186#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
187#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
188#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
189#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
190#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
191#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
192#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
193#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
194#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14)
195#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14)
196#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
197#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
198
199/* Define the bits in register CSCMR1 */
200#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
201#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
202#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
203#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
204#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
205#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
206#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
207#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
208#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
209#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
210#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
211#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
212#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
213#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
214#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
215#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
216#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
217#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
218#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
219#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
220#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
221#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
222#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
223#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
224#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
225#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
226#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
227#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
228#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
229#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
230#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
231#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
232
233/* Define the bits in register CSCMR2 */
234#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3)
235#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3))
236#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
237#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
238#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
239#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
240#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
241#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
242#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
243#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
244#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
245#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
246#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
247#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
248#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
249#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
250#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
251#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
252#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
253#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
254#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
255#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
256#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
257#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
258#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
259#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
260#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
261
262/* Define the bits in register CSCDR1 */
263#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
264#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
265#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
266#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
267#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
268#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
269#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
270#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
271#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
272#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
273#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
274#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
275#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
276#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
277#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
278#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
279#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
280#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
281
282/* Define the bits in register CS1CDR and CS2CDR */
283#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
284#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
285#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
286#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
287#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
288#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
289#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
290#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
291
292#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
293#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
294#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
295#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
296#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
297#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
298#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
299#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
300
301/* Define the bits in register CDCDR */
302#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
303#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
304#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
305#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
306#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
307#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
308#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
309#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
310#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
311#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
312#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
313#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
314#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
315#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
316#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
317#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
318
319/* Define the bits in register CHSCCDR */
320#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
321#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
322#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
323#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
324#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
325#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
326#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
327#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
328
329/* Define the bits in register CSCDR2 */
330#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
331#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
332#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
333#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
334#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
335#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
336#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
337#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
338#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
339#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
340#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
341#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
342
343/* Define the bits in register CSCDR3 */
344#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
345#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
346#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
347#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
348#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
349#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
350#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
351#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
352
353/* Define the bits in register CSCDR4 */
354#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
355#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
356#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
357#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
358#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
359#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
360#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
361#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
362
363/* Define the bits in register CDHIPR */
364#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
365#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8)
366#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7)
367#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
368#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
369#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
370#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
371#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
372#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
373#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
374
375/* Define the bits in register CDCR */
376#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
377#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
378#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
379
380/* Define the bits in register CLPCR */
381#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
382#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
383#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
384#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
385#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
386#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
387#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
388#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
389#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
390#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
391#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
392#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
393#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
394#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
395#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
396#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
397#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
398#define MXC_CCM_CLPCR_LPM_OFFSET (0)
399#define MXC_CCM_CLPCR_LPM_MASK (0x3)
400
401/* Define the bits in register CISR */
402#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
403#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
404#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
405#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
406#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
407#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
408#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
409#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
410#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
411#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
412#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
413#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
414#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
415#define MXC_CCM_CISR_LRF_PLL1 (0x1)
416
417/* Define the bits in register CIMR */
418#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
419#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
420#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
421#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
422#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
423#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
424#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
425#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
426#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
427#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
428#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
429#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
430#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
431
432/* Define the bits in register CCOSR */
433#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
434#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
435#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
436#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
437#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
438#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
439#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
440#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
441#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
442#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
443
444/* Define the bits in registers CGPR */
445#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
446#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
447#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
448#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
449
450/* Define the bits in registers CCGRx */
451#define MXC_CCM_CCGRx_CG_MASK 0x3
452#define MXC_CCM_CCGRx_MOD_OFF 0x0
453#define MXC_CCM_CCGRx_MOD_ON 0x3
454#define MXC_CCM_CCGRx_MOD_IDLE 0x1
455
456#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30)
457#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28)
458#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26)
459#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24)
460#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22)
461#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20)
462#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18)
463#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16)
464#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10)
465#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8)
466#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6)
467#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4)
468#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2)
469#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0)
470
471#define MXC_CCM_CCGRx_CG15_OFFSET 30
472#define MXC_CCM_CCGRx_CG14_OFFSET 28
473#define MXC_CCM_CCGRx_CG13_OFFSET 26
474#define MXC_CCM_CCGRx_CG12_OFFSET 24
475#define MXC_CCM_CCGRx_CG11_OFFSET 22
476#define MXC_CCM_CCGRx_CG10_OFFSET 20
477#define MXC_CCM_CCGRx_CG9_OFFSET 18
478#define MXC_CCM_CCGRx_CG8_OFFSET 16
479#define MXC_CCM_CCGRx_CG7_OFFSET 14
480#define MXC_CCM_CCGRx_CG6_OFFSET 12
481#define MXC_CCM_CCGRx_CG5_OFFSET 10
482#define MXC_CCM_CCGRx_CG4_OFFSET 8
483#define MXC_CCM_CCGRx_CG3_OFFSET 6
484#define MXC_CCM_CCGRx_CG2_OFFSET 4
485#define MXC_CCM_CCGRx_CG1_OFFSET 2
486#define MXC_CCM_CCGRx_CG0_OFFSET 0
487
488#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80)
489#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100)
490#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180)
491#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0)
492#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220)
493#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240)
494#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260)
495#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280)
496#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0)
497#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0)
498#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0)
499#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0)
500#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300)
501
502/* CORTEXA8 platform */
503#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0)
504#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4)
505#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8)
506#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC)
507#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10)
508#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14)
509#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18)
510#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20)
511#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24)
512
513/* DVFS CORE */
514#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
515#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
516#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
517#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
518#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
519#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
520#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
521#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
522#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
523#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
524#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
525#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
526#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
527#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
528#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
529#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
530#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
531
532/* GPC */
533#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0)
534#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4)
535#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8)
536#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC)
537#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10)
538#define MXC_GPC_PGR_ARMPG_OFFSET 8
539#define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
540
541/* PGC */
542#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
543#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
544#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
545#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
546#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
547#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
548
549#define MXC_PGCR_PCR 1
550#define MXC_SRPGCR_PCR 1
551#define MXC_EMPGCR_PCR 1
552#define MXC_PGSR_PSR 1
553
554
555#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
556#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
557
558/* SRPG */
559#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
560#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
561#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
562
563#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
564#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
565#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
566
567#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
568#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
569#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
570
571#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
572#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
573#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
574
575#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
576#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
577#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
578
579#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
580#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
581#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
582
583#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
new file mode 100644
index 000000000000..d6fd3961ade9
--- /dev/null
+++ b/arch/arm/mach-mx5/devices.c
@@ -0,0 +1,96 @@
1/*
2 * Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/platform_device.h>
13#include <mach/hardware.h>
14#include <mach/imx-uart.h>
15
16static struct resource uart0[] = {
17 {
18 .start = MX51_UART1_BASE_ADDR,
19 .end = MX51_UART1_BASE_ADDR + 0xfff,
20 .flags = IORESOURCE_MEM,
21 }, {
22 .start = MX51_MXC_INT_UART1,
23 .end = MX51_MXC_INT_UART1,
24 .flags = IORESOURCE_IRQ,
25 },
26};
27
28struct platform_device mxc_uart_device0 = {
29 .name = "imx-uart",
30 .id = 0,
31 .resource = uart0,
32 .num_resources = ARRAY_SIZE(uart0),
33};
34
35static struct resource uart1[] = {
36 {
37 .start = MX51_UART2_BASE_ADDR,
38 .end = MX51_UART2_BASE_ADDR + 0xfff,
39 .flags = IORESOURCE_MEM,
40 }, {
41 .start = MX51_MXC_INT_UART2,
42 .end = MX51_MXC_INT_UART2,
43 .flags = IORESOURCE_IRQ,
44 },
45};
46
47struct platform_device mxc_uart_device1 = {
48 .name = "imx-uart",
49 .id = 1,
50 .resource = uart1,
51 .num_resources = ARRAY_SIZE(uart1),
52};
53
54static struct resource uart2[] = {
55 {
56 .start = MX51_UART3_BASE_ADDR,
57 .end = MX51_UART3_BASE_ADDR + 0xfff,
58 .flags = IORESOURCE_MEM,
59 }, {
60 .start = MX51_MXC_INT_UART3,
61 .end = MX51_MXC_INT_UART3,
62 .flags = IORESOURCE_IRQ,
63 },
64};
65
66struct platform_device mxc_uart_device2 = {
67 .name = "imx-uart",
68 .id = 2,
69 .resource = uart2,
70 .num_resources = ARRAY_SIZE(uart2),
71};
72
73static struct resource mxc_fec_resources[] = {
74 {
75 .start = MX51_MXC_FEC_BASE_ADDR,
76 .end = MX51_MXC_FEC_BASE_ADDR + 0xfff,
77 .flags = IORESOURCE_MEM,
78 }, {
79 .start = MX51_MXC_INT_FEC,
80 .end = MX51_MXC_INT_FEC,
81 .flags = IORESOURCE_IRQ,
82 },
83};
84
85struct platform_device mxc_fec_device = {
86 .name = "fec",
87 .id = 0,
88 .num_resources = ARRAY_SIZE(mxc_fec_resources),
89 .resource = mxc_fec_resources,
90};
91
92/* Dummy definition to allow compiling in AVIC and TZIC simultaneously */
93int __init mxc_register_gpios(void)
94{
95 return 0;
96}
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
new file mode 100644
index 000000000000..f339ab8c19be
--- /dev/null
+++ b/arch/arm/mach-mx5/devices.h
@@ -0,0 +1,4 @@
1extern struct platform_device mxc_uart_device0;
2extern struct platform_device mxc_uart_device1;
3extern struct platform_device mxc_uart_device2;
4extern struct platform_device mxc_fec_device;
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
new file mode 100644
index 000000000000..c21e18be7af8
--- /dev/null
+++ b/arch/arm/mach-mx5/mm.c
@@ -0,0 +1,89 @@
1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * Create static mapping between physical to virtual memory.
12 */
13
14#include <linux/mm.h>
15#include <linux/init.h>
16
17#include <asm/mach/map.h>
18
19#include <mach/hardware.h>
20#include <mach/common.h>
21#include <mach/iomux-v3.h>
22
23/*
24 * Define the MX51 memory map.
25 */
26static struct map_desc mxc_io_desc[] __initdata = {
27 {
28 .virtual = MX51_IRAM_BASE_ADDR_VIRT,
29 .pfn = __phys_to_pfn(MX51_IRAM_BASE_ADDR),
30 .length = MX51_IRAM_SIZE,
31 .type = MT_DEVICE
32 }, {
33 .virtual = MX51_DEBUG_BASE_ADDR_VIRT,
34 .pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR),
35 .length = MX51_DEBUG_SIZE,
36 .type = MT_DEVICE
37 }, {
38 .virtual = MX51_TZIC_BASE_ADDR_VIRT,
39 .pfn = __phys_to_pfn(MX51_TZIC_BASE_ADDR),
40 .length = MX51_TZIC_SIZE,
41 .type = MT_DEVICE
42 }, {
43 .virtual = MX51_AIPS1_BASE_ADDR_VIRT,
44 .pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR),
45 .length = MX51_AIPS1_SIZE,
46 .type = MT_DEVICE
47 }, {
48 .virtual = MX51_SPBA0_BASE_ADDR_VIRT,
49 .pfn = __phys_to_pfn(MX51_SPBA0_BASE_ADDR),
50 .length = MX51_SPBA0_SIZE,
51 .type = MT_DEVICE
52 }, {
53 .virtual = MX51_AIPS2_BASE_ADDR_VIRT,
54 .pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR),
55 .length = MX51_AIPS2_SIZE,
56 .type = MT_DEVICE
57 }, {
58 .virtual = MX51_NFC_AXI_BASE_ADDR_VIRT,
59 .pfn = __phys_to_pfn(MX51_NFC_AXI_BASE_ADDR),
60 .length = MX51_NFC_AXI_SIZE,
61 .type = MT_DEVICE
62 },
63};
64
65/*
66 * This function initializes the memory map. It is called during the
67 * system startup to create static physical to virtual memory mappings
68 * for the IO modules.
69 */
70void __init mx51_map_io(void)
71{
72 u32 tzic_addr;
73
74 if (mx51_revision() < MX51_CHIP_REV_2_0)
75 tzic_addr = 0x8FFFC000;
76 else
77 tzic_addr = 0xE0003000;
78 mxc_io_desc[2].pfn = __phys_to_pfn(tzic_addr);
79
80 mxc_set_cpu_type(MXC_CPU_MX51);
81 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
82 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR));
83 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
84}
85
86void __init mx51_init_irq(void)
87{
88 tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
89}
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 8b0a1ee039fa..cea51a0ae9f7 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -41,6 +41,13 @@ config ARCH_MXC91231
41 help 41 help
42 This enables support for systems based on the Freescale MXC91231 family 42 This enables support for systems based on the Freescale MXC91231 family
43 43
44config ARCH_MX5
45 bool "MX5-based"
46 select CPU_V7
47 select COMMON_CLKDEV
48 help
49 This enables support for systems based on the Freescale i.MX51 family
50
44endchoice 51endchoice
45 52
46source "arch/arm/mach-mx1/Kconfig" 53source "arch/arm/mach-mx1/Kconfig"
@@ -48,6 +55,7 @@ source "arch/arm/mach-mx2/Kconfig"
48source "arch/arm/mach-mx3/Kconfig" 55source "arch/arm/mach-mx3/Kconfig"
49source "arch/arm/mach-mx25/Kconfig" 56source "arch/arm/mach-mx25/Kconfig"
50source "arch/arm/mach-mxc91231/Kconfig" 57source "arch/arm/mach-mxc91231/Kconfig"
58source "arch/arm/mach-mx5/Kconfig"
51 59
52endmenu 60endmenu
53 61
@@ -62,6 +70,14 @@ config MXC_IRQ_PRIOR
62 requirements for timing. 70 requirements for timing.
63 Say N here, unless you have a specialized requirement. 71 Say N here, unless you have a specialized requirement.
64 72
73config MXC_TZIC
74 bool "Enable TrustZone Interrupt Controller"
75 depends on ARCH_MX51
76 help
77 This will be automatically selected for all processors
78 containing this interrupt controller.
79 Say N here only if you are really sure.
80
65config MXC_PWM 81config MXC_PWM
66 tristate "Enable PWM driver" 82 tristate "Enable PWM driver"
67 depends on ARCH_MXC 83 depends on ARCH_MXC
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 7322bca8f5fb..a4bc6cb26aa4 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -5,6 +5,9 @@
5# Common support 5# Common support
6obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o 6obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o
7 7
8# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o)
9obj-$(CONFIG_MXC_TZIC) += tzic.o
10
8obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o 11obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o
9obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o 12obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
10CFLAGS_iomux-mx1-mx2.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS 13CFLAGS_iomux-mx1-mx2.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 4bf1068ffad9..2941472582d2 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -20,14 +20,17 @@ extern void mx25_map_io(void);
20extern void mx27_map_io(void); 20extern void mx27_map_io(void);
21extern void mx31_map_io(void); 21extern void mx31_map_io(void);
22extern void mx35_map_io(void); 22extern void mx35_map_io(void);
23extern void mx51_map_io(void);
23extern void mxc91231_map_io(void); 24extern void mxc91231_map_io(void);
24extern void mxc_init_irq(void __iomem *); 25extern void mxc_init_irq(void __iomem *);
26extern void tzic_init_irq(void __iomem *);
25extern void mx1_init_irq(void); 27extern void mx1_init_irq(void);
26extern void mx21_init_irq(void); 28extern void mx21_init_irq(void);
27extern void mx25_init_irq(void); 29extern void mx25_init_irq(void);
28extern void mx27_init_irq(void); 30extern void mx27_init_irq(void);
29extern void mx31_init_irq(void); 31extern void mx31_init_irq(void);
30extern void mx35_init_irq(void); 32extern void mx35_init_irq(void);
33extern void mx51_init_irq(void);
31extern void mxc91231_init_irq(void); 34extern void mxc91231_init_irq(void);
32extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); 35extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
33extern int mx1_clocks_init(unsigned long fref); 36extern int mx1_clocks_init(unsigned long fref);
@@ -36,6 +39,8 @@ extern int mx25_clocks_init(void);
36extern int mx27_clocks_init(unsigned long fref); 39extern int mx27_clocks_init(unsigned long fref);
37extern int mx31_clocks_init(unsigned long fref); 40extern int mx31_clocks_init(unsigned long fref);
38extern int mx35_clocks_init(void); 41extern int mx35_clocks_init(void);
42extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
43 unsigned long ckih1, unsigned long ckih2);
39extern int mxc91231_clocks_init(unsigned long fref); 44extern int mxc91231_clocks_init(unsigned long fref);
40extern int mxc_register_gpios(void); 45extern int mxc_register_gpios(void);
41extern int mxc_register_device(struct platform_device *pdev, void *data); 46extern int mxc_register_device(struct platform_device *pdev, void *data);
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 916d4fcb2ef2..133d66bfb533 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -45,6 +45,15 @@
45#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) 45#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
46#endif 46#endif
47 47
48#ifdef CONFIG_ARCH_MX5
49#ifdef UART_PADDR
50#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
51#endif
52#include <mach/mx51.h>
53#define UART_PADDR MX51_UART1_BASE_ADDR
54#define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR)
55#endif
56
48#ifdef CONFIG_ARCH_MXC91231 57#ifdef CONFIG_ARCH_MXC91231
49#ifdef UART_PADDR 58#ifdef UART_PADDR
50#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 59#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index 7cf290efe768..aeb08697726b 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> 2 * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
4 */ 4 */
5 5
6/* 6/*
@@ -18,11 +18,16 @@
18 .endm 18 .endm
19 19
20 .macro get_irqnr_preamble, base, tmp 20 .macro get_irqnr_preamble, base, tmp
21#ifndef CONFIG_MXC_TZIC
21 ldr \base, =avic_base 22 ldr \base, =avic_base
22 ldr \base, [\base] 23 ldr \base, [\base]
23#ifdef CONFIG_MXC_IRQ_PRIOR 24#ifdef CONFIG_MXC_IRQ_PRIOR
24 ldr r4, [\base, #AVIC_NIMASK] 25 ldr r4, [\base, #AVIC_NIMASK]
25#endif 26#endif
27#elif defined CONFIG_MXC_TZIC
28 ldr \base, =tzic_base
29 ldr \base, [\base]
30#endif /* CONFIG_MXC_TZIC */
26 .endm 31 .endm
27 32
28 .macro arch_ret_to_user, tmp1, tmp2 33 .macro arch_ret_to_user, tmp1, tmp2
@@ -32,6 +37,7 @@
32 @ and returns its number in irqnr 37 @ and returns its number in irqnr
33 @ and returns if an interrupt occured in irqstat 38 @ and returns if an interrupt occured in irqstat
34 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 39 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
40#ifndef CONFIG_MXC_TZIC
35 @ Load offset & priority of the highest priority 41 @ Load offset & priority of the highest priority
36 @ interrupt pending from AVIC_NIVECSR 42 @ interrupt pending from AVIC_NIVECSR
37 ldr \irqstat, [\base, #0x40] 43 ldr \irqstat, [\base, #0x40]
@@ -45,6 +51,32 @@
45 strne \tmp, [\base, #AVIC_NIMASK] 51 strne \tmp, [\base, #AVIC_NIMASK]
46 streq r4, [\base, #AVIC_NIMASK] 52 streq r4, [\base, #AVIC_NIMASK]
47#endif 53#endif
54#elif defined CONFIG_MXC_TZIC
55 @ Load offset & priority of the highest priority
56 @ interrupt pending.
57 @ 0xD80 is HIPND0 register
58 mov \irqnr, #0
59 mov \irqstat, #0x0D80
601000:
61 ldr \tmp, [\irqstat, \base]
62 cmp \tmp, #0
63 bne 1001f
64 addeq \irqnr, \irqnr, #32
65 addeq \irqstat, \irqstat, #4
66 cmp \irqnr, #128
67 blo 1000b
68 b 2001f
691001: mov \irqstat, #1
701002: tst \tmp, \irqstat
71 bne 2002f
72 movs \tmp, \tmp, lsr #1
73 addne \irqnr, \irqnr, #1
74 bne 1002b
752001:
76 mov \irqnr, #0
772002:
78 movs \irqnr, \irqnr
79#endif
48 .endm 80 .endm
49 81
50 @ irq priority table (not used) 82 @ irq priority table (not used)
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index db14c56930a3..ebadf4ac43fc 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -27,6 +27,10 @@
27 (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\ 27 (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\
28 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)) 28 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0))
29 29
30#ifdef CONFIG_ARCH_MX5
31#include <mach/mx51.h>
32#endif
33
30#ifdef CONFIG_ARCH_MX3 34#ifdef CONFIG_ARCH_MX3
31#include <mach/mx3x.h> 35#include <mach/mx3x.h>
32#include <mach/mx31.h> 36#include <mach/mx31.h>
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
new file mode 100644
index 000000000000..b4f975e6a665
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -0,0 +1,326 @@
1/*
2 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#ifndef __MACH_IOMUX_MX51_H__
13#define __MACH_IOMUX_MX51_H__
14
15#include <mach/iomux-v3.h>
16
17/*
18 * various IOMUX alternate output functions (1-7)
19 */
20typedef enum iomux_config {
21 IOMUX_CONFIG_ALT0,
22 IOMUX_CONFIG_ALT1,
23 IOMUX_CONFIG_ALT2,
24 IOMUX_CONFIG_ALT3,
25 IOMUX_CONFIG_ALT4,
26 IOMUX_CONFIG_ALT5,
27 IOMUX_CONFIG_ALT6,
28 IOMUX_CONFIG_ALT7,
29 IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
30 IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */
31} iomux_pin_cfg_t;
32
33/* Pad control groupings */
34#define MX51_UART1_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_DSE_HIGH)
36#define MX51_UART2_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
37 PAD_CTL_SRE_FAST)
38#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
39 PAD_CTL_SRE_FAST)
40
41/*
42 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
43 * If <padname> or <padmode> refers to a GPIO, it is named
44 * GPIO_<unit>_<num> see also iomux-v3.h
45 */
46
47/*
48 * FIXME: This was converted using scripts from existing Freescale code to
49 * this form used upstream. Need to verify the name format.
50 */
51
52/* PAD MUX ALT INPSE PATH PADCTRL */
53
54#define MX51_PAD_GPIO_2_0__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL)
55#define MX51_PAD_GPIO_2_1__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL)
56#define MX51_PAD_GPIO_2_2__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL)
57#define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL)
58#define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL)
59#define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL)
60#define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL)
61#define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL)
62
63/* Babbage UART3 */
64#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
65#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
66#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
67#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
68
69#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL)
70#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL)
71#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL)
72#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL)
73
74#define MX51_PAD_GPIO_2_10__EIM_A16 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL)
75#define MX51_PAD_GPIO_2_11__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL)
76#define MX51_PAD_GPIO_2_12__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL)
77#define MX51_PAD_GPIO_2_13__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL)
78#define MX51_PAD_GPIO_2_14__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL)
79#define MX51_PAD_GPIO_2_15__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL)
80#define MX51_PAD_GPIO_2_16__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL)
81#define MX51_PAD_GPIO_2_17__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL)
82
83#define MX51_PAD_GPIO_2_18__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL)
84#define MX51_PAD_GPIO_2_19__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL)
85#define MX51_PAD_GPIO_2_20__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL)
86#define MX51_PAD_GPIO_2_21__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL)
87#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL)
88#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL)
89#define MX51_PAD_GPIO_2_22__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL)
90#define MX51_PAD_GPIO_2_23__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL)
91
92#define MX51_PAD_GPIO_2_24__EIM_OE IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL)
93#define MX51_PAD_GPIO_2_25__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL)
94#define MX51_PAD_GPIO_2_26__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL)
95#define MX51_PAD_GPIO_2_27__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL)
96#define MX51_PAD_GPIO_2_28__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL)
97#define MX51_PAD_GPIO_2_29__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL)
98#define MX51_PAD_GPIO_2_30__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL)
99#define MX51_PAD_GPIO_2_31__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL)
100
101#define MX51_PAD_GPIO_3_1__EIM_LBA IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
102#define MX51_PAD_GPIO_3_2__EIM_CRE IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
103#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
104#define MX51_PAD_GPIO_3_3__NANDF_WE_B IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL)
105#define MX51_PAD_GPIO_3_4__NANDF_RE_B IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL)
106#define MX51_PAD_GPIO_3_5__NANDF_ALE IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL)
107#define MX51_PAD_GPIO_3_6__NANDF_CLE IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL)
108#define MX51_PAD_GPIO_3_7__NANDF_WP_B IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL)
109#define MX51_PAD_GPIO_3_8__NANDF_RB0 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
110#define MX51_PAD_GPIO_3_9__NANDF_RB1 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
111#define MX51_PAD_GPIO_3_10__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
112#define MX51_PAD_GPIO_3_11__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
113#define MX51_PAD_GPIO_3_12__GPIO_NAND IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
114/* REVISIT: Not sure of these values
115
116 #define MX51_PAD_GPIO_1___NANDF_RB4 IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL)
117 #define MX51_PAD_GPIO_3_13__NANDF_RB5 IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
118 #define MX51_PAD_GPIO_3_15__NANDF_RB7 IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
119*/
120#define MX51_PAD_GPIO_3_14__NANDF_RB6 IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
121#define MX51_PAD_GPIO_3_16__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
122#define MX51_PAD_GPIO_3_17__NANDF_CS1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
123#define MX51_PAD_GPIO_3_18__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
124#define MX51_PAD_GPIO_3_19__NANDF_CS3 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
125#define MX51_PAD_GPIO_3_20__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
126#define MX51_PAD_GPIO_3_21__NANDF_CS5 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
127#define MX51_PAD_GPIO_3_22__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
128#define MX51_PAD_GPIO_3_23__NANDF_CS7 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
129#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
130#define MX51_PAD_GPIO_3_25__NANDF_D15 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
131#define MX51_PAD_GPIO_3_26__NANDF_D14 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
132#define MX51_PAD_GPIO_3_27__NANDF_D13 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
133#define MX51_PAD_GPIO_3_28__NANDF_D12 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
134#define MX51_PAD_GPIO_3_29__NANDF_D11 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
135#define MX51_PAD_GPIO_3_30__NANDF_D10 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
136#define MX51_PAD_GPIO_3_31__NANDF_D9 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
137#define MX51_PAD_GPIO_4_0__NANDF_D8 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL)
138#define MX51_PAD_GPIO_4_1__NANDF_D7 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
139#define MX51_PAD_GPIO_4_2__NANDF_D6 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
140#define MX51_PAD_GPIO_4_3__NANDF_D5 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL)
141#define MX51_PAD_GPIO_4_4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
142#define MX51_PAD_GPIO_4_5__NANDF_D3 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
143#define MX51_PAD_GPIO_4_6__NANDF_D2 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
144#define MX51_PAD_GPIO_4_7__NANDF_D1 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
145#define MX51_PAD_GPIO_4_8__NANDF_D0 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL)
146#define MX51_PAD_GPIO_3_12__CSI1_D8 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL)
147#define MX51_PAD_GPIO_3_13__CSI1_D9 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL)
148#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
149#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
150#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
151#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
152#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
153#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
154#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
155#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
156#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
157#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
158#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
159#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
160#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
161#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
162#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
163#define MX51_PAD_GPIO_4_9__CSI2_D12 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL)
164#define MX51_PAD_GPIO_4_10__CSI2_D13 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL)
165#define MX51_PAD_GPIO_4_11__CSI2_D14 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL)
166#define MX51_PAD_GPIO_4_12__CSI2_D15 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
167#define MX51_PAD_GPIO_4_11__CSI2_D16 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL)
168#define MX51_PAD_GPIO_4_12__CSI2_D17 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL)
169#define MX51_PAD_GPIO_4_11__CSI2_D18 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL)
170#define MX51_PAD_GPIO_4_12__CSI2_D19 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL)
171#define MX51_PAD_GPIO_4_13__CSI2_VSYNC IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL)
172#define MX51_PAD_GPIO_4_14__CSI2_HSYNC IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL)
173#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL)
174#define MX51_PAD_CSI2_PKE0__CSI2_PKE0 IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
175#define MX51_PAD_GPIO_4_16__I2C1_CLK IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL)
176#define MX51_PAD_GPIO_4_17__I2C1_DAT IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
177#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
178#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
179#define MX51_PAD_GPIO_4_20__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
180#define MX51_PAD_GPIO_4_21__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
181#define MX51_PAD_GPIO_4_22__CSPI1_MOSI IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
182#define MX51_PAD_GPIO_4_23__CSPI1_MISO IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
183#define MX51_PAD_GPIO_4_24__CSPI1_SS0 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
184#define MX51_PAD_GPIO_4_25__CSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
185#define MX51_PAD_GPIO_4_26__CSPI1_RDY IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
186#define MX51_PAD_GPIO_4_27__CSPI1_SCLK IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
187
188/* Babbage UART1 */
189#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
190#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
191#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
192#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL)
193
194/* Babbage UART2 */
195#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
196#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
197
198#define MX51_PAD_GPIO_1_22__UART3_RXD IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
199#define MX51_PAD_GPIO_1_23__UART3_TXD IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
200#define MX51_PAD_GPIO_1_24__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
201#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
202#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
203#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
204#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
205#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
206#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
207#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
208#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
209#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
210#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
211#define MX51_PAD_GPIO_1_25__USBH1_CLK IOMUX_PAD(0x678, 0x278, 2, 0x0, 0, NO_PAD_CTRL)
212#define MX51_PAD_GPIO_1_26__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 2, 0x0, 0, NO_PAD_CTRL)
213#define MX51_PAD_GPIO_1_27__USBH1_STP IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, NO_PAD_CTRL)
214#define MX51_PAD_GPIO_1_28__USBH1_NXT IOMUX_PAD(0x684, 0x284, 2, 0x0, 0, NO_PAD_CTRL)
215#define MX51_PAD_GPIO_1_11__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 2, 0x0, 0, NO_PAD_CTRL)
216#define MX51_PAD_GPIO_1_12__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 2, 0x0, 0, NO_PAD_CTRL)
217#define MX51_PAD_GPIO_1_13__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 2, 0x0, 0, NO_PAD_CTRL)
218#define MX51_PAD_GPIO_1_14__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 2, 0x0, 0, NO_PAD_CTRL)
219#define MX51_PAD_GPIO_1_15__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 2, 0x0, 0, NO_PAD_CTRL)
220#define MX51_PAD_GPIO_1_16__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 2, 0x0, 0, NO_PAD_CTRL)
221#define MX51_PAD_GPIO_1_17__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 2, 0x0, 0, NO_PAD_CTRL)
222#define MX51_PAD_GPIO_1_18__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 2, 0x0, 0, NO_PAD_CTRL)
223#define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
224#define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
225#define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
226#define MX51_PAD_GPIO_3_3__DI1_D0_CS IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL)
227#define MX51_PAD_GPIO_3_4__DI1_D1_CS IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL)
228#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL)
229#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL)
230#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL)
231#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL)
232#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
233#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
234#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
235#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
236#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
237#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
238#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
239#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
240#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
241#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
242#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
243#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
244#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
245#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
246#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
247#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
248#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
249#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
250#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
251#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
252#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
253#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
254#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
255#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
256#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
257#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
258#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
259#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
260#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
261#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
262#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
263#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
264#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
265#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
266#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
267#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
268#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
269#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
270#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
271#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
272#define MX51_PAD_GPIO_1_19__DISP2_DAT6 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL)
273#define MX51_PAD_GPIO_1_29__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL)
274#define MX51_PAD_GPIO_1_30__DISP2_DAT8 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL)
275#define MX51_PAD_GPIO_1_31__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL)
276#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
277#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
278#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
279#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
280#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
281#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
282#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
283#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
284#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
285#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
286#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
287#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
288#define MX51_PAD_GPIO_1_0__GPIO1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
289#define MX51_PAD_GPIO_1_1__GPIO1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
290#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
291#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)
292#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL)
293#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL)
294#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL)
295#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL)
296#define MX51_PAD_GPIO_1_2__GPIO1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
297#define MX51_PAD_GPIO_1_3__GPIO1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
298#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
299#define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
300#define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
301#define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
302#define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, NO_PAD_CTRL)
303#define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
304 (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS))
305#define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
306
307/* EIM */
308#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL)
309#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL)
310#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL)
311#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL)
312#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL)
313#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL)
314#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL)
315#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL)
316
317#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL)
318#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL)
319#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL)
320#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL)
321#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL)
322#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL)
323#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL)
324#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL)
325
326#endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 1deda0184892..f2f73d31d5ba 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -81,11 +81,13 @@ struct pad_desc {
81 81
82#define PAD_CTL_ODE (1 << 3) 82#define PAD_CTL_ODE (1 << 3)
83 83
84#define PAD_CTL_DSE_STANDARD (0 << 1) 84#define PAD_CTL_DSE_LOW (0 << 1)
85#define PAD_CTL_DSE_HIGH (1 << 1) 85#define PAD_CTL_DSE_MED (1 << 1)
86#define PAD_CTL_DSE_MAX (2 << 1) 86#define PAD_CTL_DSE_HIGH (2 << 1)
87#define PAD_CTL_DSE_MAX (3 << 1)
87 88
88#define PAD_CTL_SRE_FAST (1 << 0) 89#define PAD_CTL_SRE_FAST (1 << 0)
90#define PAD_CTL_SRE_SLOW (0 << 0)
89 91
90/* 92/*
91 * setups a single pad in the iomuxer 93 * setups a single pad in the iomuxer
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index 0cb347645db4..a3ad643de5a1 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -12,9 +12,13 @@
12#define __ASM_ARCH_MXC_IRQS_H__ 12#define __ASM_ARCH_MXC_IRQS_H__
13 13
14/* 14/*
15 * So far all i.MX SoCs have 64 internal interrupts 15 * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64
16 */ 16 */
17#ifdef CONFIG_MXC_TZIC
18#define MXC_INTERNAL_IRQS 128
19#else
17#define MXC_INTERNAL_IRQS 64 20#define MXC_INTERNAL_IRQS 64
21#endif
18 22
19#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS 23#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
20 24
@@ -26,6 +30,8 @@
26#define MXC_GPIO_IRQS (32 * 3) 30#define MXC_GPIO_IRQS (32 * 3)
27#elif defined CONFIG_ARCH_MX25 31#elif defined CONFIG_ARCH_MX25
28#define MXC_GPIO_IRQS (32 * 4) 32#define MXC_GPIO_IRQS (32 * 4)
33#elif defined CONFIG_ARCH_MX5
34#define MXC_GPIO_IRQS (32 * 4)
29#elif defined CONFIG_ARCH_MXC91231 35#elif defined CONFIG_ARCH_MXC91231
30#define MXC_GPIO_IRQS (32 * 4) 36#define MXC_GPIO_IRQS (32 * 4)
31#endif 37#endif
@@ -51,6 +57,7 @@
51#else 57#else
52#define MX3_IPU_IRQS 0 58#define MX3_IPU_IRQS 0
53#endif 59#endif
60/* REVISIT: Add IPU irqs on IMX51 */
54 61
55#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) 62#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
56 63
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 002eb91ab235..7cae9cb6208d 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -16,6 +16,7 @@
16#define MX25_PHYS_OFFSET UL(0x80000000) 16#define MX25_PHYS_OFFSET UL(0x80000000)
17#define MX27_PHYS_OFFSET UL(0xa0000000) 17#define MX27_PHYS_OFFSET UL(0xa0000000)
18#define MX3x_PHYS_OFFSET UL(0x80000000) 18#define MX3x_PHYS_OFFSET UL(0x80000000)
19#define MX51_PHYS_OFFSET UL(0x90000000)
19#define MXC91231_PHYS_OFFSET UL(0x90000000) 20#define MXC91231_PHYS_OFFSET UL(0x90000000)
20 21
21#if !defined(CONFIG_RUNTIME_PHYS_OFFSET) 22#if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
@@ -31,6 +32,8 @@
31# define PHYS_OFFSET MX3x_PHYS_OFFSET 32# define PHYS_OFFSET MX3x_PHYS_OFFSET
32# elif defined CONFIG_ARCH_MXC91231 33# elif defined CONFIG_ARCH_MXC91231
33# define PHYS_OFFSET MXC91231_PHYS_OFFSET 34# define PHYS_OFFSET MXC91231_PHYS_OFFSET
35# elif defined CONFIG_ARCH_MX5
36# define PHYS_OFFSET MX51_PHYS_OFFSET
34# endif 37# endif
35#endif 38#endif
36 39
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
new file mode 100644
index 000000000000..771532b6b4a6
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -0,0 +1,454 @@
1#ifndef __ASM_ARCH_MXC_MX51_H__
2#define __ASM_ARCH_MXC_MX51_H__
3
4/*
5 * MX51 memory map:
6 *
7 *
8 * Virt Phys Size What
9 * ---------------------------------------------------------------------------
10 * FA3E0000 1FFE0000 128K IRAM (SCCv2 RAM)
11 * 30000000 256M GPU
12 * 40000000 512M IPU
13 * FA200000 60000000 1M DEBUG
14 * FB100000 70000000 1M SPBA 0
15 * FB000000 73F00000 1M AIPS 1
16 * FB200000 83F00000 1M AIPS 2
17 * FA100000 8FFFC000 16K TZIC (interrupt controller)
18 * 90000000 256M CSD0 SDRAM/DDR
19 * A0000000 256M CSD1 SDRAM/DDR
20 * B0000000 128M CS0 Flash
21 * B8000000 128M CS1 Flash
22 * C0000000 128M CS2 Flash
23 * C8000000 64M CS3 Flash
24 * CC000000 32M CS4 SRAM
25 * CE000000 32M CS5 SRAM
26 * F9000000 CFFF0000 64K NFC (NAND Flash AXI)
27 *
28 */
29
30/*
31 * IRAM
32 */
33#define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
34#define MX51_IRAM_BASE_ADDR_VIRT 0xFA3E0000
35#define MX51_IRAM_PARTITIONS 16
36#define MX51_IRAM_PARTITIONS_TO1 12
37#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
38
39/*
40 * NFC
41 */
42#define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */
43#define MX51_NFC_AXI_BASE_ADDR_VIRT 0xF9000000
44#define MX51_NFC_AXI_SIZE SZ_64K
45
46/*
47 * Graphics Memory of GPU
48 */
49#define MX51_GPU_BASE_ADDR 0x20000000
50#define MX51_GPU2D_BASE_ADDR 0xD0000000
51
52#define MX51_TZIC_BASE_ADDR 0x8FFFC000
53#define MX51_TZIC_BASE_ADDR_VIRT 0xFA100000
54#define MX51_TZIC_SIZE SZ_16K
55
56#define MX51_DEBUG_BASE_ADDR 0x60000000
57#define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000
58#define MX51_DEBUG_SIZE SZ_1M
59#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00001000)
60#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00002000)
61#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00003000)
62#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00004000)
63#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00005000)
64#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00006000)
65#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00007000)
66#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00008000)
67
68/*
69 * SPBA global module enabled #0
70 */
71#define MX51_SPBA0_BASE_ADDR 0x70000000
72#define MX51_SPBA0_BASE_ADDR_VIRT 0xFB100000
73#define MX51_SPBA0_SIZE SZ_1M
74
75#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000)
76#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000)
77#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000)
78#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000)
79#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000)
80#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000)
81#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000)
82#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00028000)
83#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00030000)
84#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00034000)
85#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00038000)
86#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000)
87
88/*
89 * defines for SPBA modules
90 */
91#define MX51_SPBA_SDHC1 0x04
92#define MX51_SPBA_SDHC2 0x08
93#define MX51_SPBA_UART3 0x0C
94#define MX51_SPBA_CSPI1 0x10
95#define MX51_SPBA_SSI2 0x14
96#define MX51_SPBA_SDHC3 0x20
97#define MX51_SPBA_SDHC4 0x24
98#define MX51_SPBA_SPDIF 0x28
99#define MX51_SPBA_ATA 0x30
100#define MX51_SPBA_SLIM 0x34
101#define MX51_SPBA_HSI2C 0x38
102#define MX51_SPBA_CTRL 0x3C
103
104/*
105 * AIPS 1
106 */
107#define MX51_AIPS1_BASE_ADDR 0x73F00000
108#define MX51_AIPS1_BASE_ADDR_VIRT 0xFB000000
109#define MX51_AIPS1_SIZE SZ_1M
110
111#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00080000)
112#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00084000)
113#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00088000)
114#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0008C000)
115#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00090000)
116#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00094000)
117#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00098000)
118#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0009C000)
119#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A0000)
120#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A4000)
121#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A8000)
122#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000AC000)
123#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B0000)
124#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B4000)
125#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B8000)
126#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000BC000)
127#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000C0000)
128#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D0000)
129#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D4000)
130#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D8000)
131
132/*
133 * Defines for modules using static and dynamic DMA channels
134 */
135#define MX51_MXC_DMA_CHANNEL_IRAM 30
136#define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL
137#define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL
138#define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL
139#define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL
140#define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL
141#define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL
142#define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL
143#define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL
144#define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL
145#define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL
146#define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL
147#define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL
148#ifdef CONFIG_SDMA_IRAM
149#define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1)
150#else /*CONFIG_SDMA_IRAM */
151#define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL
152#endif /*CONFIG_SDMA_IRAM */
153#define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL
154#define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL
155#define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL
156#define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL
157#define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL
158#define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL
159#define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL
160#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL
161#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL
162
163/*
164 * AIPS 2
165 */
166#define MX51_AIPS2_BASE_ADDR 0x83F00000
167#define MX51_AIPS2_BASE_ADDR_VIRT 0xFB200000
168#define MX51_AIPS2_SIZE SZ_1M
169
170#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00080000)
171#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00084000)
172#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00088000)
173#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00094000)
174#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00098000)
175#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x0009C000)
176#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A0000)
177#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000)
178#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A8000)
179#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000)
180#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B0000)
181#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B4000)
182#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B8000)
183#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000BC000)
184#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000)
185#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C4000)
186#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C8000)
187#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000CC000)
188#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D0000)
189#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D8000)
190#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D9000)
191#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DA000)
192#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DB000)
193#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DBF00)
194#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000)
195#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E0000)
196#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E4000)
197#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E8000)
198#define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000EC000)
199#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F0000)
200#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F4000)
201#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000)
202
203/*
204 * Memory regions and CS
205 */
206#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
207#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
208#define MX51_CSD0_BASE_ADDR 0x90000000
209#define MX51_CSD1_BASE_ADDR 0xA0000000
210#define MX51_CS0_BASE_ADDR 0xB0000000
211#define MX51_CS1_BASE_ADDR 0xB8000000
212#define MX51_CS2_BASE_ADDR 0xC0000000
213#define MX51_CS3_BASE_ADDR 0xC8000000
214#define MX51_CS4_BASE_ADDR 0xCC000000
215#define MX51_CS5_BASE_ADDR 0xCE000000
216
217/* Does given address belongs to the specified memory region? */
218#define ADDRESS_IN_REGION(addr, start, size) \
219 (((addr) >= (start)) && ((addr) < (start)+(size)))
220
221/* Does given address belongs to the specified named `module'? */
222#define MX51_IS_MODULE(addr, module) \
223 ADDRESS_IN_REGION(addr, MX51_ ## module ## _BASE_ADDR, \
224 MX51_ ## module ## _SIZE)
225/*
226 * This macro defines the physical to virtual address mapping for all the
227 * peripheral modules. It is used by passing in the physical address as x
228 * and returning the virtual address. If the physical address is not mapped,
229 * it returns 0xDEADBEEF
230 */
231
232#define MX51_IO_ADDRESS(x) \
233 (void __iomem *) \
234 (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \
235 MX51_IS_MODULE(x, TZIC) ? MX51_TZIC_IO_ADDRESS(x) : \
236 MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \
237 MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \
238 MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \
239 MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
240 MX51_IS_MODULE(x, NFC_AXI) ? MX51_NFC_AXI_IO_ADDRESS(x) : \
241 0xDEADBEEF)
242
243/*
244 * define the address mapping macros: in physical address order
245 */
246#define MX51_IRAM_IO_ADDRESS(x) \
247 (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)
248
249#define MX51_TZIC_IO_ADDRESS(x) \
250 (((x) - MX51_TZIC_BASE_ADDR) + MX51_TZIC_BASE_ADDR_VIRT)
251
252#define MX51_DEBUG_IO_ADDRESS(x) \
253 (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)
254
255#define MX51_SPBA0_IO_ADDRESS(x) \
256 (((x) - MX51_SPBA0_BASE_ADDR) + MX51_SPBA0_BASE_ADDR_VIRT)
257
258#define MX51_AIPS1_IO_ADDRESS(x) \
259 (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
260
261#define MX51_AIPS2_IO_ADDRESS(x) \
262 (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT)
263
264#define MX51_NFC_AXI_IO_ADDRESS(x) \
265 (((x) - MX51_NFC_AXI_BASE_ADDR) + MX51_NFC_AXI_BASE_ADDR_VIRT)
266
267#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0
268
269/*
270 * DMA request assignments
271 */
272#define MX51_DMA_REQ_SSI3_TX1 47
273#define MX51_DMA_REQ_SSI3_RX1 46
274#define MX51_DMA_REQ_SPDIF 45
275#define MX51_DMA_REQ_UART3_TX 44
276#define MX51_DMA_REQ_UART3_RX 43
277#define MX51_DMA_REQ_SLIM_B_TX 42
278#define MX51_DMA_REQ_SDHC4 41
279#define MX51_DMA_REQ_SDHC3 40
280#define MX51_DMA_REQ_CSPI_TX 39
281#define MX51_DMA_REQ_CSPI_RX 38
282#define MX51_DMA_REQ_SSI3_TX2 37
283#define MX51_DMA_REQ_IPU 36
284#define MX51_DMA_REQ_SSI3_RX2 35
285#define MX51_DMA_REQ_EPIT2 34
286#define MX51_DMA_REQ_CTI2_1 33
287#define MX51_DMA_REQ_EMI_WR 32
288#define MX51_DMA_REQ_CTI2_0 31
289#define MX51_DMA_REQ_EMI_RD 30
290#define MX51_DMA_REQ_SSI1_TX1 29
291#define MX51_DMA_REQ_SSI1_RX1 28
292#define MX51_DMA_REQ_SSI1_TX2 27
293#define MX51_DMA_REQ_SSI1_RX2 26
294#define MX51_DMA_REQ_SSI2_TX1 25
295#define MX51_DMA_REQ_SSI2_RX1 24
296#define MX51_DMA_REQ_SSI2_TX2 23
297#define MX51_DMA_REQ_SSI2_RX2 22
298#define MX51_DMA_REQ_SDHC2 21
299#define MX51_DMA_REQ_SDHC1 20
300#define MX51_DMA_REQ_UART1_TX 19
301#define MX51_DMA_REQ_UART1_RX 18
302#define MX51_DMA_REQ_UART2_TX 17
303#define MX51_DMA_REQ_UART2_RX 16
304#define MX51_DMA_REQ_GPU 15
305#define MX51_DMA_REQ_EXTREQ1 14
306#define MX51_DMA_REQ_FIRI_TX 13
307#define MX51_DMA_REQ_FIRI_RX 12
308#define MX51_DMA_REQ_HS_I2C_RX 11
309#define MX51_DMA_REQ_HS_I2C_TX 10
310#define MX51_DMA_REQ_CSPI2_TX 9
311#define MX51_DMA_REQ_CSPI2_RX 8
312#define MX51_DMA_REQ_CSPI1_TX 7
313#define MX51_DMA_REQ_CSPI1_RX 6
314#define MX51_DMA_REQ_SLIM_B 5
315#define MX51_DMA_REQ_ATA_TX_END 4
316#define MX51_DMA_REQ_ATA_TX 3
317#define MX51_DMA_REQ_ATA_RX 2
318#define MX51_DMA_REQ_GPC 1
319#define MX51_DMA_REQ_VPU 0
320
321/*
322 * Interrupt numbers
323 */
324#define MX51_MXC_INT_BASE 0
325#define MX51_MXC_INT_RESV0 0
326#define MX51_MXC_INT_MMC_SDHC1 1
327#define MX51_MXC_INT_MMC_SDHC2 2
328#define MX51_MXC_INT_MMC_SDHC3 3
329#define MX51_MXC_INT_MMC_SDHC4 4
330#define MX51_MXC_INT_RESV5 5
331#define MX51_MXC_INT_SDMA 6
332#define MX51_MXC_INT_IOMUX 7
333#define MX51_MXC_INT_NFC 8
334#define MX51_MXC_INT_VPU 9
335#define MX51_MXC_INT_IPU_ERR 10
336#define MX51_MXC_INT_IPU_SYN 11
337#define MX51_MXC_INT_GPU 12
338#define MX51_MXC_INT_RESV13 13
339#define MX51_MXC_INT_USB_H1 14
340#define MX51_MXC_INT_EMI 15
341#define MX51_MXC_INT_USB_H2 16
342#define MX51_MXC_INT_USB_H3 17
343#define MX51_MXC_INT_USB_OTG 18
344#define MX51_MXC_INT_SAHARA_H0 19
345#define MX51_MXC_INT_SAHARA_H1 20
346#define MX51_MXC_INT_SCC_SMN 21
347#define MX51_MXC_INT_SCC_STZ 22
348#define MX51_MXC_INT_SCC_SCM 23
349#define MX51_MXC_INT_SRTC_NTZ 24
350#define MX51_MXC_INT_SRTC_TZ 25
351#define MX51_MXC_INT_RTIC 26
352#define MX51_MXC_INT_CSU 27
353#define MX51_MXC_INT_SLIM_B 28
354#define MX51_MXC_INT_SSI1 29
355#define MX51_MXC_INT_SSI2 30
356#define MX51_MXC_INT_UART1 31
357#define MX51_MXC_INT_UART2 32
358#define MX51_MXC_INT_UART3 33
359#define MX51_MXC_INT_RESV34 34
360#define MX51_MXC_INT_RESV35 35
361#define MX51_MXC_INT_CSPI1 36
362#define MX51_MXC_INT_CSPI2 37
363#define MX51_MXC_INT_CSPI 38
364#define MX51_MXC_INT_GPT 39
365#define MX51_MXC_INT_EPIT1 40
366#define MX51_MXC_INT_EPIT2 41
367#define MX51_MXC_INT_GPIO1_INT7 42
368#define MX51_MXC_INT_GPIO1_INT6 43
369#define MX51_MXC_INT_GPIO1_INT5 44
370#define MX51_MXC_INT_GPIO1_INT4 45
371#define MX51_MXC_INT_GPIO1_INT3 46
372#define MX51_MXC_INT_GPIO1_INT2 47
373#define MX51_MXC_INT_GPIO1_INT1 48
374#define MX51_MXC_INT_GPIO1_INT0 49
375#define MX51_MXC_INT_GPIO1_LOW 50
376#define MX51_MXC_INT_GPIO1_HIGH 51
377#define MX51_MXC_INT_GPIO2_LOW 52
378#define MX51_MXC_INT_GPIO2_HIGH 53
379#define MX51_MXC_INT_GPIO3_LOW 54
380#define MX51_MXC_INT_GPIO3_HIGH 55
381#define MX51_MXC_INT_GPIO4_LOW 56
382#define MX51_MXC_INT_GPIO4_HIGH 57
383#define MX51_MXC_INT_WDOG1 58
384#define MX51_MXC_INT_WDOG2 59
385#define MX51_MXC_INT_KPP 60
386#define MX51_MXC_INT_PWM1 61
387#define MX51_MXC_INT_I2C1 62
388#define MX51_MXC_INT_I2C2 63
389#define MX51_MXC_INT_HS_I2C 64
390#define MX51_MXC_INT_RESV65 65
391#define MX51_MXC_INT_RESV66 66
392#define MX51_MXC_INT_SIM_IPB 67
393#define MX51_MXC_INT_SIM_DAT 68
394#define MX51_MXC_INT_IIM 69
395#define MX51_MXC_INT_ATA 70
396#define MX51_MXC_INT_CCM1 71
397#define MX51_MXC_INT_CCM2 72
398#define MX51_MXC_INT_GPC1 73
399#define MX51_MXC_INT_GPC2 74
400#define MX51_MXC_INT_SRC 75
401#define MX51_MXC_INT_NM 76
402#define MX51_MXC_INT_PMU 77
403#define MX51_MXC_INT_CTI_IRQ 78
404#define MX51_MXC_INT_CTI1_TG0 79
405#define MX51_MXC_INT_CTI1_TG1 80
406#define MX51_MXC_INT_MCG_ERR 81
407#define MX51_MXC_INT_MCG_TMR 82
408#define MX51_MXC_INT_MCG_FUNC 83
409#define MX51_MXC_INT_GPU2_IRQ 84
410#define MX51_MXC_INT_GPU2_BUSY 85
411#define MX51_MXC_INT_RESV86 86
412#define MX51_MXC_INT_FEC 87
413#define MX51_MXC_INT_OWIRE 88
414#define MX51_MXC_INT_CTI1_TG2 89
415#define MX51_MXC_INT_SJC 90
416#define MX51_MXC_INT_SPDIF 91
417#define MX51_MXC_INT_TVE 92
418#define MX51_MXC_INT_FIRI 93
419#define MX51_MXC_INT_PWM2 94
420#define MX51_MXC_INT_SLIM_EXP 95
421#define MX51_MXC_INT_SSI3 96
422#define MX51_MXC_INT_EMI_BOOT 97
423#define MX51_MXC_INT_CTI1_TG3 98
424#define MX51_MXC_INT_SMC_RX 99
425#define MX51_MXC_INT_VPU_IDLE 100
426#define MX51_MXC_INT_EMI_NFC 101
427#define MX51_MXC_INT_GPU_IDLE 102
428
429/* silicon revisions specific to i.MX51 */
430#define MX51_CHIP_REV_1_0 0x10
431#define MX51_CHIP_REV_1_1 0x11
432#define MX51_CHIP_REV_1_2 0x12
433#define MX51_CHIP_REV_1_3 0x13
434#define MX51_CHIP_REV_2_0 0x20
435#define MX51_CHIP_REV_2_1 0x21
436#define MX51_CHIP_REV_2_2 0x22
437#define MX51_CHIP_REV_2_3 0x23
438#define MX51_CHIP_REV_3_0 0x30
439#define MX51_CHIP_REV_3_1 0x31
440#define MX51_CHIP_REV_3_2 0x32
441
442/* Mandatory defines used globally */
443
444#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
445
446extern unsigned int system_rev;
447
448static inline unsigned int mx51_revision(void)
449{
450 return system_rev;
451}
452#endif
453
454#endif /* __ASM_ARCH_MXC_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 800ae2a33b15..a790bf212972 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -30,6 +30,7 @@
30#define MXC_CPU_MX27 27 30#define MXC_CPU_MX27 27
31#define MXC_CPU_MX31 31 31#define MXC_CPU_MX31 31
32#define MXC_CPU_MX35 35 32#define MXC_CPU_MX35 35
33#define MXC_CPU_MX51 51
33#define MXC_CPU_MXC91231 91231 34#define MXC_CPU_MXC91231 91231
34 35
35#ifndef __ASSEMBLY__ 36#ifndef __ASSEMBLY__
@@ -108,6 +109,18 @@ extern unsigned int __mxc_cpu_type;
108# define cpu_is_mx35() (0) 109# define cpu_is_mx35() (0)
109#endif 110#endif
110 111
112#ifdef CONFIG_ARCH_MX5
113# ifdef mxc_cpu_type
114# undef mxc_cpu_type
115# define mxc_cpu_type __mxc_cpu_type
116# else
117# define mxc_cpu_type MXC_CPU_MX51
118# endif
119# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51)
120#else
121# define cpu_is_mx51() (0)
122#endif
123
111#ifdef CONFIG_ARCH_MXC91231 124#ifdef CONFIG_ARCH_MXC91231
112# ifdef mxc_cpu_type 125# ifdef mxc_cpu_type
113# undef mxc_cpu_type 126# undef mxc_cpu_type
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 527a6c24788e..024416ed11cd 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -28,6 +28,8 @@
28#define CLOCK_TICK_RATE 16625000 28#define CLOCK_TICK_RATE 16625000
29#elif defined CONFIG_ARCH_MX25 29#elif defined CONFIG_ARCH_MX25
30#define CLOCK_TICK_RATE 16000000 30#define CLOCK_TICK_RATE 16000000
31#elif defined CONFIG_ARCH_MX5
32#define CLOCK_TICK_RATE 8000000
31#elif defined CONFIG_ARCH_MXC91231 33#elif defined CONFIG_ARCH_MXC91231
32#define CLOCK_TICK_RATE 13000000 34#define CLOCK_TICK_RATE 13000000
33#endif 35#endif
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 844567ee35fe..c1ce51abdba6 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -30,9 +30,15 @@
30#include <asm/mach/time.h> 30#include <asm/mach/time.h>
31#include <mach/common.h> 31#include <mach/common.h>
32 32
33/*
34 * There are 2 versions of the timer hardware on Freescale MXC hardware.
35 * Version 1: MX1/MXL, MX21, MX27.
36 * Version 2: MX25, MX31, MX35, MX37, MX51
37 */
38
33/* defines common for all i.MX */ 39/* defines common for all i.MX */
34#define MXC_TCTL 0x00 40#define MXC_TCTL 0x00
35#define MXC_TCTL_TEN (1 << 0) 41#define MXC_TCTL_TEN (1 << 0) /* Enable module */
36#define MXC_TPRER 0x04 42#define MXC_TPRER 0x04
37 43
38/* MX1, MX21, MX27 */ 44/* MX1, MX21, MX27 */
@@ -47,8 +53,8 @@
47#define MX2_TSTAT_CAPT (1 << 1) 53#define MX2_TSTAT_CAPT (1 << 1)
48#define MX2_TSTAT_COMP (1 << 0) 54#define MX2_TSTAT_COMP (1 << 0)
49 55
50/* MX31, MX35, MX25, MXC91231 */ 56/* MX31, MX35, MX25, MXC91231, MX5 */
51#define MX3_TCTL_WAITEN (1 << 3) 57#define MX3_TCTL_WAITEN (1 << 3) /* Wait enable mode */
52#define MX3_TCTL_CLK_IPG (1 << 6) 58#define MX3_TCTL_CLK_IPG (1 << 6)
53#define MX3_TCTL_FRR (1 << 9) 59#define MX3_TCTL_FRR (1 << 9)
54#define MX3_IR 0x0c 60#define MX3_IR 0x0c
@@ -57,6 +63,9 @@
57#define MX3_TCN 0x24 63#define MX3_TCN 0x24
58#define MX3_TCMP 0x10 64#define MX3_TCMP 0x10
59 65
66#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
67#define timer_is_v2() (!timer_is_v1())
68
60static struct clock_event_device clockevent_mxc; 69static struct clock_event_device clockevent_mxc;
61static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; 70static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
62 71
@@ -66,7 +75,7 @@ static inline void gpt_irq_disable(void)
66{ 75{
67 unsigned int tmp; 76 unsigned int tmp;
68 77
69 if (cpu_is_mx3() || cpu_is_mx25()) 78 if (timer_is_v2())
70 __raw_writel(0, timer_base + MX3_IR); 79 __raw_writel(0, timer_base + MX3_IR);
71 else { 80 else {
72 tmp = __raw_readl(timer_base + MXC_TCTL); 81 tmp = __raw_readl(timer_base + MXC_TCTL);
@@ -76,7 +85,7 @@ static inline void gpt_irq_disable(void)
76 85
77static inline void gpt_irq_enable(void) 86static inline void gpt_irq_enable(void)
78{ 87{
79 if (cpu_is_mx3() || cpu_is_mx25()) 88 if (timer_is_v2())
80 __raw_writel(1<<0, timer_base + MX3_IR); 89 __raw_writel(1<<0, timer_base + MX3_IR);
81 else { 90 else {
82 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, 91 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
@@ -86,11 +95,13 @@ static inline void gpt_irq_enable(void)
86 95
87static void gpt_irq_acknowledge(void) 96static void gpt_irq_acknowledge(void)
88{ 97{
89 if (cpu_is_mx1()) 98 if (timer_is_v1()) {
90 __raw_writel(0, timer_base + MX1_2_TSTAT); 99 if (cpu_is_mx1())
91 if (cpu_is_mx2()) 100 __raw_writel(0, timer_base + MX1_2_TSTAT);
92 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT); 101 else
93 if (cpu_is_mx3() || cpu_is_mx25()) 102 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
103 timer_base + MX1_2_TSTAT);
104 } else if (timer_is_v2())
94 __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT); 105 __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT);
95} 106}
96 107
@@ -117,7 +128,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
117{ 128{
118 unsigned int c = clk_get_rate(timer_clk); 129 unsigned int c = clk_get_rate(timer_clk);
119 130
120 if (cpu_is_mx3() || cpu_is_mx25()) 131 if (timer_is_v2())
121 clocksource_mxc.read = mx3_get_cycles; 132 clocksource_mxc.read = mx3_get_cycles;
122 133
123 clocksource_mxc.mult = clocksource_hz2mult(c, 134 clocksource_mxc.mult = clocksource_hz2mult(c,
@@ -180,7 +191,7 @@ static void mxc_set_mode(enum clock_event_mode mode,
180 191
181 if (mode != clockevent_mode) { 192 if (mode != clockevent_mode) {
182 /* Set event time into far-far future */ 193 /* Set event time into far-far future */
183 if (cpu_is_mx3() || cpu_is_mx25()) 194 if (timer_is_v2())
184 __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3, 195 __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3,
185 timer_base + MX3_TCMP); 196 timer_base + MX3_TCMP);
186 else 197 else
@@ -233,7 +244,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
233 struct clock_event_device *evt = &clockevent_mxc; 244 struct clock_event_device *evt = &clockevent_mxc;
234 uint32_t tstat; 245 uint32_t tstat;
235 246
236 if (cpu_is_mx3() || cpu_is_mx25()) 247 if (timer_is_v2())
237 tstat = __raw_readl(timer_base + MX3_TSTAT); 248 tstat = __raw_readl(timer_base + MX3_TSTAT);
238 else 249 else
239 tstat = __raw_readl(timer_base + MX1_2_TSTAT); 250 tstat = __raw_readl(timer_base + MX1_2_TSTAT);
@@ -264,7 +275,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
264{ 275{
265 unsigned int c = clk_get_rate(timer_clk); 276 unsigned int c = clk_get_rate(timer_clk);
266 277
267 if (cpu_is_mx3() || cpu_is_mx25()) 278 if (timer_is_v2())
268 clockevent_mxc.set_next_event = mx3_set_next_event; 279 clockevent_mxc.set_next_event = mx3_set_next_event;
269 280
270 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, 281 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
@@ -296,7 +307,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
296 __raw_writel(0, timer_base + MXC_TCTL); 307 __raw_writel(0, timer_base + MXC_TCTL);
297 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ 308 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
298 309
299 if (cpu_is_mx3() || cpu_is_mx25()) 310 if (timer_is_v2())
300 tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; 311 tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN;
301 else 312 else
302 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; 313 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
new file mode 100644
index 000000000000..afa6709db0b3
--- /dev/null
+++ b/arch/arm/plat-mxc/tzic.c
@@ -0,0 +1,172 @@
1/*
2 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/device.h>
16#include <linux/errno.h>
17#include <linux/io.h>
18
19#include <asm/mach/irq.h>
20
21#include <mach/hardware.h>
22
23/*
24 *****************************************
25 * TZIC Registers *
26 *****************************************
27 */
28
29#define TZIC_INTCNTL 0x0000 /* Control register */
30#define TZIC_INTTYPE 0x0004 /* Controller Type register */
31#define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */
32#define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */
33#define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */
34#define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */
35#define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
36#define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
37#define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
38#define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */
39#define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */
40#define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */
41#define TZIC_PND0 0x0D00 /* Pending Register 0 */
42#define TZIC_HIPND0 0x0D80 /* High Priority Pending Register */
43#define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */
44#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
45#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
46
47void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
48
49/**
50 * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC
51 *
52 * @param irq interrupt source number
53 */
54static void tzic_mask_irq(unsigned int irq)
55{
56 int index, off;
57
58 index = irq >> 5;
59 off = irq & 0x1F;
60 __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index));
61}
62
63/**
64 * tzic_unmask_irq() - Enable interrupt number "irq" in the TZIC
65 *
66 * @param irq interrupt source number
67 */
68static void tzic_unmask_irq(unsigned int irq)
69{
70 int index, off;
71
72 index = irq >> 5;
73 off = irq & 0x1F;
74 __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index));
75}
76
77static unsigned int wakeup_intr[4];
78
79/**
80 * tzic_set_wake_irq() - Set interrupt number "irq" in the TZIC as a wake-up source.
81 *
82 * @param irq interrupt source number
83 * @param enable enable as wake-up if equal to non-zero
84 * disble as wake-up if equal to zero
85 *
86 * @return This function returns 0 on success.
87 */
88static int tzic_set_wake_irq(unsigned int irq, unsigned int enable)
89{
90 unsigned int index, off;
91
92 index = irq >> 5;
93 off = irq & 0x1F;
94
95 if (index > 3)
96 return -EINVAL;
97
98 if (enable)
99 wakeup_intr[index] |= (1 << off);
100 else
101 wakeup_intr[index] &= ~(1 << off);
102
103 return 0;
104}
105
106static struct irq_chip mxc_tzic_chip = {
107 .name = "MXC_TZIC",
108 .ack = tzic_mask_irq,
109 .mask = tzic_mask_irq,
110 .unmask = tzic_unmask_irq,
111 .set_wake = tzic_set_wake_irq,
112};
113
114/*
115 * This function initializes the TZIC hardware and disables all the
116 * interrupts. It registers the interrupt enable and disable functions
117 * to the kernel for each interrupt source.
118 */
119void __init tzic_init_irq(void __iomem *irqbase)
120{
121 int i;
122
123 tzic_base = irqbase;
124 /* put the TZIC into the reset value with
125 * all interrupts disabled
126 */
127 i = __raw_readl(tzic_base + TZIC_INTCNTL);
128
129 __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL);
130 __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK);
131 __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL);
132
133 for (i = 0; i < 4; i++)
134 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
135
136 /* disable all interrupts */
137 for (i = 0; i < 4; i++)
138 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
139
140 /* all IRQ no FIQ Warning :: No selection */
141
142 for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
143 set_irq_chip(i, &mxc_tzic_chip);
144 set_irq_handler(i, handle_level_irq);
145 set_irq_flags(i, IRQF_VALID);
146 }
147
148 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
149}
150
151/**
152 * tzic_enable_wake() - enable wakeup interrupt
153 *
154 * @param is_idle 1 if called in idle loop (ENSET0 register);
155 * 0 to be used when called from low power entry
156 * @return 0 if successful; non-zero otherwise
157 */
158int tzic_enable_wake(int is_idle)
159{
160 unsigned int i, v;
161
162 __raw_writel(1, tzic_base + TZIC_DSMINT);
163 if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
164 return -EAGAIN;
165
166 for (i = 0; i < 4; i++) {
167 v = is_idle ? __raw_readl(TZIC_ENSET0(i)) : wakeup_intr[i];
168 __raw_writel(v, TZIC_WAKEUP0(i));
169 }
170
171 return 0;
172}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 04:56:57 -0500