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authorMike Frysinger <vapier@gentoo.org>2009-10-15 02:47:28 -0400
committerMike Frysinger <vapier@gentoo.org>2009-12-15 00:14:53 -0500
commita8e8e491686bb34eb5aea37f58c9020f48629237 (patch)
tree2d079d743fba65f89f44181670ada148955ec867
parent761ec44add46d4dfdcb3a0607bfecb4cfc0dc0f0 (diff)
Blackfin: unify duplicated power masks
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat
-rw-r--r--arch/blackfin/include/asm/dpmc.h107
-rw-r--r--arch/blackfin/mach-bf518/include/mach/blackfin.h6
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF51x_base.h52
-rw-r--r--arch/blackfin/mach-bf527/include/mach/blackfin.h6
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF52x_base.h52
-rw-r--r--arch/blackfin/mach-bf533/include/mach/defBF532.h66
-rw-r--r--arch/blackfin/mach-bf537/include/mach/blackfin.h6
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF534.h61
-rw-r--r--arch/blackfin/mach-bf538/include/mach/blackfin.h6
-rw-r--r--arch/blackfin/mach-bf538/include/mach/defBF539.h75
-rw-r--r--arch/blackfin/mach-bf548/include/mach/blackfin.h6
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF54x_base.h66
-rw-r--r--arch/blackfin/mach-bf561/include/mach/defBF561.h54
13 files changed, 104 insertions, 459 deletions
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index 925e66cb2d49..1597ae5041ee 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver 2 * Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver
3 * 3 *
4 * Copyright (C) 2004-2008 Analog Device Inc. 4 * Copyright (C) 2004-2009 Analog Device Inc.
5 * 5 *
6 * Licensed under the GPL-2 6 * Licensed under the GPL-2
7 */ 7 */
@@ -9,7 +9,109 @@
9#ifndef _BLACKFIN_DPMC_H_ 9#ifndef _BLACKFIN_DPMC_H_
10#define _BLACKFIN_DPMC_H_ 10#define _BLACKFIN_DPMC_H_
11 11
12#ifdef __KERNEL__ 12/* PLL_CTL Masks */
13#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
14#define PLL_OFF 0x0002 /* PLL Not Powered */
15#define STOPCK 0x0008 /* Core Clock Off */
16#define PDWN 0x0020 /* Enter Deep Sleep Mode */
17#ifdef __ADSPBF539__
18# define IN_DELAY 0x0014 /* Add 200ps Delay To EBIU Input Latches */
19# define OUT_DELAY 0x00C0 /* Add 200ps Delay To EBIU Output Signals */
20#else
21# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
22# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
23#endif
24#define BYPASS 0x0100 /* Bypass the PLL */
25#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
26#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */
27#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
28
29/* PLL_DIV Masks */
30#define SSEL 0x000F /* System Select */
31#define CSEL 0x0030 /* Core Select */
32#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
33#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
34#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
35#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
36
37#define CCLK_DIV1 CSEL_DIV1
38#define CCLK_DIV2 CSEL_DIV2
39#define CCLK_DIV4 CSEL_DIV4
40#define CCLK_DIV8 CSEL_DIV8
41
42#define SET_SSEL(x) ((x) & 0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
43#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
44
45/* PLL_STAT Masks */
46#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
47#define FULL_ON 0x0002 /* Processor In Full On Mode */
48#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
49#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
50
51#define RTCWS 0x0400 /* RTC/Reset Wake-Up Status */
52#define CANWS 0x0800 /* CAN Wake-Up Status */
53#define USBWS 0x2000 /* USB Wake-Up Status */
54#define KPADWS 0x4000 /* Keypad Wake-Up Status */
55#define ROTWS 0x8000 /* Rotary Wake-Up Status */
56#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
57
58/* VR_CTL Masks */
59#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
60#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
61#define FREQ_1000 0x3000 /* Switching Frequency Is 1 MHz */
62#else
63#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
64#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
65#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
66#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
67#endif
68#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
69
70#define GAIN 0x000C /* Voltage Level Gain */
71#define GAIN_5 0x0000 /* GAIN = 5 */
72#define GAIN_10 0x0004 /* GAIN = 1 */
73#define GAIN_20 0x0008 /* GAIN = 2 */
74#define GAIN_50 0x000C /* GAIN = 5 */
75
76#define VLEV 0x00F0 /* Internal Voltage Level */
77#ifdef __ADSPBF52x__
78#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
79#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
80#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
81#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
82#define VLEV_105 0x0080 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
83#define VLEV_110 0x0090 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
84#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
85#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
86#else
87#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
88#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
89#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
90#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
91#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
92#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
93#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
94#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
95#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
96#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
97#endif
98
99#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
100#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
101#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
102#define GPWE 0x0400 /* General-Purpose Wake-Up Enable */
103#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */
104#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
105#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
106#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
107#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
108
109#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
110#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
111#else
112#define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */
113#endif
114
13#ifndef __ASSEMBLY__ 115#ifndef __ASSEMBLY__
14 116
15void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); 117void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
@@ -54,6 +156,5 @@ struct bfin_dpmc_platform_data {
54 w[P0 + (x - PLL_CTL)] = R0;\ 156 w[P0 + (x - PLL_CTL)] = R0;\
55 157
56#endif 158#endif
57#endif /* __KERNEL__ */
58 159
59#endif /*_BLACKFIN_DPMC_H_*/ 160#endif /*_BLACKFIN_DPMC_H_*/
diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h
index 6cfb246aebec..9053462be4b1 100644
--- a/arch/blackfin/mach-bf518/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf518/include/mach/blackfin.h
@@ -58,10 +58,4 @@
58#define OFFSET_SCR 0x1C /* SCR Scratch Register */ 58#define OFFSET_SCR 0x1C /* SCR Scratch Register */
59#define OFFSET_GCTL 0x24 /* Global Control Register */ 59#define OFFSET_GCTL 0x24 /* Global Control Register */
60 60
61/* PLL_DIV Masks */
62#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
63#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
64#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
65#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
66
67#endif 61#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
index 78253e838f3d..a97a2bbf9f33 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
@@ -585,58 +585,6 @@
585** modifier UNLESS the lower order bits are saved and ORed back in when 585** modifier UNLESS the lower order bits are saved and ORed back in when
586** the macro is used. 586** the macro is used.
587*************************************************************************************/ 587*************************************************************************************/
588/*
589** ********************* PLL AND RESET MASKS ****************************************/
590/* PLL_CTL Masks */
591#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
592#define PLL_OFF 0x0002 /* PLL Not Powered */
593#define STOPCK 0x0008 /* Core Clock Off */
594#define PDWN 0x0020 /* Enter Deep Sleep Mode */
595#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
596#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
597#define BYPASS 0x0100 /* Bypass the PLL */
598#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
599/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
600#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
601
602/* PLL_DIV Masks */
603#define SSEL 0x000F /* System Select */
604#define CSEL 0x0030 /* Core Select */
605#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
606#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
607#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
608#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
609/* PLL_DIV Macros */
610#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
611
612/* VR_CTL Masks */
613#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
614#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
615
616#define VLEV 0x00F0 /* Internal Voltage Level */
617#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
618#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
619#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
620#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
621#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
622#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
623#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
624#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
625#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
626#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
627
628#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
629#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
630#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
631#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
632#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
633#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
634
635/* PLL_STAT Masks */
636#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
637#define FULL_ON 0x0002 /* Processor In Full On Mode */
638#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
639#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
640 588
641/* CHIPID Masks */ 589/* CHIPID Masks */
642#define CHIPID_VERSION 0xF0000000 590#define CHIPID_VERSION 0xF0000000
diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h
index e7d6034f268f..f714c5de3073 100644
--- a/arch/blackfin/mach-bf527/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf527/include/mach/blackfin.h
@@ -46,10 +46,4 @@
46#define OFFSET_SCR 0x1C /* SCR Scratch Register */ 46#define OFFSET_SCR 0x1C /* SCR Scratch Register */
47#define OFFSET_GCTL 0x24 /* Global Control Register */ 47#define OFFSET_GCTL 0x24 /* Global Control Register */
48 48
49/* PLL_DIV Masks */
50#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
51#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
52#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
53#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
54
55#endif 49#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
index 6e6a8df02c3b..da42e9c2c69c 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -586,58 +586,6 @@
586** modifier UNLESS the lower order bits are saved and ORed back in when 586** modifier UNLESS the lower order bits are saved and ORed back in when
587** the macro is used. 587** the macro is used.
588*************************************************************************************/ 588*************************************************************************************/
589/*
590** ********************* PLL AND RESET MASKS ****************************************/
591/* PLL_CTL Masks */
592#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
593#define PLL_OFF 0x0002 /* PLL Not Powered */
594#define STOPCK 0x0008 /* Core Clock Off */
595#define PDWN 0x0020 /* Enter Deep Sleep Mode */
596#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
597#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
598#define BYPASS 0x0100 /* Bypass the PLL */
599#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
600/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
601#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
602
603/* PLL_DIV Masks */
604#define SSEL 0x000F /* System Select */
605#define CSEL 0x0030 /* Core Select */
606#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
607#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
608#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
609#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
610/* PLL_DIV Macros */
611#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
612
613/* VR_CTL Masks */
614#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
615#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
616
617#define VLEV 0x00F0 /* Internal Voltage Level */
618#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
619#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
620#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
621#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
622#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
623#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
624#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
625#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
626#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
627#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
628
629#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
630#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
631#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
632#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
633#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
634#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
635
636/* PLL_STAT Masks */
637#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
638#define FULL_ON 0x0002 /* Processor In Full On Mode */
639#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
640#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
641 589
642/* CHIPID Masks */ 590/* CHIPID Masks */
643#define CHIPID_VERSION 0xF0000000 591#define CHIPID_VERSION 0xF0000000
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h
index 02b328eb0e07..7e61fe762df2 100644
--- a/arch/blackfin/mach-bf533/include/mach/defBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h
@@ -370,72 +370,6 @@
370/* System MMR Register Bits */ 370/* System MMR Register Bits */
371/******************************************************************************* */ 371/******************************************************************************* */
372 372
373/* ********************* PLL AND RESET MASKS ************************ */
374
375/* PLL_CTL Masks */
376#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
377#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
378#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
379#define PLL_OFF 0x0002 /* Shut off PLL clocks */
380#define STOPCK_OFF 0x0008 /* Core clock off */
381#define STOPCK 0x0008 /* Core Clock Off */
382#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
383#if !defined(__ADSPBF538__)
384/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */
385# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
386# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
387#endif
388#define BYPASS 0x0100 /* Bypass the PLL */
389/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
390#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
391
392/* PLL_DIV Masks */
393#define SSEL 0x000F /* System Select */
394#define CSEL 0x0030 /* Core Select */
395
396#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
397
398#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
399#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
400#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
401#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
402/* PLL_DIV Macros */
403#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
404
405/* PLL_STAT Masks */
406#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
407#define FULL_ON 0x0002 /* Processor In Full On Mode */
408#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
409#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
410
411/* VR_CTL Masks */
412#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
413#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
414#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
415#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
416#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
417
418#define GAIN 0x000C /* Voltage Level Gain */
419#define GAIN_5 0x0000 /* GAIN = 5 */
420#define GAIN_10 0x0004 /* GAIN = 10 */
421#define GAIN_20 0x0008 /* GAIN = 20 */
422#define GAIN_50 0x000C /* GAIN = 50 */
423
424#define VLEV 0x00F0 /* Internal Voltage Level */
425#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
426#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
427#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
428#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
429#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
430#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
431#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
432#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
433#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
434#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
435
436#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
437#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
438
439/* CHIPID Masks */ 373/* CHIPID Masks */
440#define CHIPID_VERSION 0xF0000000 374#define CHIPID_VERSION 0xF0000000
441#define CHIPID_FAMILY 0x0FFFF000 375#define CHIPID_FAMILY 0x0FFFF000
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h
index eab006d260c5..a12d4b6a221d 100644
--- a/arch/blackfin/mach-bf537/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h
@@ -40,10 +40,4 @@
40#define OFFSET_SCR 0x1C /* SCR Scratch Register */ 40#define OFFSET_SCR 0x1C /* SCR Scratch Register */
41#define OFFSET_GCTL 0x24 /* Global Control Register */ 41#define OFFSET_GCTL 0x24 /* Global Control Register */
42 42
43/* PLL_DIV Masks */
44#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
45#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
46#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
47#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
48
49#endif 43#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index a6d20ca57683..868e1a139944 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -958,67 +958,6 @@
958** modifier UNLESS the lower order bits are saved and ORed back in when 958** modifier UNLESS the lower order bits are saved and ORed back in when
959** the macro is used. 959** the macro is used.
960*************************************************************************************/ 960*************************************************************************************/
961/*
962** ********************* PLL AND RESET MASKS ****************************************/
963/* PLL_CTL Masks */
964#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
965#define PLL_OFF 0x0002 /* PLL Not Powered */
966#define STOPCK 0x0008 /* Core Clock Off */
967#define PDWN 0x0020 /* Enter Deep Sleep Mode */
968#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
969#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
970#define BYPASS 0x0100 /* Bypass the PLL */
971#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
972/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
973#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
974
975/* PLL_DIV Masks */
976#define SSEL 0x000F /* System Select */
977#define CSEL 0x0030 /* Core Select */
978#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
979#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
980#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
981#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
982/* PLL_DIV Macros */
983#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
984
985/* VR_CTL Masks */
986#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
987#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
988#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
989#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
990#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
991
992#define GAIN 0x000C /* Voltage Level Gain */
993#define GAIN_5 0x0000 /* GAIN = 5 */
994#define GAIN_10 0x0004 /* GAIN = 10 */
995#define GAIN_20 0x0008 /* GAIN = 20 */
996#define GAIN_50 0x000C /* GAIN = 50 */
997
998#define VLEV 0x00F0 /* Internal Voltage Level */
999#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
1000#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
1001#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
1002#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
1003#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
1004#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
1005#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
1006#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
1007#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
1008#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
1009
1010#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
1011#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
1012#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
1013#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
1014#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
1015#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
1016
1017/* PLL_STAT Masks */
1018#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
1019#define FULL_ON 0x0002 /* Processor In Full On Mode */
1020#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
1021#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
1022 961
1023/* CHIPID Masks */ 962/* CHIPID Masks */
1024#define CHIPID_VERSION 0xF0000000 963#define CHIPID_VERSION 0xF0000000
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h
index 278e8942eef2..08b5eabb1ed5 100644
--- a/arch/blackfin/mach-bf538/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h
@@ -37,10 +37,4 @@
37#define OFFSET_SCR 0x1C /* SCR Scratch Register */ 37#define OFFSET_SCR 0x1C /* SCR Scratch Register */
38#define OFFSET_GCTL 0x24 /* Global Control Register */ 38#define OFFSET_GCTL 0x24 /* Global Control Register */
39 39
40/* PLL_DIV Masks */
41#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
42#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
43#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
44#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
45
46#endif 40#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index 312686a5194d..5375819b6147 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -1422,81 +1422,6 @@
1422/* System MMR Register Bits and Macros */ 1422/* System MMR Register Bits and Macros */
1423/******************************************************************************* */ 1423/******************************************************************************* */
1424 1424
1425/* ********************* PLL AND RESET MASKS ************************ */
1426/* PLL_CTL Masks */
1427#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
1428#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
1429#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
1430#define PLL_OFF 0x0002 /* Shut off PLL clocks */
1431
1432#define STOPCK 0x0008 /* Core Clock Off */
1433#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
1434#define IN_DELAY 0x0014 /* EBIU Input Delay Select */
1435#define OUT_DELAY 0x00C0 /* EBIU Output Delay Select */
1436#define BYPASS 0x0100 /* Bypass the PLL */
1437#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
1438
1439/* PLL_CTL Macros */
1440#ifdef _MISRA_RULES
1441#define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
1442#define SET_OUT_DELAY(x) (((x)&0x03u) << 0x6)
1443#define SET_IN_DELAY(x) ((((x)&0x02u) << 0x3) | (((x)&0x01u) << 0x2))
1444#else
1445#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
1446#define SET_OUT_DELAY(x) (((x)&0x03) << 0x6)
1447#define SET_IN_DELAY(x) ((((x)&0x02) << 0x3) | (((x)&0x01) << 0x2))
1448#endif /* _MISRA_RULES */
1449
1450/* PLL_DIV Masks */
1451#define SSEL 0x000F /* System Select */
1452#define CSEL 0x0030 /* Core Select */
1453#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
1454#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
1455#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
1456#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
1457
1458#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
1459
1460/* PLL_DIV Macros */
1461#ifdef _MISRA_RULES
1462#define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
1463#else
1464#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
1465#endif /* _MISRA_RULES */
1466
1467/* PLL_STAT Masks */
1468#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
1469#define FULL_ON 0x0002 /* Processor In Full On Mode */
1470#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
1471#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
1472
1473/* VR_CTL Masks */
1474#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
1475#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
1476#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
1477#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
1478#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
1479
1480#define GAIN 0x000C /* Voltage Level Gain */
1481#define GAIN_5 0x0000 /* GAIN = 5 */
1482#define GAIN_10 0x0004 /* GAIN = 10 */
1483#define GAIN_20 0x0008 /* GAIN = 20 */
1484#define GAIN_50 0x000C /* GAIN = 50 */
1485
1486#define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */
1487#define VLEV_100 0x0090 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
1488#define VLEV_105 0x00A0 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
1489#define VLEV_110 0x00B0 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
1490#define VLEV_115 0x00C0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
1491#define VLEV_120 0x00D0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
1492#define VLEV_125 0x00E0 /* VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */
1493#define VLEV_130 0x00F0 /* VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */
1494
1495#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
1496#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
1497#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */
1498#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
1499
1500/* SWRST Mask */ 1425/* SWRST Mask */
1501#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ 1426#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
1502#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ 1427#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h
index 13302b67857a..5684030ccc21 100644
--- a/arch/blackfin/mach-bf548/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h
@@ -64,10 +64,4 @@
64#define OFFSET_THR 0x28 /* Transmit Holding register */ 64#define OFFSET_THR 0x28 /* Transmit Holding register */
65#define OFFSET_RBR 0x2C /* Receive Buffer register */ 65#define OFFSET_RBR 0x2C /* Receive Buffer register */
66 66
67/* PLL_DIV Masks */
68#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
69#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
70#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
71#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
72
73#endif 67#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 855bc608c8e7..6d97b4e892b4 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -2075,26 +2075,6 @@
2075#define AFEXIT 0x10 /* Authentication Firmware Exit */ 2075#define AFEXIT 0x10 /* Authentication Firmware Exit */
2076#define SECSTAT 0xe0 /* Secure Status */ 2076#define SECSTAT 0xe0 /* Secure Status */
2077 2077
2078/* Bit masks for PLL_DIV */
2079
2080#define CSEL 0x30 /* Core Select */
2081#define SSEL 0xf /* System Select */
2082#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
2083#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
2084#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
2085#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
2086
2087/* Bit masks for PLL_CTL */
2088
2089#define MSEL 0x7e00 /* Multiplier Select */
2090#define BYPASS 0x100 /* PLL Bypass Enable */
2091#define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */
2092#define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */
2093#define PDWN 0x20 /* Power Down */
2094#define STOPCK 0x8 /* Stop Clock */
2095#define PLL_OFF 0x2 /* Disable PLL */
2096#define DF 0x1 /* Divide Frequency */
2097
2098/* SWRST Masks */ 2078/* SWRST Masks */
2099#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ 2079#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
2100#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ 2080#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
@@ -2102,52 +2082,6 @@
2102#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ 2082#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
2103#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ 2083#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
2104 2084
2105/* Bit masks for PLL_STAT */
2106
2107#define PLL_LOCKED 0x20 /* PLL Locked Status */
2108#define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */
2109#define FULL_ON 0x2 /* Full-On Mode */
2110#define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */
2111#define RTCWS 0x400 /* RTC/Reset Wake-Up Status */
2112#define CANWS 0x800 /* CAN Wake-Up Status */
2113#define USBWS 0x2000 /* USB Wake-Up Status */
2114#define KPADWS 0x4000 /* Keypad Wake-Up Status */
2115#define ROTWS 0x8000 /* Rotary Wake-Up Status */
2116#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
2117
2118/* Bit masks for VR_CTL */
2119
2120#define FREQ 0x3 /* Regulator Switching Frequency */
2121#define GAIN 0xc /* Voltage Output Level Gain */
2122#define VLEV 0xf0 /* Internal Voltage Level */
2123#define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */
2124#define WAKE 0x100 /* RTC/Reset Wake-Up Enable */
2125#define CANWE 0x200 /* CAN0/1 Wake-Up Enable */
2126#define GPWE 0x400 /* General-Purpose Wake-Up Enable */
2127#define USBWE 0x800 /* USB Wake-Up Enable */
2128#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
2129#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
2130
2131#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
2132#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
2133#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
2134
2135#define GAIN_5 0x0000 /* GAIN = 5*/
2136#define GAIN_10 0x0004 /* GAIN = 1*/
2137#define GAIN_20 0x0008 /* GAIN = 2*/
2138#define GAIN_50 0x000C /* GAIN = 5*/
2139
2140#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
2141#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
2142#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
2143#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
2144#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
2145#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
2146#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
2147#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
2148#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
2149#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
2150
2151/* Bit masks for NFC_CTL */ 2085/* Bit masks for NFC_CTL */
2152 2086
2153#define WR_DLY 0xf /* Write Strobe Delay */ 2087#define WR_DLY 0xf /* Write Strobe Delay */
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index a31e509553fb..c2f9c8f54eab 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -884,65 +884,11 @@
884/* System MMR Register Bits */ 884/* System MMR Register Bits */
885/******************************************************************************* */ 885/******************************************************************************* */
886 886
887/* ********************* PLL AND RESET MASKS ************************ */
888
889/* PLL_CTL Masks */
890#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */
891#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */
892#define PLL_OFF 0x00000002 /* Shut off PLL clocks */
893#define STOPCK_OFF 0x00000008 /* Core clock off */
894#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */
895#define BYPASS 0x00000100 /* Bypass the PLL */
896
897/* CHIPID Masks */ 887/* CHIPID Masks */
898#define CHIPID_VERSION 0xF0000000 888#define CHIPID_VERSION 0xF0000000
899#define CHIPID_FAMILY 0x0FFFF000 889#define CHIPID_FAMILY 0x0FFFF000
900#define CHIPID_MANUFACTURE 0x00000FFE 890#define CHIPID_MANUFACTURE 0x00000FFE
901 891
902/* VR_CTL Masks */
903#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
904#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
905#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
906#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
907#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
908
909#define GAIN 0x000C /* Voltage Level Gain */
910#define GAIN_5 0x0000 /* GAIN = 5*/
911#define GAIN_10 0x0004 /* GAIN = 1*/
912#define GAIN_20 0x0008 /* GAIN = 2*/
913#define GAIN_50 0x000C /* GAIN = 5*/
914
915#define VLEV 0x00F0 /* Internal Voltage Level */
916#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
917#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
918#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
919#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
920#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
921#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
922#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
923#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
924#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
925#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
926
927#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
928#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
929
930/* PLL_DIV Masks */
931#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
932
933#define CSEL 0x30 /* Core Select */
934#define SSEL 0xf /* System Select */
935#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
936#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
937#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
938#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
939
940/* PLL_STAT Masks */
941#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
942#define FULL_ON 0x0002 /* Processor In Full On Mode */
943#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
944#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
945
946/* SICA_SYSCR Masks */ 892/* SICA_SYSCR Masks */
947#define COREB_SRAM_INIT 0x0020 893#define COREB_SRAM_INIT 0x0020
948 894
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 08:18:30 -0500