diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-09-15 12:23:10 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-10-01 11:41:01 -0400 |
commit | 3f69c0c1af288d6b124d0a928a33b51061ebf850 (patch) | |
tree | fb6b4b13c2423e98089489056d5a35cd7b0a0400 | |
parent | 639b0ae7f5bcd645862a9c3ea2d4321475c71d7a (diff) |
[ARM] Convert ARMv7 to use TEX remapping
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r-- | arch/arm/mm/proc-v7.S | 37 |
1 files changed, 33 insertions, 4 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 7c34c892b82b..18897fbbe8bf 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
@@ -100,11 +100,36 @@ ENTRY(cpu_v7_switch_mm) | |||
100 | * - pte - PTE value to store | 100 | * - pte - PTE value to store |
101 | * - ext - value for extended PTE bits | 101 | * - ext - value for extended PTE bits |
102 | */ | 102 | */ |
103 | armv6_mt_table cpu_v7 | ||
104 | |||
105 | ENTRY(cpu_v7_set_pte_ext) | 103 | ENTRY(cpu_v7_set_pte_ext) |
106 | #ifdef CONFIG_MMU | 104 | #ifdef CONFIG_MMU |
107 | armv6_set_pte_ext cpu_v7 | 105 | str r1, [r0], #-2048 @ linux version |
106 | |||
107 | bic r3, r1, #0x000003f0 | ||
108 | bic r3, r3, #PTE_TYPE_MASK | ||
109 | orr r3, r3, r2 | ||
110 | orr r3, r3, #PTE_EXT_AP0 | 2 | ||
111 | |||
112 | tst r2, #1 << 4 | ||
113 | orrne r3, r3, #PTE_EXT_TEX(1) | ||
114 | |||
115 | tst r1, #L_PTE_WRITE | ||
116 | tstne r1, #L_PTE_DIRTY | ||
117 | orreq r3, r3, #PTE_EXT_APX | ||
118 | |||
119 | tst r1, #L_PTE_USER | ||
120 | orrne r3, r3, #PTE_EXT_AP1 | ||
121 | tstne r3, #PTE_EXT_APX | ||
122 | bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 | ||
123 | |||
124 | tst r1, #L_PTE_EXEC | ||
125 | orreq r3, r3, #PTE_EXT_XN | ||
126 | |||
127 | tst r1, #L_PTE_YOUNG | ||
128 | tstne r1, #L_PTE_PRESENT | ||
129 | moveq r3, #0 | ||
130 | |||
131 | str r3, [r0] | ||
132 | mcr p15, 0, r0, c7, c10, 1 @ flush_pte | ||
108 | #endif | 133 | #endif |
109 | mov pc, lr | 134 | mov pc, lr |
110 | 135 | ||
@@ -148,6 +173,10 @@ __v7_setup: | |||
148 | mov r10, #0x1f @ domains 0, 1 = manager | 173 | mov r10, #0x1f @ domains 0, 1 = manager |
149 | mcr p15, 0, r10, c3, c0, 0 @ load domain access register | 174 | mcr p15, 0, r10, c3, c0, 0 @ load domain access register |
150 | #endif | 175 | #endif |
176 | ldr r5, =0x40e040e0 | ||
177 | ldr r6, =0xff0aa1a8 | ||
178 | mcr p15, 0, r5, c10, c2, 0 @ write PRRR | ||
179 | mcr p15, 0, r6, c10, c2, 1 @ write NMRR | ||
151 | adr r5, v7_crval | 180 | adr r5, v7_crval |
152 | ldmia r5, {r5, r6} | 181 | ldmia r5, {r5, r6} |
153 | mrc p15, 0, r0, c1, c0, 0 @ read control register | 182 | mrc p15, 0, r0, c1, c0, 0 @ read control register |
@@ -163,7 +192,7 @@ __v7_setup: | |||
163 | */ | 192 | */ |
164 | .type v7_crval, #object | 193 | .type v7_crval, #object |
165 | v7_crval: | 194 | v7_crval: |
166 | crval clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c | 195 | crval clear=0x0120c302, mmuset=0x10c0387d, ucset=0x00c0187c |
167 | 196 | ||
168 | __v7_setup_stack: | 197 | __v7_setup_stack: |
169 | .space 4 * 11 @ 11 registers | 198 | .space 4 * 11 @ 11 registers |