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authorMauro Carvalho Chehab <mchehab@redhat.com>2009-07-15 18:53:24 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2010-05-10 10:44:52 -0400
commitf237fcf2b7560be33386255042dc11167ca486d5 (patch)
tree90e650492b312c9b8dc0ab958eb588fb814ac8cb
parent8a2f118e3a023a4e8cbe56a6e51f7b78fa8c76a0 (diff)
i7core_edac: some fixes at memory error parser
m->bank is not related to the memory bank but, instead, to the MCA Error register bank. Fix it accordingly. While here, improves the comments for Nehalem bank. A later fix is needed, in order to get bank/rank information from MCA error log. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
-rw-r--r--drivers/edac/i7core_edac.c22
1 files changed, 14 insertions, 8 deletions
diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c
index 4397a3171c62..67822976992e 100644
--- a/drivers/edac/i7core_edac.c
+++ b/drivers/edac/i7core_edac.c
@@ -1322,12 +1322,13 @@ static void check_mc_test_err(struct mem_ctl_info *mci, u8 socket)
1322/* 1322/*
1323 * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32 1323 * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
1324 * Architectures Software Developer’s Manual Volume 3B. 1324 * Architectures Software Developer’s Manual Volume 3B.
1325 * The MCA registers are the following ones: 1325 * Nehalem are defined as family 0x06, model 0x1a
1326 *
1327 * The MCA registers used here are the following ones:
1326 * struct mce field MCA Register 1328 * struct mce field MCA Register
1327 * m->status MSR_IA32_MC0_STATUS 1329 * m->status MSR_IA32_MC8_STATUS
1328 * m->addr MSR_IA32_MC0_ADDR 1330 * m->addr MSR_IA32_MC8_ADDR
1329 * m->misc MSR_IA32_MC0_MISC 1331 * m->misc MSR_IA32_MC8_MISC
1330 * m->mcgstatus MSR_IA32_MCG_STATUS
1331 * In the case of Nehalem, the error information is masked at .status and .misc 1332 * In the case of Nehalem, the error information is masked at .status and .misc
1332 * fields 1333 * fields
1333 */ 1334 */
@@ -1375,10 +1376,11 @@ static void i7core_mce_output_error(struct mem_ctl_info *mci,
1375 err = "unknown"; 1376 err = "unknown";
1376 } 1377 }
1377 1378
1379 /* FIXME: should convert addr into bank and rank information */
1378 msg = kasprintf(GFP_ATOMIC, 1380 msg = kasprintf(GFP_ATOMIC,
1379 "%s (addr = 0x%08llx Bank=0x%08x, Dimm=%d, Channel=%d, " 1381 "%s (addr = 0x%08llx Dimm=%d, Channel=%d, "
1380 "syndrome=0x%08x total error count=%d Err=%d (%s))\n", 1382 "syndrome=0x%08x, count=%d Err=%d (%s))\n",
1381 type, (long long) m->addr, m->bank, dimm, channel, 1383 type, (long long) m->addr, dimm, channel,
1382 syndrome, core_err_cnt,errnum, err); 1384 syndrome, core_err_cnt,errnum, err);
1383 1385
1384 debugf0("%s", msg); 1386 debugf0("%s", msg);
@@ -1447,6 +1449,10 @@ static int i7core_mce_check_error(void *priv, struct mce *mce)
1447 if (((mce->status & 0xffff) >> 7) != 1) 1449 if (((mce->status & 0xffff) >> 7) != 1)
1448 return 0; 1450 return 0;
1449 1451
1452 /* Bank 8 registers are the only ones that we know how to handle */
1453 if (mce->bank != 8)
1454 return 0;
1455
1450 spin_lock_irqsave(&pvt->mce_lock, flags); 1456 spin_lock_irqsave(&pvt->mce_lock, flags);
1451 if (pvt->mce_count < MCE_LOG_LEN) { 1457 if (pvt->mce_count < MCE_LOG_LEN) {
1452 memcpy(&pvt->mce_entry[pvt->mce_count], mce, sizeof(*mce)); 1458 memcpy(&pvt->mce_entry[pvt->mce_count], mce, sizeof(*mce));