diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2006-04-05 19:44:25 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-04-18 22:14:29 -0400 |
| commit | 9200c0b2a07c430bd98c546fc44b94f50e67ac62 (patch) | |
| tree | 4570878f9e1e48c17e4e93beeefcbce653c3ae8a | |
| parent | 7e3bfc7cfc402458b0386086ab650ce811720927 (diff) | |
[MIPS] Fix Makefile bugs for MIPS32/MIPS64 R1 and R2.
This fixes kernel builds with gcc 3.2 (not 64-bit, that is looking like
it is beyond recovery) and 3.3. With these bugs fixed we now also can
get undo 3b4c4996a0c24da9e6f8be764e3950b756b18cc0 and similar bits for
SMTC that were added in 79cc8007b93838a670b164b8a55ab3e735a12a8b.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/Makefile | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 5d10758356a6..69b9c1b8fafc 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile | |||
| @@ -105,13 +105,13 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap | |||
| 105 | cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap | 105 | cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap |
| 106 | cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap | 106 | cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap |
| 107 | cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap | 107 | cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap |
| 108 | cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips2 -mtune=r4600) \ | 108 | cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ |
| 109 | -Wa,-mips32 -Wa,--trap | 109 | -Wa,-mips32 -Wa,--trap |
| 110 | cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips2 -mtune=r4600) \ | 110 | cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ |
| 111 | -Wa,-mips32r2 -Wa,--trap | 111 | -Wa,-mips32r2 -Wa,--trap |
| 112 | cflags-$(CONFIG_CPU_MIPS64_R1) += $(call cc-option,-march=mips64,-mips2 -mtune=r4600) \ | 112 | cflags-$(CONFIG_CPU_MIPS64_R1) += $(call cc-option,-march=mips64,-mips64 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \ |
| 113 | -Wa,-mips64 -Wa,--trap | 113 | -Wa,-mips64 -Wa,--trap |
| 114 | cflags-$(CONFIG_CPU_MIPS64_R2) += $(call cc-option,-march=mips64r2,-mips2 -mtune=r4600 ) \ | 114 | cflags-$(CONFIG_CPU_MIPS64_R2) += $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \ |
| 115 | -Wa,-mips64r2 -Wa,--trap | 115 | -Wa,-mips64r2 -Wa,--trap |
| 116 | cflags-$(CONFIG_CPU_R5000) += -march=r5000 -Wa,--trap | 116 | cflags-$(CONFIG_CPU_R5000) += -march=r5000 -Wa,--trap |
| 117 | cflags-$(CONFIG_CPU_R5432) += $(call cc-option,-march=r5400,-march=r5000) \ | 117 | cflags-$(CONFIG_CPU_R5432) += $(call cc-option,-march=r5400,-march=r5000) \ |