tg3: Use constant 500KHz MI clock on adapters with a CPMU

The MI clock is not configured correctly on adapters with the CPMU
present.  The tg3 driver has code which statically sets the MI clock to
be a fraction of the speed at which the core clock is running.
However, the CPMU can change the adapter's core clock frequency based
on operating conditions.  Consequently, the MI will run slow when the
core's clock has been slowed down.

There is a new 500KHz constant frequency clock available on adapters
with a CPMU.  This patch removes the static core clock scaling and
configures the MI clock to use this new 500KHz clock instead.

Running the MI clock at slower speeds will not directly result in data
corruption, but it does challenge the PHY read and write routine timeouts.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

2 files changed, 14 insertions, 6 deletions

diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index b66c75e3b8a1..e0dc31fdf844 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -2097,9 +2097,11 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
               MAC_STATUS_LNKSTATE_CHANGED));
         udelay(40);
 
-        tp->mi_mode = MAC_MI_MODE_BASE;
-        tw32_f(MAC_MI_MODE, tp->mi_mode);
-        udelay(80);
+        if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
+                tw32_f(MAC_MI_MODE,
+                     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
+                udelay(80);
+        }
 
         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
 
@@ -7102,7 +7104,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
         }
 
-        tp->mi_mode = MAC_MI_MODE_BASE;
+        tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
         tw32_f(MAC_MI_MODE, tp->mi_mode);
         udelay(80);
 
@@ -11764,6 +11766,12 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                         tp->phy_otp = TG3_OTP_DEFAULT;
         }
 
+        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
+            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
+                tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
+        else
+                tp->mi_mode = MAC_MI_MODE_BASE;
+
         tp->coalesce_mode = 0;
         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
@@ -12692,7 +12700,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
         tp->mac_mode = TG3_DEF_MAC_MODE;
         tp->rx_mode = TG3_DEF_RX_MODE;
         tp->tx_mode = TG3_DEF_TX_MODE;
-        tp->mi_mode = MAC_MI_MODE_BASE;
+
         if (tg3_debug > 0)
                 tp->msg_enable = tg3_debug;
         else
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index c688c3ac5035..ce2be3a96175 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -415,7 +415,7 @@
 #define  MAC_MI_MODE_CLK_10MHZ           0x00000001
 #define  MAC_MI_MODE_SHORT_PREAMBLE      0x00000002
 #define  MAC_MI_MODE_AUTO_POLL           0x00000010
-#define  MAC_MI_MODE_CORE_CLK_62MHZ      0x00008000
+#define  MAC_MI_MODE_500KHZ_CONST        0x00008000
 #define  MAC_MI_MODE_BASE                0x000c0000 /* XXX magic values XXX */
 #define MAC_AUTO_POLL_STATUS            0x00000458
 #define  MAC_AUTO_POLL_ERROR             0x00000001