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authorPaul Mundt <lethal@linux-sh.org>2010-01-13 05:11:14 -0500
committerPaul Mundt <lethal@linux-sh.org>2010-01-13 05:11:14 -0500
commit782bb5a532f883540bf403afb19f735a4eefd95b (patch)
treec2eec8aff6797fda269d4f1c3d4ed19ff1d584d7
parent206582c3161f165f5bf49ececa962c5f95fdf0a3 (diff)
sh: default to extended TLB support.
All SH-X2 and SH-X3 parts support an extended TLB mode, which has been left as experimental since support was originally merged. Now that it's had some time to stabilize and get some exposure to various platforms, we can drop it as an option and default enable it across the board. This is also good future proofing for newer parts that will drop support for the legacy TLB mode completely. This will also force 3-level page tables for all newer parts, which is necessary both for the varying page sizes and larger memories. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--arch/sh/include/asm/pgalloc.h2
-rw-r--r--arch/sh/include/asm/pgtable.h2
-rw-r--r--arch/sh/include/asm/pgtable_nopmd.h11
-rw-r--r--arch/sh/include/asm/pgtable_pmd.h5
-rw-r--r--arch/sh/mm/Kconfig29
-rw-r--r--arch/sh/mm/pgtable.c9
6 files changed, 17 insertions, 41 deletions
diff --git a/arch/sh/include/asm/pgalloc.h b/arch/sh/include/asm/pgalloc.h
index f8982f4e0405..8c00785c60d5 100644
--- a/arch/sh/include/asm/pgalloc.h
+++ b/arch/sh/include/asm/pgalloc.h
@@ -9,7 +9,7 @@
9extern pgd_t *pgd_alloc(struct mm_struct *); 9extern pgd_t *pgd_alloc(struct mm_struct *);
10extern void pgd_free(struct mm_struct *mm, pgd_t *pgd); 10extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
11 11
12#ifdef CONFIG_PGTABLE_LEVELS_3 12#if PAGETABLE_LEVELS > 2
13extern void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd); 13extern void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd);
14extern pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address); 14extern pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address);
15extern void pmd_free(struct mm_struct *mm, pmd_t *pmd); 15extern void pmd_free(struct mm_struct *mm, pmd_t *pmd);
diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h
index 78598ec33d0a..856ece07d31b 100644
--- a/arch/sh/include/asm/pgtable.h
+++ b/arch/sh/include/asm/pgtable.h
@@ -12,7 +12,7 @@
12#ifndef __ASM_SH_PGTABLE_H 12#ifndef __ASM_SH_PGTABLE_H
13#define __ASM_SH_PGTABLE_H 13#define __ASM_SH_PGTABLE_H
14 14
15#ifdef CONFIG_PGTABLE_LEVELS_3 15#ifdef CONFIG_X2TLB
16#include <asm/pgtable_pmd.h> 16#include <asm/pgtable_pmd.h>
17#else 17#else
18#include <asm/pgtable_nopmd.h> 18#include <asm/pgtable_nopmd.h>
diff --git a/arch/sh/include/asm/pgtable_nopmd.h b/arch/sh/include/asm/pgtable_nopmd.h
index f0b525b3cb4a..b8355e4057cf 100644
--- a/arch/sh/include/asm/pgtable_nopmd.h
+++ b/arch/sh/include/asm/pgtable_nopmd.h
@@ -6,17 +6,18 @@
6/* 6/*
7 * traditional two-level paging structure 7 * traditional two-level paging structure
8 */ 8 */
9#define PAGETABLE_LEVELS 2
9 10
10/* PTE bits */ 11/* PTE bits */
11#define PTE_MAGNITUDE 2 /* 32-bit PTEs */ 12#define PTE_MAGNITUDE 2 /* 32-bit PTEs */
12 13
13#define PTE_SHIFT PAGE_SHIFT 14#define PTE_SHIFT PAGE_SHIFT
14#define PTE_BITS (PTE_SHIFT - PTE_MAGNITUDE) 15#define PTE_BITS (PTE_SHIFT - PTE_MAGNITUDE)
15 16
16/* PGD bits */ 17/* PGD bits */
17#define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS) 18#define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS)
18 19
19#define PTRS_PER_PGD (PAGE_SIZE / (1 << PTE_MAGNITUDE)) 20#define PTRS_PER_PGD (PAGE_SIZE / (1 << PTE_MAGNITUDE))
20#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) 21#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
21 22
22#endif /* __ASM_SH_PGTABLE_NOPMD_H */ 23#endif /* __ASM_SH_PGTABLE_NOPMD_H */
diff --git a/arch/sh/include/asm/pgtable_pmd.h b/arch/sh/include/asm/pgtable_pmd.h
index 42a180e534a8..587b05e1d04f 100644
--- a/arch/sh/include/asm/pgtable_pmd.h
+++ b/arch/sh/include/asm/pgtable_pmd.h
@@ -7,11 +7,12 @@
7 * Some cores need a 3-level page table layout, for example when using 7 * Some cores need a 3-level page table layout, for example when using
8 * 64-bit PTEs and 4K pages. 8 * 64-bit PTEs and 4K pages.
9 */ 9 */
10#define PAGETABLE_LEVELS 3
10 11
11#define PTE_MAGNITUDE 3 /* 64-bit PTEs on extended mode SH-X2 TLB */ 12#define PTE_MAGNITUDE 3 /* 64-bit PTEs on SH-X2 TLB */
12 13
13/* PGD bits */ 14/* PGD bits */
14#define PGDIR_SHIFT 30 15#define PGDIR_SHIFT 30
15 16
16#define PTRS_PER_PGD 4 17#define PTRS_PER_PGD 4
17#define USER_PTRS_PER_PGD 2 18#define USER_PTRS_PER_PGD 2
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 860cd24b4205..7a4ebc8cbadd 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -100,13 +100,8 @@ config PMB_LEGACY
100 and allows systems to support up to 512MiB of system memory. 100 and allows systems to support up to 512MiB of system memory.
101 101
102config X2TLB 102config X2TLB
103 bool "Enable extended TLB mode" 103 def_bool y
104 depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL 104 depends on (CPU_SHX2 || CPU_SHX3) && MMU
105 help
106 Selecting this option will enable the extended mode of the SH-X2
107 TLB. For legacy SH-X behaviour and interoperability, say N. For
108 all of the fun new features and a willingless to submit bug reports,
109 say Y.
110 105
111config VSYSCALL 106config VSYSCALL
112 bool "Support vsyscall page" 107 bool "Support vsyscall page"
@@ -175,31 +170,11 @@ config ARCH_MEMORY_PROBE
175 depends on MEMORY_HOTPLUG 170 depends on MEMORY_HOTPLUG
176 171
177choice 172choice
178 prompt "Page table layout"
179 default PGTABLE_LEVELS_3 if X2TLB
180 default PGTABLE_LEVELS_2
181
182config PGTABLE_LEVELS_2
183 bool "2 Levels"
184 help
185 This is the default page table layout for all SuperH CPUs.
186
187config PGTABLE_LEVELS_3
188 bool "3 Levels"
189 depends on X2TLB
190 help
191 This enables a 3 level page table structure.
192
193endchoice
194
195choice
196 prompt "Kernel page size" 173 prompt "Kernel page size"
197 default PAGE_SIZE_8KB if X2TLB
198 default PAGE_SIZE_4KB 174 default PAGE_SIZE_4KB
199 175
200config PAGE_SIZE_4KB 176config PAGE_SIZE_4KB
201 bool "4kB" 177 bool "4kB"
202 depends on !MMU || !X2TLB || PGTABLE_LEVELS_3
203 help 178 help
204 This is the default page size used by all SuperH CPUs. 179 This is the default page size used by all SuperH CPUs.
205 180
diff --git a/arch/sh/mm/pgtable.c b/arch/sh/mm/pgtable.c
index e1bc5483cc07..6f21fb1d8726 100644
--- a/arch/sh/mm/pgtable.c
+++ b/arch/sh/mm/pgtable.c
@@ -3,8 +3,7 @@
3#define PGALLOC_GFP GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO 3#define PGALLOC_GFP GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO
4 4
5static struct kmem_cache *pgd_cachep; 5static struct kmem_cache *pgd_cachep;
6 6#if PAGETABLE_LEVELS > 2
7#ifdef CONFIG_PGTABLE_LEVELS_3
8static struct kmem_cache *pmd_cachep; 7static struct kmem_cache *pmd_cachep;
9#endif 8#endif
10 9
@@ -22,7 +21,7 @@ void pgtable_cache_init(void)
22 pgd_cachep = kmem_cache_create("pgd_cache", 21 pgd_cachep = kmem_cache_create("pgd_cache",
23 PTRS_PER_PGD * (1<<PTE_MAGNITUDE), 22 PTRS_PER_PGD * (1<<PTE_MAGNITUDE),
24 PAGE_SIZE, SLAB_PANIC, pgd_ctor); 23 PAGE_SIZE, SLAB_PANIC, pgd_ctor);
25#ifdef CONFIG_PGTABLE_LEVELS_3 24#if PAGETABLE_LEVELS > 2
26 pmd_cachep = kmem_cache_create("pmd_cache", 25 pmd_cachep = kmem_cache_create("pmd_cache",
27 PTRS_PER_PMD * (1<<PTE_MAGNITUDE), 26 PTRS_PER_PMD * (1<<PTE_MAGNITUDE),
28 PAGE_SIZE, SLAB_PANIC, NULL); 27 PAGE_SIZE, SLAB_PANIC, NULL);
@@ -39,7 +38,7 @@ void pgd_free(struct mm_struct *mm, pgd_t *pgd)
39 kmem_cache_free(pgd_cachep, pgd); 38 kmem_cache_free(pgd_cachep, pgd);
40} 39}
41 40
42#ifdef CONFIG_PGTABLE_LEVELS_3 41#if PAGETABLE_LEVELS > 2
43void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) 42void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
44{ 43{
45 set_pud(pud, __pud((unsigned long)pmd)); 44 set_pud(pud, __pud((unsigned long)pmd));
@@ -54,4 +53,4 @@ void pmd_free(struct mm_struct *mm, pmd_t *pmd)
54{ 53{
55 kmem_cache_free(pmd_cachep, pmd); 54 kmem_cache_free(pmd_cachep, pmd);
56} 55}
57#endif /* CONFIG_PGTABLE_LEVELS_3 */ 56#endif /* PAGETABLE_LEVELS > 2 */