diff options
| author | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2007-07-05 21:26:03 -0400 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2007-07-05 21:26:03 -0400 |
| commit | 75f016a7ce75220d898608791870ab7da549a430 (patch) | |
| tree | 134b9ab8e730c103e8e2280e712bb20a53c8990d | |
| parent | 880dec100761f4fbc5fa5d22e658a8718828f04e (diff) | |
sh: Fix timer-tmu build for SH-3.
With the TMU register definitions being renamed on SH-4, SH-3 ended up
breaking. Update the TSTR define to match the SH-4 convention.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| -rw-r--r-- | include/asm-sh/cpu-sh3/timer.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h index b2394cf76f49..4928b08f9d19 100644 --- a/include/asm-sh/cpu-sh3/timer.h +++ b/include/asm-sh/cpu-sh3/timer.h | |||
| @@ -29,7 +29,7 @@ | |||
| 29 | #endif | 29 | #endif |
| 30 | 30 | ||
| 31 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710) | 31 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710) |
| 32 | #define TMU_TSTR 0xa412fe92 /* Byte access */ | 32 | #define TMU_012_TSTR 0xa412fe92 /* Byte access */ |
| 33 | 33 | ||
| 34 | #define TMU0_TCOR 0xa412fe94 /* Long access */ | 34 | #define TMU0_TCOR 0xa412fe94 /* Long access */ |
| 35 | #define TMU0_TCNT 0xa412fe98 /* Long access */ | 35 | #define TMU0_TCNT 0xa412fe98 /* Long access */ |
| @@ -44,7 +44,7 @@ | |||
| 44 | #define TMU2_TCR 0xa412feb4 /* Word access */ | 44 | #define TMU2_TCR 0xa412feb4 /* Word access */ |
| 45 | 45 | ||
| 46 | #else | 46 | #else |
| 47 | #define TMU_TSTR 0xfffffe92 /* Byte access */ | 47 | #define TMU_012_TSTR 0xfffffe92 /* Byte access */ |
| 48 | 48 | ||
| 49 | #define TMU0_TCOR 0xfffffe94 /* Long access */ | 49 | #define TMU0_TCOR 0xfffffe94 /* Long access */ |
| 50 | #define TMU0_TCNT 0xfffffe98 /* Long access */ | 50 | #define TMU0_TCNT 0xfffffe98 /* Long access */ |