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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-02-07 22:32:36 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-02-07 22:32:36 -0500
commit905adce4094d64a6691df994e424fbf486301adc (patch)
treec4e3a2fb1465eeb713b3bec5ef4634c28179a14b
parent78149df6d565c36675463352d0bfe0000b02b7a7 (diff)
parent1e8f34f7d88c969a06229a786241839d49dd63e3 (diff)
Merge master.kernel.org:/pub/scm/linux/kernel/git/bart/ide-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/bart/ide-2.6: (23 commits) ide-acpi support warning fix ACPI support for IDE devices IDE Driver for Delkin/Lexar/etc.. cardbus CF adapter ide: it8213 IDE driver update (version 2) ide: add it8213 IDE driver tc86c001: add missing __init tag for tc86c001_ide_init() tc86c001: mark init_chipset_tc86c001() with __devinit tag tc86c001: init_hwif_tc86c001() can be static ide: add Toshiba TC86C001 IDE driver (take 2) pdc202xx_new: remove check_in_drive_lists abomination pdc202xx_new: remove useless code slc90e66: carry over fixes from piix driver piix: tuneproc() fixes/cleanups piix: fix 82371MX enablebits hpt366: HPT36x PCI clock detection fix hpt366: init code rewrite hpt366: clean up DMA timeout handling for HPT370 hpt366: merge HPT37x speedproc handlers hpt366: cache channel's MCR address hpt366: switch to using pci_get_slot ...
Diffstat
-rw-r--r--drivers/ide/Kconfig24
-rw-r--r--drivers/ide/Makefile1
-rw-r--r--drivers/ide/ide-acpi.c697
-rw-r--r--drivers/ide/ide-probe.c3
-rw-r--r--drivers/ide/ide.c36
-rw-r--r--drivers/ide/pci/Makefile4
-rw-r--r--drivers/ide/pci/delkin_cb.c140
-rw-r--r--drivers/ide/pci/hpt366.c1583
-rw-r--r--drivers/ide/pci/it8213.c362
-rw-r--r--drivers/ide/pci/pdc202xx_new.c56
-rw-r--r--drivers/ide/pci/pdc202xx_old.c27
-rw-r--r--drivers/ide/pci/piix.c31
-rw-r--r--drivers/ide/pci/slc90e66.c55
-rw-r--r--drivers/ide/pci/tc86c001.c309
-rw-r--r--drivers/pci/quirks.c18
-rw-r--r--include/linux/ide.h27
-rw-r--r--include/linux/pci_ids.h1
17 files changed, 2506 insertions, 868 deletions
diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig
index 3f828052f8d2..ec03341d2bd8 100644
--- a/drivers/ide/Kconfig
+++ b/drivers/ide/Kconfig
@@ -167,6 +167,13 @@ config BLK_DEV_IDECS
167 Support for Compact Flash cards, outboard IDE disks, tape drives, 167 Support for Compact Flash cards, outboard IDE disks, tape drives,
168 and CD-ROM drives connected through a PCMCIA card. 168 and CD-ROM drives connected through a PCMCIA card.
169 169
170config BLK_DEV_DELKIN
171 tristate "Cardbus IDE support (Delkin/ASKA/Workbit)"
172 depends on CARDBUS && PCI
173 help
174 Support for Delkin, ASKA, and Workbit Cardbus CompactFlash
175 Adapters. This may also work for similar SD and XD adapters.
176
170config BLK_DEV_IDECD 177config BLK_DEV_IDECD
171 tristate "Include IDE/ATAPI CDROM support" 178 tristate "Include IDE/ATAPI CDROM support"
172 ---help--- 179 ---help---
@@ -264,6 +271,13 @@ config BLK_DEV_IDESCSI
264 If both this SCSI emulation and native ATAPI support are compiled 271 If both this SCSI emulation and native ATAPI support are compiled
265 into the kernel, the native support will be used. 272 into the kernel, the native support will be used.
266 273
274config BLK_DEV_IDEACPI
275 bool "IDE ACPI support"
276 depends on ACPI
277 ---help---
278 Implement ACPI support for generic IDE devices. On modern
279 machines ACPI support is required to properly handle ACPI S3 states.
280
267config IDE_TASK_IOCTL 281config IDE_TASK_IOCTL
268 bool "IDE Taskfile Access" 282 bool "IDE Taskfile Access"
269 help 283 help
@@ -606,6 +620,11 @@ config BLK_DEV_PIIX
606 the kernel to change PIO, DMA and UDMA speeds and to configure 620 the kernel to change PIO, DMA and UDMA speeds and to configure
607 the chip to optimum performance. 621 the chip to optimum performance.
608 622
623config BLK_DEV_IT8213
624 tristate "IT8213 IDE support"
625 help
626 This driver adds support for the ITE 8213 IDE controller.
627
609config BLK_DEV_IT821X 628config BLK_DEV_IT821X
610 tristate "IT821X IDE support" 629 tristate "IT821X IDE support"
611 help 630 help
@@ -742,6 +761,11 @@ config BLK_DEV_VIA82CXXX
742 This allows the kernel to change PIO, DMA and UDMA speeds and to 761 This allows the kernel to change PIO, DMA and UDMA speeds and to
743 configure the chip to optimum performance. 762 configure the chip to optimum performance.
744 763
764config BLK_DEV_TC86C001
765 tristate "Toshiba TC86C001 support"
766 help
767 This driver adds support for Toshiba TC86C001 GOKU-S chip.
768
745endif 769endif
746 770
747config BLK_DEV_IDE_PMAC 771config BLK_DEV_IDE_PMAC
diff --git a/drivers/ide/Makefile b/drivers/ide/Makefile
index 569fae717503..d9f029e8ff74 100644
--- a/drivers/ide/Makefile
+++ b/drivers/ide/Makefile
@@ -22,6 +22,7 @@ ide-core-$(CONFIG_BLK_DEV_IDEPCI) += setup-pci.o
22ide-core-$(CONFIG_BLK_DEV_IDEDMA) += ide-dma.o 22ide-core-$(CONFIG_BLK_DEV_IDEDMA) += ide-dma.o
23ide-core-$(CONFIG_PROC_FS) += ide-proc.o 23ide-core-$(CONFIG_PROC_FS) += ide-proc.o
24ide-core-$(CONFIG_BLK_DEV_IDEPNP) += ide-pnp.o 24ide-core-$(CONFIG_BLK_DEV_IDEPNP) += ide-pnp.o
25ide-core-$(CONFIG_BLK_DEV_IDEACPI) += ide-acpi.o
25 26
26# built-in only drivers from arm/ 27# built-in only drivers from arm/
27ide-core-$(CONFIG_IDE_ARM) += arm/ide_arm.o 28ide-core-$(CONFIG_IDE_ARM) += arm/ide_arm.o
diff --git a/drivers/ide/ide-acpi.c b/drivers/ide/ide-acpi.c
new file mode 100644
index 000000000000..17aea65d7dd2
--- /dev/null
+++ b/drivers/ide/ide-acpi.c
@@ -0,0 +1,697 @@
1/*
2 * ide-acpi.c
3 * Provides ACPI support for IDE drives.
4 *
5 * Copyright (C) 2005 Intel Corp.
6 * Copyright (C) 2005 Randy Dunlap
7 * Copyright (C) 2006 SUSE Linux Products GmbH
8 * Copyright (C) 2006 Hannes Reinecke
9 */
10
11#include <linux/ata.h>
12#include <linux/delay.h>
13#include <linux/device.h>
14#include <linux/errno.h>
15#include <linux/kernel.h>
16#include <acpi/acpi.h>
17#include <linux/ide.h>
18#include <linux/pci.h>
19
20#include <acpi/acpi_bus.h>
21#include <acpi/acnames.h>
22#include <acpi/acnamesp.h>
23#include <acpi/acparser.h>
24#include <acpi/acexcep.h>
25#include <acpi/acmacros.h>
26#include <acpi/actypes.h>
27
28#define REGS_PER_GTF 7
29struct taskfile_array {
30 u8 tfa[REGS_PER_GTF]; /* regs. 0x1f1 - 0x1f7 */
31};
32
33struct GTM_buffer {
34 u32 PIO_speed0;
35 u32 DMA_speed0;
36 u32 PIO_speed1;
37 u32 DMA_speed1;
38 u32 GTM_flags;
39};
40
41struct ide_acpi_drive_link {
42 ide_drive_t *drive;
43 acpi_handle obj_handle;
44 u8 idbuff[512];
45};
46
47struct ide_acpi_hwif_link {
48 ide_hwif_t *hwif;
49 acpi_handle obj_handle;
50 struct GTM_buffer gtm;
51 struct ide_acpi_drive_link master;
52 struct ide_acpi_drive_link slave;
53};
54
55#undef DEBUGGING
56/* note: adds function name and KERN_DEBUG */
57#ifdef DEBUGGING
58#define DEBPRINT(fmt, args...) \
59 printk(KERN_DEBUG "%s: " fmt, __FUNCTION__, ## args)
60#else
61#define DEBPRINT(fmt, args...) do {} while (0)
62#endif /* DEBUGGING */
63
64extern int ide_noacpi;
65extern int ide_noacpitfs;
66extern int ide_noacpionboot;
67
68/**
69 * ide_get_dev_handle - finds acpi_handle and PCI device.function
70 * @dev: device to locate
71 * @handle: returned acpi_handle for @dev
72 * @pcidevfn: return PCI device.func for @dev
73 *
74 * Returns the ACPI object handle to the corresponding PCI device.
75 *
76 * Returns 0 on success, <0 on error.
77 */
78static int ide_get_dev_handle(struct device *dev, acpi_handle *handle,
79 acpi_integer *pcidevfn)
80{
81 struct pci_dev *pdev = to_pci_dev(dev);
82 unsigned int bus, devnum, func;
83 acpi_integer addr;
84 acpi_handle dev_handle;
85 struct acpi_buffer buffer = {.length = ACPI_ALLOCATE_BUFFER,
86 .pointer = NULL};
87 acpi_status status;
88 struct acpi_device_info *dinfo = NULL;
89 int ret = -ENODEV;
90
91 bus = pdev->bus->number;
92 devnum = PCI_SLOT(pdev->devfn);
93 func = PCI_FUNC(pdev->devfn);
94 /* ACPI _ADR encoding for PCI bus: */
95 addr = (acpi_integer)(devnum << 16 | func);
96
97 DEBPRINT("ENTER: pci %02x:%02x.%01x\n", bus, devnum, func);
98
99 dev_handle = DEVICE_ACPI_HANDLE(dev);
100 if (!dev_handle) {
101 DEBPRINT("no acpi handle for device\n");
102 goto err;
103 }
104
105 status = acpi_get_object_info(dev_handle, &buffer);
106 if (ACPI_FAILURE(status)) {
107 DEBPRINT("get_object_info for device failed\n");
108 goto err;
109 }
110 dinfo = buffer.pointer;
111 if (dinfo && (dinfo->valid & ACPI_VALID_ADR) &&
112 dinfo->address == addr) {
113 *pcidevfn = addr;
114 *handle = dev_handle;
115 } else {
116 DEBPRINT("get_object_info for device has wrong "
117 " address: %llu, should be %u\n",
118 dinfo ? (unsigned long long)dinfo->address : -1ULL,
119 (unsigned int)addr);
120 goto err;
121 }
122
123 DEBPRINT("for dev=0x%x.%x, addr=0x%llx, *handle=0x%p\n",
124 devnum, func, (unsigned long long)addr, *handle);
125 ret = 0;
126err:
127 kfree(dinfo);
128 return ret;
129}
130
131/**
132 * ide_acpi_hwif_get_handle - Get ACPI object handle for a given hwif
133 * @hwif: device to locate
134 *
135 * Retrieves the object handle for a given hwif.
136 *
137 * Returns handle on success, 0 on error.
138 */
139static acpi_handle ide_acpi_hwif_get_handle(ide_hwif_t *hwif)
140{
141 struct device *dev = hwif->gendev.parent;
142 acpi_handle dev_handle;
143 acpi_integer pcidevfn;
144 acpi_handle chan_handle;
145 int err;
146
147 DEBPRINT("ENTER: device %s\n", hwif->name);
148
149 if (!dev) {
150 DEBPRINT("no PCI device for %s\n", hwif->name);
151 return NULL;
152 }
153
154 err = ide_get_dev_handle(dev, &dev_handle, &pcidevfn);
155 if (err < 0) {
156 DEBPRINT("ide_get_dev_handle failed (%d)\n", err);
157 return NULL;
158 }
159
160 /* get child objects of dev_handle == channel objects,
161 * + _their_ children == drive objects */
162 /* channel is hwif->channel */
163 chan_handle = acpi_get_child(dev_handle, hwif->channel);
164 DEBPRINT("chan adr=%d: handle=0x%p\n",
165 hwif->channel, chan_handle);
166
167 return chan_handle;
168}
169
170/**
171 * ide_acpi_drive_get_handle - Get ACPI object handle for a given drive
172 * @drive: device to locate
173 *
174 * Retrieves the object handle of a given drive. According to the ACPI
175 * spec the drive is a child of the hwif.
176 *
177 * Returns handle on success, 0 on error.
178 */
179static acpi_handle ide_acpi_drive_get_handle(ide_drive_t *drive)
180{
181 ide_hwif_t *hwif = HWIF(drive);
182 int port;
183 acpi_handle drive_handle;
184
185 if (!hwif->acpidata)
186 return NULL;
187
188 if (!hwif->acpidata->obj_handle)
189 return NULL;
190
191 port = hwif->channel ? drive->dn - 2: drive->dn;
192
193 DEBPRINT("ENTER: %s at channel#: %d port#: %d\n",
194 drive->name, hwif->channel, port);
195
196
197 /* TBD: could also check ACPI object VALID bits */
198 drive_handle = acpi_get_child(hwif->acpidata->obj_handle, port);
199 DEBPRINT("drive %s handle 0x%p\n", drive->name, drive_handle);
200
201 return drive_handle;
202}
203
204/**
205 * do_drive_get_GTF - get the drive bootup default taskfile settings
206 * @drive: the drive for which the taskfile settings should be retrieved
207 * @gtf_length: number of bytes of _GTF data returned at @gtf_address
208 * @gtf_address: buffer containing _GTF taskfile arrays
209 *
210 * The _GTF method has no input parameters.
211 * It returns a variable number of register set values (registers
212 * hex 1F1..1F7, taskfiles).
213 * The <variable number> is not known in advance, so have ACPI-CA
214 * allocate the buffer as needed and return it, then free it later.
215 *
216 * The returned @gtf_length and @gtf_address are only valid if the
217 * function return value is 0.
218 */
219static int do_drive_get_GTF(ide_drive_t *drive,
220 unsigned int *gtf_length, unsigned long *gtf_address,
221 unsigned long *obj_loc)
222{
223 acpi_status status;
224 struct acpi_buffer output;
225 union acpi_object *out_obj;
226 ide_hwif_t *hwif = HWIF(drive);
227 struct device *dev = hwif->gendev.parent;
228 int err = -ENODEV;
229 int port;
230
231 *gtf_length = 0;
232 *gtf_address = 0UL;
233 *obj_loc = 0UL;
234
235 if (ide_noacpi)
236 return 0;
237
238 if (!dev) {
239 DEBPRINT("no PCI device for %s\n", hwif->name);
240 goto out;
241 }
242
243 if (!hwif->acpidata) {
244 DEBPRINT("no ACPI data for %s\n", hwif->name);
245 goto out;
246 }
247
248 port = hwif->channel ? drive->dn - 2: drive->dn;
249
250 if (!drive->acpidata) {
251 if (port == 0) {
252 drive->acpidata = &hwif->acpidata->master;
253 hwif->acpidata->master.drive = drive;
254 } else {
255 drive->acpidata = &hwif->acpidata->slave;
256 hwif->acpidata->slave.drive = drive;
257 }
258 }
259
260 DEBPRINT("ENTER: %s at %s, port#: %d, hard_port#: %d\n",
261 hwif->name, dev->bus_id, port, hwif->channel);
262
263 if (!drive->present) {
264 DEBPRINT("%s drive %d:%d not present\n",
265 hwif->name, hwif->channel, port);
266 goto out;
267 }
268
269 /* Get this drive's _ADR info. if not already known. */
270 if (!drive->acpidata->obj_handle) {
271 drive->acpidata->obj_handle = ide_acpi_drive_get_handle(drive);
272 if (!drive->acpidata->obj_handle) {
273 DEBPRINT("No ACPI object found for %s\n",
274 drive->name);
275 goto out;
276 }
277 }
278
279 /* Setting up output buffer */
280 output.length = ACPI_ALLOCATE_BUFFER;
281 output.pointer = NULL; /* ACPI-CA sets this; save/free it later */
282
283 /* _GTF has no input parameters */
284 err = -EIO;
285 status = acpi_evaluate_object(drive->acpidata->obj_handle, "_GTF",
286 NULL, &output);
287 if (ACPI_FAILURE(status)) {
288 printk(KERN_DEBUG
289 "%s: Run _GTF error: status = 0x%x\n",
290 __FUNCTION__, status);
291 goto out;
292 }
293
294 if (!output.length || !output.pointer) {
295 DEBPRINT("Run _GTF: "
296 "length or ptr is NULL (0x%llx, 0x%p)\n",
297 (unsigned long long)output.length,
298 output.pointer);
299 goto out;
300 }
301
302 out_obj = output.pointer;
303 if (out_obj->type != ACPI_TYPE_BUFFER) {
304 DEBPRINT("Run _GTF: error: "
305 "expected object type of ACPI_TYPE_BUFFER, "
306 "got 0x%x\n", out_obj->type);
307 err = -ENOENT;
308 kfree(output.pointer);
309 goto out;
310 }
311
312 if (!out_obj->buffer.length || !out_obj->buffer.pointer ||
313 out_obj->buffer.length % REGS_PER_GTF) {
314 printk(KERN_ERR
315 "%s: unexpected GTF length (%d) or addr (0x%p)\n",
316 __FUNCTION__, out_obj->buffer.length,
317 out_obj->buffer.pointer);
318 err = -ENOENT;
319 kfree(output.pointer);
320 goto out;
321 }
322
323 *gtf_length = out_obj->buffer.length;
324 *gtf_address = (unsigned long)out_obj->buffer.pointer;
325 *obj_loc = (unsigned long)out_obj;
326 DEBPRINT("returning gtf_length=%d, gtf_address=0x%lx, obj_loc=0x%lx\n",
327 *gtf_length, *gtf_address, *obj_loc);
328 err = 0;
329out:
330 return err;
331}
332
333/**
334 * taskfile_load_raw - send taskfile registers to drive
335 * @drive: drive to which output is sent
336 * @gtf: raw ATA taskfile register set (0x1f1 - 0x1f7)
337 *
338 * Outputs IDE taskfile to the drive.
339 */
340static int taskfile_load_raw(ide_drive_t *drive,
341 const struct taskfile_array *gtf)
342{
343 ide_task_t args;
344 int err = 0;
345
346 DEBPRINT("(0x1f1-1f7): hex: "
347 "%02x %02x %02x %02x %02x %02x %02x\n",
348 gtf->tfa[0], gtf->tfa[1], gtf->tfa[2],
349 gtf->tfa[3], gtf->tfa[4], gtf->tfa[5], gtf->tfa[6]);
350
351 memset(&args, 0, sizeof(ide_task_t));
352 args.command_type = IDE_DRIVE_TASK_NO_DATA;
353 args.data_phase = TASKFILE_IN;
354 args.handler = &task_no_data_intr;
355
356 /* convert gtf to IDE Taskfile */
357 args.tfRegister[1] = gtf->tfa[0]; /* 0x1f1 */
358 args.tfRegister[2] = gtf->tfa[1]; /* 0x1f2 */
359 args.tfRegister[3] = gtf->tfa[2]; /* 0x1f3 */
360 args.tfRegister[4] = gtf->tfa[3]; /* 0x1f4 */
361 args.tfRegister[5] = gtf->tfa[4]; /* 0x1f5 */
362 args.tfRegister[6] = gtf->tfa[5]; /* 0x1f6 */
363 args.tfRegister[7] = gtf->tfa[6]; /* 0x1f7 */
364
365 if (ide_noacpitfs) {
366 DEBPRINT("_GTF execution disabled\n");
367 return err;
368 }
369
370 err = ide_raw_taskfile(drive, &args, NULL);
371 if (err)
372 printk(KERN_ERR "%s: ide_raw_taskfile failed: %u\n",
373 __FUNCTION__, err);
374
375 return err;
376}
377
378/**
379 * do_drive_set_taskfiles - write the drive taskfile settings from _GTF
380 * @drive: the drive to which the taskfile command should be sent
381 * @gtf_length: total number of bytes of _GTF taskfiles
382 * @gtf_address: location of _GTF taskfile arrays
383 *
384 * Write {gtf_address, length gtf_length} in groups of
385 * REGS_PER_GTF bytes.
386 */
387static int do_drive_set_taskfiles(ide_drive_t *drive,
388 unsigned int gtf_length,
389 unsigned long gtf_address)
390{
391 int rc = -ENODEV, err;
392 int gtf_count = gtf_length / REGS_PER_GTF;
393 int ix;
394 struct taskfile_array *gtf;
395
396 if (ide_noacpi)
397 return 0;
398
399 DEBPRINT("ENTER: %s, hard_port#: %d\n", drive->name, drive->dn);
400
401 if (!drive->present)
402 goto out;
403 if (!gtf_count) /* shouldn't be here */
404 goto out;
405
406 DEBPRINT("total GTF bytes=%u (0x%x), gtf_count=%d, addr=0x%lx\n",
407 gtf_length, gtf_length, gtf_count, gtf_address);
408
409 if (gtf_length % REGS_PER_GTF) {
410 printk(KERN_ERR "%s: unexpected GTF length (%d)\n",
411 __FUNCTION__, gtf_length);
412 goto out;
413 }
414
415 rc = 0;
416 for (ix = 0; ix < gtf_count; ix++) {
417 gtf = (struct taskfile_array *)
418 (gtf_address + ix * REGS_PER_GTF);
419
420 /* send all TaskFile registers (0x1f1-0x1f7) *in*that*order* */
421 err = taskfile_load_raw(drive, gtf);
422 if (err)
423 rc = err;
424 }
425
426out:
427 return rc;
428}
429
430/**
431 * ide_acpi_exec_tfs - get then write drive taskfile settings
432 * @drive: the drive for which the taskfile settings should be
433 * written.
434 *
435 * According to the ACPI spec this should be called after _STM
436 * has been evaluated for the interface. Some ACPI vendors interpret
437 * that as a hard requirement and modify the taskfile according
438 * to the Identify Drive information passed down with _STM.
439 * So one should really make sure to call this only after _STM has
440 * been executed.
441 */
442int ide_acpi_exec_tfs(ide_drive_t *drive)
443{
444 int ret;
445 unsigned int gtf_length;
446 unsigned long gtf_address;
447 unsigned long obj_loc;
448
449 if (ide_noacpi)
450 return 0;
451
452 DEBPRINT("call get_GTF, drive=%s port=%d\n", drive->name, drive->dn);
453
454 ret = do_drive_get_GTF(drive, &gtf_length, &gtf_address, &obj_loc);
455 if (ret < 0) {
456 DEBPRINT("get_GTF error (%d)\n", ret);
457 return ret;
458 }
459
460 DEBPRINT("call set_taskfiles, drive=%s\n", drive->name);
461
462 ret = do_drive_set_taskfiles(drive, gtf_length, gtf_address);
463 kfree((void *)obj_loc);
464 if (ret < 0) {
465 DEBPRINT("set_taskfiles error (%d)\n", ret);
466 }
467
468 DEBPRINT("ret=%d\n", ret);
469
470 return ret;
471}
472EXPORT_SYMBOL_GPL(ide_acpi_exec_tfs);
473
474/**
475 * ide_acpi_get_timing - get the channel (controller) timings
476 * @hwif: target IDE interface (channel)
477 *
478 * This function executes the _GTM ACPI method for the target channel.
479 *
480 */
481void ide_acpi_get_timing(ide_hwif_t *hwif)
482{
483 acpi_status status;
484 struct acpi_buffer output;
485 union acpi_object *out_obj;
486
487 if (ide_noacpi)
488 return;
489
490 DEBPRINT("ENTER:\n");
491
492 if (!hwif->acpidata) {
493 DEBPRINT("no ACPI data for %s\n", hwif->name);
494 return;
495 }
496
497 /* Setting up output buffer for _GTM */
498 output.length = ACPI_ALLOCATE_BUFFER;
499 output.pointer = NULL; /* ACPI-CA sets this; save/free it later */
500
501 /* _GTM has no input parameters */
502 status = acpi_evaluate_object(hwif->acpidata->obj_handle, "_GTM",
503 NULL, &output);
504
505 DEBPRINT("_GTM status: %d, outptr: 0x%p, outlen: 0x%llx\n",
506 status, output.pointer,
507 (unsigned long long)output.length);
508
509 if (ACPI_FAILURE(status)) {
510 DEBPRINT("Run _GTM error: status = 0x%x\n", status);
511 return;
512 }
513
514 if (!output.length || !output.pointer) {
515 DEBPRINT("Run _GTM: length or ptr is NULL (0x%llx, 0x%p)\n",
516 (unsigned long long)output.length,
517 output.pointer);
518 kfree(output.pointer);
519 return;
520 }
521
522 out_obj = output.pointer;
523 if (out_obj->type != ACPI_TYPE_BUFFER) {
524 kfree(output.pointer);
525 DEBPRINT("Run _GTM: error: "
526 "expected object type of ACPI_TYPE_BUFFER, "
527 "got 0x%x\n", out_obj->type);
528 return;
529 }
530
531 if (!out_obj->buffer.length || !out_obj->buffer.pointer ||
532 out_obj->buffer.length != sizeof(struct GTM_buffer)) {
533 kfree(output.pointer);
534 printk(KERN_ERR
535 "%s: unexpected _GTM length (0x%x)[should be 0x%zx] or "
536 "addr (0x%p)\n",
537 __FUNCTION__, out_obj->buffer.length,
538 sizeof(struct GTM_buffer), out_obj->buffer.pointer);
539 return;
540 }
541
542 memcpy(&hwif->acpidata->gtm, out_obj->buffer.pointer,
543 sizeof(struct GTM_buffer));
544
545 DEBPRINT("_GTM info: ptr: 0x%p, len: 0x%x, exp.len: 0x%Zx\n",
546 out_obj->buffer.pointer, out_obj->buffer.length,
547 sizeof(struct GTM_buffer));
548
549 DEBPRINT("_GTM fields: 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
550 hwif->acpidata->gtm.PIO_speed0,
551 hwif->acpidata->gtm.DMA_speed0,
552 hwif->acpidata->gtm.PIO_speed1,
553 hwif->acpidata->gtm.DMA_speed1,
554 hwif->acpidata->gtm.GTM_flags);
555
556 kfree(output.pointer);
557}
558EXPORT_SYMBOL_GPL(ide_acpi_get_timing);
559
560/**
561 * ide_acpi_push_timing - set the channel (controller) timings
562 * @hwif: target IDE interface (channel)
563 *
564 * This function executes the _STM ACPI method for the target channel.
565 *
566 * _STM requires Identify Drive data, which has to passed as an argument.
567 * Unfortunately hd_driveid is a mangled version which we can't readily
568 * use; hence we'll get the information afresh.
569 */
570void ide_acpi_push_timing(ide_hwif_t *hwif)
571{
572 acpi_status status;
573 struct acpi_object_list input;
574 union acpi_object in_params[3];
575 struct ide_acpi_drive_link *master = &hwif->acpidata->master;
576 struct ide_acpi_drive_link *slave = &hwif->acpidata->slave;
577
578 if (ide_noacpi)
579 return;
580
581 DEBPRINT("ENTER:\n");
582
583 if (!hwif->acpidata) {
584 DEBPRINT("no ACPI data for %s\n", hwif->name);
585 return;
586 }
587
588 /* Give the GTM buffer + drive Identify data to the channel via the
589 * _STM method: */
590 /* setup input parameters buffer for _STM */
591 input.count = 3;
592 input.pointer = in_params;
593 in_params[0].type = ACPI_TYPE_BUFFER;
594 in_params[0].buffer.length = sizeof(struct GTM_buffer);
595 in_params[0].buffer.pointer = (u8 *)&hwif->acpidata->gtm;
596 in_params[1].type = ACPI_TYPE_BUFFER;
597 in_params[1].buffer.length = sizeof(struct hd_driveid);
598 in_params[1].buffer.pointer = (u8 *)&master->idbuff;
599 in_params[2].type = ACPI_TYPE_BUFFER;
600 in_params[2].buffer.length = sizeof(struct hd_driveid);
601 in_params[2].buffer.pointer = (u8 *)&slave->idbuff;
602 /* Output buffer: _STM has no output */
603
604 status = acpi_evaluate_object(hwif->acpidata->obj_handle, "_STM",
605 &input, NULL);
606
607 if (ACPI_FAILURE(status)) {
608 DEBPRINT("Run _STM error: status = 0x%x\n", status);
609 }
610 DEBPRINT("_STM status: %d\n", status);
611}
612EXPORT_SYMBOL_GPL(ide_acpi_push_timing);
613
614/**
615 * ide_acpi_init - initialize the ACPI link for an IDE interface
616 * @hwif: target IDE interface (channel)
617 *
618 * The ACPI spec is not quite clear when the drive identify buffer
619 * should be obtained. Calling IDENTIFY DEVICE during shutdown
620 * is not the best of ideas as the drive might already being put to
621 * sleep. And obviously we can't call it during resume.
622 * So we get the information during startup; but this means that
623 * any changes during run-time will be lost after resume.
624 */
625void ide_acpi_init(ide_hwif_t *hwif)
626{
627 int unit;
628 int err;
629 struct ide_acpi_drive_link *master;
630 struct ide_acpi_drive_link *slave;
631
632 hwif->acpidata = kzalloc(sizeof(struct ide_acpi_hwif_link), GFP_KERNEL);
633 if (!hwif->acpidata)
634 return;
635
636 hwif->acpidata->obj_handle = ide_acpi_hwif_get_handle(hwif);
637 if (!hwif->acpidata->obj_handle) {
638 DEBPRINT("no ACPI object for %s found\n", hwif->name);
639 kfree(hwif->acpidata);
640 hwif->acpidata = NULL;
641 return;
642 }
643
644 /*
645 * The ACPI spec mandates that we send information
646 * for both drives, regardless whether they are connected
647 * or not.
648 */
649 hwif->acpidata->master.drive = &hwif->drives[0];
650 hwif->drives[0].acpidata = &hwif->acpidata->master;
651 master = &hwif->acpidata->master;
652
653 hwif->acpidata->slave.drive = &hwif->drives[1];
654 hwif->drives[1].acpidata = &hwif->acpidata->slave;
655 slave = &hwif->acpidata->slave;
656
657
658 /*
659 * Send IDENTIFY for each drive
660 */
661 if (master->drive->present) {
662 err = taskfile_lib_get_identify(master->drive, master->idbuff);
663 if (err) {
664 DEBPRINT("identify device %s failed (%d)\n",
665 master->drive->name, err);
666 }
667 }
668
669 if (slave->drive->present) {
670 err = taskfile_lib_get_identify(slave->drive, slave->idbuff);
671 if (err) {
672 DEBPRINT("identify device %s failed (%d)\n",
673 slave->drive->name, err);
674 }
675 }
676
677 if (ide_noacpionboot) {
678 DEBPRINT("ACPI methods disabled on boot\n");
679 return;
680 }
681
682 /*
683 * ACPI requires us to call _STM on startup
684 */
685 ide_acpi_get_timing(hwif);
686 ide_acpi_push_timing(hwif);
687
688 for (unit = 0; unit < MAX_DRIVES; ++unit) {
689 ide_drive_t *drive = &hwif->drives[unit];
690
691 if (drive->present) {
692 /* Execute ACPI startup code */
693 ide_acpi_exec_tfs(drive);
694 }
695 }
696}
697EXPORT_SYMBOL_GPL(ide_acpi_init);
diff --git a/drivers/ide/ide-probe.c b/drivers/ide/ide-probe.c
index 5a5c565a32a8..176bbc850d6b 100644
--- a/drivers/ide/ide-probe.c
+++ b/drivers/ide/ide-probe.c
@@ -1384,6 +1384,9 @@ static int hwif_init(ide_hwif_t *hwif)
1384 1384
1385done: 1385done:
1386 init_gendisk(hwif); 1386 init_gendisk(hwif);
1387
1388 ide_acpi_init(hwif);
1389
1387 hwif->present = 1; /* success */ 1390 hwif->present = 1; /* success */
1388 return 1; 1391 return 1;
1389 1392
diff --git a/drivers/ide/ide.c b/drivers/ide/ide.c
index 6c9bd5165bdb..c750f6ce770a 100644
--- a/drivers/ide/ide.c
+++ b/drivers/ide/ide.c
@@ -187,6 +187,12 @@ int noautodma = 1;
187 187
188EXPORT_SYMBOL(noautodma); 188EXPORT_SYMBOL(noautodma);
189 189
190#ifdef CONFIG_BLK_DEV_IDEACPI
191int ide_noacpi = 0;
192int ide_noacpitfs = 1;
193int ide_noacpionboot = 1;
194#endif
195
190/* 196/*
191 * This is declared extern in ide.h, for access by other IDE modules: 197 * This is declared extern in ide.h, for access by other IDE modules:
192 */ 198 */
@@ -1214,10 +1220,15 @@ EXPORT_SYMBOL(system_bus_clock);
1214static int generic_ide_suspend(struct device *dev, pm_message_t mesg) 1220static int generic_ide_suspend(struct device *dev, pm_message_t mesg)
1215{ 1221{
1216 ide_drive_t *drive = dev->driver_data; 1222 ide_drive_t *drive = dev->driver_data;
1223 ide_hwif_t *hwif = HWIF(drive);
1217 struct request rq; 1224 struct request rq;
1218 struct request_pm_state rqpm; 1225 struct request_pm_state rqpm;
1219 ide_task_t args; 1226 ide_task_t args;
1220 1227
1228 /* Call ACPI _GTM only once */
1229 if (!(drive->dn % 2))
1230 ide_acpi_get_timing(hwif);
1231
1221 memset(&rq, 0, sizeof(rq)); 1232 memset(&rq, 0, sizeof(rq));
1222 memset(&rqpm, 0, sizeof(rqpm)); 1233 memset(&rqpm, 0, sizeof(rqpm));
1223 memset(&args, 0, sizeof(args)); 1234 memset(&args, 0, sizeof(args));
@@ -1235,10 +1246,17 @@ static int generic_ide_suspend(struct device *dev, pm_message_t mesg)
1235static int generic_ide_resume(struct device *dev) 1246static int generic_ide_resume(struct device *dev)
1236{ 1247{
1237 ide_drive_t *drive = dev->driver_data; 1248 ide_drive_t *drive = dev->driver_data;
1249 ide_hwif_t *hwif = HWIF(drive);
1238 struct request rq; 1250 struct request rq;
1239 struct request_pm_state rqpm; 1251 struct request_pm_state rqpm;
1240 ide_task_t args; 1252 ide_task_t args;
1241 1253
1254 /* Call ACPI _STM only once */
1255 if (!(drive->dn % 2))
1256 ide_acpi_push_timing(hwif);
1257
1258 ide_acpi_exec_tfs(drive);
1259
1242 memset(&rq, 0, sizeof(rq)); 1260 memset(&rq, 0, sizeof(rq));
1243 memset(&rqpm, 0, sizeof(rqpm)); 1261 memset(&rqpm, 0, sizeof(rqpm));
1244 memset(&args, 0, sizeof(args)); 1262 memset(&args, 0, sizeof(args));
@@ -1543,6 +1561,24 @@ static int __init ide_setup(char *s)
1543 } 1561 }
1544#endif /* CONFIG_BLK_DEV_IDEPCI */ 1562#endif /* CONFIG_BLK_DEV_IDEPCI */
1545 1563
1564#ifdef CONFIG_BLK_DEV_IDEACPI
1565 if (!strcmp(s, "ide=noacpi")) {
1566 //printk(" : Disable IDE ACPI support.\n");
1567 ide_noacpi = 1;
1568 return 1;
1569 }
1570 if (!strcmp(s, "ide=acpigtf")) {
1571 //printk(" : Enable IDE ACPI _GTF support.\n");
1572 ide_noacpitfs = 0;
1573 return 1;
1574 }
1575 if (!strcmp(s, "ide=acpionboot")) {
1576 //printk(" : Call IDE ACPI methods on boot.\n");
1577 ide_noacpionboot = 0;
1578 return 1;
1579 }
1580#endif /* CONFIG_BLK_DEV_IDEACPI */
1581
1546 /* 1582 /*
1547 * Look for drive options: "hdx=" 1583 * Look for drive options: "hdx="
1548 */ 1584 */
diff --git a/drivers/ide/pci/Makefile b/drivers/ide/pci/Makefile
index fef08960aa4c..6591ff4753cb 100644
--- a/drivers/ide/pci/Makefile
+++ b/drivers/ide/pci/Makefile
@@ -9,9 +9,10 @@ obj-$(CONFIG_BLK_DEV_CS5530) += cs5530.o
9obj-$(CONFIG_BLK_DEV_CS5535) += cs5535.o 9obj-$(CONFIG_BLK_DEV_CS5535) += cs5535.o
10obj-$(CONFIG_BLK_DEV_SC1200) += sc1200.o 10obj-$(CONFIG_BLK_DEV_SC1200) += sc1200.o
11obj-$(CONFIG_BLK_DEV_CY82C693) += cy82c693.o 11obj-$(CONFIG_BLK_DEV_CY82C693) += cy82c693.o
12obj-$(CONFIG_BLK_DEV_DELKIN) += delkin_cb.o
12obj-$(CONFIG_BLK_DEV_HPT34X) += hpt34x.o 13obj-$(CONFIG_BLK_DEV_HPT34X) += hpt34x.o
13obj-$(CONFIG_BLK_DEV_HPT366) += hpt366.o 14obj-$(CONFIG_BLK_DEV_HPT366) += hpt366.o
14#obj-$(CONFIG_BLK_DEV_HPT37X) += hpt37x.o 15obj-$(CONFIG_BLK_DEV_IT8213) += it8213.o
15obj-$(CONFIG_BLK_DEV_IT821X) += it821x.o 16obj-$(CONFIG_BLK_DEV_IT821X) += it821x.o
16obj-$(CONFIG_BLK_DEV_JMICRON) += jmicron.o 17obj-$(CONFIG_BLK_DEV_JMICRON) += jmicron.o
17obj-$(CONFIG_BLK_DEV_NS87415) += ns87415.o 18obj-$(CONFIG_BLK_DEV_NS87415) += ns87415.o
@@ -26,6 +27,7 @@ obj-$(CONFIG_BLK_DEV_SIIMAGE) += siimage.o
26obj-$(CONFIG_BLK_DEV_SIS5513) += sis5513.o 27obj-$(CONFIG_BLK_DEV_SIS5513) += sis5513.o
27obj-$(CONFIG_BLK_DEV_SL82C105) += sl82c105.o 28obj-$(CONFIG_BLK_DEV_SL82C105) += sl82c105.o
28obj-$(CONFIG_BLK_DEV_SLC90E66) += slc90e66.o 29obj-$(CONFIG_BLK_DEV_SLC90E66) += slc90e66.o
30obj-$(CONFIG_BLK_DEV_TC86C001) += tc86c001.o
29obj-$(CONFIG_BLK_DEV_TRIFLEX) += triflex.o 31obj-$(CONFIG_BLK_DEV_TRIFLEX) += triflex.o
30obj-$(CONFIG_BLK_DEV_TRM290) += trm290.o 32obj-$(CONFIG_BLK_DEV_TRM290) += trm290.o
31obj-$(CONFIG_BLK_DEV_VIA82CXXX) += via82cxxx.o 33obj-$(CONFIG_BLK_DEV_VIA82CXXX) += via82cxxx.o
diff --git a/drivers/ide/pci/delkin_cb.c b/drivers/ide/pci/delkin_cb.c
new file mode 100644
index 000000000000..e2672fc65d30
--- /dev/null
+++ b/drivers/ide/pci/delkin_cb.c
@@ -0,0 +1,140 @@
1/*
2 * linux/drivers/ide/pci/delkin_cb.c
3 *
4 * Created 20 Oct 2004 by Mark Lord
5 *
6 * Basic support for Delkin/ASKA/Workbit Cardbus CompactFlash adapter
7 *
8 * Modeled after the 16-bit PCMCIA driver: ide-cs.c
9 *
10 * This is slightly peculiar, in that it is a PCI driver,
11 * but is NOT an IDE PCI driver -- the IDE layer does not directly
12 * support hot insertion/removal of PCI interfaces, so this driver
13 * is unable to use the IDE PCI interfaces. Instead, it uses the
14 * same interfaces as the ide-cs (PCMCIA) driver uses.
15 * On the plus side, the driver is also smaller/simpler this way.
16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file COPYING in the main directory of this archive for
19 * more details.
20 */
21#include <linux/autoconf.h>
22#include <linux/types.h>
23#include <linux/module.h>
24#include <linux/mm.h>
25#include <linux/blkdev.h>
26#include <linux/hdreg.h>
27#include <linux/ide.h>
28#include <linux/init.h>
29#include <linux/pci.h>
30#include <asm/io.h>
31
32/*
33 * No chip documentation has yet been found,
34 * so these configuration values were pulled from
35 * a running Win98 system using "debug".
36 * This gives around 3MByte/second read performance,
37 * which is about 2/3 of what the chip is capable of.
38 *
39 * There is also a 4KByte mmio region on the card,
40 * but its purpose has yet to be reverse-engineered.
41 */
42static const u8 setup[] = {
43 0x00, 0x05, 0xbe, 0x01, 0x20, 0x8f, 0x00, 0x00,
44 0xa4, 0x1f, 0xb3, 0x1b, 0x00, 0x00, 0x00, 0x80,
45 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
46 0x00, 0x00, 0x00, 0x00, 0xa4, 0x83, 0x02, 0x13,
47};
48
49static int __devinit
50delkin_cb_probe (struct pci_dev *dev, const struct pci_device_id *id)
51{
52 unsigned long base;
53 hw_regs_t hw;
54 ide_hwif_t *hwif = NULL;
55 ide_drive_t *drive;
56 int i, rc;
57
58 rc = pci_enable_device(dev);
59 if (rc) {
60 printk(KERN_ERR "delkin_cb: pci_enable_device failed (%d)\n", rc);
61 return rc;
62 }
63 rc = pci_request_regions(dev, "delkin_cb");
64 if (rc) {
65 printk(KERN_ERR "delkin_cb: pci_request_regions failed (%d)\n", rc);
66 pci_disable_device(dev);
67 return rc;
68 }
69 base = pci_resource_start(dev, 0);
70 outb(0x02, base + 0x1e); /* set nIEN to block interrupts */
71 inb(base + 0x17); /* read status to clear interrupts */
72 for (i = 0; i < sizeof(setup); ++i) {
73 if (setup[i])
74 outb(setup[i], base + i);
75 }
76 pci_release_regions(dev); /* IDE layer handles regions itself */
77
78 memset(&hw, 0, sizeof(hw));
79 ide_std_init_ports(&hw, base + 0x10, base + 0x1e);
80 hw.irq = dev->irq;
81 hw.chipset = ide_pci; /* this enables IRQ sharing */
82
83 rc = ide_register_hw_with_fixup(&hw, &hwif, ide_undecoded_slave);
84 if (rc < 0) {
85 printk(KERN_ERR "delkin_cb: ide_register_hw failed (%d)\n", rc);
86 pci_disable_device(dev);
87 return -ENODEV;
88 }
89 pci_set_drvdata(dev, hwif);
90 hwif->pci_dev = dev;
91 drive = &hwif->drives[0];
92 if (drive->present) {
93 drive->io_32bit = 1;
94 drive->unmask = 1;
95 }
96 return 0;
97}
98
99static void
100delkin_cb_remove (struct pci_dev *dev)
101{
102 ide_hwif_t *hwif = pci_get_drvdata(dev);
103
104 if (hwif)
105 ide_unregister(hwif->index);
106 pci_disable_device(dev);
107}
108
109static struct pci_device_id delkin_cb_pci_tbl[] __devinitdata = {
110 { 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
111 { 0, },
112};
113MODULE_DEVICE_TABLE(pci, delkin_cb_pci_tbl);
114
115static struct pci_driver driver = {
116 .name = "Delkin-ASKA-Workbit Cardbus IDE",
117 .id_table = delkin_cb_pci_tbl,
118 .probe = delkin_cb_probe,
119 .remove = delkin_cb_remove,
120};
121
122static int
123delkin_cb_init (void)
124{
125 return pci_module_init(&driver);
126}
127
128static void
129delkin_cb_exit (void)
130{
131 pci_unregister_driver(&driver);
132}
133
134module_init(delkin_cb_init);
135module_exit(delkin_cb_exit);
136
137MODULE_AUTHOR("Mark Lord");
138MODULE_DESCRIPTION("Basic support for Delkin/ASKA/Workbit Cardbus IDE");
139MODULE_LICENSE("GPL");
140
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c
index b486442dd5d7..05be8fadda7a 100644
--- a/drivers/ide/pci/hpt366.c
+++ b/drivers/ide/pci/hpt366.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 2 * linux/drivers/ide/pci/hpt366.c Version 1.01 Dec 23, 2006
3 * 3 *
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
@@ -60,13 +60,10 @@
60 * channel caused the cached register value to get out of sync with the 60 * channel caused the cached register value to get out of sync with the
61 * actual one, the channels weren't serialized, the turnaround shouldn't 61 * actual one, the channels weren't serialized, the turnaround shouldn't
62 * be done on 66 MHz PCI bus 62 * be done on 66 MHz PCI bus
63 * - avoid calibrating PLL twice as the second time results in a wrong PCI 63 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
64 * frequency and thus in the wrong timings for the secondary channel 64 * does not allow for this speed anyway
65 * - disable UltraATA/133 for HPT372 by default (50 MHz DPLL clock do not 65 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
66 * allow for this speed anyway) 66 * their primary channel is kind of virtual, it isn't tied to any pins)
67 * - add support for HPT302N and HPT371N clocking (the same as for HPT372N)
68 * - HPT371/N are single channel chips, so avoid touching the primary channel
69 * which exists only virtually (there's no pins for it)
70 * - fix/remove bad/unused timing tables and use one set of tables for the whole 67 * - fix/remove bad/unused timing tables and use one set of tables for the whole
71 * HPT37x chip family; save space by introducing the separate transfer mode 68 * HPT37x chip family; save space by introducing the separate transfer mode
72 * table in which the mode lookup is done 69 * table in which the mode lookup is done
@@ -76,11 +73,47 @@
76 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead 73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
77 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as 74 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
78 * they tamper with its fields 75 * they tamper with its fields
79 * <source@mvista.com> 76 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
80 * 77 * since they may tamper with its fields
78 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
80 * - optimize the rate masking/filtering and the drive list lookup code
81 * - use pci_get_slot() to get to the function 1 of HPT36x/374
82 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
85 * function 1
86 * - rename all the register related variables consistently
87 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
89 * - merge two HPT37x speedproc handlers, fix the PIO timing register mask and
90 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
94 * - clean up DMA timeout handling for HPT370
95 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
97 * init_setup stage
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
102 * supported DMA mode, and the chip settings table pointer filled, then, at
103 * the init_chipset stage, allocate per-chip instance and fill it with the
104 * rest of the necessary information
105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
107 * frequency
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
109 * anything newer than HPT370/A
110 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
111 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
112 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
113 * the register setting lists into the table indexed by the clock selected
114 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
81 */ 115 */
82 116
83
84#include <linux/types.h> 117#include <linux/types.h>
85#include <linux/module.h> 118#include <linux/module.h>
86#include <linux/kernel.h> 119#include <linux/kernel.h>
@@ -332,93 +365,159 @@ static u32 sixty_six_base_hpt37x[] = {
332}; 365};
333 366
334#define HPT366_DEBUG_DRIVE_INFO 0 367#define HPT366_DEBUG_DRIVE_INFO 0
335#define HPT374_ALLOW_ATA133_6 0 368#define HPT374_ALLOW_ATA133_6 1
336#define HPT371_ALLOW_ATA133_6 0 369#define HPT371_ALLOW_ATA133_6 1
337#define HPT302_ALLOW_ATA133_6 0 370#define HPT302_ALLOW_ATA133_6 1
338#define HPT372_ALLOW_ATA133_6 0 371#define HPT372_ALLOW_ATA133_6 1
339#define HPT370_ALLOW_ATA100_5 1 372#define HPT370_ALLOW_ATA100_5 0
340#define HPT366_ALLOW_ATA66_4 1 373#define HPT366_ALLOW_ATA66_4 1
341#define HPT366_ALLOW_ATA66_3 1 374#define HPT366_ALLOW_ATA66_3 1
342#define HPT366_MAX_DEVS 8 375#define HPT366_MAX_DEVS 8
343 376
344#define F_LOW_PCI_33 0x23 377/* Supported ATA clock frequencies */
345#define F_LOW_PCI_40 0x29 378enum ata_clock {
346#define F_LOW_PCI_50 0x2d 379 ATA_CLOCK_25MHZ,
347#define F_LOW_PCI_66 0x42 380 ATA_CLOCK_33MHZ,
381 ATA_CLOCK_40MHZ,
382 ATA_CLOCK_50MHZ,
383 ATA_CLOCK_66MHZ,
384 NUM_ATA_CLOCKS
385};
348 386
349/* 387/*
350 * Hold all the highpoint quirks and revision information in one 388 * Hold all the HighPoint chip information in one place.
351 * place.
352 */ 389 */
353 390
354struct hpt_info 391struct hpt_info {
355{ 392 u8 chip_type; /* Chip type */
356 u8 max_mode; /* Speeds allowed */ 393 u8 max_mode; /* Speeds allowed */
357 int revision; /* Chipset revision */ 394 u8 dpll_clk; /* DPLL clock in MHz */
358 int flags; /* Chipset properties */ 395 u8 pci_clk; /* PCI clock in MHz */
359#define PLL_MODE 1 396 u32 **settings; /* Chipset settings table */
360#define IS_3xxN 2
361#define PCI_66MHZ 4
362 /* Speed table */
363 u32 *speed;
364}; 397};
365 398
366/* 399/* Supported HighPoint chips */
367 * This wants fixing so that we do everything not by classrev 400enum {
368 * (which breaks on the newest chips) but by creating an 401 HPT36x,
369 * enumeration of chip variants and using that 402 HPT370,
370 */ 403 HPT370A,
404 HPT374,
405 HPT372,
406 HPT372A,
407 HPT302,
408 HPT371,
409 HPT372N,
410 HPT302N,
411 HPT371N
412};
413
414static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = {
415 twenty_five_base_hpt36x,
416 thirty_three_base_hpt36x,
417 forty_base_hpt36x,
418 NULL,
419 NULL
420};
421
422static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
423 NULL,
424 thirty_three_base_hpt37x,
425 NULL,
426 fifty_base_hpt37x,
427 sixty_six_base_hpt37x
428};
429
430static struct hpt_info hpt36x __devinitdata = {
431 .chip_type = HPT36x,
432 .max_mode = (HPT366_ALLOW_ATA66_4 || HPT366_ALLOW_ATA66_3) ? 2 : 1,
433 .dpll_clk = 0, /* no DPLL */
434 .settings = hpt36x_settings
435};
436
437static struct hpt_info hpt370 __devinitdata = {
438 .chip_type = HPT370,
439 .max_mode = HPT370_ALLOW_ATA100_5 ? 3 : 2,
440 .dpll_clk = 48,
441 .settings = hpt37x_settings
442};
443
444static struct hpt_info hpt370a __devinitdata = {
445 .chip_type = HPT370A,
446 .max_mode = HPT370_ALLOW_ATA100_5 ? 3 : 2,
447 .dpll_clk = 48,
448 .settings = hpt37x_settings
449};
450
451static struct hpt_info hpt374 __devinitdata = {
452 .chip_type = HPT374,
453 .max_mode = HPT374_ALLOW_ATA133_6 ? 4 : 3,
454 .dpll_clk = 48,
455 .settings = hpt37x_settings
456};
457
458static struct hpt_info hpt372 __devinitdata = {
459 .chip_type = HPT372,
460 .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3,
461 .dpll_clk = 55,
462 .settings = hpt37x_settings
463};
464
465static struct hpt_info hpt372a __devinitdata = {
466 .chip_type = HPT372A,
467 .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3,
468 .dpll_clk = 66,
469 .settings = hpt37x_settings
470};
471
472static struct hpt_info hpt302 __devinitdata = {
473 .chip_type = HPT302,
474 .max_mode = HPT302_ALLOW_ATA133_6 ? 4 : 3,
475 .dpll_clk = 66,
476 .settings = hpt37x_settings
477};
478
479static struct hpt_info hpt371 __devinitdata = {
480 .chip_type = HPT371,
481 .max_mode = HPT371_ALLOW_ATA133_6 ? 4 : 3,
482 .dpll_clk = 66,
483 .settings = hpt37x_settings
484};
485
486static struct hpt_info hpt372n __devinitdata = {
487 .chip_type = HPT372N,
488 .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3,
489 .dpll_clk = 77,
490 .settings = hpt37x_settings
491};
492
493static struct hpt_info hpt302n __devinitdata = {
494 .chip_type = HPT302N,
495 .max_mode = HPT302_ALLOW_ATA133_6 ? 4 : 3,
496 .dpll_clk = 77,
497};
371 498
372static __devinit u32 hpt_revision (struct pci_dev *dev) 499static struct hpt_info hpt371n __devinitdata = {
500 .chip_type = HPT371N,
501 .max_mode = HPT371_ALLOW_ATA133_6 ? 4 : 3,
502 .dpll_clk = 77,
503 .settings = hpt37x_settings
504};
505
506static int check_in_drive_list(ide_drive_t *drive, const char **list)
373{ 507{
374 u32 class_rev; 508 struct hd_driveid *id = drive->id;
375 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
376 class_rev &= 0xff;
377
378 switch(dev->device) {
379 /* Remap new 372N onto 372 */
380 case PCI_DEVICE_ID_TTI_HPT372N:
381 class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
382 case PCI_DEVICE_ID_TTI_HPT374:
383 class_rev = PCI_DEVICE_ID_TTI_HPT374; break;
384 case PCI_DEVICE_ID_TTI_HPT371:
385 class_rev = PCI_DEVICE_ID_TTI_HPT371; break;
386 case PCI_DEVICE_ID_TTI_HPT302:
387 class_rev = PCI_DEVICE_ID_TTI_HPT302; break;
388 case PCI_DEVICE_ID_TTI_HPT372:
389 class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
390 default:
391 break;
392 }
393 return class_rev;
394}
395 509
396static int check_in_drive_lists(ide_drive_t *drive, const char **list); 510 while (*list)
511 if (!strcmp(*list++,id->model))
512 return 1;
513 return 0;
514}
397 515
398static u8 hpt3xx_ratemask (ide_drive_t *drive) 516static u8 hpt3xx_ratemask(ide_drive_t *drive)
399{ 517{
400 ide_hwif_t *hwif = drive->hwif; 518 struct hpt_info *info = pci_get_drvdata(HWIF(drive)->pci_dev);
401 struct hpt_info *info = ide_get_hwifdata(hwif); 519 u8 mode = info->max_mode;
402 u8 mode = 0; 520
403
404 /* FIXME: TODO - move this to set info->mode once at boot */
405
406 if (info->revision >= 8) { /* HPT374 */
407 mode = (HPT374_ALLOW_ATA133_6) ? 4 : 3;
408 } else if (info->revision >= 7) { /* HPT371 */
409 mode = (HPT371_ALLOW_ATA133_6) ? 4 : 3;
410 } else if (info->revision >= 6) { /* HPT302 */
411 mode = (HPT302_ALLOW_ATA133_6) ? 4 : 3;
412 } else if (info->revision >= 5) { /* HPT372 */
413 mode = (HPT372_ALLOW_ATA133_6) ? 4 : 3;
414 } else if (info->revision >= 4) { /* HPT370A */
415 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
416 } else if (info->revision >= 3) { /* HPT370 */
417 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
418 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : mode;
419 } else { /* HPT366 and HPT368 */
420 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : 2;
421 }
422 if (!eighty_ninty_three(drive) && mode) 521 if (!eighty_ninty_three(drive) && mode)
423 mode = min(mode, (u8)1); 522 mode = min(mode, (u8)1);
424 return mode; 523 return mode;
@@ -429,75 +528,61 @@ static u8 hpt3xx_ratemask (ide_drive_t *drive)
429 * either PIO or UDMA modes 0,4,5 528 * either PIO or UDMA modes 0,4,5
430 */ 529 */
431 530
432static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed) 531static u8 hpt3xx_ratefilter(ide_drive_t *drive, u8 speed)
433{ 532{
434 ide_hwif_t *hwif = drive->hwif; 533 struct hpt_info *info = pci_get_drvdata(HWIF(drive)->pci_dev);
435 struct hpt_info *info = ide_get_hwifdata(hwif); 534 u8 chip_type = info->chip_type;
436 u8 mode = hpt3xx_ratemask(drive); 535 u8 mode = hpt3xx_ratemask(drive);
437 536
438 if (drive->media != ide_disk) 537 if (drive->media != ide_disk)
439 return min(speed, (u8)XFER_PIO_4); 538 return min(speed, (u8)XFER_PIO_4);
440 539
441 switch(mode) { 540 switch (mode) {
442 case 0x04: 541 case 0x04:
443 speed = min(speed, (u8)XFER_UDMA_6); 542 speed = min_t(u8, speed, XFER_UDMA_6);
444 break; 543 break;
445 case 0x03: 544 case 0x03:
446 speed = min(speed, (u8)XFER_UDMA_5); 545 speed = min_t(u8, speed, XFER_UDMA_5);
447 if (info->revision >= 5) 546 if (chip_type >= HPT374)
448 break; 547 break;
449 if (check_in_drive_lists(drive, bad_ata100_5)) 548 if (!check_in_drive_list(drive, bad_ata100_5))
450 speed = min(speed, (u8)XFER_UDMA_4); 549 goto check_bad_ata33;
451 break; 550 /* fall thru */
452 case 0x02: 551 case 0x02:
453 speed = min(speed, (u8)XFER_UDMA_4); 552 speed = min_t(u8, speed, XFER_UDMA_4);
454 /* 553
455 * CHECK ME, Does this need to be set to 5 ?? 554 /*
456 */ 555 * CHECK ME, Does this need to be changed to HPT374 ??
457 if (info->revision >= 3) 556 */
458 break; 557 if (chip_type >= HPT370)
459 if ((check_in_drive_lists(drive, bad_ata66_4)) || 558 goto check_bad_ata33;
460 (!(HPT366_ALLOW_ATA66_4))) 559 if (HPT366_ALLOW_ATA66_4 &&
461 speed = min(speed, (u8)XFER_UDMA_3); 560 !check_in_drive_list(drive, bad_ata66_4))
462 if ((check_in_drive_lists(drive, bad_ata66_3)) || 561 goto check_bad_ata33;
463 (!(HPT366_ALLOW_ATA66_3))) 562
464 speed = min(speed, (u8)XFER_UDMA_2); 563 speed = min_t(u8, speed, XFER_UDMA_3);
465 break; 564 if (HPT366_ALLOW_ATA66_3 &&
565 !check_in_drive_list(drive, bad_ata66_3))
566 goto check_bad_ata33;
567 /* fall thru */
466 case 0x01: 568 case 0x01:
467 speed = min(speed, (u8)XFER_UDMA_2); 569 speed = min_t(u8, speed, XFER_UDMA_2);
468 /* 570
469 * CHECK ME, Does this need to be set to 5 ?? 571 check_bad_ata33:
470 */ 572 if (chip_type >= HPT370A)
471 if (info->revision >= 3)
472 break; 573 break;
473 if (check_in_drive_lists(drive, bad_ata33)) 574 if (!check_in_drive_list(drive, bad_ata33))
474 speed = min(speed, (u8)XFER_MW_DMA_2); 575 break;
475 break; 576 /* fall thru */
476 case 0x00: 577 case 0x00:
477 default: 578 default:
478 speed = min(speed, (u8)XFER_MW_DMA_2); 579 speed = min_t(u8, speed, XFER_MW_DMA_2);
479 break; 580 break;
480 } 581 }
481 return speed; 582 return speed;
482} 583}
483 584
484static int check_in_drive_lists (ide_drive_t *drive, const char **list) 585static u32 get_speed_setting(u8 speed, struct hpt_info *info)
485{
486 struct hd_driveid *id = drive->id;
487
488 if (quirk_drives == list) {
489 while (*list)
490 if (strstr(id->model, *list++))
491 return 1;
492 } else {
493 while (*list)
494 if (!strcmp(*list++,id->model))
495 return 1;
496 }
497 return 0;
498}
499
500static u32 pci_bus_clock_list(u8 speed, u32 *chipset_table)
501{ 586{
502 int i; 587 int i;
503 588
@@ -510,228 +595,161 @@ static u32 pci_bus_clock_list(u8 speed, u32 *chipset_table)
510 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++) 595 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
511 if (xfer_speeds[i] == speed) 596 if (xfer_speeds[i] == speed)
512 break; 597 break;
513 return chipset_table[i]; 598 /*
599 * NOTE: info->settings only points to the pointer
600 * to the list of the actual register values
601 */
602 return (*info->settings)[i];
514} 603}
515 604
516static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed) 605static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
517{ 606{
518 ide_hwif_t *hwif = drive->hwif; 607 ide_hwif_t *hwif = HWIF(drive);
519 struct pci_dev *dev = hwif->pci_dev; 608 struct pci_dev *dev = hwif->pci_dev;
520 struct hpt_info *info = ide_get_hwifdata(hwif); 609 struct hpt_info *info = pci_get_drvdata(dev);
521 u8 speed = hpt3xx_ratefilter(drive, xferspeed); 610 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
522 u8 regtime = (drive->select.b.unit & 0x01) ? 0x44 : 0x40; 611 u8 itr_addr = drive->dn ? 0x44 : 0x40;
523 u8 regfast = (hwif->channel) ? 0x55 : 0x51; 612 u32 itr_mask = speed < XFER_MW_DMA_0 ? 0x30070000 :
524 u8 drive_fast = 0; 613 (speed < XFER_UDMA_0 ? 0xc0070000 : 0xc03800ff);
525 u32 reg1 = 0, reg2 = 0; 614 u32 new_itr = get_speed_setting(speed, info);
526 615 u32 old_itr = 0;
527 /*
528 * Disable the "fast interrupt" prediction.
529 */
530 pci_read_config_byte(dev, regfast, &drive_fast);
531 if (drive_fast & 0x80)
532 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
533
534 reg2 = pci_bus_clock_list(speed, info->speed);
535 616
536 /* 617 /*
537 * Disable on-chip PIO FIFO/buffer 618 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
538 * (to avoid problems handling I/O errors later) 619 * to avoid problems handling I/O errors later
539 */ 620 */
540 pci_read_config_dword(dev, regtime, &reg1); 621 pci_read_config_dword(dev, itr_addr, &old_itr);
541 if (speed >= XFER_MW_DMA_0) { 622 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
542 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000); 623 new_itr &= ~0xc0000000;
543 } else {
544 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
545 }
546 reg2 &= ~0x80000000;
547 624
548 pci_write_config_dword(dev, regtime, reg2); 625 pci_write_config_dword(dev, itr_addr, new_itr);
549 626
550 return ide_config_drive_speed(drive, speed); 627 return ide_config_drive_speed(drive, speed);
551} 628}
552 629
553static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed) 630static int hpt37x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
554{ 631{
555 ide_hwif_t *hwif = drive->hwif; 632 ide_hwif_t *hwif = HWIF(drive);
556 struct pci_dev *dev = hwif->pci_dev; 633 struct pci_dev *dev = hwif->pci_dev;
557 struct hpt_info *info = ide_get_hwifdata(hwif); 634 struct hpt_info *info = pci_get_drvdata(dev);
558 u8 speed = hpt3xx_ratefilter(drive, xferspeed); 635 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
559 u8 regfast = (drive->hwif->channel) ? 0x55 : 0x51; 636 u8 itr_addr = 0x40 + (drive->dn * 4);
560 u8 drive_pci = 0x40 + (drive->dn * 4); 637 u32 itr_mask = speed < XFER_MW_DMA_0 ? 0x303c0000 :
561 u8 new_fast = 0, drive_fast = 0; 638 (speed < XFER_UDMA_0 ? 0xc03c0000 : 0xc1c001ff);
562 u32 list_conf = 0, drive_conf = 0; 639 u32 new_itr = get_speed_setting(speed, info);
563 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000; 640 u32 old_itr = 0;
564 641
565 /* 642 pci_read_config_dword(dev, itr_addr, &old_itr);
566 * Disable the "fast interrupt" prediction. 643 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
567 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
568 */
569 pci_read_config_byte(dev, regfast, &drive_fast);
570 new_fast = drive_fast;
571 if (new_fast & 0x02)
572 new_fast &= ~0x02;
573
574#ifdef HPT_DELAY_INTERRUPT
575 if (new_fast & 0x01)
576 new_fast &= ~0x01;
577#else
578 if ((new_fast & 0x01) == 0)
579 new_fast |= 0x01;
580#endif
581 if (new_fast != drive_fast)
582 pci_write_config_byte(dev, regfast, new_fast);
583
584 list_conf = pci_bus_clock_list(speed, info->speed);
585
586 pci_read_config_dword(dev, drive_pci, &drive_conf);
587 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
588 644
589 if (speed < XFER_MW_DMA_0) 645 if (speed < XFER_MW_DMA_0)
590 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */ 646 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
591 pci_write_config_dword(dev, drive_pci, list_conf); 647 pci_write_config_dword(dev, itr_addr, new_itr);
592 648
593 return ide_config_drive_speed(drive, speed); 649 return ide_config_drive_speed(drive, speed);
594} 650}
595 651
596static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed) 652static int hpt3xx_tune_chipset(ide_drive_t *drive, u8 speed)
597{ 653{
598 ide_hwif_t *hwif = drive->hwif; 654 ide_hwif_t *hwif = HWIF(drive);
599 struct pci_dev *dev = hwif->pci_dev; 655 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
600 struct hpt_info *info = ide_get_hwifdata(hwif);
601 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
602 u8 regfast = (drive->hwif->channel) ? 0x55 : 0x51;
603 u8 drive_fast = 0, drive_pci = 0x40 + (drive->dn * 4);
604 u32 list_conf = 0, drive_conf = 0;
605 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
606
607 /*
608 * Disable the "fast interrupt" prediction.
609 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
610 */
611 pci_read_config_byte(dev, regfast, &drive_fast);
612 drive_fast &= ~0x07;
613 pci_write_config_byte(dev, regfast, drive_fast);
614
615 list_conf = pci_bus_clock_list(speed, info->speed);
616 pci_read_config_dword(dev, drive_pci, &drive_conf);
617 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
618 if (speed < XFER_MW_DMA_0)
619 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
620 pci_write_config_dword(dev, drive_pci, list_conf);
621
622 return ide_config_drive_speed(drive, speed);
623}
624 656
625static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed) 657 if (info->chip_type >= HPT370)
626{ 658 return hpt37x_tune_chipset(drive, speed);
627 ide_hwif_t *hwif = drive->hwif;
628 struct hpt_info *info = ide_get_hwifdata(hwif);
629
630 if (info->revision >= 8)
631 return hpt372_tune_chipset(drive, speed); /* not a typo */
632 else if (info->revision >= 5)
633 return hpt372_tune_chipset(drive, speed);
634 else if (info->revision >= 3)
635 return hpt370_tune_chipset(drive, speed);
636 else /* hpt368: hpt_minimum_revision(dev, 2) */ 659 else /* hpt368: hpt_minimum_revision(dev, 2) */
637 return hpt36x_tune_chipset(drive, speed); 660 return hpt36x_tune_chipset(drive, speed);
638} 661}
639 662
640static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio) 663static void hpt3xx_tune_drive(ide_drive_t *drive, u8 pio)
641{ 664{
642 pio = ide_get_best_pio_mode(drive, 255, pio, NULL); 665 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
643 (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio)); 666 (void) hpt3xx_tune_chipset (drive, XFER_PIO_0 + pio);
644} 667}
645 668
646/* 669/*
647 * This allows the configuration of ide_pci chipset registers 670 * This allows the configuration of ide_pci chipset registers
648 * for cards that learn about the drive's UDMA, DMA, PIO capabilities 671 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
649 * after the drive is reported by the OS. Initially for designed for 672 * after the drive is reported by the OS. Initially designed for
650 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc. 673 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
651 * 674 *
652 * check_in_drive_lists(drive, bad_ata66_4)
653 * check_in_drive_lists(drive, bad_ata66_3)
654 * check_in_drive_lists(drive, bad_ata33)
655 *
656 */ 675 */
657static int config_chipset_for_dma (ide_drive_t *drive) 676static int config_chipset_for_dma(ide_drive_t *drive)
658{ 677{
659 u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive)); 678 u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
660 ide_hwif_t *hwif = drive->hwif;
661 struct hpt_info *info = ide_get_hwifdata(hwif);
662 679
663 if (!speed) 680 if (!speed)
664 return 0; 681 return 0;
665 682
666 /* If we don't have any timings we can't do a lot */
667 if (info->speed == NULL)
668 return 0;
669
670 (void) hpt3xx_tune_chipset(drive, speed); 683 (void) hpt3xx_tune_chipset(drive, speed);
671 return ide_dma_enable(drive); 684 return ide_dma_enable(drive);
672} 685}
673 686
674static int hpt3xx_quirkproc (ide_drive_t *drive) 687static int hpt3xx_quirkproc(ide_drive_t *drive)
675{ 688{
676 return ((int) check_in_drive_lists(drive, quirk_drives)); 689 struct hd_driveid *id = drive->id;
690 const char **list = quirk_drives;
691
692 while (*list)
693 if (strstr(id->model, *list++))
694 return 1;
695 return 0;
677} 696}
678 697
679static void hpt3xx_intrproc (ide_drive_t *drive) 698static void hpt3xx_intrproc(ide_drive_t *drive)
680{ 699{
681 ide_hwif_t *hwif = drive->hwif; 700 ide_hwif_t *hwif = HWIF(drive);
682 701
683 if (drive->quirk_list) 702 if (drive->quirk_list)
684 return; 703 return;
685 /* drives in the quirk_list may not like intr setups/cleanups */ 704 /* drives in the quirk_list may not like intr setups/cleanups */
686 hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG); 705 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
687} 706}
688 707
689static void hpt3xx_maskproc (ide_drive_t *drive, int mask) 708static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
690{ 709{
691 ide_hwif_t *hwif = drive->hwif; 710 ide_hwif_t *hwif = HWIF(drive);
692 struct hpt_info *info = ide_get_hwifdata(hwif); 711 struct pci_dev *dev = hwif->pci_dev;
693 struct pci_dev *dev = hwif->pci_dev; 712 struct hpt_info *info = pci_get_drvdata(dev);
694 713
695 if (drive->quirk_list) { 714 if (drive->quirk_list) {
696 if (info->revision >= 3) { 715 if (info->chip_type >= HPT370) {
697 u8 reg5a = 0; 716 u8 scr1 = 0;
698 pci_read_config_byte(dev, 0x5a, &reg5a); 717
699 if (((reg5a & 0x10) >> 4) != mask) 718 pci_read_config_byte(dev, 0x5a, &scr1);
700 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10)); 719 if (((scr1 & 0x10) >> 4) != mask) {
720 if (mask)
721 scr1 |= 0x10;
722 else
723 scr1 &= ~0x10;
724 pci_write_config_byte(dev, 0x5a, scr1);
725 }
701 } else { 726 } else {
702 if (mask) { 727 if (mask)
703 disable_irq(hwif->irq); 728 disable_irq(hwif->irq);
704 } else { 729 else
705 enable_irq(hwif->irq); 730 enable_irq (hwif->irq);
706 }
707 } 731 }
708 } else { 732 } else
709 if (IDE_CONTROL_REG) 733 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
710 hwif->OUTB(mask ? (drive->ctl | 2) : 734 IDE_CONTROL_REG);
711 (drive->ctl & ~2),
712 IDE_CONTROL_REG);
713 }
714} 735}
715 736
716static int hpt366_config_drive_xfer_rate (ide_drive_t *drive) 737static int hpt366_config_drive_xfer_rate(ide_drive_t *drive)
717{ 738{
718 ide_hwif_t *hwif = drive->hwif; 739 ide_hwif_t *hwif = HWIF(drive);
719 struct hd_driveid *id = drive->id; 740 struct hd_driveid *id = drive->id;
720 741
721 drive->init_speed = 0; 742 drive->init_speed = 0;
722 743
723 if ((id->capability & 1) && drive->autodma) { 744 if ((id->capability & 1) && drive->autodma) {
724 745 if (ide_use_dma(drive) && config_chipset_for_dma(drive))
725 if (ide_use_dma(drive)) { 746 return hwif->ide_dma_on(drive);
726 if (config_chipset_for_dma(drive))
727 return hwif->ide_dma_on(drive);
728 }
729 747
730 goto fast_ata_pio; 748 goto fast_ata_pio;
731 749
732 } else if ((id->capability & 8) || (id->field_valid & 2)) { 750 } else if ((id->capability & 8) || (id->field_valid & 2)) {
733fast_ata_pio: 751fast_ata_pio:
734 hpt3xx_tune_drive(drive, 5); 752 hpt3xx_tune_drive(drive, 255);
735 return hwif->ide_dma_off_quietly(drive); 753 return hwif->ide_dma_off_quietly(drive);
736 } 754 }
737 /* IORDY not supported */ 755 /* IORDY not supported */
@@ -739,31 +757,48 @@ fast_ata_pio:
739} 757}
740 758
741/* 759/*
742 * This is specific to the HPT366 UDMA bios chipset 760 * This is specific to the HPT366 UDMA chipset
743 * by HighPoint|Triones Technologies, Inc. 761 * by HighPoint|Triones Technologies, Inc.
744 */ 762 */
745static int hpt366_ide_dma_lostirq (ide_drive_t *drive) 763static int hpt366_ide_dma_lostirq(ide_drive_t *drive)
746{ 764{
747 struct pci_dev *dev = HWIF(drive)->pci_dev; 765 struct pci_dev *dev = HWIF(drive)->pci_dev;
748 u8 reg50h = 0, reg52h = 0, reg5ah = 0; 766 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
749 767
750 pci_read_config_byte(dev, 0x50, &reg50h); 768 pci_read_config_byte(dev, 0x50, &mcr1);
751 pci_read_config_byte(dev, 0x52, &reg52h); 769 pci_read_config_byte(dev, 0x52, &mcr3);
752 pci_read_config_byte(dev, 0x5a, &reg5ah); 770 pci_read_config_byte(dev, 0x5a, &scr1);
753 printk("%s: (%s) reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n", 771 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
754 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah); 772 drive->name, __FUNCTION__, mcr1, mcr3, scr1);
755 if (reg5ah & 0x10) 773 if (scr1 & 0x10)
756 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10); 774 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
757 return __ide_dma_lostirq(drive); 775 return __ide_dma_lostirq(drive);
758} 776}
759 777
760static void hpt370_clear_engine (ide_drive_t *drive) 778static void hpt370_clear_engine(ide_drive_t *drive)
761{ 779{
762 u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50; 780 ide_hwif_t *hwif = HWIF(drive);
763 pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37); 781
782 pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
764 udelay(10); 783 udelay(10);
765} 784}
766 785
786static void hpt370_irq_timeout(ide_drive_t *drive)
787{
788 ide_hwif_t *hwif = HWIF(drive);
789 u16 bfifo = 0;
790 u8 dma_cmd;
791
792 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
793 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
794
795 /* get DMA command mode */
796 dma_cmd = hwif->INB(hwif->dma_command);
797 /* stop DMA */
798 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
799 hpt370_clear_engine(drive);
800}
801
767static void hpt370_ide_dma_start(ide_drive_t *drive) 802static void hpt370_ide_dma_start(ide_drive_t *drive)
768{ 803{
769#ifdef HPT_RESET_STATE_ENGINE 804#ifdef HPT_RESET_STATE_ENGINE
@@ -772,64 +807,35 @@ static void hpt370_ide_dma_start(ide_drive_t *drive)
772 ide_dma_start(drive); 807 ide_dma_start(drive);
773} 808}
774 809
775static int hpt370_ide_dma_end (ide_drive_t *drive) 810static int hpt370_ide_dma_end(ide_drive_t *drive)
776{ 811{
777 ide_hwif_t *hwif = HWIF(drive); 812 ide_hwif_t *hwif = HWIF(drive);
778 u8 dma_stat = hwif->INB(hwif->dma_status); 813 u8 dma_stat = hwif->INB(hwif->dma_status);
779 814
780 if (dma_stat & 0x01) { 815 if (dma_stat & 0x01) {
781 /* wait a little */ 816 /* wait a little */
782 udelay(20); 817 udelay(20);
783 dma_stat = hwif->INB(hwif->dma_status); 818 dma_stat = hwif->INB(hwif->dma_status);
819 if (dma_stat & 0x01)
820 hpt370_irq_timeout(drive);
784 } 821 }
785 if ((dma_stat & 0x01) != 0)
786 /* fallthrough */
787 (void) HWIF(drive)->ide_dma_timeout(drive);
788
789 return __ide_dma_end(drive); 822 return __ide_dma_end(drive);
790} 823}
791 824
792static void hpt370_lostirq_timeout (ide_drive_t *drive) 825static int hpt370_ide_dma_timeout(ide_drive_t *drive)
793{ 826{
794 ide_hwif_t *hwif = HWIF(drive); 827 hpt370_irq_timeout(drive);
795 u8 bfifo = 0, reginfo = hwif->channel ? 0x56 : 0x52;
796 u8 dma_stat = 0, dma_cmd = 0;
797
798 pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
799 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo);
800 hpt370_clear_engine(drive);
801 /* get dma command mode */
802 dma_cmd = hwif->INB(hwif->dma_command);
803 /* stop dma */
804 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
805 dma_stat = hwif->INB(hwif->dma_status);
806 /* clear errors */
807 hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
808}
809
810static int hpt370_ide_dma_timeout (ide_drive_t *drive)
811{
812 hpt370_lostirq_timeout(drive);
813 hpt370_clear_engine(drive);
814 return __ide_dma_timeout(drive); 828 return __ide_dma_timeout(drive);
815} 829}
816 830
817static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
818{
819 hpt370_lostirq_timeout(drive);
820 hpt370_clear_engine(drive);
821 return __ide_dma_lostirq(drive);
822}
823
824/* returns 1 if DMA IRQ issued, 0 otherwise */ 831/* returns 1 if DMA IRQ issued, 0 otherwise */
825static int hpt374_ide_dma_test_irq(ide_drive_t *drive) 832static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
826{ 833{
827 ide_hwif_t *hwif = HWIF(drive); 834 ide_hwif_t *hwif = HWIF(drive);
828 u16 bfifo = 0; 835 u16 bfifo = 0;
829 u8 reginfo = hwif->channel ? 0x56 : 0x52; 836 u8 dma_stat;
830 u8 dma_stat;
831 837
832 pci_read_config_word(hwif->pci_dev, reginfo, &bfifo); 838 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
833 if (bfifo & 0x1FF) { 839 if (bfifo & 0x1FF) {
834// printk("%s: %d bytes in FIFO\n", drive->name, bfifo); 840// printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
835 return 0; 841 return 0;
@@ -837,7 +843,7 @@ static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
837 843
838 dma_stat = hwif->INB(hwif->dma_status); 844 dma_stat = hwif->INB(hwif->dma_status);
839 /* return 1 if INTR asserted */ 845 /* return 1 if INTR asserted */
840 if ((dma_stat & 4) == 4) 846 if (dma_stat & 4)
841 return 1; 847 return 1;
842 848
843 if (!drive->waiting_for_dma) 849 if (!drive->waiting_for_dma)
@@ -846,17 +852,17 @@ static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
846 return 0; 852 return 0;
847} 853}
848 854
849static int hpt374_ide_dma_end (ide_drive_t *drive) 855static int hpt374_ide_dma_end(ide_drive_t *drive)
850{ 856{
851 struct pci_dev *dev = HWIF(drive)->pci_dev;
852 ide_hwif_t *hwif = HWIF(drive); 857 ide_hwif_t *hwif = HWIF(drive);
853 u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50; 858 struct pci_dev *dev = hwif->pci_dev;
854 u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01; 859 u8 mcr = 0, mcr_addr = hwif->select_data;
855 860 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
856 pci_read_config_byte(dev, 0x6a, &bwsr_stat); 861
857 pci_read_config_byte(dev, mscreg, &msc_stat); 862 pci_read_config_byte(dev, 0x6a, &bwsr);
858 if ((bwsr_stat & bwsr_mask) == bwsr_mask) 863 pci_read_config_byte(dev, mcr_addr, &mcr);
859 pci_write_config_byte(dev, mscreg, msc_stat|0x30); 864 if (bwsr & mask)
865 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
860 return __ide_dma_end(drive); 866 return __ide_dma_end(drive);
861} 867}
862 868
@@ -866,40 +872,37 @@ static int hpt374_ide_dma_end (ide_drive_t *drive)
866 * @mode: clocking mode (0x21 for write, 0x23 otherwise) 872 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
867 * 873 *
868 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess. 874 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
869 * NOTE: avoid touching the disabled primary channel on HPT371N -- it
870 * doesn't physically exist anyway...
871 */ 875 */
872 876
873static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode) 877static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
874{ 878{
875 u8 mcr1, scr2 = hwif->INB(hwif->dma_master + 0x7b); 879 u8 scr2 = hwif->INB(hwif->dma_master + 0x7b);
876 880
877 if ((scr2 & 0x7f) == mode) 881 if ((scr2 & 0x7f) == mode)
878 return; 882 return;
879 883
880 /* MISC. control register 1 has the channel enable bit... */
881 mcr1 = hwif->INB(hwif->dma_master + 0x70);
882
883 /* Tristate the bus */ 884 /* Tristate the bus */
884 if (mcr1 & 0x04) 885 hwif->OUTB(0x80, hwif->dma_master + 0x73);
885 hwif->OUTB(0x80, hwif->dma_master + 0x73);
886 hwif->OUTB(0x80, hwif->dma_master + 0x77); 886 hwif->OUTB(0x80, hwif->dma_master + 0x77);
887 887
888 /* Switch clock and reset channels */ 888 /* Switch clock and reset channels */
889 hwif->OUTB(mode, hwif->dma_master + 0x7b); 889 hwif->OUTB(mode, hwif->dma_master + 0x7b);
890 hwif->OUTB(0xc0, hwif->dma_master + 0x79); 890 hwif->OUTB(0xc0, hwif->dma_master + 0x79);
891 891
892 /* Reset state machines */ 892 /*
893 if (mcr1 & 0x04) 893 * Reset the state machines.
894 hwif->OUTB(0x37, hwif->dma_master + 0x70); 894 * NOTE: avoid accidentally enabling the disabled channels.
895 hwif->OUTB(0x37, hwif->dma_master + 0x74); 895 */
896 hwif->OUTB(hwif->INB(hwif->dma_master + 0x70) | 0x32,
897 hwif->dma_master + 0x70);
898 hwif->OUTB(hwif->INB(hwif->dma_master + 0x74) | 0x32,
899 hwif->dma_master + 0x74);
896 900
897 /* Complete reset */ 901 /* Complete reset */
898 hwif->OUTB(0x00, hwif->dma_master + 0x79); 902 hwif->OUTB(0x00, hwif->dma_master + 0x79);
899 903
900 /* Reconnect channels to bus */ 904 /* Reconnect channels to bus */
901 if (mcr1 & 0x04) 905 hwif->OUTB(0x00, hwif->dma_master + 0x73);
902 hwif->OUTB(0x00, hwif->dma_master + 0x73);
903 hwif->OUTB(0x00, hwif->dma_master + 0x77); 906 hwif->OUTB(0x00, hwif->dma_master + 0x77);
904} 907}
905 908
@@ -914,14 +917,12 @@ static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
914 917
915static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq) 918static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
916{ 919{
917 ide_hwif_t *hwif = HWIF(drive); 920 hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
918 u8 wantclock = rq_data_dir(rq) ? 0x23 : 0x21;
919
920 hpt3xxn_set_clock(hwif, wantclock);
921} 921}
922 922
923/* 923/*
924 * Set/get power state for a drive. 924 * Set/get power state for a drive.
925 * NOTE: affects both drives on each channel.
925 * 926 *
926 * When we turn the power back on, we need to re-initialize things. 927 * When we turn the power back on, we need to re-initialize things.
927 */ 928 */
@@ -929,26 +930,18 @@ static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
929 930
930static int hpt3xx_busproc(ide_drive_t *drive, int state) 931static int hpt3xx_busproc(ide_drive_t *drive, int state)
931{ 932{
932 ide_hwif_t *hwif = drive->hwif; 933 ide_hwif_t *hwif = HWIF(drive);
933 struct pci_dev *dev = hwif->pci_dev; 934 struct pci_dev *dev = hwif->pci_dev;
934 u8 tristate, resetmask, bus_reg = 0; 935 u8 mcr_addr = hwif->select_data + 2;
935 u16 tri_reg = 0; 936 u8 resetmask = hwif->channel ? 0x80 : 0x40;
937 u8 bsr2 = 0;
938 u16 mcr = 0;
936 939
937 hwif->bus_state = state; 940 hwif->bus_state = state;
938 941
939 if (hwif->channel) {
940 /* secondary channel */
941 tristate = 0x56;
942 resetmask = 0x80;
943 } else {
944 /* primary channel */
945 tristate = 0x52;
946 resetmask = 0x40;
947 }
948
949 /* Grab the status. */ 942 /* Grab the status. */
950 pci_read_config_word(dev, tristate, &tri_reg); 943 pci_read_config_word(dev, mcr_addr, &mcr);
951 pci_read_config_byte(dev, 0x59, &bus_reg); 944 pci_read_config_byte(dev, 0x59, &bsr2);
952 945
953 /* 946 /*
954 * Set the state. We don't set it if we don't need to do so. 947 * Set the state. We don't set it if we don't need to do so.
@@ -956,22 +949,22 @@ static int hpt3xx_busproc(ide_drive_t *drive, int state)
956 */ 949 */
957 switch (state) { 950 switch (state) {
958 case BUSSTATE_ON: 951 case BUSSTATE_ON:
959 if (!(bus_reg & resetmask)) 952 if (!(bsr2 & resetmask))
960 return 0; 953 return 0;
961 hwif->drives[0].failures = hwif->drives[1].failures = 0; 954 hwif->drives[0].failures = hwif->drives[1].failures = 0;
962 955
963 pci_write_config_byte(dev, 0x59, bus_reg & ~resetmask); 956 pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
964 pci_write_config_word(dev, tristate, tri_reg & ~TRISTATE_BIT); 957 pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
965 return 0; 958 return 0;
966 case BUSSTATE_OFF: 959 case BUSSTATE_OFF:
967 if ((bus_reg & resetmask) && !(tri_reg & TRISTATE_BIT)) 960 if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
968 return 0; 961 return 0;
969 tri_reg &= ~TRISTATE_BIT; 962 mcr &= ~TRISTATE_BIT;
970 break; 963 break;
971 case BUSSTATE_TRISTATE: 964 case BUSSTATE_TRISTATE:
972 if ((bus_reg & resetmask) && (tri_reg & TRISTATE_BIT)) 965 if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT))
973 return 0; 966 return 0;
974 tri_reg |= TRISTATE_BIT; 967 mcr |= TRISTATE_BIT;
975 break; 968 break;
976 default: 969 default:
977 return -EINVAL; 970 return -EINVAL;
@@ -980,268 +973,320 @@ static int hpt3xx_busproc(ide_drive_t *drive, int state)
980 hwif->drives[0].failures = hwif->drives[0].max_failures + 1; 973 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
981 hwif->drives[1].failures = hwif->drives[1].max_failures + 1; 974 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
982 975
983 pci_write_config_word(dev, tristate, tri_reg); 976 pci_write_config_word(dev, mcr_addr, mcr);
984 pci_write_config_byte(dev, 0x59, bus_reg | resetmask); 977 pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
985 return 0; 978 return 0;
986} 979}
987 980
988static void __devinit hpt366_clocking(ide_hwif_t *hwif) 981/**
982 * hpt37x_calibrate_dpll - calibrate the DPLL
983 * @dev: PCI device
984 *
985 * Perform a calibration cycle on the DPLL.
986 * Returns 1 if this succeeds
987 */
988static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
989{ 989{
990 u32 reg1 = 0; 990 u32 dpll = (f_high << 16) | f_low | 0x100;
991 struct hpt_info *info = ide_get_hwifdata(hwif); 991 u8 scr2;
992 int i;
992 993
993 pci_read_config_dword(hwif->pci_dev, 0x40, &reg1); 994 pci_write_config_dword(dev, 0x5c, dpll);
994 995
995 /* detect bus speed by looking at control reg timing: */ 996 /* Wait for oscillator ready */
996 switch((reg1 >> 8) & 7) { 997 for(i = 0; i < 0x5000; ++i) {
997 case 5: 998 udelay(50);
998 info->speed = forty_base_hpt36x; 999 pci_read_config_byte(dev, 0x5b, &scr2);
999 break; 1000 if (scr2 & 0x80)
1000 case 9:
1001 info->speed = twenty_five_base_hpt36x;
1002 break;
1003 case 7:
1004 default:
1005 info->speed = thirty_three_base_hpt36x;
1006 break; 1001 break;
1007 } 1002 }
1003 /* See if it stays ready (we'll just bail out if it's not yet) */
1004 for(i = 0; i < 0x1000; ++i) {
1005 pci_read_config_byte(dev, 0x5b, &scr2);
1006 /* DPLL destabilized? */
1007 if(!(scr2 & 0x80))
1008 return 0;
1009 }
1010 /* Turn off tuning, we have the DPLL set */
1011 pci_read_config_dword (dev, 0x5c, &dpll);
1012 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
1013 return 1;
1008} 1014}
1009 1015
1010static void __devinit hpt37x_clocking(ide_hwif_t *hwif) 1016static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1011{ 1017{
1012 struct hpt_info *info = ide_get_hwifdata(hwif); 1018 struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
1013 struct pci_dev *dev = hwif->pci_dev; 1019 unsigned long io_base = pci_resource_start(dev, 4);
1014 int adjust, i; 1020 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
1015 u16 freq = 0; 1021 enum ata_clock clock;
1016 u32 pll, temp = 0; 1022
1017 u8 reg5bh = 0, mcr1 = 0; 1023 if (info == NULL) {
1018 1024 printk(KERN_ERR "%s: out of memory!\n", name);
1025 return -ENOMEM;
1026 }
1027
1019 /* 1028 /*
1020 * default to pci clock. make sure MA15/16 are set to output 1029 * Copy everything from a static "template" structure
1021 * to prevent drives having problems with 40-pin cables. Needed 1030 * to just allocated per-chip hpt_info structure.
1022 * for some drives such as IBM-DTLA which will not enter ready
1023 * state on reset when PDIAG is a input.
1024 *
1025 * ToDo: should we set 0x21 when using PLL mode ?
1026 */ 1031 */
1027 pci_write_config_byte(dev, 0x5b, 0x23); 1032 *info = *(struct hpt_info *)pci_get_drvdata(dev);
1028 1033
1029 /* 1034 /*
1030 * We'll have to read f_CNT value in order to determine 1035 * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1031 * the PCI clock frequency according to the following ratio: 1036 * We don't seem to be using it.
1032 *
1033 * f_CNT = Fpci * 192 / Fdpll
1034 *
1035 * First try reading the register in which the HighPoint BIOS
1036 * saves f_CNT value before reprogramming the DPLL from its
1037 * default setting (which differs for the various chips).
1038 * NOTE: This register is only accessible via I/O space.
1039 *
1040 * In case the signature check fails, we'll have to resort to
1041 * reading the f_CNT register itself in hopes that nobody has
1042 * touched the DPLL yet...
1043 */ 1037 */
1044 temp = inl(pci_resource_start(dev, 4) + 0x90); 1038 if (dev->resource[PCI_ROM_RESOURCE].start)
1045 if ((temp & 0xFFFFF000) != 0xABCDE000) { 1039 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1046 printk(KERN_WARNING "HPT37X: no clock data saved by BIOS\n"); 1040 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1047 1041
1048 /* Calculate the average value of f_CNT */ 1042 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1049 for (temp = i = 0; i < 128; i++) { 1043 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1050 pci_read_config_word(dev, 0x78, &freq); 1044 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1051 temp += freq & 0x1ff; 1045 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1052 mdelay(1);
1053 }
1054 freq = temp / 128;
1055 } else
1056 freq = temp & 0x1ff;
1057 1046
1058 /* 1047 /*
1059 * HPT3xxN chips use different PCI clock information. 1048 * First, try to estimate the PCI clock frequency...
1060 * Currently we always set up the PLL for them.
1061 */ 1049 */
1050 if (info->chip_type >= HPT370) {
1051 u8 scr1 = 0;
1052 u16 f_cnt = 0;
1053 u32 temp = 0;
1062 1054
1063 if (info->flags & IS_3xxN) { 1055 /* Interrupt force enable. */
1064 if(freq < 0x55) 1056 pci_read_config_byte(dev, 0x5a, &scr1);
1065 pll = F_LOW_PCI_33; 1057 if (scr1 & 0x10)
1066 else if(freq < 0x70) 1058 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
1067 pll = F_LOW_PCI_40;
1068 else if(freq < 0x7F)
1069 pll = F_LOW_PCI_50;
1070 else
1071 pll = F_LOW_PCI_66;
1072 1059
1073 printk(KERN_INFO "HPT3xxN detected, FREQ: %d, PLL: %d\n", freq, pll); 1060 /*
1074 } 1061 * HighPoint does this for HPT372A.
1075 else 1062 * NOTE: This register is only writeable via I/O space.
1076 { 1063 */
1077 if(freq < 0x9C) 1064 if (info->chip_type == HPT372A)
1078 pll = F_LOW_PCI_33; 1065 outb(0x0e, io_base + 0x9c);
1079 else if(freq < 0xb0) 1066
1080 pll = F_LOW_PCI_40; 1067 /*
1081 else if(freq <0xc8) 1068 * Default to PCI clock. Make sure MA15/16 are set to output
1082 pll = F_LOW_PCI_50; 1069 * to prevent drives having problems with 40-pin cables.
1070 */
1071 pci_write_config_byte(dev, 0x5b, 0x23);
1072
1073 /*
1074 * We'll have to read f_CNT value in order to determine
1075 * the PCI clock frequency according to the following ratio:
1076 *
1077 * f_CNT = Fpci * 192 / Fdpll
1078 *
1079 * First try reading the register in which the HighPoint BIOS
1080 * saves f_CNT value before reprogramming the DPLL from its
1081 * default setting (which differs for the various chips).
1082 * NOTE: This register is only accessible via I/O space.
1083 *
1084 * In case the signature check fails, we'll have to resort to
1085 * reading the f_CNT register itself in hopes that nobody has
1086 * touched the DPLL yet...
1087 */
1088 temp = inl(io_base + 0x90);
1089 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1090 int i;
1091
1092 printk(KERN_WARNING "%s: no clock data saved by BIOS\n",
1093 name);
1094
1095 /* Calculate the average value of f_CNT. */
1096 for (temp = i = 0; i < 128; i++) {
1097 pci_read_config_word(dev, 0x78, &f_cnt);
1098 temp += f_cnt & 0x1ff;
1099 mdelay(1);
1100 }
1101 f_cnt = temp / 128;
1102 } else
1103 f_cnt = temp & 0x1ff;
1104
1105 dpll_clk = info->dpll_clk;
1106 pci_clk = (f_cnt * dpll_clk) / 192;
1107
1108 /* Clamp PCI clock to bands. */
1109 if (pci_clk < 40)
1110 pci_clk = 33;
1111 else if(pci_clk < 45)
1112 pci_clk = 40;
1113 else if(pci_clk < 55)
1114 pci_clk = 50;
1083 else 1115 else
1084 pll = F_LOW_PCI_66; 1116 pci_clk = 66;
1085 1117
1086 if (pll == F_LOW_PCI_33) { 1118 printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, "
1087 info->speed = thirty_three_base_hpt37x; 1119 "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk);
1088 printk(KERN_DEBUG "HPT37X: using 33MHz PCI clock\n"); 1120 } else {
1089 } else if (pll == F_LOW_PCI_40) { 1121 u32 itr1 = 0;
1090 /* Unsupported */ 1122
1091 } else if (pll == F_LOW_PCI_50) { 1123 pci_read_config_dword(dev, 0x40, &itr1);
1092 info->speed = fifty_base_hpt37x; 1124
1093 printk(KERN_DEBUG "HPT37X: using 50MHz PCI clock\n"); 1125 /* Detect PCI clock by looking at cmd_high_time. */
1094 } else { 1126 switch((itr1 >> 8) & 0x07) {
1095 info->speed = sixty_six_base_hpt37x; 1127 case 0x09:
1096 printk(KERN_DEBUG "HPT37X: using 66MHz PCI clock\n"); 1128 pci_clk = 40;
1129 break;
1130 case 0x05:
1131 pci_clk = 25;
1132 break;
1133 case 0x07:
1134 default:
1135 pci_clk = 33;
1136 break;
1097 } 1137 }
1098 } 1138 }
1099 1139
1100 if (pll == F_LOW_PCI_66) 1140 /* Let's assume we'll use PCI clock for the ATA clock... */
1101 info->flags |= PCI_66MHZ; 1141 switch (pci_clk) {
1142 case 25:
1143 clock = ATA_CLOCK_25MHZ;
1144 break;
1145 case 33:
1146 default:
1147 clock = ATA_CLOCK_33MHZ;
1148 break;
1149 case 40:
1150 clock = ATA_CLOCK_40MHZ;
1151 break;
1152 case 50:
1153 clock = ATA_CLOCK_50MHZ;
1154 break;
1155 case 66:
1156 clock = ATA_CLOCK_66MHZ;
1157 break;
1158 }
1102 1159
1103 /* 1160 /*
1104 * only try the pll if we don't have a table for the clock 1161 * Only try the DPLL if we don't have a table for the PCI clock that
1105 * speed that we're running at. NOTE: the internal PLL will 1162 * we are running at for HPT370/A, always use it for anything newer...
1106 * result in slow reads when using a 33MHz PCI clock. we also
1107 * don't like to use the PLL because it will cause glitches
1108 * on PRST/SRST when the HPT state engine gets reset.
1109 * 1163 *
1110 * ToDo: Use 66MHz PLL when ATA133 devices are present on a 1164 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1111 * 372 device so we can get ATA133 support 1165 * We also don't like using the DPLL because this causes glitches
1166 * on PRST-/SRST- when the state engine gets reset...
1112 */ 1167 */
1113 if (info->speed) 1168 if (info->chip_type >= HPT374 || info->settings[clock] == NULL) {
1114 goto init_hpt37X_done; 1169 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1170 int adjust;
1171
1172 /*
1173 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1174 * supported/enabled, use 50 MHz DPLL clock otherwise...
1175 */
1176 if (info->max_mode == 0x04) {
1177 dpll_clk = 66;
1178 clock = ATA_CLOCK_66MHZ;
1179 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1180 dpll_clk = 50;
1181 clock = ATA_CLOCK_50MHZ;
1182 }
1115 1183
1116 info->flags |= PLL_MODE; 1184 if (info->settings[clock] == NULL) {
1117 1185 printk(KERN_ERR "%s: unknown bus timing!\n", name);
1118 /* 1186 kfree(info);
1119 * Adjust the PLL based upon the PCI clock, enable it, and 1187 return -EIO;
1120 * wait for stabilization...
1121 */
1122 adjust = 0;
1123 freq = (pll < F_LOW_PCI_50) ? 2 : 4;
1124 while (adjust++ < 6) {
1125 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
1126 pll | 0x100);
1127
1128 /* wait for clock stabilization */
1129 for (i = 0; i < 0x50000; i++) {
1130 pci_read_config_byte(dev, 0x5b, &reg5bh);
1131 if (reg5bh & 0x80) {
1132 /* spin looking for the clock to destabilize */
1133 for (i = 0; i < 0x1000; ++i) {
1134 pci_read_config_byte(dev, 0x5b,
1135 &reg5bh);
1136 if ((reg5bh & 0x80) == 0)
1137 goto pll_recal;
1138 }
1139 pci_read_config_dword(dev, 0x5c, &pll);
1140 pci_write_config_dword(dev, 0x5c,
1141 pll & ~0x100);
1142 pci_write_config_byte(dev, 0x5b, 0x21);
1143
1144 info->speed = fifty_base_hpt37x;
1145 printk("HPT37X: using 50MHz internal PLL\n");
1146 goto init_hpt37X_done;
1147 }
1148 } 1188 }
1149pll_recal:
1150 if (adjust & 1)
1151 pll -= (adjust >> 1);
1152 else
1153 pll += (adjust >> 1);
1154 }
1155 1189
1156init_hpt37X_done: 1190 /* Select the DPLL clock. */
1157 if (!info->speed) 1191 pci_write_config_byte(dev, 0x5b, 0x21);
1158 printk(KERN_ERR "HPT37x%s: unknown bus timing [%d %d].\n",
1159 (info->flags & IS_3xxN) ? "N" : "", pll, freq);
1160 /*
1161 * Reset the state engines.
1162 * NOTE: avoid accidentally enabling the primary channel on HPT371N.
1163 */
1164 pci_read_config_byte(dev, 0x50, &mcr1);
1165 if (mcr1 & 0x04)
1166 pci_write_config_byte(dev, 0x50, 0x37);
1167 pci_write_config_byte(dev, 0x54, 0x37);
1168 udelay(100);
1169}
1170 1192
1171static int __devinit init_hpt37x(struct pci_dev *dev) 1193 /*
1172{ 1194 * Adjust the DPLL based upon PCI clock, enable it,
1173 u8 reg5ah; 1195 * and wait for stabilization...
1196 */
1197 f_low = (pci_clk * 48) / dpll_clk;
1174 1198
1175 pci_read_config_byte(dev, 0x5a, &reg5ah); 1199 for (adjust = 0; adjust < 8; adjust++) {
1176 /* interrupt force enable */ 1200 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1177 pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10)); 1201 break;
1178 return 0;
1179}
1180 1202
1181static int __devinit init_hpt366(struct pci_dev *dev) 1203 /*
1182{ 1204 * See if it'll settle at a fractionally different clock
1183 u32 reg1 = 0; 1205 */
1184 u8 drive_fast = 0; 1206 if (adjust & 1)
1207 f_low -= adjust >> 1;
1208 else
1209 f_low += adjust >> 1;
1210 }
1211 if (adjust == 8) {
1212 printk(KERN_ERR "%s: DPLL did not stabilize!\n", name);
1213 kfree(info);
1214 return -EIO;
1215 }
1185 1216
1186 /* 1217 printk("%s: using %d MHz DPLL clock\n", name, dpll_clk);
1187 * Disable the "fast interrupt" prediction. 1218 } else {
1188 */ 1219 /* Mark the fact that we're not using the DPLL. */
1189 pci_read_config_byte(dev, 0x51, &drive_fast); 1220 dpll_clk = 0;
1190 if (drive_fast & 0x80)
1191 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
1192 pci_read_config_dword(dev, 0x40, &reg1);
1193
1194 return 0;
1195}
1196 1221
1197static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name) 1222 printk("%s: using %d MHz PCI clock\n", name, pci_clk);
1198{ 1223 }
1199 int ret = 0;
1200 1224
1201 /* 1225 /*
1202 * FIXME: Not portable. Also, why do we enable the ROM in the first place? 1226 * Advance the table pointer to a slot which points to the list
1203 * We don't seem to be using it. 1227 * of the register values settings matching the clock being used.
1204 */ 1228 */
1205 if (dev->resource[PCI_ROM_RESOURCE].start) 1229 info->settings += clock;
1206 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1207 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1208 1230
1209 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); 1231 /* Store the clock frequencies. */
1210 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); 1232 info->dpll_clk = dpll_clk;
1211 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); 1233 info->pci_clk = pci_clk;
1212 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1213 1234
1214 if (hpt_revision(dev) >= 3) 1235 /* Point to this chip's own instance of the hpt_info structure. */
1215 ret = init_hpt37x(dev); 1236 pci_set_drvdata(dev, info);
1216 else
1217 ret = init_hpt366(dev);
1218 1237
1219 if (ret) 1238 if (info->chip_type >= HPT370) {
1220 return ret; 1239 u8 mcr1, mcr4;
1240
1241 /*
1242 * Reset the state engines.
1243 * NOTE: Avoid accidentally enabling the disabled channels.
1244 */
1245 pci_read_config_byte (dev, 0x50, &mcr1);
1246 pci_read_config_byte (dev, 0x54, &mcr4);
1247 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1248 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1249 udelay(100);
1250 }
1251
1252 /*
1253 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1254 * the MISC. register to stretch the UltraDMA Tss timing.
1255 * NOTE: This register is only writeable via I/O space.
1256 */
1257 if (info->chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1258
1259 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1221 1260
1222 return dev->irq; 1261 return dev->irq;
1223} 1262}
1224 1263
1225static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) 1264static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1226{ 1265{
1227 struct pci_dev *dev = hwif->pci_dev; 1266 struct pci_dev *dev = hwif->pci_dev;
1228 struct hpt_info *info = ide_get_hwifdata(hwif); 1267 struct hpt_info *info = pci_get_drvdata(dev);
1229 u8 ata66 = 0, regmask = (hwif->channel) ? 0x01 : 0x02;
1230 int serialize = HPT_SERIALIZE_IO; 1268 int serialize = HPT_SERIALIZE_IO;
1231 1269 u8 scr1 = 0, ata66 = (hwif->channel) ? 0x01 : 0x02;
1270 u8 chip_type = info->chip_type;
1271 u8 new_mcr, old_mcr = 0;
1272
1273 /* Cache the channel's MISC. control registers' offset */
1274 hwif->select_data = hwif->channel ? 0x54 : 0x50;
1275
1232 hwif->tuneproc = &hpt3xx_tune_drive; 1276 hwif->tuneproc = &hpt3xx_tune_drive;
1233 hwif->speedproc = &hpt3xx_tune_chipset; 1277 hwif->speedproc = &hpt3xx_tune_chipset;
1234 hwif->quirkproc = &hpt3xx_quirkproc; 1278 hwif->quirkproc = &hpt3xx_quirkproc;
1235 hwif->intrproc = &hpt3xx_intrproc; 1279 hwif->intrproc = &hpt3xx_intrproc;
1236 hwif->maskproc = &hpt3xx_maskproc; 1280 hwif->maskproc = &hpt3xx_maskproc;
1237 1281 hwif->busproc = &hpt3xx_busproc;
1282
1238 /* 1283 /*
1239 * HPT3xxN chips have some complications: 1284 * HPT3xxN chips have some complications:
1240 * 1285 *
1241 * - on 33 MHz PCI we must clock switch 1286 * - on 33 MHz PCI we must clock switch
1242 * - on 66 MHz PCI we must NOT use the PCI clock 1287 * - on 66 MHz PCI we must NOT use the PCI clock
1243 */ 1288 */
1244 if ((info->flags & (IS_3xxN | PCI_66MHZ)) == IS_3xxN) { 1289 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1245 /* 1290 /*
1246 * Clock is shared between the channels, 1291 * Clock is shared between the channels,
1247 * so we'll have to serialize them... :-( 1292 * so we'll have to serialize them... :-(
@@ -1250,200 +1295,171 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1250 hwif->rw_disk = &hpt3xxn_rw_disk; 1295 hwif->rw_disk = &hpt3xxn_rw_disk;
1251 } 1296 }
1252 1297
1298 /* Serialize access to this device if needed */
1299 if (serialize && hwif->mate)
1300 hwif->serialized = hwif->mate->serialized = 1;
1301
1302 /*
1303 * Disable the "fast interrupt" prediction. Don't hold off
1304 * on interrupts. (== 0x01 despite what the docs say)
1305 */
1306 pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);
1307
1308 if (info->chip_type >= HPT374)
1309 new_mcr = old_mcr & ~0x07;
1310 else if (info->chip_type >= HPT370) {
1311 new_mcr = old_mcr;
1312 new_mcr &= ~0x02;
1313
1314#ifdef HPT_DELAY_INTERRUPT
1315 new_mcr &= ~0x01;
1316#else
1317 new_mcr |= 0x01;
1318#endif
1319 } else /* HPT366 and HPT368 */
1320 new_mcr = old_mcr & ~0x80;
1321
1322 if (new_mcr != old_mcr)
1323 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
1324
1325 if (!hwif->dma_base) {
1326 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1327 return;
1328 }
1329
1330 hwif->ultra_mask = 0x7f;
1331 hwif->mwdma_mask = 0x07;
1332
1253 /* 1333 /*
1254 * The HPT37x uses the CBLID pins as outputs for MA15/MA16 1334 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1255 * address lines to access an external eeprom. To read valid 1335 * address lines to access an external EEPROM. To read valid
1256 * cable detect state the pins must be enabled as inputs. 1336 * cable detect state the pins must be enabled as inputs.
1257 */ 1337 */
1258 if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) { 1338 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1259 /* 1339 /*
1260 * HPT374 PCI function 1 1340 * HPT374 PCI function 1
1261 * - set bit 15 of reg 0x52 to enable TCBLID as input 1341 * - set bit 15 of reg 0x52 to enable TCBLID as input
1262 * - set bit 15 of reg 0x56 to enable FCBLID as input 1342 * - set bit 15 of reg 0x56 to enable FCBLID as input
1263 */ 1343 */
1264 u16 mcr3, mcr6; 1344 u8 mcr_addr = hwif->select_data + 2;
1265 pci_read_config_word(dev, 0x52, &mcr3); 1345 u16 mcr;
1266 pci_read_config_word(dev, 0x56, &mcr6); 1346
1267 pci_write_config_word(dev, 0x52, mcr3 | 0x8000); 1347 pci_read_config_word (dev, mcr_addr, &mcr);
1268 pci_write_config_word(dev, 0x56, mcr6 | 0x8000); 1348 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1269 /* now read cable id register */ 1349 /* now read cable id register */
1270 pci_read_config_byte(dev, 0x5a, &ata66); 1350 pci_read_config_byte (dev, 0x5a, &scr1);
1271 pci_write_config_word(dev, 0x52, mcr3); 1351 pci_write_config_word(dev, mcr_addr, mcr);
1272 pci_write_config_word(dev, 0x56, mcr6); 1352 } else if (chip_type >= HPT370) {
1273 } else if (info->revision >= 3) {
1274 /* 1353 /*
1275 * HPT370/372 and 374 pcifn 0 1354 * HPT370/372 and 374 pcifn 0
1276 * - clear bit 0 of 0x5b to enable P/SCBLID as inputs 1355 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1277 */ 1356 */
1278 u8 scr2; 1357 u8 scr2 = 0;
1279 pci_read_config_byte(dev, 0x5b, &scr2);
1280 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1281 /* now read cable id register */
1282 pci_read_config_byte(dev, 0x5a, &ata66);
1283 pci_write_config_byte(dev, 0x5b, scr2);
1284 } else {
1285 pci_read_config_byte(dev, 0x5a, &ata66);
1286 }
1287 1358
1288#ifdef DEBUG 1359 pci_read_config_byte (dev, 0x5b, &scr2);
1289 printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n", 1360 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1290 ata66, (ata66 & regmask) ? "33" : "66", 1361 /* now read cable id register */
1291 PCI_FUNC(hwif->pci_dev->devfn)); 1362 pci_read_config_byte (dev, 0x5a, &scr1);
1292#endif /* DEBUG */ 1363 pci_write_config_byte(dev, 0x5b, scr2);
1293 1364 } else
1294 /* Serialize access to this device */ 1365 pci_read_config_byte (dev, 0x5a, &scr1);
1295 if (serialize && hwif->mate)
1296 hwif->serialized = hwif->mate->serialized = 1;
1297 1366
1298 /* 1367 if (!hwif->udma_four)
1299 * Set up ioctl for power status. 1368 hwif->udma_four = (scr1 & ata66) ? 0 : 1;
1300 * NOTE: power affects both drives on each channel.
1301 */
1302 hwif->busproc = &hpt3xx_busproc;
1303 1369
1304 if (!hwif->dma_base) { 1370 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1305 hwif->drives[0].autotune = 1;
1306 hwif->drives[1].autotune = 1;
1307 return;
1308 }
1309 1371
1310 hwif->ultra_mask = 0x7f; 1372 if (chip_type >= HPT374) {
1311 hwif->mwdma_mask = 0x07; 1373 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1312 1374 hwif->ide_dma_end = &hpt374_ide_dma_end;
1313 if (!(hwif->udma_four)) 1375 } else if (chip_type >= HPT370) {
1314 hwif->udma_four = ((ata66 & regmask) ? 0 : 1); 1376 hwif->dma_start = &hpt370_ide_dma_start;
1315 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate; 1377 hwif->ide_dma_end = &hpt370_ide_dma_end;
1316 1378 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1317 if (info->revision >= 8) { 1379 } else
1318 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq; 1380 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1319 hwif->ide_dma_end = &hpt374_ide_dma_end;
1320 } else if (info->revision >= 5) {
1321 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1322 hwif->ide_dma_end = &hpt374_ide_dma_end;
1323 } else if (info->revision >= 3) {
1324 hwif->dma_start = &hpt370_ide_dma_start;
1325 hwif->ide_dma_end = &hpt370_ide_dma_end;
1326 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1327 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1328 } else if (info->revision >= 2)
1329 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1330 else
1331 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1332 1381
1333 if (!noautodma) 1382 if (!noautodma)
1334 hwif->autodma = 1; 1383 hwif->autodma = 1;
1335 hwif->drives[0].autodma = hwif->autodma; 1384 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1336 hwif->drives[1].autodma = hwif->autodma;
1337} 1385}
1338 1386
1339static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase) 1387static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1340{ 1388{
1341 struct hpt_info *info = ide_get_hwifdata(hwif); 1389 struct pci_dev *dev = hwif->pci_dev;
1342 u8 masterdma = 0, slavedma = 0; 1390 u8 masterdma = 0, slavedma = 0;
1343 u8 dma_new = 0, dma_old = 0; 1391 u8 dma_new = 0, dma_old = 0;
1344 u8 primary = hwif->channel ? 0x4b : 0x43;
1345 u8 secondary = hwif->channel ? 0x4f : 0x47;
1346 unsigned long flags; 1392 unsigned long flags;
1347 1393
1348 if (!dmabase) 1394 if (!dmabase)
1349 return; 1395 return;
1350 1396
1351 if(info->speed == NULL) { 1397 dma_old = hwif->INB(dmabase + 2);
1352 printk(KERN_WARNING "hpt366: no known IDE timings, disabling DMA.\n");
1353 return;
1354 }
1355
1356 dma_old = hwif->INB(dmabase+2);
1357 1398
1358 local_irq_save(flags); 1399 local_irq_save(flags);
1359 1400
1360 dma_new = dma_old; 1401 dma_new = dma_old;
1361 pci_read_config_byte(hwif->pci_dev, primary, &masterdma); 1402 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1362 pci_read_config_byte(hwif->pci_dev, secondary, &slavedma); 1403 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
1363 1404
1364 if (masterdma & 0x30) dma_new |= 0x20; 1405 if (masterdma & 0x30) dma_new |= 0x20;
1365 if (slavedma & 0x30) dma_new |= 0x40; 1406 if ( slavedma & 0x30) dma_new |= 0x40;
1366 if (dma_new != dma_old) 1407 if (dma_new != dma_old)
1367 hwif->OUTB(dma_new, dmabase+2); 1408 hwif->OUTB(dma_new, dmabase + 2);
1368 1409
1369 local_irq_restore(flags); 1410 local_irq_restore(flags);
1370 1411
1371 ide_setup_dma(hwif, dmabase, 8); 1412 ide_setup_dma(hwif, dmabase, 8);
1372} 1413}
1373 1414
1374/*
1375 * We "borrow" this hook in order to set the data structures
1376 * up early enough before dma or init_hwif calls are made.
1377 */
1378
1379static void __devinit init_iops_hpt366(ide_hwif_t *hwif)
1380{
1381 struct hpt_info *info = kzalloc(sizeof(struct hpt_info), GFP_KERNEL);
1382 struct pci_dev *dev = hwif->pci_dev;
1383 u16 did = dev->device;
1384 u8 rid = 0;
1385
1386 if(info == NULL) {
1387 printk(KERN_WARNING "hpt366: out of memory.\n");
1388 return;
1389 }
1390 ide_set_hwifdata(hwif, info);
1391
1392 /* Avoid doing the same thing twice. */
1393 if (hwif->channel && hwif->mate) {
1394 memcpy(info, ide_get_hwifdata(hwif->mate), sizeof(struct hpt_info));
1395 return;
1396 }
1397
1398 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rid);
1399
1400 if (( did == PCI_DEVICE_ID_TTI_HPT366 && rid == 6) ||
1401 ((did == PCI_DEVICE_ID_TTI_HPT372 ||
1402 did == PCI_DEVICE_ID_TTI_HPT302 ||
1403 did == PCI_DEVICE_ID_TTI_HPT371) && rid > 1) ||
1404 did == PCI_DEVICE_ID_TTI_HPT372N)
1405 info->flags |= IS_3xxN;
1406
1407 info->revision = hpt_revision(dev);
1408
1409 if (info->revision >= 3)
1410 hpt37x_clocking(hwif);
1411 else
1412 hpt366_clocking(hwif);
1413}
1414
1415static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d) 1415static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1416{ 1416{
1417 struct pci_dev *findev = NULL; 1417 struct pci_dev *dev2;
1418 1418
1419 if (PCI_FUNC(dev->devfn) & 1) 1419 if (PCI_FUNC(dev->devfn) & 1)
1420 return -ENODEV; 1420 return -ENODEV;
1421 1421
1422 while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) { 1422 pci_set_drvdata(dev, &hpt374);
1423 if ((findev->vendor == dev->vendor) && 1423
1424 (findev->device == dev->device) && 1424 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1425 ((findev->devfn - dev->devfn) == 1) && 1425 int ret;
1426 (PCI_FUNC(findev->devfn) & 1)) { 1426
1427 if (findev->irq != dev->irq) { 1427 pci_set_drvdata(dev2, &hpt374);
1428 /* FIXME: we need a core pci_set_interrupt() */ 1428
1429 findev->irq = dev->irq; 1429 if (dev2->irq != dev->irq) {
1430 printk(KERN_WARNING "%s: pci-config space interrupt " 1430 /* FIXME: we need a core pci_set_interrupt() */
1431 "fixed.\n", d->name); 1431 dev2->irq = dev->irq;
1432 } 1432 printk(KERN_WARNING "%s: PCI config space interrupt "
1433 return ide_setup_pci_devices(dev, findev, d); 1433 "fixed.\n", d->name);
1434 } 1434 }
1435 ret = ide_setup_pci_devices(dev, dev2, d);
1436 if (ret < 0)
1437 pci_dev_put(dev2);
1438 return ret;
1435 } 1439 }
1436 return ide_setup_pci_device(dev, d); 1440 return ide_setup_pci_device(dev, d);
1437} 1441}
1438 1442
1439static int __devinit init_setup_hpt37x(struct pci_dev *dev, ide_pci_device_t *d) 1443static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
1440{ 1444{
1445 pci_set_drvdata(dev, &hpt372n);
1446
1441 return ide_setup_pci_device(dev, d); 1447 return ide_setup_pci_device(dev, d);
1442} 1448}
1443 1449
1444static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d) 1450static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1445{ 1451{
1446 u8 mcr1 = 0; 1452 struct hpt_info *info;
1453 u8 rev = 0, mcr1 = 0;
1454
1455 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1456
1457 if (rev > 1) {
1458 d->name = "HPT371N";
1459
1460 info = &hpt371n;
1461 } else
1462 info = &hpt371;
1447 1463
1448 /* 1464 /*
1449 * HPT371 chips physically have only one channel, the secondary one, 1465 * HPT371 chips physically have only one channel, the secondary one,
@@ -1453,59 +1469,94 @@ static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1453 */ 1469 */
1454 pci_read_config_byte(dev, 0x50, &mcr1); 1470 pci_read_config_byte(dev, 0x50, &mcr1);
1455 if (mcr1 & 0x04) 1471 if (mcr1 & 0x04)
1456 pci_write_config_byte(dev, 0x50, (mcr1 & ~0x04)); 1472 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1473
1474 pci_set_drvdata(dev, info);
1475
1476 return ide_setup_pci_device(dev, d);
1477}
1478
1479static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
1480{
1481 struct hpt_info *info;
1482 u8 rev = 0;
1483
1484 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1485
1486 if (rev > 1) {
1487 d->name = "HPT372N";
1488
1489 info = &hpt372n;
1490 } else
1491 info = &hpt372a;
1492 pci_set_drvdata(dev, info);
1493
1494 return ide_setup_pci_device(dev, d);
1495}
1496
1497static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
1498{
1499 struct hpt_info *info;
1500 u8 rev = 0;
1501
1502 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1503
1504 if (rev > 1) {
1505 d->name = "HPT302N";
1506
1507 info = &hpt302n;
1508 } else
1509 info = &hpt302;
1510 pci_set_drvdata(dev, info);
1457 1511
1458 return ide_setup_pci_device(dev, d); 1512 return ide_setup_pci_device(dev, d);
1459} 1513}
1460 1514
1461static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d) 1515static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1462{ 1516{
1463 struct pci_dev *findev = NULL; 1517 struct pci_dev *dev2;
1464 u8 pin1 = 0, pin2 = 0; 1518 u8 rev = 0;
1465 unsigned int class_rev; 1519 static char *chipset_names[] = { "HPT366", "HPT366", "HPT368",
1466 char *chipset_names[] = {"HPT366", "HPT366", "HPT368", 1520 "HPT370", "HPT370A", "HPT372",
1467 "HPT370", "HPT370A", "HPT372", 1521 "HPT372N" };
1468 "HPT372N" }; 1522 static struct hpt_info *info[] = { &hpt36x, &hpt36x, &hpt36x,
1523 &hpt370, &hpt370a, &hpt372,
1524 &hpt372n };
1469 1525
1470 if (PCI_FUNC(dev->devfn) & 1) 1526 if (PCI_FUNC(dev->devfn) & 1)
1471 return -ENODEV; 1527 return -ENODEV;
1472 1528
1473 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); 1529 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1474 class_rev &= 0xff;
1475 1530
1476 if(dev->device == PCI_DEVICE_ID_TTI_HPT372N) 1531 if (rev > 6)
1477 class_rev = 6; 1532 rev = 6;
1478 1533
1479 if(class_rev <= 6) 1534 d->name = chipset_names[rev];
1480 d->name = chipset_names[class_rev]; 1535
1481 1536 pci_set_drvdata(dev, info[rev]);
1482 switch(class_rev) { 1537
1483 case 6: 1538 if (rev > 2)
1484 case 5: 1539 goto init_single;
1485 case 4:
1486 case 3:
1487 goto init_single;
1488 default:
1489 break;
1490 }
1491 1540
1492 d->channels = 1; 1541 d->channels = 1;
1493 1542
1494 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1); 1543 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1495 while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) { 1544 u8 pin1 = 0, pin2 = 0;
1496 if ((findev->vendor == dev->vendor) && 1545 int ret;
1497 (findev->device == dev->device) && 1546
1498 ((findev->devfn - dev->devfn) == 1) && 1547 pci_set_drvdata(dev2, info[rev]);
1499 (PCI_FUNC(findev->devfn) & 1)) { 1548
1500 pci_read_config_byte(findev, PCI_INTERRUPT_PIN, &pin2); 1549 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1501 if ((pin1 != pin2) && (dev->irq == findev->irq)) { 1550 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1502 d->bootable = ON_BOARD; 1551 if (pin1 != pin2 && dev->irq == dev2->irq) {
1503 printk("%s: onboard version of chipset, " 1552 d->bootable = ON_BOARD;
1504 "pin1=%d pin2=%d\n", d->name, 1553 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
1505 pin1, pin2); 1554 d->name, pin1, pin2);
1506 }
1507 return ide_setup_pci_devices(dev, findev, d);
1508 } 1555 }
1556 ret = ide_setup_pci_devices(dev, dev2, d);
1557 if (ret < 0)
1558 pci_dev_put(dev2);
1559 return ret;
1509 } 1560 }
1510init_single: 1561init_single:
1511 return ide_setup_pci_device(dev, d); 1562 return ide_setup_pci_device(dev, d);
@@ -1516,64 +1567,68 @@ static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1516 .name = "HPT366", 1567 .name = "HPT366",
1517 .init_setup = init_setup_hpt366, 1568 .init_setup = init_setup_hpt366,
1518 .init_chipset = init_chipset_hpt366, 1569 .init_chipset = init_chipset_hpt366,
1519 .init_iops = init_iops_hpt366,
1520 .init_hwif = init_hwif_hpt366, 1570 .init_hwif = init_hwif_hpt366,
1521 .init_dma = init_dma_hpt366, 1571 .init_dma = init_dma_hpt366,
1522 .channels = 2, 1572 .channels = 2,
1523 .autodma = AUTODMA, 1573 .autodma = AUTODMA,
1574 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1524 .bootable = OFF_BOARD, 1575 .bootable = OFF_BOARD,
1525 .extra = 240 1576 .extra = 240
1526 },{ /* 1 */ 1577 },{ /* 1 */
1527 .name = "HPT372A", 1578 .name = "HPT372A",
1528 .init_setup = init_setup_hpt37x, 1579 .init_setup = init_setup_hpt372a,
1529 .init_chipset = init_chipset_hpt366, 1580 .init_chipset = init_chipset_hpt366,
1530 .init_iops = init_iops_hpt366,
1531 .init_hwif = init_hwif_hpt366, 1581 .init_hwif = init_hwif_hpt366,
1532 .init_dma = init_dma_hpt366, 1582 .init_dma = init_dma_hpt366,
1533 .channels = 2, 1583 .channels = 2,
1534 .autodma = AUTODMA, 1584 .autodma = AUTODMA,
1585 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1535 .bootable = OFF_BOARD, 1586 .bootable = OFF_BOARD,
1587 .extra = 240
1536 },{ /* 2 */ 1588 },{ /* 2 */
1537 .name = "HPT302", 1589 .name = "HPT302",
1538 .init_setup = init_setup_hpt37x, 1590 .init_setup = init_setup_hpt302,
1539 .init_chipset = init_chipset_hpt366, 1591 .init_chipset = init_chipset_hpt366,
1540 .init_iops = init_iops_hpt366,
1541 .init_hwif = init_hwif_hpt366, 1592 .init_hwif = init_hwif_hpt366,
1542 .init_dma = init_dma_hpt366, 1593 .init_dma = init_dma_hpt366,
1543 .channels = 2, 1594 .channels = 2,
1544 .autodma = AUTODMA, 1595 .autodma = AUTODMA,
1596 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1545 .bootable = OFF_BOARD, 1597 .bootable = OFF_BOARD,
1598 .extra = 240
1546 },{ /* 3 */ 1599 },{ /* 3 */
1547 .name = "HPT371", 1600 .name = "HPT371",
1548 .init_setup = init_setup_hpt371, 1601 .init_setup = init_setup_hpt371,
1549 .init_chipset = init_chipset_hpt366, 1602 .init_chipset = init_chipset_hpt366,
1550 .init_iops = init_iops_hpt366,
1551 .init_hwif = init_hwif_hpt366, 1603 .init_hwif = init_hwif_hpt366,
1552 .init_dma = init_dma_hpt366, 1604 .init_dma = init_dma_hpt366,
1553 .channels = 2, 1605 .channels = 2,
1554 .autodma = AUTODMA, 1606 .autodma = AUTODMA,
1555 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1607 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1556 .bootable = OFF_BOARD, 1608 .bootable = OFF_BOARD,
1609 .extra = 240
1557 },{ /* 4 */ 1610 },{ /* 4 */
1558 .name = "HPT374", 1611 .name = "HPT374",
1559 .init_setup = init_setup_hpt374, 1612 .init_setup = init_setup_hpt374,
1560 .init_chipset = init_chipset_hpt366, 1613 .init_chipset = init_chipset_hpt366,
1561 .init_iops = init_iops_hpt366,
1562 .init_hwif = init_hwif_hpt366, 1614 .init_hwif = init_hwif_hpt366,
1563 .init_dma = init_dma_hpt366, 1615 .init_dma = init_dma_hpt366,
1564 .channels = 2, /* 4 */ 1616 .channels = 2, /* 4 */
1565 .autodma = AUTODMA, 1617 .autodma = AUTODMA,
1618 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1566 .bootable = OFF_BOARD, 1619 .bootable = OFF_BOARD,
1620 .extra = 240
1567 },{ /* 5 */ 1621 },{ /* 5 */
1568 .name = "HPT372N", 1622 .name = "HPT372N",
1569 .init_setup = init_setup_hpt37x, 1623 .init_setup = init_setup_hpt372n,
1570 .init_chipset = init_chipset_hpt366, 1624 .init_chipset = init_chipset_hpt366,
1571 .init_iops = init_iops_hpt366,
1572 .init_hwif = init_hwif_hpt366, 1625 .init_hwif = init_hwif_hpt366,
1573 .init_dma = init_dma_hpt366, 1626 .init_dma = init_dma_hpt366,
1574 .channels = 2, /* 4 */ 1627 .channels = 2, /* 4 */
1575 .autodma = AUTODMA, 1628 .autodma = AUTODMA,
1629 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1576 .bootable = OFF_BOARD, 1630 .bootable = OFF_BOARD,
1631 .extra = 240
1577 } 1632 }
1578}; 1633};
1579 1634
diff --git a/drivers/ide/pci/it8213.c b/drivers/ide/pci/it8213.c
new file mode 100644
index 000000000000..63248b6909fa
--- /dev/null
+++ b/drivers/ide/pci/it8213.c
@@ -0,0 +1,362 @@
1/*
2 * ITE 8213 IDE driver
3 *
4 * Copyright (C) 2006 Jack Lee
5 * Copyright (C) 2006 Alan Cox
6 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
7 */
8
9#include <linux/kernel.h>
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/delay.h>
14#include <linux/hdreg.h>
15#include <linux/ide.h>
16#include <linux/init.h>
17
18#include <asm/io.h>
19
20/*
21 * it8213_ratemask - Compute available modes
22 * @drive: IDE drive
23 *
24 * Compute the available speeds for the devices on the interface. This
25 * is all modes to ATA133 clipped by drive cable setup.
26 */
27
28static u8 it8213_ratemask (ide_drive_t *drive)
29{
30 u8 mode = 4;
31 if (!eighty_ninty_three(drive))
32 mode = min_t(u8, mode, 1);
33 return mode;
34}
35
36/**
37 * it8213_dma_2_pio - return the PIO mode matching DMA
38 * @xfer_rate: transfer speed
39 *
40 * Returns the nearest equivalent PIO timing for the PIO or DMA
41 * mode requested by the controller.
42 */
43
44static u8 it8213_dma_2_pio (u8 xfer_rate) {
45 switch(xfer_rate) {
46 case XFER_UDMA_6:
47 case XFER_UDMA_5:
48 case XFER_UDMA_4:
49 case XFER_UDMA_3:
50 case XFER_UDMA_2:
51 case XFER_UDMA_1:
52 case XFER_UDMA_0:
53 case XFER_MW_DMA_2:
54 case XFER_PIO_4:
55 return 4;
56 case XFER_MW_DMA_1:
57 case XFER_PIO_3:
58 return 3;
59 case XFER_SW_DMA_2:
60 case XFER_PIO_2:
61 return 2;
62 case XFER_MW_DMA_0:
63 case XFER_SW_DMA_1:
64 case XFER_SW_DMA_0:
65 case XFER_PIO_1:
66 case XFER_PIO_0:
67 case XFER_PIO_SLOW:
68 default:
69 return 0;
70 }
71}
72
73/*
74 * it8213_tuneproc - tune a drive
75 * @drive: drive to tune
76 * @pio: desired PIO mode
77 *
78 * Set the interface PIO mode.
79 */
80
81static void it8213_tuneproc (ide_drive_t *drive, u8 pio)
82{
83 ide_hwif_t *hwif = HWIF(drive);
84 struct pci_dev *dev = hwif->pci_dev;
85 int is_slave = drive->dn & 1;
86 int master_port = 0x40;
87 int slave_port = 0x44;
88 unsigned long flags;
89 u16 master_data;
90 u8 slave_data;
91 static DEFINE_SPINLOCK(tune_lock);
92 int control = 0;
93
94 static const u8 timings[][2]= {
95 { 0, 0 },
96 { 0, 0 },
97 { 1, 0 },
98 { 2, 1 },
99 { 2, 3 }, };
100
101 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
102
103 spin_lock_irqsave(&tune_lock, flags);
104 pci_read_config_word(dev, master_port, &master_data);
105
106 if (pio > 1)
107 control |= 1; /* Programmable timing on */
108 if (drive->media != ide_disk)
109 control |= 4; /* ATAPI */
110 if (pio > 2)
111 control |= 2; /* IORDY */
112 if (is_slave) {
113 master_data |= 0x4000;
114 master_data &= ~0x0070;
115 if (pio > 1)
116 master_data = master_data | (control << 4);
117 pci_read_config_byte(dev, slave_port, &slave_data);
118 slave_data = slave_data & 0xf0;
119 slave_data = slave_data | (timings[pio][0] << 2) | timings[pio][1];
120 } else {
121 master_data &= ~0x3307;
122 if (pio > 1)
123 master_data = master_data | control;
124 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
125 }
126 pci_write_config_word(dev, master_port, master_data);
127 if (is_slave)
128 pci_write_config_byte(dev, slave_port, slave_data);
129 spin_unlock_irqrestore(&tune_lock, flags);
130}
131
132/**
133 * it8213_tune_chipset - set controller timings
134 * @drive: Drive to set up
135 * @xferspeed: speed we want to achieve
136 *
137 * Tune the ITE chipset for the desired mode. If we can't achieve
138 * the desired mode then tune for a lower one, but ultimately
139 * make the thing work.
140 */
141
142static int it8213_tune_chipset (ide_drive_t *drive, u8 xferspeed)
143{
144
145 ide_hwif_t *hwif = HWIF(drive);
146 struct pci_dev *dev = hwif->pci_dev;
147 u8 maslave = 0x40;
148 u8 speed = ide_rate_filter(it8213_ratemask(drive), xferspeed);
149 int a_speed = 3 << (drive->dn * 4);
150 int u_flag = 1 << drive->dn;
151 int v_flag = 0x01 << drive->dn;
152 int w_flag = 0x10 << drive->dn;
153 int u_speed = 0;
154 u16 reg4042, reg4a;
155 u8 reg48, reg54, reg55;
156
157 pci_read_config_word(dev, maslave, &reg4042);
158 pci_read_config_byte(dev, 0x48, &reg48);
159 pci_read_config_word(dev, 0x4a, &reg4a);
160 pci_read_config_byte(dev, 0x54, &reg54);
161 pci_read_config_byte(dev, 0x55, &reg55);
162
163 switch(speed) {
164 case XFER_UDMA_6:
165 case XFER_UDMA_4:
166 case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
167 case XFER_UDMA_5:
168 case XFER_UDMA_3:
169 case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
170 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
171 break;
172 case XFER_MW_DMA_2:
173 case XFER_MW_DMA_1:
174 case XFER_SW_DMA_2:
175 break;
176 case XFER_PIO_4:
177 case XFER_PIO_3:
178 case XFER_PIO_2:
179 case XFER_PIO_1:
180 case XFER_PIO_0:
181 break;
182 default:
183 return -1;
184 }
185
186 if (speed >= XFER_UDMA_0) {
187 if (!(reg48 & u_flag))
188 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
189 if (speed >= XFER_UDMA_5) {
190 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
191 } else {
192 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
193 }
194
195 if ((reg4a & a_speed) != u_speed)
196 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
197 if (speed > XFER_UDMA_2) {
198 if (!(reg54 & v_flag))
199 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
200 } else
201 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
202 } else {
203 if (reg48 & u_flag)
204 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
205 if (reg4a & a_speed)
206 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
207 if (reg54 & v_flag)
208 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
209 if (reg55 & w_flag)
210 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
211 }
212 it8213_tuneproc(drive, it8213_dma_2_pio(speed));
213 return ide_config_drive_speed(drive, speed);
214}
215
216/*
217 * config_chipset_for_dma - configure for DMA
218 * @drive: drive to configure
219 *
220 * Called by the IDE layer when it wants the timings set up.
221 */
222
223static int config_chipset_for_dma (ide_drive_t *drive)
224{
225 u8 speed = ide_dma_speed(drive, it8213_ratemask(drive));
226
227 if (!speed)
228 return 0;
229
230 it8213_tune_chipset(drive, speed);
231
232 return ide_dma_enable(drive);
233}
234
235/**
236 * it8213_configure_drive_for_dma - set up for DMA transfers
237 * @drive: drive we are going to set up
238 *
239 * Set up the drive for DMA, tune the controller and drive as
240 * required. If the drive isn't suitable for DMA or we hit
241 * other problems then we will drop down to PIO and set up
242 * PIO appropriately
243 */
244
245static int it8213_config_drive_for_dma (ide_drive_t *drive)
246{
247 ide_hwif_t *hwif = drive->hwif;
248
249 if (ide_use_dma(drive)) {
250 if (config_chipset_for_dma(drive))
251 return hwif->ide_dma_on(drive);
252 }
253
254 hwif->speedproc(drive, XFER_PIO_0
255 + ide_get_best_pio_mode(drive, 255, 4, NULL));
256
257 return hwif->ide_dma_off_quietly(drive);
258}
259
260/**
261 * init_hwif_it8213 - set up hwif structs
262 * @hwif: interface to set up
263 *
264 * We do the basic set up of the interface structure. The IT8212
265 * requires several custom handlers so we override the default
266 * ide DMA handlers appropriately
267 */
268
269static void __devinit init_hwif_it8213(ide_hwif_t *hwif)
270{
271 u8 reg42h = 0, ata66 = 0;
272
273 hwif->speedproc = &it8213_tune_chipset;
274 hwif->tuneproc = &it8213_tuneproc;
275
276 hwif->autodma = 0;
277
278 hwif->drives[0].autotune = 1;
279 hwif->drives[1].autotune = 1;
280
281 if (!hwif->dma_base)
282 return;
283
284 hwif->atapi_dma = 1;
285 hwif->ultra_mask = 0x7f;
286 hwif->mwdma_mask = 0x06;
287 hwif->swdma_mask = 0x04;
288
289 pci_read_config_byte(hwif->pci_dev, 0x42, &reg42h);
290 ata66 = (reg42h & 0x02) ? 0 : 1;
291
292 hwif->ide_dma_check = &it8213_config_drive_for_dma;
293 if (!(hwif->udma_four))
294 hwif->udma_four = ata66;
295
296 /*
297 * The BIOS often doesn't set up DMA on this controller
298 * so we always do it.
299 */
300 if (!noautodma)
301 hwif->autodma = 1;
302
303 hwif->drives[0].autodma = hwif->autodma;
304 hwif->drives[1].autodma = hwif->autodma;
305}
306
307
308#define DECLARE_ITE_DEV(name_str) \
309 { \
310 .name = name_str, \
311 .init_hwif = init_hwif_it8213, \
312 .channels = 1, \
313 .autodma = AUTODMA, \
314 .enablebits = {{0x41,0x80,0x80}}, \
315 .bootable = ON_BOARD, \
316 }
317
318static ide_pci_device_t it8213_chipsets[] __devinitdata = {
319 /* 0 */ DECLARE_ITE_DEV("IT8213"),
320};
321
322
323/**
324 * it8213_init_one - pci layer discovery entry
325 * @dev: PCI device
326 * @id: ident table entry
327 *
328 * Called by the PCI code when it finds an ITE8213 controller. As
329 * this device follows the standard interfaces we can use the
330 * standard helper functions to do almost all the work for us.
331 */
332
333static int __devinit it8213_init_one(struct pci_dev *dev, const struct pci_device_id *id)
334{
335 ide_setup_pci_device(dev, &it8213_chipsets[id->driver_data]);
336 return 0;
337}
338
339
340static struct pci_device_id it8213_pci_tbl[] = {
341 { PCI_VENDOR_ID_ITE, 0x8213, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
342 { 0, },
343};
344
345MODULE_DEVICE_TABLE(pci, it8213_pci_tbl);
346
347static struct pci_driver driver = {
348 .name = "ITE8213_IDE",
349 .id_table = it8213_pci_tbl,
350 .probe = it8213_init_one,
351};
352
353static int __init it8213_ide_init(void)
354{
355 return ide_pci_register_driver(&driver);
356}
357
358module_init(it8213_ide_init);
359
360MODULE_AUTHOR("Jack Lee, Alan Cox");
361MODULE_DESCRIPTION("PCI driver module for the ITE 8213");
362MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/pdc202xx_new.c b/drivers/ide/pci/pdc202xx_new.c
index 77a9aaa7dab9..236a03144a27 100644
--- a/drivers/ide/pci/pdc202xx_new.c
+++ b/drivers/ide/pci/pdc202xx_new.c
@@ -92,26 +92,6 @@ static u8 pdcnew_ratemask(ide_drive_t *drive)
92 return mode; 92 return mode;
93} 93}
94 94
95static int check_in_drive_lists(ide_drive_t *drive, const char **list)
96{
97 struct hd_driveid *id = drive->id;
98
99 if (pdc_quirk_drives == list) {
100 while (*list) {
101 if (strstr(id->model, *list++)) {
102 return 2;
103 }
104 }
105 } else {
106 while (*list) {
107 if (!strcmp(*list++,id->model)) {
108 return 1;
109 }
110 }
111 }
112 return 0;
113}
114
115/** 95/**
116 * get_indexed_reg - Get indexed register 96 * get_indexed_reg - Get indexed register
117 * @hwif: for the port address 97 * @hwif: for the port address
@@ -249,13 +229,6 @@ static int pdcnew_tune_chipset(ide_drive_t *drive, u8 speed)
249 return err; 229 return err;
250} 230}
251 231
252/* 0 1 2 3 4 5 6 7 8
253 * 960, 480, 390, 300, 240, 180, 120, 90, 60
254 * 180, 150, 120, 90, 60
255 * DMA_Speed
256 * 180, 120, 90, 90, 90, 60, 30
257 * 11, 5, 4, 3, 2, 1, 0
258 */
259static void pdcnew_tune_drive(ide_drive_t *drive, u8 pio) 232static void pdcnew_tune_drive(ide_drive_t *drive, u8 pio)
260{ 233{
261 pio = ide_get_best_pio_mode(drive, pio, 4, NULL); 234 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
@@ -313,12 +286,10 @@ static int pdcnew_config_drive_xfer_rate(ide_drive_t *drive)
313 286
314 drive->init_speed = 0; 287 drive->init_speed = 0;
315 288
316 if (id && (id->capability & 1) && drive->autodma) { 289 if ((id->capability & 1) && drive->autodma) {
317 290
318 if (ide_use_dma(drive)) { 291 if (ide_use_dma(drive) && config_chipset_for_dma(drive))
319 if (config_chipset_for_dma(drive)) 292 return hwif->ide_dma_on(drive);
320 return hwif->ide_dma_on(drive);
321 }
322 293
323 goto fast_ata_pio; 294 goto fast_ata_pio;
324 295
@@ -333,21 +304,12 @@ fast_ata_pio:
333 304
334static int pdcnew_quirkproc(ide_drive_t *drive) 305static int pdcnew_quirkproc(ide_drive_t *drive)
335{ 306{
336 return check_in_drive_lists(drive, pdc_quirk_drives); 307 const char **list, *model = drive->id->model;
337}
338 308
339static int pdcnew_ide_dma_lostirq(ide_drive_t *drive) 309 for (list = pdc_quirk_drives; *list != NULL; list++)
340{ 310 if (strstr(model, *list) != NULL)
341 if (HWIF(drive)->resetproc != NULL) 311 return 2;
342 HWIF(drive)->resetproc(drive); 312 return 0;
343 return __ide_dma_lostirq(drive);
344}
345
346static int pdcnew_ide_dma_timeout(ide_drive_t *drive)
347{
348 if (HWIF(drive)->resetproc != NULL)
349 HWIF(drive)->resetproc(drive);
350 return __ide_dma_timeout(drive);
351} 313}
352 314
353static void pdcnew_reset(ide_drive_t *drive) 315static void pdcnew_reset(ide_drive_t *drive)
@@ -599,8 +561,6 @@ static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
599 hwif->err_stops_fifo = 1; 561 hwif->err_stops_fifo = 1;
600 562
601 hwif->ide_dma_check = &pdcnew_config_drive_xfer_rate; 563 hwif->ide_dma_check = &pdcnew_config_drive_xfer_rate;
602 hwif->ide_dma_lostirq = &pdcnew_ide_dma_lostirq;
603 hwif->ide_dma_timeout = &pdcnew_ide_dma_timeout;
604 564
605 if (!hwif->udma_four) 565 if (!hwif->udma_four)
606 hwif->udma_four = pdcnew_cable_detect(hwif) ? 0 : 1; 566 hwif->udma_four = pdcnew_cable_detect(hwif) ? 0 : 1;
diff --git a/drivers/ide/pci/pdc202xx_old.c b/drivers/ide/pci/pdc202xx_old.c
index 143239c093d5..730e8d1ec2f5 100644
--- a/drivers/ide/pci/pdc202xx_old.c
+++ b/drivers/ide/pci/pdc202xx_old.c
@@ -123,26 +123,6 @@ static u8 pdc202xx_ratemask (ide_drive_t *drive)
123 return mode; 123 return mode;
124} 124}
125 125
126static int check_in_drive_lists (ide_drive_t *drive, const char **list)
127{
128 struct hd_driveid *id = drive->id;
129
130 if (pdc_quirk_drives == list) {
131 while (*list) {
132 if (strstr(id->model, *list++)) {
133 return 2;
134 }
135 }
136 } else {
137 while (*list) {
138 if (!strcmp(*list++,id->model)) {
139 return 1;
140 }
141 }
142 }
143 return 0;
144}
145
146static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed) 126static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
147{ 127{
148 ide_hwif_t *hwif = HWIF(drive); 128 ide_hwif_t *hwif = HWIF(drive);
@@ -377,7 +357,12 @@ fast_ata_pio:
377 357
378static int pdc202xx_quirkproc (ide_drive_t *drive) 358static int pdc202xx_quirkproc (ide_drive_t *drive)
379{ 359{
380 return ((int) check_in_drive_lists(drive, pdc_quirk_drives)); 360 const char **list, *model = drive->id->model;
361
362 for (list = pdc_quirk_drives; *list != NULL; list++)
363 if (strstr(model, *list) != NULL)
364 return 2;
365 return 0;
381} 366}
382 367
383static void pdc202xx_old_ide_dma_start(ide_drive_t *drive) 368static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
diff --git a/drivers/ide/pci/piix.c b/drivers/ide/pci/piix.c
index edb37f3d558d..52cfc2ac22c1 100644
--- a/drivers/ide/pci/piix.c
+++ b/drivers/ide/pci/piix.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/ide/pci/piix.c Version 0.45 May 12, 2006 2 * linux/drivers/ide/pci/piix.c Version 0.46 December 3, 2006
3 * 3 *
4 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer 4 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
@@ -163,7 +163,7 @@ static u8 piix_ratemask (ide_drive_t *drive)
163 * if the drive cannot see an 80pin cable. 163 * if the drive cannot see an 80pin cable.
164 */ 164 */
165 if (!eighty_ninty_three(drive)) 165 if (!eighty_ninty_three(drive))
166 mode = min(mode, (u8)1); 166 mode = min_t(u8, mode, 1);
167 return mode; 167 return mode;
168} 168}
169 169
@@ -216,7 +216,7 @@ static void piix_tune_drive (ide_drive_t *drive, u8 pio)
216{ 216{
217 ide_hwif_t *hwif = HWIF(drive); 217 ide_hwif_t *hwif = HWIF(drive);
218 struct pci_dev *dev = hwif->pci_dev; 218 struct pci_dev *dev = hwif->pci_dev;
219 int is_slave = (&hwif->drives[1] == drive); 219 int is_slave = drive->dn & 1;
220 int master_port = hwif->channel ? 0x42 : 0x40; 220 int master_port = hwif->channel ? 0x42 : 0x40;
221 int slave_port = 0x44; 221 int slave_port = 0x44;
222 unsigned long flags; 222 unsigned long flags;
@@ -225,7 +225,7 @@ static void piix_tune_drive (ide_drive_t *drive, u8 pio)
225 static DEFINE_SPINLOCK(tune_lock); 225 static DEFINE_SPINLOCK(tune_lock);
226 int control = 0; 226 int control = 0;
227 227
228 /* ISP RTC */ 228 /* ISP RTC */
229 static const u8 timings[][2]= { 229 static const u8 timings[][2]= {
230 { 0, 0 }, 230 { 0, 0 },
231 { 0, 0 }, 231 { 0, 0 },
@@ -233,7 +233,7 @@ static void piix_tune_drive (ide_drive_t *drive, u8 pio)
233 { 2, 1 }, 233 { 2, 1 },
234 { 2, 3 }, }; 234 { 2, 3 }, };
235 235
236 pio = ide_get_best_pio_mode(drive, pio, 5, NULL); 236 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
237 237
238 /* 238 /*
239 * Master vs slave is synchronized above us but the slave register is 239 * Master vs slave is synchronized above us but the slave register is
@@ -243,25 +243,24 @@ static void piix_tune_drive (ide_drive_t *drive, u8 pio)
243 spin_lock_irqsave(&tune_lock, flags); 243 spin_lock_irqsave(&tune_lock, flags);
244 pci_read_config_word(dev, master_port, &master_data); 244 pci_read_config_word(dev, master_port, &master_data);
245 245
246 if (pio >= 2) 246 if (pio > 1)
247 control |= 1; /* Programmable timing on */ 247 control |= 1; /* Programmable timing on */
248 if (drive->media == ide_disk) 248 if (drive->media == ide_disk)
249 control |= 4; /* Prefetch, post write */ 249 control |= 4; /* Prefetch, post write */
250 if (pio >= 3) 250 if (pio > 2)
251 control |= 2; /* IORDY */ 251 control |= 2; /* IORDY */
252 if (is_slave) { 252 if (is_slave) {
253 master_data = master_data | 0x4000; 253 master_data |= 0x4000;
254 master_data &= ~0x0070;
254 if (pio > 1) { 255 if (pio > 1) {
255 /* enable PPE, IE and TIME */ 256 /* enable PPE, IE and TIME */
256 master_data = master_data | (control << 4); 257 master_data = master_data | (control << 4);
257 } else {
258 master_data &= ~0x0070;
259 } 258 }
260 pci_read_config_byte(dev, slave_port, &slave_data); 259 pci_read_config_byte(dev, slave_port, &slave_data);
261 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0); 260 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
262 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0)); 261 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
263 } else { 262 } else {
264 master_data = master_data & 0xccf8; 263 master_data &= ~0x3307;
265 if (pio > 1) { 264 if (pio > 1) {
266 /* enable PPE, IE and TIME */ 265 /* enable PPE, IE and TIME */
267 master_data = master_data | control; 266 master_data = master_data | control;
@@ -539,13 +538,19 @@ static ide_pci_device_t piix_pci_info[] __devinitdata = {
539 /* 0 */ DECLARE_PIIX_DEV("PIIXa"), 538 /* 0 */ DECLARE_PIIX_DEV("PIIXa"),
540 /* 1 */ DECLARE_PIIX_DEV("PIIXb"), 539 /* 1 */ DECLARE_PIIX_DEV("PIIXb"),
541 540
542 { /* 2 */ 541 /* 2 */
542 { /*
543 * MPIIX actually has only a single IDE channel mapped to
544 * the primary or secondary ports depending on the value
545 * of the bit 14 of the IDETIM register at offset 0x6c
546 */
543 .name = "MPIIX", 547 .name = "MPIIX",
544 .init_hwif = init_hwif_piix, 548 .init_hwif = init_hwif_piix,
545 .channels = 2, 549 .channels = 2,
546 .autodma = NODMA, 550 .autodma = NODMA,
547 .enablebits = {{0x6D,0x80,0x80}, {0x6F,0x80,0x80}}, 551 .enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
548 .bootable = ON_BOARD, 552 .bootable = ON_BOARD,
553 .flags = IDEPCI_FLAG_ISA_PORTS
549 }, 554 },
550 555
551 /* 3 */ DECLARE_PIIX_DEV("PIIX3"), 556 /* 3 */ DECLARE_PIIX_DEV("PIIX3"),
diff --git a/drivers/ide/pci/slc90e66.c b/drivers/ide/pci/slc90e66.c
index 90e79c0844d2..2663ddbd9b67 100644
--- a/drivers/ide/pci/slc90e66.c
+++ b/drivers/ide/pci/slc90e66.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/ide/pci/slc90e66.c Version 0.12 May 12, 2006 2 * linux/drivers/ide/pci/slc90e66.c Version 0.13 December 30, 2006
3 * 3 *
4 * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org> 4 * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2006 MontaVista Software, Inc. <source@mvista.com> 5 * Copyright (C) 2006 MontaVista Software, Inc. <source@mvista.com>
@@ -26,7 +26,7 @@ static u8 slc90e66_ratemask (ide_drive_t *drive)
26 u8 mode = 2; 26 u8 mode = 2;
27 27
28 if (!eighty_ninty_three(drive)) 28 if (!eighty_ninty_three(drive))
29 mode = min(mode, (u8)1); 29 mode = min_t(u8, mode, 1);
30 return mode; 30 return mode;
31} 31}
32 32
@@ -65,36 +65,47 @@ static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
65{ 65{
66 ide_hwif_t *hwif = HWIF(drive); 66 ide_hwif_t *hwif = HWIF(drive);
67 struct pci_dev *dev = hwif->pci_dev; 67 struct pci_dev *dev = hwif->pci_dev;
68 int is_slave = (&hwif->drives[1] == drive); 68 int is_slave = drive->dn & 1;
69 int master_port = hwif->channel ? 0x42 : 0x40; 69 int master_port = hwif->channel ? 0x42 : 0x40;
70 int slave_port = 0x44; 70 int slave_port = 0x44;
71 unsigned long flags; 71 unsigned long flags;
72 u16 master_data; 72 u16 master_data;
73 u8 slave_data; 73 u8 slave_data;
74 /* ISP RTC */ 74 int control = 0;
75 /* ISP RTC */
75 static const u8 timings[][2]= { 76 static const u8 timings[][2]= {
76 { 0, 0 }, 77 { 0, 0 },
77 { 0, 0 }, 78 { 0, 0 },
78 { 1, 0 }, 79 { 1, 0 },
79 { 2, 1 }, 80 { 2, 1 },
80 { 2, 3 }, }; 81 { 2, 3 }, };
81 82
82 pio = ide_get_best_pio_mode(drive, pio, 5, NULL); 83 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
83 spin_lock_irqsave(&ide_lock, flags); 84 spin_lock_irqsave(&ide_lock, flags);
84 pci_read_config_word(dev, master_port, &master_data); 85 pci_read_config_word(dev, master_port, &master_data);
86
87 if (pio > 1)
88 control |= 1; /* Programmable timing on */
89 if (drive->media == ide_disk)
90 control |= 4; /* Prefetch, post write */
91 if (pio > 2)
92 control |= 2; /* IORDY */
85 if (is_slave) { 93 if (is_slave) {
86 master_data = master_data | 0x4000; 94 master_data |= 0x4000;
87 if (pio > 1) 95 master_data &= ~0x0070;
96 if (pio > 1) {
88 /* enable PPE, IE and TIME */ 97 /* enable PPE, IE and TIME */
89 master_data = master_data | 0x0070; 98 master_data = master_data | (control << 4);
99 }
90 pci_read_config_byte(dev, slave_port, &slave_data); 100 pci_read_config_byte(dev, slave_port, &slave_data);
91 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0); 101 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
92 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0)); 102 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
93 } else { 103 } else {
94 master_data = master_data & 0xccf8; 104 master_data &= ~0x3307;
95 if (pio > 1) 105 if (pio > 1) {
96 /* enable PPE, IE and TIME */ 106 /* enable PPE, IE and TIME */
97 master_data = master_data | 0x0007; 107 master_data = master_data | control;
108 }
98 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8); 109 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
99 } 110 }
100 pci_write_config_word(dev, master_port, master_data); 111 pci_write_config_word(dev, master_port, master_data);
@@ -173,7 +184,7 @@ static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)
173 184
174 drive->init_speed = 0; 185 drive->init_speed = 0;
175 186
176 if (id && (id->capability & 1) && drive->autodma) { 187 if ((id->capability & 1) && drive->autodma) {
177 188
178 if (ide_use_dma(drive) && slc90e66_config_drive_for_dma(drive)) 189 if (ide_use_dma(drive) && slc90e66_config_drive_for_dma(drive))
179 return hwif->ide_dma_on(drive); 190 return hwif->ide_dma_on(drive);
@@ -201,7 +212,7 @@ static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
201 hwif->irq = hwif->channel ? 15 : 14; 212 hwif->irq = hwif->channel ? 15 : 14;
202 213
203 hwif->speedproc = &slc90e66_tune_chipset; 214 hwif->speedproc = &slc90e66_tune_chipset;
204 hwif->tuneproc = &slc90e66_tune_drive; 215 hwif->tuneproc = &slc90e66_tune_drive;
205 216
206 pci_read_config_byte(hwif->pci_dev, 0x47, &reg47); 217 pci_read_config_byte(hwif->pci_dev, 0x47, &reg47);
207 218
@@ -213,14 +224,16 @@ static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
213 224
214 hwif->atapi_dma = 1; 225 hwif->atapi_dma = 1;
215 hwif->ultra_mask = 0x1f; 226 hwif->ultra_mask = 0x1f;
216 hwif->mwdma_mask = 0x07; 227 hwif->mwdma_mask = 0x06;
217 hwif->swdma_mask = 0x07; 228 hwif->swdma_mask = 0x04;
218 229
219 if (!(hwif->udma_four)) 230 if (!hwif->udma_four) {
220 /* bit[0(1)]: 0:80, 1:40 */ 231 /* bit[0(1)]: 0:80, 1:40 */
221 hwif->udma_four = (reg47 & mask) ? 0 : 1; 232 hwif->udma_four = (reg47 & mask) ? 0 : 1;
233 }
222 234
223 hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate; 235 hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate;
236
224 if (!noautodma) 237 if (!noautodma)
225 hwif->autodma = 1; 238 hwif->autodma = 1;
226 hwif->drives[0].autodma = hwif->autodma; 239 hwif->drives[0].autodma = hwif->autodma;
diff --git a/drivers/ide/pci/tc86c001.c b/drivers/ide/pci/tc86c001.c
new file mode 100644
index 000000000000..2ad72bbda342
--- /dev/null
+++ b/drivers/ide/pci/tc86c001.c
@@ -0,0 +1,309 @@
1/*
2 * drivers/ide/pci/tc86c001.c Version 1.00 Dec 12, 2006
3 *
4 * Copyright (C) 2002 Toshiba Corporation
5 * Copyright (C) 2005-2006 MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/types.h>
13#include <linux/pci.h>
14#include <linux/ide.h>
15
16static inline u8 tc86c001_ratemask(ide_drive_t *drive)
17{
18 return eighty_ninty_three(drive) ? 2 : 1;
19}
20
21static int tc86c001_tune_chipset(ide_drive_t *drive, u8 speed)
22{
23 ide_hwif_t *hwif = HWIF(drive);
24 unsigned long scr_port = hwif->config_data + (drive->dn ? 0x02 : 0x00);
25 u16 mode, scr = hwif->INW(scr_port);
26
27 speed = ide_rate_filter(tc86c001_ratemask(drive), speed);
28
29 switch (speed) {
30 case XFER_UDMA_4: mode = 0x00c0; break;
31 case XFER_UDMA_3: mode = 0x00b0; break;
32 case XFER_UDMA_2: mode = 0x00a0; break;
33 case XFER_UDMA_1: mode = 0x0090; break;
34 case XFER_UDMA_0: mode = 0x0080; break;
35 case XFER_MW_DMA_2: mode = 0x0070; break;
36 case XFER_MW_DMA_1: mode = 0x0060; break;
37 case XFER_MW_DMA_0: mode = 0x0050; break;
38 case XFER_PIO_4: mode = 0x0400; break;
39 case XFER_PIO_3: mode = 0x0300; break;
40 case XFER_PIO_2: mode = 0x0200; break;
41 case XFER_PIO_1: mode = 0x0100; break;
42 case XFER_PIO_0:
43 default: mode = 0x0000; break;
44 }
45
46 scr &= (speed < XFER_MW_DMA_0) ? 0xf8ff : 0xff0f;
47 scr |= mode;
48 hwif->OUTW(scr, scr_port);
49
50 return ide_config_drive_speed(drive, speed);
51}
52
53static void tc86c001_tune_drive(ide_drive_t *drive, u8 pio)
54{
55 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
56 (void) tc86c001_tune_chipset(drive, XFER_PIO_0 + pio);
57}
58
59/*
60 * HACKITY HACK
61 *
62 * This is a workaround for the limitation 5 of the TC86C001 IDE controller:
63 * if a DMA transfer terminates prematurely, the controller leaves the device's
64 * interrupt request (INTRQ) pending and does not generate a PCI interrupt (or
65 * set the interrupt bit in the DMA status register), thus no PCI interrupt
66 * will occur until a DMA transfer has been successfully completed.
67 *
68 * We work around this by initiating dummy, zero-length DMA transfer on
69 * a DMA timeout expiration. I found no better way to do this with the current
70 * IDE core than to temporarily replace a higher level driver's timer expiry
71 * handler with our own backing up to that handler in case our recovery fails.
72 */
73static int tc86c001_timer_expiry(ide_drive_t *drive)
74{
75 ide_hwif_t *hwif = HWIF(drive);
76 ide_expiry_t *expiry = ide_get_hwifdata(hwif);
77 ide_hwgroup_t *hwgroup = HWGROUP(drive);
78 u8 dma_stat = hwif->INB(hwif->dma_status);
79
80 /* Restore a higher level driver's expiry handler first. */
81 hwgroup->expiry = expiry;
82
83 if ((dma_stat & 5) == 1) { /* DMA active and no interrupt */
84 unsigned long sc_base = hwif->config_data;
85 unsigned long twcr_port = sc_base + (drive->dn ? 0x06 : 0x04);
86 u8 dma_cmd = hwif->INB(hwif->dma_command);
87
88 printk(KERN_WARNING "%s: DMA interrupt possibly stuck, "
89 "attempting recovery...\n", drive->name);
90
91 /* Stop DMA */
92 hwif->OUTB(dma_cmd & ~0x01, hwif->dma_command);
93
94 /* Setup the dummy DMA transfer */
95 hwif->OUTW(0, sc_base + 0x0a); /* Sector Count */
96 hwif->OUTW(0, twcr_port); /* Transfer Word Count 1 or 2 */
97
98 /* Start the dummy DMA transfer */
99 hwif->OUTB(0x00, hwif->dma_command); /* clear R_OR_WCTR for write */
100 hwif->OUTB(0x01, hwif->dma_command); /* set START_STOPBM */
101
102 /*
103 * If an interrupt was pending, it should come thru shortly.
104 * If not, a higher level driver's expiry handler should
105 * eventually cause some kind of recovery from the DMA stall.
106 */
107 return WAIT_MIN_SLEEP;
108 }
109
110 /* Chain to the restored expiry handler if DMA wasn't active. */
111 if (likely(expiry != NULL))
112 return expiry(drive);
113
114 /* If there was no handler, "emulate" that for ide_timer_expiry()... */
115 return -1;
116}
117
118static void tc86c001_dma_start(ide_drive_t *drive)
119{
120 ide_hwif_t *hwif = HWIF(drive);
121 ide_hwgroup_t *hwgroup = HWGROUP(drive);
122 unsigned long sc_base = hwif->config_data;
123 unsigned long twcr_port = sc_base + (drive->dn ? 0x06 : 0x04);
124 unsigned long nsectors = hwgroup->rq->nr_sectors;
125
126 /*
127 * We have to manually load the sector count and size into
128 * the appropriate system control registers for DMA to work
129 * with LBA48 and ATAPI devices...
130 */
131 hwif->OUTW(nsectors, sc_base + 0x0a); /* Sector Count */
132 hwif->OUTW(SECTOR_SIZE / 2, twcr_port); /* Transfer Word Count 1/2 */
133
134 /* Install our timeout expiry hook, saving the current handler... */
135 ide_set_hwifdata(hwif, hwgroup->expiry);
136 hwgroup->expiry = &tc86c001_timer_expiry;
137
138 ide_dma_start(drive);
139}
140
141static int tc86c001_busproc(ide_drive_t *drive, int state)
142{
143 ide_hwif_t *hwif = HWIF(drive);
144 unsigned long sc_base = hwif->config_data;
145 u16 scr1;
146
147 /* System Control 1 Register bit 11 (ATA Hard Reset) read */
148 scr1 = hwif->INW(sc_base + 0x00);
149
150 switch (state) {
151 case BUSSTATE_ON:
152 if (!(scr1 & 0x0800))
153 return 0;
154 scr1 &= ~0x0800;
155
156 hwif->drives[0].failures = hwif->drives[1].failures = 0;
157 break;
158 case BUSSTATE_OFF:
159 if (scr1 & 0x0800)
160 return 0;
161 scr1 |= 0x0800;
162
163 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
164 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
165 break;
166 default:
167 return -EINVAL;
168 }
169
170 /* System Control 1 Register bit 11 (ATA Hard Reset) write */
171 hwif->OUTW(scr1, sc_base + 0x00);
172 return 0;
173}
174
175static int config_chipset_for_dma(ide_drive_t *drive)
176{
177 u8 speed = ide_dma_speed(drive, tc86c001_ratemask(drive));
178
179 if (!speed)
180 return 0;
181
182 (void) tc86c001_tune_chipset(drive, speed);
183 return ide_dma_enable(drive);
184}
185
186static int tc86c001_config_drive_xfer_rate(ide_drive_t *drive)
187{
188 ide_hwif_t *hwif = HWIF(drive);
189 struct hd_driveid *id = drive->id;
190
191 if ((id->capability & 1) && drive->autodma) {
192
193 if (ide_use_dma(drive) && config_chipset_for_dma(drive))
194 return hwif->ide_dma_on(drive);
195
196 goto fast_ata_pio;
197
198 } else if ((id->capability & 8) || (id->field_valid & 2)) {
199fast_ata_pio:
200 tc86c001_tune_drive(drive, 255);
201 return hwif->ide_dma_off_quietly(drive);
202 }
203 /* IORDY not supported */
204 return 0;
205}
206
207static void __devinit init_hwif_tc86c001(ide_hwif_t *hwif)
208{
209 unsigned long sc_base = pci_resource_start(hwif->pci_dev, 5);
210 u16 scr1 = hwif->INW(sc_base + 0x00);;
211
212 /* System Control 1 Register bit 15 (Soft Reset) set */
213 hwif->OUTW(scr1 | 0x8000, sc_base + 0x00);
214
215 /* System Control 1 Register bit 14 (FIFO Reset) set */
216 hwif->OUTW(scr1 | 0x4000, sc_base + 0x00);
217
218 /* System Control 1 Register: reset clear */
219 hwif->OUTW(scr1 & ~0xc000, sc_base + 0x00);
220
221 /* Store the system control register base for convenience... */
222 hwif->config_data = sc_base;
223
224 hwif->tuneproc = &tc86c001_tune_drive;
225 hwif->speedproc = &tc86c001_tune_chipset;
226 hwif->busproc = &tc86c001_busproc;
227
228 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
229
230 if (!hwif->dma_base)
231 return;
232
233 /*
234 * Sector Count Control Register bits 0 and 1 set:
235 * software sets Sector Count Register for master and slave device
236 */
237 hwif->OUTW(0x0003, sc_base + 0x0c);
238
239 /* Sector Count Register limit */
240 hwif->rqsize = 0xffff;
241
242 hwif->atapi_dma = 1;
243 hwif->ultra_mask = 0x1f;
244 hwif->mwdma_mask = 0x07;
245
246 hwif->ide_dma_check = &tc86c001_config_drive_xfer_rate;
247 hwif->dma_start = &tc86c001_dma_start;
248
249 if (!hwif->udma_four) {
250 /*
251 * System Control 1 Register bit 13 (PDIAGN):
252 * 0=80-pin cable, 1=40-pin cable
253 */
254 scr1 = hwif->INW(sc_base + 0x00);
255 hwif->udma_four = (scr1 & 0x2000) ? 0 : 1;
256 }
257
258 if (!noautodma)
259 hwif->autodma = 1;
260 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
261}
262
263static unsigned int __devinit init_chipset_tc86c001(struct pci_dev *dev,
264 const char *name)
265{
266 int err = pci_request_region(dev, 5, name);
267
268 if (err)
269 printk(KERN_ERR "%s: system control regs already in use", name);
270 return err;
271}
272
273static ide_pci_device_t tc86c001_chipset __devinitdata = {
274 .name = "TC86C001",
275 .init_chipset = init_chipset_tc86c001,
276 .init_hwif = init_hwif_tc86c001,
277 .channels = 1,
278 .autodma = AUTODMA,
279 .bootable = OFF_BOARD
280};
281
282static int __devinit tc86c001_init_one(struct pci_dev *dev,
283 const struct pci_device_id *id)
284{
285 return ide_setup_pci_device(dev, &tc86c001_chipset);
286}
287
288static struct pci_device_id tc86c001_pci_tbl[] = {
289 { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
290 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
291 { 0, }
292};
293MODULE_DEVICE_TABLE(pci, tc86c001_pci_tbl);
294
295static struct pci_driver driver = {
296 .name = "TC86C001",
297 .id_table = tc86c001_pci_tbl,
298 .probe = tc86c001_init_one
299};
300
301static int __init tc86c001_ide_init(void)
302{
303 return ide_pci_register_driver(&driver);
304}
305module_init(tc86c001_ide_init);
306
307MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
308MODULE_DESCRIPTION("PCI driver module for TC86C001 IDE");
309MODULE_LICENSE("GPL");
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 0d0ba2fad5fc..11217bda4b9e 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -1460,6 +1460,24 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1460DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1460DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1461DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1461DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1462 1462
1463/*
1464 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1465 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1466 * Re-allocate the region if needed...
1467 */
1468static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1469{
1470 struct resource *r = &dev->resource[0];
1471
1472 if (r->start & 0x8) {
1473 r->start = 0;
1474 r->end = 0xf;
1475 }
1476}
1477DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1478 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1479 quirk_tc86c001_ide);
1480
1463static void __devinit quirk_netmos(struct pci_dev *dev) 1481static void __devinit quirk_netmos(struct pci_dev *dev)
1464{ 1482{
1465 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1483 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
diff --git a/include/linux/ide.h b/include/linux/ide.h
index 827688f41d6c..04e0fa97ac99 100644
--- a/include/linux/ide.h
+++ b/include/linux/ide.h
@@ -18,6 +18,9 @@
18#include <linux/device.h> 18#include <linux/device.h>
19#include <linux/pci.h> 19#include <linux/pci.h>
20#include <linux/completion.h> 20#include <linux/completion.h>
21#ifdef CONFIG_BLK_DEV_IDEACPI
22#include <acpi/acpi.h>
23#endif
21#include <asm/byteorder.h> 24#include <asm/byteorder.h>
22#include <asm/system.h> 25#include <asm/system.h>
23#include <asm/io.h> 26#include <asm/io.h>
@@ -541,6 +544,11 @@ typedef enum {
541struct ide_driver_s; 544struct ide_driver_s;
542struct ide_settings_s; 545struct ide_settings_s;
543 546
547#ifdef CONFIG_BLK_DEV_IDEACPI
548struct ide_acpi_drive_link;
549struct ide_acpi_hwif_link;
550#endif
551
544typedef struct ide_drive_s { 552typedef struct ide_drive_s {
545 char name[4]; /* drive name, such as "hda" */ 553 char name[4]; /* drive name, such as "hda" */
546 char driver_req[10]; /* requests specific driver */ 554 char driver_req[10]; /* requests specific driver */
@@ -637,6 +645,9 @@ typedef struct ide_drive_s {
637 645
638 int lun; /* logical unit */ 646 int lun; /* logical unit */
639 int crc_count; /* crc counter to reduce drive speed */ 647 int crc_count; /* crc counter to reduce drive speed */
648#ifdef CONFIG_BLK_DEV_IDEACPI
649 struct ide_acpi_drive_link *acpidata;
650#endif
640 struct list_head list; 651 struct list_head list;
641 struct device gendev; 652 struct device gendev;
642 struct completion gendev_rel_comp; /* to deal with device release() */ 653 struct completion gendev_rel_comp; /* to deal with device release() */
@@ -804,6 +815,10 @@ typedef struct hwif_s {
804 void *hwif_data; /* extra hwif data */ 815 void *hwif_data; /* extra hwif data */
805 816
806 unsigned dma; 817 unsigned dma;
818
819#ifdef CONFIG_BLK_DEV_IDEACPI
820 struct ide_acpi_hwif_link *acpidata;
821#endif
807} ____cacheline_internodealigned_in_smp ide_hwif_t; 822} ____cacheline_internodealigned_in_smp ide_hwif_t;
808 823
809/* 824/*
@@ -1298,6 +1313,18 @@ static inline void ide_dma_verbose(ide_drive_t *drive) { ; }
1298static inline void ide_release_dma(ide_hwif_t *drive) {;} 1313static inline void ide_release_dma(ide_hwif_t *drive) {;}
1299#endif 1314#endif
1300 1315
1316#ifdef CONFIG_BLK_DEV_IDEACPI
1317extern int ide_acpi_exec_tfs(ide_drive_t *drive);
1318extern void ide_acpi_get_timing(ide_hwif_t *hwif);
1319extern void ide_acpi_push_timing(ide_hwif_t *hwif);
1320extern void ide_acpi_init(ide_hwif_t *hwif);
1321#else
1322static inline int ide_acpi_exec_tfs(ide_drive_t *drive) { return 0; }
1323static inline void ide_acpi_get_timing(ide_hwif_t *hwif) { ; }
1324static inline void ide_acpi_push_timing(ide_hwif_t *hwif) { ; }
1325static inline void ide_acpi_init(ide_hwif_t *hwif) { ; }
1326#endif
1327
1301extern int ide_hwif_request_regions(ide_hwif_t *hwif); 1328extern int ide_hwif_request_regions(ide_hwif_t *hwif);
1302extern void ide_hwif_release_regions(ide_hwif_t* hwif); 1329extern void ide_hwif_release_regions(ide_hwif_t* hwif);
1303extern void ide_unregister (unsigned int index); 1330extern void ide_unregister (unsigned int index);
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 5b4f1e3caf5d..defdeed20641 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1454,6 +1454,7 @@
1454 1454
1455#define PCI_VENDOR_ID_TOSHIBA_2 0x102f 1455#define PCI_VENDOR_ID_TOSHIBA_2 0x102f
1456#define PCI_DEVICE_ID_TOSHIBA_TC35815CF 0x0030 1456#define PCI_DEVICE_ID_TOSHIBA_TC35815CF 0x0030
1457#define PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE 0x0105
1457#define PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC 0x0108 1458#define PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC 0x0108
1458#define PCI_DEVICE_ID_TOSHIBA_SPIDER_NET 0x01b3 1459#define PCI_DEVICE_ID_TOSHIBA_SPIDER_NET 0x01b3
1459 1460
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 04:36:22 -0500