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authorSonic Zhang <sonic.zhang@analog.com>2008-02-06 04:38:20 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2008-02-06 13:41:11 -0500
commit13f3e642b24632d206fe2f6a5ee8b275ea062790 (patch)
tree39f2a7d7db8a68cb433fbc57aef2ce8c3ddd4c20
parent4fd432d9c7ac9a14e750d2ab0c91bc151e9af32e (diff)
spi_bfin: wait for tx to complete on write paths
SPI writes should also not return until the last bit is sent. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
-rw-r--r--drivers/spi/spi_bfin5xx.c22
1 files changed, 10 insertions, 12 deletions
diff --git a/drivers/spi/spi_bfin5xx.c b/drivers/spi/spi_bfin5xx.c
index f61b5eeb0427..7a4ace6dba55 100644
--- a/drivers/spi/spi_bfin5xx.c
+++ b/drivers/spi/spi_bfin5xx.c
@@ -278,16 +278,16 @@ static void u8_writer(struct driver_data *drv_data)
278 dev_dbg(&drv_data->pdev->dev, 278 dev_dbg(&drv_data->pdev->dev,
279 "cr8-s is 0x%x\n", read_STAT(drv_data)); 279 "cr8-s is 0x%x\n", read_STAT(drv_data));
280 280
281 /* poll for SPI completion before start */
282 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
283 cpu_relax();
284
285 while (drv_data->tx < drv_data->tx_end) { 281 while (drv_data->tx < drv_data->tx_end) {
286 write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); 282 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
287 while (read_STAT(drv_data) & BIT_STAT_TXS) 283 while (read_STAT(drv_data) & BIT_STAT_TXS)
288 cpu_relax(); 284 cpu_relax();
289 ++drv_data->tx; 285 ++drv_data->tx;
290 } 286 }
287
288 /* poll for SPI completion before return */
289 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
290 cpu_relax();
291} 291}
292 292
293static void u8_cs_chg_writer(struct driver_data *drv_data) 293static void u8_cs_chg_writer(struct driver_data *drv_data)
@@ -398,32 +398,30 @@ static void u16_writer(struct driver_data *drv_data)
398 dev_dbg(&drv_data->pdev->dev, 398 dev_dbg(&drv_data->pdev->dev,
399 "cr16 is 0x%x\n", read_STAT(drv_data)); 399 "cr16 is 0x%x\n", read_STAT(drv_data));
400 400
401 /* poll for SPI completion before start */
402 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
403 cpu_relax();
404
405 while (drv_data->tx < drv_data->tx_end) { 401 while (drv_data->tx < drv_data->tx_end) {
406 write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); 402 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
407 while ((read_STAT(drv_data) & BIT_STAT_TXS)) 403 while ((read_STAT(drv_data) & BIT_STAT_TXS))
408 cpu_relax(); 404 cpu_relax();
409 drv_data->tx += 2; 405 drv_data->tx += 2;
410 } 406 }
407
408 /* poll for SPI completion before return */
409 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
410 cpu_relax();
411} 411}
412 412
413static void u16_cs_chg_writer(struct driver_data *drv_data) 413static void u16_cs_chg_writer(struct driver_data *drv_data)
414{ 414{
415 struct chip_data *chip = drv_data->cur_chip; 415 struct chip_data *chip = drv_data->cur_chip;
416 416
417 /* poll for SPI completion before start */
418 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
419 cpu_relax();
420
421 while (drv_data->tx < drv_data->tx_end) { 417 while (drv_data->tx < drv_data->tx_end) {
422 cs_active(drv_data, chip); 418 cs_active(drv_data, chip);
423 419
424 write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); 420 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
425 while ((read_STAT(drv_data) & BIT_STAT_TXS)) 421 while ((read_STAT(drv_data) & BIT_STAT_TXS))
426 cpu_relax(); 422 cpu_relax();
423 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
424 cpu_relax();
427 425
428 cs_deactive(drv_data, chip); 426 cs_deactive(drv_data, chip);
429 427