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authorEric Miao <eric.miao@marvell.com>2008-09-08 03:26:43 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-10-07 14:12:56 -0400
commit87f3dd77974cba1ba0798abd741ede50f56b3eb3 (patch)
tree9f89bf77ac4ddc919a91b438d061849314ea5049
parentcbd18f8e3de62f91001963467ab6aad80a2a25ac (diff)
[ARM] pxa: simplify DMA register definitions
1. DRCMRxx is no longer recommended, use DRCMR(xx) instead, and pass DRCMR index by "struct resource" if possible 2. DCSRxx, DDADRxx, DSADRxx, DTADRxx, DCMDxx is never used, use DCSR(), DDADR(), DSADR(), DTADR(), DCMD() instead Signed-off-by: Eric Miao <eric.miao@marvell.com> Acked-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa-regs.h154
-rw-r--r--drivers/media/video/pxa_camera.c12
-rw-r--r--drivers/net/irda/pxaficp_ir.c8
-rw-r--r--sound/arm/pxa2xx-ac97.c4
-rw-r--r--sound/soc/pxa/pxa2xx-ac97.c10
-rw-r--r--sound/soc/pxa/pxa2xx-i2s.c4
6 files changed, 19 insertions, 173 deletions
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h
index f842fd3d39a2..4cac9269fdf2 100644
--- a/arch/arm/mach-pxa/include/mach/pxa-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h
@@ -69,24 +69,6 @@
69/* 69/*
70 * DMA Controller 70 * DMA Controller
71 */ 71 */
72
73#define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */
74#define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */
75#define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */
76#define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */
77#define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */
78#define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */
79#define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */
80#define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */
81#define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */
82#define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */
83#define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */
84#define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */
85#define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */
86#define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */
87#define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */
88#define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */
89
90#define DCSR(x) __REG2(0x40000000, (x) << 2) 72#define DCSR(x) __REG2(0x40000000, (x) << 2)
91 73
92#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ 74#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
@@ -115,145 +97,9 @@
115 &__REG2(0x40000100, ((n) & 0x3f) << 2) : \ 97 &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
116 &__REG2(0x40001100, ((n) & 0x3f) << 2))) 98 &__REG2(0x40001100, ((n) & 0x3f) << 2)))
117 99
118#define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
119#define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
120#define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */
121#define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */
122#define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */
123#define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */
124#define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */
125#define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */
126#define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */
127#define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */
128#define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */
129#define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */
130#define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */
131#define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */
132#define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */
133#define DRCMR15 __REG(0x4000013c) /* Request to Channel Map Register for SSP2 receive Request */
134#define DRCMR16 __REG(0x40000140) /* Request to Channel Map Register for SSP2 transmit Request */
135#define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */
136#define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */
137#define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */
138#define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */
139#define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */
140#define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */
141#define DRCMR23 __REG(0x4000015c) /* Reserved */
142#define DRCMR24 __REG(0x40000160) /* Reserved */
143#define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */
144#define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */
145#define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */
146#define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */
147#define DRCMR29 __REG(0x40000174) /* Reserved */
148#define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */
149#define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */
150#define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */
151#define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */
152#define DRCMR34 __REG(0x40000188) /* Reserved */
153#define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */
154#define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */
155#define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */
156#define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
157#define DRCMR39 __REG(0x4000019C) /* Reserved */
158#define DRCMR66 __REG(0x40001108) /* Request to Channel Map Register for SSP3 receive Request */
159#define DRCMR67 __REG(0x4000110C) /* Request to Channel Map Register for SSP3 transmit Request */
160#define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */
161#define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */
162#define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */
163
164#define DRCMRRXSADR DRCMR2
165#define DRCMRTXSADR DRCMR3
166#define DRCMRRXBTRBR DRCMR4
167#define DRCMRTXBTTHR DRCMR5
168#define DRCMRRXFFRBR DRCMR6
169#define DRCMRTXFFTHR DRCMR7
170#define DRCMRRXMCDR DRCMR8
171#define DRCMRRXMODR DRCMR9
172#define DRCMRTXMODR DRCMR10
173#define DRCMRRXPCDR DRCMR11
174#define DRCMRTXPCDR DRCMR12
175#define DRCMRRXSSDR DRCMR13
176#define DRCMRTXSSDR DRCMR14
177#define DRCMRRXSS2DR DRCMR15
178#define DRCMRTXSS2DR DRCMR16
179#define DRCMRRXICDR DRCMR17
180#define DRCMRTXICDR DRCMR18
181#define DRCMRRXSTRBR DRCMR19
182#define DRCMRTXSTTHR DRCMR20
183#define DRCMRRXMMC DRCMR21
184#define DRCMRTXMMC DRCMR22
185#define DRCMRRXSS3DR DRCMR66
186#define DRCMRTXSS3DR DRCMR67
187#define DRCMRUDC(x) DRCMR((x) + 24)
188
189#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ 100#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
190#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ 101#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
191 102
192#define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */
193#define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */
194#define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */
195#define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */
196#define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */
197#define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */
198#define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */
199#define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */
200#define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */
201#define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */
202#define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */
203#define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */
204#define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */
205#define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */
206#define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */
207#define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */
208#define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */
209#define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */
210#define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */
211#define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */
212#define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */
213#define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */
214#define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */
215#define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */
216#define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */
217#define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */
218#define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */
219#define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */
220#define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */
221#define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */
222#define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */
223#define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */
224#define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */
225#define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */
226#define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */
227#define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */
228#define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */
229#define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */
230#define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */
231#define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */
232#define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */
233#define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */
234#define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */
235#define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */
236#define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */
237#define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */
238#define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */
239#define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */
240#define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */
241#define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */
242#define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */
243#define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */
244#define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */
245#define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */
246#define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */
247#define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */
248#define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */
249#define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */
250#define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */
251#define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */
252#define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */
253#define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */
254#define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */
255#define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */
256
257#define DDADR(x) __REG2(0x40000200, (x) << 4) 103#define DDADR(x) __REG2(0x40000200, (x) << 4)
258#define DSADR(x) __REG2(0x40000204, (x) << 4) 104#define DSADR(x) __REG2(0x40000204, (x) << 4)
259#define DTADR(x) __REG2(0x40000208, (x) << 4) 105#define DTADR(x) __REG2(0x40000208, (x) << 4)
diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c
index 388cf94055d3..cf96b2cc4f1c 100644
--- a/drivers/media/video/pxa_camera.c
+++ b/drivers/media/video/pxa_camera.c
@@ -1025,9 +1025,9 @@ static int pxa_camera_resume(struct soc_camera_device *icd)
1025 struct pxa_camera_dev *pcdev = ici->priv; 1025 struct pxa_camera_dev *pcdev = ici->priv;
1026 int i = 0, ret = 0; 1026 int i = 0, ret = 0;
1027 1027
1028 DRCMR68 = pcdev->dma_chans[0] | DRCMR_MAPVLD; 1028 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1029 DRCMR69 = pcdev->dma_chans[1] | DRCMR_MAPVLD; 1029 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1030 DRCMR70 = pcdev->dma_chans[2] | DRCMR_MAPVLD; 1030 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1031 1031
1032 CICR0 = pcdev->save_cicr[i++] & ~CICR0_ENB; 1032 CICR0 = pcdev->save_cicr[i++] & ~CICR0_ENB;
1033 CICR1 = pcdev->save_cicr[i++]; 1033 CICR1 = pcdev->save_cicr[i++];
@@ -1171,9 +1171,9 @@ static int pxa_camera_probe(struct platform_device *pdev)
1171 } 1171 }
1172 dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]); 1172 dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1173 1173
1174 DRCMR68 = pcdev->dma_chans[0] | DRCMR_MAPVLD; 1174 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1175 DRCMR69 = pcdev->dma_chans[1] | DRCMR_MAPVLD; 1175 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1176 DRCMR70 = pcdev->dma_chans[2] | DRCMR_MAPVLD; 1176 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1177 1177
1178 /* request irq */ 1178 /* request irq */
1179 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME, 1179 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c
index 4aa61a1a3d55..c5b02b66f756 100644
--- a/drivers/net/irda/pxaficp_ir.c
+++ b/drivers/net/irda/pxaficp_ir.c
@@ -572,8 +572,8 @@ static void pxa_irda_startup(struct pxa_irda *si)
572 ICCR2 = ICCR2_TXP | ICCR2_TRIG_32; 572 ICCR2 = ICCR2_TXP | ICCR2_TRIG_32;
573 573
574 /* configure DMAC */ 574 /* configure DMAC */
575 DRCMR17 = si->rxdma | DRCMR_MAPVLD; 575 DRCMR(17) = si->rxdma | DRCMR_MAPVLD;
576 DRCMR18 = si->txdma | DRCMR_MAPVLD; 576 DRCMR(18) = si->txdma | DRCMR_MAPVLD;
577 577
578 /* force SIR reinitialization */ 578 /* force SIR reinitialization */
579 si->speed = 4000000; 579 si->speed = 4000000;
@@ -602,8 +602,8 @@ static void pxa_irda_shutdown(struct pxa_irda *si)
602 /* disable the STUART or FICP clocks */ 602 /* disable the STUART or FICP clocks */
603 pxa_irda_disable_clk(si); 603 pxa_irda_disable_clk(si);
604 604
605 DRCMR17 = 0; 605 DRCMR(17) = 0;
606 DRCMR18 = 0; 606 DRCMR(18) = 0;
607 607
608 local_irq_restore(flags); 608 local_irq_restore(flags);
609 609
diff --git a/sound/arm/pxa2xx-ac97.c b/sound/arm/pxa2xx-ac97.c
index 199cca3366df..714b3baa4be7 100644
--- a/sound/arm/pxa2xx-ac97.c
+++ b/sound/arm/pxa2xx-ac97.c
@@ -215,7 +215,7 @@ static struct snd_ac97_bus_ops pxa2xx_ac97_ops = {
215static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_out = { 215static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_out = {
216 .name = "AC97 PCM out", 216 .name = "AC97 PCM out",
217 .dev_addr = __PREG(PCDR), 217 .dev_addr = __PREG(PCDR),
218 .drcmr = &DRCMRTXPCDR, 218 .drcmr = &DRCMR(12),
219 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | 219 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
220 DCMD_BURST32 | DCMD_WIDTH4, 220 DCMD_BURST32 | DCMD_WIDTH4,
221}; 221};
@@ -223,7 +223,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_out = {
223static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_in = { 223static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_in = {
224 .name = "AC97 PCM in", 224 .name = "AC97 PCM in",
225 .dev_addr = __PREG(PCDR), 225 .dev_addr = __PREG(PCDR),
226 .drcmr = &DRCMRRXPCDR, 226 .drcmr = &DRCMR(11),
227 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | 227 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
228 DCMD_BURST32 | DCMD_WIDTH4, 228 DCMD_BURST32 | DCMD_WIDTH4,
229}; 229};
diff --git a/sound/soc/pxa/pxa2xx-ac97.c b/sound/soc/pxa/pxa2xx-ac97.c
index 7d7ce1648361..ac8f227bab0b 100644
--- a/sound/soc/pxa/pxa2xx-ac97.c
+++ b/sound/soc/pxa/pxa2xx-ac97.c
@@ -244,7 +244,7 @@ struct snd_ac97_bus_ops soc_ac97_ops = {
244static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_out = { 244static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_out = {
245 .name = "AC97 PCM Stereo out", 245 .name = "AC97 PCM Stereo out",
246 .dev_addr = __PREG(PCDR), 246 .dev_addr = __PREG(PCDR),
247 .drcmr = &DRCMRTXPCDR, 247 .drcmr = &DRCMR(12),
248 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | 248 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
249 DCMD_BURST32 | DCMD_WIDTH4, 249 DCMD_BURST32 | DCMD_WIDTH4,
250}; 250};
@@ -252,7 +252,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_out = {
252static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_in = { 252static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_in = {
253 .name = "AC97 PCM Stereo in", 253 .name = "AC97 PCM Stereo in",
254 .dev_addr = __PREG(PCDR), 254 .dev_addr = __PREG(PCDR),
255 .drcmr = &DRCMRRXPCDR, 255 .drcmr = &DRCMR(11),
256 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | 256 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
257 DCMD_BURST32 | DCMD_WIDTH4, 257 DCMD_BURST32 | DCMD_WIDTH4,
258}; 258};
@@ -260,7 +260,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_in = {
260static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_out = { 260static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_out = {
261 .name = "AC97 Aux PCM (Slot 5) Mono out", 261 .name = "AC97 Aux PCM (Slot 5) Mono out",
262 .dev_addr = __PREG(MODR), 262 .dev_addr = __PREG(MODR),
263 .drcmr = &DRCMRTXMODR, 263 .drcmr = &DRCMR(10),
264 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | 264 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
265 DCMD_BURST16 | DCMD_WIDTH2, 265 DCMD_BURST16 | DCMD_WIDTH2,
266}; 266};
@@ -268,7 +268,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_out = {
268static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_in = { 268static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_in = {
269 .name = "AC97 Aux PCM (Slot 5) Mono in", 269 .name = "AC97 Aux PCM (Slot 5) Mono in",
270 .dev_addr = __PREG(MODR), 270 .dev_addr = __PREG(MODR),
271 .drcmr = &DRCMRRXMODR, 271 .drcmr = &DRCMR(9),
272 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | 272 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
273 DCMD_BURST16 | DCMD_WIDTH2, 273 DCMD_BURST16 | DCMD_WIDTH2,
274}; 274};
@@ -276,7 +276,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_in = {
276static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_mic_mono_in = { 276static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_mic_mono_in = {
277 .name = "AC97 Mic PCM (Slot 6) Mono in", 277 .name = "AC97 Mic PCM (Slot 6) Mono in",
278 .dev_addr = __PREG(MCDR), 278 .dev_addr = __PREG(MCDR),
279 .drcmr = &DRCMRRXMCDR, 279 .drcmr = &DRCMR(8),
280 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | 280 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
281 DCMD_BURST16 | DCMD_WIDTH2, 281 DCMD_BURST16 | DCMD_WIDTH2,
282}; 282};
diff --git a/sound/soc/pxa/pxa2xx-i2s.c b/sound/soc/pxa/pxa2xx-i2s.c
index c796b1882776..2dbe612fdddc 100644
--- a/sound/soc/pxa/pxa2xx-i2s.c
+++ b/sound/soc/pxa/pxa2xx-i2s.c
@@ -44,7 +44,7 @@ static struct clk *clk_i2s;
44static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = { 44static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
45 .name = "I2S PCM Stereo out", 45 .name = "I2S PCM Stereo out",
46 .dev_addr = __PREG(SADR), 46 .dev_addr = __PREG(SADR),
47 .drcmr = &DRCMRTXSADR, 47 .drcmr = &DRCMR(3),
48 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | 48 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
49 DCMD_BURST32 | DCMD_WIDTH4, 49 DCMD_BURST32 | DCMD_WIDTH4,
50}; 50};
@@ -52,7 +52,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
52static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = { 52static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
53 .name = "I2S PCM Stereo in", 53 .name = "I2S PCM Stereo in",
54 .dev_addr = __PREG(SADR), 54 .dev_addr = __PREG(SADR),
55 .drcmr = &DRCMRRXSADR, 55 .drcmr = &DRCMR(2),
56 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | 56 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
57 DCMD_BURST32 | DCMD_WIDTH4, 57 DCMD_BURST32 | DCMD_WIDTH4,
58}; 58};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 12:21:19 -0500