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authorDon Skidmore <donald.c.skidmore@intel.com>2009-01-19 19:54:13 -0500
committerDavid S. Miller <davem@davemloft.net>2009-01-19 19:54:13 -0500
commit15005a320473b8d3676b878deb29bbe738ef9027 (patch)
treee451ad3d95824833b09bd45bf6b7ea8f2e3f0a30
parent67fd1a731ff1a990d4da7689909317756e50cb4d (diff)
ixgbe: fix dca issue with relaxed ordering turned on
The is an issue where setting Relaxed Ordering (RO) bit (in a PCI-E write transaction) on 82598 causing the chipset to drop DCA hints. This patch forces RO not to be set for descriptors as well as payload. This will only be in effect while DCA is enabled and no performance difference was noticed in testing. Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c3
-rw-r--r--drivers/net/ixgbe/ixgbe_type.h3
2 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index acef3c65cd2c..92d9b17a081a 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -318,6 +318,9 @@ static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
318 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); 318 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
319 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; 319 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
320 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; 320 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
321 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
322 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
323 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
321 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl); 324 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
322 rx_ring->cpu = cpu; 325 rx_ring->cpu = cpu;
323 } 326 }
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index 83a11ff9ffd1..f011c57c9205 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -404,6 +404,9 @@
404#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 404#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
405#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ 405#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
406#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ 406#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
407#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
408#define IXGBE_DCA_RXCTRL_DESC_WRO_EN (1 << 13) /* DCA Rx wr Desc Relax Order */
409#define IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15) /* DCA Rx Split Header RO */
407 410
408#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 411#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
409#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 412#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */