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authorJohannes Stezenbach <js@linuxtv.org>2006-01-09 12:25:08 -0500
committerMauro Carvalho Chehab <mchehab@brturbo.com.br>2006-01-09 12:25:08 -0500
commite3b152bc9ee2b7f841565dc93a042f527cf3116c (patch)
tree5b3ab8aaa19993a293ee60954b05fce0a5b138f1
parentb79cb6531d5ba9174f9677ce2213c017d1e2ef19 (diff)
DVB (2446): Minor cleanups.
- Minor cleanups. Signed-off-by: Johannes Stezenbach <js@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@brturbo.com.br>
-rw-r--r--drivers/media/dvb/frontends/cx24123.c238
-rw-r--r--drivers/media/dvb/frontends/cx24123.h143
2 files changed, 192 insertions, 189 deletions
diff --git a/drivers/media/dvb/frontends/cx24123.c b/drivers/media/dvb/frontends/cx24123.c
index 0061c7793436..cfb7d2edd5a9 100644
--- a/drivers/media/dvb/frontends/cx24123.c
+++ b/drivers/media/dvb/frontends/cx24123.c
@@ -33,8 +33,8 @@ static int debug;
33 if (debug) printk (KERN_DEBUG "cx24123: " args); \ 33 if (debug) printk (KERN_DEBUG "cx24123: " args); \
34 } while (0) 34 } while (0)
35 35
36struct cx24123_state { 36struct cx24123_state
37 37{
38 struct i2c_adapter* i2c; 38 struct i2c_adapter* i2c;
39 struct dvb_frontend_ops ops; 39 struct dvb_frontend_ops ops;
40 const struct cx24123_config* config; 40 const struct cx24123_config* config;
@@ -56,6 +56,148 @@ struct cx24123_state {
56 u32 currentsymbolrate; 56 u32 currentsymbolrate;
57}; 57};
58 58
59/* Various tuner defaults need to be established for a given symbol rate Sps */
60static struct
61{
62 u32 symbolrate_low;
63 u32 symbolrate_high;
64 u32 VCAslope;
65 u32 VCAoffset;
66 u32 VGA1offset;
67 u32 VGA2offset;
68 u32 VCAprogdata;
69 u32 VGAprogdata;
70} cx24123_AGC_vals[] =
71{
72 {
73 .symbolrate_low = 1000000,
74 .symbolrate_high = 4999999,
75 .VCAslope = 0x07,
76 .VCAoffset = 0x0f,
77 .VGA1offset = 0x1f8,
78 .VGA2offset = 0x1f8,
79 .VGAprogdata = (2 << 18) | (0x1f8 << 9) | 0x1f8,
80 .VCAprogdata = (4 << 18) | (0x07 << 9) | 0x07,
81 },
82 {
83 .symbolrate_low = 5000000,
84 .symbolrate_high = 14999999,
85 .VCAslope = 0x1f,
86 .VCAoffset = 0x1f,
87 .VGA1offset = 0x1e0,
88 .VGA2offset = 0x180,
89 .VGAprogdata = (2 << 18) | (0x180 << 9) | 0x1e0,
90 .VCAprogdata = (4 << 18) | (0x07 << 9) | 0x1f,
91 },
92 {
93 .symbolrate_low = 15000000,
94 .symbolrate_high = 45000000,
95 .VCAslope = 0x3f,
96 .VCAoffset = 0x3f,
97 .VGA1offset = 0x180,
98 .VGA2offset = 0x100,
99 .VGAprogdata = (2 << 18) | (0x100 << 9) | 0x180,
100 .VCAprogdata = (4 << 18) | (0x07 << 9) | 0x3f,
101 },
102};
103
104/*
105 * Various tuner defaults need to be established for a given frequency kHz.
106 * fixme: The bounds on the bands do not match the doc in real life.
107 * fixme: Some of them have been moved, other might need adjustment.
108 */
109static struct
110{
111 u32 freq_low;
112 u32 freq_high;
113 u32 bandselect;
114 u32 VCOdivider;
115 u32 VCOnumber;
116 u32 progdata;
117} cx24123_bandselect_vals[] =
118{
119 {
120 .freq_low = 950000,
121 .freq_high = 1018999,
122 .bandselect = 0x40,
123 .VCOdivider = 4,
124 .VCOnumber = 7,
125 .progdata = (0 << 18) | (0 << 9) | 0x40,
126 },
127 {
128 .freq_low = 1019000,
129 .freq_high = 1074999,
130 .bandselect = 0x80,
131 .VCOdivider = 4,
132 .VCOnumber = 8,
133 .progdata = (0 << 18) | (0 << 9) | 0x80,
134 },
135 {
136 .freq_low = 1075000,
137 .freq_high = 1227999,
138 .bandselect = 0x01,
139 .VCOdivider = 2,
140 .VCOnumber = 1,
141 .progdata = (0 << 18) | (1 << 9) | 0x01,
142 },
143 {
144 .freq_low = 1228000,
145 .freq_high = 1349999,
146 .bandselect = 0x02,
147 .VCOdivider = 2,
148 .VCOnumber = 2,
149 .progdata = (0 << 18) | (1 << 9) | 0x02,
150 },
151 {
152 .freq_low = 1350000,
153 .freq_high = 1481999,
154 .bandselect = 0x04,
155 .VCOdivider = 2,
156 .VCOnumber = 3,
157 .progdata = (0 << 18) | (1 << 9) | 0x04,
158 },
159 {
160 .freq_low = 1482000,
161 .freq_high = 1595999,
162 .bandselect = 0x08,
163 .VCOdivider = 2,
164 .VCOnumber = 4,
165 .progdata = (0 << 18) | (1 << 9) | 0x08,
166 },
167 {
168 .freq_low = 1596000,
169 .freq_high = 1717999,
170 .bandselect = 0x10,
171 .VCOdivider = 2,
172 .VCOnumber = 5,
173 .progdata = (0 << 18) | (1 << 9) | 0x10,
174 },
175 {
176 .freq_low = 1718000,
177 .freq_high = 1855999,
178 .bandselect = 0x20,
179 .VCOdivider = 2,
180 .VCOnumber = 6,
181 .progdata = (0 << 18) | (1 << 9) | 0x20,
182 },
183 {
184 .freq_low = 1856000,
185 .freq_high = 2035999,
186 .bandselect = 0x40,
187 .VCOdivider = 2,
188 .VCOnumber = 7,
189 .progdata = (0 << 18) | (1 << 9) | 0x40,
190 },
191 {
192 .freq_low = 2036000,
193 .freq_high = 2149999,
194 .bandselect = 0x80,
195 .VCOdivider = 2,
196 .VCOnumber = 8,
197 .progdata = (0 << 18) | (1 << 9) | 0x80,
198 },
199};
200
59static struct { 201static struct {
60 u8 reg; 202 u8 reg;
61 u8 data; 203 u8 data;
@@ -195,9 +337,9 @@ static int cx24123_get_inversion(struct cx24123_state* state, fe_spectral_invers
195 val = cx24123_readreg(state, 0x1b) >> 7; 337 val = cx24123_readreg(state, 0x1b) >> 7;
196 338
197 if (val == 0) 339 if (val == 0)
198 *inversion=INVERSION_OFF; 340 *inversion = INVERSION_OFF;
199 else 341 else
200 *inversion=INVERSION_ON; 342 *inversion = INVERSION_ON;
201 343
202 return 0; 344 return 0;
203} 345}
@@ -205,12 +347,12 @@ static int cx24123_get_inversion(struct cx24123_state* state, fe_spectral_invers
205static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec) 347static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec)
206{ 348{
207 if ( (fec < FEC_NONE) || (fec > FEC_AUTO) ) 349 if ( (fec < FEC_NONE) || (fec > FEC_AUTO) )
208 fec=FEC_AUTO; 350 fec = FEC_AUTO;
209 351
210 /* Hardware has 5/11 and 3/5 but are never unused */ 352 /* Hardware has 5/11 and 3/5 but are never unused */
211 switch (fec) { 353 switch (fec) {
212 case FEC_NONE: 354 case FEC_NONE:
213 return cx24123_writereg(state, 0x0f,0x01); 355 return cx24123_writereg(state, 0x0f, 0x01);
214 case FEC_1_2: 356 case FEC_1_2:
215 return cx24123_writereg(state, 0x0f, 0x02); 357 return cx24123_writereg(state, 0x0f, 0x02);
216 case FEC_2_3: 358 case FEC_2_3:
@@ -230,37 +372,41 @@ static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec)
230 372
231static int cx24123_get_fec(struct cx24123_state* state, fe_code_rate_t *fec) 373static int cx24123_get_fec(struct cx24123_state* state, fe_code_rate_t *fec)
232{ 374{
375 int ret;
233 u8 val; 376 u8 val;
234 377
235 val = cx24123_readreg (state, 0x1b) & 0x07; 378 ret = cx24123_readreg (state, 0x1b);
379 if (ret < 0)
380 return ret;
381 val = ret & 0x07;
236 switch (val) { 382 switch (val) {
237 case 1: 383 case 1:
238 *fec=FEC_1_2; 384 *fec = FEC_1_2;
239 return 0; 385 break;
240 case 3: 386 case 3:
241 *fec=FEC_2_3; 387 *fec = FEC_2_3;
242 return 0; 388 break;
243 case 4: 389 case 4:
244 *fec=FEC_3_4; 390 *fec = FEC_3_4;
245 return 0; 391 break;
246 case 5: 392 case 5:
247 *fec=FEC_4_5; 393 *fec = FEC_4_5;
248 return 0; 394 break;
249 case 6: 395 case 6:
250 *fec=FEC_5_6; 396 *fec = FEC_5_6;
251 return 0; 397 break;
252 case 7: 398 case 7:
253 *fec=FEC_7_8; 399 *fec = FEC_7_8;
254 return 0; 400 break;
255 case 2: /* *fec=FEC_3_5; return 0; */ 401 case 2: /* *fec = FEC_3_5; break; */
256 case 0: /* *fec=FEC_5_11; return 0; */ 402 case 0: /* *fec = FEC_5_11; break; */
257 *fec=FEC_AUTO; 403 *fec = FEC_AUTO;
258 return 0; 404 break;
259 default: 405 default:
260 *fec=FEC_NONE; return 0; 406 *fec = FEC_NONE; // can't happen
261 } 407 }
262 408
263 return -EREMOTEIO; 409 return 0;
264} 410}
265 411
266/* fixme: Symbol rates < 3MSps may not work because of precision loss */ 412/* fixme: Symbol rates < 3MSps may not work because of precision loss */
@@ -268,14 +414,14 @@ static int cx24123_set_symbolrate(struct cx24123_state* state, u32 srate)
268{ 414{
269 u32 val; 415 u32 val;
270 416
271 val = (srate/1185)*100; 417 val = (srate / 1185) * 100;
272 418
273 /* Compensate for scaling up, by removing 17 symbols per 1Msps */ 419 /* Compensate for scaling up, by removing 17 symbols per 1Msps */
274 val = val - (17*(srate / 1000000)); 420 val = val - (17 * (srate / 1000000));
275 421
276 cx24123_writereg(state, 0x08, (val >>16) & 0xff ); 422 cx24123_writereg(state, 0x08, (val >> 16) & 0xff );
277 cx24123_writereg(state, 0x09, (val >> 8) & 0xff ); 423 cx24123_writereg(state, 0x09, (val >> 8) & 0xff );
278 cx24123_writereg(state, 0x0a, (val ) & 0xff ); 424 cx24123_writereg(state, 0x0a, (val ) & 0xff );
279 425
280 return 0; 426 return 0;
281} 427}
@@ -287,8 +433,8 @@ static int cx24123_set_symbolrate(struct cx24123_state* state, u32 srate)
287static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 433static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
288{ 434{
289 struct cx24123_state *state = fe->demodulator_priv; 435 struct cx24123_state *state = fe->demodulator_priv;
290 u32 ndiv=0, adiv=0, vco_div=0; 436 u32 ndiv = 0, adiv = 0, vco_div = 0;
291 int i=0; 437 int i = 0;
292 438
293 /* Defaults for low freq, low rate */ 439 /* Defaults for low freq, low rate */
294 state->VCAarg = cx24123_AGC_vals[0].VCAprogdata; 440 state->VCAarg = cx24123_AGC_vals[0].VCAprogdata;
@@ -297,7 +443,7 @@ static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_pa
297 vco_div = cx24123_bandselect_vals[0].VCOdivider; 443 vco_div = cx24123_bandselect_vals[0].VCOdivider;
298 444
299 /* For the given symbolerate, determine the VCA and VGA programming bits */ 445 /* For the given symbolerate, determine the VCA and VGA programming bits */
300 for (i=0; i < sizeof(cx24123_AGC_vals) / sizeof(cx24123_AGC_vals[0]); i++) 446 for (i = 0; i < sizeof(cx24123_AGC_vals) / sizeof(cx24123_AGC_vals[0]); i++)
301 { 447 {
302 if ((cx24123_AGC_vals[i].symbolrate_low <= p->u.qpsk.symbol_rate) && 448 if ((cx24123_AGC_vals[i].symbolrate_low <= p->u.qpsk.symbol_rate) &&
303 (cx24123_AGC_vals[i].symbolrate_high >= p->u.qpsk.symbol_rate) ) { 449 (cx24123_AGC_vals[i].symbolrate_high >= p->u.qpsk.symbol_rate) ) {
@@ -307,7 +453,7 @@ static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_pa
307 } 453 }
308 454
309 /* For the given frequency, determine the bandselect programming bits */ 455 /* For the given frequency, determine the bandselect programming bits */
310 for (i=0; i < sizeof(cx24123_bandselect_vals) / sizeof(cx24123_bandselect_vals[0]); i++) 456 for (i = 0; i < sizeof(cx24123_bandselect_vals) / sizeof(cx24123_bandselect_vals[0]); i++)
311 { 457 {
312 if ((cx24123_bandselect_vals[i].freq_low <= p->frequency) && 458 if ((cx24123_bandselect_vals[i].freq_low <= p->frequency) &&
313 (cx24123_bandselect_vals[i].freq_high >= p->frequency) ) { 459 (cx24123_bandselect_vals[i].freq_high >= p->frequency) ) {
@@ -340,7 +486,7 @@ static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_par
340{ 486{
341 struct cx24123_state *state = fe->demodulator_priv; 487 struct cx24123_state *state = fe->demodulator_priv;
342 488
343 u8 timeout=0; 489 u8 timeout = 0;
344 490
345 /* align the 21 bytes into to bit23 boundary */ 491 /* align the 21 bytes into to bit23 boundary */
346 data = data << 3; 492 data = data << 3;
@@ -348,9 +494,9 @@ static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_par
348 /* Reset the demod pll word length to 0x15 bits */ 494 /* Reset the demod pll word length to 0x15 bits */
349 cx24123_writereg(state, 0x21, 0x15); 495 cx24123_writereg(state, 0x21, 0x15);
350 496
351 timeout=0; 497 timeout = 0;
352 /* write the msb 8 bits, wait for the send to be completed */ 498 /* write the msb 8 bits, wait for the send to be completed */
353 cx24123_writereg(state, 0x22, (data>>16) & 0xff); 499 cx24123_writereg(state, 0x22, (data >> 16) & 0xff);
354 while ( ( cx24123_readreg(state, 0x20) & 0x40 ) == 0 ) 500 while ( ( cx24123_readreg(state, 0x20) & 0x40 ) == 0 )
355 { 501 {
356 /* Safety - No reason why the write should not complete, and we never get here, avoid hang */ 502 /* Safety - No reason why the write should not complete, and we never get here, avoid hang */
@@ -361,7 +507,7 @@ static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_par
361 msleep(500); 507 msleep(500);
362 } 508 }
363 509
364 timeout=0; 510 timeout = 0;
365 /* send another 8 bytes, wait for the send to be completed */ 511 /* send another 8 bytes, wait for the send to be completed */
366 cx24123_writereg(state, 0x22, (data>>8) & 0xff ); 512 cx24123_writereg(state, 0x22, (data>>8) & 0xff );
367 while ( (cx24123_readreg(state, 0x20) & 0x40 ) == 0 ) 513 while ( (cx24123_readreg(state, 0x20) & 0x40 ) == 0 )
@@ -374,7 +520,7 @@ static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_par
374 msleep(500); 520 msleep(500);
375 } 521 }
376 522
377 timeout=0; 523 timeout = 0;
378 /* send the lower 5 bits of this byte, padded with 3 LBB, wait for the send to be completed */ 524 /* send the lower 5 bits of this byte, padded with 3 LBB, wait for the send to be completed */
379 cx24123_writereg(state, 0x22, (data) & 0xff ); 525 cx24123_writereg(state, 0x22, (data) & 0xff );
380 while ((cx24123_readreg(state, 0x20) & 0x80)) 526 while ((cx24123_readreg(state, 0x20) & 0x80))
@@ -398,7 +544,7 @@ static int cx24123_pll_tune(struct dvb_frontend* fe, struct dvb_frontend_paramet
398{ 544{
399 struct cx24123_state *state = fe->demodulator_priv; 545 struct cx24123_state *state = fe->demodulator_priv;
400 546
401 if (cx24123_pll_calculate(fe, p)!=0) { 547 if (cx24123_pll_calculate(fe, p) != 0) {
402 printk("%s: cx24123_pll_calcutate failed\n",__FUNCTION__); 548 printk("%s: cx24123_pll_calcutate failed\n",__FUNCTION__);
403 return -EINVAL; 549 return -EINVAL;
404 } 550 }
@@ -420,7 +566,7 @@ static int cx24123_initfe(struct dvb_frontend* fe)
420 int i; 566 int i;
421 567
422 /* Configure the demod to a good set of defaults */ 568 /* Configure the demod to a good set of defaults */
423 for (i=0; i < sizeof(cx24123_regdata) / sizeof(cx24123_regdata[0]); i++) 569 for (i = 0; i < sizeof(cx24123_regdata) / sizeof(cx24123_regdata[0]); i++)
424 cx24123_writereg(state, cx24123_regdata[i].reg, cx24123_regdata[i].data); 570 cx24123_writereg(state, cx24123_regdata[i].reg, cx24123_regdata[i].data);
425 571
426 if (state->config->pll_init) 572 if (state->config->pll_init)
@@ -452,7 +598,7 @@ static int cx24123_set_voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage
452} 598}
453 599
454static int cx24123_send_diseqc_msg(struct dvb_frontend* fe, 600static int cx24123_send_diseqc_msg(struct dvb_frontend* fe,
455 struct dvb_diseqc_master_cmd *cmd) 601 struct dvb_diseqc_master_cmd *cmd)
456{ 602{
457 /* fixme: Implement diseqc */ 603 /* fixme: Implement diseqc */
458 printk("%s: No support yet\n",__FUNCTION__); 604 printk("%s: No support yet\n",__FUNCTION__);
@@ -545,7 +691,7 @@ static int cx24123_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_par
545 state->config->set_ts_params(fe, 0); 691 state->config->set_ts_params(fe, 0);
546 692
547 state->currentfreq=p->frequency; 693 state->currentfreq=p->frequency;
548 state->currentsymbolrate=p->u.qpsk.symbol_rate; 694 state->currentsymbolrate = p->u.qpsk.symbol_rate;
549 695
550 cx24123_set_inversion(state, p->inversion); 696 cx24123_set_inversion(state, p->inversion);
551 cx24123_set_fec(state, p->u.qpsk.fec_inner); 697 cx24123_set_fec(state, p->u.qpsk.fec_inner);
@@ -553,7 +699,7 @@ static int cx24123_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_par
553 cx24123_pll_tune(fe, p); 699 cx24123_pll_tune(fe, p);
554 700
555 /* Enable automatic aquisition and reset cycle */ 701 /* Enable automatic aquisition and reset cycle */
556 cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07) ); 702 cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07));
557 cx24123_writereg(state, 0x00, 0x10); 703 cx24123_writereg(state, 0x00, 0x10);
558 cx24123_writereg(state, 0x00, 0); 704 cx24123_writereg(state, 0x00, 0);
559 705
@@ -605,7 +751,8 @@ static void cx24123_release(struct dvb_frontend* fe)
605 751
606static struct dvb_frontend_ops cx24123_ops; 752static struct dvb_frontend_ops cx24123_ops;
607 753
608struct dvb_frontend* cx24123_attach(const struct cx24123_config* config, struct i2c_adapter* i2c) 754struct dvb_frontend* cx24123_attach(const struct cx24123_config* config,
755 struct i2c_adapter* i2c)
609{ 756{
610 struct cx24123_state* state = NULL; 757 struct cx24123_state* state = NULL;
611 int ret; 758 int ret;
@@ -691,4 +838,3 @@ MODULE_AUTHOR("Steven Toth");
691MODULE_LICENSE("GPL"); 838MODULE_LICENSE("GPL");
692 839
693EXPORT_SYMBOL(cx24123_attach); 840EXPORT_SYMBOL(cx24123_attach);
694
diff --git a/drivers/media/dvb/frontends/cx24123.h b/drivers/media/dvb/frontends/cx24123.h
index 80b66a695261..a6b85d517578 100644
--- a/drivers/media/dvb/frontends/cx24123.h
+++ b/drivers/media/dvb/frontends/cx24123.h
@@ -36,150 +36,7 @@ struct cx24123_config
36 int (*set_ts_params)(struct dvb_frontend* fe, int is_punctured); 36 int (*set_ts_params)(struct dvb_frontend* fe, int is_punctured);
37}; 37};
38 38
39/* Various tuner defaults need to be established for a given symbol rate Sps */
40struct
41{
42 u32 symbolrate_low;
43 u32 symbolrate_high;
44 u32 VCAslope;
45 u32 VCAoffset;
46 u32 VGA1offset;
47 u32 VGA2offset;
48 u32 VCAprogdata;
49 u32 VGAprogdata;
50} cx24123_AGC_vals[] =
51{
52 {
53 .symbolrate_low = 1000000,
54 .symbolrate_high = 4999999,
55 .VCAslope = 0x07,
56 .VCAoffset = 0x0f,
57 .VGA1offset = 0x1f8,
58 .VGA2offset = 0x1f8,
59 .VGAprogdata = (2 << 18) | (0x1f8 << 9) | 0x1f8,
60 .VCAprogdata = (4 << 18) | (0x07 << 9) | 0x07,
61 },
62 {
63 .symbolrate_low = 5000000,
64 .symbolrate_high = 14999999,
65 .VCAslope = 0x1f,
66 .VCAoffset = 0x1f,
67 .VGA1offset = 0x1e0,
68 .VGA2offset = 0x180,
69 .VGAprogdata = (2 << 18) | (0x180 << 9) | 0x1e0,
70 .VCAprogdata = (4 << 18) | (0x07 << 9) | 0x1f,
71 },
72 {
73 .symbolrate_low = 15000000,
74 .symbolrate_high = 45000000,
75 .VCAslope = 0x3f,
76 .VCAoffset = 0x3f,
77 .VGA1offset = 0x180,
78 .VGA2offset = 0x100,
79 .VGAprogdata = (2 << 18) | (0x100 << 9) | 0x180,
80 .VCAprogdata = (4 << 18) | (0x07 << 9) | 0x3f,
81 },
82};
83
84/*
85 * Various tuner defaults need to be established for a given frequency kHz.
86 * fixme: The bounds on the bands do not match the doc in real life.
87 * fixme: Some of them have been moved, other might need adjustment.
88 */
89struct
90{
91 u32 freq_low;
92 u32 freq_high;
93 u32 bandselect;
94 u32 VCOdivider;
95 u32 VCOnumber;
96 u32 progdata;
97} cx24123_bandselect_vals[] =
98{
99 {
100 .freq_low = 950000,
101 .freq_high = 1018999,
102 .bandselect = 0x40,
103 .VCOdivider = 4,
104 .VCOnumber = 7,
105 .progdata = (0 << 18) | (0 << 9) | 0x40,
106 },
107 {
108 .freq_low = 1019000,
109 .freq_high = 1074999,
110 .bandselect = 0x80,
111 .VCOdivider = 4,
112 .VCOnumber = 8,
113 .progdata = (0 << 18) | (0 << 9) | 0x80,
114 },
115 {
116 .freq_low = 1075000,
117 .freq_high = 1227999,
118 .bandselect = 0x01,
119 .VCOdivider = 2,
120 .VCOnumber = 1,
121 .progdata = (0 << 18) | (1 << 9) | 0x01,
122 },
123 {
124 .freq_low = 1228000,
125 .freq_high = 1349999,
126 .bandselect = 0x02,
127 .VCOdivider = 2,
128 .VCOnumber = 2,
129 .progdata = (0 << 18) | (1 << 9) | 0x02,
130 },
131 {
132 .freq_low = 1350000,
133 .freq_high = 1481999,
134 .bandselect = 0x04,
135 .VCOdivider = 2,
136 .VCOnumber = 3,
137 .progdata = (0 << 18) | (1 << 9) | 0x04,
138 },
139 {
140 .freq_low = 1482000,
141 .freq_high = 1595999,
142 .bandselect = 0x08,
143 .VCOdivider = 2,
144 .VCOnumber = 4,
145 .progdata = (0 << 18) | (1 << 9) | 0x08,
146 },
147 {
148 .freq_low = 1596000,
149 .freq_high = 1717999,
150 .bandselect = 0x10,
151 .VCOdivider = 2,
152 .VCOnumber = 5,
153 .progdata = (0 << 18) | (1 << 9) | 0x10,
154 },
155 {
156 .freq_low = 1718000,
157 .freq_high = 1855999,
158 .bandselect = 0x20,
159 .VCOdivider = 2,
160 .VCOnumber = 6,
161 .progdata = (0 << 18) | (1 << 9) | 0x20,
162 },
163 {
164 .freq_low = 1856000,
165 .freq_high = 2035999,
166 .bandselect = 0x40,
167 .VCOdivider = 2,
168 .VCOnumber = 7,
169 .progdata = (0 << 18) | (1 << 9) | 0x40,
170 },
171 {
172 .freq_low = 2036000,
173 .freq_high = 2149999,
174 .bandselect = 0x80,
175 .VCOdivider = 2,
176 .VCOnumber = 8,
177 .progdata = (0 << 18) | (1 << 9) | 0x80,
178 },
179};
180
181extern struct dvb_frontend* cx24123_attach(const struct cx24123_config* config, 39extern struct dvb_frontend* cx24123_attach(const struct cx24123_config* config,
182 struct i2c_adapter* i2c); 40 struct i2c_adapter* i2c);
183 41
184#endif /* CX24123_H */ 42#endif /* CX24123_H */
185