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authorOlof Johansson <olof@lixom.net>2007-01-31 22:43:54 -0500
committerJeff Garzik <jeff@garzik.org>2007-02-05 16:58:52 -0500
commitf5cd7872768d5856b1b409a33f516e5ac7798f75 (patch)
tree75c7e49f1c036ec4217c741d54017a16e3d8aad1
parent1ee6dd770b2302e32fdae489f4fc58c374399da4 (diff)
PA Semi PWRficient Ethernet driver
Driver for the PA Semi PWRficient on-chip Ethernet (1/10G) Basic enablement, will be complemented with performance enhancements over time. PHY support will be added as well. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat
-rw-r--r--MAINTAINERS6
-rw-r--r--drivers/net/Kconfig7
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/pasemi_mac.c1019
-rw-r--r--drivers/net/pasemi_mac.h460
-rw-r--r--include/linux/pci_ids.h2
6 files changed, 1495 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 603066666f86..32581c2f859d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2477,6 +2477,12 @@ L: orinoco-devel@lists.sourceforge.net
2477W: http://www.nongnu.org/orinoco/ 2477W: http://www.nongnu.org/orinoco/
2478S: Maintained 2478S: Maintained
2479 2479
2480PA SEMI ETHERNET DRIVER
2481P: Olof Johansson
2482M: olof@lixom.net
2483L: netdev@vger.kernel.org
2484S: Maintained
2485
2480PARALLEL PORT SUPPORT 2486PARALLEL PORT SUPPORT
2481P: Phil Blundell 2487P: Phil Blundell
2482M: philb@gnu.org 2488M: philb@gnu.org
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 8ffa82559116..a005517a4184 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2493,6 +2493,13 @@ config NETXEN_NIC
2493 help 2493 help
2494 This enables the support for NetXen's Gigabit Ethernet card. 2494 This enables the support for NetXen's Gigabit Ethernet card.
2495 2495
2496config PASEMI_MAC
2497 tristate "PA Semi 1/10Gbit MAC"
2498 depends on PPC64 && PCI
2499 help
2500 This driver supports the on-chip 1/10Gbit Ethernet controller on
2501 PA Semi's PWRficient line of chips.
2502
2496endmenu 2503endmenu
2497 2504
2498source "drivers/net/tokenring/Kconfig" 2505source "drivers/net/tokenring/Kconfig"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 9a86ebf9ab77..0878e3df5174 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -195,6 +195,7 @@ obj-$(CONFIG_SMC91X) += smc91x.o
195obj-$(CONFIG_SMC911X) += smc911x.o 195obj-$(CONFIG_SMC911X) += smc911x.o
196obj-$(CONFIG_DM9000) += dm9000.o 196obj-$(CONFIG_DM9000) += dm9000.o
197obj-$(CONFIG_FEC_8XX) += fec_8xx/ 197obj-$(CONFIG_FEC_8XX) += fec_8xx/
198obj-$(CONFIG_PASEMI_MAC) += pasemi_mac.o
198 199
199obj-$(CONFIG_MACB) += macb.o 200obj-$(CONFIG_MACB) += macb.o
200 201
diff --git a/drivers/net/pasemi_mac.c b/drivers/net/pasemi_mac.c
new file mode 100644
index 000000000000..d670ac74824f
--- /dev/null
+++ b/drivers/net/pasemi_mac.c
@@ -0,0 +1,1019 @@
1/*
2 * Copyright (C) 2006-2007 PA Semi, Inc
3 *
4 * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/interrupt.h>
24#include <linux/dmaengine.h>
25#include <linux/delay.h>
26#include <linux/netdevice.h>
27#include <linux/etherdevice.h>
28#include <asm/dma-mapping.h>
29#include <linux/in.h>
30#include <linux/skbuff.h>
31
32#include <linux/ip.h>
33#include <linux/tcp.h>
34#include <net/checksum.h>
35
36#include "pasemi_mac.h"
37
38
39/* TODO list
40 *
41 * - Get rid of pci_{read,write}_config(), map registers with ioremap
42 * for performance
43 * - PHY support
44 * - Multicast support
45 * - Large MTU support
46 * - Other performance improvements
47 */
48
49
50/* Must be a power of two */
51#define RX_RING_SIZE 512
52#define TX_RING_SIZE 512
53
54#define TX_DESC(mac, num) ((mac)->tx->desc[(num) & (TX_RING_SIZE-1)])
55#define TX_DESC_INFO(mac, num) ((mac)->tx->desc_info[(num) & (TX_RING_SIZE-1)])
56#define RX_DESC(mac, num) ((mac)->rx->desc[(num) & (RX_RING_SIZE-1)])
57#define RX_DESC_INFO(mac, num) ((mac)->rx->desc_info[(num) & (RX_RING_SIZE-1)])
58#define RX_BUFF(mac, num) ((mac)->rx->buffers[(num) & (RX_RING_SIZE-1)])
59
60#define BUF_SIZE 1646 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
61
62/* XXXOJN these should come out of the device tree some day */
63#define PAS_DMA_CAP_BASE 0xe00d0040
64#define PAS_DMA_CAP_SIZE 0x100
65#define PAS_DMA_COM_BASE 0xe00d0100
66#define PAS_DMA_COM_SIZE 0x100
67
68static struct pasdma_status *dma_status;
69
70static int pasemi_get_mac_addr(struct pasemi_mac *mac)
71{
72 struct pci_dev *pdev = mac->pdev;
73 struct device_node *dn = pci_device_to_OF_node(pdev);
74 const u8 *maddr;
75 u8 addr[6];
76
77 if (!dn) {
78 dev_dbg(&pdev->dev,
79 "No device node for mac, not configuring\n");
80 return -ENOENT;
81 }
82
83 maddr = get_property(dn, "mac-address", NULL);
84 if (maddr == NULL) {
85 dev_warn(&pdev->dev,
86 "no mac address in device tree, not configuring\n");
87 return -ENOENT;
88 }
89
90 if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0],
91 &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) {
92 dev_warn(&pdev->dev,
93 "can't parse mac address, not configuring\n");
94 return -EINVAL;
95 }
96
97 memcpy(mac->mac_addr, addr, sizeof(addr));
98 return 0;
99}
100
101static int pasemi_mac_setup_rx_resources(struct net_device *dev)
102{
103 struct pasemi_mac_rxring *ring;
104 struct pasemi_mac *mac = netdev_priv(dev);
105 int chan_id = mac->dma_rxch;
106
107 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
108
109 if (!ring)
110 goto out_ring;
111
112 spin_lock_init(&ring->lock);
113
114 ring->desc_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
115 RX_RING_SIZE, GFP_KERNEL);
116
117 if (!ring->desc_info)
118 goto out_desc_info;
119
120 /* Allocate descriptors */
121 ring->desc = dma_alloc_coherent(&mac->dma_pdev->dev,
122 RX_RING_SIZE *
123 sizeof(struct pas_dma_xct_descr),
124 &ring->dma, GFP_KERNEL);
125
126 if (!ring->desc)
127 goto out_desc;
128
129 memset(ring->desc, 0, RX_RING_SIZE * sizeof(struct pas_dma_xct_descr));
130
131 ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev,
132 RX_RING_SIZE * sizeof(u64),
133 &ring->buf_dma, GFP_KERNEL);
134 if (!ring->buffers)
135 goto out_buffers;
136
137 memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64));
138
139 pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_BASEL(chan_id),
140 PAS_DMA_RXCHAN_BASEL_BRBL(ring->dma));
141
142 pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_BASEU(chan_id),
143 PAS_DMA_RXCHAN_BASEU_BRBH(ring->dma >> 32) |
144 PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 2));
145
146 pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_CFG(chan_id),
147 PAS_DMA_RXCHAN_CFG_HBU(1));
148
149 pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXINT_BASEL(mac->dma_if),
150 PAS_DMA_RXINT_BASEL_BRBL(__pa(ring->buffers)));
151
152 pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXINT_BASEU(mac->dma_if),
153 PAS_DMA_RXINT_BASEU_BRBH(__pa(ring->buffers) >> 32) |
154 PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
155
156 ring->next_to_fill = 0;
157 ring->next_to_clean = 0;
158
159 snprintf(ring->irq_name, sizeof(ring->irq_name),
160 "%s rx", dev->name);
161 mac->rx = ring;
162
163 return 0;
164
165out_buffers:
166 dma_free_coherent(&mac->dma_pdev->dev,
167 RX_RING_SIZE * sizeof(struct pas_dma_xct_descr),
168 mac->rx->desc, mac->rx->dma);
169out_desc:
170 kfree(ring->desc_info);
171out_desc_info:
172 kfree(ring);
173out_ring:
174 return -ENOMEM;
175}
176
177
178static int pasemi_mac_setup_tx_resources(struct net_device *dev)
179{
180 struct pasemi_mac *mac = netdev_priv(dev);
181 u32 val;
182 int chan_id = mac->dma_txch;
183 struct pasemi_mac_txring *ring;
184
185 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
186 if (!ring)
187 goto out_ring;
188
189 spin_lock_init(&ring->lock);
190
191 ring->desc_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
192 TX_RING_SIZE, GFP_KERNEL);
193 if (!ring->desc_info)
194 goto out_desc_info;
195
196 /* Allocate descriptors */
197 ring->desc = dma_alloc_coherent(&mac->dma_pdev->dev,
198 TX_RING_SIZE *
199 sizeof(struct pas_dma_xct_descr),
200 &ring->dma, GFP_KERNEL);
201 if (!ring->desc)
202 goto out_desc;
203
204 memset(ring->desc, 0, TX_RING_SIZE * sizeof(struct pas_dma_xct_descr));
205
206 pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_BASEL(chan_id),
207 PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma));
208 val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32);
209 val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2);
210
211 pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_BASEU(chan_id), val);
212
213 pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_CFG(chan_id),
214 PAS_DMA_TXCHAN_CFG_TY_IFACE |
215 PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
216 PAS_DMA_TXCHAN_CFG_UP |
217 PAS_DMA_TXCHAN_CFG_WT(2));
218
219 ring->next_to_use = 0;
220 ring->next_to_clean = 0;
221
222 snprintf(ring->irq_name, sizeof(ring->irq_name),
223 "%s tx", dev->name);
224 mac->tx = ring;
225
226 return 0;
227
228out_desc:
229 kfree(ring->desc_info);
230out_desc_info:
231 kfree(ring);
232out_ring:
233 return -ENOMEM;
234}
235
236static void pasemi_mac_free_tx_resources(struct net_device *dev)
237{
238 struct pasemi_mac *mac = netdev_priv(dev);
239 unsigned int i;
240 struct pasemi_mac_buffer *info;
241 struct pas_dma_xct_descr *dp;
242
243 for (i = 0; i < TX_RING_SIZE; i++) {
244 info = &TX_DESC_INFO(mac, i);
245 dp = &TX_DESC(mac, i);
246 if (info->dma) {
247 if (info->skb) {
248 pci_unmap_single(mac->dma_pdev,
249 info->dma,
250 info->skb->len,
251 PCI_DMA_TODEVICE);
252 dev_kfree_skb_any(info->skb);
253 }
254 info->dma = 0;
255 info->skb = NULL;
256 dp->mactx = 0;
257 dp->ptr = 0;
258 }
259 }
260
261 dma_free_coherent(&mac->dma_pdev->dev,
262 TX_RING_SIZE * sizeof(struct pas_dma_xct_descr),
263 mac->tx->desc, mac->tx->dma);
264
265 kfree(mac->tx->desc_info);
266 kfree(mac->tx);
267 mac->tx = NULL;
268}
269
270static void pasemi_mac_free_rx_resources(struct net_device *dev)
271{
272 struct pasemi_mac *mac = netdev_priv(dev);
273 unsigned int i;
274 struct pasemi_mac_buffer *info;
275 struct pas_dma_xct_descr *dp;
276
277 for (i = 0; i < RX_RING_SIZE; i++) {
278 info = &RX_DESC_INFO(mac, i);
279 dp = &RX_DESC(mac, i);
280 if (info->dma) {
281 if (info->skb) {
282 pci_unmap_single(mac->dma_pdev,
283 info->dma,
284 info->skb->len,
285 PCI_DMA_FROMDEVICE);
286 dev_kfree_skb_any(info->skb);
287 }
288 info->dma = 0;
289 info->skb = NULL;
290 dp->macrx = 0;
291 dp->ptr = 0;
292 }
293 }
294
295 dma_free_coherent(&mac->dma_pdev->dev,
296 RX_RING_SIZE * sizeof(struct pas_dma_xct_descr),
297 mac->rx->desc, mac->rx->dma);
298
299 dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64),
300 mac->rx->buffers, mac->rx->buf_dma);
301
302 kfree(mac->rx->desc_info);
303 kfree(mac->rx);
304 mac->rx = NULL;
305}
306
307static void pasemi_mac_replenish_rx_ring(struct net_device *dev)
308{
309 struct pasemi_mac *mac = netdev_priv(dev);
310 unsigned int i;
311 int start = mac->rx->next_to_fill;
312 unsigned int count;
313
314 count = (mac->rx->next_to_clean + RX_RING_SIZE -
315 mac->rx->next_to_fill) & (RX_RING_SIZE - 1);
316
317 /* Check to see if we're doing first-time setup */
318 if (unlikely(mac->rx->next_to_clean == 0 && mac->rx->next_to_fill == 0))
319 count = RX_RING_SIZE;
320
321 if (count <= 0)
322 return;
323
324 for (i = start; i < start + count; i++) {
325 struct pasemi_mac_buffer *info = &RX_DESC_INFO(mac, i);
326 u64 *buff = &RX_BUFF(mac, i);
327 struct sk_buff *skb;
328 dma_addr_t dma;
329
330 skb = dev_alloc_skb(BUF_SIZE);
331
332 if (!skb) {
333 count = i - start;
334 break;
335 }
336
337 skb->dev = dev;
338
339 dma = pci_map_single(mac->dma_pdev, skb->data, skb->len,
340 PCI_DMA_FROMDEVICE);
341
342 if (dma_mapping_error(dma)) {
343 dev_kfree_skb_irq(info->skb);
344 count = i - start;
345 break;
346 }
347
348 info->skb = skb;
349 info->dma = dma;
350 *buff = XCT_RXB_LEN(BUF_SIZE) | XCT_RXB_ADDR(dma);
351 }
352
353 wmb();
354
355 pci_write_config_dword(mac->dma_pdev,
356 PAS_DMA_RXCHAN_INCR(mac->dma_rxch),
357 count);
358 pci_write_config_dword(mac->dma_pdev,
359 PAS_DMA_RXINT_INCR(mac->dma_if),
360 count);
361
362 mac->rx->next_to_fill += count;
363}
364
365static int pasemi_mac_clean_rx(struct pasemi_mac *mac, int limit)
366{
367 unsigned int i;
368 int start, count;
369
370 spin_lock(&mac->rx->lock);
371
372 start = mac->rx->next_to_clean;
373 count = 0;
374
375 for (i = start; i < (start + RX_RING_SIZE) && count < limit; i++) {
376 struct pas_dma_xct_descr *dp;
377 struct pasemi_mac_buffer *info;
378 struct sk_buff *skb;
379 unsigned int j, len;
380 dma_addr_t dma;
381
382 rmb();
383
384 dp = &RX_DESC(mac, i);
385
386 if (!(dp->macrx & XCT_MACRX_O))
387 break;
388
389 count++;
390
391 info = NULL;
392
393 /* We have to scan for our skb since there's no way
394 * to back-map them from the descriptor, and if we
395 * have several receive channels then they might not
396 * show up in the same order as they were put on the
397 * interface ring.
398 */
399
400 dma = (dp->ptr & XCT_PTR_ADDR_M);
401 for (j = start; j < (start + RX_RING_SIZE); j++) {
402 info = &RX_DESC_INFO(mac, j);
403 if (info->dma == dma)
404 break;
405 }
406
407 BUG_ON(!info);
408 BUG_ON(info->dma != dma);
409
410 pci_unmap_single(mac->dma_pdev, info->dma, info->skb->len,
411 PCI_DMA_FROMDEVICE);
412
413 skb = info->skb;
414
415 len = (dp->macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S;
416
417 skb_put(skb, len);
418
419 skb->protocol = eth_type_trans(skb, mac->netdev);
420
421 if ((dp->macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK) {
422 skb->ip_summed = CHECKSUM_COMPLETE;
423 skb->csum = (dp->macrx & XCT_MACRX_CSUM_M) >>
424 XCT_MACRX_CSUM_S;
425 } else
426 skb->ip_summed = CHECKSUM_NONE;
427
428 mac->stats.rx_bytes += len;
429 mac->stats.rx_packets++;
430
431 netif_receive_skb(skb);
432
433 info->dma = 0;
434 info->skb = NULL;
435 dp->ptr = 0;
436 dp->macrx = 0;
437 }
438
439 mac->rx->next_to_clean += count;
440 pasemi_mac_replenish_rx_ring(mac->netdev);
441
442 spin_unlock(&mac->rx->lock);
443
444 return count;
445}
446
447static int pasemi_mac_clean_tx(struct pasemi_mac *mac)
448{
449 int i;
450 struct pasemi_mac_buffer *info;
451 struct pas_dma_xct_descr *dp;
452 int start, count;
453 int flags;
454
455 spin_lock_irqsave(&mac->tx->lock, flags);
456
457 start = mac->tx->next_to_clean;
458 count = 0;
459
460 for (i = start; i < mac->tx->next_to_use; i++) {
461 dp = &TX_DESC(mac, i);
462 if (!dp || (dp->mactx & XCT_MACTX_O))
463 break;
464
465 count++;
466
467 info = &TX_DESC_INFO(mac, i);
468
469 pci_unmap_single(mac->dma_pdev, info->dma,
470 info->skb->len, PCI_DMA_TODEVICE);
471 dev_kfree_skb_irq(info->skb);
472
473 info->skb = NULL;
474 info->dma = 0;
475 dp->mactx = 0;
476 dp->ptr = 0;
477 }
478 mac->tx->next_to_clean += count;
479 spin_unlock_irqrestore(&mac->tx->lock, flags);
480
481 return count;
482}
483
484
485static irqreturn_t pasemi_mac_rx_intr(int irq, void *data)
486{
487 struct net_device *dev = data;
488 struct pasemi_mac *mac = netdev_priv(dev);
489 unsigned int reg;
490
491 if (!(*mac->rx_status & PAS_STATUS_INT))
492 return IRQ_NONE;
493
494 netif_rx_schedule(dev);
495 pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_COM_TIMEOUTCFG,
496 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0));
497
498 reg = PAS_IOB_DMA_RXCH_RESET_PINTC | PAS_IOB_DMA_RXCH_RESET_SINTC |
499 PAS_IOB_DMA_RXCH_RESET_DINTC;
500 if (*mac->rx_status & PAS_STATUS_TIMER)
501 reg |= PAS_IOB_DMA_RXCH_RESET_TINTC;
502
503 pci_write_config_dword(mac->iob_pdev,
504 PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg);
505
506
507 return IRQ_HANDLED;
508}
509
510static irqreturn_t pasemi_mac_tx_intr(int irq, void *data)
511{
512 struct net_device *dev = data;
513 struct pasemi_mac *mac = netdev_priv(dev);
514 unsigned int reg;
515 int was_full;
516
517 was_full = mac->tx->next_to_clean - mac->tx->next_to_use == TX_RING_SIZE;
518
519 if (!(*mac->tx_status & PAS_STATUS_INT))
520 return IRQ_NONE;
521
522 pasemi_mac_clean_tx(mac);
523
524 reg = PAS_IOB_DMA_TXCH_RESET_PINTC | PAS_IOB_DMA_TXCH_RESET_SINTC;
525 if (*mac->tx_status & PAS_STATUS_TIMER)
526 reg |= PAS_IOB_DMA_TXCH_RESET_TINTC;
527
528 pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_TXCH_RESET(mac->dma_txch),
529 reg);
530
531 if (was_full)
532 netif_wake_queue(dev);
533
534 return IRQ_HANDLED;
535}
536
537static int pasemi_mac_open(struct net_device *dev)
538{
539 struct pasemi_mac *mac = netdev_priv(dev);
540 unsigned int flags;
541 int ret;
542
543 /* enable rx section */
544 pci_write_config_dword(mac->dma_pdev, PAS_DMA_COM_RXCMD,
545 PAS_DMA_COM_RXCMD_EN);
546
547 /* enable tx section */
548 pci_write_config_dword(mac->dma_pdev, PAS_DMA_COM_TXCMD,
549 PAS_DMA_COM_TXCMD_EN);
550
551 flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
552 PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
553 PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12);
554
555 pci_write_config_dword(mac->pdev, PAS_MAC_CFG_TXP, flags);
556
557 flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PE |
558 PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE;
559
560 flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G;
561
562 pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_RXCH_CFG(mac->dma_rxch),
563 PAS_IOB_DMA_RXCH_CFG_CNTTH(30));
564
565 pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_COM_TIMEOUTCFG,
566 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(1000000));
567
568 pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, flags);
569
570 ret = pasemi_mac_setup_rx_resources(dev);
571 if (ret)
572 goto out_rx_resources;
573
574 ret = pasemi_mac_setup_tx_resources(dev);
575 if (ret)
576 goto out_tx_resources;
577
578 pci_write_config_dword(mac->pdev, PAS_MAC_IPC_CHNL,
579 PAS_MAC_IPC_CHNL_DCHNO(mac->dma_rxch) |
580 PAS_MAC_IPC_CHNL_BCH(mac->dma_rxch));
581
582 /* enable rx if */
583 pci_write_config_dword(mac->dma_pdev,
584 PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
585 PAS_DMA_RXINT_RCMDSTA_EN);
586
587 /* enable rx channel */
588 pci_write_config_dword(mac->dma_pdev,
589 PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
590 PAS_DMA_RXCHAN_CCMDSTA_EN |
591 PAS_DMA_RXCHAN_CCMDSTA_DU);
592
593 /* enable tx channel */
594 pci_write_config_dword(mac->dma_pdev,
595 PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
596 PAS_DMA_TXCHAN_TCMDSTA_EN);
597
598 pasemi_mac_replenish_rx_ring(dev);
599
600 netif_start_queue(dev);
601 netif_poll_enable(dev);
602
603 ret = request_irq(mac->dma_pdev->irq + mac->dma_txch,
604 &pasemi_mac_tx_intr, IRQF_DISABLED,
605 mac->tx->irq_name, dev);
606 if (ret) {
607 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
608 mac->dma_pdev->irq + mac->dma_txch, ret);
609 goto out_tx_int;
610 }
611
612 ret = request_irq(mac->dma_pdev->irq + 20 + mac->dma_rxch,
613 &pasemi_mac_rx_intr, IRQF_DISABLED,
614 mac->rx->irq_name, dev);
615 if (ret) {
616 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
617 mac->dma_pdev->irq + 20 + mac->dma_rxch, ret);
618 goto out_rx_int;
619 }
620
621 return 0;
622
623out_rx_int:
624 free_irq(mac->dma_pdev->irq + mac->dma_txch, dev);
625out_tx_int:
626 netif_poll_disable(dev);
627 netif_stop_queue(dev);
628 pasemi_mac_free_tx_resources(dev);
629out_tx_resources:
630 pasemi_mac_free_rx_resources(dev);
631out_rx_resources:
632
633 return ret;
634}
635
636#define MAX_RETRIES 5000
637
638static int pasemi_mac_close(struct net_device *dev)
639{
640 struct pasemi_mac *mac = netdev_priv(dev);
641 unsigned int stat;
642 int retries;
643
644 netif_stop_queue(dev);
645
646 /* Clean out any pending buffers */
647 pasemi_mac_clean_tx(mac);
648 pasemi_mac_clean_rx(mac, RX_RING_SIZE);
649
650 /* Disable interface */
651 pci_write_config_dword(mac->dma_pdev,
652 PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
653 PAS_DMA_TXCHAN_TCMDSTA_ST);
654 pci_write_config_dword(mac->dma_pdev,
655 PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
656 PAS_DMA_RXINT_RCMDSTA_ST);
657 pci_write_config_dword(mac->dma_pdev,
658 PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
659 PAS_DMA_RXCHAN_CCMDSTA_ST);
660
661 for (retries = 0; retries < MAX_RETRIES; retries++) {
662 pci_read_config_dword(mac->dma_pdev,
663 PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
664 &stat);
665 if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)
666 break;
667 cond_resched();
668 }
669
670 if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)) {
671 dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n");
672 }
673
674 for (retries = 0; retries < MAX_RETRIES; retries++) {
675 pci_read_config_dword(mac->dma_pdev,
676 PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
677 &stat);
678 if (stat & PAS_DMA_RXCHAN_CCMDSTA_ACT)
679 break;
680 cond_resched();
681 }
682
683 if (!(stat & PAS_DMA_RXCHAN_CCMDSTA_ACT)) {
684 dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n");
685 }
686
687 for (retries = 0; retries < MAX_RETRIES; retries++) {
688 pci_read_config_dword(mac->dma_pdev,
689 PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
690 &stat);
691 if (stat & PAS_DMA_RXINT_RCMDSTA_ACT)
692 break;
693 cond_resched();
694 }
695
696 if (!(stat & PAS_DMA_RXINT_RCMDSTA_ACT)) {
697 dev_err(&mac->dma_pdev->dev, "Failed to stop rx interface\n");
698 }
699
700 /* Then, disable the channel. This must be done separately from
701 * stopping, since you can't disable when active.
702 */
703
704 pci_write_config_dword(mac->dma_pdev,
705 PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), 0);
706 pci_write_config_dword(mac->dma_pdev,
707 PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), 0);
708 pci_write_config_dword(mac->dma_pdev,
709 PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0);
710
711 free_irq(mac->dma_pdev->irq + mac->dma_txch, dev);
712 free_irq(mac->dma_pdev->irq + 20 + mac->dma_rxch, dev);
713
714 /* Free resources */
715 pasemi_mac_free_rx_resources(dev);
716 pasemi_mac_free_tx_resources(dev);
717
718 return 0;
719}
720
721static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
722{
723 struct pasemi_mac *mac = netdev_priv(dev);
724 struct pasemi_mac_txring *txring;
725 struct pasemi_mac_buffer *info;
726 struct pas_dma_xct_descr *dp;
727 u64 dflags;
728 dma_addr_t map;
729 int flags;
730
731 dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_SS | XCT_MACTX_CRC_PAD;
732
733 if (skb->ip_summed == CHECKSUM_PARTIAL) {
734 switch (skb->nh.iph->protocol) {
735 case IPPROTO_TCP:
736 dflags |= XCT_MACTX_CSUM_TCP;
737 dflags |= XCT_MACTX_IPH((skb->h.raw - skb->nh.raw) >> 2);
738 dflags |= XCT_MACTX_IPO(skb->nh.raw - skb->data);
739 break;
740 case IPPROTO_UDP:
741 dflags |= XCT_MACTX_CSUM_UDP;
742 dflags |= XCT_MACTX_IPH((skb->h.raw - skb->nh.raw) >> 2);
743 dflags |= XCT_MACTX_IPO(skb->nh.raw - skb->data);
744 break;
745 }
746 }
747
748 map = pci_map_single(mac->dma_pdev, skb->data, skb->len, PCI_DMA_TODEVICE);
749
750 if (dma_mapping_error(map))
751 return NETDEV_TX_BUSY;
752
753 txring = mac->tx;
754
755 spin_lock_irqsave(&txring->lock, flags);
756
757 if (txring->next_to_clean - txring->next_to_use == TX_RING_SIZE) {
758 spin_unlock_irqrestore(&txring->lock, flags);
759 pasemi_mac_clean_tx(mac);
760 spin_lock_irqsave(&txring->lock, flags);
761
762 if (txring->next_to_clean - txring->next_to_use ==
763 TX_RING_SIZE) {
764 /* Still no room -- stop the queue and wait for tx
765 * intr when there's room.
766 */
767 netif_stop_queue(dev);
768 goto out_err;
769 }
770 }
771
772
773 dp = &TX_DESC(mac, txring->next_to_use);
774 info = &TX_DESC_INFO(mac, txring->next_to_use);
775
776 dp->mactx = dflags | XCT_MACTX_LLEN(skb->len);
777 dp->ptr = XCT_PTR_LEN(skb->len) | XCT_PTR_ADDR(map);
778 info->dma = map;
779 info->skb = skb;
780
781 txring->next_to_use++;
782 mac->stats.tx_packets++;
783 mac->stats.tx_bytes += skb->len;
784
785 spin_unlock_irqrestore(&txring->lock, flags);
786
787 pci_write_config_dword(mac->dma_pdev,
788 PAS_DMA_TXCHAN_INCR(mac->dma_txch), 1);
789
790 return NETDEV_TX_OK;
791
792out_err:
793 spin_unlock_irqrestore(&txring->lock, flags);
794 pci_unmap_single(mac->dma_pdev, map, skb->len, PCI_DMA_TODEVICE);
795 return NETDEV_TX_BUSY;
796}
797
798static struct net_device_stats *pasemi_mac_get_stats(struct net_device *dev)
799{
800 struct pasemi_mac *mac = netdev_priv(dev);
801
802 return &mac->stats;
803}
804
805static void pasemi_mac_set_rx_mode(struct net_device *dev)
806{
807 struct pasemi_mac *mac = netdev_priv(dev);
808 unsigned int flags;
809
810 pci_read_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, &flags);
811
812 /* Set promiscuous */
813 if (dev->flags & IFF_PROMISC)
814 flags |= PAS_MAC_CFG_PCFG_PR;
815 else
816 flags &= ~PAS_MAC_CFG_PCFG_PR;
817
818 pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, flags);
819}
820
821
822static int pasemi_mac_poll(struct net_device *dev, int *budget)
823{
824 int pkts, limit = min(*budget, dev->quota);
825 struct pasemi_mac *mac = netdev_priv(dev);
826
827 pkts = pasemi_mac_clean_rx(mac, limit);
828
829 if (pkts < limit) {
830 /* all done, no more packets present */
831 netif_rx_complete(dev);
832
833 /* re-enable receive interrupts */
834 pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_COM_TIMEOUTCFG,
835 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(1000000));
836 return 0;
837 } else {
838 /* used up our quantum, so reschedule */
839 dev->quota -= pkts;
840 *budget -= pkts;
841 return 1;
842 }
843}
844
845static int __devinit
846pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
847{
848 static int index = 0;
849 struct net_device *dev;
850 struct pasemi_mac *mac;
851 int err;
852
853 err = pci_enable_device(pdev);
854 if (err)
855 return err;
856
857 dev = alloc_etherdev(sizeof(struct pasemi_mac));
858 if (dev == NULL) {
859 dev_err(&pdev->dev,
860 "pasemi_mac: Could not allocate ethernet device.\n");
861 err = -ENOMEM;
862 goto out_disable_device;
863 }
864
865 SET_MODULE_OWNER(dev);
866 pci_set_drvdata(pdev, dev);
867 SET_NETDEV_DEV(dev, &pdev->dev);
868
869 mac = netdev_priv(dev);
870
871 mac->pdev = pdev;
872 mac->netdev = dev;
873 mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
874
875 if (!mac->dma_pdev) {
876 dev_err(&pdev->dev, "Can't find DMA Controller\n");
877 err = -ENODEV;
878 goto out_free_netdev;
879 }
880
881 mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
882
883 if (!mac->iob_pdev) {
884 dev_err(&pdev->dev, "Can't find I/O Bridge\n");
885 err = -ENODEV;
886 goto out_put_dma_pdev;
887 }
888
889 /* These should come out of the device tree eventually */
890 mac->dma_txch = index;
891 mac->dma_rxch = index;
892
893 /* We probe GMAC before XAUI, but the DMA interfaces are
894 * in XAUI, GMAC order.
895 */
896 if (index < 4)
897 mac->dma_if = index + 2;
898 else
899 mac->dma_if = index - 4;
900 index++;
901
902 switch (pdev->device) {
903 case 0xa005:
904 mac->type = MAC_TYPE_GMAC;
905 break;
906 case 0xa006:
907 mac->type = MAC_TYPE_XAUI;
908 break;
909 default:
910 err = -ENODEV;
911 goto out;
912 }
913
914 /* get mac addr from device tree */
915 if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) {
916 err = -ENODEV;
917 goto out;
918 }
919 memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr));
920
921 dev->open = pasemi_mac_open;
922 dev->stop = pasemi_mac_close;
923 dev->hard_start_xmit = pasemi_mac_start_tx;
924 dev->get_stats = pasemi_mac_get_stats;
925 dev->set_multicast_list = pasemi_mac_set_rx_mode;
926 dev->weight = 64;
927 dev->poll = pasemi_mac_poll;
928 dev->features = NETIF_F_HW_CSUM;
929
930 /* The dma status structure is located in the I/O bridge, and
931 * is cache coherent.
932 */
933 if (!dma_status)
934 /* XXXOJN This should come from the device tree */
935 dma_status = __ioremap(0xfd800000, 0x1000, 0);
936
937 mac->rx_status = &dma_status->rx_sta[mac->dma_rxch];
938 mac->tx_status = &dma_status->tx_sta[mac->dma_txch];
939
940 err = register_netdev(dev);
941
942 if (err) {
943 dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n",
944 err);
945 goto out;
946 } else
947 printk(KERN_INFO "%s: PA Semi %s: intf %d, txch %d, rxch %d, "
948 "hw addr %02x:%02x:%02x:%02x:%02x:%02x\n",
949 dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI",
950 mac->dma_if, mac->dma_txch, mac->dma_rxch,
951 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
952 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
953
954 return err;
955
956out:
957 pci_dev_put(mac->iob_pdev);
958out_put_dma_pdev:
959 pci_dev_put(mac->dma_pdev);
960out_free_netdev:
961 free_netdev(dev);
962out_disable_device:
963 pci_disable_device(pdev);
964 return err;
965
966}
967
968static void __devexit pasemi_mac_remove(struct pci_dev *pdev)
969{
970 struct net_device *netdev = pci_get_drvdata(pdev);
971 struct pasemi_mac *mac;
972
973 if (!netdev)
974 return;
975
976 mac = netdev_priv(netdev);
977
978 unregister_netdev(netdev);
979
980 pci_disable_device(pdev);
981 pci_dev_put(mac->dma_pdev);
982 pci_dev_put(mac->iob_pdev);
983
984 pci_set_drvdata(pdev, NULL);
985 free_netdev(netdev);
986}
987
988static struct pci_device_id pasemi_mac_pci_tbl[] = {
989 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) },
990 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) },
991};
992
993MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl);
994
995static struct pci_driver pasemi_mac_driver = {
996 .name = "pasemi_mac",
997 .id_table = pasemi_mac_pci_tbl,
998 .probe = pasemi_mac_probe,
999 .remove = __devexit_p(pasemi_mac_remove),
1000};
1001
1002static void __exit pasemi_mac_cleanup_module(void)
1003{
1004 pci_unregister_driver(&pasemi_mac_driver);
1005 __iounmap(dma_status);
1006 dma_status = NULL;
1007}
1008
1009int pasemi_mac_init_module(void)
1010{
1011 return pci_register_driver(&pasemi_mac_driver);
1012}
1013
1014MODULE_LICENSE("GPL");
1015MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
1016MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
1017
1018module_init(pasemi_mac_init_module);
1019module_exit(pasemi_mac_cleanup_module);
diff --git a/drivers/net/pasemi_mac.h b/drivers/net/pasemi_mac.h
new file mode 100644
index 000000000000..c3e37e46a18a
--- /dev/null
+++ b/drivers/net/pasemi_mac.h
@@ -0,0 +1,460 @@
1/*
2 * Copyright (C) 2006 PA Semi, Inc
3 *
4 * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
5 * hardware register layouts.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef PASEMI_MAC_H
22#define PASEMI_MAC_H
23
24#include <linux/ethtool.h>
25#include <linux/netdevice.h>
26#include <linux/spinlock.h>
27
28struct pasemi_mac_txring {
29 spinlock_t lock;
30 struct pas_dma_xct_descr *desc;
31 dma_addr_t dma;
32 unsigned int size;
33 unsigned int next_to_use;
34 unsigned int next_to_clean;
35 struct pasemi_mac_buffer *desc_info;
36 char irq_name[10]; /* "eth%d tx" */
37};
38
39struct pasemi_mac_rxring {
40 spinlock_t lock;
41 struct pas_dma_xct_descr *desc; /* RX channel descriptor ring */
42 dma_addr_t dma;
43 u64 *buffers; /* RX interface buffer ring */
44 dma_addr_t buf_dma;
45 unsigned int size;
46 unsigned int next_to_fill;
47 unsigned int next_to_clean;
48 struct pasemi_mac_buffer *desc_info;
49 char irq_name[10]; /* "eth%d rx" */
50};
51
52struct pasemi_mac {
53 struct net_device *netdev;
54 struct pci_dev *pdev;
55 struct pci_dev *dma_pdev;
56 struct pci_dev *iob_pdev;
57 struct net_device_stats stats;
58
59 /* Pointer to the cacheable per-channel status registers */
60 u64 *rx_status;
61 u64 *tx_status;
62
63 u8 type;
64#define MAC_TYPE_GMAC 1
65#define MAC_TYPE_XAUI 2
66 u32 dma_txch;
67 u32 dma_if;
68 u32 dma_rxch;
69
70 u8 mac_addr[6];
71
72 struct timer_list rxtimer;
73
74 struct pasemi_mac_txring *tx;
75 struct pasemi_mac_rxring *rx;
76};
77
78/* Software status descriptor (desc_info) */
79struct pasemi_mac_buffer {
80 struct sk_buff *skb;
81 dma_addr_t dma;
82};
83
84
85/* status register layout in IOB region, at 0xfb800000 */
86struct pasdma_status {
87 u64 rx_sta[64];
88 u64 tx_sta[20];
89};
90
91/* descriptor structure */
92struct pas_dma_xct_descr {
93 union {
94 u64 mactx;
95 u64 macrx;
96 };
97 union {
98 u64 ptr;
99 u64 rxb;
100 };
101};
102
103/* MAC CFG register offsets */
104
105enum {
106 PAS_MAC_CFG_PCFG = 0x80,
107 PAS_MAC_CFG_TXP = 0x98,
108 PAS_MAC_IPC_CHNL = 0x208,
109};
110
111/* MAC CFG register fields */
112#define PAS_MAC_CFG_PCFG_PE 0x80000000
113#define PAS_MAC_CFG_PCFG_CE 0x40000000
114#define PAS_MAC_CFG_PCFG_BU 0x20000000
115#define PAS_MAC_CFG_PCFG_TT 0x10000000
116#define PAS_MAC_CFG_PCFG_TSR_M 0x0c000000
117#define PAS_MAC_CFG_PCFG_TSR_10M 0x00000000
118#define PAS_MAC_CFG_PCFG_TSR_100M 0x04000000
119#define PAS_MAC_CFG_PCFG_TSR_1G 0x08000000
120#define PAS_MAC_CFG_PCFG_TSR_10G 0x0c000000
121#define PAS_MAC_CFG_PCFG_T24 0x02000000
122#define PAS_MAC_CFG_PCFG_PR 0x01000000
123#define PAS_MAC_CFG_PCFG_CRO_M 0x00ff0000
124#define PAS_MAC_CFG_PCFG_CRO_S 16
125#define PAS_MAC_CFG_PCFG_IPO_M 0x0000ff00
126#define PAS_MAC_CFG_PCFG_IPO_S 8
127#define PAS_MAC_CFG_PCFG_S1 0x00000080
128#define PAS_MAC_CFG_PCFG_IO_M 0x00000060
129#define PAS_MAC_CFG_PCFG_IO_MAC 0x00000000
130#define PAS_MAC_CFG_PCFG_IO_OFF 0x00000020
131#define PAS_MAC_CFG_PCFG_IO_IND_ETH 0x00000040
132#define PAS_MAC_CFG_PCFG_IO_IND_IP 0x00000060
133#define PAS_MAC_CFG_PCFG_LP 0x00000010
134#define PAS_MAC_CFG_PCFG_TS 0x00000008
135#define PAS_MAC_CFG_PCFG_HD 0x00000004
136#define PAS_MAC_CFG_PCFG_SPD_M 0x00000003
137#define PAS_MAC_CFG_PCFG_SPD_10M 0x00000000
138#define PAS_MAC_CFG_PCFG_SPD_100M 0x00000001
139#define PAS_MAC_CFG_PCFG_SPD_1G 0x00000002
140#define PAS_MAC_CFG_PCFG_SPD_10G 0x00000003
141#define PAS_MAC_CFG_TXP_FCF 0x01000000
142#define PAS_MAC_CFG_TXP_FCE 0x00800000
143#define PAS_MAC_CFG_TXP_FC 0x00400000
144#define PAS_MAC_CFG_TXP_FPC_M 0x00300000
145#define PAS_MAC_CFG_TXP_FPC_S 20
146#define PAS_MAC_CFG_TXP_FPC(x) (((x) << PAS_MAC_CFG_TXP_FPC_S) & \
147 PAS_MAC_CFG_TXP_FPC_M)
148#define PAS_MAC_CFG_TXP_RT 0x00080000
149#define PAS_MAC_CFG_TXP_BL 0x00040000
150#define PAS_MAC_CFG_TXP_SL_M 0x00030000
151#define PAS_MAC_CFG_TXP_SL_S 16
152#define PAS_MAC_CFG_TXP_SL(x) (((x) << PAS_MAC_CFG_TXP_SL_S) & \
153 PAS_MAC_CFG_TXP_SL_M)
154#define PAS_MAC_CFG_TXP_COB_M 0x0000f000
155#define PAS_MAC_CFG_TXP_COB_S 12
156#define PAS_MAC_CFG_TXP_COB(x) (((x) << PAS_MAC_CFG_TXP_COB_S) & \
157 PAS_MAC_CFG_TXP_COB_M)
158#define PAS_MAC_CFG_TXP_TIFT_M 0x00000f00
159#define PAS_MAC_CFG_TXP_TIFT_S 8
160#define PAS_MAC_CFG_TXP_TIFT(x) (((x) << PAS_MAC_CFG_TXP_TIFT_S) & \
161 PAS_MAC_CFG_TXP_TIFT_M)
162#define PAS_MAC_CFG_TXP_TIFG_M 0x000000ff
163#define PAS_MAC_CFG_TXP_TIFG_S 0
164#define PAS_MAC_CFG_TXP_TIFG(x) (((x) << PAS_MAC_CFG_TXP_TIFG_S) & \
165 PAS_MAC_CFG_TXP_TIFG_M)
166
167#define PAS_MAC_IPC_CHNL_DCHNO_M 0x003f0000
168#define PAS_MAC_IPC_CHNL_DCHNO_S 16
169#define PAS_MAC_IPC_CHNL_DCHNO(x) (((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \
170 PAS_MAC_IPC_CHNL_DCHNO_M)
171#define PAS_MAC_IPC_CHNL_BCH_M 0x0000003f
172#define PAS_MAC_IPC_CHNL_BCH_S 0
173#define PAS_MAC_IPC_CHNL_BCH(x) (((x) << PAS_MAC_IPC_CHNL_BCH_S) & \
174 PAS_MAC_IPC_CHNL_BCH_M)
175
176/* All these registers live in the PCI configuration space for the DMA PCI
177 * device. Use the normal PCI config access functions for them.
178 */
179enum {
180 PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */
181 PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */
182 PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */
183 PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */
184};
185#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */
186#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */
187#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */
188#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */
189
190
191/* Per-interface and per-channel registers */
192#define _PAS_DMA_RXINT_STRIDE 0x20
193#define PAS_DMA_RXINT_RCMDSTA(i) (0x200+(i)*_PAS_DMA_RXINT_STRIDE)
194#define PAS_DMA_RXINT_RCMDSTA_EN 0x00000001
195#define PAS_DMA_RXINT_RCMDSTA_ST 0x00000002
196#define PAS_DMA_RXINT_RCMDSTA_OO 0x00000100
197#define PAS_DMA_RXINT_RCMDSTA_BP 0x00000200
198#define PAS_DMA_RXINT_RCMDSTA_DR 0x00000400
199#define PAS_DMA_RXINT_RCMDSTA_BT 0x00000800
200#define PAS_DMA_RXINT_RCMDSTA_TB 0x00001000
201#define PAS_DMA_RXINT_RCMDSTA_ACT 0x00010000
202#define PAS_DMA_RXINT_RCMDSTA_DROPS_M 0xfffe0000
203#define PAS_DMA_RXINT_RCMDSTA_DROPS_S 17
204#define PAS_DMA_RXINT_INCR(i) (0x210+(i)*_PAS_DMA_RXINT_STRIDE)
205#define PAS_DMA_RXINT_INCR_INCR_M 0x0000ffff
206#define PAS_DMA_RXINT_INCR_INCR_S 0
207#define PAS_DMA_RXINT_INCR_INCR(x) ((x) & 0x0000ffff)
208#define PAS_DMA_RXINT_BASEL(i) (0x218+(i)*_PAS_DMA_RXINT_STRIDE)
209#define PAS_DMA_RXINT_BASEL_BRBL(x) ((x) & ~0x3f)
210#define PAS_DMA_RXINT_BASEU(i) (0x21c+(i)*_PAS_DMA_RXINT_STRIDE)
211#define PAS_DMA_RXINT_BASEU_BRBH(x) ((x) & 0xfff)
212#define PAS_DMA_RXINT_BASEU_SIZ_M 0x3fff0000 /* # of cache lines worth of buffer ring */
213#define PAS_DMA_RXINT_BASEU_SIZ_S 16 /* 0 = 16K */
214#define PAS_DMA_RXINT_BASEU_SIZ(x) (((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \
215 PAS_DMA_RXINT_BASEU_SIZ_M)
216
217
218#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */
219#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */
220#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */
221#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */
222#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */
223#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */
224#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */
225#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */
226#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE)
227#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */
228#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */
229#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */
230#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
231#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */
232#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c
233#define PAS_DMA_TXCHAN_CFG_TATTR_S 2
234#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
235 PAS_DMA_TXCHAN_CFG_TATTR_M)
236#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0
237#define PAS_DMA_TXCHAN_CFG_WT_S 6
238#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
239 PAS_DMA_TXCHAN_CFG_WT_M)
240#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */
241#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */
242#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */
243#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE)
244#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE)
245#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0
246#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0
247#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \
248 PAS_DMA_TXCHAN_BASEL_BRBL_M)
249#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE)
250#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff
251#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0
252#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \
253 PAS_DMA_TXCHAN_BASEU_BRBH_M)
254/* # of cache lines worth of buffer ring */
255#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000
256#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
257#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \
258 PAS_DMA_TXCHAN_BASEU_SIZ_M)
259
260#define _PAS_DMA_RXCHAN_STRIDE 0x20 /* Size per channel */
261#define _PAS_DMA_RXCHAN_CCMDSTA 0x800 /* Command / Status */
262#define _PAS_DMA_RXCHAN_CFG 0x804 /* Configuration */
263#define _PAS_DMA_RXCHAN_INCR 0x810 /* Descriptor increment */
264#define _PAS_DMA_RXCHAN_CNT 0x814 /* Descriptor count/offset */
265#define _PAS_DMA_RXCHAN_BASEL 0x818 /* Descriptor ring base (low) */
266#define _PAS_DMA_RXCHAN_BASEU 0x81c /* (high) */
267#define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE)
268#define PAS_DMA_RXCHAN_CCMDSTA_EN 0x00000001 /* Enabled */
269#define PAS_DMA_RXCHAN_CCMDSTA_ST 0x00000002 /* Stop interface */
270#define PAS_DMA_RXCHAN_CCMDSTA_ACT 0x00010000 /* Active */
271#define PAS_DMA_RXCHAN_CCMDSTA_DU 0x00020000
272#define PAS_DMA_RXCHAN_CFG(c) (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE)
273#define PAS_DMA_RXCHAN_CFG_HBU_M 0x00000380
274#define PAS_DMA_RXCHAN_CFG_HBU_S 7
275#define PAS_DMA_RXCHAN_CFG_HBU(x) (((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \
276 PAS_DMA_RXCHAN_CFG_HBU_M)
277#define PAS_DMA_RXCHAN_INCR(c) (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE)
278#define PAS_DMA_RXCHAN_BASEL(c) (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE)
279#define PAS_DMA_RXCHAN_BASEL_BRBL_M 0xffffffc0
280#define PAS_DMA_RXCHAN_BASEL_BRBL_S 0
281#define PAS_DMA_RXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \
282 PAS_DMA_RXCHAN_BASEL_BRBL_M)
283#define PAS_DMA_RXCHAN_BASEU(c) (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE)
284#define PAS_DMA_RXCHAN_BASEU_BRBH_M 0x00000fff
285#define PAS_DMA_RXCHAN_BASEU_BRBH_S 0
286#define PAS_DMA_RXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \
287 PAS_DMA_RXCHAN_BASEU_BRBH_M)
288/* # of cache lines worth of buffer ring */
289#define PAS_DMA_RXCHAN_BASEU_SIZ_M 0x3fff0000
290#define PAS_DMA_RXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
291#define PAS_DMA_RXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \
292 PAS_DMA_RXCHAN_BASEU_SIZ_M)
293
294#define PAS_STATUS_PCNT_M 0x000000000000ffffull
295#define PAS_STATUS_PCNT_S 0
296#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull
297#define PAS_STATUS_DCNT_S 16
298#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull
299#define PAS_STATUS_BPCNT_S 32
300#define PAS_STATUS_TIMER 0x1000000000000000ull
301#define PAS_STATUS_ERROR 0x2000000000000000ull
302#define PAS_STATUS_SOFT 0x4000000000000000ull
303#define PAS_STATUS_INT 0x8000000000000000ull
304
305#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4)
306#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff
307#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0
308#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \
309 PAS_IOB_DMA_RXCH_CFG_CNTTH_M)
310#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4)
311#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff
312#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0
313#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \
314 PAS_IOB_DMA_TXCH_CFG_CNTTH_M)
315#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4)
316#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000
317#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff
318#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0
319#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\
320 PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
321#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4)
322#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000
323#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff
324#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0
325#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\
326 PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
327#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4)
328#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000
329#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 0
330#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \
331 PAS_IOB_DMA_RXCH_RESET_PCNT_M)
332#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020
333#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010
334#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008
335#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004
336#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002
337#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001
338#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4)
339#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000
340#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 0
341#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \
342 PAS_IOB_DMA_TXCH_RESET_PCNT_M)
343#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020
344#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010
345#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008
346#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004
347#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002
348#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001
349
350#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700
351#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff
352#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0
353#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \
354 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M)
355
356/* Transmit descriptor fields */
357#define XCT_MACTX_T 0x8000000000000000ull
358#define XCT_MACTX_ST 0x4000000000000000ull
359#define XCT_MACTX_NORES 0x0000000000000000ull
360#define XCT_MACTX_8BRES 0x1000000000000000ull
361#define XCT_MACTX_24BRES 0x2000000000000000ull
362#define XCT_MACTX_40BRES 0x3000000000000000ull
363#define XCT_MACTX_I 0x0800000000000000ull
364#define XCT_MACTX_O 0x0400000000000000ull
365#define XCT_MACTX_E 0x0200000000000000ull
366#define XCT_MACTX_VLAN_M 0x0180000000000000ull
367#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull
368#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull
369#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull
370#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull
371#define XCT_MACTX_CRC_M 0x0060000000000000ull
372#define XCT_MACTX_CRC_NOP 0x0000000000000000ull
373#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull
374#define XCT_MACTX_CRC_PAD 0x0040000000000000ull
375#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull
376#define XCT_MACTX_SS 0x0010000000000000ull
377#define XCT_MACTX_LLEN_M 0x00007fff00000000ull
378#define XCT_MACTX_LLEN_S 32ull
379#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \
380 XCT_MACTX_LLEN_M)
381#define XCT_MACTX_IPH_M 0x00000000f8000000ull
382#define XCT_MACTX_IPH_S 27ull
383#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \
384 XCT_MACTX_IPH_M)
385#define XCT_MACTX_IPO_M 0x0000000007c00000ull
386#define XCT_MACTX_IPO_S 22ull
387#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \
388 XCT_MACTX_IPO_M)
389#define XCT_MACTX_CSUM_M 0x0000000000000060ull
390#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull
391#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull
392#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull
393#define XCT_MACTX_V6 0x0000000000000010ull
394#define XCT_MACTX_C 0x0000000000000004ull
395#define XCT_MACTX_AL2 0x0000000000000002ull
396
397/* Receive descriptor fields */
398#define XCT_MACRX_T 0x8000000000000000ull
399#define XCT_MACRX_ST 0x4000000000000000ull
400#define XCT_MACRX_NORES 0x0000000000000000ull
401#define XCT_MACRX_8BRES 0x1000000000000000ull
402#define XCT_MACRX_24BRES 0x2000000000000000ull
403#define XCT_MACRX_40BRES 0x3000000000000000ull
404#define XCT_MACRX_O 0x0400000000000000ull
405#define XCT_MACRX_E 0x0200000000000000ull
406#define XCT_MACRX_FF 0x0100000000000000ull
407#define XCT_MACRX_PF 0x0080000000000000ull
408#define XCT_MACRX_OB 0x0040000000000000ull
409#define XCT_MACRX_OD 0x0020000000000000ull
410#define XCT_MACRX_FS 0x0010000000000000ull
411#define XCT_MACRX_NB_M 0x000fc00000000000ull
412#define XCT_MACRX_NB_S 46ULL
413#define XCT_MACRX_NB(x) ((((long)(x)) << XCT_MACRX_NB_S) & \
414 XCT_MACRX_NB_M)
415#define XCT_MACRX_LLEN_M 0x00003fff00000000ull
416#define XCT_MACRX_LLEN_S 32ULL
417#define XCT_MACRX_LLEN(x) ((((long)(x)) << XCT_MACRX_LLEN_S) & \
418 XCT_MACRX_LLEN_M)
419#define XCT_MACRX_CRC 0x0000000080000000ull
420#define XCT_MACRX_LEN_M 0x0000000060000000ull
421#define XCT_MACRX_LEN_TOOSHORT 0x0000000020000000ull
422#define XCT_MACRX_LEN_BELOWMIN 0x0000000040000000ull
423#define XCT_MACRX_LEN_TRUNC 0x0000000060000000ull
424#define XCT_MACRX_CAST_M 0x0000000018000000ull
425#define XCT_MACRX_CAST_UNI 0x0000000000000000ull
426#define XCT_MACRX_CAST_MULTI 0x0000000008000000ull
427#define XCT_MACRX_CAST_BROAD 0x0000000010000000ull
428#define XCT_MACRX_CAST_PAUSE 0x0000000018000000ull
429#define XCT_MACRX_VLC_M 0x0000000006000000ull
430#define XCT_MACRX_FM 0x0000000001000000ull
431#define XCT_MACRX_HTY_M 0x0000000000c00000ull
432#define XCT_MACRX_HTY_IPV4_OK 0x0000000000000000ull
433#define XCT_MACRX_HTY_IPV6 0x0000000000400000ull
434#define XCT_MACRX_HTY_IPV4_BAD 0x0000000000800000ull
435#define XCT_MACRX_HTY_NONIP 0x0000000000c00000ull
436#define XCT_MACRX_IPP_M 0x00000000003f0000ull
437#define XCT_MACRX_IPP_S 16
438#define XCT_MACRX_CSUM_M 0x000000000000ffffull
439#define XCT_MACRX_CSUM_S 0
440
441#define XCT_PTR_T 0x8000000000000000ull
442#define XCT_PTR_LEN_M 0x7ffff00000000000ull
443#define XCT_PTR_LEN_S 44
444#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \
445 XCT_PTR_LEN_M)
446#define XCT_PTR_ADDR_M 0x00000fffffffffffull
447#define XCT_PTR_ADDR_S 0
448#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \
449 XCT_PTR_ADDR_M)
450
451/* Receive interface buffer fields */
452#define XCT_RXB_LEN_M 0x0ffff00000000000ull
453#define XCT_RXB_LEN_S 44
454#define XCT_RXB_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & XCT_PTR_LEN_M)
455#define XCT_RXB_ADDR_M 0x00000fffffffffffull
456#define XCT_RXB_ADDR_S 0
457#define XCT_RXB_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & XCT_PTR_ADDR_M)
458
459
460#endif /* PASEMI_MAC_H */
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 3d1d21035dec..7098961cc869 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2066,6 +2066,8 @@
2066#define PCI_VENDOR_ID_TDI 0x192E 2066#define PCI_VENDOR_ID_TDI 0x192E
2067#define PCI_DEVICE_ID_TDI_EHCI 0x0101 2067#define PCI_DEVICE_ID_TDI_EHCI 0x0101
2068 2068
2069#define PCI_VENDOR_ID_PASEMI 0x1959
2070
2069#define PCI_VENDOR_ID_JMICRON 0x197B 2071#define PCI_VENDOR_ID_JMICRON 0x197B
2070#define PCI_DEVICE_ID_JMICRON_JMB360 0x2360 2072#define PCI_DEVICE_ID_JMICRON_JMB360 0x2360
2071#define PCI_DEVICE_ID_JMICRON_JMB361 0x2361 2073#define PCI_DEVICE_ID_JMICRON_JMB361 0x2361
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-23 22:30:09 -0400