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authorJason Wessel <jason.wessel@windriver.com>2009-08-20 16:39:48 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2009-09-23 09:46:38 -0400
commitdf6c516900d48df3581b23d37d6516a22ec4f2ca (patch)
treed1210b893b7ba69d8694e6022c47764134a79ae7
parentfd4f3a931f6e047e88bc8c6023666acad957109a (diff)
USB: ehci,dbgp,early_printk: split ehci debug driver from early_printk.c
Move the dbgp early printk driver in advance of refactoring and adding new code, so the changes to this code are tracked separately from the move of the code. The drivers/usb/early directory will be the location of the current and future early usb code for driving usb devices prior initializing the standard interrupt driven USB drivers. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: "Eric W. Biederman" <ebiederm@xmission.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat
-rw-r--r--arch/x86/kernel/early_printk.c715
-rw-r--r--drivers/usb/Makefile1
-rw-r--r--drivers/usb/early/Makefile5
-rw-r--r--drivers/usb/early/ehci-dbgp.c723
-rw-r--r--include/linux/usb/ehci_def.h6
5 files changed, 735 insertions, 715 deletions
diff --git a/arch/x86/kernel/early_printk.c b/arch/x86/kernel/early_printk.c
index b11cab3c323a..519a5e10be53 100644
--- a/arch/x86/kernel/early_printk.c
+++ b/arch/x86/kernel/early_printk.c
@@ -160,721 +160,6 @@ static struct console early_serial_console = {
160 .index = -1, 160 .index = -1,
161}; 161};
162 162
163#ifdef CONFIG_EARLY_PRINTK_DBGP
164
165static struct ehci_caps __iomem *ehci_caps;
166static struct ehci_regs __iomem *ehci_regs;
167static struct ehci_dbg_port __iomem *ehci_debug;
168static unsigned int dbgp_endpoint_out;
169
170struct ehci_dev {
171 u32 bus;
172 u32 slot;
173 u32 func;
174};
175
176static struct ehci_dev ehci_dev;
177
178#define USB_DEBUG_DEVNUM 127
179
180#define DBGP_DATA_TOGGLE 0x8800
181
182static inline u32 dbgp_pid_update(u32 x, u32 tok)
183{
184 return ((x ^ DBGP_DATA_TOGGLE) & 0xffff00) | (tok & 0xff);
185}
186
187static inline u32 dbgp_len_update(u32 x, u32 len)
188{
189 return (x & ~0x0f) | (len & 0x0f);
190}
191
192/*
193 * USB Packet IDs (PIDs)
194 */
195
196/* token */
197#define USB_PID_OUT 0xe1
198#define USB_PID_IN 0x69
199#define USB_PID_SOF 0xa5
200#define USB_PID_SETUP 0x2d
201/* handshake */
202#define USB_PID_ACK 0xd2
203#define USB_PID_NAK 0x5a
204#define USB_PID_STALL 0x1e
205#define USB_PID_NYET 0x96
206/* data */
207#define USB_PID_DATA0 0xc3
208#define USB_PID_DATA1 0x4b
209#define USB_PID_DATA2 0x87
210#define USB_PID_MDATA 0x0f
211/* Special */
212#define USB_PID_PREAMBLE 0x3c
213#define USB_PID_ERR 0x3c
214#define USB_PID_SPLIT 0x78
215#define USB_PID_PING 0xb4
216#define USB_PID_UNDEF_0 0xf0
217
218#define USB_PID_DATA_TOGGLE 0x88
219#define DBGP_CLAIM (DBGP_OWNER | DBGP_ENABLED | DBGP_INUSE)
220
221#define PCI_CAP_ID_EHCI_DEBUG 0xa
222
223#define HUB_ROOT_RESET_TIME 50 /* times are in msec */
224#define HUB_SHORT_RESET_TIME 10
225#define HUB_LONG_RESET_TIME 200
226#define HUB_RESET_TIMEOUT 500
227
228#define DBGP_MAX_PACKET 8
229
230static int dbgp_wait_until_complete(void)
231{
232 u32 ctrl;
233 int loop = 0x100000;
234
235 do {
236 ctrl = readl(&ehci_debug->control);
237 /* Stop when the transaction is finished */
238 if (ctrl & DBGP_DONE)
239 break;
240 } while (--loop > 0);
241
242 if (!loop)
243 return -1;
244
245 /*
246 * Now that we have observed the completed transaction,
247 * clear the done bit.
248 */
249 writel(ctrl | DBGP_DONE, &ehci_debug->control);
250 return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
251}
252
253static void __init dbgp_mdelay(int ms)
254{
255 int i;
256
257 while (ms--) {
258 for (i = 0; i < 1000; i++)
259 outb(0x1, 0x80);
260 }
261}
262
263static void dbgp_breath(void)
264{
265 /* Sleep to give the debug port a chance to breathe */
266}
267
268static int dbgp_wait_until_done(unsigned ctrl)
269{
270 u32 pids, lpid;
271 int ret;
272 int loop = 3;
273
274retry:
275 writel(ctrl | DBGP_GO, &ehci_debug->control);
276 ret = dbgp_wait_until_complete();
277 pids = readl(&ehci_debug->pids);
278 lpid = DBGP_PID_GET(pids);
279
280 if (ret < 0)
281 return ret;
282
283 /*
284 * If the port is getting full or it has dropped data
285 * start pacing ourselves, not necessary but it's friendly.
286 */
287 if ((lpid == USB_PID_NAK) || (lpid == USB_PID_NYET))
288 dbgp_breath();
289
290 /* If I get a NACK reissue the transmission */
291 if (lpid == USB_PID_NAK) {
292 if (--loop > 0)
293 goto retry;
294 }
295
296 return ret;
297}
298
299static void dbgp_set_data(const void *buf, int size)
300{
301 const unsigned char *bytes = buf;
302 u32 lo, hi;
303 int i;
304
305 lo = hi = 0;
306 for (i = 0; i < 4 && i < size; i++)
307 lo |= bytes[i] << (8*i);
308 for (; i < 8 && i < size; i++)
309 hi |= bytes[i] << (8*(i - 4));
310 writel(lo, &ehci_debug->data03);
311 writel(hi, &ehci_debug->data47);
312}
313
314static void __init dbgp_get_data(void *buf, int size)
315{
316 unsigned char *bytes = buf;
317 u32 lo, hi;
318 int i;
319
320 lo = readl(&ehci_debug->data03);
321 hi = readl(&ehci_debug->data47);
322 for (i = 0; i < 4 && i < size; i++)
323 bytes[i] = (lo >> (8*i)) & 0xff;
324 for (; i < 8 && i < size; i++)
325 bytes[i] = (hi >> (8*(i - 4))) & 0xff;
326}
327
328static int dbgp_bulk_write(unsigned devnum, unsigned endpoint,
329 const char *bytes, int size)
330{
331 u32 pids, addr, ctrl;
332 int ret;
333
334 if (size > DBGP_MAX_PACKET)
335 return -1;
336
337 addr = DBGP_EPADDR(devnum, endpoint);
338
339 pids = readl(&ehci_debug->pids);
340 pids = dbgp_pid_update(pids, USB_PID_OUT);
341
342 ctrl = readl(&ehci_debug->control);
343 ctrl = dbgp_len_update(ctrl, size);
344 ctrl |= DBGP_OUT;
345 ctrl |= DBGP_GO;
346
347 dbgp_set_data(bytes, size);
348 writel(addr, &ehci_debug->address);
349 writel(pids, &ehci_debug->pids);
350
351 ret = dbgp_wait_until_done(ctrl);
352 if (ret < 0)
353 return ret;
354
355 return ret;
356}
357
358static int __init dbgp_bulk_read(unsigned devnum, unsigned endpoint, void *data,
359 int size)
360{
361 u32 pids, addr, ctrl;
362 int ret;
363
364 if (size > DBGP_MAX_PACKET)
365 return -1;
366
367 addr = DBGP_EPADDR(devnum, endpoint);
368
369 pids = readl(&ehci_debug->pids);
370 pids = dbgp_pid_update(pids, USB_PID_IN);
371
372 ctrl = readl(&ehci_debug->control);
373 ctrl = dbgp_len_update(ctrl, size);
374 ctrl &= ~DBGP_OUT;
375 ctrl |= DBGP_GO;
376
377 writel(addr, &ehci_debug->address);
378 writel(pids, &ehci_debug->pids);
379 ret = dbgp_wait_until_done(ctrl);
380 if (ret < 0)
381 return ret;
382
383 if (size > ret)
384 size = ret;
385 dbgp_get_data(data, size);
386 return ret;
387}
388
389static int __init dbgp_control_msg(unsigned devnum, int requesttype,
390 int request, int value, int index, void *data, int size)
391{
392 u32 pids, addr, ctrl;
393 struct usb_ctrlrequest req;
394 int read;
395 int ret;
396
397 read = (requesttype & USB_DIR_IN) != 0;
398 if (size > (read ? DBGP_MAX_PACKET:0))
399 return -1;
400
401 /* Compute the control message */
402 req.bRequestType = requesttype;
403 req.bRequest = request;
404 req.wValue = cpu_to_le16(value);
405 req.wIndex = cpu_to_le16(index);
406 req.wLength = cpu_to_le16(size);
407
408 pids = DBGP_PID_SET(USB_PID_DATA0, USB_PID_SETUP);
409 addr = DBGP_EPADDR(devnum, 0);
410
411 ctrl = readl(&ehci_debug->control);
412 ctrl = dbgp_len_update(ctrl, sizeof(req));
413 ctrl |= DBGP_OUT;
414 ctrl |= DBGP_GO;
415
416 /* Send the setup message */
417 dbgp_set_data(&req, sizeof(req));
418 writel(addr, &ehci_debug->address);
419 writel(pids, &ehci_debug->pids);
420 ret = dbgp_wait_until_done(ctrl);
421 if (ret < 0)
422 return ret;
423
424 /* Read the result */
425 return dbgp_bulk_read(devnum, 0, data, size);
426}
427
428
429/* Find a PCI capability */
430static u32 __init find_cap(u32 num, u32 slot, u32 func, int cap)
431{
432 u8 pos;
433 int bytes;
434
435 if (!(read_pci_config_16(num, slot, func, PCI_STATUS) &
436 PCI_STATUS_CAP_LIST))
437 return 0;
438
439 pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST);
440 for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
441 u8 id;
442
443 pos &= ~3;
444 id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID);
445 if (id == 0xff)
446 break;
447 if (id == cap)
448 return pos;
449
450 pos = read_pci_config_byte(num, slot, func,
451 pos+PCI_CAP_LIST_NEXT);
452 }
453 return 0;
454}
455
456static u32 __init __find_dbgp(u32 bus, u32 slot, u32 func)
457{
458 u32 class;
459
460 class = read_pci_config(bus, slot, func, PCI_CLASS_REVISION);
461 if ((class >> 8) != PCI_CLASS_SERIAL_USB_EHCI)
462 return 0;
463
464 return find_cap(bus, slot, func, PCI_CAP_ID_EHCI_DEBUG);
465}
466
467static u32 __init find_dbgp(int ehci_num, u32 *rbus, u32 *rslot, u32 *rfunc)
468{
469 u32 bus, slot, func;
470
471 for (bus = 0; bus < 256; bus++) {
472 for (slot = 0; slot < 32; slot++) {
473 for (func = 0; func < 8; func++) {
474 unsigned cap;
475
476 cap = __find_dbgp(bus, slot, func);
477
478 if (!cap)
479 continue;
480 if (ehci_num-- != 0)
481 continue;
482 *rbus = bus;
483 *rslot = slot;
484 *rfunc = func;
485 return cap;
486 }
487 }
488 }
489 return 0;
490}
491
492static int __init ehci_reset_port(int port)
493{
494 u32 portsc;
495 u32 delay_time, delay;
496 int loop;
497
498 /* Reset the usb debug port */
499 portsc = readl(&ehci_regs->port_status[port - 1]);
500 portsc &= ~PORT_PE;
501 portsc |= PORT_RESET;
502 writel(portsc, &ehci_regs->port_status[port - 1]);
503
504 delay = HUB_ROOT_RESET_TIME;
505 for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT;
506 delay_time += delay) {
507 dbgp_mdelay(delay);
508
509 portsc = readl(&ehci_regs->port_status[port - 1]);
510 if (portsc & PORT_RESET) {
511 /* force reset to complete */
512 loop = 2;
513 writel(portsc & ~(PORT_RWC_BITS | PORT_RESET),
514 &ehci_regs->port_status[port - 1]);
515 do {
516 portsc = readl(&ehci_regs->port_status[port-1]);
517 } while ((portsc & PORT_RESET) && (--loop > 0));
518 }
519
520 /* Device went away? */
521 if (!(portsc & PORT_CONNECT))
522 return -ENOTCONN;
523
524 /* bomb out completely if something weird happend */
525 if ((portsc & PORT_CSC))
526 return -EINVAL;
527
528 /* If we've finished resetting, then break out of the loop */
529 if (!(portsc & PORT_RESET) && (portsc & PORT_PE))
530 return 0;
531 }
532 return -EBUSY;
533}
534
535static int __init ehci_wait_for_port(int port)
536{
537 u32 status;
538 int ret, reps;
539
540 for (reps = 0; reps < 3; reps++) {
541 dbgp_mdelay(100);
542 status = readl(&ehci_regs->status);
543 if (status & STS_PCD) {
544 ret = ehci_reset_port(port);
545 if (ret == 0)
546 return 0;
547 }
548 }
549 return -ENOTCONN;
550}
551
552#ifdef DBGP_DEBUG
553# define dbgp_printk early_printk
554#else
555static inline void dbgp_printk(const char *fmt, ...) { }
556#endif
557
558typedef void (*set_debug_port_t)(int port);
559
560static void __init default_set_debug_port(int port)
561{
562}
563
564static set_debug_port_t __initdata set_debug_port = default_set_debug_port;
565
566static void __init nvidia_set_debug_port(int port)
567{
568 u32 dword;
569 dword = read_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func,
570 0x74);
571 dword &= ~(0x0f<<12);
572 dword |= ((port & 0x0f)<<12);
573 write_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func, 0x74,
574 dword);
575 dbgp_printk("set debug port to %d\n", port);
576}
577
578static void __init detect_set_debug_port(void)
579{
580 u32 vendorid;
581
582 vendorid = read_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func,
583 0x00);
584
585 if ((vendorid & 0xffff) == 0x10de) {
586 dbgp_printk("using nvidia set_debug_port\n");
587 set_debug_port = nvidia_set_debug_port;
588 }
589}
590
591static int __init ehci_setup(void)
592{
593 struct usb_debug_descriptor dbgp_desc;
594 u32 cmd, ctrl, status, portsc, hcs_params;
595 u32 debug_port, new_debug_port = 0, n_ports;
596 u32 devnum;
597 int ret, i;
598 int loop;
599 int port_map_tried;
600 int playtimes = 3;
601
602try_next_time:
603 port_map_tried = 0;
604
605try_next_port:
606
607 hcs_params = readl(&ehci_caps->hcs_params);
608 debug_port = HCS_DEBUG_PORT(hcs_params);
609 n_ports = HCS_N_PORTS(hcs_params);
610
611 dbgp_printk("debug_port: %d\n", debug_port);
612 dbgp_printk("n_ports: %d\n", n_ports);
613
614 for (i = 1; i <= n_ports; i++) {
615 portsc = readl(&ehci_regs->port_status[i-1]);
616 dbgp_printk("portstatus%d: %08x\n", i, portsc);
617 }
618
619 if (port_map_tried && (new_debug_port != debug_port)) {
620 if (--playtimes) {
621 set_debug_port(new_debug_port);
622 goto try_next_time;
623 }
624 return -1;
625 }
626
627 loop = 100000;
628 /* Reset the EHCI controller */
629 cmd = readl(&ehci_regs->command);
630 cmd |= CMD_RESET;
631 writel(cmd, &ehci_regs->command);
632 do {
633 cmd = readl(&ehci_regs->command);
634 } while ((cmd & CMD_RESET) && (--loop > 0));
635
636 if (!loop) {
637 dbgp_printk("can not reset ehci\n");
638 return -1;
639 }
640 dbgp_printk("ehci reset done\n");
641
642 /* Claim ownership, but do not enable yet */
643 ctrl = readl(&ehci_debug->control);
644 ctrl |= DBGP_OWNER;
645 ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
646 writel(ctrl, &ehci_debug->control);
647
648 /* Start the ehci running */
649 cmd = readl(&ehci_regs->command);
650 cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
651 cmd |= CMD_RUN;
652 writel(cmd, &ehci_regs->command);
653
654 /* Ensure everything is routed to the EHCI */
655 writel(FLAG_CF, &ehci_regs->configured_flag);
656
657 /* Wait until the controller is no longer halted */
658 loop = 10;
659 do {
660 status = readl(&ehci_regs->status);
661 } while ((status & STS_HALT) && (--loop > 0));
662
663 if (!loop) {
664 dbgp_printk("ehci can be started\n");
665 return -1;
666 }
667 dbgp_printk("ehci started\n");
668
669 /* Wait for a device to show up in the debug port */
670 ret = ehci_wait_for_port(debug_port);
671 if (ret < 0) {
672 dbgp_printk("No device found in debug port\n");
673 goto next_debug_port;
674 }
675 dbgp_printk("ehci wait for port done\n");
676
677 /* Enable the debug port */
678 ctrl = readl(&ehci_debug->control);
679 ctrl |= DBGP_CLAIM;
680 writel(ctrl, &ehci_debug->control);
681 ctrl = readl(&ehci_debug->control);
682 if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
683 dbgp_printk("No device in debug port\n");
684 writel(ctrl & ~DBGP_CLAIM, &ehci_debug->control);
685 goto err;
686 }
687 dbgp_printk("debug ported enabled\n");
688
689 /* Completely transfer the debug device to the debug controller */
690 portsc = readl(&ehci_regs->port_status[debug_port - 1]);
691 portsc &= ~PORT_PE;
692 writel(portsc, &ehci_regs->port_status[debug_port - 1]);
693
694 dbgp_mdelay(100);
695
696 /* Find the debug device and make it device number 127 */
697 for (devnum = 0; devnum <= 127; devnum++) {
698 ret = dbgp_control_msg(devnum,
699 USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
700 USB_REQ_GET_DESCRIPTOR, (USB_DT_DEBUG << 8), 0,
701 &dbgp_desc, sizeof(dbgp_desc));
702 if (ret > 0)
703 break;
704 }
705 if (devnum > 127) {
706 dbgp_printk("Could not find attached debug device\n");
707 goto err;
708 }
709 if (ret < 0) {
710 dbgp_printk("Attached device is not a debug device\n");
711 goto err;
712 }
713 dbgp_endpoint_out = dbgp_desc.bDebugOutEndpoint;
714
715 /* Move the device to 127 if it isn't already there */
716 if (devnum != USB_DEBUG_DEVNUM) {
717 ret = dbgp_control_msg(devnum,
718 USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
719 USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0);
720 if (ret < 0) {
721 dbgp_printk("Could not move attached device to %d\n",
722 USB_DEBUG_DEVNUM);
723 goto err;
724 }
725 devnum = USB_DEBUG_DEVNUM;
726 dbgp_printk("debug device renamed to 127\n");
727 }
728
729 /* Enable the debug interface */
730 ret = dbgp_control_msg(USB_DEBUG_DEVNUM,
731 USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
732 USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE, 0, NULL, 0);
733 if (ret < 0) {
734 dbgp_printk(" Could not enable the debug device\n");
735 goto err;
736 }
737 dbgp_printk("debug interface enabled\n");
738
739 /* Perform a small write to get the even/odd data state in sync
740 */
741 ret = dbgp_bulk_write(USB_DEBUG_DEVNUM, dbgp_endpoint_out, " ", 1);
742 if (ret < 0) {
743 dbgp_printk("dbgp_bulk_write failed: %d\n", ret);
744 goto err;
745 }
746 dbgp_printk("small write doned\n");
747
748 return 0;
749err:
750 /* Things didn't work so remove my claim */
751 ctrl = readl(&ehci_debug->control);
752 ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
753 writel(ctrl, &ehci_debug->control);
754 return -1;
755
756next_debug_port:
757 port_map_tried |= (1<<(debug_port - 1));
758 new_debug_port = ((debug_port-1+1)%n_ports) + 1;
759 if (port_map_tried != ((1<<n_ports) - 1)) {
760 set_debug_port(new_debug_port);
761 goto try_next_port;
762 }
763 if (--playtimes) {
764 set_debug_port(new_debug_port);
765 goto try_next_time;
766 }
767
768 return -1;
769}
770
771static int __init early_dbgp_init(char *s)
772{
773 u32 debug_port, bar, offset;
774 u32 bus, slot, func, cap;
775 void __iomem *ehci_bar;
776 u32 dbgp_num;
777 u32 bar_val;
778 char *e;
779 int ret;
780 u8 byte;
781
782 if (!early_pci_allowed())
783 return -1;
784
785 dbgp_num = 0;
786 if (*s)
787 dbgp_num = simple_strtoul(s, &e, 10);
788 dbgp_printk("dbgp_num: %d\n", dbgp_num);
789
790 cap = find_dbgp(dbgp_num, &bus, &slot, &func);
791 if (!cap)
792 return -1;
793
794 dbgp_printk("Found EHCI debug port on %02x:%02x.%1x\n", bus, slot,
795 func);
796
797 debug_port = read_pci_config(bus, slot, func, cap);
798 bar = (debug_port >> 29) & 0x7;
799 bar = (bar * 4) + 0xc;
800 offset = (debug_port >> 16) & 0xfff;
801 dbgp_printk("bar: %02x offset: %03x\n", bar, offset);
802 if (bar != PCI_BASE_ADDRESS_0) {
803 dbgp_printk("only debug ports on bar 1 handled.\n");
804
805 return -1;
806 }
807
808 bar_val = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
809 dbgp_printk("bar_val: %02x offset: %03x\n", bar_val, offset);
810 if (bar_val & ~PCI_BASE_ADDRESS_MEM_MASK) {
811 dbgp_printk("only simple 32bit mmio bars supported\n");
812
813 return -1;
814 }
815
816 /* double check if the mem space is enabled */
817 byte = read_pci_config_byte(bus, slot, func, 0x04);
818 if (!(byte & 0x2)) {
819 byte |= 0x02;
820 write_pci_config_byte(bus, slot, func, 0x04, byte);
821 dbgp_printk("mmio for ehci enabled\n");
822 }
823
824 /*
825 * FIXME I don't have the bar size so just guess PAGE_SIZE is more
826 * than enough. 1K is the biggest I have seen.
827 */
828 set_fixmap_nocache(FIX_DBGP_BASE, bar_val & PAGE_MASK);
829 ehci_bar = (void __iomem *)__fix_to_virt(FIX_DBGP_BASE);
830 ehci_bar += bar_val & ~PAGE_MASK;
831 dbgp_printk("ehci_bar: %p\n", ehci_bar);
832
833 ehci_caps = ehci_bar;
834 ehci_regs = ehci_bar + HC_LENGTH(readl(&ehci_caps->hc_capbase));
835 ehci_debug = ehci_bar + offset;
836 ehci_dev.bus = bus;
837 ehci_dev.slot = slot;
838 ehci_dev.func = func;
839
840 detect_set_debug_port();
841
842 ret = ehci_setup();
843 if (ret < 0) {
844 dbgp_printk("ehci_setup failed\n");
845 ehci_debug = NULL;
846
847 return -1;
848 }
849
850 return 0;
851}
852
853static void early_dbgp_write(struct console *con, const char *str, u32 n)
854{
855 int chunk, ret;
856
857 if (!ehci_debug)
858 return;
859 while (n > 0) {
860 chunk = n;
861 if (chunk > DBGP_MAX_PACKET)
862 chunk = DBGP_MAX_PACKET;
863 ret = dbgp_bulk_write(USB_DEBUG_DEVNUM,
864 dbgp_endpoint_out, str, chunk);
865 str += chunk;
866 n -= chunk;
867 }
868}
869
870static struct console early_dbgp_console = {
871 .name = "earlydbg",
872 .write = early_dbgp_write,
873 .flags = CON_PRINTBUFFER,
874 .index = -1,
875};
876#endif
877
878/* Direct interface for emergencies */ 163/* Direct interface for emergencies */
879static struct console *early_console = &early_vga_console; 164static struct console *early_console = &early_vga_console;
880static int __initdata early_console_initialized; 165static int __initdata early_console_initialized;
diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
index dbe4fb694ad2..be3c9b80bc9f 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_USB_MICROTEK) += image/
40obj-$(CONFIG_USB_SERIAL) += serial/ 40obj-$(CONFIG_USB_SERIAL) += serial/
41 41
42obj-$(CONFIG_USB) += misc/ 42obj-$(CONFIG_USB) += misc/
43obj-y += early/
43 44
44obj-$(CONFIG_USB_ATM) += atm/ 45obj-$(CONFIG_USB_ATM) += atm/
45obj-$(CONFIG_USB_SPEEDTOUCH) += atm/ 46obj-$(CONFIG_USB_SPEEDTOUCH) += atm/
diff --git a/drivers/usb/early/Makefile b/drivers/usb/early/Makefile
new file mode 100644
index 000000000000..dfedee8c45b6
--- /dev/null
+++ b/drivers/usb/early/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for early USB devices
3#
4
5obj-$(CONFIG_EARLY_PRINTK_DBGP) += ehci-dbgp.o
diff --git a/drivers/usb/early/ehci-dbgp.c b/drivers/usb/early/ehci-dbgp.c
new file mode 100644
index 000000000000..821b7b21c29c
--- /dev/null
+++ b/drivers/usb/early/ehci-dbgp.c
@@ -0,0 +1,723 @@
1#include <linux/console.h>
2#include <linux/errno.h>
3#include <linux/pci_regs.h>
4#include <linux/pci_ids.h>
5#include <linux/usb/ch9.h>
6#include <linux/usb/ehci_def.h>
7#include <linux/delay.h>
8#include <asm/io.h>
9#include <asm/pci-direct.h>
10#include <asm/fixmap.h>
11
12static struct ehci_caps __iomem *ehci_caps;
13static struct ehci_regs __iomem *ehci_regs;
14static struct ehci_dbg_port __iomem *ehci_debug;
15static unsigned int dbgp_endpoint_out;
16
17struct ehci_dev {
18 u32 bus;
19 u32 slot;
20 u32 func;
21};
22
23static struct ehci_dev ehci_dev;
24
25#define USB_DEBUG_DEVNUM 127
26
27#define DBGP_DATA_TOGGLE 0x8800
28
29static inline u32 dbgp_pid_update(u32 x, u32 tok)
30{
31 return ((x ^ DBGP_DATA_TOGGLE) & 0xffff00) | (tok & 0xff);
32}
33
34static inline u32 dbgp_len_update(u32 x, u32 len)
35{
36 return (x & ~0x0f) | (len & 0x0f);
37}
38
39/*
40 * USB Packet IDs (PIDs)
41 */
42
43/* token */
44#define USB_PID_OUT 0xe1
45#define USB_PID_IN 0x69
46#define USB_PID_SOF 0xa5
47#define USB_PID_SETUP 0x2d
48/* handshake */
49#define USB_PID_ACK 0xd2
50#define USB_PID_NAK 0x5a
51#define USB_PID_STALL 0x1e
52#define USB_PID_NYET 0x96
53/* data */
54#define USB_PID_DATA0 0xc3
55#define USB_PID_DATA1 0x4b
56#define USB_PID_DATA2 0x87
57#define USB_PID_MDATA 0x0f
58/* Special */
59#define USB_PID_PREAMBLE 0x3c
60#define USB_PID_ERR 0x3c
61#define USB_PID_SPLIT 0x78
62#define USB_PID_PING 0xb4
63#define USB_PID_UNDEF_0 0xf0
64
65#define USB_PID_DATA_TOGGLE 0x88
66#define DBGP_CLAIM (DBGP_OWNER | DBGP_ENABLED | DBGP_INUSE)
67
68#define PCI_CAP_ID_EHCI_DEBUG 0xa
69
70#define HUB_ROOT_RESET_TIME 50 /* times are in msec */
71#define HUB_SHORT_RESET_TIME 10
72#define HUB_LONG_RESET_TIME 200
73#define HUB_RESET_TIMEOUT 500
74
75#define DBGP_MAX_PACKET 8
76
77static int dbgp_wait_until_complete(void)
78{
79 u32 ctrl;
80 int loop = 0x100000;
81
82 do {
83 ctrl = readl(&ehci_debug->control);
84 /* Stop when the transaction is finished */
85 if (ctrl & DBGP_DONE)
86 break;
87 } while (--loop > 0);
88
89 if (!loop)
90 return -1;
91
92 /*
93 * Now that we have observed the completed transaction,
94 * clear the done bit.
95 */
96 writel(ctrl | DBGP_DONE, &ehci_debug->control);
97 return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
98}
99
100static void __init dbgp_mdelay(int ms)
101{
102 int i;
103
104 while (ms--) {
105 for (i = 0; i < 1000; i++)
106 outb(0x1, 0x80);
107 }
108}
109
110static void dbgp_breath(void)
111{
112 /* Sleep to give the debug port a chance to breathe */
113}
114
115static int dbgp_wait_until_done(unsigned ctrl)
116{
117 u32 pids, lpid;
118 int ret;
119 int loop = 3;
120
121retry:
122 writel(ctrl | DBGP_GO, &ehci_debug->control);
123 ret = dbgp_wait_until_complete();
124 pids = readl(&ehci_debug->pids);
125 lpid = DBGP_PID_GET(pids);
126
127 if (ret < 0)
128 return ret;
129
130 /*
131 * If the port is getting full or it has dropped data
132 * start pacing ourselves, not necessary but it's friendly.
133 */
134 if ((lpid == USB_PID_NAK) || (lpid == USB_PID_NYET))
135 dbgp_breath();
136
137 /* If I get a NACK reissue the transmission */
138 if (lpid == USB_PID_NAK) {
139 if (--loop > 0)
140 goto retry;
141 }
142
143 return ret;
144}
145
146static void dbgp_set_data(const void *buf, int size)
147{
148 const unsigned char *bytes = buf;
149 u32 lo, hi;
150 int i;
151
152 lo = hi = 0;
153 for (i = 0; i < 4 && i < size; i++)
154 lo |= bytes[i] << (8*i);
155 for (; i < 8 && i < size; i++)
156 hi |= bytes[i] << (8*(i - 4));
157 writel(lo, &ehci_debug->data03);
158 writel(hi, &ehci_debug->data47);
159}
160
161static void __init dbgp_get_data(void *buf, int size)
162{
163 unsigned char *bytes = buf;
164 u32 lo, hi;
165 int i;
166
167 lo = readl(&ehci_debug->data03);
168 hi = readl(&ehci_debug->data47);
169 for (i = 0; i < 4 && i < size; i++)
170 bytes[i] = (lo >> (8*i)) & 0xff;
171 for (; i < 8 && i < size; i++)
172 bytes[i] = (hi >> (8*(i - 4))) & 0xff;
173}
174
175static int dbgp_bulk_write(unsigned devnum, unsigned endpoint,
176 const char *bytes, int size)
177{
178 u32 pids, addr, ctrl;
179 int ret;
180
181 if (size > DBGP_MAX_PACKET)
182 return -1;
183
184 addr = DBGP_EPADDR(devnum, endpoint);
185
186 pids = readl(&ehci_debug->pids);
187 pids = dbgp_pid_update(pids, USB_PID_OUT);
188
189 ctrl = readl(&ehci_debug->control);
190 ctrl = dbgp_len_update(ctrl, size);
191 ctrl |= DBGP_OUT;
192 ctrl |= DBGP_GO;
193
194 dbgp_set_data(bytes, size);
195 writel(addr, &ehci_debug->address);
196 writel(pids, &ehci_debug->pids);
197
198 ret = dbgp_wait_until_done(ctrl);
199 if (ret < 0)
200 return ret;
201
202 return ret;
203}
204
205static int __init dbgp_bulk_read(unsigned devnum, unsigned endpoint, void *data,
206 int size)
207{
208 u32 pids, addr, ctrl;
209 int ret;
210
211 if (size > DBGP_MAX_PACKET)
212 return -1;
213
214 addr = DBGP_EPADDR(devnum, endpoint);
215
216 pids = readl(&ehci_debug->pids);
217 pids = dbgp_pid_update(pids, USB_PID_IN);
218
219 ctrl = readl(&ehci_debug->control);
220 ctrl = dbgp_len_update(ctrl, size);
221 ctrl &= ~DBGP_OUT;
222 ctrl |= DBGP_GO;
223
224 writel(addr, &ehci_debug->address);
225 writel(pids, &ehci_debug->pids);
226 ret = dbgp_wait_until_done(ctrl);
227 if (ret < 0)
228 return ret;
229
230 if (size > ret)
231 size = ret;
232 dbgp_get_data(data, size);
233 return ret;
234}
235
236static int __init dbgp_control_msg(unsigned devnum, int requesttype,
237 int request, int value, int index, void *data, int size)
238{
239 u32 pids, addr, ctrl;
240 struct usb_ctrlrequest req;
241 int read;
242 int ret;
243
244 read = (requesttype & USB_DIR_IN) != 0;
245 if (size > (read ? DBGP_MAX_PACKET:0))
246 return -1;
247
248 /* Compute the control message */
249 req.bRequestType = requesttype;
250 req.bRequest = request;
251 req.wValue = cpu_to_le16(value);
252 req.wIndex = cpu_to_le16(index);
253 req.wLength = cpu_to_le16(size);
254
255 pids = DBGP_PID_SET(USB_PID_DATA0, USB_PID_SETUP);
256 addr = DBGP_EPADDR(devnum, 0);
257
258 ctrl = readl(&ehci_debug->control);
259 ctrl = dbgp_len_update(ctrl, sizeof(req));
260 ctrl |= DBGP_OUT;
261 ctrl |= DBGP_GO;
262
263 /* Send the setup message */
264 dbgp_set_data(&req, sizeof(req));
265 writel(addr, &ehci_debug->address);
266 writel(pids, &ehci_debug->pids);
267 ret = dbgp_wait_until_done(ctrl);
268 if (ret < 0)
269 return ret;
270
271 /* Read the result */
272 return dbgp_bulk_read(devnum, 0, data, size);
273}
274
275
276/* Find a PCI capability */
277static u32 __init find_cap(u32 num, u32 slot, u32 func, int cap)
278{
279 u8 pos;
280 int bytes;
281
282 if (!(read_pci_config_16(num, slot, func, PCI_STATUS) &
283 PCI_STATUS_CAP_LIST))
284 return 0;
285
286 pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST);
287 for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
288 u8 id;
289
290 pos &= ~3;
291 id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID);
292 if (id == 0xff)
293 break;
294 if (id == cap)
295 return pos;
296
297 pos = read_pci_config_byte(num, slot, func,
298 pos+PCI_CAP_LIST_NEXT);
299 }
300 return 0;
301}
302
303static u32 __init __find_dbgp(u32 bus, u32 slot, u32 func)
304{
305 u32 class;
306
307 class = read_pci_config(bus, slot, func, PCI_CLASS_REVISION);
308 if ((class >> 8) != PCI_CLASS_SERIAL_USB_EHCI)
309 return 0;
310
311 return find_cap(bus, slot, func, PCI_CAP_ID_EHCI_DEBUG);
312}
313
314static u32 __init find_dbgp(int ehci_num, u32 *rbus, u32 *rslot, u32 *rfunc)
315{
316 u32 bus, slot, func;
317
318 for (bus = 0; bus < 256; bus++) {
319 for (slot = 0; slot < 32; slot++) {
320 for (func = 0; func < 8; func++) {
321 unsigned cap;
322
323 cap = __find_dbgp(bus, slot, func);
324
325 if (!cap)
326 continue;
327 if (ehci_num-- != 0)
328 continue;
329 *rbus = bus;
330 *rslot = slot;
331 *rfunc = func;
332 return cap;
333 }
334 }
335 }
336 return 0;
337}
338
339static int __init ehci_reset_port(int port)
340{
341 u32 portsc;
342 u32 delay_time, delay;
343 int loop;
344
345 /* Reset the usb debug port */
346 portsc = readl(&ehci_regs->port_status[port - 1]);
347 portsc &= ~PORT_PE;
348 portsc |= PORT_RESET;
349 writel(portsc, &ehci_regs->port_status[port - 1]);
350
351 delay = HUB_ROOT_RESET_TIME;
352 for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT;
353 delay_time += delay) {
354 dbgp_mdelay(delay);
355
356 portsc = readl(&ehci_regs->port_status[port - 1]);
357 if (portsc & PORT_RESET) {
358 /* force reset to complete */
359 loop = 2;
360 writel(portsc & ~(PORT_RWC_BITS | PORT_RESET),
361 &ehci_regs->port_status[port - 1]);
362 do {
363 portsc = readl(&ehci_regs->port_status[port-1]);
364 } while ((portsc & PORT_RESET) && (--loop > 0));
365 }
366
367 /* Device went away? */
368 if (!(portsc & PORT_CONNECT))
369 return -ENOTCONN;
370
371 /* bomb out completely if something weird happend */
372 if ((portsc & PORT_CSC))
373 return -EINVAL;
374
375 /* If we've finished resetting, then break out of the loop */
376 if (!(portsc & PORT_RESET) && (portsc & PORT_PE))
377 return 0;
378 }
379 return -EBUSY;
380}
381
382static int __init ehci_wait_for_port(int port)
383{
384 u32 status;
385 int ret, reps;
386
387 for (reps = 0; reps < 3; reps++) {
388 dbgp_mdelay(100);
389 status = readl(&ehci_regs->status);
390 if (status & STS_PCD) {
391 ret = ehci_reset_port(port);
392 if (ret == 0)
393 return 0;
394 }
395 }
396 return -ENOTCONN;
397}
398
399#ifdef DBGP_DEBUG
400# define dbgp_printk early_printk
401#else
402static inline void dbgp_printk(const char *fmt, ...) { }
403#endif
404
405typedef void (*set_debug_port_t)(int port);
406
407static void __init default_set_debug_port(int port)
408{
409}
410
411static set_debug_port_t __initdata set_debug_port = default_set_debug_port;
412
413static void __init nvidia_set_debug_port(int port)
414{
415 u32 dword;
416 dword = read_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func,
417 0x74);
418 dword &= ~(0x0f<<12);
419 dword |= ((port & 0x0f)<<12);
420 write_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func, 0x74,
421 dword);
422 dbgp_printk("set debug port to %d\n", port);
423}
424
425static void __init detect_set_debug_port(void)
426{
427 u32 vendorid;
428
429 vendorid = read_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func,
430 0x00);
431
432 if ((vendorid & 0xffff) == 0x10de) {
433 dbgp_printk("using nvidia set_debug_port\n");
434 set_debug_port = nvidia_set_debug_port;
435 }
436}
437
438static int __init ehci_setup(void)
439{
440 struct usb_debug_descriptor dbgp_desc;
441 u32 cmd, ctrl, status, portsc, hcs_params;
442 u32 debug_port, new_debug_port = 0, n_ports;
443 u32 devnum;
444 int ret, i;
445 int loop;
446 int port_map_tried;
447 int playtimes = 3;
448
449try_next_time:
450 port_map_tried = 0;
451
452try_next_port:
453
454 hcs_params = readl(&ehci_caps->hcs_params);
455 debug_port = HCS_DEBUG_PORT(hcs_params);
456 n_ports = HCS_N_PORTS(hcs_params);
457
458 dbgp_printk("debug_port: %d\n", debug_port);
459 dbgp_printk("n_ports: %d\n", n_ports);
460
461 for (i = 1; i <= n_ports; i++) {
462 portsc = readl(&ehci_regs->port_status[i-1]);
463 dbgp_printk("portstatus%d: %08x\n", i, portsc);
464 }
465
466 if (port_map_tried && (new_debug_port != debug_port)) {
467 if (--playtimes) {
468 set_debug_port(new_debug_port);
469 goto try_next_time;
470 }
471 return -1;
472 }
473
474 loop = 100000;
475 /* Reset the EHCI controller */
476 cmd = readl(&ehci_regs->command);
477 cmd |= CMD_RESET;
478 writel(cmd, &ehci_regs->command);
479 do {
480 cmd = readl(&ehci_regs->command);
481 } while ((cmd & CMD_RESET) && (--loop > 0));
482
483 if (!loop) {
484 dbgp_printk("can not reset ehci\n");
485 return -1;
486 }
487 dbgp_printk("ehci reset done\n");
488
489 /* Claim ownership, but do not enable yet */
490 ctrl = readl(&ehci_debug->control);
491 ctrl |= DBGP_OWNER;
492 ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
493 writel(ctrl, &ehci_debug->control);
494
495 /* Start the ehci running */
496 cmd = readl(&ehci_regs->command);
497 cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
498 cmd |= CMD_RUN;
499 writel(cmd, &ehci_regs->command);
500
501 /* Ensure everything is routed to the EHCI */
502 writel(FLAG_CF, &ehci_regs->configured_flag);
503
504 /* Wait until the controller is no longer halted */
505 loop = 10;
506 do {
507 status = readl(&ehci_regs->status);
508 } while ((status & STS_HALT) && (--loop > 0));
509
510 if (!loop) {
511 dbgp_printk("ehci can be started\n");
512 return -1;
513 }
514 dbgp_printk("ehci started\n");
515
516 /* Wait for a device to show up in the debug port */
517 ret = ehci_wait_for_port(debug_port);
518 if (ret < 0) {
519 dbgp_printk("No device found in debug port\n");
520 goto next_debug_port;
521 }
522 dbgp_printk("ehci wait for port done\n");
523
524 /* Enable the debug port */
525 ctrl = readl(&ehci_debug->control);
526 ctrl |= DBGP_CLAIM;
527 writel(ctrl, &ehci_debug->control);
528 ctrl = readl(&ehci_debug->control);
529 if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
530 dbgp_printk("No device in debug port\n");
531 writel(ctrl & ~DBGP_CLAIM, &ehci_debug->control);
532 goto err;
533 }
534 dbgp_printk("debug ported enabled\n");
535
536 /* Completely transfer the debug device to the debug controller */
537 portsc = readl(&ehci_regs->port_status[debug_port - 1]);
538 portsc &= ~PORT_PE;
539 writel(portsc, &ehci_regs->port_status[debug_port - 1]);
540
541 dbgp_mdelay(100);
542
543 /* Find the debug device and make it device number 127 */
544 for (devnum = 0; devnum <= 127; devnum++) {
545 ret = dbgp_control_msg(devnum,
546 USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
547 USB_REQ_GET_DESCRIPTOR, (USB_DT_DEBUG << 8), 0,
548 &dbgp_desc, sizeof(dbgp_desc));
549 if (ret > 0)
550 break;
551 }
552 if (devnum > 127) {
553 dbgp_printk("Could not find attached debug device\n");
554 goto err;
555 }
556 if (ret < 0) {
557 dbgp_printk("Attached device is not a debug device\n");
558 goto err;
559 }
560 dbgp_endpoint_out = dbgp_desc.bDebugOutEndpoint;
561
562 /* Move the device to 127 if it isn't already there */
563 if (devnum != USB_DEBUG_DEVNUM) {
564 ret = dbgp_control_msg(devnum,
565 USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
566 USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0);
567 if (ret < 0) {
568 dbgp_printk("Could not move attached device to %d\n",
569 USB_DEBUG_DEVNUM);
570 goto err;
571 }
572 devnum = USB_DEBUG_DEVNUM;
573 dbgp_printk("debug device renamed to 127\n");
574 }
575
576 /* Enable the debug interface */
577 ret = dbgp_control_msg(USB_DEBUG_DEVNUM,
578 USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
579 USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE, 0, NULL, 0);
580 if (ret < 0) {
581 dbgp_printk(" Could not enable the debug device\n");
582 goto err;
583 }
584 dbgp_printk("debug interface enabled\n");
585
586 /* Perform a small write to get the even/odd data state in sync
587 */
588 ret = dbgp_bulk_write(USB_DEBUG_DEVNUM, dbgp_endpoint_out, " ", 1);
589 if (ret < 0) {
590 dbgp_printk("dbgp_bulk_write failed: %d\n", ret);
591 goto err;
592 }
593 dbgp_printk("small write doned\n");
594
595 return 0;
596err:
597 /* Things didn't work so remove my claim */
598 ctrl = readl(&ehci_debug->control);
599 ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
600 writel(ctrl, &ehci_debug->control);
601 return -1;
602
603next_debug_port:
604 port_map_tried |= (1<<(debug_port - 1));
605 new_debug_port = ((debug_port-1+1)%n_ports) + 1;
606 if (port_map_tried != ((1<<n_ports) - 1)) {
607 set_debug_port(new_debug_port);
608 goto try_next_port;
609 }
610 if (--playtimes) {
611 set_debug_port(new_debug_port);
612 goto try_next_time;
613 }
614
615 return -1;
616}
617
618int __init early_dbgp_init(char *s)
619{
620 u32 debug_port, bar, offset;
621 u32 bus, slot, func, cap;
622 void __iomem *ehci_bar;
623 u32 dbgp_num;
624 u32 bar_val;
625 char *e;
626 int ret;
627 u8 byte;
628
629 if (!early_pci_allowed())
630 return -1;
631
632 dbgp_num = 0;
633 if (*s)
634 dbgp_num = simple_strtoul(s, &e, 10);
635 dbgp_printk("dbgp_num: %d\n", dbgp_num);
636
637 cap = find_dbgp(dbgp_num, &bus, &slot, &func);
638 if (!cap)
639 return -1;
640
641 dbgp_printk("Found EHCI debug port on %02x:%02x.%1x\n", bus, slot,
642 func);
643
644 debug_port = read_pci_config(bus, slot, func, cap);
645 bar = (debug_port >> 29) & 0x7;
646 bar = (bar * 4) + 0xc;
647 offset = (debug_port >> 16) & 0xfff;
648 dbgp_printk("bar: %02x offset: %03x\n", bar, offset);
649 if (bar != PCI_BASE_ADDRESS_0) {
650 dbgp_printk("only debug ports on bar 1 handled.\n");
651
652 return -1;
653 }
654
655 bar_val = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
656 dbgp_printk("bar_val: %02x offset: %03x\n", bar_val, offset);
657 if (bar_val & ~PCI_BASE_ADDRESS_MEM_MASK) {
658 dbgp_printk("only simple 32bit mmio bars supported\n");
659
660 return -1;
661 }
662
663 /* double check if the mem space is enabled */
664 byte = read_pci_config_byte(bus, slot, func, 0x04);
665 if (!(byte & 0x2)) {
666 byte |= 0x02;
667 write_pci_config_byte(bus, slot, func, 0x04, byte);
668 dbgp_printk("mmio for ehci enabled\n");
669 }
670
671 /*
672 * FIXME I don't have the bar size so just guess PAGE_SIZE is more
673 * than enough. 1K is the biggest I have seen.
674 */
675 set_fixmap_nocache(FIX_DBGP_BASE, bar_val & PAGE_MASK);
676 ehci_bar = (void __iomem *)__fix_to_virt(FIX_DBGP_BASE);
677 ehci_bar += bar_val & ~PAGE_MASK;
678 dbgp_printk("ehci_bar: %p\n", ehci_bar);
679
680 ehci_caps = ehci_bar;
681 ehci_regs = ehci_bar + HC_LENGTH(readl(&ehci_caps->hc_capbase));
682 ehci_debug = ehci_bar + offset;
683 ehci_dev.bus = bus;
684 ehci_dev.slot = slot;
685 ehci_dev.func = func;
686
687 detect_set_debug_port();
688
689 ret = ehci_setup();
690 if (ret < 0) {
691 dbgp_printk("ehci_setup failed\n");
692 ehci_debug = NULL;
693
694 return -1;
695 }
696
697 return 0;
698}
699
700static void early_dbgp_write(struct console *con, const char *str, u32 n)
701{
702 int chunk, ret;
703
704 if (!ehci_debug)
705 return;
706 while (n > 0) {
707 chunk = n;
708 if (chunk > DBGP_MAX_PACKET)
709 chunk = DBGP_MAX_PACKET;
710 ret = dbgp_bulk_write(USB_DEBUG_DEVNUM,
711 dbgp_endpoint_out, str, chunk);
712 str += chunk;
713 n -= chunk;
714 }
715}
716
717struct console early_dbgp_console = {
718 .name = "earlydbg",
719 .write = early_dbgp_write,
720 .flags = CON_PRINTBUFFER,
721 .index = -1,
722};
723
diff --git a/include/linux/usb/ehci_def.h b/include/linux/usb/ehci_def.h
index 4c4b701ff265..1deac2a7b12e 100644
--- a/include/linux/usb/ehci_def.h
+++ b/include/linux/usb/ehci_def.h
@@ -170,4 +170,10 @@ struct ehci_dbg_port {
170#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep)) 170#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
171} __attribute__ ((packed)); 171} __attribute__ ((packed));
172 172
173#ifdef CONFIG_EARLY_PRINTK_DBGP
174#include <linux/init.h>
175extern int __init early_dbgp_init(char *s);
176extern struct console early_dbgp_console;
177#endif /* CONFIG_EARLY_PRINTK_DBGP */
178
173#endif /* __LINUX_USB_EHCI_DEF_H */ 179#endif /* __LINUX_USB_EHCI_DEF_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 13:47:56 -0500