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authorJerome Glisse <jglisse@redhat.com>2010-02-17 16:54:29 -0500
committerDave Airlie <airlied@redhat.com>2010-02-17 23:49:35 -0500
commitd594e46ace22afa1621254f6f669e65430048153 (patch)
treebefd5b54ce1b8284acc4ee450d085a7d2c7b01fd
parent44ca7478d46aaad488d916f7262253e000ee60f9 (diff)
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the computation of vram_start|end & gtt_start|end. For R1XX-R2XX we place VRAM at the same address of PCI aperture, those GPU shouldn't have much memory and seems to behave better when setup that way. For R3XX and newer we place VRAM at 0. For R6XX-R7XX AGP we place VRAM before or after AGP aperture this might limit to limit the VRAM size but it's very unlikely. For IGP we don't change the VRAM placement. Tested on (compiz,quake3,suspend/resume): PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710 AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730 IGP:RS480(RPB*),RS690,RS780(RPB*),RS880 RPB: resume previously broken V2 correct commit message to reflect more accurately the bug and move VRAM placement to 0 for most of the GPU to avoid limiting VRAM. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c51
-rw-r--r--drivers/gpu/drm/radeon/r100.c93
-rw-r--r--drivers/gpu/drm/radeon/r300.c27
-rw-r--r--drivers/gpu/drm/radeon/r420.c36
-rw-r--r--drivers/gpu/drm/radeon/r520.c21
-rw-r--r--drivers/gpu/drm/radeon/r600.c123
-rw-r--r--drivers/gpu/drm/radeon/radeon.h13
-rw-r--r--drivers/gpu/drm/radeon/radeon_agp.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c157
-rw-r--r--drivers/gpu/drm/radeon/radeon_fb.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_test.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_ttm.c12
-rw-r--r--drivers/gpu/drm/radeon/rs400.c38
-rw-r--r--drivers/gpu/drm/radeon/rs600.c42
-rw-r--r--drivers/gpu/drm/radeon/rs690.c40
-rw-r--r--drivers/gpu/drm/radeon/rv515.c21
-rw-r--r--drivers/gpu/drm/radeon/rv770.c41
18 files changed, 301 insertions, 424 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 3368920df5f4..3f973d411d61 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -439,7 +439,6 @@ int evergreen_mc_init(struct radeon_device *rdev)
439 fixed20_12 a; 439 fixed20_12 a;
440 u32 tmp; 440 u32 tmp;
441 int chansize, numchan; 441 int chansize, numchan;
442 int r;
443 442
444 /* Get VRAM informations */ 443 /* Get VRAM informations */
445 rdev->mc.vram_is_ddr = true; 444 rdev->mc.vram_is_ddr = true;
@@ -475,48 +474,12 @@ int evergreen_mc_init(struct radeon_device *rdev)
475 /* size in MB on evergreen */ 474 /* size in MB on evergreen */
476 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 475 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
477 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 476 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
478 477 /* FIXME remove this once we support unmappable VRAM */
479 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) 478 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
480 rdev->mc.mc_vram_size = rdev->mc.aper_size; 479 rdev->mc.mc_vram_size = rdev->mc.aper_size;
481
482 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
483 rdev->mc.real_vram_size = rdev->mc.aper_size; 480 rdev->mc.real_vram_size = rdev->mc.aper_size;
484
485 if (rdev->flags & RADEON_IS_AGP) {
486 r = radeon_agp_init(rdev);
487 if (r)
488 return r;
489 /* gtt_size is setup by radeon_agp_init */
490 rdev->mc.gtt_location = rdev->mc.agp_base;
491 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
492 /* Try to put vram before or after AGP because we
493 * we want SYSTEM_APERTURE to cover both VRAM and
494 * AGP so that GPU can catch out of VRAM/AGP access
495 */
496 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
497 /* Enought place before */
498 rdev->mc.vram_location = rdev->mc.gtt_location -
499 rdev->mc.mc_vram_size;
500 } else if (tmp > rdev->mc.mc_vram_size) {
501 /* Enought place after */
502 rdev->mc.vram_location = rdev->mc.gtt_location +
503 rdev->mc.gtt_size;
504 } else {
505 /* Try to setup VRAM then AGP might not
506 * not work on some card
507 */
508 rdev->mc.vram_location = 0x00000000UL;
509 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
510 }
511 } else {
512 rdev->mc.vram_location = 0x00000000UL;
513 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
514 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
515 } 481 }
516 rdev->mc.vram_start = rdev->mc.vram_location; 482 r600_vram_gtt_location(rdev, &rdev->mc);
517 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
518 rdev->mc.gtt_start = rdev->mc.gtt_location;
519 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
520 /* FIXME: we should enforce default clock in case GPU is not in 483 /* FIXME: we should enforce default clock in case GPU is not in
521 * default setup 484 * default setup
522 */ 485 */
@@ -525,6 +488,7 @@ int evergreen_mc_init(struct radeon_device *rdev)
525 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); 488 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
526 return 0; 489 return 0;
527} 490}
491
528int evergreen_gpu_reset(struct radeon_device *rdev) 492int evergreen_gpu_reset(struct radeon_device *rdev)
529{ 493{
530 /* FIXME: implement for evergreen */ 494 /* FIXME: implement for evergreen */
@@ -726,6 +690,13 @@ int evergreen_init(struct radeon_device *rdev)
726 r = radeon_fence_driver_init(rdev); 690 r = radeon_fence_driver_init(rdev);
727 if (r) 691 if (r)
728 return r; 692 return r;
693 /* initialize AGP */
694 if (rdev->flags & RADEON_IS_AGP) {
695 r = radeon_agp_init(rdev);
696 if (r)
697 radeon_agp_disable(rdev);
698 }
699 /* initialize memory controller */
729 r = evergreen_mc_init(rdev); 700 r = evergreen_mc_init(rdev);
730 if (r) 701 if (r)
731 return r; 702 return r;
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index bc7d9e9211c8..1fdd793343b9 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -202,9 +202,8 @@ int r100_pci_gart_enable(struct radeon_device *rdev)
202 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 202 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
203 WREG32(RADEON_AIC_CNTL, tmp); 203 WREG32(RADEON_AIC_CNTL, tmp);
204 /* set address range for PCI address translate */ 204 /* set address range for PCI address translate */
205 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location); 205 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
206 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; 206 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
207 WREG32(RADEON_AIC_HI_ADDR, tmp);
208 /* set PCI GART page-table base address */ 207 /* set PCI GART page-table base address */
209 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 208 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
210 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 209 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
@@ -1957,17 +1956,17 @@ static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1957void r100_vram_init_sizes(struct radeon_device *rdev) 1956void r100_vram_init_sizes(struct radeon_device *rdev)
1958{ 1957{
1959 u64 config_aper_size; 1958 u64 config_aper_size;
1960 u32 accessible;
1961 1959
1960 /* work out accessible VRAM */
1961 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
1962 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1963 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1962 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 1964 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1963
1964 if (rdev->flags & RADEON_IS_IGP) { 1965 if (rdev->flags & RADEON_IS_IGP) {
1965 uint32_t tom; 1966 uint32_t tom;
1966 /* read NB_TOM to get the amount of ram stolen for the GPU */ 1967 /* read NB_TOM to get the amount of ram stolen for the GPU */
1967 tom = RREG32(RADEON_NB_TOM); 1968 tom = RREG32(RADEON_NB_TOM);
1968 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 1969 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1969 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1970 rdev->mc.vram_location = (tom & 0xffff) << 16;
1971 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 1970 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1972 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 1971 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1973 } else { 1972 } else {
@@ -1979,30 +1978,19 @@ void r100_vram_init_sizes(struct radeon_device *rdev)
1979 rdev->mc.real_vram_size = 8192 * 1024; 1978 rdev->mc.real_vram_size = 8192 * 1024;
1980 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 1979 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1981 } 1980 }
1982 /* let driver place VRAM */ 1981 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1983 rdev->mc.vram_location = 0xFFFFFFFFUL; 1982 * Novell bug 204882 + along with lots of ubuntu ones
1984 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 1983 */
1985 * Novell bug 204882 + along with lots of ubuntu ones */
1986 if (config_aper_size > rdev->mc.real_vram_size) 1984 if (config_aper_size > rdev->mc.real_vram_size)
1987 rdev->mc.mc_vram_size = config_aper_size; 1985 rdev->mc.mc_vram_size = config_aper_size;
1988 else 1986 else
1989 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 1987 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1990 } 1988 }
1991 1989 /* FIXME remove this once we support unmappable VRAM */
1992 /* work out accessible VRAM */ 1990 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
1993 accessible = r100_get_accessible_vram(rdev);
1994
1995 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1996 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1997
1998 if (accessible > rdev->mc.aper_size)
1999 accessible = rdev->mc.aper_size;
2000
2001 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
2002 rdev->mc.mc_vram_size = rdev->mc.aper_size; 1991 rdev->mc.mc_vram_size = rdev->mc.aper_size;
2003
2004 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
2005 rdev->mc.real_vram_size = rdev->mc.aper_size; 1992 rdev->mc.real_vram_size = rdev->mc.aper_size;
1993 }
2006} 1994}
2007 1995
2008void r100_vga_set_state(struct radeon_device *rdev, bool state) 1996void r100_vga_set_state(struct radeon_device *rdev, bool state)
@@ -2019,11 +2007,18 @@ void r100_vga_set_state(struct radeon_device *rdev, bool state)
2019 WREG32(RADEON_CONFIG_CNTL, temp); 2007 WREG32(RADEON_CONFIG_CNTL, temp);
2020} 2008}
2021 2009
2022void r100_vram_info(struct radeon_device *rdev) 2010void r100_mc_init(struct radeon_device *rdev)
2023{ 2011{
2024 r100_vram_get_type(rdev); 2012 u64 base;
2025 2013
2014 r100_vram_get_type(rdev);
2026 r100_vram_init_sizes(rdev); 2015 r100_vram_init_sizes(rdev);
2016 base = rdev->mc.aper_base;
2017 if (rdev->flags & RADEON_IS_IGP)
2018 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2019 radeon_vram_location(rdev, &rdev->mc, base);
2020 if (!(rdev->flags & RADEON_IS_AGP))
2021 radeon_gtt_location(rdev, &rdev->mc);
2027} 2022}
2028 2023
2029 2024
@@ -3294,10 +3289,9 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3294void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 3289void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3295{ 3290{
3296 /* Update base address for crtc */ 3291 /* Update base address for crtc */
3297 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location); 3292 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3298 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3293 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3299 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, 3294 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3300 rdev->mc.vram_location);
3301 } 3295 }
3302 /* Restore CRTC registers */ 3296 /* Restore CRTC registers */
3303 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 3297 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
@@ -3458,32 +3452,6 @@ void r100_fini(struct radeon_device *rdev)
3458 rdev->bios = NULL; 3452 rdev->bios = NULL;
3459} 3453}
3460 3454
3461int r100_mc_init(struct radeon_device *rdev)
3462{
3463 int r;
3464 u32 tmp;
3465
3466 /* Setup GPU memory space */
3467 rdev->mc.vram_location = 0xFFFFFFFFUL;
3468 rdev->mc.gtt_location = 0xFFFFFFFFUL;
3469 if (rdev->flags & RADEON_IS_IGP) {
3470 tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
3471 rdev->mc.vram_location = tmp << 16;
3472 }
3473 if (rdev->flags & RADEON_IS_AGP) {
3474 r = radeon_agp_init(rdev);
3475 if (r) {
3476 radeon_agp_disable(rdev);
3477 } else {
3478 rdev->mc.gtt_location = rdev->mc.agp_base;
3479 }
3480 }
3481 r = radeon_mc_setup(rdev);
3482 if (r)
3483 return r;
3484 return 0;
3485}
3486
3487int r100_init(struct radeon_device *rdev) 3455int r100_init(struct radeon_device *rdev)
3488{ 3456{
3489 int r; 3457 int r;
@@ -3526,12 +3494,15 @@ int r100_init(struct radeon_device *rdev)
3526 radeon_get_clock_info(rdev->ddev); 3494 radeon_get_clock_info(rdev->ddev);
3527 /* Initialize power management */ 3495 /* Initialize power management */
3528 radeon_pm_init(rdev); 3496 radeon_pm_init(rdev);
3529 /* Get vram informations */ 3497 /* initialize AGP */
3530 r100_vram_info(rdev); 3498 if (rdev->flags & RADEON_IS_AGP) {
3531 /* Initialize memory controller (also test AGP) */ 3499 r = radeon_agp_init(rdev);
3532 r = r100_mc_init(rdev); 3500 if (r) {
3533 if (r) 3501 radeon_agp_disable(rdev);
3534 return r; 3502 }
3503 }
3504 /* initialize VRAM */
3505 r100_mc_init(rdev);
3535 /* Fence driver */ 3506 /* Fence driver */
3536 r = radeon_fence_driver_init(rdev); 3507 r = radeon_fence_driver_init(rdev);
3537 if (r) 3508 if (r)
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index a4f395226b34..7e9f95653cbe 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -121,15 +121,15 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev)
121 /* discard memory request outside of configured range */ 121 /* discard memory request outside of configured range */
122 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 122 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
123 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 123 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
124 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location); 124 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
125 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - RADEON_GPU_PAGE_SIZE; 125 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
126 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); 126 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
127 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 127 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
128 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 128 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
129 table_addr = rdev->gart.table_addr; 129 table_addr = rdev->gart.table_addr;
130 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); 130 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
131 /* FIXME: setup default page */ 131 /* FIXME: setup default page */
132 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location); 132 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
133 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); 133 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
134 /* Clear error */ 134 /* Clear error */
135 WREG32_PCIE(0x18, 0); 135 WREG32_PCIE(0x18, 0);
@@ -459,13 +459,12 @@ int r300_gpu_reset(struct radeon_device *rdev)
459/* 459/*
460 * r300,r350,rv350,rv380 VRAM info 460 * r300,r350,rv350,rv380 VRAM info
461 */ 461 */
462void r300_vram_info(struct radeon_device *rdev) 462void r300_mc_init(struct radeon_device *rdev)
463{ 463{
464 uint32_t tmp; 464 uint32_t tmp;
465 465
466 /* DDR for all card after R300 & IGP */ 466 /* DDR for all card after R300 & IGP */
467 rdev->mc.vram_is_ddr = true; 467 rdev->mc.vram_is_ddr = true;
468
469 tmp = RREG32(RADEON_MEM_CNTL); 468 tmp = RREG32(RADEON_MEM_CNTL);
470 tmp &= R300_MEM_NUM_CHANNELS_MASK; 469 tmp &= R300_MEM_NUM_CHANNELS_MASK;
471 switch (tmp) { 470 switch (tmp) {
@@ -474,8 +473,9 @@ void r300_vram_info(struct radeon_device *rdev)
474 case 2: rdev->mc.vram_width = 256; break; 473 case 2: rdev->mc.vram_width = 256; break;
475 default: rdev->mc.vram_width = 128; break; 474 default: rdev->mc.vram_width = 128; break;
476 } 475 }
477
478 r100_vram_init_sizes(rdev); 476 r100_vram_init_sizes(rdev);
477 if (!(rdev->flags & RADEON_IS_AGP))
478 radeon_gtt_location(rdev, &rdev->mc);
479} 479}
480 480
481void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) 481void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
@@ -1377,12 +1377,15 @@ int r300_init(struct radeon_device *rdev)
1377 radeon_get_clock_info(rdev->ddev); 1377 radeon_get_clock_info(rdev->ddev);
1378 /* Initialize power management */ 1378 /* Initialize power management */
1379 radeon_pm_init(rdev); 1379 radeon_pm_init(rdev);
1380 /* Get vram informations */ 1380 /* initialize AGP */
1381 r300_vram_info(rdev); 1381 if (rdev->flags & RADEON_IS_AGP) {
1382 /* Initialize memory controller (also test AGP) */ 1382 r = radeon_agp_init(rdev);
1383 r = r420_mc_init(rdev); 1383 if (r) {
1384 if (r) 1384 radeon_agp_disable(rdev);
1385 return r; 1385 }
1386 }
1387 /* initialize memory controller */
1388 r300_mc_init(rdev);
1386 /* Fence driver */ 1389 /* Fence driver */
1387 r = radeon_fence_driver_init(rdev); 1390 r = radeon_fence_driver_init(rdev);
1388 if (r) 1391 if (r)
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 12ebbdb83d1c..c7593b8f58ee 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -40,28 +40,6 @@ static void r420_set_reg_safe(struct radeon_device *rdev)
40 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); 40 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
41} 41}
42 42
43int r420_mc_init(struct radeon_device *rdev)
44{
45 int r;
46
47 /* Setup GPU memory space */
48 rdev->mc.vram_location = 0xFFFFFFFFUL;
49 rdev->mc.gtt_location = 0xFFFFFFFFUL;
50 if (rdev->flags & RADEON_IS_AGP) {
51 r = radeon_agp_init(rdev);
52 if (r) {
53 radeon_agp_disable(rdev);
54 } else {
55 rdev->mc.gtt_location = rdev->mc.agp_base;
56 }
57 }
58 r = radeon_mc_setup(rdev);
59 if (r) {
60 return r;
61 }
62 return 0;
63}
64
65void r420_pipes_init(struct radeon_device *rdev) 43void r420_pipes_init(struct radeon_device *rdev)
66{ 44{
67 unsigned tmp; 45 unsigned tmp;
@@ -349,13 +327,15 @@ int r420_init(struct radeon_device *rdev)
349 radeon_get_clock_info(rdev->ddev); 327 radeon_get_clock_info(rdev->ddev);
350 /* Initialize power management */ 328 /* Initialize power management */
351 radeon_pm_init(rdev); 329 radeon_pm_init(rdev);
352 /* Get vram informations */ 330 /* initialize AGP */
353 r300_vram_info(rdev); 331 if (rdev->flags & RADEON_IS_AGP) {
354 /* Initialize memory controller (also test AGP) */ 332 r = radeon_agp_init(rdev);
355 r = r420_mc_init(rdev); 333 if (r) {
356 if (r) { 334 radeon_agp_disable(rdev);
357 return r; 335 }
358 } 336 }
337 /* initialize memory controller */
338 r300_mc_init(rdev);
359 r420_debugfs(rdev); 339 r420_debugfs(rdev);
360 /* Fence driver */ 340 /* Fence driver */
361 r = radeon_fence_driver_init(rdev); 341 r = radeon_fence_driver_init(rdev);
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index ddf5731eba0d..2b8a5dd13516 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -119,13 +119,15 @@ static void r520_vram_get_type(struct radeon_device *rdev)
119 rdev->mc.vram_width *= 2; 119 rdev->mc.vram_width *= 2;
120} 120}
121 121
122void r520_vram_info(struct radeon_device *rdev) 122void r520_mc_init(struct radeon_device *rdev)
123{ 123{
124 fixed20_12 a; 124 fixed20_12 a;
125 125
126 r520_vram_get_type(rdev); 126 r520_vram_get_type(rdev);
127
128 r100_vram_init_sizes(rdev); 127 r100_vram_init_sizes(rdev);
128 radeon_vram_location(rdev, &rdev->mc, 0);
129 if (!(rdev->flags & RADEON_IS_AGP))
130 radeon_gtt_location(rdev, &rdev->mc);
129 /* FIXME: we should enforce default clock in case GPU is not in 131 /* FIXME: we should enforce default clock in case GPU is not in
130 * default setup 132 * default setup
131 */ 133 */
@@ -267,12 +269,15 @@ int r520_init(struct radeon_device *rdev)
267 radeon_get_clock_info(rdev->ddev); 269 radeon_get_clock_info(rdev->ddev);
268 /* Initialize power management */ 270 /* Initialize power management */
269 radeon_pm_init(rdev); 271 radeon_pm_init(rdev);
270 /* Get vram informations */ 272 /* initialize AGP */
271 r520_vram_info(rdev); 273 if (rdev->flags & RADEON_IS_AGP) {
272 /* Initialize memory controller (also test AGP) */ 274 r = radeon_agp_init(rdev);
273 r = r420_mc_init(rdev); 275 if (r) {
274 if (r) 276 radeon_agp_disable(rdev);
275 return r; 277 }
278 }
279 /* initialize memory controller */
280 r520_mc_init(rdev);
276 rv515_debugfs(rdev); 281 rv515_debugfs(rdev);
277 /* Fence driver */ 282 /* Fence driver */
278 r = radeon_fence_driver_init(rdev); 283 r = radeon_fence_driver_init(rdev);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index a865946d2d08..694a4c564f52 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -611,6 +611,68 @@ static void r600_mc_program(struct radeon_device *rdev)
611 rv515_vga_render_disable(rdev); 611 rv515_vga_render_disable(rdev);
612} 612}
613 613
614/**
615 * r600_vram_gtt_location - try to find VRAM & GTT location
616 * @rdev: radeon device structure holding all necessary informations
617 * @mc: memory controller structure holding memory informations
618 *
619 * Function will place try to place VRAM at same place as in CPU (PCI)
620 * address space as some GPU seems to have issue when we reprogram at
621 * different address space.
622 *
623 * If there is not enough space to fit the unvisible VRAM after the
624 * aperture then we limit the VRAM size to the aperture.
625 *
626 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
627 * them to be in one from GPU point of view so that we can program GPU to
628 * catch access outside them (weird GPU policy see ??).
629 *
630 * This function will never fails, worst case are limiting VRAM or GTT.
631 *
632 * Note: GTT start, end, size should be initialized before calling this
633 * function on AGP platform.
634 */
635void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
636{
637 u64 size_bf, size_af;
638
639 if (mc->mc_vram_size > 0xE0000000) {
640 /* leave room for at least 512M GTT */
641 dev_warn(rdev->dev, "limiting VRAM\n");
642 mc->real_vram_size = 0xE0000000;
643 mc->mc_vram_size = 0xE0000000;
644 }
645 if (rdev->flags & RADEON_IS_AGP) {
646 size_bf = mc->gtt_start;
647 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
648 if (size_bf > size_af) {
649 if (mc->mc_vram_size > size_bf) {
650 dev_warn(rdev->dev, "limiting VRAM\n");
651 mc->real_vram_size = size_bf;
652 mc->mc_vram_size = size_bf;
653 }
654 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
655 } else {
656 if (mc->mc_vram_size > size_af) {
657 dev_warn(rdev->dev, "limiting VRAM\n");
658 mc->real_vram_size = size_af;
659 mc->mc_vram_size = size_af;
660 }
661 mc->vram_start = mc->gtt_end;
662 }
663 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
664 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
665 mc->mc_vram_size >> 20, mc->vram_start,
666 mc->vram_end, mc->real_vram_size >> 20);
667 } else {
668 u64 base = 0;
669 if (rdev->flags & RADEON_IS_IGP)
670 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
671 radeon_vram_location(rdev, &rdev->mc, base);
672 radeon_gtt_location(rdev, mc);
673 }
674}
675
614int r600_mc_init(struct radeon_device *rdev) 676int r600_mc_init(struct radeon_device *rdev)
615{ 677{
616 fixed20_12 a; 678 fixed20_12 a;
@@ -650,75 +712,20 @@ int r600_mc_init(struct radeon_device *rdev)
650 /* Setup GPU memory space */ 712 /* Setup GPU memory space */
651 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 713 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
652 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 714 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
653 715 /* FIXME remove this once we support unmappable VRAM */
654 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) 716 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
655 rdev->mc.mc_vram_size = rdev->mc.aper_size; 717 rdev->mc.mc_vram_size = rdev->mc.aper_size;
656
657 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
658 rdev->mc.real_vram_size = rdev->mc.aper_size; 718 rdev->mc.real_vram_size = rdev->mc.aper_size;
659
660 if (rdev->flags & RADEON_IS_AGP) {
661 /* gtt_size is setup by radeon_agp_init */
662 rdev->mc.gtt_location = rdev->mc.agp_base;
663 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
664 /* Try to put vram before or after AGP because we
665 * we want SYSTEM_APERTURE to cover both VRAM and
666 * AGP so that GPU can catch out of VRAM/AGP access
667 */
668 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
669 /* Enought place before */
670 rdev->mc.vram_location = rdev->mc.gtt_location -
671 rdev->mc.mc_vram_size;
672 } else if (tmp > rdev->mc.mc_vram_size) {
673 /* Enought place after */
674 rdev->mc.vram_location = rdev->mc.gtt_location +
675 rdev->mc.gtt_size;
676 } else {
677 /* Try to setup VRAM then AGP might not
678 * not work on some card
679 */
680 rdev->mc.vram_location = 0x00000000UL;
681 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
682 }
683 } else {
684 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
685 rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
686 0xFFFF) << 24;
687 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
688 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
689 /* Enough place after vram */
690 rdev->mc.gtt_location = tmp;
691 } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
692 /* Enough place before vram */
693 rdev->mc.gtt_location = 0;
694 } else {
695 /* Not enough place after or before shrink
696 * gart size
697 */
698 if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
699 rdev->mc.gtt_location = 0;
700 rdev->mc.gtt_size = rdev->mc.vram_location;
701 } else {
702 rdev->mc.gtt_location = tmp;
703 rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
704 }
705 }
706 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
707 } 719 }
708 rdev->mc.vram_start = rdev->mc.vram_location; 720 r600_vram_gtt_location(rdev, &rdev->mc);
709 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
710 rdev->mc.gtt_start = rdev->mc.gtt_location;
711 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
712 /* FIXME: we should enforce default clock in case GPU is not in 721 /* FIXME: we should enforce default clock in case GPU is not in
713 * default setup 722 * default setup
714 */ 723 */
715 a.full = rfixed_const(100); 724 a.full = rfixed_const(100);
716 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); 725 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
717 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); 726 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
718
719 if (rdev->flags & RADEON_IS_IGP) 727 if (rdev->flags & RADEON_IS_IGP)
720 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 728 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
721
722 return 0; 729 return 0;
723} 730}
724 731
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 350ae71953e9..0ca83ca91111 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -282,6 +282,7 @@ union radeon_gart_table {
282}; 282};
283 283
284#define RADEON_GPU_PAGE_SIZE 4096 284#define RADEON_GPU_PAGE_SIZE 4096
285#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
285 286
286struct radeon_gart { 287struct radeon_gart {
287 dma_addr_t table_addr; 288 dma_addr_t table_addr;
@@ -316,21 +317,19 @@ struct radeon_mc {
316 /* for some chips with <= 32MB we need to lie 317 /* for some chips with <= 32MB we need to lie
317 * about vram size near mc fb location */ 318 * about vram size near mc fb location */
318 u64 mc_vram_size; 319 u64 mc_vram_size;
319 u64 gtt_location; 320 u64 visible_vram_size;
320 u64 gtt_size; 321 u64 gtt_size;
321 u64 gtt_start; 322 u64 gtt_start;
322 u64 gtt_end; 323 u64 gtt_end;
323 u64 vram_location;
324 u64 vram_start; 324 u64 vram_start;
325 u64 vram_end; 325 u64 vram_end;
326 unsigned vram_width; 326 unsigned vram_width;
327 u64 real_vram_size; 327 u64 real_vram_size;
328 int vram_mtrr; 328 int vram_mtrr;
329 bool vram_is_ddr; 329 bool vram_is_ddr;
330 bool igp_sideport_enabled; 330 bool igp_sideport_enabled;
331}; 331};
332 332
333int radeon_mc_setup(struct radeon_device *rdev);
334bool radeon_combios_sideport_present(struct radeon_device *rdev); 333bool radeon_combios_sideport_present(struct radeon_device *rdev);
335bool radeon_atombios_sideport_present(struct radeon_device *rdev); 334bool radeon_atombios_sideport_present(struct radeon_device *rdev);
336 335
@@ -1165,6 +1164,8 @@ extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enabl
1165extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 1164extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1166extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 1165extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1167extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 1166extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1167extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1168extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1168 1169
1169/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ 1170/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1170struct r100_mc_save { 1171struct r100_mc_save {
@@ -1219,7 +1220,7 @@ extern void r200_set_safe_registers(struct radeon_device *rdev);
1219/* r300,r350,rv350,rv370,rv380 */ 1220/* r300,r350,rv350,rv370,rv380 */
1220extern void r300_set_reg_safe(struct radeon_device *rdev); 1221extern void r300_set_reg_safe(struct radeon_device *rdev);
1221extern void r300_mc_program(struct radeon_device *rdev); 1222extern void r300_mc_program(struct radeon_device *rdev);
1222extern void r300_vram_info(struct radeon_device *rdev); 1223extern void r300_mc_init(struct radeon_device *rdev);
1223extern void r300_clock_startup(struct radeon_device *rdev); 1224extern void r300_clock_startup(struct radeon_device *rdev);
1224extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 1225extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1225extern int rv370_pcie_gart_init(struct radeon_device *rdev); 1226extern int rv370_pcie_gart_init(struct radeon_device *rdev);
@@ -1228,7 +1229,6 @@ extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1228extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 1229extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1229 1230
1230/* r420,r423,rv410 */ 1231/* r420,r423,rv410 */
1231extern int r420_mc_init(struct radeon_device *rdev);
1232extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 1232extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1233extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 1233extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1234extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 1234extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
@@ -1270,6 +1270,7 @@ extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1270 struct drm_display_mode *mode2); 1270 struct drm_display_mode *mode2);
1271 1271
1272/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ 1272/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1273extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1273extern bool r600_card_posted(struct radeon_device *rdev); 1274extern bool r600_card_posted(struct radeon_device *rdev);
1274extern void r600_cp_stop(struct radeon_device *rdev); 1275extern void r600_cp_stop(struct radeon_device *rdev);
1275extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); 1276extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c
index c0681a5556dc..c4457791dff1 100644
--- a/drivers/gpu/drm/radeon/radeon_agp.c
+++ b/drivers/gpu/drm/radeon/radeon_agp.c
@@ -237,6 +237,10 @@ int radeon_agp_init(struct radeon_device *rdev)
237 237
238 rdev->mc.agp_base = rdev->ddev->agp->agp_info.aper_base; 238 rdev->mc.agp_base = rdev->ddev->agp->agp_info.aper_base;
239 rdev->mc.gtt_size = rdev->ddev->agp->agp_info.aper_size << 20; 239 rdev->mc.gtt_size = rdev->ddev->agp->agp_info.aper_size << 20;
240 rdev->mc.gtt_start = rdev->mc.agp_base;
241 rdev->mc.gtt_end = rdev->mc.gtt_start + rdev->mc.gtt_size - 1;
242 dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
243 rdev->mc.gtt_size >> 20, rdev->mc.gtt_start, rdev->mc.gtt_end);
240 244
241 /* workaround some hw issues */ 245 /* workaround some hw issues */
242 if (rdev->family < CHIP_R200) { 246 if (rdev->family < CHIP_R200) {
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 7be3a6968463..91a9b966238e 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -100,80 +100,103 @@ void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
100 } 100 }
101} 101}
102 102
103/* 103/**
104 * MC common functions 104 * radeon_vram_location - try to find VRAM location
105 * @rdev: radeon device structure holding all necessary informations
106 * @mc: memory controller structure holding memory informations
107 * @base: base address at which to put VRAM
108 *
109 * Function will place try to place VRAM at base address provided
110 * as parameter (which is so far either PCI aperture address or
111 * for IGP TOM base address).
112 *
113 * If there is not enough space to fit the unvisible VRAM in the 32bits
114 * address space then we limit the VRAM size to the aperture.
115 *
116 * If we are using AGP and if the AGP aperture doesn't allow us to have
117 * room for all the VRAM than we restrict the VRAM to the PCI aperture
118 * size and print a warning.
119 *
120 * This function will never fails, worst case are limiting VRAM.
121 *
122 * Note: GTT start, end, size should be initialized before calling this
123 * function on AGP platform.
124 *
125 * Note: We don't explictly enforce VRAM start to be aligned on VRAM size,
126 * this shouldn't be a problem as we are using the PCI aperture as a reference.
127 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
128 * not IGP.
129 *
130 * Note: we use mc_vram_size as on some board we need to program the mc to
131 * cover the whole aperture even if VRAM size is inferior to aperture size
132 * Novell bug 204882 + along with lots of ubuntu ones
133 *
134 * Note: when limiting vram it's safe to overwritte real_vram_size because
135 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
136 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
137 * ones)
138 *
139 * Note: IGP TOM addr should be the same as the aperture addr, we don't
140 * explicitly check for that thought.
141 *
142 * FIXME: when reducing VRAM size align new size on power of 2.
105 */ 143 */
106int radeon_mc_setup(struct radeon_device *rdev) 144void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
145{
146 mc->vram_start = base;
147 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
148 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
149 mc->real_vram_size = mc->aper_size;
150 mc->mc_vram_size = mc->aper_size;
151 }
152 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
153 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_end <= mc->gtt_end) {
154 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
155 mc->real_vram_size = mc->aper_size;
156 mc->mc_vram_size = mc->aper_size;
157 }
158 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
159 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
160 mc->mc_vram_size >> 20, mc->vram_start,
161 mc->vram_end, mc->real_vram_size >> 20);
162}
163
164/**
165 * radeon_gtt_location - try to find GTT location
166 * @rdev: radeon device structure holding all necessary informations
167 * @mc: memory controller structure holding memory informations
168 *
169 * Function will place try to place GTT before or after VRAM.
170 *
171 * If GTT size is bigger than space left then we ajust GTT size.
172 * Thus function will never fails.
173 *
174 * FIXME: when reducing GTT size align new size on power of 2.
175 */
176void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
107{ 177{
108 uint32_t tmp; 178 u64 size_af, size_bf;
109 179
110 /* Some chips have an "issue" with the memory controller, the 180 size_af = 0xFFFFFFFF - mc->vram_end;
111 * location must be aligned to the size. We just align it down, 181 size_bf = mc->vram_start;
112 * too bad if we walk over the top of system memory, we don't 182 if (size_bf > size_af) {
113 * use DMA without a remapped anyway. 183 if (mc->gtt_size > size_bf) {
114 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP 184 dev_warn(rdev->dev, "limiting GTT\n");
115 */ 185 mc->gtt_size = size_bf;
116 /* FGLRX seems to setup like this, VRAM a 0, then GART.
117 */
118 /*
119 * Note: from R6xx the address space is 40bits but here we only
120 * use 32bits (still have to see a card which would exhaust 4G
121 * address space).
122 */
123 if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
124 /* vram location was already setup try to put gtt after
125 * if it fits */
126 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
127 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
128 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
129 rdev->mc.gtt_location = tmp;
130 } else {
131 if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
132 printk(KERN_ERR "[drm] GTT too big to fit "
133 "before or after vram location.\n");
134 return -EINVAL;
135 }
136 rdev->mc.gtt_location = 0;
137 }
138 } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
139 /* gtt location was already setup try to put vram before
140 * if it fits */
141 if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
142 rdev->mc.vram_location = 0;
143 } else {
144 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
145 tmp += (rdev->mc.mc_vram_size - 1);
146 tmp &= ~(rdev->mc.mc_vram_size - 1);
147 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
148 rdev->mc.vram_location = tmp;
149 } else {
150 printk(KERN_ERR "[drm] vram too big to fit "
151 "before or after GTT location.\n");
152 return -EINVAL;
153 }
154 } 186 }
187 mc->gtt_start = mc->vram_start - mc->gtt_size;
155 } else { 188 } else {
156 rdev->mc.vram_location = 0; 189 if (mc->gtt_size > size_af) {
157 tmp = rdev->mc.mc_vram_size; 190 dev_warn(rdev->dev, "limiting GTT\n");
158 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); 191 mc->gtt_size = size_af;
159 rdev->mc.gtt_location = tmp; 192 }
160 } 193 mc->gtt_start = mc->vram_end + 1;
161 rdev->mc.vram_start = rdev->mc.vram_location; 194 }
162 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; 195 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
163 rdev->mc.gtt_start = rdev->mc.gtt_location; 196 dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
164 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; 197 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
165 DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
166 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
167 (unsigned)rdev->mc.vram_location,
168 (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
169 DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
170 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
171 (unsigned)rdev->mc.gtt_location,
172 (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
173 return 0;
174} 198}
175 199
176
177/* 200/*
178 * GPU helpers function. 201 * GPU helpers function.
179 */ 202 */
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index 105c678fa73a..c39ddda13840 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -252,7 +252,7 @@ int radeonfb_create(struct drm_device *dev,
252 info->flags = FBINFO_DEFAULT; 252 info->flags = FBINFO_DEFAULT;
253 info->fbops = &radeonfb_ops; 253 info->fbops = &radeonfb_ops;
254 254
255 tmp = fb_gpuaddr - rdev->mc.vram_location; 255 tmp = fb_gpuaddr - rdev->mc.vram_start;
256 info->fix.smem_start = rdev->mc.aper_base + tmp; 256 info->fix.smem_start = rdev->mc.aper_base + tmp;
257 info->fix.smem_len = size; 257 info->fix.smem_len = size;
258 info->screen_base = fbptr; 258 info->screen_base = fbptr;
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 83d4dbd6d067..643251719f1c 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -403,7 +403,7 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
403 403
404 /* if scanout was in GTT this really wouldn't work */ 404 /* if scanout was in GTT this really wouldn't work */
405 /* crtc offset is from display base addr not FB location */ 405 /* crtc offset is from display base addr not FB location */
406 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location; 406 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
407 407
408 base -= radeon_crtc->legacy_display_base_addr; 408 base -= radeon_crtc->legacy_display_base_addr;
409 409
diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c
index 9f5e2f929da9..313c96bc09da 100644
--- a/drivers/gpu/drm/radeon/radeon_test.c
+++ b/drivers/gpu/drm/radeon/radeon_test.c
@@ -186,7 +186,7 @@ void radeon_test_moves(struct radeon_device *rdev)
186 radeon_bo_kunmap(gtt_obj[i]); 186 radeon_bo_kunmap(gtt_obj[i]);
187 187
188 DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n", 188 DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n",
189 gtt_addr - rdev->mc.gtt_location); 189 gtt_addr - rdev->mc.gtt_start);
190 } 190 }
191 191
192out_cleanup: 192out_cleanup:
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index db820ae9a034..1157e0f758fa 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -150,7 +150,7 @@ static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
150 man->default_caching = TTM_PL_FLAG_CACHED; 150 man->default_caching = TTM_PL_FLAG_CACHED;
151 break; 151 break;
152 case TTM_PL_TT: 152 case TTM_PL_TT:
153 man->gpu_offset = rdev->mc.gtt_location; 153 man->gpu_offset = rdev->mc.gtt_start;
154 man->available_caching = TTM_PL_MASK_CACHING; 154 man->available_caching = TTM_PL_MASK_CACHING;
155 man->default_caching = TTM_PL_FLAG_CACHED; 155 man->default_caching = TTM_PL_FLAG_CACHED;
156 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; 156 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
@@ -180,7 +180,7 @@ static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
180 break; 180 break;
181 case TTM_PL_VRAM: 181 case TTM_PL_VRAM:
182 /* "On-card" video ram */ 182 /* "On-card" video ram */
183 man->gpu_offset = rdev->mc.vram_location; 183 man->gpu_offset = rdev->mc.vram_start;
184 man->flags = TTM_MEMTYPE_FLAG_FIXED | 184 man->flags = TTM_MEMTYPE_FLAG_FIXED |
185 TTM_MEMTYPE_FLAG_NEEDS_IOREMAP | 185 TTM_MEMTYPE_FLAG_NEEDS_IOREMAP |
186 TTM_MEMTYPE_FLAG_MAPPABLE; 186 TTM_MEMTYPE_FLAG_MAPPABLE;
@@ -262,10 +262,10 @@ static int radeon_move_blit(struct ttm_buffer_object *bo,
262 262
263 switch (old_mem->mem_type) { 263 switch (old_mem->mem_type) {
264 case TTM_PL_VRAM: 264 case TTM_PL_VRAM:
265 old_start += rdev->mc.vram_location; 265 old_start += rdev->mc.vram_start;
266 break; 266 break;
267 case TTM_PL_TT: 267 case TTM_PL_TT:
268 old_start += rdev->mc.gtt_location; 268 old_start += rdev->mc.gtt_start;
269 break; 269 break;
270 default: 270 default:
271 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 271 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
@@ -273,10 +273,10 @@ static int radeon_move_blit(struct ttm_buffer_object *bo,
273 } 273 }
274 switch (new_mem->mem_type) { 274 switch (new_mem->mem_type) {
275 case TTM_PL_VRAM: 275 case TTM_PL_VRAM:
276 new_start += rdev->mc.vram_location; 276 new_start += rdev->mc.vram_start;
277 break; 277 break;
278 case TTM_PL_TT: 278 case TTM_PL_TT:
279 new_start += rdev->mc.gtt_location; 279 new_start += rdev->mc.gtt_start;
280 break; 280 break;
281 default: 281 default:
282 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 282 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index 1e4582e27c14..626d51891ee9 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -151,9 +151,8 @@ int rs400_gart_enable(struct radeon_device *rdev)
151 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); 151 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
152 WREG32(RS480_AGP_BASE_2, 0); 152 WREG32(RS480_AGP_BASE_2, 0);
153 } 153 }
154 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; 154 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
155 tmp = REG_SET(RS690_MC_AGP_TOP, tmp >> 16); 155 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
156 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_location >> 16);
157 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 156 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
158 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); 157 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
159 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 158 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
@@ -252,14 +251,19 @@ void rs400_gpu_init(struct radeon_device *rdev)
252 } 251 }
253} 252}
254 253
255void rs400_vram_info(struct radeon_device *rdev) 254void rs400_mc_init(struct radeon_device *rdev)
256{ 255{
256 u64 base;
257
257 rs400_gart_adjust_size(rdev); 258 rs400_gart_adjust_size(rdev);
259 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
258 /* DDR for all card after R300 & IGP */ 260 /* DDR for all card after R300 & IGP */
259 rdev->mc.vram_is_ddr = true; 261 rdev->mc.vram_is_ddr = true;
260 rdev->mc.vram_width = 128; 262 rdev->mc.vram_width = 128;
261
262 r100_vram_init_sizes(rdev); 263 r100_vram_init_sizes(rdev);
264 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
265 radeon_vram_location(rdev, &rdev->mc, base);
266 radeon_gtt_location(rdev, &rdev->mc);
263} 267}
264 268
265uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) 269uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
@@ -363,22 +367,6 @@ static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
363#endif 367#endif
364} 368}
365 369
366static int rs400_mc_init(struct radeon_device *rdev)
367{
368 int r;
369 u32 tmp;
370
371 /* Setup GPU memory space */
372 tmp = RREG32(R_00015C_NB_TOM);
373 rdev->mc.vram_location = G_00015C_MC_FB_START(tmp) << 16;
374 rdev->mc.gtt_location = 0xFFFFFFFFUL;
375 r = radeon_mc_setup(rdev);
376 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
377 if (r)
378 return r;
379 return 0;
380}
381
382void rs400_mc_program(struct radeon_device *rdev) 370void rs400_mc_program(struct radeon_device *rdev)
383{ 371{
384 struct r100_mc_save save; 372 struct r100_mc_save save;
@@ -517,12 +505,8 @@ int rs400_init(struct radeon_device *rdev)
517 radeon_get_clock_info(rdev->ddev); 505 radeon_get_clock_info(rdev->ddev);
518 /* Initialize power management */ 506 /* Initialize power management */
519 radeon_pm_init(rdev); 507 radeon_pm_init(rdev);
520 /* Get vram informations */ 508 /* initialize memory controller */
521 rs400_vram_info(rdev); 509 rs400_mc_init(rdev);
522 /* Initialize memory controller (also test AGP) */
523 r = rs400_mc_init(rdev);
524 if (r)
525 return r;
526 /* Fence driver */ 510 /* Fence driver */
527 r = radeon_fence_driver_init(rdev); 511 r = radeon_fence_driver_init(rdev);
528 if (r) 512 if (r)
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 28c8690c7a35..d5aeb2a31d59 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -45,23 +45,6 @@
45void rs600_gpu_init(struct radeon_device *rdev); 45void rs600_gpu_init(struct radeon_device *rdev);
46int rs600_mc_wait_for_idle(struct radeon_device *rdev); 46int rs600_mc_wait_for_idle(struct radeon_device *rdev);
47 47
48int rs600_mc_init(struct radeon_device *rdev)
49{
50 /* read back the MC value from the hw */
51 int r;
52 u32 tmp;
53
54 /* Setup GPU memory space */
55 tmp = RREG32_MC(R_000004_MC_FB_LOCATION);
56 rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16;
57 rdev->mc.gtt_location = 0xffffffffUL;
58 r = radeon_mc_setup(rdev);
59 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
60 if (r)
61 return r;
62 return 0;
63}
64
65/* hpd for digital panel detect/disconnect */ 48/* hpd for digital panel detect/disconnect */
66bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 49bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
67{ 50{
@@ -475,22 +458,21 @@ void rs600_gpu_init(struct radeon_device *rdev)
475 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 458 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
476} 459}
477 460
478void rs600_vram_info(struct radeon_device *rdev) 461void rs600_mc_init(struct radeon_device *rdev)
479{ 462{
463 u64 base;
464
480 rdev->mc.vram_is_ddr = true; 465 rdev->mc.vram_is_ddr = true;
481 rdev->mc.vram_width = 128; 466 rdev->mc.vram_width = 128;
482
483 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 467 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
484 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 468 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
485
486 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 469 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
487 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 470 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
488 471 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
489 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) 472 base = RREG32_MC(R_000004_MC_FB_LOCATION);
490 rdev->mc.mc_vram_size = rdev->mc.aper_size; 473 base = G_000004_MC_FB_START(base) << 16;
491 474 radeon_vram_location(rdev, &rdev->mc, base);
492 if (rdev->mc.real_vram_size > rdev->mc.aper_size) 475 radeon_gtt_location(rdev, &rdev->mc);
493 rdev->mc.real_vram_size = rdev->mc.aper_size;
494} 476}
495 477
496void rs600_bandwidth_update(struct radeon_device *rdev) 478void rs600_bandwidth_update(struct radeon_device *rdev)
@@ -666,12 +648,8 @@ int rs600_init(struct radeon_device *rdev)
666 radeon_get_clock_info(rdev->ddev); 648 radeon_get_clock_info(rdev->ddev);
667 /* Initialize power management */ 649 /* Initialize power management */
668 radeon_pm_init(rdev); 650 radeon_pm_init(rdev);
669 /* Get vram informations */ 651 /* initialize memory controller */
670 rs600_vram_info(rdev); 652 rs600_mc_init(rdev);
671 /* Initialize memory controller (also test AGP) */
672 r = rs600_mc_init(rdev);
673 if (r)
674 return r;
675 rs600_debugfs(rdev); 653 rs600_debugfs(rdev);
676 /* Fence driver */ 654 /* Fence driver */
677 r = radeon_fence_driver_init(rdev); 655 r = radeon_fence_driver_init(rdev);
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 06e2771aee5a..8d37501da7df 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -129,27 +129,20 @@ void rs690_pm_info(struct radeon_device *rdev)
129 rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp); 129 rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp);
130} 130}
131 131
132void rs690_vram_info(struct radeon_device *rdev) 132void rs690_mc_init(struct radeon_device *rdev)
133{ 133{
134 fixed20_12 a; 134 fixed20_12 a;
135 u64 base;
135 136
136 rs400_gart_adjust_size(rdev); 137 rs400_gart_adjust_size(rdev);
137
138 rdev->mc.vram_is_ddr = true; 138 rdev->mc.vram_is_ddr = true;
139 rdev->mc.vram_width = 128; 139 rdev->mc.vram_width = 128;
140
141 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 140 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
142 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 141 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
143
144 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 142 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
145 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 143 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
146 144 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
147 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) 145 base = G_000100_MC_FB_START(base) << 16;
148 rdev->mc.mc_vram_size = rdev->mc.aper_size;
149
150 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
151 rdev->mc.real_vram_size = rdev->mc.aper_size;
152
153 rs690_pm_info(rdev); 146 rs690_pm_info(rdev);
154 /* FIXME: we should enforce default clock in case GPU is not in 147 /* FIXME: we should enforce default clock in case GPU is not in
155 * default setup 148 * default setup
@@ -160,22 +153,9 @@ void rs690_vram_info(struct radeon_device *rdev)
160 a.full = rfixed_const(16); 153 a.full = rfixed_const(16);
161 /* core_bandwidth = sclk(Mhz) * 16 */ 154 /* core_bandwidth = sclk(Mhz) * 16 */
162 rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a); 155 rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a);
163}
164
165static int rs690_mc_init(struct radeon_device *rdev)
166{
167 int r;
168 u32 tmp;
169
170 /* Setup GPU memory space */
171 tmp = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
172 rdev->mc.vram_location = G_000100_MC_FB_START(tmp) << 16;
173 rdev->mc.gtt_location = 0xFFFFFFFFUL;
174 r = radeon_mc_setup(rdev);
175 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 156 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
176 if (r) 157 radeon_vram_location(rdev, &rdev->mc, base);
177 return r; 158 radeon_gtt_location(rdev, &rdev->mc);
178 return 0;
179} 159}
180 160
181void rs690_line_buffer_adjust(struct radeon_device *rdev, 161void rs690_line_buffer_adjust(struct radeon_device *rdev,
@@ -728,12 +708,8 @@ int rs690_init(struct radeon_device *rdev)
728 radeon_get_clock_info(rdev->ddev); 708 radeon_get_clock_info(rdev->ddev);
729 /* Initialize power management */ 709 /* Initialize power management */
730 radeon_pm_init(rdev); 710 radeon_pm_init(rdev);
731 /* Get vram informations */ 711 /* initialize memory controller */
732 rs690_vram_info(rdev); 712 rs690_mc_init(rdev);
733 /* Initialize memory controller (also test AGP) */
734 r = rs690_mc_init(rdev);
735 if (r)
736 return r;
737 rv515_debugfs(rdev); 713 rv515_debugfs(rdev);
738 /* Fence driver */ 714 /* Fence driver */
739 r = radeon_fence_driver_init(rdev); 715 r = radeon_fence_driver_init(rdev);
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 0e1e6b8632b8..bea747da123f 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -277,13 +277,15 @@ static void rv515_vram_get_type(struct radeon_device *rdev)
277 } 277 }
278} 278}
279 279
280void rv515_vram_info(struct radeon_device *rdev) 280void rv515_mc_init(struct radeon_device *rdev)
281{ 281{
282 fixed20_12 a; 282 fixed20_12 a;
283 283
284 rv515_vram_get_type(rdev); 284 rv515_vram_get_type(rdev);
285
286 r100_vram_init_sizes(rdev); 285 r100_vram_init_sizes(rdev);
286 radeon_vram_location(rdev, &rdev->mc, 0);
287 if (!(rdev->flags & RADEON_IS_AGP))
288 radeon_gtt_location(rdev, &rdev->mc);
287 /* FIXME: we should enforce default clock in case GPU is not in 289 /* FIXME: we should enforce default clock in case GPU is not in
288 * default setup 290 * default setup
289 */ 291 */
@@ -587,12 +589,15 @@ int rv515_init(struct radeon_device *rdev)
587 radeon_get_clock_info(rdev->ddev); 589 radeon_get_clock_info(rdev->ddev);
588 /* Initialize power management */ 590 /* Initialize power management */
589 radeon_pm_init(rdev); 591 radeon_pm_init(rdev);
590 /* Get vram informations */ 592 /* initialize AGP */
591 rv515_vram_info(rdev); 593 if (rdev->flags & RADEON_IS_AGP) {
592 /* Initialize memory controller (also test AGP) */ 594 r = radeon_agp_init(rdev);
593 r = r420_mc_init(rdev); 595 if (r) {
594 if (r) 596 radeon_agp_disable(rdev);
595 return r; 597 }
598 }
599 /* initialize memory controller */
600 rv515_mc_init(rdev);
596 rv515_debugfs(rdev); 601 rv515_debugfs(rdev);
597 /* Fence driver */ 602 /* Fence driver */
598 r = radeon_fence_driver_init(rdev); 603 r = radeon_fence_driver_init(rdev);
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 6f1f4abbe88c..323fa6be5082 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -820,45 +820,12 @@ int rv770_mc_init(struct radeon_device *rdev)
820 /* Setup GPU memory space */ 820 /* Setup GPU memory space */
821 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 821 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
822 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 822 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
823 823 /* FIXME remove this once we support unmappable VRAM */
824 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) 824 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
825 rdev->mc.mc_vram_size = rdev->mc.aper_size; 825 rdev->mc.mc_vram_size = rdev->mc.aper_size;
826
827 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
828 rdev->mc.real_vram_size = rdev->mc.aper_size; 826 rdev->mc.real_vram_size = rdev->mc.aper_size;
829
830 if (rdev->flags & RADEON_IS_AGP) {
831 /* gtt_size is setup by radeon_agp_init */
832 rdev->mc.gtt_location = rdev->mc.agp_base;
833 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
834 /* Try to put vram before or after AGP because we
835 * we want SYSTEM_APERTURE to cover both VRAM and
836 * AGP so that GPU can catch out of VRAM/AGP access
837 */
838 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
839 /* Enought place before */
840 rdev->mc.vram_location = rdev->mc.gtt_location -
841 rdev->mc.mc_vram_size;
842 } else if (tmp > rdev->mc.mc_vram_size) {
843 /* Enought place after */
844 rdev->mc.vram_location = rdev->mc.gtt_location +
845 rdev->mc.gtt_size;
846 } else {
847 /* Try to setup VRAM then AGP might not
848 * not work on some card
849 */
850 rdev->mc.vram_location = 0x00000000UL;
851 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
852 }
853 } else {
854 rdev->mc.vram_location = 0x00000000UL;
855 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
856 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
857 } 827 }
858 rdev->mc.vram_start = rdev->mc.vram_location; 828 r600_vram_gtt_location(rdev, &rdev->mc);
859 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
860 rdev->mc.gtt_start = rdev->mc.gtt_location;
861 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
862 /* FIXME: we should enforce default clock in case GPU is not in 829 /* FIXME: we should enforce default clock in case GPU is not in
863 * default setup 830 * default setup
864 */ 831 */
@@ -867,6 +834,7 @@ int rv770_mc_init(struct radeon_device *rdev)
867 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); 834 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
868 return 0; 835 return 0;
869} 836}
837
870int rv770_gpu_reset(struct radeon_device *rdev) 838int rv770_gpu_reset(struct radeon_device *rdev)
871{ 839{
872 /* FIXME: implement any rv770 specific bits */ 840 /* FIXME: implement any rv770 specific bits */
@@ -1042,6 +1010,7 @@ int rv770_init(struct radeon_device *rdev)
1042 r = radeon_fence_driver_init(rdev); 1010 r = radeon_fence_driver_init(rdev);
1043 if (r) 1011 if (r)
1044 return r; 1012 return r;
1013 /* initialize AGP */
1045 if (rdev->flags & RADEON_IS_AGP) { 1014 if (rdev->flags & RADEON_IS_AGP) {
1046 r = radeon_agp_init(rdev); 1015 r = radeon_agp_init(rdev);
1047 if (r) 1016 if (r)