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authorDavid S. Miller <davem@davemloft.net>2008-03-26 03:19:43 -0400
committerDavid S. Miller <davem@davemloft.net>2008-03-26 03:19:43 -0400
commit99cd220133cdf2a559529d522a78b2ebc1bef2d8 (patch)
treef65066410c4166880d0a7b5210227370c53b0010
parent3d5ae6b69eacfac025021998d2ce159768edcfe1 (diff)
[SPARC64]: Fix sparse errors in arch/sparc64/kernel/traps.c
Add 'UL' markers to DCU_* macros. Declare C functions called from assembler in entry.h Declare C functions called from within the sparc64 arch code in include/asm-sparc64/*.h headers as appropriate. Remove unused routines in traps.c Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--arch/sparc64/kernel/entry.h141
-rw-r--r--arch/sparc64/kernel/traps.c49
-rw-r--r--arch/sparc64/mm/init.c4
-rw-r--r--include/asm-sparc64/dcu.h41
-rw-r--r--include/asm-sparc64/pgtable.h2
5 files changed, 167 insertions, 70 deletions
diff --git a/arch/sparc64/kernel/entry.h b/arch/sparc64/kernel/entry.h
index bfcd1b8d23dc..a5084d6821ba 100644
--- a/arch/sparc64/kernel/entry.h
+++ b/arch/sparc64/kernel/entry.h
@@ -2,6 +2,7 @@
2#define _ENTRY_H 2#define _ENTRY_H
3 3
4#include <linux/init.h> 4#include <linux/init.h>
5#include <linux/types.h>
5 6
6extern char *sparc_cpu_type; 7extern char *sparc_cpu_type;
7extern char *sparc_fpu_type; 8extern char *sparc_fpu_type;
@@ -12,4 +13,144 @@ extern void __init boot_cpu_id_too_large(int cpu);
12extern unsigned int dcache_parity_tl1_occurred; 13extern unsigned int dcache_parity_tl1_occurred;
13extern unsigned int icache_parity_tl1_occurred; 14extern unsigned int icache_parity_tl1_occurred;
14 15
16extern void bad_trap_tl1(struct pt_regs *regs, long lvl);
17
18extern void do_fpe_common(struct pt_regs *regs);
19extern void do_fpieee(struct pt_regs *regs);
20extern void do_fpother(struct pt_regs *regs);
21extern void do_tof(struct pt_regs *regs);
22extern void do_div0(struct pt_regs *regs);
23extern void do_illegal_instruction(struct pt_regs *regs);
24extern void mem_address_unaligned(struct pt_regs *regs,
25 unsigned long sfar,
26 unsigned long sfsr);
27extern void sun4v_do_mna(struct pt_regs *regs,
28 unsigned long addr,
29 unsigned long type_ctx);
30extern void do_privop(struct pt_regs *regs);
31extern void do_privact(struct pt_regs *regs);
32extern void do_cee(struct pt_regs *regs);
33extern void do_cee_tl1(struct pt_regs *regs);
34extern void do_dae_tl1(struct pt_regs *regs);
35extern void do_iae_tl1(struct pt_regs *regs);
36extern void do_div0_tl1(struct pt_regs *regs);
37extern void do_fpdis_tl1(struct pt_regs *regs);
38extern void do_fpieee_tl1(struct pt_regs *regs);
39extern void do_fpother_tl1(struct pt_regs *regs);
40extern void do_ill_tl1(struct pt_regs *regs);
41extern void do_irq_tl1(struct pt_regs *regs);
42extern void do_lddfmna_tl1(struct pt_regs *regs);
43extern void do_stdfmna_tl1(struct pt_regs *regs);
44extern void do_paw(struct pt_regs *regs);
45extern void do_paw_tl1(struct pt_regs *regs);
46extern void do_vaw(struct pt_regs *regs);
47extern void do_vaw_tl1(struct pt_regs *regs);
48extern void do_tof_tl1(struct pt_regs *regs);
49extern void do_getpsr(struct pt_regs *regs);
50
51extern void spitfire_insn_access_exception(struct pt_regs *regs,
52 unsigned long sfsr,
53 unsigned long sfar);
54extern void spitfire_insn_access_exception_tl1(struct pt_regs *regs,
55 unsigned long sfsr,
56 unsigned long sfar);
57extern void spitfire_data_access_exception(struct pt_regs *regs,
58 unsigned long sfsr,
59 unsigned long sfar);
60extern void spitfire_data_access_exception_tl1(struct pt_regs *regs,
61 unsigned long sfsr,
62 unsigned long sfar);
63extern void spitfire_access_error(struct pt_regs *regs,
64 unsigned long status_encoded,
65 unsigned long afar);
66
67extern void cheetah_fecc_handler(struct pt_regs *regs,
68 unsigned long afsr,
69 unsigned long afar);
70extern void cheetah_cee_handler(struct pt_regs *regs,
71 unsigned long afsr,
72 unsigned long afar);
73extern void cheetah_deferred_handler(struct pt_regs *regs,
74 unsigned long afsr,
75 unsigned long afar);
76extern void cheetah_plus_parity_error(int type, struct pt_regs *regs);
77
78extern void sun4v_insn_access_exception(struct pt_regs *regs,
79 unsigned long addr,
80 unsigned long type_ctx);
81extern void sun4v_insn_access_exception_tl1(struct pt_regs *regs,
82 unsigned long addr,
83 unsigned long type_ctx);
84extern void sun4v_data_access_exception(struct pt_regs *regs,
85 unsigned long addr,
86 unsigned long type_ctx);
87extern void sun4v_data_access_exception_tl1(struct pt_regs *regs,
88 unsigned long addr,
89 unsigned long type_ctx);
90extern void sun4v_resum_error(struct pt_regs *regs,
91 unsigned long offset);
92extern void sun4v_resum_overflow(struct pt_regs *regs);
93extern void sun4v_nonresum_error(struct pt_regs *regs,
94 unsigned long offset);
95extern void sun4v_nonresum_overflow(struct pt_regs *regs);
96
97extern unsigned long sun4v_err_itlb_vaddr;
98extern unsigned long sun4v_err_itlb_ctx;
99extern unsigned long sun4v_err_itlb_pte;
100extern unsigned long sun4v_err_itlb_error;
101
102extern void sun4v_itlb_error_report(struct pt_regs *regs, int tl);
103
104extern unsigned long sun4v_err_dtlb_vaddr;
105extern unsigned long sun4v_err_dtlb_ctx;
106extern unsigned long sun4v_err_dtlb_pte;
107extern unsigned long sun4v_err_dtlb_error;
108
109extern void sun4v_dtlb_error_report(struct pt_regs *regs, int tl);
110extern void hypervisor_tlbop_error(unsigned long err,
111 unsigned long op);
112extern void hypervisor_tlbop_error_xcall(unsigned long err,
113 unsigned long op);
114
115/* WARNING: The error trap handlers in assembly know the precise
116 * layout of the following structure.
117 *
118 * C-level handlers in traps.c use this information to log the
119 * error and then determine how to recover (if possible).
120 */
121struct cheetah_err_info {
122/*0x00*/u64 afsr;
123/*0x08*/u64 afar;
124
125 /* D-cache state */
126/*0x10*/u64 dcache_data[4]; /* The actual data */
127/*0x30*/u64 dcache_index; /* D-cache index */
128/*0x38*/u64 dcache_tag; /* D-cache tag/valid */
129/*0x40*/u64 dcache_utag; /* D-cache microtag */
130/*0x48*/u64 dcache_stag; /* D-cache snooptag */
131
132 /* I-cache state */
133/*0x50*/u64 icache_data[8]; /* The actual insns + predecode */
134/*0x90*/u64 icache_index; /* I-cache index */
135/*0x98*/u64 icache_tag; /* I-cache phys tag */
136/*0xa0*/u64 icache_utag; /* I-cache microtag */
137/*0xa8*/u64 icache_stag; /* I-cache snooptag */
138/*0xb0*/u64 icache_upper; /* I-cache upper-tag */
139/*0xb8*/u64 icache_lower; /* I-cache lower-tag */
140
141 /* E-cache state */
142/*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */
143/*0xe0*/u64 ecache_index; /* E-cache index */
144/*0xe8*/u64 ecache_tag; /* E-cache tag/state */
145
146/*0xf0*/u64 __pad[32 - 30];
147};
148#define CHAFSR_INVALID ((u64)-1L)
149
150/* This is allocated at boot time based upon the largest hardware
151 * cpu ID in the system. We allocate two entries per cpu, one for
152 * TL==0 logging and one for TL >= 1 logging.
153 */
154extern struct cheetah_err_info *cheetah_error_log;
155
15#endif /* _ENTRY_H */ 156#endif /* _ENTRY_H */
diff --git a/arch/sparc64/kernel/traps.c b/arch/sparc64/kernel/traps.c
index 007f5317c0de..96da847023f3 100644
--- a/arch/sparc64/kernel/traps.c
+++ b/arch/sparc64/kernel/traps.c
@@ -42,6 +42,7 @@
42#endif 42#endif
43#include <asm/prom.h> 43#include <asm/prom.h>
44 44
45#include "entry.h"
45 46
46/* When an irrecoverable trap occurs at tl > 0, the trap entry 47/* When an irrecoverable trap occurs at tl > 0, the trap entry
47 * code logs the trap state registers at every level in the trap 48 * code logs the trap state registers at every level in the trap
@@ -77,11 +78,6 @@ static void dump_tl1_traplog(struct tl1_traplog *p)
77 } 78 }
78} 79}
79 80
80void do_call_debug(struct pt_regs *regs)
81{
82 notify_die(DIE_CALL, "debug call", regs, 0, 255, SIGINT);
83}
84
85void bad_trap(struct pt_regs *regs, long lvl) 81void bad_trap(struct pt_regs *regs, long lvl)
86{ 82{
87 char buffer[32]; 83 char buffer[32];
@@ -550,41 +546,6 @@ static unsigned long ecache_flush_physbase;
550static unsigned long ecache_flush_linesize; 546static unsigned long ecache_flush_linesize;
551static unsigned long ecache_flush_size; 547static unsigned long ecache_flush_size;
552 548
553/* WARNING: The error trap handlers in assembly know the precise
554 * layout of the following structure.
555 *
556 * C-level handlers below use this information to log the error
557 * and then determine how to recover (if possible).
558 */
559struct cheetah_err_info {
560/*0x00*/u64 afsr;
561/*0x08*/u64 afar;
562
563 /* D-cache state */
564/*0x10*/u64 dcache_data[4]; /* The actual data */
565/*0x30*/u64 dcache_index; /* D-cache index */
566/*0x38*/u64 dcache_tag; /* D-cache tag/valid */
567/*0x40*/u64 dcache_utag; /* D-cache microtag */
568/*0x48*/u64 dcache_stag; /* D-cache snooptag */
569
570 /* I-cache state */
571/*0x50*/u64 icache_data[8]; /* The actual insns + predecode */
572/*0x90*/u64 icache_index; /* I-cache index */
573/*0x98*/u64 icache_tag; /* I-cache phys tag */
574/*0xa0*/u64 icache_utag; /* I-cache microtag */
575/*0xa8*/u64 icache_stag; /* I-cache snooptag */
576/*0xb0*/u64 icache_upper; /* I-cache upper-tag */
577/*0xb8*/u64 icache_lower; /* I-cache lower-tag */
578
579 /* E-cache state */
580/*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */
581/*0xe0*/u64 ecache_index; /* E-cache index */
582/*0xe8*/u64 ecache_tag; /* E-cache tag/state */
583
584/*0xf0*/u64 __pad[32 - 30];
585};
586#define CHAFSR_INVALID ((u64)-1L)
587
588/* This table is ordered in priority of errors and matches the 549/* This table is ordered in priority of errors and matches the
589 * AFAR overwrite policy as well. 550 * AFAR overwrite policy as well.
590 */ 551 */
@@ -758,10 +719,6 @@ static struct afsr_error_table __jalapeno_error_table[] = {
758static struct afsr_error_table *cheetah_error_table; 719static struct afsr_error_table *cheetah_error_table;
759static unsigned long cheetah_afsr_errors; 720static unsigned long cheetah_afsr_errors;
760 721
761/* This is allocated at boot time based upon the largest hardware
762 * cpu ID in the system. We allocate two entries per cpu, one for
763 * TL==0 logging and one for TL >= 1 logging.
764 */
765struct cheetah_err_info *cheetah_error_log; 722struct cheetah_err_info *cheetah_error_log;
766 723
767static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr) 724static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
@@ -2102,7 +2059,7 @@ void do_div0(struct pt_regs *regs)
2102 force_sig_info(SIGFPE, &info, current); 2059 force_sig_info(SIGFPE, &info, current);
2103} 2060}
2104 2061
2105void instruction_dump (unsigned int *pc) 2062static void instruction_dump(unsigned int *pc)
2106{ 2063{
2107 int i; 2064 int i;
2108 2065
@@ -2115,7 +2072,7 @@ void instruction_dump (unsigned int *pc)
2115 printk("\n"); 2072 printk("\n");
2116} 2073}
2117 2074
2118static void user_instruction_dump (unsigned int __user *pc) 2075static void user_instruction_dump(unsigned int __user *pc)
2119{ 2076{
2120 int i; 2077 int i;
2121 unsigned int buf[9]; 2078 unsigned int buf[9];
diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
index fced6dfe77a8..f37078d96407 100644
--- a/arch/sparc64/mm/init.c
+++ b/arch/sparc64/mm/init.c
@@ -1274,10 +1274,6 @@ void __cpuinit sun4v_ktsb_register(void)
1274 1274
1275/* paging_init() sets up the page tables */ 1275/* paging_init() sets up the page tables */
1276 1276
1277extern void cheetah_ecache_flush_init(void);
1278extern void sun4v_patch_tlb_handlers(void);
1279
1280extern void cpu_probe(void);
1281extern void central_probe(void); 1277extern void central_probe(void);
1282 1278
1283static unsigned long last_valid_pfn; 1279static unsigned long last_valid_pfn;
diff --git a/include/asm-sparc64/dcu.h b/include/asm-sparc64/dcu.h
index ecbed2ae548f..0f704e106a1b 100644
--- a/include/asm-sparc64/dcu.h
+++ b/include/asm-sparc64/dcu.h
@@ -1,26 +1,27 @@
1/* $Id: dcu.h,v 1.2 2001/03/01 23:23:33 davem Exp $ */
2#ifndef _SPARC64_DCU_H 1#ifndef _SPARC64_DCU_H
3#define _SPARC64_DCU_H 2#define _SPARC64_DCU_H
4 3
4#include <linux/const.h>
5
5/* UltraSparc-III Data Cache Unit Control Register */ 6/* UltraSparc-III Data Cache Unit Control Register */
6#define DCU_CP 0x0002000000000000 /* Physical Cache Enable w/o mmu*/ 7#define DCU_CP _AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu */
7#define DCU_CV 0x0001000000000000 /* Virtual Cache Enable w/o mmu */ 8#define DCU_CV _AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu */
8#define DCU_ME 0x0000800000000000 /* NC-store Merging Enable */ 9#define DCU_ME _AC(0x0000800000000000,UL) /* NC-store Merging Enable */
9#define DCU_RE 0x0000400000000000 /* RAW bypass Enable */ 10#define DCU_RE _AC(0x0000400000000000,UL) /* RAW bypass Enable */
10#define DCU_PE 0x0000200000000000 /* PCache Enable */ 11#define DCU_PE _AC(0x0000200000000000,UL) /* PCache Enable */
11#define DCU_HPE 0x0000100000000000 /* HW prefetch Enable */ 12#define DCU_HPE _AC(0x0000100000000000,UL) /* HW prefetch Enable */
12#define DCU_SPE 0x0000080000000000 /* SW prefetch Enable */ 13#define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable */
13#define DCU_SL 0x0000040000000000 /* Secondary load steering Enab */ 14#define DCU_SL _AC(0x0000040000000000,UL) /* Secondary ld-steering Enab*/
14#define DCU_WE 0x0000020000000000 /* WCache enable */ 15#define DCU_WE _AC(0x0000020000000000,UL) /* WCache enable */
15#define DCU_PM 0x000001fe00000000 /* PA Watchpoint Byte Mask */ 16#define DCU_PM _AC(0x000001fe00000000,UL) /* PA Watchpoint Byte Mask */
16#define DCU_VM 0x00000001fe000000 /* VA Watchpoint Byte Mask */ 17#define DCU_VM _AC(0x00000001fe000000,UL) /* VA Watchpoint Byte Mask */
17#define DCU_PR 0x0000000001000000 /* PA Watchpoint Read Enable */ 18#define DCU_PR _AC(0x0000000001000000,UL) /* PA Watchpoint Read Enable */
18#define DCU_PW 0x0000000000800000 /* PA Watchpoint Write Enable */ 19#define DCU_PW _AC(0x0000000000800000,UL) /* PA Watchpoint Write Enable*/
19#define DCU_VR 0x0000000000400000 /* VA Watchpoint Read Enable */ 20#define DCU_VR _AC(0x0000000000400000,UL) /* VA Watchpoint Read Enable */
20#define DCU_VW 0x0000000000200000 /* VA Watchpoint Write Enable */ 21#define DCU_VW _AC(0x0000000000200000,UL) /* VA Watchpoint Write Enable*/
21#define DCU_DM 0x0000000000000008 /* DMMU Enable */ 22#define DCU_DM _AC(0x0000000000000008,UL) /* DMMU Enable */
22#define DCU_IM 0x0000000000000004 /* IMMU Enable */ 23#define DCU_IM _AC(0x0000000000000004,UL) /* IMMU Enable */
23#define DCU_DC 0x0000000000000002 /* Data Cache Enable */ 24#define DCU_DC _AC(0x0000000000000002,UL) /* Data Cache Enable */
24#define DCU_IC 0x0000000000000001 /* Instruction Cache Enable */ 25#define DCU_IC _AC(0x0000000000000001,UL) /* Instruction Cache Enable */
25 26
26#endif /* _SPARC64_DCU_H */ 27#endif /* _SPARC64_DCU_H */
diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h
index 95303f5be86b..549e45266b68 100644
--- a/include/asm-sparc64/pgtable.h
+++ b/include/asm-sparc64/pgtable.h
@@ -761,6 +761,8 @@ extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
761extern void pgtable_cache_init(void); 761extern void pgtable_cache_init(void);
762extern void sun4v_register_fault_status(void); 762extern void sun4v_register_fault_status(void);
763extern void sun4v_ktsb_register(void); 763extern void sun4v_ktsb_register(void);
764extern void __init cheetah_ecache_flush_init(void);
765extern void sun4v_patch_tlb_handlers(void);
764 766
765extern unsigned long cmdline_memory_size; 767extern unsigned long cmdline_memory_size;
766 768
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 20:50:33 -0500