diff options
author | Divy Le Ray <divy@chelsio.com> | 2007-09-05 18:58:15 -0400 |
---|---|---|
committer | David S. Miller <davem@sunset.davemloft.net> | 2007-10-10 19:51:03 -0400 |
commit | 3eea3337a08a2ed2addac1551a9d446f2c16acd5 (patch) | |
tree | 74896c03574ed13bd455384523adcab75613c0fc | |
parent | a5a3b4601bfa3c7671944067d4e4b04bf647e6d9 (diff) |
cxgb3 - log and clear PEX errors
Clear pciE PEX errors late at module load time.
Log details when PEX errors occur.
Signed-off-by: Divy Le Ray <divy@chelsio.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
-rw-r--r-- | drivers/net/cxgb3/t3_hw.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/cxgb3/t3_hw.c b/drivers/net/cxgb3/t3_hw.c index 2b49b96a6fdb..cdcfc132e37d 100644 --- a/drivers/net/cxgb3/t3_hw.c +++ b/drivers/net/cxgb3/t3_hw.c | |||
@@ -1358,6 +1358,10 @@ static void pcie_intr_handler(struct adapter *adapter) | |||
1358 | {0} | 1358 | {0} |
1359 | }; | 1359 | }; |
1360 | 1360 | ||
1361 | if (t3_read_reg(adapter, A_PCIE_INT_CAUSE) & F_PEXERR) | ||
1362 | CH_ALERT(adapter, "PEX error code 0x%x\n", | ||
1363 | t3_read_reg(adapter, A_PCIE_PEX_ERR)); | ||
1364 | |||
1361 | if (t3_handle_intr_status(adapter, A_PCIE_INT_CAUSE, PCIE_INTR_MASK, | 1365 | if (t3_handle_intr_status(adapter, A_PCIE_INT_CAUSE, PCIE_INTR_MASK, |
1362 | pcie_intr_info, adapter->irq_stats)) | 1366 | pcie_intr_info, adapter->irq_stats)) |
1363 | t3_fatal_err(adapter); | 1367 | t3_fatal_err(adapter); |
@@ -1809,6 +1813,8 @@ void t3_intr_clear(struct adapter *adapter) | |||
1809 | for (i = 0; i < ARRAY_SIZE(cause_reg_addr); ++i) | 1813 | for (i = 0; i < ARRAY_SIZE(cause_reg_addr); ++i) |
1810 | t3_write_reg(adapter, cause_reg_addr[i], 0xffffffff); | 1814 | t3_write_reg(adapter, cause_reg_addr[i], 0xffffffff); |
1811 | 1815 | ||
1816 | if (is_pcie(adapter)) | ||
1817 | t3_write_reg(adapter, A_PCIE_PEX_ERR, 0xffffffff); | ||
1812 | t3_write_reg(adapter, A_PL_INT_CAUSE0, 0xffffffff); | 1818 | t3_write_reg(adapter, A_PL_INT_CAUSE0, 0xffffffff); |
1813 | t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */ | 1819 | t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */ |
1814 | } | 1820 | } |