diff options
author | Andrew Victor <linux@maxim.org.za> | 2008-04-02 16:38:40 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-04-04 04:52:18 -0400 |
commit | b78eabde89f9b19d463a77abe420508c0ef29249 (patch) | |
tree | 87ea72234455b7fa72cb9f6311948fa0146813ee | |
parent | 3ad0920d7b11a88379ec4db186be3eee667c4278 (diff) |
[ARM] 4902/1: [AT91] SAM9/CAP9 memory controller header
The AT91CAP9 processor includes the same Static Memory Controller
(SMC) peripheral as the SAM9 processors, but replaces the SDRAM
Controller with a DDR/SDR Controller (DDRSDRC).
This patch splits the existing
include/asm-arm/arch-at91/at91sam926x_mc.h into at91sam9_sdramc.h and
at91sam9_smc.h.
It also adds an at91cap9_ddrsdr.h for the DDRSDRC controller.
Signed-off-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r-- | arch/arm/mach-at91/at91cap9_devices.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/at91sam9260_devices.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/at91sam9261_devices.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/at91sam9263_devices.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/at91sam9rl_devices.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/board-cap9adk.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/board-sam9260ek.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/board-sam9261ek.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/board-sam9263ek.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/board-sam9rlek.c | 2 | ||||
-rw-r--r-- | include/asm-arm/arch-at91/at91cap9_ddrsdr.h | 100 | ||||
-rw-r--r-- | include/asm-arm/arch-at91/at91sam9_sdramc.h (renamed from include/asm-arm/arch-at91/at91sam926x_mc.h) | 68 | ||||
-rw-r--r-- | include/asm-arm/arch-at91/at91sam9_smc.h | 73 |
13 files changed, 188 insertions, 73 deletions
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c index c50fad9cd143..0c341a4624ff 100644 --- a/arch/arm/mach-at91/at91cap9_devices.c +++ b/arch/arm/mach-at91/at91cap9_devices.c | |||
@@ -23,8 +23,8 @@ | |||
23 | #include <asm/arch/board.h> | 23 | #include <asm/arch/board.h> |
24 | #include <asm/arch/gpio.h> | 24 | #include <asm/arch/gpio.h> |
25 | #include <asm/arch/at91cap9.h> | 25 | #include <asm/arch/at91cap9.h> |
26 | #include <asm/arch/at91sam926x_mc.h> | ||
27 | #include <asm/arch/at91cap9_matrix.h> | 26 | #include <asm/arch/at91cap9_matrix.h> |
27 | #include <asm/arch/at91sam9_smc.h> | ||
28 | 28 | ||
29 | #include "generic.h" | 29 | #include "generic.h" |
30 | 30 | ||
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index 105f8403860b..b758e66c60f8 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c | |||
@@ -19,8 +19,8 @@ | |||
19 | #include <asm/arch/board.h> | 19 | #include <asm/arch/board.h> |
20 | #include <asm/arch/gpio.h> | 20 | #include <asm/arch/gpio.h> |
21 | #include <asm/arch/at91sam9260.h> | 21 | #include <asm/arch/at91sam9260.h> |
22 | #include <asm/arch/at91sam926x_mc.h> | ||
23 | #include <asm/arch/at91sam9260_matrix.h> | 22 | #include <asm/arch/at91sam9260_matrix.h> |
23 | #include <asm/arch/at91sam9_smc.h> | ||
24 | 24 | ||
25 | #include "generic.h" | 25 | #include "generic.h" |
26 | 26 | ||
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index 245641263fce..48ecbeffd9b0 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c | |||
@@ -24,7 +24,7 @@ | |||
24 | #include <asm/arch/gpio.h> | 24 | #include <asm/arch/gpio.h> |
25 | #include <asm/arch/at91sam9261.h> | 25 | #include <asm/arch/at91sam9261.h> |
26 | #include <asm/arch/at91sam9261_matrix.h> | 26 | #include <asm/arch/at91sam9261_matrix.h> |
27 | #include <asm/arch/at91sam926x_mc.h> | 27 | #include <asm/arch/at91sam9_smc.h> |
28 | 28 | ||
29 | #include "generic.h" | 29 | #include "generic.h" |
30 | 30 | ||
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index 0b12e1adcc8e..fc14af8617f0 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c | |||
@@ -22,8 +22,8 @@ | |||
22 | #include <asm/arch/board.h> | 22 | #include <asm/arch/board.h> |
23 | #include <asm/arch/gpio.h> | 23 | #include <asm/arch/gpio.h> |
24 | #include <asm/arch/at91sam9263.h> | 24 | #include <asm/arch/at91sam9263.h> |
25 | #include <asm/arch/at91sam926x_mc.h> | ||
26 | #include <asm/arch/at91sam9263_matrix.h> | 25 | #include <asm/arch/at91sam9263_matrix.h> |
26 | #include <asm/arch/at91sam9_smc.h> | ||
27 | 27 | ||
28 | #include "generic.h" | 28 | #include "generic.h" |
29 | 29 | ||
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c index f43b5c33e45d..fb74b33bba68 100644 --- a/arch/arm/mach-at91/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/at91sam9rl_devices.c | |||
@@ -20,7 +20,7 @@ | |||
20 | #include <asm/arch/gpio.h> | 20 | #include <asm/arch/gpio.h> |
21 | #include <asm/arch/at91sam9rl.h> | 21 | #include <asm/arch/at91sam9rl.h> |
22 | #include <asm/arch/at91sam9rl_matrix.h> | 22 | #include <asm/arch/at91sam9rl_matrix.h> |
23 | #include <asm/arch/at91sam926x_mc.h> | 23 | #include <asm/arch/at91sam9_smc.h> |
24 | 24 | ||
25 | #include "generic.h" | 25 | #include "generic.h" |
26 | 26 | ||
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c index 185437131541..e5512d1ff217 100644 --- a/arch/arm/mach-at91/board-cap9adk.c +++ b/arch/arm/mach-at91/board-cap9adk.c | |||
@@ -45,7 +45,7 @@ | |||
45 | #include <asm/arch/board.h> | 45 | #include <asm/arch/board.h> |
46 | #include <asm/arch/gpio.h> | 46 | #include <asm/arch/gpio.h> |
47 | #include <asm/arch/at91cap9_matrix.h> | 47 | #include <asm/arch/at91cap9_matrix.h> |
48 | #include <asm/arch/at91sam926x_mc.h> | 48 | #include <asm/arch/at91sam9_smc.h> |
49 | 49 | ||
50 | #include "generic.h" | 50 | #include "generic.h" |
51 | 51 | ||
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c index b343a6c28120..8c657a9288ee 100644 --- a/arch/arm/mach-at91/board-sam9260ek.c +++ b/arch/arm/mach-at91/board-sam9260ek.c | |||
@@ -37,7 +37,7 @@ | |||
37 | 37 | ||
38 | #include <asm/arch/board.h> | 38 | #include <asm/arch/board.h> |
39 | #include <asm/arch/gpio.h> | 39 | #include <asm/arch/gpio.h> |
40 | #include <asm/arch/at91sam926x_mc.h> | 40 | #include <asm/arch/at91sam9_smc.h> |
41 | 41 | ||
42 | #include "generic.h" | 42 | #include "generic.h" |
43 | 43 | ||
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index 0ce38dfa6ebe..f71ff750b3d2 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c | |||
@@ -44,7 +44,7 @@ | |||
44 | 44 | ||
45 | #include <asm/arch/board.h> | 45 | #include <asm/arch/board.h> |
46 | #include <asm/arch/gpio.h> | 46 | #include <asm/arch/gpio.h> |
47 | #include <asm/arch/at91sam926x_mc.h> | 47 | #include <asm/arch/at91sam9_smc.h> |
48 | 48 | ||
49 | #include "generic.h" | 49 | #include "generic.h" |
50 | 50 | ||
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c index bf103b24c937..a65bd1654021 100644 --- a/arch/arm/mach-at91/board-sam9263ek.c +++ b/arch/arm/mach-at91/board-sam9263ek.c | |||
@@ -43,7 +43,7 @@ | |||
43 | 43 | ||
44 | #include <asm/arch/board.h> | 44 | #include <asm/arch/board.h> |
45 | #include <asm/arch/gpio.h> | 45 | #include <asm/arch/gpio.h> |
46 | #include <asm/arch/at91sam926x_mc.h> | 46 | #include <asm/arch/at91sam9_smc.h> |
47 | 47 | ||
48 | #include "generic.h" | 48 | #include "generic.h" |
49 | 49 | ||
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c index bc0546d7245f..ce83b60c450d 100644 --- a/arch/arm/mach-at91/board-sam9rlek.c +++ b/arch/arm/mach-at91/board-sam9rlek.c | |||
@@ -29,7 +29,7 @@ | |||
29 | 29 | ||
30 | #include <asm/arch/board.h> | 30 | #include <asm/arch/board.h> |
31 | #include <asm/arch/gpio.h> | 31 | #include <asm/arch/gpio.h> |
32 | #include <asm/arch/at91sam926x_mc.h> | 32 | #include <asm/arch/at91sam9_smc.h> |
33 | 33 | ||
34 | #include "generic.h" | 34 | #include "generic.h" |
35 | 35 | ||
diff --git a/include/asm-arm/arch-at91/at91cap9_ddrsdr.h b/include/asm-arm/arch-at91/at91cap9_ddrsdr.h new file mode 100644 index 000000000000..efdb23af1ee4 --- /dev/null +++ b/include/asm-arm/arch-at91/at91cap9_ddrsdr.h | |||
@@ -0,0 +1,100 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-at91/at91cap9_ddrsdr.h | ||
3 | * | ||
4 | * DDR/SDR Controller (DDRSDRC) - System peripherals registers. | ||
5 | * Based on AT91CAP9 datasheet revision B. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | */ | ||
12 | |||
13 | #ifndef AT91CAP9_DDRSDR_H | ||
14 | #define AT91CAP9_DDRSDR_H | ||
15 | |||
16 | #define AT91_DDRSDRC_MR (AT91_DDRSDRC + 0x00) /* Mode Register */ | ||
17 | #define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */ | ||
18 | #define AT91_DDRSDRC_MODE_NORMAL 0 | ||
19 | #define AT91_DDRSDRC_MODE_NOP 1 | ||
20 | #define AT91_DDRSDRC_MODE_PRECHARGE 2 | ||
21 | #define AT91_DDRSDRC_MODE_LMR 3 | ||
22 | #define AT91_DDRSDRC_MODE_REFRESH 4 | ||
23 | #define AT91_DDRSDRC_MODE_EXT_LMR 5 | ||
24 | #define AT91_DDRSDRC_MODE_DEEP 6 | ||
25 | |||
26 | #define AT91_DDRSDRC_RTR (AT91_DDRSDRC + 0x04) /* Refresh Timer Register */ | ||
27 | #define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ | ||
28 | |||
29 | #define AT91_DDRSDRC_CR (AT91_DDRSDRC + 0x08) /* Configuration Register */ | ||
30 | #define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ | ||
31 | #define AT91_DDRSDRC_NC_SDR8 (0 << 0) | ||
32 | #define AT91_DDRSDRC_NC_SDR9 (1 << 0) | ||
33 | #define AT91_DDRSDRC_NC_SDR10 (2 << 0) | ||
34 | #define AT91_DDRSDRC_NC_SDR11 (3 << 0) | ||
35 | #define AT91_DDRSDRC_NC_DDR9 (0 << 0) | ||
36 | #define AT91_DDRSDRC_NC_DDR10 (1 << 0) | ||
37 | #define AT91_DDRSDRC_NC_DDR11 (2 << 0) | ||
38 | #define AT91_DDRSDRC_NC_DDR12 (3 << 0) | ||
39 | #define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */ | ||
40 | #define AT91_DDRSDRC_NR_11 (0 << 2) | ||
41 | #define AT91_DDRSDRC_NR_12 (1 << 2) | ||
42 | #define AT91_DDRSDRC_NR_13 (2 << 2) | ||
43 | #define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */ | ||
44 | #define AT91_DDRSDRC_CAS_2 (2 << 4) | ||
45 | #define AT91_DDRSDRC_CAS_3 (3 << 4) | ||
46 | #define AT91_DDRSDRC_CAS_25 (6 << 4) | ||
47 | #define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */ | ||
48 | #define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ | ||
49 | |||
50 | #define AT91_DDRSDRC_T0PR (AT91_DDRSDRC + 0x0C) /* Timing 0 Register */ | ||
51 | #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ | ||
52 | #define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ | ||
53 | #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ | ||
54 | #define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */ | ||
55 | #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ | ||
56 | #define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ | ||
57 | #define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */ | ||
58 | #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ | ||
59 | |||
60 | #define AT91_DDRSDRC_T1PR (AT91_DDRSDRC + 0x10) /* Timing 1 Register */ | ||
61 | #define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ | ||
62 | #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ | ||
63 | #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ | ||
64 | #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ | ||
65 | |||
66 | #define AT91_DDRSDRC_LPR (AT91_DDRSDRC + 0x18) /* Low Power Register */ | ||
67 | #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ | ||
68 | #define AT91_DDRSDRC_LPCB_DISABLE 0 | ||
69 | #define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 | ||
70 | #define AT91_DDRSDRC_LPCB_POWER_DOWN 2 | ||
71 | #define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 | ||
72 | #define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */ | ||
73 | #define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */ | ||
74 | #define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ | ||
75 | #define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */ | ||
76 | #define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ | ||
77 | #define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12) | ||
78 | #define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) | ||
79 | #define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) | ||
80 | |||
81 | #define AT91_DDRSDRC_MDR (AT91_DDRSDRC + 0x1C) /* Memory Device Register */ | ||
82 | #define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ | ||
83 | #define AT91_DDRSDRC_MD_SDR 0 | ||
84 | #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 | ||
85 | #define AT91_DDRSDRC_MD_DDR 2 | ||
86 | #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 | ||
87 | |||
88 | #define AT91_DDRSDRC_DLLR (AT91_DDRSDRC + 0x20) /* DLL Information Register */ | ||
89 | #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ | ||
90 | #define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ | ||
91 | #define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ | ||
92 | #define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */ | ||
93 | #define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */ | ||
94 | #define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */ | ||
95 | #define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ | ||
96 | #define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */ | ||
97 | #define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */ | ||
98 | |||
99 | |||
100 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91sam926x_mc.h b/include/asm-arm/arch-at91/at91sam9_sdramc.h index d82631c251f1..d3b8b3da6b4d 100644 --- a/include/asm-arm/arch-at91/at91sam926x_mc.h +++ b/include/asm-arm/arch-at91/at91sam9_sdramc.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * include/asm-arm/arch-at91/at91sam926x_mc.h | 2 | * include/asm-arm/arch-at91/at91sam9_sdramc.h |
3 | * | 3 | * |
4 | * Memory Controllers (SMC, SDRAMC) - System peripherals registers. | 4 | * SDRAM Controllers (SDRAMC) - System peripherals registers. |
5 | * Based on AT91SAM9261 datasheet revision D. | 5 | * Based on AT91SAM9261 datasheet revision D. |
6 | * | 6 | * |
7 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
@@ -10,8 +10,8 @@ | |||
10 | * (at your option) any later version. | 10 | * (at your option) any later version. |
11 | */ | 11 | */ |
12 | 12 | ||
13 | #ifndef AT91SAM926x_MC_H | 13 | #ifndef AT91SAM9_SDRAMC_H |
14 | #define AT91SAM926x_MC_H | 14 | #define AT91SAM9_SDRAMC_H |
15 | 15 | ||
16 | /* SDRAM Controller (SDRAMC) registers */ | 16 | /* SDRAM Controller (SDRAMC) registers */ |
17 | #define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ | 17 | #define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ |
@@ -62,7 +62,7 @@ | |||
62 | #define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 | 62 | #define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 |
63 | #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ | 63 | #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ |
64 | #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ | 64 | #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ |
65 | #define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */ | 65 | #define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */ |
66 | #define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ | 66 | #define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ |
67 | #define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) | 67 | #define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) |
68 | #define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) | 68 | #define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) |
@@ -80,62 +80,4 @@ | |||
80 | #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 | 80 | #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 |
81 | 81 | ||
82 | 82 | ||
83 | /* Static Memory Controller (SMC) registers */ | ||
84 | #define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ | ||
85 | #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ | ||
86 | #define AT91_SMC_NWESETUP_(x) ((x) << 0) | ||
87 | #define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ | ||
88 | #define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) | ||
89 | #define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ | ||
90 | #define AT91_SMC_NRDSETUP_(x) ((x) << 16) | ||
91 | #define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ | ||
92 | #define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) | ||
93 | |||
94 | #define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ | ||
95 | #define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ | ||
96 | #define AT91_SMC_NWEPULSE_(x) ((x) << 0) | ||
97 | #define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ | ||
98 | #define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) | ||
99 | #define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ | ||
100 | #define AT91_SMC_NRDPULSE_(x) ((x) << 16) | ||
101 | #define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ | ||
102 | #define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) | ||
103 | |||
104 | #define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ | ||
105 | #define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ | ||
106 | #define AT91_SMC_NWECYCLE_(x) ((x) << 0) | ||
107 | #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ | ||
108 | #define AT91_SMC_NRDCYCLE_(x) ((x) << 16) | ||
109 | |||
110 | #define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ | ||
111 | #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ | ||
112 | #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ | ||
113 | #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ | ||
114 | #define AT91_SMC_EXNWMODE_DISABLE (0 << 4) | ||
115 | #define AT91_SMC_EXNWMODE_FROZEN (2 << 4) | ||
116 | #define AT91_SMC_EXNWMODE_READY (3 << 4) | ||
117 | #define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ | ||
118 | #define AT91_SMC_BAT_SELECT (0 << 8) | ||
119 | #define AT91_SMC_BAT_WRITE (1 << 8) | ||
120 | #define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ | ||
121 | #define AT91_SMC_DBW_8 (0 << 12) | ||
122 | #define AT91_SMC_DBW_16 (1 << 12) | ||
123 | #define AT91_SMC_DBW_32 (2 << 12) | ||
124 | #define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ | ||
125 | #define AT91_SMC_TDF_(x) ((x) << 16) | ||
126 | #define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ | ||
127 | #define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ | ||
128 | #define AT91_SMC_PS (3 << 28) /* Page Size */ | ||
129 | #define AT91_SMC_PS_4 (0 << 28) | ||
130 | #define AT91_SMC_PS_8 (1 << 28) | ||
131 | #define AT91_SMC_PS_16 (2 << 28) | ||
132 | #define AT91_SMC_PS_32 (3 << 28) | ||
133 | |||
134 | #if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ | ||
135 | #define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ | ||
136 | #define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ | ||
137 | #define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ | ||
138 | #define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ | ||
139 | #endif | ||
140 | |||
141 | #endif | 83 | #endif |
diff --git a/include/asm-arm/arch-at91/at91sam9_smc.h b/include/asm-arm/arch-at91/at91sam9_smc.h new file mode 100644 index 000000000000..9e49eed31e50 --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9_smc.h | |||
@@ -0,0 +1,73 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-at91/at91sam9_smc.h | ||
3 | * | ||
4 | * Static Memory Controllers (SMC) - System peripherals registers. | ||
5 | * Based on AT91SAM9261 datasheet revision D. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | */ | ||
12 | |||
13 | #ifndef AT91SAM9_SMC_H | ||
14 | #define AT91SAM9_SMC_H | ||
15 | |||
16 | #define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ | ||
17 | #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ | ||
18 | #define AT91_SMC_NWESETUP_(x) ((x) << 0) | ||
19 | #define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ | ||
20 | #define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) | ||
21 | #define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ | ||
22 | #define AT91_SMC_NRDSETUP_(x) ((x) << 16) | ||
23 | #define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ | ||
24 | #define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) | ||
25 | |||
26 | #define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ | ||
27 | #define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ | ||
28 | #define AT91_SMC_NWEPULSE_(x) ((x) << 0) | ||
29 | #define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ | ||
30 | #define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) | ||
31 | #define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ | ||
32 | #define AT91_SMC_NRDPULSE_(x) ((x) << 16) | ||
33 | #define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ | ||
34 | #define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) | ||
35 | |||
36 | #define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ | ||
37 | #define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ | ||
38 | #define AT91_SMC_NWECYCLE_(x) ((x) << 0) | ||
39 | #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ | ||
40 | #define AT91_SMC_NRDCYCLE_(x) ((x) << 16) | ||
41 | |||
42 | #define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ | ||
43 | #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ | ||
44 | #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ | ||
45 | #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ | ||
46 | #define AT91_SMC_EXNWMODE_DISABLE (0 << 4) | ||
47 | #define AT91_SMC_EXNWMODE_FROZEN (2 << 4) | ||
48 | #define AT91_SMC_EXNWMODE_READY (3 << 4) | ||
49 | #define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ | ||
50 | #define AT91_SMC_BAT_SELECT (0 << 8) | ||
51 | #define AT91_SMC_BAT_WRITE (1 << 8) | ||
52 | #define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ | ||
53 | #define AT91_SMC_DBW_8 (0 << 12) | ||
54 | #define AT91_SMC_DBW_16 (1 << 12) | ||
55 | #define AT91_SMC_DBW_32 (2 << 12) | ||
56 | #define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ | ||
57 | #define AT91_SMC_TDF_(x) ((x) << 16) | ||
58 | #define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ | ||
59 | #define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ | ||
60 | #define AT91_SMC_PS (3 << 28) /* Page Size */ | ||
61 | #define AT91_SMC_PS_4 (0 << 28) | ||
62 | #define AT91_SMC_PS_8 (1 << 28) | ||
63 | #define AT91_SMC_PS_16 (2 << 28) | ||
64 | #define AT91_SMC_PS_32 (3 << 28) | ||
65 | |||
66 | #if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ | ||
67 | #define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ | ||
68 | #define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ | ||
69 | #define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ | ||
70 | #define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ | ||
71 | #endif | ||
72 | |||
73 | #endif | ||