[POWERPC] 83xx: Add the MPC8315E RDB dts

Add the dts for the MPC8315E Reference Development Board (RDB). The board is a mini-ITX reference board with 128M DDR2, 8M flash, 32M NAND, USB, PCI, gigabit ethernet, SATA, and serial. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
author: Kim Phillips <kim.phillips@freescale.com> 2008-01-24 21:46:06 -0500
committer: Kumar Gala <galak@kernel.crashing.org> 2008-01-28 09:33:01 -0500
commit: 64ee61bbf1983549b48e6d52fc6d98b31a4fa8fb (patch)
tree: 4f507b27c7a459cc6cf29d375417cbffa56d5b7a
parent: 846aace363a8cdaa2e7525f489165297bcf865b3 (diff)
1 files changed, 287 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts
new file mode 100644
index 000000000000..e157f2342ea0
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8315erdb.dts
@@ -0,0 +1,287 @@
+/*
+ * MPC8315E RDB Device Tree Source
+ *
+ * Copyright 2007 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+/dts-v1/;
+/ {
+        compatible = "fsl,mpc8315erdb";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        aliases {
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                pci0 = &pci0;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                PowerPC,8315@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        d-cache-line-size = <32>;
+                        i-cache-line-size = <32>;
+                        d-cache-size = <16384>;
+                        i-cache-size = <16384>;
+                        timebase-frequency = <0>;       // from bootloader
+                        bus-frequency = <0>;            // from bootloader
+                        clock-frequency = <0>;          // from bootloader
+                };
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x08000000>;  // 128MB at 0
+        };
+        localbus@e0005000 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
+                reg = <0xe0005000 0x1000>;
+                interrupts = <77 8>;
+                interrupt-parent = <&ipic>;
+                // CS0 and CS1 are swapped when
+                // booting from nand, but the
+                // addresses are the same.
+                ranges = <0 0 0xfe000000 0x00800000
+                          1 0 0xe0600000 0x00002000
+                          2 0 0xf0000000 0x00020000
+                          3 0 0xfa000000 0x00008000>;
+                flash@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0 0 0x800000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+                };
+                nand@1,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8315-fcm-nand",
+                                     "fsl,elbc-fcm-nand";
+                        reg = <1 0 0x2000>;
+                        u-boot@0 {
+                                reg = <0x0 0x100000>;
+                                read-only;
+                        };
+                        kernel@100000 {
+                                reg = <0x100000 0x300000>;
+                        };
+                        fs@400000 {
+                                reg = <0x400000 0x1c00000>;
+                        };
+                };
+        };
+        immr@e0000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "simple-bus";
+                ranges = <0 0xe0000000 0x00100000>;
+                reg = <0xe0000000 0x00000200>;
+                bus-frequency = <0>;
+                wdt@200 {
+                        device_type = "watchdog";
+                        compatible = "mpc83xx_wdt";
+                        reg = <0x200 0x100>;
+                };
+                i2c@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3000 0x100>;
+                        interrupts = <14 8>;
+                        interrupt-parent = < &ipic >;
+                        dfsrr;
+                        rtc@68 {
+                                device_type = "rtc";
+                                compatible = "dallas,ds1339";
+                                reg = <0x68>;
+                        };
+                };
+                spi@7000 {
+                        cell-index = <0>;
+                        compatible = "fsl,spi";
+                        reg = <0x7000 0x1000>;
+                        interrupts = <16 8>;
+                        interrupt-parent = < &ipic >;
+                        mode = "cpu";
+                };
+                usb@23000 {
+                        compatible = "fsl-usb2-dr";
+                        reg = <0x23000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupt-parent = < &ipic >;
+                        interrupts = <38 8>;
+                        phy_type = "utmi";
+                };
+                mdio@24520 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,gianfar-mdio";
+                        reg = <0x24520 0x20>;
+                        phy0: ethernet-phy@0 {
+                                interrupt-parent = < &ipic >;
+                                interrupts = <20 8>;
+                                reg = <0>;
+                                device_type = "ethernet-phy";
+                        };
+                        phy1: ethernet-phy@1 {
+                                interrupt-parent = < &ipic >;
+                                interrupts = <19 8>;
+                                reg = <1>;
+                                device_type = "ethernet-phy";
+                        };
+                };
+                enet0: ethernet@24000 {
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x24000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <32 8 33 8 34 8>;
+                        interrupt-parent = < &ipic >;
+                        phy-handle = < &phy0 >;
+                };
+                enet1: ethernet@25000 {
+                        cell-index = <1>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x25000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <35 8 36 8 37 8>;
+                        interrupt-parent = < &ipic >;
+                        phy-handle = < &phy1 >;
+                };
+                serial0: serial@4500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4500 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <9 8>;
+                        interrupt-parent = < &ipic >;
+                };
+                serial1: serial@4600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4600 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <10 8>;
+                        interrupt-parent = < &ipic >;
+                };
+                crypto@30000 {
+                        model = "SEC3";
+                        device_type = "crypto";
+                        compatible = "talitos";
+                        reg = <0x30000 0x10000>;
+                        interrupts = <11 8>;
+                        interrupt-parent = < &ipic >;
+                        /* Rev. 3.0 geometry */
+                        num-channels = <4>;
+                        channel-fifo-len = <24>;
+                        exec-units-mask = <0x000001fe>;
+                        descriptor-types-mask = <0x03ab0ebf>;
+                };
+                sata@18000 {
+                        compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
+                        reg = <0x18000 0x1000>;
+                        cell-index = <1>;
+                        interrupts = <44 8>;
+                        interrupt-parent = < &ipic >;
+                };
+                sata@19000 {
+                        compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
+                        reg = <0x19000 0x1000>;
+                        cell-index = <2>;
+                        interrupts = <45 8>;
+                        interrupt-parent = < &ipic >;
+                };
+                /* IPIC
+                 * interrupts cell = <intr #, sense>
+                 * sense values match linux IORESOURCE_IRQ_* defines:
+                 * sense == 8: Level, low assertion
+                 * sense == 2: Edge, high-to-low change
+                 */
+                ipic: interrupt-controller@700 {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x700 0x100>;
+                        device_type = "ipic";
+                };
+        };
+        pci0: pci@e0008500 {
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                                /* IDSEL 0x0E -mini PCI */
+                                 0x7000 0 0 1 &ipic 18 8
+                                 0x7000 0 0 2 &ipic 18 8
+                                 0x7000 0 0 3 &ipic 18 8
+                                 0x7000 0 0 4 &ipic 18 8
+                                /* IDSEL 0x0F -mini PCI */
+                                 0x7800 0 0 1 &ipic 17 8
+                                 0x7800 0 0 2 &ipic 17 8
+                                 0x7800 0 0 3 &ipic 17 8
+                                 0x7800 0 0 4 &ipic 17 8
+                                /* IDSEL 0x10 - PCI slot */
+                                 0x8000 0 0 1 &ipic 48 8
+                                 0x8000 0 0 2 &ipic 17 8
+                                 0x8000 0 0 3 &ipic 48 8
+                                 0x8000 0 0 4 &ipic 17 8>;
+                interrupt-parent = < &ipic >;
+                interrupts = <66 8>;
+                bus-range = <0 0>;
+                ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
+                          0x42000000 0 0x80000000 0x80000000 0 0x10000000
+                          0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
+                clock-frequency = <66666666>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xe0008500 0x100>;
+                compatible = "fsl,mpc8349-pci";
+                device_type = "pci";
+        };
+};
author	Kim Phillips <kim.phillips@freescale.com>	2008-01-24 21:46:06 -0500
committer	Kumar Gala <galak@kernel.crashing.org>	2008-01-28 09:33:01 -0500
commit	64ee61bbf1983549b48e6d52fc6d98b31a4fa8fb (patch)
tree	4f507b27c7a459cc6cf29d375417cbffa56d5b7a
parent	846aace363a8cdaa2e7525f489165297bcf865b3 (diff)

diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts new file mode 100644 index 000000000000..e157f2342ea0 --- /dev/null +++ b/arch/powerpc/boot/dts/mpc8315erdb.dts
@@ -0,0 +1,287 @@
	1	/*
	2	* MPC8315E RDB Device Tree Source
	3	*
	4	* Copyright 2007 Freescale Semiconductor Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
	12	/dts-v1/;
	13
	14	/ {
	15	compatible = "fsl,mpc8315erdb";
	16	#address-cells = <1>;
	17	#size-cells = <1>;
	18
	19	aliases {
	20	ethernet0 = &enet0;
	21	ethernet1 = &enet1;
	22	serial0 = &serial0;
	23	serial1 = &serial1;
	24	pci0 = &pci0;
	25	};
	26
	27	cpus {
	28	#address-cells = <1>;
	29	#size-cells = <0>;
	30
	31	PowerPC,8315@0 {
	32	device_type = "cpu";
	33	reg = <0>;
	34	d-cache-line-size = <32>;
	35	i-cache-line-size = <32>;
	36	d-cache-size = <16384>;
	37	i-cache-size = <16384>;
	38	timebase-frequency = <0>; // from bootloader
	39	bus-frequency = <0>; // from bootloader
	40	clock-frequency = <0>; // from bootloader
	41	};
	42	};
	43
	44	memory {
	45	device_type = "memory";
	46	reg = <0x00000000 0x08000000>; // 128MB at 0
	47	};
	48
	49	localbus@e0005000 {
	50	#address-cells = <2>;
	51	#size-cells = <1>;
	52	compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
	53	reg = <0xe0005000 0x1000>;
	54	interrupts = <77 8>;
	55	interrupt-parent = <&ipic>;
	56
	57	// CS0 and CS1 are swapped when
	58	// booting from nand, but the
	59	// addresses are the same.
	60	ranges = <0 0 0xfe000000 0x00800000
	61	1 0 0xe0600000 0x00002000
	62	2 0 0xf0000000 0x00020000
	63	3 0 0xfa000000 0x00008000>;
	64
	65	flash@0,0 {
	66	#address-cells = <1>;
	67	#size-cells = <1>;
	68	compatible = "cfi-flash";
	69	reg = <0 0 0x800000>;
	70	bank-width = <2>;
	71	device-width = <1>;
	72	};
	73
	74	nand@1,0 {
	75	#address-cells = <1>;
	76	#size-cells = <1>;
	77	compatible = "fsl,mpc8315-fcm-nand",
	78	"fsl,elbc-fcm-nand";
	79	reg = <1 0 0x2000>;
	80
	81	u-boot@0 {
	82	reg = <0x0 0x100000>;
	83	read-only;
	84	};
	85
	86	kernel@100000 {
	87	reg = <0x100000 0x300000>;
	88	};
	89	fs@400000 {
	90	reg = <0x400000 0x1c00000>;
	91	};
	92	};
	93	};
	94
	95	immr@e0000000 {
	96	#address-cells = <1>;
	97	#size-cells = <1>;
	98	device_type = "soc";
	99	compatible = "simple-bus";
	100	ranges = <0 0xe0000000 0x00100000>;
	101	reg = <0xe0000000 0x00000200>;
	102	bus-frequency = <0>;
	103
	104	wdt@200 {
	105	device_type = "watchdog";
	106	compatible = "mpc83xx_wdt";
	107	reg = <0x200 0x100>;
	108	};
	109
	110	i2c@3000 {
	111	#address-cells = <1>;
	112	#size-cells = <0>;
	113	cell-index = <0>;
	114	compatible = "fsl-i2c";
	115	reg = <0x3000 0x100>;
	116	interrupts = <14 8>;
	117	interrupt-parent = < &ipic >;
	118	dfsrr;
	119	rtc@68 {
	120	device_type = "rtc";
	121	compatible = "dallas,ds1339";
	122	reg = <0x68>;
	123	};
	124	};
	125
	126	spi@7000 {
	127	cell-index = <0>;
	128	compatible = "fsl,spi";
	129	reg = <0x7000 0x1000>;
	130	interrupts = <16 8>;
	131	interrupt-parent = < &ipic >;
	132	mode = "cpu";
	133	};
	134
	135	usb@23000 {
	136	compatible = "fsl-usb2-dr";
	137	reg = <0x23000 0x1000>;
	138	#address-cells = <1>;
	139	#size-cells = <0>;
	140	interrupt-parent = < &ipic >;
	141	interrupts = <38 8>;
	142	phy_type = "utmi";
	143	};
	144
	145	mdio@24520 {
	146	#address-cells = <1>;
	147	#size-cells = <0>;
	148	compatible = "fsl,gianfar-mdio";
	149	reg = <0x24520 0x20>;
	150	phy0: ethernet-phy@0 {
	151	interrupt-parent = < &ipic >;
	152	interrupts = <20 8>;
	153	reg = <0>;
	154	device_type = "ethernet-phy";
	155	};
	156	phy1: ethernet-phy@1 {
	157	interrupt-parent = < &ipic >;
	158	interrupts = <19 8>;
	159	reg = <1>;
	160	device_type = "ethernet-phy";
	161	};
	162	};
	163
	164	enet0: ethernet@24000 {
	165	cell-index = <0>;
	166	device_type = "network";
	167	model = "eTSEC";
	168	compatible = "gianfar";
	169	reg = <0x24000 0x1000>;
	170	local-mac-address = [ 00 00 00 00 00 00 ];
	171	interrupts = <32 8 33 8 34 8>;
	172	interrupt-parent = < &ipic >;
	173	phy-handle = < &phy0 >;
	174	};
	175
	176	enet1: ethernet@25000 {
	177	cell-index = <1>;
	178	device_type = "network";
	179	model = "eTSEC";
	180	compatible = "gianfar";
	181	reg = <0x25000 0x1000>;
	182	local-mac-address = [ 00 00 00 00 00 00 ];
	183	interrupts = <35 8 36 8 37 8>;
	184	interrupt-parent = < &ipic >;
	185	phy-handle = < &phy1 >;
	186	};
	187
	188	serial0: serial@4500 {
	189	cell-index = <0>;
	190	device_type = "serial";
	191	compatible = "ns16550";
	192	reg = <0x4500 0x100>;
	193	clock-frequency = <0>;
	194	interrupts = <9 8>;
	195	interrupt-parent = < &ipic >;
	196	};
	197
	198	serial1: serial@4600 {
	199	cell-index = <1>;
	200	device_type = "serial";
	201	compatible = "ns16550";
	202	reg = <0x4600 0x100>;
	203	clock-frequency = <0>;
	204	interrupts = <10 8>;
	205	interrupt-parent = < &ipic >;
	206	};
	207
	208	crypto@30000 {
	209	model = "SEC3";
	210	device_type = "crypto";
	211	compatible = "talitos";
	212	reg = <0x30000 0x10000>;
	213	interrupts = <11 8>;
	214	interrupt-parent = < &ipic >;
	215	/* Rev. 3.0 geometry */
	216	num-channels = <4>;
	217	channel-fifo-len = <24>;
	218	exec-units-mask = <0x000001fe>;
	219	descriptor-types-mask = <0x03ab0ebf>;
	220	};
	221
	222	sata@18000 {
	223	compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
	224	reg = <0x18000 0x1000>;
	225	cell-index = <1>;
	226	interrupts = <44 8>;
	227	interrupt-parent = < &ipic >;
	228	};
	229
	230	sata@19000 {
	231	compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
	232	reg = <0x19000 0x1000>;
	233	cell-index = <2>;
	234	interrupts = <45 8>;
	235	interrupt-parent = < &ipic >;
	236	};
	237
	238	/* IPIC
	239	* interrupts cell = <intr #, sense>
	240	* sense values match linux IORESOURCE_IRQ_* defines:
	241	* sense == 8: Level, low assertion
	242	* sense == 2: Edge, high-to-low change
	243	*/
	244	ipic: interrupt-controller@700 {
	245	interrupt-controller;
	246	#address-cells = <0>;
	247	#interrupt-cells = <2>;
	248	reg = <0x700 0x100>;
	249	device_type = "ipic";
	250	};
	251	};
	252
	253	pci0: pci@e0008500 {
	254	interrupt-map-mask = <0xf800 0 0 7>;
	255	interrupt-map = <
	256	/* IDSEL 0x0E -mini PCI */
	257	0x7000 0 0 1 &ipic 18 8
	258	0x7000 0 0 2 &ipic 18 8
	259	0x7000 0 0 3 &ipic 18 8
	260	0x7000 0 0 4 &ipic 18 8
	261
	262	/* IDSEL 0x0F -mini PCI */
	263	0x7800 0 0 1 &ipic 17 8
	264	0x7800 0 0 2 &ipic 17 8
	265	0x7800 0 0 3 &ipic 17 8
	266	0x7800 0 0 4 &ipic 17 8
	267
	268	/* IDSEL 0x10 - PCI slot */
	269	0x8000 0 0 1 &ipic 48 8
	270	0x8000 0 0 2 &ipic 17 8
	271	0x8000 0 0 3 &ipic 48 8
	272	0x8000 0 0 4 &ipic 17 8>;
	273	interrupt-parent = < &ipic >;
	274	interrupts = <66 8>;
	275	bus-range = <0 0>;
	276	ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
	277	0x42000000 0 0x80000000 0x80000000 0 0x10000000
	278	0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
	279	clock-frequency = <66666666>;
	280	#interrupt-cells = <1>;
	281	#size-cells = <2>;
	282	#address-cells = <3>;
	283	reg = <0xe0008500 0x100>;
	284	compatible = "fsl,mpc8349-pci";
	285	device_type = "pci";
	286	};
	287	};