diff options
author | Ben Dooks <ben-linux@fluff.org> | 2006-06-27 17:53:04 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-06-28 12:54:54 -0400 |
commit | 2b8b4913efa20f76718f524accf40e6d02a3bf0a (patch) | |
tree | 35f2df1ad0169182d8741a5744141c1a66314077 | |
parent | b8ccca4a57c91dfd81b0a50e16942699bb01600a (diff) |
[ARM] 3661/1: S3C2412: Fix compilation if CPU_S3C2410 only
Patch from Ben Dooks
If only the S3C2412 based machines are selected,
then the regs-dsc.h does not export the S3C2412_DSC
registers as it is wrapped in CONFIG_CPU_S3C2440.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r-- | include/asm-arm/arch-s3c2410/regs-dsc.h | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-dsc.h b/include/asm-arm/arch-s3c2410/regs-dsc.h index 84aca61cbaa3..a0a124875164 100644 --- a/include/asm-arm/arch-s3c2410/regs-dsc.h +++ b/include/asm-arm/arch-s3c2410/regs-dsc.h | |||
@@ -7,25 +7,23 @@ | |||
7 | * it under the terms of the GNU General Public License version 2 as | 7 | * it under the terms of the GNU General Public License version 2 as |
8 | * published by the Free Software Foundation. | 8 | * published by the Free Software Foundation. |
9 | * | 9 | * |
10 | * S3C2440 Signal Drive Strength Control | 10 | * S3C2440/S3C2412 Signal Drive Strength Control |
11 | * | ||
12 | * Changelog: | ||
13 | * 11-Aug-2004 BJD Created file | ||
14 | * 25-Aug-2004 BJD Added the _SELECT_* defs for using with functions | ||
15 | */ | 11 | */ |
16 | 12 | ||
17 | 13 | ||
18 | #ifndef __ASM_ARCH_REGS_DSC_H | 14 | #ifndef __ASM_ARCH_REGS_DSC_H |
19 | #define __ASM_ARCH_REGS_DSC_H "2440-dsc" | 15 | #define __ASM_ARCH_REGS_DSC_H "2440-dsc" |
20 | 16 | ||
21 | #ifdef CONFIG_CPU_S3C2440 | 17 | #if defined(CONFIG_CPU_S3C2412) |
18 | #define S3C2412_DSC0 S3C2410_GPIOREG(0xdc) | ||
19 | #define S3C2412_DSC1 S3C2410_GPIOREG(0xe0) | ||
20 | #endif | ||
21 | |||
22 | #if defined(CONFIG_CPU_S3C2440) | ||
22 | 23 | ||
23 | #define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) | 24 | #define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) |
24 | #define S3C2440_DSC1 S3C2410_GPIOREG(0xc8) | 25 | #define S3C2440_DSC1 S3C2410_GPIOREG(0xc8) |
25 | 26 | ||
26 | #define S3C2412_DSC0 S3C2410_GPIOREG(0xdc) | ||
27 | #define S3C2412_DSC1 S3C2410_GPIOREG(0xe0) | ||
28 | |||
29 | #define S3C2440_SELECT_DSC0 (0) | 27 | #define S3C2440_SELECT_DSC0 (0) |
30 | #define S3C2440_SELECT_DSC1 (1<<31) | 28 | #define S3C2440_SELECT_DSC1 (1<<31) |
31 | 29 | ||