diff options
author | Nicolas Pitre <nico@cam.org> | 2006-02-01 14:26:01 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-02-01 14:26:01 -0500 |
commit | 18afea04f1dfc5d52fd2579cd17adc3956acd4ad (patch) | |
tree | 45b56a2a6c16662bfd135637295798a9fba3ac69 | |
parent | 8a052e0bc25ff52f17b3dff150846ca9eb969162 (diff) |
[ARM] 3294/1: don't invalidate individual BTB entries on ARMv6
Patch from Nicolas Pitre
Doing so adds a much larger cost to the loop than the cost implied by
simply invalidating the whole BTB at once.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r-- | arch/arm/mm/cache-v6.S | 18 |
1 files changed, 6 insertions, 12 deletions
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index 72966d90e956..d921c1024ae0 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S | |||
@@ -92,22 +92,16 @@ ENTRY(v6_coherent_kern_range) | |||
92 | * - the Icache does not read data from the write buffer | 92 | * - the Icache does not read data from the write buffer |
93 | */ | 93 | */ |
94 | ENTRY(v6_coherent_user_range) | 94 | ENTRY(v6_coherent_user_range) |
95 | bic r0, r0, #CACHE_LINE_SIZE - 1 | 95 | |
96 | 1: | ||
97 | #ifdef HARVARD_CACHE | 96 | #ifdef HARVARD_CACHE |
98 | mcr p15, 0, r0, c7, c10, 1 @ clean D line | 97 | bic r0, r0, #CACHE_LINE_SIZE - 1 |
98 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D line | ||
99 | mcr p15, 0, r0, c7, c5, 1 @ invalidate I line | 99 | mcr p15, 0, r0, c7, c5, 1 @ invalidate I line |
100 | #endif | 100 | add r0, r0, #CACHE_LINE_SIZE |
101 | mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry | ||
102 | add r0, r0, #BTB_FLUSH_SIZE | ||
103 | mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry | ||
104 | add r0, r0, #BTB_FLUSH_SIZE | ||
105 | mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry | ||
106 | add r0, r0, #BTB_FLUSH_SIZE | ||
107 | mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry | ||
108 | add r0, r0, #BTB_FLUSH_SIZE | ||
109 | cmp r0, r1 | 101 | cmp r0, r1 |
110 | blo 1b | 102 | blo 1b |
103 | #endif | ||
104 | mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB | ||
111 | #ifdef HARVARD_CACHE | 105 | #ifdef HARVARD_CACHE |
112 | mov r0, #0 | 106 | mov r0, #0 |
113 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | 107 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer |