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authorPaul Walmsley <paul@pwsan.com>2009-01-28 14:08:38 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-02-08 12:50:34 -0500
commitb32450409847dddf060a468707212d3493df4f63 (patch)
treeadb1a04af8998d9c2d492665614d37d698889f56
parentc1bd7aaf678a7e35086520e284d5b44bc69b6599 (diff)
[ARM] OMAP3 clock: remove unnecessary dpll_data dereferences
Remove some clutter from omap2_dpll_round_rate(). linux-omap source commit is 4625dceb8583c02a6d67ededc9f6a8347b6b8cb7. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/mach-omap2/clock.c23
1 files changed, 13 insertions, 10 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 886f73f3933a..2f0eaaad4819 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -877,19 +877,22 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
877 int m, n, r, e, scaled_max_m; 877 int m, n, r, e, scaled_max_m;
878 unsigned long scaled_rt_rp, new_rate; 878 unsigned long scaled_rt_rp, new_rate;
879 int min_e = -1, min_e_m = -1, min_e_n = -1; 879 int min_e = -1, min_e_m = -1, min_e_n = -1;
880 struct dpll_data *dd;
880 881
881 if (!clk || !clk->dpll_data) 882 if (!clk || !clk->dpll_data)
882 return ~0; 883 return ~0;
883 884
885 dd = clk->dpll_data;
886
884 pr_debug("clock: starting DPLL round_rate for clock %s, target rate " 887 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
885 "%ld\n", clk->name, target_rate); 888 "%ld\n", clk->name, target_rate);
886 889
887 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR); 890 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
888 scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR; 891 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
889 892
890 clk->dpll_data->last_rounded_rate = 0; 893 dd->last_rounded_rate = 0;
891 894
892 for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) { 895 for (n = dd->max_divider; n >= DPLL_MIN_DIVIDER; n--) {
893 896
894 /* Compute the scaled DPLL multiplier, based on the divider */ 897 /* Compute the scaled DPLL multiplier, based on the divider */
895 m = scaled_rt_rp * n; 898 m = scaled_rt_rp * n;
@@ -909,7 +912,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
909 "(new_rate = %ld)\n", n, m, e, new_rate); 912 "(new_rate = %ld)\n", n, m, e, new_rate);
910 913
911 if (min_e == -1 || 914 if (min_e == -1 ||
912 min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) { 915 min_e >= (int)(abs(e) - dd->rate_tolerance)) {
913 min_e = e; 916 min_e = e;
914 min_e_m = m; 917 min_e_m = m;
915 min_e_n = n; 918 min_e_n = n;
@@ -932,17 +935,17 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
932 return ~0; 935 return ~0;
933 } 936 }
934 937
935 clk->dpll_data->last_rounded_m = min_e_m; 938 dd->last_rounded_m = min_e_m;
936 clk->dpll_data->last_rounded_n = min_e_n; 939 dd->last_rounded_n = min_e_n;
937 clk->dpll_data->last_rounded_rate = 940 dd->last_rounded_rate = _dpll_compute_new_rate(clk->parent->rate,
938 _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n); 941 min_e_m, min_e_n);
939 942
940 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", 943 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
941 min_e, min_e_m, min_e_n); 944 min_e, min_e_m, min_e_n);
942 pr_debug("clock: final rate: %ld (target rate: %ld)\n", 945 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
943 clk->dpll_data->last_rounded_rate, target_rate); 946 dd->last_rounded_rate, target_rate);
944 947
945 return clk->dpll_data->last_rounded_rate; 948 return dd->last_rounded_rate;
946} 949}
947 950
948/*------------------------------------------------------------------------- 951/*-------------------------------------------------------------------------