aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorDaniel Drake <dsd@gentoo.org>2006-12-11 20:25:13 -0500
committerJeff Garzik <jeff@garzik.org>2007-02-05 16:58:41 -0500
commit34c4491264ceafa5c81f74a5f24f49e8e24f12f2 (patch)
treecb7f36244b4a3d18a921f201d9a6ba1a8d4b61b2
parent7e721579479350b15b2bf1e232cd372c704aff7b (diff)
[PATCH] zd1211rw: Generic HMAC initialization
Many of the registers written during ZD1211 HMAC initialization are duplicated exactly for ZD1211B. Move the identical ones into a generic part, and write the hardware-specific ones separately. Signed-off-by: Daniel Drake <dsd@gentoo.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r--drivers/net/wireless/zd1211rw/zd_chip.c67
1 files changed, 18 insertions, 49 deletions
diff --git a/drivers/net/wireless/zd1211rw/zd_chip.c b/drivers/net/wireless/zd1211rw/zd_chip.c
index 78ea72fb8f0c..cc5151683fa1 100644
--- a/drivers/net/wireless/zd1211rw/zd_chip.c
+++ b/drivers/net/wireless/zd1211rw/zd_chip.c
@@ -798,47 +798,18 @@ static int hw_reset_phy(struct zd_chip *chip)
798static int zd1211_hw_init_hmac(struct zd_chip *chip) 798static int zd1211_hw_init_hmac(struct zd_chip *chip)
799{ 799{
800 static const struct zd_ioreq32 ioreqs[] = { 800 static const struct zd_ioreq32 ioreqs[] = {
801 { CR_ACK_TIMEOUT_EXT, 0x20 },
802 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
803 { CR_ZD1211_RETRY_MAX, 0x2 }, 801 { CR_ZD1211_RETRY_MAX, 0x2 },
804 { CR_SNIFFER_ON, 0 },
805 { CR_RX_FILTER, STA_RX_FILTER },
806 { CR_GROUP_HASH_P1, 0x00 },
807 { CR_GROUP_HASH_P2, 0x80000000 },
808 { CR_REG1, 0xa4 },
809 { CR_ADDA_PWR_DWN, 0x7f },
810 { CR_BCN_PLCP_CFG, 0x00f00401 },
811 { CR_PHY_DELAY, 0x00 },
812 { CR_ACK_TIMEOUT_EXT, 0x80 },
813 { CR_ADDA_PWR_DWN, 0x00 },
814 { CR_ACK_TIME_80211, 0x100 },
815 { CR_RX_PE_DELAY, 0x70 },
816 { CR_PS_CTRL, 0x10000000 },
817 { CR_RTS_CTS_RATE, 0x02030203 },
818 { CR_RX_THRESHOLD, 0x000c0640 }, 802 { CR_RX_THRESHOLD, 0x000c0640 },
819 { CR_AFTER_PNP, 0x1 },
820 { CR_WEP_PROTECT, 0x114 },
821 }; 803 };
822 804
823 int r;
824
825 dev_dbg_f(zd_chip_dev(chip), "\n"); 805 dev_dbg_f(zd_chip_dev(chip), "\n");
826 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 806 ZD_ASSERT(mutex_is_locked(&chip->mutex));
827 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 807 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
828#ifdef DEBUG
829 if (r) {
830 dev_err(zd_chip_dev(chip),
831 "error in zd_iowrite32a_locked. Error number %d\n", r);
832 }
833#endif /* DEBUG */
834 return r;
835} 808}
836 809
837static int zd1211b_hw_init_hmac(struct zd_chip *chip) 810static int zd1211b_hw_init_hmac(struct zd_chip *chip)
838{ 811{
839 static const struct zd_ioreq32 ioreqs[] = { 812 static const struct zd_ioreq32 ioreqs[] = {
840 { CR_ACK_TIMEOUT_EXT, 0x20 },
841 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
842 { CR_ZD1211B_RETRY_MAX, 0x02020202 }, 813 { CR_ZD1211B_RETRY_MAX, 0x02020202 },
843 { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f }, 814 { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f },
844 { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f }, 815 { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f },
@@ -847,6 +818,20 @@ static int zd1211b_hw_init_hmac(struct zd_chip *chip)
847 { CR_ZD1211B_AIFS_CTL1, 0x00280028 }, 818 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
848 { CR_ZD1211B_AIFS_CTL2, 0x008C003C }, 819 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
849 { CR_ZD1211B_TXOP, 0x01800824 }, 820 { CR_ZD1211B_TXOP, 0x01800824 },
821 { CR_RX_THRESHOLD, 0x000c0eff, },
822 };
823
824 dev_dbg_f(zd_chip_dev(chip), "\n");
825 ZD_ASSERT(mutex_is_locked(&chip->mutex));
826 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
827}
828
829static int hw_init_hmac(struct zd_chip *chip)
830{
831 int r;
832 static const struct zd_ioreq32 ioreqs[] = {
833 { CR_ACK_TIMEOUT_EXT, 0x20 },
834 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
850 { CR_SNIFFER_ON, 0 }, 835 { CR_SNIFFER_ON, 0 },
851 { CR_RX_FILTER, STA_RX_FILTER }, 836 { CR_RX_FILTER, STA_RX_FILTER },
852 { CR_GROUP_HASH_P1, 0x00 }, 837 { CR_GROUP_HASH_P1, 0x00 },
@@ -861,25 +846,16 @@ static int zd1211b_hw_init_hmac(struct zd_chip *chip)
861 { CR_RX_PE_DELAY, 0x70 }, 846 { CR_RX_PE_DELAY, 0x70 },
862 { CR_PS_CTRL, 0x10000000 }, 847 { CR_PS_CTRL, 0x10000000 },
863 { CR_RTS_CTS_RATE, 0x02030203 }, 848 { CR_RTS_CTS_RATE, 0x02030203 },
864 { CR_RX_THRESHOLD, 0x000c0eff, },
865 { CR_AFTER_PNP, 0x1 }, 849 { CR_AFTER_PNP, 0x1 },
866 { CR_WEP_PROTECT, 0x114 }, 850 { CR_WEP_PROTECT, 0x114 },
851 { CR_IFS_VALUE, IFS_VALUE_DEFAULT },
867 }; 852 };
868 853
869 int r;
870
871 dev_dbg_f(zd_chip_dev(chip), "\n");
872 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 854 ZD_ASSERT(mutex_is_locked(&chip->mutex));
873 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); 855 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
874 if (r) { 856 if (r)
875 dev_dbg_f(zd_chip_dev(chip), 857 return r;
876 "error in zd_iowrite32a_locked. Error number %d\n", r);
877 }
878 return r;
879}
880 858
881static int hw_init_hmac(struct zd_chip *chip)
882{
883 return chip->is_zd1211b ? 859 return chip->is_zd1211b ?
884 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip); 860 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
885} 861}
@@ -974,13 +950,6 @@ static int hw_init(struct zd_chip *chip)
974 if (r) 950 if (r)
975 return r; 951 return r;
976 952
977 /* Although the vendor driver defaults to a different value during
978 * init, it overwrites the IFS value with the following every time
979 * the channel changes. We should aim to be more intelligent... */
980 r = zd_iowrite32_locked(chip, IFS_VALUE_DEFAULT, CR_IFS_VALUE);
981 if (r)
982 return r;
983
984 return set_beacon_interval(chip, 100); 953 return set_beacon_interval(chip, 100);
985} 954}
986 955