x86: add MSR_IA32_MISC_ENABLE bits to <asm/msr-index.h>

Impact: None (new bit definitions currently unused)

Add bit definitions for the MSR_IA32_MISC_ENABLE MSRs to
<asm/msr-index.h>.

Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>

1 files changed, 29 insertions, 0 deletions

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index cb58643947b9..358acc59ae04 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -202,6 +202,35 @@
 #define MSR_IA32_THERM_STATUS           0x0000019c
 #define MSR_IA32_MISC_ENABLE            0x000001a0
 
+/* MISC_ENABLE bits: architectural */
+#define MSR_IA32_MISC_ENABLE_FAST_STRING        (1ULL << 0)
+#define MSR_IA32_MISC_ENABLE_TCC                (1ULL << 1)
+#define MSR_IA32_MISC_ENABLE_EMON               (1ULL << 7)
+#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL        (1ULL << 11)
+#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL       (1ULL << 12)
+#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16)
+#define MSR_IA32_MISC_ENABLE_MWAIT              (1ULL << 18)
+#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID        (1ULL << 22)
+#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE       (1ULL << 23)
+#define MSR_IA32_MISC_ENABLE_XD_DISABLE         (1ULL << 34)
+
+/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
+#define MSR_IA32_MISC_ENABLE_X87_COMPAT         (1ULL << 2)
+#define MSR_IA32_MISC_ENABLE_TM1                (1ULL << 3)
+#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4)
+#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE    (1ULL << 6)
+#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK      (1ULL << 8)
+#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE   (1ULL << 9)
+#define MSR_IA32_MISC_ENABLE_FERR               (1ULL << 10)
+#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX     (1ULL << 10)
+#define MSR_IA32_MISC_ENABLE_TM2                (1ULL << 13)
+#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE   (1ULL << 19)
+#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK     (1ULL << 20)
+#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT        (1ULL << 24)
+#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE   (1ULL << 37)
+#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE      (1ULL << 38)
+#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE    (1ULL << 39)
+
 /* Intel Model 6 */
 #define MSR_P6_EVNTSEL0                 0x00000186
 #define MSR_P6_EVNTSEL1                 0x00000187