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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2008-12-18 14:13:24 -0500
committerPaul Mackerras <paulus@samba.org>2008-12-20 22:21:15 -0500
commit5e696617c425eb97bd943d781f3941fb1e8f0e5b (patch)
tree82138fbda2e28fbe8d0e5821f218cb160230ce27
parent6d2170be4561293a6aa821c773687bd3f18e8206 (diff)
powerpc/mm: Split mmu_context handling
This splits the mmu_context handling between 32-bit hash based processors, 64-bit hash based processors and everybody else. This is preliminary work for adding SMP support for BookE processors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat
-rw-r--r--arch/powerpc/include/asm/mmu_context.h260
-rw-r--r--arch/powerpc/kernel/asm-offsets.c1
-rw-r--r--arch/powerpc/kernel/head_32.S12
-rw-r--r--arch/powerpc/kernel/ppc_ksyms.c3
-rw-r--r--arch/powerpc/kernel/swsusp.c2
-rw-r--r--arch/powerpc/mm/Makefile7
-rw-r--r--arch/powerpc/mm/mmu_context_32.c84
-rw-r--r--arch/powerpc/mm/mmu_context_hash32.c103
-rw-r--r--arch/powerpc/mm/mmu_context_hash64.c (renamed from arch/powerpc/mm/mmu_context_64.c)8
-rw-r--r--arch/powerpc/mm/mmu_context_nohash.c162
-rw-r--r--arch/powerpc/platforms/Kconfig.cputype10
-rw-r--r--arch/powerpc/platforms/powermac/cpufreq_32.c2
-rw-r--r--drivers/macintosh/via-pmu.c4
13 files changed, 337 insertions, 321 deletions
diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h
index b570209b71a8..ab4f19263c42 100644
--- a/arch/powerpc/include/asm/mmu_context.h
+++ b/arch/powerpc/include/asm/mmu_context.h
@@ -2,240 +2,26 @@
2#define __ASM_POWERPC_MMU_CONTEXT_H 2#define __ASM_POWERPC_MMU_CONTEXT_H
3#ifdef __KERNEL__ 3#ifdef __KERNEL__
4 4
5#include <linux/kernel.h>
6#include <linux/mm.h>
7#include <linux/sched.h>
8#include <linux/spinlock.h>
5#include <asm/mmu.h> 9#include <asm/mmu.h>
6#include <asm/cputable.h> 10#include <asm/cputable.h>
7#include <asm-generic/mm_hooks.h> 11#include <asm-generic/mm_hooks.h>
8 12#include <asm/cputhreads.h>
9#ifndef CONFIG_PPC64
10#include <asm/atomic.h>
11#include <linux/bitops.h>
12
13/*
14 * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs
15 * (virtual segment identifiers) for each context. Although the
16 * hardware supports 24-bit VSIDs, and thus >1 million contexts,
17 * we only use 32,768 of them. That is ample, since there can be
18 * at most around 30,000 tasks in the system anyway, and it means
19 * that we can use a bitmap to indicate which contexts are in use.
20 * Using a bitmap means that we entirely avoid all of the problems
21 * that we used to have when the context number overflowed,
22 * particularly on SMP systems.
23 * -- paulus.
24 */
25
26/*
27 * This function defines the mapping from contexts to VSIDs (virtual
28 * segment IDs). We use a skew on both the context and the high 4 bits
29 * of the 32-bit virtual address (the "effective segment ID") in order
30 * to spread out the entries in the MMU hash table. Note, if this
31 * function is changed then arch/ppc/mm/hashtable.S will have to be
32 * changed to correspond.
33 */
34#define CTX_TO_VSID(ctx, va) (((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \
35 & 0xffffff)
36
37/*
38 The MPC8xx has only 16 contexts. We rotate through them on each
39 task switch. A better way would be to keep track of tasks that
40 own contexts, and implement an LRU usage. That way very active
41 tasks don't always have to pay the TLB reload overhead. The
42 kernel pages are mapped shared, so the kernel can run on behalf
43 of any task that makes a kernel entry. Shared does not mean they
44 are not protected, just that the ASID comparison is not performed.
45 -- Dan
46
47 The IBM4xx has 256 contexts, so we can just rotate through these
48 as a way of "switching" contexts. If the TID of the TLB is zero,
49 the PID/TID comparison is disabled, so we can use a TID of zero
50 to represent all kernel pages as shared among all contexts.
51 -- Dan
52 */
53
54static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
55{
56}
57
58#ifdef CONFIG_8xx
59#define NO_CONTEXT 16
60#define LAST_CONTEXT 15
61#define FIRST_CONTEXT 0
62
63#elif defined(CONFIG_4xx)
64#define NO_CONTEXT 256
65#define LAST_CONTEXT 255
66#define FIRST_CONTEXT 1
67
68#elif defined(CONFIG_E200) || defined(CONFIG_E500)
69#define NO_CONTEXT 256
70#define LAST_CONTEXT 255
71#define FIRST_CONTEXT 1
72
73#else
74
75/* PPC 6xx, 7xx CPUs */
76#define NO_CONTEXT ((unsigned long) -1)
77#define LAST_CONTEXT 32767
78#define FIRST_CONTEXT 1
79#endif
80
81/*
82 * Set the current MMU context.
83 * On 32-bit PowerPCs (other than the 8xx embedded chips), this is done by
84 * loading up the segment registers for the user part of the address space.
85 *
86 * Since the PGD is immediately available, it is much faster to simply
87 * pass this along as a second parameter, which is required for 8xx and
88 * can be used for debugging on all processors (if you happen to have
89 * an Abatron).
90 */
91extern void set_context(unsigned long contextid, pgd_t *pgd);
92
93/*
94 * Bitmap of contexts in use.
95 * The size of this bitmap is LAST_CONTEXT + 1 bits.
96 */
97extern unsigned long context_map[];
98
99/*
100 * This caches the next context number that we expect to be free.
101 * Its use is an optimization only, we can't rely on this context
102 * number to be free, but it usually will be.
103 */
104extern unsigned long next_mmu_context;
105
106/*
107 * If we don't have sufficient contexts to give one to every task
108 * that could be in the system, we need to be able to steal contexts.
109 * These variables support that.
110 */
111#if LAST_CONTEXT < 30000
112#define FEW_CONTEXTS 1
113extern atomic_t nr_free_contexts;
114extern struct mm_struct *context_mm[LAST_CONTEXT+1];
115extern void steal_context(void);
116#endif
117
118/*
119 * Get a new mmu context for the address space described by `mm'.
120 */
121static inline void get_mmu_context(struct mm_struct *mm)
122{
123 unsigned long ctx;
124
125 if (mm->context.id != NO_CONTEXT)
126 return;
127#ifdef FEW_CONTEXTS
128 while (atomic_dec_if_positive(&nr_free_contexts) < 0)
129 steal_context();
130#endif
131 ctx = next_mmu_context;
132 while (test_and_set_bit(ctx, context_map)) {
133 ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
134 if (ctx > LAST_CONTEXT)
135 ctx = 0;
136 }
137 next_mmu_context = (ctx + 1) & LAST_CONTEXT;
138 mm->context.id = ctx;
139#ifdef FEW_CONTEXTS
140 context_mm[ctx] = mm;
141#endif
142}
143 13
144/* 14/*
145 * Set up the context for a new address space. 15 * Most if the context management is out of line
146 */ 16 */
147static inline int init_new_context(struct task_struct *t, struct mm_struct *mm)
148{
149 mm->context.id = NO_CONTEXT;
150 return 0;
151}
152
153/*
154 * We're finished using the context for an address space.
155 */
156static inline void destroy_context(struct mm_struct *mm)
157{
158 preempt_disable();
159 if (mm->context.id != NO_CONTEXT) {
160 clear_bit(mm->context.id, context_map);
161 mm->context.id = NO_CONTEXT;
162#ifdef FEW_CONTEXTS
163 atomic_inc(&nr_free_contexts);
164#endif
165 }
166 preempt_enable();
167}
168
169static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
170 struct task_struct *tsk)
171{
172#ifdef CONFIG_ALTIVEC
173 if (cpu_has_feature(CPU_FTR_ALTIVEC))
174 asm volatile ("dssall;\n"
175#ifndef CONFIG_POWER4
176 "sync;\n" /* G4 needs a sync here, G5 apparently not */
177#endif
178 : : );
179#endif /* CONFIG_ALTIVEC */
180
181 tsk->thread.pgdir = next->pgd;
182
183 if (!cpu_isset(smp_processor_id(), next->cpu_vm_mask))
184 cpu_set(smp_processor_id(), next->cpu_vm_mask);
185
186 /* No need to flush userspace segments if the mm doesnt change */
187 if (prev == next)
188 return;
189
190 /* Setup new userspace context */
191 get_mmu_context(next);
192 set_context(next->context.id, next->pgd);
193}
194
195#define deactivate_mm(tsk,mm) do { } while (0)
196
197/*
198 * After we have set current->mm to a new value, this activates
199 * the context for the new mm so we see the new mappings.
200 */
201#define activate_mm(active_mm, mm) switch_mm(active_mm, mm, current)
202
203extern void mmu_context_init(void); 17extern void mmu_context_init(void);
204
205
206#else
207
208#include <linux/kernel.h>
209#include <linux/mm.h>
210#include <linux/sched.h>
211
212/*
213 * Copyright (C) 2001 PPC 64 Team, IBM Corp
214 *
215 * This program is free software; you can redistribute it and/or
216 * modify it under the terms of the GNU General Public License
217 * as published by the Free Software Foundation; either version
218 * 2 of the License, or (at your option) any later version.
219 */
220
221static inline void enter_lazy_tlb(struct mm_struct *mm,
222 struct task_struct *tsk)
223{
224}
225
226/*
227 * The proto-VSID space has 2^35 - 1 segments available for user mappings.
228 * Each segment contains 2^28 bytes. Each context maps 2^44 bytes,
229 * so we can support 2^19-1 contexts (19 == 35 + 28 - 44).
230 */
231#define NO_CONTEXT 0
232#define MAX_CONTEXT ((1UL << 19) - 1)
233
234extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm); 18extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
235extern void destroy_context(struct mm_struct *mm); 19extern void destroy_context(struct mm_struct *mm);
236 20
21extern void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
237extern void switch_stab(struct task_struct *tsk, struct mm_struct *mm); 22extern void switch_stab(struct task_struct *tsk, struct mm_struct *mm);
238extern void switch_slb(struct task_struct *tsk, struct mm_struct *mm); 23extern void switch_slb(struct task_struct *tsk, struct mm_struct *mm);
24extern void set_context(unsigned long id, pgd_t *pgd);
239 25
240/* 26/*
241 * switch_mm is the entry point called from the architecture independent 27 * switch_mm is the entry point called from the architecture independent
@@ -244,22 +30,39 @@ extern void switch_slb(struct task_struct *tsk, struct mm_struct *mm);
244static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 30static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
245 struct task_struct *tsk) 31 struct task_struct *tsk)
246{ 32{
247 if (!cpu_isset(smp_processor_id(), next->cpu_vm_mask)) 33 /* Mark this context has been used on the new CPU */
248 cpu_set(smp_processor_id(), next->cpu_vm_mask); 34 cpu_set(smp_processor_id(), next->cpu_vm_mask);
35
36 /* 32-bit keeps track of the current PGDIR in the thread struct */
37#ifdef CONFIG_PPC32
38 tsk->thread.pgdir = next->pgd;
39#endif /* CONFIG_PPC32 */
249 40
250 /* No need to flush userspace segments if the mm doesnt change */ 41 /* Nothing else to do if we aren't actually switching */
251 if (prev == next) 42 if (prev == next)
252 return; 43 return;
253 44
45 /* We must stop all altivec streams before changing the HW
46 * context
47 */
254#ifdef CONFIG_ALTIVEC 48#ifdef CONFIG_ALTIVEC
255 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 49 if (cpu_has_feature(CPU_FTR_ALTIVEC))
256 asm volatile ("dssall"); 50 asm volatile ("dssall");
257#endif /* CONFIG_ALTIVEC */ 51#endif /* CONFIG_ALTIVEC */
258 52
53 /* The actual HW switching method differs between the various
54 * sub architectures.
55 */
56#ifdef CONFIG_PPC_STD_MMU_64
259 if (cpu_has_feature(CPU_FTR_SLB)) 57 if (cpu_has_feature(CPU_FTR_SLB))
260 switch_slb(tsk, next); 58 switch_slb(tsk, next);
261 else 59 else
262 switch_stab(tsk, next); 60 switch_stab(tsk, next);
61#else
62 /* Out of line for now */
63 switch_mmu_context(prev, next);
64#endif
65
263} 66}
264 67
265#define deactivate_mm(tsk,mm) do { } while (0) 68#define deactivate_mm(tsk,mm) do { } while (0)
@@ -277,6 +80,11 @@ static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next)
277 local_irq_restore(flags); 80 local_irq_restore(flags);
278} 81}
279 82
280#endif /* CONFIG_PPC64 */ 83/* We don't currently use enter_lazy_tlb() for anything */
84static inline void enter_lazy_tlb(struct mm_struct *mm,
85 struct task_struct *tsk)
86{
87}
88
281#endif /* __KERNEL__ */ 89#endif /* __KERNEL__ */
282#endif /* __ASM_POWERPC_MMU_CONTEXT_H */ 90#endif /* __ASM_POWERPC_MMU_CONTEXT_H */
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 050abfd5c17c..c05ab1d3e620 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -60,6 +60,7 @@ int main(void)
60{ 60{
61 DEFINE(THREAD, offsetof(struct task_struct, thread)); 61 DEFINE(THREAD, offsetof(struct task_struct, thread));
62 DEFINE(MM, offsetof(struct task_struct, mm)); 62 DEFINE(MM, offsetof(struct task_struct, mm));
63 DEFINE(MMCONTEXTID, offsetof(struct mm_struct, context.id));
63#ifdef CONFIG_PPC64 64#ifdef CONFIG_PPC64
64 DEFINE(AUDITCONTEXT, offsetof(struct task_struct, audit_context)); 65 DEFINE(AUDITCONTEXT, offsetof(struct task_struct, audit_context));
65#else 66#else
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 0c326823c6d4..be9f9e5470e8 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -31,6 +31,7 @@
31#include <asm/ppc_asm.h> 31#include <asm/ppc_asm.h>
32#include <asm/asm-offsets.h> 32#include <asm/asm-offsets.h>
33#include <asm/ptrace.h> 33#include <asm/ptrace.h>
34#include <asm/bug.h>
34 35
35/* 601 only have IBAT; cr0.eq is set on 601 when using this macro */ 36/* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
36#define LOAD_BAT(n, reg, RA, RB) \ 37#define LOAD_BAT(n, reg, RA, RB) \
@@ -1070,9 +1071,14 @@ start_here:
1070 RFI 1071 RFI
1071 1072
1072/* 1073/*
1074 * void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
1075 *
1073 * Set up the segment registers for a new context. 1076 * Set up the segment registers for a new context.
1074 */ 1077 */
1075_ENTRY(set_context) 1078_ENTRY(switch_mmu_context)
1079 lwz r3,MMCONTEXTID(r4)
1080 cmpwi cr0,r3,0
1081 blt- 4f
1076 mulli r3,r3,897 /* multiply context by skew factor */ 1082 mulli r3,r3,897 /* multiply context by skew factor */
1077 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */ 1083 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1078 addis r3,r3,0x6000 /* Set Ks, Ku bits */ 1084 addis r3,r3,0x6000 /* Set Ks, Ku bits */
@@ -1083,6 +1089,7 @@ _ENTRY(set_context)
1083 /* Context switch the PTE pointer for the Abatron BDI2000. 1089 /* Context switch the PTE pointer for the Abatron BDI2000.
1084 * The PGDIR is passed as second argument. 1090 * The PGDIR is passed as second argument.
1085 */ 1091 */
1092 lwz r4,MM_PGD(r4)
1086 lis r5, KERNELBASE@h 1093 lis r5, KERNELBASE@h
1087 lwz r5, 0xf0(r5) 1094 lwz r5, 0xf0(r5)
1088 stw r4, 0x4(r5) 1095 stw r4, 0x4(r5)
@@ -1098,6 +1105,9 @@ _ENTRY(set_context)
1098 sync 1105 sync
1099 isync 1106 isync
1100 blr 1107 blr
11084: trap
1109 EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0
1110 blr
1101 1111
1102/* 1112/*
1103 * An undocumented "feature" of 604e requires that the v bit 1113 * An undocumented "feature" of 604e requires that the v bit
diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c
index 260089dccfb0..341b3d3048e0 100644
--- a/arch/powerpc/kernel/ppc_ksyms.c
+++ b/arch/powerpc/kernel/ppc_ksyms.c
@@ -174,8 +174,7 @@ EXPORT_SYMBOL(cacheable_memcpy);
174#endif 174#endif
175 175
176#ifdef CONFIG_PPC32 176#ifdef CONFIG_PPC32
177EXPORT_SYMBOL(next_mmu_context); 177EXPORT_SYMBOL(switch_mmu_context);
178EXPORT_SYMBOL(set_context);
179#endif 178#endif
180 179
181#ifdef CONFIG_PPC_STD_MMU_32 180#ifdef CONFIG_PPC_STD_MMU_32
diff --git a/arch/powerpc/kernel/swsusp.c b/arch/powerpc/kernel/swsusp.c
index 77b7b34b5955..560c96119501 100644
--- a/arch/powerpc/kernel/swsusp.c
+++ b/arch/powerpc/kernel/swsusp.c
@@ -34,6 +34,6 @@ void save_processor_state(void)
34void restore_processor_state(void) 34void restore_processor_state(void)
35{ 35{
36#ifdef CONFIG_PPC32 36#ifdef CONFIG_PPC32
37 set_context(current->active_mm->context.id, current->active_mm->pgd); 37 switch_mmu_context(NULL, current->active_mm);
38#endif 38#endif
39} 39}
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index 148de35c9eef..923bd3fa7d64 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -8,15 +8,16 @@ endif
8 8
9obj-y := fault.o mem.o pgtable.o \ 9obj-y := fault.o mem.o pgtable.o \
10 init_$(CONFIG_WORD_SIZE).o \ 10 init_$(CONFIG_WORD_SIZE).o \
11 pgtable_$(CONFIG_WORD_SIZE).o \ 11 pgtable_$(CONFIG_WORD_SIZE).o
12 mmu_context_$(CONFIG_WORD_SIZE).o 12obj-$(CONFIG_PPC_MMU_NOHASH) += mmu_context_nohash.o
13hash-$(CONFIG_PPC_NATIVE) := hash_native_64.o 13hash-$(CONFIG_PPC_NATIVE) := hash_native_64.o
14obj-$(CONFIG_PPC64) += hash_utils_64.o \ 14obj-$(CONFIG_PPC64) += hash_utils_64.o \
15 slb_low.o slb.o stab.o \ 15 slb_low.o slb.o stab.o \
16 gup.o mmap.o $(hash-y) 16 gup.o mmap.o $(hash-y)
17obj-$(CONFIG_PPC_STD_MMU_32) += ppc_mmu_32.o 17obj-$(CONFIG_PPC_STD_MMU_32) += ppc_mmu_32.o
18obj-$(CONFIG_PPC_STD_MMU) += hash_low_$(CONFIG_WORD_SIZE).o \ 18obj-$(CONFIG_PPC_STD_MMU) += hash_low_$(CONFIG_WORD_SIZE).o \
19 tlb_hash$(CONFIG_WORD_SIZE).o 19 tlb_hash$(CONFIG_WORD_SIZE).o \
20 mmu_context_hash$(CONFIG_WORD_SIZE).o
20obj-$(CONFIG_40x) += 40x_mmu.o 21obj-$(CONFIG_40x) += 40x_mmu.o
21obj-$(CONFIG_44x) += 44x_mmu.o 22obj-$(CONFIG_44x) += 44x_mmu.o
22obj-$(CONFIG_FSL_BOOKE) += fsl_booke_mmu.o 23obj-$(CONFIG_FSL_BOOKE) += fsl_booke_mmu.o
diff --git a/arch/powerpc/mm/mmu_context_32.c b/arch/powerpc/mm/mmu_context_32.c
deleted file mode 100644
index cc32ba41d900..000000000000
--- a/arch/powerpc/mm/mmu_context_32.c
+++ /dev/null
@@ -1,84 +0,0 @@
1/*
2 * This file contains the routines for handling the MMU on those
3 * PowerPC implementations where the MMU substantially follows the
4 * architecture specification. This includes the 6xx, 7xx, 7xxx,
5 * 8260, and POWER3 implementations but excludes the 8xx and 4xx.
6 * -- paulus
7 *
8 * Derived from arch/ppc/mm/init.c:
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
10 *
11 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
12 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
13 * Copyright (C) 1996 Paul Mackerras
14 *
15 * Derived from "arch/i386/mm/init.c"
16 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
22 *
23 */
24
25#include <linux/mm.h>
26#include <linux/init.h>
27
28#include <asm/mmu_context.h>
29#include <asm/tlbflush.h>
30
31unsigned long next_mmu_context;
32unsigned long context_map[LAST_CONTEXT / BITS_PER_LONG + 1];
33#ifdef FEW_CONTEXTS
34atomic_t nr_free_contexts;
35struct mm_struct *context_mm[LAST_CONTEXT+1];
36void steal_context(void);
37#endif /* FEW_CONTEXTS */
38
39/*
40 * Initialize the context management stuff.
41 */
42void __init
43mmu_context_init(void)
44{
45 /*
46 * Some processors have too few contexts to reserve one for
47 * init_mm, and require using context 0 for a normal task.
48 * Other processors reserve the use of context zero for the kernel.
49 * This code assumes FIRST_CONTEXT < 32.
50 */
51 context_map[0] = (1 << FIRST_CONTEXT) - 1;
52 next_mmu_context = FIRST_CONTEXT;
53#ifdef FEW_CONTEXTS
54 atomic_set(&nr_free_contexts, LAST_CONTEXT - FIRST_CONTEXT + 1);
55#endif /* FEW_CONTEXTS */
56}
57
58#ifdef FEW_CONTEXTS
59/*
60 * Steal a context from a task that has one at the moment.
61 * This is only used on 8xx and 4xx and we presently assume that
62 * they don't do SMP. If they do then this will have to check
63 * whether the MM we steal is in use.
64 * We also assume that this is only used on systems that don't
65 * use an MMU hash table - this is true for 8xx and 4xx.
66 * This isn't an LRU system, it just frees up each context in
67 * turn (sort-of pseudo-random replacement :). This would be the
68 * place to implement an LRU scheme if anyone was motivated to do it.
69 * -- paulus
70 */
71void
72steal_context(void)
73{
74 struct mm_struct *mm;
75
76 /* free up context `next_mmu_context' */
77 /* if we shouldn't free context 0, don't... */
78 if (next_mmu_context < FIRST_CONTEXT)
79 next_mmu_context = FIRST_CONTEXT;
80 mm = context_mm[next_mmu_context];
81 flush_tlb_mm(mm);
82 destroy_context(mm);
83}
84#endif /* FEW_CONTEXTS */
diff --git a/arch/powerpc/mm/mmu_context_hash32.c b/arch/powerpc/mm/mmu_context_hash32.c
new file mode 100644
index 000000000000..0dfba2bf7f31
--- /dev/null
+++ b/arch/powerpc/mm/mmu_context_hash32.c
@@ -0,0 +1,103 @@
1/*
2 * This file contains the routines for handling the MMU on those
3 * PowerPC implementations where the MMU substantially follows the
4 * architecture specification. This includes the 6xx, 7xx, 7xxx,
5 * 8260, and POWER3 implementations but excludes the 8xx and 4xx.
6 * -- paulus
7 *
8 * Derived from arch/ppc/mm/init.c:
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
10 *
11 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
12 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
13 * Copyright (C) 1996 Paul Mackerras
14 *
15 * Derived from "arch/i386/mm/init.c"
16 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
22 *
23 */
24
25#include <linux/mm.h>
26#include <linux/init.h>
27
28#include <asm/mmu_context.h>
29#include <asm/tlbflush.h>
30
31/*
32 * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs
33 * (virtual segment identifiers) for each context. Although the
34 * hardware supports 24-bit VSIDs, and thus >1 million contexts,
35 * we only use 32,768 of them. That is ample, since there can be
36 * at most around 30,000 tasks in the system anyway, and it means
37 * that we can use a bitmap to indicate which contexts are in use.
38 * Using a bitmap means that we entirely avoid all of the problems
39 * that we used to have when the context number overflowed,
40 * particularly on SMP systems.
41 * -- paulus.
42 */
43#define NO_CONTEXT ((unsigned long) -1)
44#define LAST_CONTEXT 32767
45#define FIRST_CONTEXT 1
46
47/*
48 * This function defines the mapping from contexts to VSIDs (virtual
49 * segment IDs). We use a skew on both the context and the high 4 bits
50 * of the 32-bit virtual address (the "effective segment ID") in order
51 * to spread out the entries in the MMU hash table. Note, if this
52 * function is changed then arch/ppc/mm/hashtable.S will have to be
53 * changed to correspond.
54 *
55 *
56 * CTX_TO_VSID(ctx, va) (((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \
57 * & 0xffffff)
58 */
59
60static unsigned long next_mmu_context;
61static unsigned long context_map[LAST_CONTEXT / BITS_PER_LONG + 1];
62
63
64/*
65 * Set up the context for a new address space.
66 */
67int init_new_context(struct task_struct *t, struct mm_struct *mm)
68{
69 unsigned long ctx = next_mmu_context;
70
71 while (test_and_set_bit(ctx, context_map)) {
72 ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
73 if (ctx > LAST_CONTEXT)
74 ctx = 0;
75 }
76 next_mmu_context = (ctx + 1) & LAST_CONTEXT;
77 mm->context.id = ctx;
78
79 return 0;
80}
81
82/*
83 * We're finished using the context for an address space.
84 */
85void destroy_context(struct mm_struct *mm)
86{
87 preempt_disable();
88 if (mm->context.id != NO_CONTEXT) {
89 clear_bit(mm->context.id, context_map);
90 mm->context.id = NO_CONTEXT;
91 }
92 preempt_enable();
93}
94
95/*
96 * Initialize the context management stuff.
97 */
98void __init mmu_context_init(void)
99{
100 /* Reserve context 0 for kernel use */
101 context_map[0] = (1 << FIRST_CONTEXT) - 1;
102 next_mmu_context = FIRST_CONTEXT;
103}
diff --git a/arch/powerpc/mm/mmu_context_64.c b/arch/powerpc/mm/mmu_context_hash64.c
index 1db38ba1f544..dbeb86ac90cd 100644
--- a/arch/powerpc/mm/mmu_context_64.c
+++ b/arch/powerpc/mm/mmu_context_hash64.c
@@ -24,6 +24,14 @@
24static DEFINE_SPINLOCK(mmu_context_lock); 24static DEFINE_SPINLOCK(mmu_context_lock);
25static DEFINE_IDR(mmu_context_idr); 25static DEFINE_IDR(mmu_context_idr);
26 26
27/*
28 * The proto-VSID space has 2^35 - 1 segments available for user mappings.
29 * Each segment contains 2^28 bytes. Each context maps 2^44 bytes,
30 * so we can support 2^19-1 contexts (19 == 35 + 28 - 44).
31 */
32#define NO_CONTEXT 0
33#define MAX_CONTEXT ((1UL << 19) - 1)
34
27int init_new_context(struct task_struct *tsk, struct mm_struct *mm) 35int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
28{ 36{
29 int index; 37 int index;
diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm/mmu_context_nohash.c
new file mode 100644
index 000000000000..00e02150abef
--- /dev/null
+++ b/arch/powerpc/mm/mmu_context_nohash.c
@@ -0,0 +1,162 @@
1/*
2 * This file contains the routines for handling the MMU on those
3 * PowerPC implementations where the MMU is not using the hash
4 * table, such as 8xx, 4xx, BookE's etc...
5 *
6 * Copyright 2008 Ben Herrenschmidt <benh@kernel.crashing.org>
7 * IBM Corp.
8 *
9 * Derived from previous arch/powerpc/mm/mmu_context.c
10 * and arch/powerpc/include/asm/mmu_context.h
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
16 *
17 */
18
19#include <linux/mm.h>
20#include <linux/init.h>
21
22#include <asm/mmu_context.h>
23#include <asm/tlbflush.h>
24
25/*
26 * The MPC8xx has only 16 contexts. We rotate through them on each
27 * task switch. A better way would be to keep track of tasks that
28 * own contexts, and implement an LRU usage. That way very active
29 * tasks don't always have to pay the TLB reload overhead. The
30 * kernel pages are mapped shared, so the kernel can run on behalf
31 * of any task that makes a kernel entry. Shared does not mean they
32 * are not protected, just that the ASID comparison is not performed.
33 * -- Dan
34 *
35 * The IBM4xx has 256 contexts, so we can just rotate through these
36 * as a way of "switching" contexts. If the TID of the TLB is zero,
37 * the PID/TID comparison is disabled, so we can use a TID of zero
38 * to represent all kernel pages as shared among all contexts.
39 * -- Dan
40 */
41
42#ifdef CONFIG_8xx
43#define NO_CONTEXT 16
44#define LAST_CONTEXT 15
45#define FIRST_CONTEXT 0
46
47#elif defined(CONFIG_4xx)
48#define NO_CONTEXT 256
49#define LAST_CONTEXT 255
50#define FIRST_CONTEXT 1
51
52#elif defined(CONFIG_E200) || defined(CONFIG_E500)
53#define NO_CONTEXT 256
54#define LAST_CONTEXT 255
55#define FIRST_CONTEXT 1
56
57#else
58#error Unsupported processor type
59#endif
60
61static unsigned long next_mmu_context;
62static unsigned long context_map[LAST_CONTEXT / BITS_PER_LONG + 1];
63static atomic_t nr_free_contexts;
64static struct mm_struct *context_mm[LAST_CONTEXT+1];
65static void steal_context(void);
66
67/* Steal a context from a task that has one at the moment.
68 * This is only used on 8xx and 4xx and we presently assume that
69 * they don't do SMP. If they do then this will have to check
70 * whether the MM we steal is in use.
71 * We also assume that this is only used on systems that don't
72 * use an MMU hash table - this is true for 8xx and 4xx.
73 * This isn't an LRU system, it just frees up each context in
74 * turn (sort-of pseudo-random replacement :). This would be the
75 * place to implement an LRU scheme if anyone was motivated to do it.
76 * -- paulus
77 */
78static void steal_context(void)
79{
80 struct mm_struct *mm;
81
82 /* free up context `next_mmu_context' */
83 /* if we shouldn't free context 0, don't... */
84 if (next_mmu_context < FIRST_CONTEXT)
85 next_mmu_context = FIRST_CONTEXT;
86 mm = context_mm[next_mmu_context];
87 flush_tlb_mm(mm);
88 destroy_context(mm);
89}
90
91
92/*
93 * Get a new mmu context for the address space described by `mm'.
94 */
95static inline void get_mmu_context(struct mm_struct *mm)
96{
97 unsigned long ctx;
98
99 if (mm->context.id != NO_CONTEXT)
100 return;
101
102 while (atomic_dec_if_positive(&nr_free_contexts) < 0)
103 steal_context();
104
105 ctx = next_mmu_context;
106 while (test_and_set_bit(ctx, context_map)) {
107 ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
108 if (ctx > LAST_CONTEXT)
109 ctx = 0;
110 }
111 next_mmu_context = (ctx + 1) & LAST_CONTEXT;
112 mm->context.id = ctx;
113 context_mm[ctx] = mm;
114}
115
116void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
117{
118 get_mmu_context(next);
119
120 set_context(next->context.id, next->pgd);
121}
122
123/*
124 * Set up the context for a new address space.
125 */
126int init_new_context(struct task_struct *t, struct mm_struct *mm)
127{
128 mm->context.id = NO_CONTEXT;
129 return 0;
130}
131
132/*
133 * We're finished using the context for an address space.
134 */
135void destroy_context(struct mm_struct *mm)
136{
137 preempt_disable();
138 if (mm->context.id != NO_CONTEXT) {
139 clear_bit(mm->context.id, context_map);
140 mm->context.id = NO_CONTEXT;
141 atomic_inc(&nr_free_contexts);
142 }
143 preempt_enable();
144}
145
146
147/*
148 * Initialize the context management stuff.
149 */
150void __init mmu_context_init(void)
151{
152 /*
153 * Some processors have too few contexts to reserve one for
154 * init_mm, and require using context 0 for a normal task.
155 * Other processors reserve the use of context zero for the kernel.
156 * This code assumes FIRST_CONTEXT < 32.
157 */
158 context_map[0] = (1 << FIRST_CONTEXT) - 1;
159 next_mmu_context = FIRST_CONTEXT;
160 atomic_set(&nr_free_contexts, LAST_CONTEXT - FIRST_CONTEXT + 1);
161}
162
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 548efa55c8fe..db61dafb924d 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -195,13 +195,21 @@ config SPE
195 195
196config PPC_STD_MMU 196config PPC_STD_MMU
197 bool 197 bool
198 depends on 6xx || POWER3 || POWER4 || PPC64 198 depends on 6xx || PPC64
199 default y 199 default y
200 200
201config PPC_STD_MMU_32 201config PPC_STD_MMU_32
202 def_bool y 202 def_bool y
203 depends on PPC_STD_MMU && PPC32 203 depends on PPC_STD_MMU && PPC32
204 204
205config PPC_STD_MMU_64
206 def_bool y
207 depends on PPC_STD_MMU && PPC64
208
209config PPC_MMU_NOHASH
210 def_bool y
211 depends on !PPC_STD_MMU
212
205config PPC_MM_SLICES 213config PPC_MM_SLICES
206 bool 214 bool
207 default y if HUGETLB_PAGE || PPC_64K_PAGES 215 default y if HUGETLB_PAGE || PPC_64K_PAGES
diff --git a/arch/powerpc/platforms/powermac/cpufreq_32.c b/arch/powerpc/platforms/powermac/cpufreq_32.c
index 792d3ce8112e..65c585b8b00d 100644
--- a/arch/powerpc/platforms/powermac/cpufreq_32.c
+++ b/arch/powerpc/platforms/powermac/cpufreq_32.c
@@ -310,7 +310,7 @@ static int pmu_set_cpu_speed(int low_speed)
310 _set_L3CR(save_l3cr); 310 _set_L3CR(save_l3cr);
311 311
312 /* Restore userland MMU context */ 312 /* Restore userland MMU context */
313 set_context(current->active_mm->context.id, current->active_mm->pgd); 313 switch_mmu_context(NULL, current->active_mm);
314 314
315#ifdef DEBUG_FREQ 315#ifdef DEBUG_FREQ
316 printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1)); 316 printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1));
diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c
index d524dc245a2c..b40fb9b6c862 100644
--- a/drivers/macintosh/via-pmu.c
+++ b/drivers/macintosh/via-pmu.c
@@ -1814,7 +1814,7 @@ static int powerbook_sleep_grackle(void)
1814 _set_L2CR(save_l2cr); 1814 _set_L2CR(save_l2cr);
1815 1815
1816 /* Restore userland MMU context */ 1816 /* Restore userland MMU context */
1817 set_context(current->active_mm->context.id, current->active_mm->pgd); 1817 switch_mmu_context(NULL, current->active_mm);
1818 1818
1819 /* Power things up */ 1819 /* Power things up */
1820 pmu_unlock(); 1820 pmu_unlock();
@@ -1903,7 +1903,7 @@ powerbook_sleep_Core99(void)
1903 _set_L3CR(save_l3cr); 1903 _set_L3CR(save_l3cr);
1904 1904
1905 /* Restore userland MMU context */ 1905 /* Restore userland MMU context */
1906 set_context(current->active_mm->context.id, current->active_mm->pgd); 1906 switch_mmu_context(NULL, current->active_mm);
1907 1907
1908 /* Tell PMU we are ready */ 1908 /* Tell PMU we are ready */
1909 pmu_unlock(); 1909 pmu_unlock();
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 19:52:02 -0500