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authorPaul Mundt <lethal@linux-sh.org>2009-12-24 00:52:43 -0500
committerPaul Mundt <lethal@linux-sh.org>2009-12-24 00:52:43 -0500
commit32b53076c31ce9159740b744d5eb5d9505312add (patch)
tree6687980a51c74629085eb8fa2e62172f480b3d53
parent154280fd0e890814a249bf4a79b4340fb367f1a7 (diff)
serial: sh-sci: Convert tremaining ctrl_xxx I/O routines to __raw_xxx.
ctrl_xxx() is an antiquated SH interface, while __raw_xxx is the standard API that accomplishes the same thing. As such, this converts the remaining sh-sci straggles over, which enables the driver to be wired up for ARM SH-Mobile CPUs as well. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--drivers/serial/sh-sci.c4
-rw-r--r--drivers/serial/sh-sci.h118
2 files changed, 61 insertions, 61 deletions
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index a88699051136..37f0de9dd9ce 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -222,9 +222,9 @@ static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
222 Set SCP6MD1,0 = {01} (output) */ 222 Set SCP6MD1,0 = {01} (output) */
223 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR); 223 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
224 224
225 data = ctrl_inb(SCPDR); 225 data = __raw_readb(SCPDR);
226 /* Set /RTS2 (bit6) = 0 */ 226 /* Set /RTS2 (bit6) = 0 */
227 ctrl_outb(data & 0xbf, SCPDR); 227 __raw_writeb(data & 0xbf, SCPDR);
228 } 228 }
229} 229}
230#elif defined(CONFIG_CPU_SUBTYPE_SH7722) 230#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index a32094eeb42b..0efcded59ae6 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -517,20 +517,20 @@ static const struct __attribute__((packed)) {
517static inline int sci_rxd_in(struct uart_port *port) 517static inline int sci_rxd_in(struct uart_port *port)
518{ 518{
519 if (port->mapbase == 0xfffffe80) 519 if (port->mapbase == 0xfffffe80)
520 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */ 520 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
521 if (port->mapbase == 0xa4000150) 521 if (port->mapbase == 0xa4000150)
522 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ 522 return __raw_readb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
523 if (port->mapbase == 0xa4000140) 523 if (port->mapbase == 0xa4000140)
524 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ 524 return __raw_readb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
525 return 1; 525 return 1;
526} 526}
527#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 527#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
528static inline int sci_rxd_in(struct uart_port *port) 528static inline int sci_rxd_in(struct uart_port *port)
529{ 529{
530 if (port->mapbase == SCIF0) 530 if (port->mapbase == SCIF0)
531 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ 531 return __raw_readb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
532 if (port->mapbase == SCIF2) 532 if (port->mapbase == SCIF2)
533 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ 533 return __raw_readb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
534 return 1; 534 return 1;
535} 535}
536#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 536#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
@@ -557,68 +557,68 @@ static inline int sci_rxd_in(struct uart_port *port)
557static inline int sci_rxd_in(struct uart_port *port) 557static inline int sci_rxd_in(struct uart_port *port)
558{ 558{
559 if (port->mapbase == 0xffe00000) 559 if (port->mapbase == 0xffe00000)
560 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ 560 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
561 if (port->mapbase == 0xffe80000) 561 if (port->mapbase == 0xffe80000)
562 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ 562 return __raw_readw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
563 return 1; 563 return 1;
564} 564}
565#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) 565#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
566static inline int sci_rxd_in(struct uart_port *port) 566static inline int sci_rxd_in(struct uart_port *port)
567{ 567{
568 if (port->mapbase == 0xffe80000) 568 if (port->mapbase == 0xffe80000)
569 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ 569 return __raw_readw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
570 return 1; 570 return 1;
571} 571}
572#elif defined(CONFIG_CPU_SUBTYPE_SH7757) 572#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
573static inline int sci_rxd_in(struct uart_port *port) 573static inline int sci_rxd_in(struct uart_port *port)
574{ 574{
575 if (port->mapbase == 0xfe4b0000) 575 if (port->mapbase == 0xfe4b0000)
576 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; 576 return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0;
577 if (port->mapbase == 0xfe4c0000) 577 if (port->mapbase == 0xfe4c0000)
578 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; 578 return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0;
579 if (port->mapbase == 0xfe4d0000) 579 if (port->mapbase == 0xfe4d0000)
580 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; 580 return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0;
581} 581}
582#elif defined(CONFIG_CPU_SUBTYPE_SH7760) 582#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
583static inline int sci_rxd_in(struct uart_port *port) 583static inline int sci_rxd_in(struct uart_port *port)
584{ 584{
585 if (port->mapbase == 0xfe600000) 585 if (port->mapbase == 0xfe600000)
586 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 586 return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
587 if (port->mapbase == 0xfe610000) 587 if (port->mapbase == 0xfe610000)
588 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 588 return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
589 if (port->mapbase == 0xfe620000) 589 if (port->mapbase == 0xfe620000)
590 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 590 return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
591 return 1; 591 return 1;
592} 592}
593#elif defined(CONFIG_CPU_SUBTYPE_SH7343) 593#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
594static inline int sci_rxd_in(struct uart_port *port) 594static inline int sci_rxd_in(struct uart_port *port)
595{ 595{
596 if (port->mapbase == 0xffe00000) 596 if (port->mapbase == 0xffe00000)
597 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 597 return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
598 if (port->mapbase == 0xffe10000) 598 if (port->mapbase == 0xffe10000)
599 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 599 return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
600 if (port->mapbase == 0xffe20000) 600 if (port->mapbase == 0xffe20000)
601 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 601 return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
602 if (port->mapbase == 0xffe30000) 602 if (port->mapbase == 0xffe30000)
603 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 603 return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
604 return 1; 604 return 1;
605} 605}
606#elif defined(CONFIG_CPU_SUBTYPE_SH7366) 606#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
607static inline int sci_rxd_in(struct uart_port *port) 607static inline int sci_rxd_in(struct uart_port *port)
608{ 608{
609 if (port->mapbase == 0xffe00000) 609 if (port->mapbase == 0xffe00000)
610 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ 610 return __raw_readb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
611 return 1; 611 return 1;
612} 612}
613#elif defined(CONFIG_CPU_SUBTYPE_SH7722) 613#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
614static inline int sci_rxd_in(struct uart_port *port) 614static inline int sci_rxd_in(struct uart_port *port)
615{ 615{
616 if (port->mapbase == 0xffe00000) 616 if (port->mapbase == 0xffe00000)
617 return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */ 617 return __raw_readb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */
618 if (port->mapbase == 0xffe10000) 618 if (port->mapbase == 0xffe10000)
619 return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */ 619 return __raw_readb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */
620 if (port->mapbase == 0xffe20000) 620 if (port->mapbase == 0xffe20000)
621 return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */ 621 return __raw_readb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */
622 622
623 return 1; 623 return 1;
624} 624}
@@ -626,17 +626,17 @@ static inline int sci_rxd_in(struct uart_port *port)
626static inline int sci_rxd_in(struct uart_port *port) 626static inline int sci_rxd_in(struct uart_port *port)
627{ 627{
628 if (port->mapbase == 0xffe00000) 628 if (port->mapbase == 0xffe00000)
629 return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */ 629 return __raw_readb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
630 if (port->mapbase == 0xffe10000) 630 if (port->mapbase == 0xffe10000)
631 return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */ 631 return __raw_readb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
632 if (port->mapbase == 0xffe20000) 632 if (port->mapbase == 0xffe20000)
633 return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */ 633 return __raw_readb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
634 if (port->mapbase == 0xa4e30000) 634 if (port->mapbase == 0xa4e30000)
635 return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */ 635 return __raw_readb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
636 if (port->mapbase == 0xa4e40000) 636 if (port->mapbase == 0xa4e40000)
637 return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */ 637 return __raw_readb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
638 if (port->mapbase == 0xa4e50000) 638 if (port->mapbase == 0xa4e50000)
639 return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */ 639 return __raw_readb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
640 return 1; 640 return 1;
641} 641}
642#elif defined(CONFIG_CPU_SUBTYPE_SH7724) 642#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
@@ -645,9 +645,9 @@ static inline int sci_rxd_in(struct uart_port *port)
645static inline int sci_rxd_in(struct uart_port *port) 645static inline int sci_rxd_in(struct uart_port *port)
646{ 646{
647 if (port->type == PORT_SCIF) 647 if (port->type == PORT_SCIF)
648 return ctrl_inw((port->mapbase + SCFSR)) & SCIF_BRK ? 1 : 0; 648 return __raw_readw((port->mapbase + SCFSR)) & SCIF_BRK ? 1 : 0;
649 if (port->type == PORT_SCIFA) 649 if (port->type == PORT_SCIFA)
650 return ctrl_inw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0; 650 return __raw_readw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0;
651 return 1; 651 return 1;
652} 652}
653#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) 653#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
@@ -665,11 +665,11 @@ static inline int sci_rxd_in(struct uart_port *port)
665static inline int sci_rxd_in(struct uart_port *port) 665static inline int sci_rxd_in(struct uart_port *port)
666{ 666{
667 if (port->mapbase == 0xffe00000) 667 if (port->mapbase == 0xffe00000)
668 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 668 return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
669 if (port->mapbase == 0xffe08000) 669 if (port->mapbase == 0xffe08000)
670 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 670 return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
671 if (port->mapbase == 0xffe10000) 671 if (port->mapbase == 0xffe10000)
672 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */ 672 return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */
673 673
674 return 1; 674 return 1;
675} 675}
@@ -677,20 +677,20 @@ static inline int sci_rxd_in(struct uart_port *port)
677static inline int sci_rxd_in(struct uart_port *port) 677static inline int sci_rxd_in(struct uart_port *port)
678{ 678{
679 if (port->mapbase == 0xff923000) 679 if (port->mapbase == 0xff923000)
680 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 680 return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
681 if (port->mapbase == 0xff924000) 681 if (port->mapbase == 0xff924000)
682 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 682 return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
683 if (port->mapbase == 0xff925000) 683 if (port->mapbase == 0xff925000)
684 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 684 return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
685 return 1; 685 return 1;
686} 686}
687#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 687#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
688static inline int sci_rxd_in(struct uart_port *port) 688static inline int sci_rxd_in(struct uart_port *port)
689{ 689{
690 if (port->mapbase == 0xffe00000) 690 if (port->mapbase == 0xffe00000)
691 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 691 return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
692 if (port->mapbase == 0xffe10000) 692 if (port->mapbase == 0xffe10000)
693 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 693 return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
694 return 1; 694 return 1;
695} 695}
696#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \ 696#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
@@ -698,17 +698,17 @@ static inline int sci_rxd_in(struct uart_port *port)
698static inline int sci_rxd_in(struct uart_port *port) 698static inline int sci_rxd_in(struct uart_port *port)
699{ 699{
700 if (port->mapbase == 0xffea0000) 700 if (port->mapbase == 0xffea0000)
701 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 701 return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
702 if (port->mapbase == 0xffeb0000) 702 if (port->mapbase == 0xffeb0000)
703 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 703 return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
704 if (port->mapbase == 0xffec0000) 704 if (port->mapbase == 0xffec0000)
705 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 705 return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
706 if (port->mapbase == 0xffed0000) 706 if (port->mapbase == 0xffed0000)
707 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 707 return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
708 if (port->mapbase == 0xffee0000) 708 if (port->mapbase == 0xffee0000)
709 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */ 709 return __raw_readw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
710 if (port->mapbase == 0xffef0000) 710 if (port->mapbase == 0xffef0000)
711 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */ 711 return __raw_readw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
712 return 1; 712 return 1;
713} 713}
714#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \ 714#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
@@ -718,22 +718,22 @@ static inline int sci_rxd_in(struct uart_port *port)
718static inline int sci_rxd_in(struct uart_port *port) 718static inline int sci_rxd_in(struct uart_port *port)
719{ 719{
720 if (port->mapbase == 0xfffe8000) 720 if (port->mapbase == 0xfffe8000)
721 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 721 return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
722 if (port->mapbase == 0xfffe8800) 722 if (port->mapbase == 0xfffe8800)
723 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 723 return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
724 if (port->mapbase == 0xfffe9000) 724 if (port->mapbase == 0xfffe9000)
725 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 725 return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
726 if (port->mapbase == 0xfffe9800) 726 if (port->mapbase == 0xfffe9800)
727 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 727 return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
728#if defined(CONFIG_CPU_SUBTYPE_SH7201) 728#if defined(CONFIG_CPU_SUBTYPE_SH7201)
729 if (port->mapbase == 0xfffeA000) 729 if (port->mapbase == 0xfffeA000)
730 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 730 return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
731 if (port->mapbase == 0xfffeA800) 731 if (port->mapbase == 0xfffeA800)
732 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 732 return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
733 if (port->mapbase == 0xfffeB000) 733 if (port->mapbase == 0xfffeB000)
734 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 734 return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
735 if (port->mapbase == 0xfffeB800) 735 if (port->mapbase == 0xfffeB800)
736 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 736 return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
737#endif 737#endif
738 return 1; 738 return 1;
739} 739}
@@ -741,24 +741,24 @@ static inline int sci_rxd_in(struct uart_port *port)
741static inline int sci_rxd_in(struct uart_port *port) 741static inline int sci_rxd_in(struct uart_port *port)
742{ 742{
743 if (port->mapbase == 0xf8400000) 743 if (port->mapbase == 0xf8400000)
744 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 744 return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
745 if (port->mapbase == 0xf8410000) 745 if (port->mapbase == 0xf8410000)
746 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 746 return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
747 if (port->mapbase == 0xf8420000) 747 if (port->mapbase == 0xf8420000)
748 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 748 return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
749 return 1; 749 return 1;
750} 750}
751#elif defined(CONFIG_CPU_SUBTYPE_SHX3) 751#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
752static inline int sci_rxd_in(struct uart_port *port) 752static inline int sci_rxd_in(struct uart_port *port)
753{ 753{
754 if (port->mapbase == 0xffc30000) 754 if (port->mapbase == 0xffc30000)
755 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 755 return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
756 if (port->mapbase == 0xffc40000) 756 if (port->mapbase == 0xffc40000)
757 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 757 return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
758 if (port->mapbase == 0xffc50000) 758 if (port->mapbase == 0xffc50000)
759 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 759 return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
760 if (port->mapbase == 0xffc60000) 760 if (port->mapbase == 0xffc60000)
761 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 761 return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
762 return 1; 762 return 1;
763} 763}
764#endif 764#endif