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authorClemens Ladisch <clemens@ladisch.de>2008-01-18 03:17:53 -0500
committerJaroslav Kysela <perex@perex.cz>2008-01-31 11:30:04 -0500
commitc2353a0826d2b8fe9f5c6a6aca99149e4ee7b196 (patch)
treebd15b1625da94b87a6f0602b47a35c09385f56ba
parent4052ce4cbf48531bdd8ff43b673ccb5c005dec79 (diff)
[ALSA] oxygen: add register definitions
Add more symbols for registers and register fields. Signed-off-by: Clemens Ladisch <clemens@ladisch.de> Signed-off-by: Jaroslav Kysela <perex@perex.cz>
Diffstat
-rw-r--r--sound/pci/oxygen/oxygen.c11
-rw-r--r--sound/pci/oxygen/oxygen_io.c4
-rw-r--r--sound/pci/oxygen/oxygen_lib.c49
-rw-r--r--sound/pci/oxygen/oxygen_pcm.c33
-rw-r--r--sound/pci/oxygen/oxygen_regs.h289
-rw-r--r--sound/pci/oxygen/virtuoso.c5
6 files changed, 296 insertions, 95 deletions
diff --git a/sound/pci/oxygen/oxygen.c b/sound/pci/oxygen/oxygen.c
index e618cde7f9e4..e0e54ab51e5c 100644
--- a/sound/pci/oxygen/oxygen.c
+++ b/sound/pci/oxygen/oxygen.c
@@ -102,18 +102,21 @@ static void ak4396_write(struct oxygen *chip, unsigned int codec,
102 static const u8 codec_spi_map[4] = { 102 static const u8 codec_spi_map[4] = {
103 0, 1, 2, 4 103 0, 1, 2, 4
104 }; 104 };
105 oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER_WRITE | 105 oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
106 OXYGEN_SPI_DATA_LENGTH_2 | 106 OXYGEN_SPI_DATA_LENGTH_2 |
107 OXYGEN_SPI_CLOCK_160 |
107 (codec_spi_map[codec] << OXYGEN_SPI_CODEC_SHIFT) | 108 (codec_spi_map[codec] << OXYGEN_SPI_CODEC_SHIFT) |
108 OXYGEN_SPI_MAGIC, 109 OXYGEN_SPI_CEN_LATCH_CLOCK_HI,
109 AK4396_WRITE | (reg << 8) | value); 110 AK4396_WRITE | (reg << 8) | value);
110} 111}
111 112
112static void wm8785_write(struct oxygen *chip, u8 reg, unsigned int value) 113static void wm8785_write(struct oxygen *chip, u8 reg, unsigned int value)
113{ 114{
114 oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER_WRITE | 115 oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
115 OXYGEN_SPI_DATA_LENGTH_2 | 116 OXYGEN_SPI_DATA_LENGTH_2 |
116 (3 << OXYGEN_SPI_CODEC_SHIFT), 117 OXYGEN_SPI_CLOCK_160 |
118 (3 << OXYGEN_SPI_CODEC_SHIFT) |
119 OXYGEN_SPI_CEN_LATCH_CLOCK_LO,
117 (reg << 9) | value); 120 (reg << 9) | value);
118} 121}
119 122
diff --git a/sound/pci/oxygen/oxygen_io.c b/sound/pci/oxygen/oxygen_io.c
index 616087c552e2..ebafc65dc345 100644
--- a/sound/pci/oxygen/oxygen_io.c
+++ b/sound/pci/oxygen/oxygen_io.c
@@ -119,7 +119,7 @@ void oxygen_write_ac97(struct oxygen *chip, unsigned int codec,
119 udelay(5); 119 udelay(5);
120 oxygen_write32(chip, OXYGEN_AC97_REGS, reg); 120 oxygen_write32(chip, OXYGEN_AC97_REGS, reg);
121 /* require two "completed" writes, just to be sure */ 121 /* require two "completed" writes, just to be sure */
122 if (oxygen_ac97_wait(chip, OXYGEN_AC97_WRITE_COMPLETE) >= 0 && 122 if (oxygen_ac97_wait(chip, OXYGEN_AC97_INT_WRITE_DONE) >= 0 &&
123 ++succeeded >= 2) 123 ++succeeded >= 2)
124 return; 124 return;
125 } 125 }
@@ -141,7 +141,7 @@ u16 oxygen_read_ac97(struct oxygen *chip, unsigned int codec,
141 udelay(5); 141 udelay(5);
142 oxygen_write32(chip, OXYGEN_AC97_REGS, reg); 142 oxygen_write32(chip, OXYGEN_AC97_REGS, reg);
143 udelay(10); 143 udelay(10);
144 if (oxygen_ac97_wait(chip, OXYGEN_AC97_READ_COMPLETE) >= 0) { 144 if (oxygen_ac97_wait(chip, OXYGEN_AC97_INT_READ_DONE) >= 0) {
145 u16 value = oxygen_read16(chip, OXYGEN_AC97_REGS); 145 u16 value = oxygen_read16(chip, OXYGEN_AC97_REGS);
146 /* we require two consecutive reads of the same value */ 146 /* we require two consecutive reads of the same value */
147 if (value == last_read) 147 if (value == last_read)
diff --git a/sound/pci/oxygen/oxygen_lib.c b/sound/pci/oxygen/oxygen_lib.c
index 4edf40b65ae1..79e7c16c71ff 100644
--- a/sound/pci/oxygen/oxygen_lib.c
+++ b/sound/pci/oxygen/oxygen_lib.c
@@ -51,11 +51,11 @@ static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
51 OXYGEN_CHANNEL_SPDIF | 51 OXYGEN_CHANNEL_SPDIF |
52 OXYGEN_CHANNEL_MULTICH | 52 OXYGEN_CHANNEL_MULTICH |
53 OXYGEN_CHANNEL_AC97 | 53 OXYGEN_CHANNEL_AC97 |
54 OXYGEN_INT_SPDIF_IN_CHANGE | 54 OXYGEN_INT_SPDIF_IN_DETECT |
55 OXYGEN_INT_GPIO); 55 OXYGEN_INT_GPIO);
56 if (clear) { 56 if (clear) {
57 if (clear & OXYGEN_INT_SPDIF_IN_CHANGE) 57 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
58 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_CHANGE; 58 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
59 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 59 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
60 chip->interrupt_mask & ~clear); 60 chip->interrupt_mask & ~clear);
61 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 61 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
@@ -70,10 +70,10 @@ static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
70 if ((elapsed_streams & (1 << i)) && chip->streams[i]) 70 if ((elapsed_streams & (1 << i)) && chip->streams[i])
71 snd_pcm_period_elapsed(chip->streams[i]); 71 snd_pcm_period_elapsed(chip->streams[i]);
72 72
73 if (status & OXYGEN_INT_SPDIF_IN_CHANGE) { 73 if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
74 spin_lock(&chip->reg_lock); 74 spin_lock(&chip->reg_lock);
75 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); 75 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
76 if (i & OXYGEN_SPDIF_IN_CHANGE) { 76 if (i & OXYGEN_SPDIF_RATE_INT) {
77 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i); 77 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
78 schedule_work(&chip->spdif_input_bits_work); 78 schedule_work(&chip->spdif_input_bits_work);
79 } 79 }
@@ -95,28 +95,32 @@ static void oxygen_spdif_input_bits_changed(struct work_struct *work)
95 spdif_input_bits_work); 95 spdif_input_bits_work);
96 96
97 spin_lock_irq(&chip->reg_lock); 97 spin_lock_irq(&chip->reg_lock);
98 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_IN_INVERT); 98 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
99 OXYGEN_SPDIF_IN_CLOCK_96,
100 OXYGEN_SPDIF_IN_CLOCK_MASK);
99 spin_unlock_irq(&chip->reg_lock); 101 spin_unlock_irq(&chip->reg_lock);
100 msleep(1); 102 msleep(1);
101 if (!(oxygen_read32(chip, OXYGEN_SPDIF_CONTROL) 103 if (!(oxygen_read32(chip, OXYGEN_SPDIF_CONTROL)
102 & OXYGEN_SPDIF_IN_VALID)) { 104 & OXYGEN_SPDIF_LOCK_STATUS)) {
103 spin_lock_irq(&chip->reg_lock); 105 spin_lock_irq(&chip->reg_lock);
104 oxygen_set_bits32(chip, OXYGEN_SPDIF_CONTROL, 106 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
105 OXYGEN_SPDIF_IN_INVERT); 107 OXYGEN_SPDIF_IN_CLOCK_192,
108 OXYGEN_SPDIF_IN_CLOCK_MASK);
106 spin_unlock_irq(&chip->reg_lock); 109 spin_unlock_irq(&chip->reg_lock);
107 msleep(1); 110 msleep(1);
108 if (!(oxygen_read32(chip, OXYGEN_SPDIF_CONTROL) 111 if (!(oxygen_read32(chip, OXYGEN_SPDIF_CONTROL)
109 & OXYGEN_SPDIF_IN_VALID)) { 112 & OXYGEN_SPDIF_LOCK_STATUS)) {
110 spin_lock_irq(&chip->reg_lock); 113 spin_lock_irq(&chip->reg_lock);
111 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, 114 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
112 OXYGEN_SPDIF_IN_INVERT); 115 OXYGEN_SPDIF_IN_CLOCK_96,
116 OXYGEN_SPDIF_IN_CLOCK_MASK);
113 spin_unlock_irq(&chip->reg_lock); 117 spin_unlock_irq(&chip->reg_lock);
114 } 118 }
115 } 119 }
116 120
117 if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) { 121 if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
118 spin_lock_irq(&chip->reg_lock); 122 spin_lock_irq(&chip->reg_lock);
119 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_CHANGE; 123 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
120 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 124 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
121 chip->interrupt_mask); 125 chip->interrupt_mask);
122 spin_unlock_irq(&chip->reg_lock); 126 spin_unlock_irq(&chip->reg_lock);
@@ -194,7 +198,8 @@ static void __devinit oxygen_init(struct oxygen *chip)
194 chip->revision = 1; 198 chip->revision = 1;
195 199
196 if (chip->revision == 1) 200 if (chip->revision == 1)
197 oxygen_set_bits8(chip, OXYGEN_MISC, OXYGEN_MISC_MAGIC); 201 oxygen_set_bits8(chip, OXYGEN_MISC,
202 OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
198 203
199 i = oxygen_read16(chip, OXYGEN_AC97_CONTROL); 204 i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
200 chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0; 205 chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
@@ -207,7 +212,7 @@ static void __devinit oxygen_init(struct oxygen *chip)
207 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, 0x010a); 212 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, 0x010a);
208 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT, 0x010a); 213 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT, 0x010a);
209 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT, 0x010a); 214 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT, 0x010a);
210 oxygen_set_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_MAGIC2); 215 oxygen_set_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_RATE_MASK);
211 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits); 216 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
212 oxygen_write16(chip, OXYGEN_PLAY_ROUTING, 0xe100); 217 oxygen_write16(chip, OXYGEN_PLAY_ROUTING, 0xe100);
213 oxygen_write8(chip, OXYGEN_REC_ROUTING, 0x10); 218 oxygen_write8(chip, OXYGEN_REC_ROUTING, 0x10);
@@ -220,9 +225,17 @@ static void __devinit oxygen_init(struct oxygen *chip)
220 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0x00); 225 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0x00);
221 if (chip->has_ac97_0) { 226 if (chip->has_ac97_0) {
222 oxygen_clear_bits16(chip, OXYGEN_AC97_OUT_CONFIG, 227 oxygen_clear_bits16(chip, OXYGEN_AC97_OUT_CONFIG,
223 OXYGEN_AC97_OUT_MAGIC3); 228 OXYGEN_AC97_CODEC0_FRONTL |
229 OXYGEN_AC97_CODEC0_FRONTR |
230 OXYGEN_AC97_CODEC0_SIDEL |
231 OXYGEN_AC97_CODEC0_SIDER |
232 OXYGEN_AC97_CODEC0_CENTER |
233 OXYGEN_AC97_CODEC0_BASE |
234 OXYGEN_AC97_CODEC0_REARL |
235 OXYGEN_AC97_CODEC0_REARR);
224 oxygen_set_bits16(chip, OXYGEN_AC97_IN_CONFIG, 236 oxygen_set_bits16(chip, OXYGEN_AC97_IN_CONFIG,
225 OXYGEN_AC97_IN_MAGIC3); 237 OXYGEN_AC97_CODEC0_LINEL |
238 OXYGEN_AC97_CODEC0_LINER);
226 oxygen_write_ac97(chip, 0, AC97_RESET, 0); 239 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
227 msleep(1); 240 msleep(1);
228 oxygen_ac97_set_bits(chip, 0, 0x70, 0x0300); 241 oxygen_ac97_set_bits(chip, 0, 0x70, 0x0300);
@@ -349,7 +362,7 @@ int __devinit oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
349 oxygen_proc_init(chip); 362 oxygen_proc_init(chip);
350 363
351 spin_lock_irq(&chip->reg_lock); 364 spin_lock_irq(&chip->reg_lock);
352 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_CHANGE; 365 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
353 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask); 366 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
354 spin_unlock_irq(&chip->reg_lock); 367 spin_unlock_irq(&chip->reg_lock);
355 368
diff --git a/sound/pci/oxygen/oxygen_pcm.c b/sound/pci/oxygen/oxygen_pcm.c
index f24659af53d3..72481fdd11f3 100644
--- a/sound/pci/oxygen/oxygen_pcm.c
+++ b/sound/pci/oxygen/oxygen_pcm.c
@@ -308,9 +308,10 @@ static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
308 } 308 }
309} 309}
310 310
311static unsigned int oxygen_i2s_magic2(struct snd_pcm_hw_params *hw_params) 311static unsigned int oxygen_i2s_mclk(struct snd_pcm_hw_params *hw_params)
312{ 312{
313 return params_rate(hw_params) <= 96000 ? 0x10 : 0x00; 313 return params_rate(hw_params) <= 96000
314 ? OXYGEN_I2S_MCLK_256 : OXYGEN_I2S_MCLK_128;
314} 315}
315 316
316static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params) 317static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
@@ -388,12 +389,12 @@ static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
388 OXYGEN_REC_FORMAT_A_MASK); 389 OXYGEN_REC_FORMAT_A_MASK);
389 oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT, 390 oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT,
390 oxygen_rate(hw_params) | 391 oxygen_rate(hw_params) |
391 oxygen_i2s_magic2(hw_params) | 392 oxygen_i2s_mclk(hw_params) |
392 chip->model->adc_i2s_format | 393 chip->model->adc_i2s_format |
393 oxygen_i2s_bits(hw_params), 394 oxygen_i2s_bits(hw_params),
394 OXYGEN_I2S_RATE_MASK | 395 OXYGEN_I2S_RATE_MASK |
395 OXYGEN_I2S_FORMAT_MASK | 396 OXYGEN_I2S_FORMAT_MASK |
396 OXYGEN_I2S_MAGIC2_MASK | 397 OXYGEN_I2S_MCLK_MASK |
397 OXYGEN_I2S_BITS_MASK); 398 OXYGEN_I2S_BITS_MASK);
398 oxygen_clear_bits8(chip, OXYGEN_REC_ROUTING, 0x08); 399 oxygen_clear_bits8(chip, OXYGEN_REC_ROUTING, 0x08);
399 spin_unlock_irq(&chip->reg_lock); 400 spin_unlock_irq(&chip->reg_lock);
@@ -420,12 +421,12 @@ static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
420 OXYGEN_REC_FORMAT_B_MASK); 421 OXYGEN_REC_FORMAT_B_MASK);
421 oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT, 422 oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT,
422 oxygen_rate(hw_params) | 423 oxygen_rate(hw_params) |
423 oxygen_i2s_magic2(hw_params) | 424 oxygen_i2s_mclk(hw_params) |
424 chip->model->adc_i2s_format | 425 chip->model->adc_i2s_format |
425 oxygen_i2s_bits(hw_params), 426 oxygen_i2s_bits(hw_params),
426 OXYGEN_I2S_RATE_MASK | 427 OXYGEN_I2S_RATE_MASK |
427 OXYGEN_I2S_FORMAT_MASK | 428 OXYGEN_I2S_FORMAT_MASK |
428 OXYGEN_I2S_MAGIC2_MASK | 429 OXYGEN_I2S_MCLK_MASK |
429 OXYGEN_I2S_BITS_MASK); 430 OXYGEN_I2S_BITS_MASK);
430 oxygen_clear_bits8(chip, OXYGEN_REC_ROUTING, 0x10); 431 oxygen_clear_bits8(chip, OXYGEN_REC_ROUTING, 0x10);
431 spin_unlock_irq(&chip->reg_lock); 432 spin_unlock_irq(&chip->reg_lock);
@@ -514,24 +515,6 @@ static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
514 return 0; 515 return 0;
515} 516}
516 517
517static int oxygen_ac97_hw_params(struct snd_pcm_substream *substream,
518 struct snd_pcm_hw_params *hw_params)
519{
520 struct oxygen *chip = snd_pcm_substream_chip(substream);
521 int err;
522
523 err = oxygen_hw_params(substream, hw_params);
524 if (err < 0)
525 return err;
526
527 spin_lock_irq(&chip->reg_lock);
528 oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
529 oxygen_format(hw_params) << OXYGEN_AC97_FORMAT_SHIFT,
530 OXYGEN_AC97_FORMAT_MASK);
531 spin_unlock_irq(&chip->reg_lock);
532 return 0;
533}
534
535static int oxygen_hw_free(struct snd_pcm_substream *substream) 518static int oxygen_hw_free(struct snd_pcm_substream *substream)
536{ 519{
537 struct oxygen *chip = snd_pcm_substream_chip(substream); 520 struct oxygen *chip = snd_pcm_substream_chip(substream);
@@ -680,7 +663,7 @@ static struct snd_pcm_ops oxygen_ac97_ops = {
680 .open = oxygen_ac97_open, 663 .open = oxygen_ac97_open,
681 .close = oxygen_close, 664 .close = oxygen_close,
682 .ioctl = snd_pcm_lib_ioctl, 665 .ioctl = snd_pcm_lib_ioctl,
683 .hw_params = oxygen_ac97_hw_params, 666 .hw_params = oxygen_hw_params,
684 .hw_free = oxygen_hw_free, 667 .hw_free = oxygen_hw_free,
685 .prepare = oxygen_prepare, 668 .prepare = oxygen_prepare,
686 .trigger = oxygen_trigger, 669 .trigger = oxygen_trigger,
diff --git a/sound/pci/oxygen/oxygen_regs.h b/sound/pci/oxygen/oxygen_regs.h
index b3491f73c598..530f1486f901 100644
--- a/sound/pci/oxygen/oxygen_regs.h
+++ b/sound/pci/oxygen/oxygen_regs.h
@@ -23,8 +23,8 @@
23 23
24/* multichannel playback channel */ 24/* multichannel playback channel */
25#define OXYGEN_DMA_MULTICH_ADDRESS 0x20 25#define OXYGEN_DMA_MULTICH_ADDRESS 0x20
26#define OXYGEN_DMA_MULTICH_COUNT 0x24 /* 32 bits */ 26#define OXYGEN_DMA_MULTICH_COUNT 0x24 /* 24 bits */
27#define OXYGEN_DMA_MULTICH_TCOUNT 0x28 /* 32 bits */ 27#define OXYGEN_DMA_MULTICH_TCOUNT 0x28 /* 24 bits */
28 28
29/* AC'97 (front panel) playback channel */ 29/* AC'97 (front panel) playback channel */
30#define OXYGEN_DMA_AC97_ADDRESS 0x30 30#define OXYGEN_DMA_AC97_ADDRESS 0x30
@@ -41,6 +41,9 @@
41#define OXYGEN_CHANNEL_MULTICH 0x10 41#define OXYGEN_CHANNEL_MULTICH 0x10
42#define OXYGEN_CHANNEL_AC97 0x20 42#define OXYGEN_CHANNEL_AC97 0x20
43 43
44#define OXYGEN_DMA_PAUSE 0x41 /* 1 = pause */
45/* OXYGEN_CHANNEL_* */
46
44#define OXYGEN_DMA_RESET 0x42 47#define OXYGEN_DMA_RESET 0x42
45/* OXYGEN_CHANNEL_* */ 48/* OXYGEN_CHANNEL_* */
46 49
@@ -50,19 +53,37 @@
50#define OXYGEN_PLAY_CHANNELS_4 0x01 53#define OXYGEN_PLAY_CHANNELS_4 0x01
51#define OXYGEN_PLAY_CHANNELS_6 0x02 54#define OXYGEN_PLAY_CHANNELS_6 0x02
52#define OXYGEN_PLAY_CHANNELS_8 0x03 55#define OXYGEN_PLAY_CHANNELS_8 0x03
56#define OXYGEN_DMA_A_BURST_MASK 0x04
57#define OXYGEN_DMA_A_BURST_8 0x00 /* dwords */
58#define OXYGEN_DMA_A_BURST_16 0x04
59#define OXYGEN_DMA_MULTICH_BURST_MASK 0x08
60#define OXYGEN_DMA_MULTICH_BURST_8 0x00
61#define OXYGEN_DMA_MULTICH_BURST_16 0x08
53 62
54#define OXYGEN_INTERRUPT_MASK 0x44 63#define OXYGEN_INTERRUPT_MASK 0x44
55/* OXYGEN_CHANNEL_* */ 64/* OXYGEN_CHANNEL_* */
56#define OXYGEN_INT_SPDIF_IN_CHANGE 0x0100 65#define OXYGEN_INT_SPDIF_IN_DETECT 0x0100
66#define OXYGEN_INT_MCU 0x0200
67#define OXYGEN_INT_2WIRE 0x0400
57#define OXYGEN_INT_GPIO 0x0800 68#define OXYGEN_INT_GPIO 0x0800
69#define OXYGEN_INT_MCB 0x2000
70#define OXYGEN_INT_AC97 0x4000
58 71
59#define OXYGEN_INTERRUPT_STATUS 0x46 72#define OXYGEN_INTERRUPT_STATUS 0x46
60/* OXYGEN_CHANNEL_* amd OXYGEN_INT_* */ 73/* OXYGEN_CHANNEL_* amd OXYGEN_INT_* */
61#define OXYGEN_INT_MIDI 0x1000 74#define OXYGEN_INT_MIDI 0x1000
62 75
63#define OXYGEN_MISC 0x48 76#define OXYGEN_MISC 0x48
64#define OXYGEN_MISC_MAGIC 0x20 77#define OXYGEN_MISC_WRITE_PCI_SUBID 0x01
78#define OXYGEN_MISC_LATENCY_3F 0x02
79#define OXYGEN_MISC_REC_C_FROM_SPDIF 0x04
80#define OXYGEN_MISC_REC_B_FROM_AC97 0x08
81#define OXYGEN_MISC_REC_A_FROM_MULTICH 0x10
82#define OXYGEN_MISC_PCI_MEM_W_1_CLOCK 0x20
65#define OXYGEN_MISC_MIDI 0x40 83#define OXYGEN_MISC_MIDI 0x40
84#define OXYGEN_MISC_CRYSTAL_MASK 0x80
85#define OXYGEN_MISC_CRYSTAL_24576 0x00
86#define OXYGEN_MISC_CRYSTAL_27 0x80 /* MHz */
66 87
67#define OXYGEN_REC_FORMAT 0x4a 88#define OXYGEN_REC_FORMAT 0x4a
68#define OXYGEN_REC_FORMAT_A_MASK 0x03 89#define OXYGEN_REC_FORMAT_A_MASK 0x03
@@ -80,23 +101,32 @@
80#define OXYGEN_SPDIF_FORMAT_SHIFT 0 101#define OXYGEN_SPDIF_FORMAT_SHIFT 0
81#define OXYGEN_MULTICH_FORMAT_MASK 0x0c 102#define OXYGEN_MULTICH_FORMAT_MASK 0x0c
82#define OXYGEN_MULTICH_FORMAT_SHIFT 2 103#define OXYGEN_MULTICH_FORMAT_SHIFT 2
83#define OXYGEN_AC97_FORMAT_MASK 0x30
84#define OXYGEN_AC97_FORMAT_SHIFT 4
85/* OXYGEN_FORMAT_* */ 104/* OXYGEN_FORMAT_* */
86 105
87#define OXYGEN_REC_CHANNELS 0x4c 106#define OXYGEN_REC_CHANNELS 0x4c
88#define OXYGEN_REC_A_CHANNELS_MASK 0x07 107#define OXYGEN_REC_CHANNELS_MASK 0x07
89#define OXYGEN_REC_CHANNELS_2 0x00 108#define OXYGEN_REC_CHANNELS_2_2_2 0x00 /* DMA A, B, C */
90#define OXYGEN_REC_CHANNELS_4 0x01 109#define OXYGEN_REC_CHANNELS_4_2_2 0x01
91#define OXYGEN_REC_CHANNELS_6 0x03 /* or 0x02 */ 110#define OXYGEN_REC_CHANNELS_6_0_2 0x02
92#define OXYGEN_REC_CHANNELS_8 0x04 111#define OXYGEN_REC_CHANNELS_6_2_0 0x03
112#define OXYGEN_REC_CHANNELS_8_0_0 0x04
93 113
94#define OXYGEN_FUNCTION 0x50 114#define OXYGEN_FUNCTION 0x50
115#define OXYGEN_FUNCTION_CLOCK_MASK 0x01
116#define OXYGEN_FUNCTION_CLOCK_PLL 0x00
117#define OXYGEN_FUNCTION_CLOCK_CRYSTAL 0x01
95#define OXYGEN_FUNCTION_RESET_CODEC 0x02 118#define OXYGEN_FUNCTION_RESET_CODEC 0x02
96#define OXYGEN_FUNCTION_ENABLE_SPI_4_5 0x80 119#define OXYGEN_FUNCTION_RESET_POL 0x04
120#define OXYGEN_FUNCTION_PWDN 0x08
121#define OXYGEN_FUNCTION_PWDN_EN 0x10
122#define OXYGEN_FUNCTION_PWDN_POL 0x20
123#define OXYGEN_FUNCTION_2WIRE_SPI_MASK 0x40
124#define OXYGEN_FUNCTION_SPI 0x00
125#define OXYGEN_FUNCTION_2WIRE 0x40
126#define OXYGEN_FUNCTION_ENABLE_SPI_4_5 0x80 /* 0 = EEPROM */
97 127
98#define OXYGEN_I2S_MULTICH_FORMAT 0x60 128#define OXYGEN_I2S_MULTICH_FORMAT 0x60
99#define OXYGEN_I2S_RATE_MASK 0x0007 129#define OXYGEN_I2S_RATE_MASK 0x0007 /* LRCK */
100#define OXYGEN_RATE_32000 0x0000 130#define OXYGEN_RATE_32000 0x0000
101#define OXYGEN_RATE_44100 0x0001 131#define OXYGEN_RATE_44100 0x0001
102#define OXYGEN_RATE_48000 0x0002 132#define OXYGEN_RATE_48000 0x0002
@@ -108,12 +138,21 @@
108#define OXYGEN_I2S_FORMAT_MASK 0x0008 138#define OXYGEN_I2S_FORMAT_MASK 0x0008
109#define OXYGEN_I2S_FORMAT_I2S 0x0000 139#define OXYGEN_I2S_FORMAT_I2S 0x0000
110#define OXYGEN_I2S_FORMAT_LJUST 0x0008 140#define OXYGEN_I2S_FORMAT_LJUST 0x0008
111#define OXYGEN_I2S_MAGIC2_MASK 0x0030 141#define OXYGEN_I2S_MCLK_MASK 0x0030 /* MCLK/LRCK */
142#define OXYGEN_I2S_MCLK_128 0x0000
143#define OXYGEN_I2S_MCLK_256 0x0010
144#define OXYGEN_I2S_MCLK_512 0x0020
112#define OXYGEN_I2S_BITS_MASK 0x00c0 145#define OXYGEN_I2S_BITS_MASK 0x00c0
113#define OXYGEN_I2S_BITS_16 0x0000 146#define OXYGEN_I2S_BITS_16 0x0000
114#define OXYGEN_I2S_BITS_20 0x0040 147#define OXYGEN_I2S_BITS_20 0x0040
115#define OXYGEN_I2S_BITS_24 0x0080 148#define OXYGEN_I2S_BITS_24 0x0080
116#define OXYGEN_I2S_BITS_32 0x00c0 149#define OXYGEN_I2S_BITS_32 0x00c0
150#define OXYGEN_I2S_MASTER 0x0100
151#define OXYGEN_I2S_BCLK_MASK 0x0600 /* BCLK/LRCK */
152#define OXYGEN_I2S_BCLK_64 0x0000
153#define OXYGEN_I2S_BCLK_128 0x0200
154#define OXYGEN_I2S_BCLK_256 0x0400
155#define OXYGEN_I2S_MUTE_MCLK 0x0800
117 156
118#define OXYGEN_I2S_A_FORMAT 0x62 157#define OXYGEN_I2S_A_FORMAT 0x62
119#define OXYGEN_I2S_B_FORMAT 0x64 158#define OXYGEN_I2S_B_FORMAT 0x64
@@ -122,12 +161,21 @@
122 161
123#define OXYGEN_SPDIF_CONTROL 0x70 162#define OXYGEN_SPDIF_CONTROL 0x70
124#define OXYGEN_SPDIF_OUT_ENABLE 0x00000002 163#define OXYGEN_SPDIF_OUT_ENABLE 0x00000002
125#define OXYGEN_SPDIF_LOOPBACK 0x00000004 164#define OXYGEN_SPDIF_LOOPBACK 0x00000004 /* in to out */
126#define OXYGEN_SPDIF_MAGIC2 0x00000020 165#define OXYGEN_SPDIF_SENSE_MASK 0x00000008
127#define OXYGEN_SPDIF_MAGIC3 0x00000040 166#define OXYGEN_SPDIF_LOCK_MASK 0x00000010
128#define OXYGEN_SPDIF_IN_VALID 0x00001000 167#define OXYGEN_SPDIF_RATE_MASK 0x00000020
129#define OXYGEN_SPDIF_IN_CHANGE 0x00008000 /* r/wc */ 168#define OXYGEN_SPDIF_SPDVALID 0x00000040
130#define OXYGEN_SPDIF_IN_INVERT 0x00010000 /* ? */ 169#define OXYGEN_SPDIF_SENSE_PAR 0x00000200
170#define OXYGEN_SPDIF_LOCK_PAR 0x00000400
171#define OXYGEN_SPDIF_SENSE_STATUS 0x00000800
172#define OXYGEN_SPDIF_LOCK_STATUS 0x00001000
173#define OXYGEN_SPDIF_SENSE_INT 0x00002000 /* r/wc */
174#define OXYGEN_SPDIF_LOCK_INT 0x00004000 /* r/wc */
175#define OXYGEN_SPDIF_RATE_INT 0x00008000 /* r/wc */
176#define OXYGEN_SPDIF_IN_CLOCK_MASK 0x00010000
177#define OXYGEN_SPDIF_IN_CLOCK_96 0x00000000 /* <= 96 kHz */
178#define OXYGEN_SPDIF_IN_CLOCK_192 0x00010000 /* > 96 kHz */
131#define OXYGEN_SPDIF_OUT_RATE_MASK 0x07000000 179#define OXYGEN_SPDIF_OUT_RATE_MASK 0x07000000
132#define OXYGEN_SPDIF_OUT_RATE_SHIFT 24 180#define OXYGEN_SPDIF_OUT_RATE_SHIFT 24
133/* OXYGEN_RATE_* << OXYGEN_SPDIF_OUT_RATE_SHIFT */ 181/* OXYGEN_RATE_* << OXYGEN_SPDIF_OUT_RATE_SHIFT */
@@ -146,10 +194,22 @@
146#define OXYGEN_SPDIF_INPUT_BITS 0x78 194#define OXYGEN_SPDIF_INPUT_BITS 0x78
147/* 32 bits, IEC958_AES_* */ 195/* 32 bits, IEC958_AES_* */
148 196
197#define OXYGEN_EEPROM_CONTROL 0x80
198#define OXYGEN_EEPROM_ADDRESS_MASK 0x7f
199#define OXYGEN_EEPROM_DIR_MASK 0x80
200#define OXYGEN_EEPROM_DIR_READ 0x00
201#define OXYGEN_EEPROM_DIR_WRITE 0x80
202
203#define OXYGEN_EEPROM_STATUS 0x81
204#define OXYGEN_EEPROM_VALID 0x40
205#define OXYGEN_EEPROM_BUSY 0x80
206
207#define OXYGEN_EEPROM_DATA 0x82 /* 16 bits */
208
149#define OXYGEN_2WIRE_CONTROL 0x90 209#define OXYGEN_2WIRE_CONTROL 0x90
150#define OXYGEN_2WIRE_DIR_MASK 0x01 210#define OXYGEN_2WIRE_DIR_MASK 0x01
151#define OXYGEN_2WIRE_DIR_WRITE 0x00 /* ? */ 211#define OXYGEN_2WIRE_DIR_WRITE 0x00
152#define OXYGEN_2WIRE_DIR_READ 0x01 /* ? */ 212#define OXYGEN_2WIRE_DIR_READ 0x01
153#define OXYGEN_2WIRE_ADDRESS_MASK 0xfe /* slave device address */ 213#define OXYGEN_2WIRE_ADDRESS_MASK 0xfe /* slave device address */
154#define OXYGEN_2WIRE_ADDRESS_SHIFT 1 214#define OXYGEN_2WIRE_ADDRESS_SHIFT 1
155 215
@@ -157,17 +217,37 @@
157#define OXYGEN_2WIRE_DATA 0x92 /* data, 16 bits */ 217#define OXYGEN_2WIRE_DATA 0x92 /* data, 16 bits */
158 218
159#define OXYGEN_2WIRE_BUS_STATUS 0x94 219#define OXYGEN_2WIRE_BUS_STATUS 0x94
160#define OXYGEN_2WIRE_BUSY 0x01 220#define OXYGEN_2WIRE_BUSY 0x0001
221#define OXYGEN_2WIRE_LENGTH_MASK 0x0002
222#define OXYGEN_2WIRE_LENGTH_8 0x0000
223#define OXYGEN_2WIRE_LENGTH_16 0x0002
224#define OXYGEN_2WIRE_MANUAL_READ 0x0004 /* 0 = auto read */
225#define OXYGEN_2WIRE_WRITE_MAP_ONLY 0x0008
226#define OXYGEN_2WIRE_SLAVE_AD_MASK 0x0030 /* AD0, AD1 */
227#define OXYGEN_2WIRE_INTERRUPT_MASK 0x0040 /* 0 = int. if not responding */
228#define OXYGEN_2WIRE_SLAVE_NO_RESPONSE 0x0080
229#define OXYGEN_2WIRE_SPEED_MASK 0x0100
230#define OXYGEN_2WIRE_SPEED_STANDARD 0x0000
231#define OXYGEN_2WIRE_SPEED_FAST 0x0100
232#define OXYGEN_2WIRE_CLOCK_SYNC 0x0200
233#define OXYGEN_2WIRE_BUS_RESET 0x0400
161 234
162#define OXYGEN_SPI_CONTROL 0x98 235#define OXYGEN_SPI_CONTROL 0x98
163#define OXYGEN_SPI_BUSY 0x01 /* read */ 236#define OXYGEN_SPI_BUSY 0x01 /* read */
164#define OXYGEN_SPI_TRIGGER_WRITE 0x01 /* write */ 237#define OXYGEN_SPI_TRIGGER 0x01 /* write */
165#define OXYGEN_SPI_DATA_LENGTH_MASK 0x02 238#define OXYGEN_SPI_DATA_LENGTH_MASK 0x02
166#define OXYGEN_SPI_DATA_LENGTH_2 0x00 239#define OXYGEN_SPI_DATA_LENGTH_2 0x00
167#define OXYGEN_SPI_DATA_LENGTH_3 0x02 240#define OXYGEN_SPI_DATA_LENGTH_3 0x02
241#define OXYGEN_SPI_CLOCK_MASK 0xc0
242#define OXYGEN_SPI_CLOCK_160 0x00 /* ns */
243#define OXYGEN_SPI_CLOCK_320 0x40
244#define OXYGEN_SPI_CLOCK_640 0x80
245#define OXYGEN_SPI_CLOCK_1280 0xc0
168#define OXYGEN_SPI_CODEC_MASK 0x70 /* 0..5 */ 246#define OXYGEN_SPI_CODEC_MASK 0x70 /* 0..5 */
169#define OXYGEN_SPI_CODEC_SHIFT 4 247#define OXYGEN_SPI_CODEC_SHIFT 4
170#define OXYGEN_SPI_MAGIC 0x80 248#define OXYGEN_SPI_CEN_MASK 0x80
249#define OXYGEN_SPI_CEN_LATCH_CLOCK_LO 0x00
250#define OXYGEN_SPI_CEN_LATCH_CLOCK_HI 0x80
171 251
172#define OXYGEN_SPI_DATA1 0x99 252#define OXYGEN_SPI_DATA1 0x99
173#define OXYGEN_SPI_DATA2 0x9a 253#define OXYGEN_SPI_DATA2 0x9a
@@ -175,56 +255,161 @@
175 255
176#define OXYGEN_MPU401 0xa0 256#define OXYGEN_MPU401 0xa0
177 257
258#define OXYGEN_MPU401_CONTROL 0xa2
259#define OXYGEN_MPU401_LOOPBACK 0x01 /* TXD to RXD */
260
178#define OXYGEN_GPI_DATA 0xa4 261#define OXYGEN_GPI_DATA 0xa4
262/* bits 0..5 = pin XGPI0..XGPI5 */
179 263
180#define OXYGEN_GPI_INTERRUPT_MASK 0xa5 264#define OXYGEN_GPI_INTERRUPT_MASK 0xa5
265/* bits 0..5, 1 = enable */
181 266
182#define OXYGEN_GPIO_DATA 0xa6 267#define OXYGEN_GPIO_DATA 0xa6
268/* bits 0..9 */
183 269
184#define OXYGEN_GPIO_CONTROL 0xa8 270#define OXYGEN_GPIO_CONTROL 0xa8
185/* 0: input, 1: output */ 271/* bits 0..9, 0 = input, 1 = output */
272#define OXYGEN_GPIO1_XSLAVE_RDY 0x8000
186 273
187#define OXYGEN_GPIO_INTERRUPT_MASK 0xaa 274#define OXYGEN_GPIO_INTERRUPT_MASK 0xaa
188 275/* bits 0..9, 1 = enable */
189#define OXYGEN_DEVICE_SENSE 0xac /* ? */ 276
277#define OXYGEN_DEVICE_SENSE 0xac
278#define OXYGEN_HEAD_PHONE_DETECT 0x01
279#define OXYGEN_HEAD_PHONE_MASK 0x06
280#define OXYGEN_HEAD_PHONE_PASSIVE_SPK 0x00
281#define OXYGEN_HEAD_PHONE_HP 0x02
282#define OXYGEN_HEAD_PHONE_ACTIVE_SPK 0x04
283
284#define OXYGEN_MCU_2WIRE_DATA 0xb0
285
286#define OXYGEN_MCU_2WIRE_MAP 0xb2
287
288#define OXYGEN_MCU_2WIRE_STATUS 0xb3
289#define OXYGEN_MCU_2WIRE_BUSY 0x01
290#define OXYGEN_MCU_2WIRE_LENGTH_MASK 0x06
291#define OXYGEN_MCU_2WIRE_LENGTH_1 0x00
292#define OXYGEN_MCU_2WIRE_LENGTH_2 0x02
293#define OXYGEN_MCU_2WIRE_LENGTH_3 0x04
294#define OXYGEN_MCU_2WIRE_WRITE 0x08 /* r/wc */
295#define OXYGEN_MCU_2WIRE_READ 0x10 /* r/wc */
296#define OXYGEN_MCU_2WIRE_DRV_XACT_FAIL 0x20 /* r/wc */
297#define OXYGEN_MCU_2WIRE_RESET 0x40
298
299#define OXYGEN_MCU_2WIRE_CONTROL 0xb4
300#define OXYGEN_MCU_2WIRE_DRV_ACK 0x01
301#define OXYGEN_MCU_2WIRE_DRV_XACT 0x02
302#define OXYGEN_MCU_2WIRE_INT_MASK 0x04
303#define OXYGEN_MCU_2WIRE_SYNC_MASK 0x08
304#define OXYGEN_MCU_2WIRE_SYNC_RDY_PIN 0x00
305#define OXYGEN_MCU_2WIRE_SYNC_DATA 0x08
306#define OXYGEN_MCU_2WIRE_ADDRESS_MASK 0x30
307#define OXYGEN_MCU_2WIRE_ADDRESS_10 0x00
308#define OXYGEN_MCU_2WIRE_ADDRESS_12 0x10
309#define OXYGEN_MCU_2WIRE_ADDRESS_14 0x20
310#define OXYGEN_MCU_2WIRE_ADDRESS_16 0x30
311#define OXYGEN_MCU_2WIRE_INT_POL 0x40
312#define OXYGEN_MCU_2WIRE_SYNC_ENABLE 0x80
190 313
191#define OXYGEN_PLAY_ROUTING 0xc0 314#define OXYGEN_PLAY_ROUTING 0xc0
315#define OXYGEN_PLAY_MUTE01 0x0001
316#define OXYGEN_PLAY_MUTE23 0x0002
317#define OXYGEN_PLAY_MUTE45 0x0004
318#define OXYGEN_PLAY_MUTE67 0x0008
319#define OXYGEN_PLAY_MULTICH_MASK 0x0010
320#define OXYGEN_PLAY_MULTICH_I2S_DAC 0x0000
321#define OXYGEN_PLAY_MULTICH_AC97 0x0010
322#define OXYGEN_PLAY_SPDIF_MASK 0x00e0
323#define OXYGEN_PLAY_SPDIF_SPDIF 0x0000
324#define OXYGEN_PLAY_SPDIF_MULTICH_01 0x0020
325#define OXYGEN_PLAY_SPDIF_MULTICH_23 0x0040
326#define OXYGEN_PLAY_SPDIF_MULTICH_45 0x0060
327#define OXYGEN_PLAY_SPDIF_MULTICH_67 0x0080
328#define OXYGEN_PLAY_SPDIF_REC_A 0x00a0
329#define OXYGEN_PLAY_SPDIF_REC_B 0x00c0
330#define OXYGEN_PLAY_SPDIF_I2S_ADC_3 0x00e0
192#define OXYGEN_PLAY_DAC0_SOURCE_MASK 0x0300 331#define OXYGEN_PLAY_DAC0_SOURCE_MASK 0x0300
332#define OXYGEN_PLAY_DAC0_SOURCE_SHIFT 8
193#define OXYGEN_PLAY_DAC1_SOURCE_MASK 0x0700 333#define OXYGEN_PLAY_DAC1_SOURCE_MASK 0x0700
334#define OXYGEN_PLAY_DAC1_SOURCE_SHIFT 10
194#define OXYGEN_PLAY_DAC2_SOURCE_MASK 0x3000 335#define OXYGEN_PLAY_DAC2_SOURCE_MASK 0x3000
336#define OXYGEN_PLAY_DAC2_SOURCE_SHIFT 12
195#define OXYGEN_PLAY_DAC3_SOURCE_MASK 0x7000 337#define OXYGEN_PLAY_DAC3_SOURCE_MASK 0x7000
338#define OXYGEN_PLAY_DAC3_SOURCE_SHIFT 14
196 339
197#define OXYGEN_REC_ROUTING 0xc2 340#define OXYGEN_REC_ROUTING 0xc2
341#define OXYGEN_MUTE_I2S_ADC_1 0x01
342#define OXYGEN_MUTE_I2S_ADC_2 0x02
343#define OXYGEN_MUTE_I2S_ADC_3 0x04
344#define OXYGEN_REC_A_ROUTE_MASK 0x08
345#define OXYGEN_REC_A_ROUTE_I2S_ADC_1 0x00
346#define OXYGEN_REC_A_ROUTE_AC97_0 0x08
347#define OXYGEN_REC_B_ROUTE_MASK 0x10
348#define OXYGEN_REC_B_ROUTE_I2S_ADC_2 0x00
349#define OXYGEN_REC_B_ROUTE_AC97_1 0x10
350#define OXYGEN_REC_C_ROUTE_MASK 0x20
351#define OXYGEN_REC_C_ROUTE_SPDIF 0x00
352#define OXYGEN_REC_C_ROUTE_I2S_ADC_3 0x20
198 353
199#define OXYGEN_ADC_MONITOR 0xc3 354#define OXYGEN_ADC_MONITOR 0xc3
200#define OXYGEN_ADC_MONITOR_MULTICH 0x01 355#define OXYGEN_ADC_MONITOR_A 0x01
201#define OXYGEN_ADC_MONITOR_AC97 0x04 356#define OXYGEN_ADC_MONITOR_A_HALF_VOL 0x02
202#define OXYGEN_ADC_MONITOR_SPDIF 0x10 357#define OXYGEN_ADC_MONITOR_B 0x04
358#define OXYGEN_ADC_MONITOR_B_HALF_VOL 0x08
359#define OXYGEN_ADC_MONITOR_C 0x10
360#define OXYGEN_ADC_MONITOR_C_HALF_VOL 0x20
203 361
204#define OXYGEN_A_MONITOR_ROUTING 0xc4 362#define OXYGEN_A_MONITOR_ROUTING 0xc4
363#define OXYGEN_A_MONITOR_ROUTE_01_MASK 0x03
364#define OXYGEN_A_MONITOR_ROUTE_23_MASK 0x0c
365#define OXYGEN_A_MONITOR_ROUTE_45_MASK 0x30
366#define OXYGEN_A_MONITOR_ROUTE_67_MASK 0xc0
205 367
206#define OXYGEN_AC97_CONTROL 0xd0 368#define OXYGEN_AC97_CONTROL 0xd0
207#define OXYGEN_AC97_RESET1 0x0001 369#define OXYGEN_AC97_COLD_RESET 0x0001
208#define OXYGEN_AC97_RESET1_BUSY 0x0002 370#define OXYGEN_AC97_SUSPENDED 0x0002 /* read */
209#define OXYGEN_AC97_RESET2 0x0008 371#define OXYGEN_AC97_RESUME 0x0002 /* write */
372#define OXYGEN_AC97_CLOCK_DISABLE 0x0004
373#define OXYGEN_AC97_NO_CODEC_0 0x0008
210#define OXYGEN_AC97_CODEC_0 0x0010 374#define OXYGEN_AC97_CODEC_0 0x0010
211#define OXYGEN_AC97_CODEC_1 0x0020 375#define OXYGEN_AC97_CODEC_1 0x0020
212 376
213#define OXYGEN_AC97_INTERRUPT_MASK 0xd2 377#define OXYGEN_AC97_INTERRUPT_MASK 0xd2
378#define OXYGEN_AC97_INT_READ_DONE 0x01
379#define OXYGEN_AC97_INT_WRITE_DONE 0x02
380#define OXYGEN_AC97_INT_CODEC_0 0x10
381#define OXYGEN_AC97_INT_CODEC_1 0x20
214 382
215#define OXYGEN_AC97_INTERRUPT_STATUS 0xd3 383#define OXYGEN_AC97_INTERRUPT_STATUS 0xd3
216#define OXYGEN_AC97_READ_COMPLETE 0x01 384/* OXYGEN_AC97_INT_* */
217#define OXYGEN_AC97_WRITE_COMPLETE 0x02
218 385
219#define OXYGEN_AC97_OUT_CONFIG 0xd4 386#define OXYGEN_AC97_OUT_CONFIG 0xd4
220#define OXYGEN_AC97_OUT_MAGIC1 0x00000011 387#define OXYGEN_AC97_CODEC1_SLOT3 0x00000001
221#define OXYGEN_AC97_OUT_MAGIC2 0x00000033 388#define OXYGEN_AC97_CODEC1_SLOT3_VSR 0x00000002
222#define OXYGEN_AC97_OUT_MAGIC3 0x0000ff00 389#define OXYGEN_AC97_CODEC1_SLOT4 0x00000010
390#define OXYGEN_AC97_CODEC1_SLOT4_VSR 0x00000020
391#define OXYGEN_AC97_CODEC0_FRONTL 0x00000100
392#define OXYGEN_AC97_CODEC0_FRONTR 0x00000200
393#define OXYGEN_AC97_CODEC0_SIDEL 0x00000400
394#define OXYGEN_AC97_CODEC0_SIDER 0x00000800
395#define OXYGEN_AC97_CODEC0_CENTER 0x00001000
396#define OXYGEN_AC97_CODEC0_BASE 0x00002000
397#define OXYGEN_AC97_CODEC0_REARL 0x00004000
398#define OXYGEN_AC97_CODEC0_REARR 0x00008000
223 399
224#define OXYGEN_AC97_IN_CONFIG 0xd8 400#define OXYGEN_AC97_IN_CONFIG 0xd8
225#define OXYGEN_AC97_IN_MAGIC1 0x00000011 401#define OXYGEN_AC97_CODEC1_LINEL 0x00000001
226#define OXYGEN_AC97_IN_MAGIC2 0x00000033 402#define OXYGEN_AC97_CODEC1_LINEL_VSR 0x00000002
227#define OXYGEN_AC97_IN_MAGIC3 0x00000300 403#define OXYGEN_AC97_CODEC1_LINEL_16 0x00000000
404#define OXYGEN_AC97_CODEC1_LINEL_18 0x00000004
405#define OXYGEN_AC97_CODEC1_LINEL_20 0x00000008
406#define OXYGEN_AC97_CODEC1_LINER 0x00000010
407#define OXYGEN_AC97_CODEC1_LINER_VSR 0x00000020
408#define OXYGEN_AC97_CODEC1_LINER_16 0x00000000
409#define OXYGEN_AC97_CODEC1_LINER_18 0x00000040
410#define OXYGEN_AC97_CODEC1_LINER_20 0x00000080
411#define OXYGEN_AC97_CODEC0_LINEL 0x00000100
412#define OXYGEN_AC97_CODEC0_LINER 0x00000200
228 413
229#define OXYGEN_AC97_REGS 0xdc 414#define OXYGEN_AC97_REGS 0xdc
230#define OXYGEN_AC97_REG_DATA_MASK 0x0000ffff 415#define OXYGEN_AC97_REG_DATA_MASK 0x0000ffff
@@ -236,13 +421,29 @@
236#define OXYGEN_AC97_REG_CODEC_MASK 0x01000000 421#define OXYGEN_AC97_REG_CODEC_MASK 0x01000000
237#define OXYGEN_AC97_REG_CODEC_SHIFT 24 422#define OXYGEN_AC97_REG_CODEC_SHIFT 24
238 423
424#define OXYGEN_TEST 0xe0
425#define OXYGEN_TEST_RAM_SUCCEEDED 0x01
426#define OXYGEN_TEST_PLAYBACK_RAM 0x02
427#define OXYGEN_TEST_RECORD_RAM 0x04
428#define OXYGEN_TEST_PLL 0x08
429#define OXYGEN_TEST_2WIRE_LOOPBACK 0x10
430
239#define OXYGEN_DMA_FLUSH 0xe1 431#define OXYGEN_DMA_FLUSH 0xe1
240/* OXYGEN_CHANNEL_* */ 432/* OXYGEN_CHANNEL_* */
241 433
242#define OXYGEN_CODEC_VERSION 0xe4 434#define OXYGEN_CODEC_VERSION 0xe4
435#define OXYGEN_XCID_MASK 0x07
243 436
244#define OXYGEN_REVISION 0xe6 437#define OXYGEN_REVISION 0xe6
245#define OXYGEN_REVISION_2 0x08 /* bit flag */ 438#define OXYGEN_REVISION_XPKGID_MASK 0x0007
246#define OXYGEN_REVISION_8787 0x14 /* all 8 bits */ 439#define OXYGEN_REVISION_MASK 0xfff8
440#define OXYGEN_REVISION_2 0x0008 /* bit flag */
441#define OXYGEN_REVISION_8787 0x0014 /* 8 bits */
442
443#define OXYGEN_OFFSIN_48K 0xe8
444#define OXYGEN_OFFSBASE_48K 0xe9
445#define OXYGEN_OFFSBASE_MASK 0x0fff
446#define OXYGEN_OFFSIN_44K 0xec
447#define OXYGEN_OFFSBASE_44K 0xed
247 448
248#endif 449#endif
diff --git a/sound/pci/oxygen/virtuoso.c b/sound/pci/oxygen/virtuoso.c
index 83c2c43e7b85..1a0367b7ae35 100644
--- a/sound/pci/oxygen/virtuoso.c
+++ b/sound/pci/oxygen/virtuoso.c
@@ -80,10 +80,11 @@ static void pcm1796_write(struct oxygen *chip, unsigned int codec,
80 static const u8 codec_map[4] = { 80 static const u8 codec_map[4] = {
81 0, 1, 2, 4 81 0, 1, 2, 4
82 }; 82 };
83 oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER_WRITE | 83 oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
84 OXYGEN_SPI_DATA_LENGTH_2 | 84 OXYGEN_SPI_DATA_LENGTH_2 |
85 OXYGEN_SPI_CLOCK_160 |
85 (codec_map[codec] << OXYGEN_SPI_CODEC_SHIFT) | 86 (codec_map[codec] << OXYGEN_SPI_CODEC_SHIFT) |
86 OXYGEN_SPI_MAGIC, 87 OXYGEN_SPI_CEN_LATCH_CLOCK_HI,
87 (reg << 8) | value); 88 (reg << 8) | value);
88} 89}
89 90
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 17:01:58 -0500