[ARM] Clean up save_and_disable_irqs macro and allow use of ARMv6 CPSID

save_and_disable_irqs does not need to use mov + msr (which was
introduced to work around a documentation bug which was propagated
into binutils.)  Use msr with an immediate constant, and if we're
building for ARMv6 or later, use the new CPSID instruction.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

2 files changed, 8 insertions, 5 deletions

diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h
index f35d91fbe117..b8c14e936697 100644
--- a/arch/arm/lib/bitops.h
+++ b/arch/arm/lib/bitops.h
@@ -34,7 +34,7 @@
         and     r2, r0, #7
         mov     r3, #1
         mov     r3, r3, lsl r2
-        save_and_disable_irqs ip, r2
+        save_and_disable_irqs ip
         ldrb    r2, [r1, r0, lsr #3]
         \instr  r2, r2, r3
         strb    r2, [r1, r0, lsr #3]
@@ -54,7 +54,7 @@
         add     r1, r1, r0, lsr #3
         and     r3, r0, #7
         mov     r0, #1
-        save_and_disable_irqs ip, r2
+        save_and_disable_irqs ip
         ldrb    r2, [r1]
         tst     r2, r0, lsl r3
         \instr  r2, r2, r0, lsl r3
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index 69a28f96bee2..f31ac92b6c7f 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -83,10 +83,13 @@
  * Save the current IRQ state and disable IRQs.  Note that this macro
  * assumes FIQs are enabled, and that the processor is in SVC mode.
  */
-        .macro  save_and_disable_irqs, oldcpsr, temp
+        .macro  save_and_disable_irqs, oldcpsr
         mrs     \oldcpsr, cpsr
-        mov     \temp, #PSR_I_BIT | MODE_SVC
-        msr     cpsr_c, \temp
+#if __LINUX_ARM_ARCH__ >= 6
+        cpsid   i
+#else
+        msr     cpsr_c, #PSR_I_BIT | MODE_SVC
+#endif
         .endm
 
 /*