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authorLinus Torvalds <torvalds@linux-foundation.org>2008-10-31 10:53:17 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-10-31 10:53:17 -0400
commit1fe01cb57c6272577ebb107a03253484f6dabe7c (patch)
tree11cd44b8bd5704589d477fbf2bb27d8f3fc17122
parent63b40456a30912084c90753582137b9e0495c5c3 (diff)
parent216813a8bb4db97eb7a6e75c533894430053df48 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (21 commits) sh: fix sh2a cache entry_mask sh: Enable NFS root in Migo-R defconfig. sh: FTRACE renamed to FUNCTION_TRACER. sh: Fix up the shared IRQ demuxer's control bit testing logic. Define SCSPTR1 for SH 7751R sh: Add sci_rxd_in of SH4-202 Add support usb setting on sh 7366 sh: Change register name SCSPTR to SCSPTR2 sh: use the new byteorder headers. sh: SHmedia ISA tuning fixups. sh: Kill off long-dead HD64465 cchip support. sh: Revert "SH 7366 needs SCIF_ONLY" sh: Simplify and lock down the ISA tuning. sh: sh7785lcr: Select uImage as default image target. sh: Add on-chip RTC support for SH7722. SH 7366 needs SCIF_ONLY gdrom: Fix compile error sh: Provide a sample defconfig for the UL2 (SH7366) board. sh: Fix FPU tuning on toolchains with mismatched multilib targets. sh: oprofile: Fix up the SH7750 performance counter name. ...
Diffstat
-rw-r--r--Documentation/sh/new-machine.txt4
-rw-r--r--arch/sh/Kconfig2
-rw-r--r--arch/sh/Makefile31
-rw-r--r--arch/sh/boot/compressed/Makefile_322
-rw-r--r--arch/sh/cchips/Kconfig33
-rw-r--r--arch/sh/cchips/hd6446x/Makefile1
-rw-r--r--arch/sh/cchips/hd6446x/hd64465/Makefile6
-rw-r--r--arch/sh/cchips/hd6446x/hd64465/gpio.c196
-rw-r--r--arch/sh/cchips/hd6446x/hd64465/io.c211
-rw-r--r--arch/sh/cchips/hd6446x/hd64465/setup.c181
-rw-r--r--arch/sh/configs/migor_defconfig35
-rw-r--r--arch/sh/configs/ul2_defconfig1169
-rw-r--r--arch/sh/include/asm/byteorder.h36
-rw-r--r--arch/sh/include/asm/hd64465/gpio.h46
-rw-r--r--arch/sh/include/asm/hd64465/hd64465.h256
-rw-r--r--arch/sh/include/asm/hd64465/io.h44
-rw-r--r--arch/sh/include/asm/serial.h17
-rw-r--r--arch/sh/include/cpu-sh4/cpu/rtc.h2
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c28
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c34
-rw-r--r--arch/sh/kernel/entry-common.S4
-rw-r--r--arch/sh/kernel/sh_ksyms_32.c13
-rw-r--r--arch/sh/mm/cache-sh2a.c8
-rw-r--r--arch/sh/oprofile/op_model_sh7750.c6
-rw-r--r--arch/sh/tools/mach-types1
-rw-r--r--drivers/cdrom/gdrom.c5
-rw-r--r--drivers/pcmcia/Kconfig4
-rw-r--r--drivers/pcmcia/Makefile1
-rw-r--r--drivers/pcmcia/hd64465_ss.c939
-rw-r--r--drivers/serial/sh-sci.c40
-rw-r--r--drivers/serial/sh-sci.h96
31 files changed, 1357 insertions, 2094 deletions
diff --git a/Documentation/sh/new-machine.txt b/Documentation/sh/new-machine.txt
index 5482bf5d005b..f0354164cb0e 100644
--- a/Documentation/sh/new-machine.txt
+++ b/Documentation/sh/new-machine.txt
@@ -47,9 +47,7 @@ Next, for companion chips:
47 `-- sh 47 `-- sh
48 `-- cchips 48 `-- cchips
49 `-- hd6446x 49 `-- hd6446x
50 |-- hd64461 50 `-- hd64461
51 | `-- cchip-specific files
52 `-- hd64465
53 `-- cchip-specific files 51 `-- cchip-specific files
54 52
55... and so on. Headers for the companion chips are treated the same way as 53... and so on. Headers for the companion chips are treated the same way as
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index cb2c87df70ce..80119b3398e7 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -24,7 +24,7 @@ config SUPERH32
24 select HAVE_KPROBES 24 select HAVE_KPROBES
25 select HAVE_KRETPROBES 25 select HAVE_KRETPROBES
26 select HAVE_ARCH_TRACEHOOK 26 select HAVE_ARCH_TRACEHOOK
27 select HAVE_FTRACE 27 select HAVE_FUNCTION_TRACER
28 28
29config SUPERH64 29config SUPERH64
30 def_bool y if CPU_SH5 30 def_bool y if CPU_SH5
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index 1f409bf81809..c43eb0d7fa3b 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -2,7 +2,7 @@
2# arch/sh/Makefile 2# arch/sh/Makefile
3# 3#
4# Copyright (C) 1999 Kaz Kojima 4# Copyright (C) 1999 Kaz Kojima
5# Copyright (C) 2002, 2003, 2004 Paul Mundt 5# Copyright (C) 2002 - 2008 Paul Mundt
6# Copyright (C) 2002 M. R. Brown 6# Copyright (C) 2002 M. R. Brown
7# 7#
8# This file is subject to the terms and conditions of the GNU General Public 8# This file is subject to the terms and conditions of the GNU General Public
@@ -18,16 +18,12 @@ isa-$(CONFIG_CPU_SH4) := sh4
18isa-$(CONFIG_CPU_SH4A) := sh4a 18isa-$(CONFIG_CPU_SH4A) := sh4a
19isa-$(CONFIG_CPU_SH4AL_DSP) := sh4al 19isa-$(CONFIG_CPU_SH4AL_DSP) := sh4al
20isa-$(CONFIG_CPU_SH5) := shmedia 20isa-$(CONFIG_CPU_SH5) := shmedia
21isa-$(CONFIG_SH_DSP) := $(isa-y)-dsp
22 21
23ifndef CONFIG_SH_DSP 22ifeq ($(CONFIG_SUPERH32),y)
24ifndef CONFIG_SH_FPU 23isa-$(CONFIG_SH_DSP) := $(isa-y)-dsp
25isa-y := $(isa-y)-nofpu 24isa-y := $(isa-y)-up
26endif
27endif 25endif
28 26
29isa-y := $(isa-y)-up
30
31cflags-$(CONFIG_CPU_SH2) := $(call cc-option,-m2,) 27cflags-$(CONFIG_CPU_SH2) := $(call cc-option,-m2,)
32cflags-$(CONFIG_CPU_SH2A) += $(call cc-option,-m2a,) \ 28cflags-$(CONFIG_CPU_SH2A) += $(call cc-option,-m2a,) \
33 $(call cc-option,-m2a-nofpu,) 29 $(call cc-option,-m2a-nofpu,)
@@ -38,6 +34,22 @@ cflags-$(CONFIG_CPU_SH4A) += $(call cc-option,-m4a,) \
38 $(call cc-option,-m4a-nofpu,) 34 $(call cc-option,-m4a-nofpu,)
39cflags-$(CONFIG_CPU_SH5) := $(call cc-option,-m5-32media-nofpu,) 35cflags-$(CONFIG_CPU_SH5) := $(call cc-option,-m5-32media-nofpu,)
40 36
37ifeq ($(cflags-y),)
38#
39# In the case where we are stuck with a compiler that has been uselessly
40# restricted to a particular ISA, a favourite default of newer GCCs when
41# extensive multilib targets are not provided, ensure we get the best fit
42# regarding FP generation. This is necessary to avoid references to FP
43# variants in libgcc where integer variants exist, which otherwise result
44# in link errors. This is intentionally stupid (albeit many orders of
45# magnitude less than GCC's default behaviour), as anything with a large
46# number of multilib targets better have been built correctly for
47# the target in mind.
48#
49cflags-y += $(shell $(CC) $(KBUILD_CFLAGS) -print-multi-lib | \
50 grep nofpu | sed q | sed -e 's/^/-/;s/;.*$$//')
51endif
52
41cflags-$(CONFIG_CPU_BIG_ENDIAN) += -mb 53cflags-$(CONFIG_CPU_BIG_ENDIAN) += -mb
42cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -ml 54cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -ml
43 55
@@ -65,7 +77,8 @@ OBJCOPYFLAGS := -O binary -R .note -R .note.gnu.build-id -R .comment \
65 -R .stab -R .stabstr -S 77 -R .stab -R .stabstr -S
66 78
67# Give the various platforms the opportunity to set default image types 79# Give the various platforms the opportunity to set default image types
68defaultimage-$(CONFIG_SUPERH32) := zImage 80defaultimage-$(CONFIG_SUPERH32) := zImage
81defaultimage-$(CONFIG_SH_SH7785LCR) := uImage
69 82
70# Set some sensible Kbuild defaults 83# Set some sensible Kbuild defaults
71KBUILD_DEFCONFIG := shx3_defconfig 84KBUILD_DEFCONFIG := shx3_defconfig
diff --git a/arch/sh/boot/compressed/Makefile_32 b/arch/sh/boot/compressed/Makefile_32
index 301e6d503256..b96a055b053e 100644
--- a/arch/sh/boot/compressed/Makefile_32
+++ b/arch/sh/boot/compressed/Makefile_32
@@ -23,7 +23,7 @@ IMAGE_OFFSET := $(shell /bin/bash -c 'printf "0x%08x" \
23 23
24LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name) 24LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
25 25
26ifeq ($(CONFIG_FTRACE),y) 26ifeq ($(CONFIG_FUNCTION_TRACER),y)
27ORIG_CFLAGS := $(KBUILD_CFLAGS) 27ORIG_CFLAGS := $(KBUILD_CFLAGS)
28KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) 28KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
29endif 29endif
diff --git a/arch/sh/cchips/Kconfig b/arch/sh/cchips/Kconfig
index 7892361eedc8..f43d18373f22 100644
--- a/arch/sh/cchips/Kconfig
+++ b/arch/sh/cchips/Kconfig
@@ -22,20 +22,6 @@ config HD64461
22 Say Y if you want support for the HD64461. 22 Say Y if you want support for the HD64461.
23 Otherwise, say N. 23 Otherwise, say N.
24 24
25config HD64465
26 bool "Hitachi HD64465 companion chip support"
27 ---help---
28 The Hitachi HD64465 provides an interface for
29 the SH7750 CPU, supporting a LCD controller,
30 CRT color controller, IrDA, USB, PCMCIA,
31 keyboard controller, and a printer interface.
32
33 More information is available at
34 <http://global.hitachi.com/New/cnews/E/1998/981019B.html>.
35
36 Say Y if you want support for the HD64465.
37 Otherwise, say N.
38
39endchoice 25endchoice
40 26
41# These will also be split into the Kconfig's below 27# These will also be split into the Kconfig's below
@@ -61,23 +47,4 @@ config HD64461_ENABLER
61 via the HD64461 companion chip. 47 via the HD64461 companion chip.
62 Otherwise, say N. 48 Otherwise, say N.
63 49
64config HD64465_IOBASE
65 hex "HD64465 start address"
66 depends on HD64465
67 default "0xb0000000"
68 help
69 The default setting of the HD64465 IO base address is 0xb0000000.
70
71 Do not change this unless you know what you are doing.
72
73config HD64465_IRQ
74 int "HD64465 IRQ"
75 depends on HD64465
76 default "5"
77 help
78 The default setting of the HD64465 IRQ is 5.
79
80 Do not change this unless you know what you are doing.
81
82endmenu 50endmenu
83
diff --git a/arch/sh/cchips/hd6446x/Makefile b/arch/sh/cchips/hd6446x/Makefile
index f7de4076e242..9682e3ab668f 100644
--- a/arch/sh/cchips/hd6446x/Makefile
+++ b/arch/sh/cchips/hd6446x/Makefile
@@ -1,4 +1,3 @@
1obj-$(CONFIG_HD64461) += hd64461.o 1obj-$(CONFIG_HD64461) += hd64461.o
2obj-$(CONFIG_HD64465) += hd64465/
3 2
4EXTRA_CFLAGS += -Werror 3EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/cchips/hd6446x/hd64465/Makefile b/arch/sh/cchips/hd6446x/hd64465/Makefile
deleted file mode 100644
index f66edcb52c5b..000000000000
--- a/arch/sh/cchips/hd6446x/hd64465/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
1#
2# Makefile for the HD64465
3#
4
5obj-y := setup.o io.o gpio.o
6
diff --git a/arch/sh/cchips/hd6446x/hd64465/gpio.c b/arch/sh/cchips/hd6446x/hd64465/gpio.c
deleted file mode 100644
index 43431855ec86..000000000000
--- a/arch/sh/cchips/hd6446x/hd64465/gpio.c
+++ /dev/null
@@ -1,196 +0,0 @@
1/*
2 * $Id: gpio.c,v 1.4 2003/05/19 22:24:18 lethal Exp $
3 * by Greg Banks <gbanks@pocketpenguins.com>
4 * (c) 2000 PocketPenguins Inc
5 *
6 * GPIO pin support for HD64465 companion chip.
7 */
8
9#include <linux/kernel.h>
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/sched.h>
13#include <linux/ioport.h>
14#include <asm/io.h>
15#include <asm/hd64465/gpio.h>
16
17#define _PORTOF(portpin) (((portpin)>>3)&0x7)
18#define _PINOF(portpin) ((portpin)&0x7)
19
20/* Register addresses parametrised on port */
21#define GPIO_CR(port) (HD64465_REG_GPACR+((port)<<1))
22#define GPIO_DR(port) (HD64465_REG_GPADR+((port)<<1))
23#define GPIO_ICR(port) (HD64465_REG_GPAICR+((port)<<1))
24#define GPIO_ISR(port) (HD64465_REG_GPAISR+((port)<<1))
25
26#define GPIO_NPORTS 5
27
28#define MODNAME "hd64465_gpio"
29
30EXPORT_SYMBOL(hd64465_gpio_configure);
31EXPORT_SYMBOL(hd64465_gpio_get_pin);
32EXPORT_SYMBOL(hd64465_gpio_get_port);
33EXPORT_SYMBOL(hd64465_gpio_register_irq);
34EXPORT_SYMBOL(hd64465_gpio_set_pin);
35EXPORT_SYMBOL(hd64465_gpio_set_port);
36EXPORT_SYMBOL(hd64465_gpio_unregister_irq);
37
38/* TODO: each port should be protected with a spinlock */
39
40
41void hd64465_gpio_configure(int portpin, int direction)
42{
43 unsigned short cr;
44 unsigned int shift = (_PINOF(portpin)<<1);
45
46 cr = inw(GPIO_CR(_PORTOF(portpin)));
47 cr &= ~(3<<shift);
48 cr |= direction<<shift;
49 outw(cr, GPIO_CR(_PORTOF(portpin)));
50}
51
52void hd64465_gpio_set_pin(int portpin, unsigned int value)
53{
54 unsigned short d;
55 unsigned short mask = 1<<(_PINOF(portpin));
56
57 d = inw(GPIO_DR(_PORTOF(portpin)));
58 if (value)
59 d |= mask;
60 else
61 d &= ~mask;
62 outw(d, GPIO_DR(_PORTOF(portpin)));
63}
64
65unsigned int hd64465_gpio_get_pin(int portpin)
66{
67 return inw(GPIO_DR(_PORTOF(portpin))) & (1<<(_PINOF(portpin)));
68}
69
70/* TODO: for cleaner atomicity semantics, add a mask to this routine */
71
72void hd64465_gpio_set_port(int port, unsigned int value)
73{
74 outw(value, GPIO_DR(port));
75}
76
77unsigned int hd64465_gpio_get_port(int port)
78{
79 return inw(GPIO_DR(port));
80}
81
82
83static struct {
84 void (*func)(int portpin, void *dev);
85 void *dev;
86} handlers[GPIO_NPORTS * 8];
87
88static irqreturn_t hd64465_gpio_interrupt(int irq, void *dev)
89{
90 unsigned short port, pin, isr, mask, portpin;
91
92 for (port=0 ; port<GPIO_NPORTS ; port++) {
93 isr = inw(GPIO_ISR(port));
94
95 for (pin=0 ; pin<8 ; pin++) {
96 mask = 1<<pin;
97 if (isr & mask) {
98 portpin = (port<<3)|pin;
99 if (handlers[portpin].func != 0)
100 handlers[portpin].func(portpin, handlers[portpin].dev);
101 else
102 printk(KERN_NOTICE "unexpected GPIO interrupt, pin %c%d\n",
103 port+'A', (int)pin);
104 }
105 }
106
107 /* Write 1s back to ISR to clear it? That's what the manual says.. */
108 outw(isr, GPIO_ISR(port));
109 }
110
111 return IRQ_HANDLED;
112}
113
114void hd64465_gpio_register_irq(int portpin, int mode,
115 void (*handler)(int portpin, void *dev), void *dev)
116{
117 unsigned long flags;
118 unsigned short icr, mask;
119
120 if (handler == 0)
121 return;
122
123 local_irq_save(flags);
124
125 handlers[portpin].func = handler;
126 handlers[portpin].dev = dev;
127
128 /*
129 * Configure Interrupt Control Register
130 */
131 icr = inw(GPIO_ICR(_PORTOF(portpin)));
132 mask = (1<<_PINOF(portpin));
133
134 /* unmask interrupt */
135 icr &= ~mask;
136
137 /* set TS bit */
138 mask <<= 8;
139 icr &= ~mask;
140 if (mode == HD64465_GPIO_RISING)
141 icr |= mask;
142
143 outw(icr, GPIO_ICR(_PORTOF(portpin)));
144
145 local_irq_restore(flags);
146}
147
148void hd64465_gpio_unregister_irq(int portpin)
149{
150 unsigned long flags;
151 unsigned short icr;
152
153 local_irq_save(flags);
154
155 /*
156 * Configure Interrupt Control Register
157 */
158 icr = inw(GPIO_ICR(_PORTOF(portpin)));
159 icr |= (1<<_PINOF(portpin)); /* mask interrupt */
160 outw(icr, GPIO_ICR(_PORTOF(portpin)));
161
162 handlers[portpin].func = 0;
163 handlers[portpin].dev = 0;
164
165 local_irq_restore(flags);
166}
167
168static int __init hd64465_gpio_init(void)
169{
170 if (!request_region(HD64465_REG_GPACR, 0x1000, MODNAME))
171 return -EBUSY;
172 if (request_irq(HD64465_IRQ_GPIO, hd64465_gpio_interrupt,
173 IRQF_DISABLED, MODNAME, 0))
174 goto out_irqfailed;
175
176 printk("HD64465 GPIO layer on irq %d\n", HD64465_IRQ_GPIO);
177
178 return 0;
179
180out_irqfailed:
181 release_region(HD64465_REG_GPACR, 0x1000);
182
183 return -EINVAL;
184}
185
186static void __exit hd64465_gpio_exit(void)
187{
188 release_region(HD64465_REG_GPACR, 0x1000);
189 free_irq(HD64465_IRQ_GPIO, 0);
190}
191
192module_init(hd64465_gpio_init);
193module_exit(hd64465_gpio_exit);
194
195MODULE_LICENSE("GPL");
196
diff --git a/arch/sh/cchips/hd6446x/hd64465/io.c b/arch/sh/cchips/hd6446x/hd64465/io.c
deleted file mode 100644
index 58704d066ae2..000000000000
--- a/arch/sh/cchips/hd6446x/hd64465/io.c
+++ /dev/null
@@ -1,211 +0,0 @@
1/*
2 * $Id: io.c,v 1.4 2003/08/03 03:05:10 lethal Exp $
3 * by Greg Banks <gbanks@pocketpenguins.com>
4 * (c) 2000 PocketPenguins Inc
5 *
6 * Derived from io_hd64461.c, which bore the message:
7 * Copyright (C) 2000 YAEGASHI Takeshi
8 *
9 * Typical I/O routines for HD64465 system.
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <asm/io.h>
15#include <asm/hd64465/hd64465.h>
16
17
18#define HD64465_DEBUG 0
19
20#if HD64465_DEBUG
21#define DPRINTK(args...) printk(args)
22#define DIPRINTK(n, args...) if (hd64465_io_debug>(n)) printk(args)
23#else
24#define DPRINTK(args...)
25#define DIPRINTK(n, args...)
26#endif
27
28
29
30/* This is a hack suitable only for debugging IO port problems */
31int hd64465_io_debug;
32EXPORT_SYMBOL(hd64465_io_debug);
33
34/* Low iomap maps port 0-1K to addresses in 8byte chunks */
35#define HD64465_IOMAP_LO_THRESH 0x400
36#define HD64465_IOMAP_LO_SHIFT 3
37#define HD64465_IOMAP_LO_MASK ((1<<HD64465_IOMAP_LO_SHIFT)-1)
38#define HD64465_IOMAP_LO_NMAP (HD64465_IOMAP_LO_THRESH>>HD64465_IOMAP_LO_SHIFT)
39static unsigned long hd64465_iomap_lo[HD64465_IOMAP_LO_NMAP];
40static unsigned char hd64465_iomap_lo_shift[HD64465_IOMAP_LO_NMAP];
41
42/* High iomap maps port 1K-64K to addresses in 1K chunks */
43#define HD64465_IOMAP_HI_THRESH 0x10000
44#define HD64465_IOMAP_HI_SHIFT 10
45#define HD64465_IOMAP_HI_MASK ((1<<HD64465_IOMAP_HI_SHIFT)-1)
46#define HD64465_IOMAP_HI_NMAP (HD64465_IOMAP_HI_THRESH>>HD64465_IOMAP_HI_SHIFT)
47static unsigned long hd64465_iomap_hi[HD64465_IOMAP_HI_NMAP];
48static unsigned char hd64465_iomap_hi_shift[HD64465_IOMAP_HI_NMAP];
49
50#define PORT2ADDR(x) (sh_mv.mv_isa_port2addr(x))
51
52void hd64465_port_map(unsigned short baseport, unsigned int nports,
53 unsigned long addr, unsigned char shift)
54{
55 unsigned int port, endport = baseport + nports;
56
57 DPRINTK("hd64465_port_map(base=0x%04hx, n=0x%04hx, addr=0x%08lx,endport=0x%04x)\n",
58 baseport, nports, addr,endport);
59
60 for (port = baseport ;
61 port < endport && port < HD64465_IOMAP_LO_THRESH ;
62 port += (1<<HD64465_IOMAP_LO_SHIFT)) {
63 DPRINTK(" maplo[0x%x] = 0x%08lx\n", port, addr);
64 hd64465_iomap_lo[port>>HD64465_IOMAP_LO_SHIFT] = addr;
65 hd64465_iomap_lo_shift[port>>HD64465_IOMAP_LO_SHIFT] = shift;
66 addr += (1<<(HD64465_IOMAP_LO_SHIFT));
67 }
68
69 for (port = max_t(unsigned int, baseport, HD64465_IOMAP_LO_THRESH);
70 port < endport && port < HD64465_IOMAP_HI_THRESH ;
71 port += (1<<HD64465_IOMAP_HI_SHIFT)) {
72 DPRINTK(" maphi[0x%x] = 0x%08lx\n", port, addr);
73 hd64465_iomap_hi[port>>HD64465_IOMAP_HI_SHIFT] = addr;
74 hd64465_iomap_hi_shift[port>>HD64465_IOMAP_HI_SHIFT] = shift;
75 addr += (1<<(HD64465_IOMAP_HI_SHIFT));
76 }
77}
78EXPORT_SYMBOL(hd64465_port_map);
79
80void hd64465_port_unmap(unsigned short baseport, unsigned int nports)
81{
82 unsigned int port, endport = baseport + nports;
83
84 DPRINTK("hd64465_port_unmap(base=0x%04hx, n=0x%04hx)\n",
85 baseport, nports);
86
87 for (port = baseport ;
88 port < endport && port < HD64465_IOMAP_LO_THRESH ;
89 port += (1<<HD64465_IOMAP_LO_SHIFT)) {
90 hd64465_iomap_lo[port>>HD64465_IOMAP_LO_SHIFT] = 0;
91 }
92
93 for (port = max_t(unsigned int, baseport, HD64465_IOMAP_LO_THRESH);
94 port < endport && port < HD64465_IOMAP_HI_THRESH ;
95 port += (1<<HD64465_IOMAP_HI_SHIFT)) {
96 hd64465_iomap_hi[port>>HD64465_IOMAP_HI_SHIFT] = 0;
97 }
98}
99EXPORT_SYMBOL(hd64465_port_unmap);
100
101unsigned long hd64465_isa_port2addr(unsigned long port)
102{
103 unsigned long addr = 0;
104 unsigned char shift;
105
106 /* handle remapping of low IO ports */
107 if (port < HD64465_IOMAP_LO_THRESH) {
108 addr = hd64465_iomap_lo[port >> HD64465_IOMAP_LO_SHIFT];
109 shift = hd64465_iomap_lo_shift[port >> HD64465_IOMAP_LO_SHIFT];
110 if (addr != 0)
111 addr += (port & HD64465_IOMAP_LO_MASK) << shift;
112 else
113 printk(KERN_NOTICE "io_hd64465: access to un-mapped port %lx\n", port);
114 } else if (port < HD64465_IOMAP_HI_THRESH) {
115 addr = hd64465_iomap_hi[port >> HD64465_IOMAP_HI_SHIFT];
116 shift = hd64465_iomap_hi_shift[port >> HD64465_IOMAP_HI_SHIFT];
117 if (addr != 0)
118 addr += (port & HD64465_IOMAP_HI_MASK) << shift;
119 else
120 printk(KERN_NOTICE "io_hd64465: access to un-mapped port %lx\n", port);
121 }
122
123 /* HD64465 internal devices (0xb0000000) */
124 else if (port < 0x20000)
125 addr = CONFIG_HD64465_IOBASE + port - 0x10000;
126
127 /* Whole physical address space (0xa0000000) */
128 else
129 addr = P2SEGADDR(port);
130
131 DIPRINTK(2, "PORT2ADDR(0x%08lx) = 0x%08lx\n", port, addr);
132
133 return addr;
134}
135
136static inline void delay(void)
137{
138 ctrl_inw(0xa0000000);
139}
140
141unsigned char hd64465_inb(unsigned long port)
142{
143 unsigned long addr = PORT2ADDR(port);
144 unsigned long b = (addr == 0 ? 0 : *(volatile unsigned char*)addr);
145
146 DIPRINTK(0, "inb(%08lx) = %02x\n", addr, (unsigned)b);
147 return b;
148}
149
150unsigned char hd64465_inb_p(unsigned long port)
151{
152 unsigned long v;
153 unsigned long addr = PORT2ADDR(port);
154
155 v = (addr == 0 ? 0 : *(volatile unsigned char*)addr);
156 delay();
157 DIPRINTK(0, "inb_p(%08lx) = %02x\n", addr, (unsigned)v);
158 return v;
159}
160
161unsigned short hd64465_inw(unsigned long port)
162{
163 unsigned long addr = PORT2ADDR(port);
164 unsigned long b = (addr == 0 ? 0 : *(volatile unsigned short*)addr);
165 DIPRINTK(0, "inw(%08lx) = %04lx\n", addr, b);
166 return b;
167}
168
169unsigned int hd64465_inl(unsigned long port)
170{
171 unsigned long addr = PORT2ADDR(port);
172 unsigned int b = (addr == 0 ? 0 : *(volatile unsigned long*)addr);
173 DIPRINTK(0, "inl(%08lx) = %08x\n", addr, b);
174 return b;
175}
176
177void hd64465_outb(unsigned char b, unsigned long port)
178{
179 unsigned long addr = PORT2ADDR(port);
180
181 DIPRINTK(0, "outb(%02x, %08lx)\n", (unsigned)b, addr);
182 if (addr != 0)
183 *(volatile unsigned char*)addr = b;
184}
185
186void hd64465_outb_p(unsigned char b, unsigned long port)
187{
188 unsigned long addr = PORT2ADDR(port);
189
190 DIPRINTK(0, "outb_p(%02x, %08lx)\n", (unsigned)b, addr);
191 if (addr != 0)
192 *(volatile unsigned char*)addr = b;
193 delay();
194}
195
196void hd64465_outw(unsigned short b, unsigned long port)
197{
198 unsigned long addr = PORT2ADDR(port);
199 DIPRINTK(0, "outw(%04x, %08lx)\n", (unsigned)b, addr);
200 if (addr != 0)
201 *(volatile unsigned short*)addr = b;
202}
203
204void hd64465_outl(unsigned int b, unsigned long port)
205{
206 unsigned long addr = PORT2ADDR(port);
207 DIPRINTK(0, "outl(%08x, %08lx)\n", b, addr);
208 if (addr != 0)
209 *(volatile unsigned long*)addr = b;
210}
211
diff --git a/arch/sh/cchips/hd6446x/hd64465/setup.c b/arch/sh/cchips/hd6446x/hd64465/setup.c
deleted file mode 100644
index 9b8820c36701..000000000000
--- a/arch/sh/cchips/hd6446x/hd64465/setup.c
+++ /dev/null
@@ -1,181 +0,0 @@
1/*
2 * $Id: setup.c,v 1.4 2003/08/03 03:05:10 lethal Exp $
3 *
4 * Setup and IRQ handling code for the HD64465 companion chip.
5 * by Greg Banks <gbanks@pocketpenguins.com>
6 * Copyright (c) 2000 PocketPenguins Inc
7 *
8 * Derived from setup_hd64461.c which bore the message:
9 * Copyright (C) 2000 YAEGASHI Takeshi
10 */
11
12#include <linux/sched.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/param.h>
16#include <linux/ioport.h>
17#include <linux/interrupt.h>
18#include <linux/init.h>
19#include <linux/irq.h>
20#include <asm/io.h>
21#include <asm/irq.h>
22#include <asm/hd64465/hd64465.h>
23
24static void disable_hd64465_irq(unsigned int irq)
25{
26 unsigned short nimr;
27 unsigned short mask = 1 << (irq - HD64465_IRQ_BASE);
28
29 pr_debug("disable_hd64465_irq(%d): mask=%x\n", irq, mask);
30 nimr = inw(HD64465_REG_NIMR);
31 nimr |= mask;
32 outw(nimr, HD64465_REG_NIMR);
33}
34
35static void enable_hd64465_irq(unsigned int irq)
36{
37 unsigned short nimr;
38 unsigned short mask = 1 << (irq - HD64465_IRQ_BASE);
39
40 pr_debug("enable_hd64465_irq(%d): mask=%x\n", irq, mask);
41 nimr = inw(HD64465_REG_NIMR);
42 nimr &= ~mask;
43 outw(nimr, HD64465_REG_NIMR);
44}
45
46static void mask_and_ack_hd64465(unsigned int irq)
47{
48 disable_hd64465_irq(irq);
49}
50
51static void end_hd64465_irq(unsigned int irq)
52{
53 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
54 enable_hd64465_irq(irq);
55}
56
57static unsigned int startup_hd64465_irq(unsigned int irq)
58{
59 enable_hd64465_irq(irq);
60 return 0;
61}
62
63static void shutdown_hd64465_irq(unsigned int irq)
64{
65 disable_hd64465_irq(irq);
66}
67
68static struct hw_interrupt_type hd64465_irq_type = {
69 .typename = "HD64465-IRQ",
70 .startup = startup_hd64465_irq,
71 .shutdown = shutdown_hd64465_irq,
72 .enable = enable_hd64465_irq,
73 .disable = disable_hd64465_irq,
74 .ack = mask_and_ack_hd64465,
75 .end = end_hd64465_irq,
76};
77
78static irqreturn_t hd64465_interrupt(int irq, void *dev_id)
79{
80 printk(KERN_INFO
81 "HD64465: spurious interrupt, nirr: 0x%x nimr: 0x%x\n",
82 inw(HD64465_REG_NIRR), inw(HD64465_REG_NIMR));
83
84 return IRQ_NONE;
85}
86
87/*
88 * Support for a secondary IRQ demux step. This is necessary
89 * because the HD64465 presents a very thin interface to the
90 * PCMCIA bus; a lot of features (such as remapping interrupts)
91 * normally done in hardware by other PCMCIA host bridges is
92 * instead done in software.
93 */
94static struct {
95 int (*func)(int, void *);
96 void *dev;
97} hd64465_demux[HD64465_IRQ_NUM];
98
99void hd64465_register_irq_demux(int irq,
100 int (*demux)(int irq, void *dev), void *dev)
101{
102 hd64465_demux[irq - HD64465_IRQ_BASE].func = demux;
103 hd64465_demux[irq - HD64465_IRQ_BASE].dev = dev;
104}
105EXPORT_SYMBOL(hd64465_register_irq_demux);
106
107void hd64465_unregister_irq_demux(int irq)
108{
109 hd64465_demux[irq - HD64465_IRQ_BASE].func = 0;
110}
111EXPORT_SYMBOL(hd64465_unregister_irq_demux);
112
113int hd64465_irq_demux(int irq)
114{
115 if (irq == CONFIG_HD64465_IRQ) {
116 unsigned short i, bit;
117 unsigned short nirr = inw(HD64465_REG_NIRR);
118 unsigned short nimr = inw(HD64465_REG_NIMR);
119
120 pr_debug("hd64465_irq_demux, nirr=%04x, nimr=%04x\n", nirr, nimr);
121 nirr &= ~nimr;
122 for (bit = 1, i = 0 ; i < HD64465_IRQ_NUM ; bit <<= 1, i++)
123 if (nirr & bit)
124 break;
125
126 if (i < HD64465_IRQ_NUM) {
127 irq = HD64465_IRQ_BASE + i;
128 if (hd64465_demux[i].func != 0)
129 irq = hd64465_demux[i].func(irq, hd64465_demux[i].dev);
130 }
131 }
132 return irq;
133}
134
135static struct irqaction irq0 = {
136 .handler = hd64465_interrupt,
137 .flags = IRQF_DISABLED,
138 .mask = CPU_MASK_NONE,
139 .name = "HD64465",
140};
141
142static int __init setup_hd64465(void)
143{
144 int i;
145 unsigned short rev;
146 unsigned short smscr;
147
148 if (!MACH_HD64465)
149 return 0;
150
151 printk(KERN_INFO "HD64465 configured at 0x%x on irq %d(mapped into %d to %d)\n",
152 CONFIG_HD64465_IOBASE,
153 CONFIG_HD64465_IRQ,
154 HD64465_IRQ_BASE,
155 HD64465_IRQ_BASE+HD64465_IRQ_NUM-1);
156
157 if (inw(HD64465_REG_SDID) != HD64465_SDID) {
158 printk(KERN_ERR "HD64465 device ID not found, check base address\n");
159 }
160
161 rev = inw(HD64465_REG_SRR);
162 printk(KERN_INFO "HD64465 hardware revision %d.%d\n", (rev >> 8) & 0xff, rev & 0xff);
163
164 outw(0xffff, HD64465_REG_NIMR); /* mask all interrupts */
165
166 for (i = 0; i < HD64465_IRQ_NUM ; i++) {
167 irq_desc[HD64465_IRQ_BASE + i].chip = &hd64465_irq_type;
168 }
169
170 setup_irq(CONFIG_HD64465_IRQ, &irq0);
171
172 /* wake up the UART from STANDBY at this point */
173 smscr = inw(HD64465_REG_SMSCR);
174 outw(smscr & (~HD64465_SMSCR_UARTST), HD64465_REG_SMSCR);
175
176 /* remap IO ports for first ISA serial port to HD64465 UART */
177 hd64465_port_map(0x3f8, 8, CONFIG_HD64465_IOBASE + 0x8000, 1);
178
179 return 0;
180}
181module_init(setup_hd64465);
diff --git a/arch/sh/configs/migor_defconfig b/arch/sh/configs/migor_defconfig
index 624c47aa66d3..30cac42f25e7 100644
--- a/arch/sh/configs/migor_defconfig
+++ b/arch/sh/configs/migor_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.27 3# Linux kernel version: 2.6.28-rc2
4# Tue Oct 21 12:57:28 2008 4# Fri Oct 31 15:58:06 2008
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
@@ -73,7 +73,6 @@ CONFIG_EVENTFD=y
73CONFIG_SHMEM=y 73CONFIG_SHMEM=y
74CONFIG_AIO=y 74CONFIG_AIO=y
75CONFIG_VM_EVENT_COUNTERS=y 75CONFIG_VM_EVENT_COUNTERS=y
76CONFIG_PCI_QUIRKS=y
77CONFIG_SLAB=y 76CONFIG_SLAB=y
78# CONFIG_SLUB is not set 77# CONFIG_SLUB is not set
79# CONFIG_SLOB is not set 78# CONFIG_SLOB is not set
@@ -285,7 +284,7 @@ CONFIG_GUSA=y
285CONFIG_ZERO_PAGE_OFFSET=0x00001000 284CONFIG_ZERO_PAGE_OFFSET=0x00001000
286CONFIG_BOOT_LINK_OFFSET=0x00800000 285CONFIG_BOOT_LINK_OFFSET=0x00800000
287CONFIG_CMDLINE_BOOL=y 286CONFIG_CMDLINE_BOOL=y
288CONFIG_CMDLINE="console=ttySC0,115200 earlyprintk=serial ip=on" 287CONFIG_CMDLINE="console=ttySC0,115200 earlyprintk=serial ip=on root=/dev/nfs ip=dhcp"
289 288
290# 289#
291# Bus options 290# Bus options
@@ -718,6 +717,7 @@ CONFIG_SSB_POSSIBLE=y
718# CONFIG_MFD_SM501 is not set 717# CONFIG_MFD_SM501 is not set
719# CONFIG_HTC_PASIC3 is not set 718# CONFIG_HTC_PASIC3 is not set
720# CONFIG_MFD_TMIO is not set 719# CONFIG_MFD_TMIO is not set
720# CONFIG_PMIC_DA903X is not set
721# CONFIG_MFD_WM8400 is not set 721# CONFIG_MFD_WM8400 is not set
722# CONFIG_MFD_WM8350_I2C is not set 722# CONFIG_MFD_WM8350_I2C is not set
723 723
@@ -969,7 +969,23 @@ CONFIG_TMPFS=y
969# CONFIG_ROMFS_FS is not set 969# CONFIG_ROMFS_FS is not set
970# CONFIG_SYSV_FS is not set 970# CONFIG_SYSV_FS is not set
971# CONFIG_UFS_FS is not set 971# CONFIG_UFS_FS is not set
972# CONFIG_NETWORK_FILESYSTEMS is not set 972CONFIG_NETWORK_FILESYSTEMS=y
973CONFIG_NFS_FS=y
974# CONFIG_NFS_V3 is not set
975# CONFIG_NFS_V4 is not set
976CONFIG_ROOT_NFS=y
977# CONFIG_NFSD is not set
978CONFIG_LOCKD=y
979CONFIG_NFS_COMMON=y
980CONFIG_SUNRPC=y
981# CONFIG_SUNRPC_REGISTER_V4 is not set
982# CONFIG_RPCSEC_GSS_KRB5 is not set
983# CONFIG_RPCSEC_GSS_SPKM3 is not set
984# CONFIG_SMB_FS is not set
985# CONFIG_CIFS is not set
986# CONFIG_NCP_FS is not set
987# CONFIG_CODA_FS is not set
988# CONFIG_AFS_FS is not set
973 989
974# 990#
975# Partition Types 991# Partition Types
@@ -1019,7 +1035,12 @@ CONFIG_CRYPTO=y
1019# Crypto core or helper 1035# Crypto core or helper
1020# 1036#
1021# CONFIG_CRYPTO_FIPS is not set 1037# CONFIG_CRYPTO_FIPS is not set
1022# CONFIG_CRYPTO_MANAGER is not set 1038CONFIG_CRYPTO_ALGAPI=y
1039CONFIG_CRYPTO_AEAD=y
1040CONFIG_CRYPTO_BLKCIPHER=y
1041CONFIG_CRYPTO_HASH=y
1042CONFIG_CRYPTO_RNG=y
1043CONFIG_CRYPTO_MANAGER=y
1023# CONFIG_CRYPTO_GF128MUL is not set 1044# CONFIG_CRYPTO_GF128MUL is not set
1024# CONFIG_CRYPTO_NULL is not set 1045# CONFIG_CRYPTO_NULL is not set
1025# CONFIG_CRYPTO_CRYPTD is not set 1046# CONFIG_CRYPTO_CRYPTD is not set
@@ -1096,7 +1117,7 @@ CONFIG_CRYPTO=y
1096# Random Number Generation 1117# Random Number Generation
1097# 1118#
1098# CONFIG_CRYPTO_ANSI_CPRNG is not set 1119# CONFIG_CRYPTO_ANSI_CPRNG is not set
1099CONFIG_CRYPTO_HW=y 1120# CONFIG_CRYPTO_HW is not set
1100 1121
1101# 1122#
1102# Library routines 1123# Library routines
diff --git a/arch/sh/configs/ul2_defconfig b/arch/sh/configs/ul2_defconfig
new file mode 100644
index 000000000000..9afff67d9ff2
--- /dev/null
+++ b/arch/sh/configs/ul2_defconfig
@@ -0,0 +1,1169 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.28-rc2
4# Tue Oct 28 17:35:17 2008
5#
6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y
11CONFIG_GENERIC_FIND_NEXT_BIT=y
12CONFIG_GENERIC_HWEIGHT=y
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
15CONFIG_GENERIC_IRQ_PROBE=y
16# CONFIG_GENERIC_GPIO is not set
17CONFIG_GENERIC_TIME=y
18CONFIG_GENERIC_CLOCKEVENTS=y
19CONFIG_SYS_SUPPORTS_NUMA=y
20CONFIG_STACKTRACE_SUPPORT=y
21CONFIG_LOCKDEP_SUPPORT=y
22CONFIG_HAVE_LATENCYTOP_SUPPORT=y
23# CONFIG_ARCH_HAS_ILOG2_U32 is not set
24# CONFIG_ARCH_HAS_ILOG2_U64 is not set
25CONFIG_ARCH_NO_VIRT_TO_BUS=y
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# General setup
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_LOCK_KERNEL=y
34CONFIG_INIT_ENV_ARG_LIMIT=32
35CONFIG_LOCALVERSION=""
36CONFIG_LOCALVERSION_AUTO=y
37CONFIG_SWAP=y
38CONFIG_SYSVIPC=y
39CONFIG_SYSVIPC_SYSCTL=y
40# CONFIG_POSIX_MQUEUE is not set
41CONFIG_BSD_PROCESS_ACCT=y
42# CONFIG_BSD_PROCESS_ACCT_V3 is not set
43# CONFIG_TASKSTATS is not set
44# CONFIG_AUDIT is not set
45CONFIG_IKCONFIG=y
46CONFIG_IKCONFIG_PROC=y
47CONFIG_LOG_BUF_SHIFT=14
48# CONFIG_CGROUPS is not set
49# CONFIG_GROUP_SCHED is not set
50CONFIG_SYSFS_DEPRECATED=y
51CONFIG_SYSFS_DEPRECATED_V2=y
52# CONFIG_RELAY is not set
53# CONFIG_NAMESPACES is not set
54CONFIG_BLK_DEV_INITRD=y
55CONFIG_INITRAMFS_SOURCE=""
56CONFIG_CC_OPTIMIZE_FOR_SIZE=y
57CONFIG_SYSCTL=y
58CONFIG_EMBEDDED=y
59CONFIG_UID16=y
60CONFIG_SYSCTL_SYSCALL=y
61CONFIG_KALLSYMS=y
62# CONFIG_KALLSYMS_EXTRA_PASS is not set
63CONFIG_HOTPLUG=y
64CONFIG_PRINTK=y
65CONFIG_BUG=y
66CONFIG_ELF_CORE=y
67CONFIG_COMPAT_BRK=y
68CONFIG_BASE_FULL=y
69CONFIG_FUTEX=y
70CONFIG_ANON_INODES=y
71CONFIG_EPOLL=y
72CONFIG_SIGNALFD=y
73CONFIG_TIMERFD=y
74CONFIG_EVENTFD=y
75CONFIG_SHMEM=y
76CONFIG_AIO=y
77CONFIG_VM_EVENT_COUNTERS=y
78CONFIG_SLUB_DEBUG=y
79# CONFIG_SLAB is not set
80CONFIG_SLUB=y
81# CONFIG_SLOB is not set
82CONFIG_PROFILING=y
83# CONFIG_MARKERS is not set
84# CONFIG_OPROFILE is not set
85CONFIG_HAVE_OPROFILE=y
86# CONFIG_KPROBES is not set
87CONFIG_HAVE_IOREMAP_PROT=y
88CONFIG_HAVE_KPROBES=y
89CONFIG_HAVE_KRETPROBES=y
90CONFIG_HAVE_ARCH_TRACEHOOK=y
91CONFIG_HAVE_CLK=y
92CONFIG_HAVE_GENERIC_DMA_COHERENT=y
93CONFIG_SLABINFO=y
94CONFIG_RT_MUTEXES=y
95# CONFIG_TINY_SHMEM is not set
96CONFIG_BASE_SMALL=0
97CONFIG_MODULES=y
98# CONFIG_MODULE_FORCE_LOAD is not set
99CONFIG_MODULE_UNLOAD=y
100# CONFIG_MODULE_FORCE_UNLOAD is not set
101# CONFIG_MODVERSIONS is not set
102# CONFIG_MODULE_SRCVERSION_ALL is not set
103CONFIG_KMOD=y
104CONFIG_BLOCK=y
105# CONFIG_LBD is not set
106# CONFIG_BLK_DEV_IO_TRACE is not set
107# CONFIG_LSF is not set
108# CONFIG_BLK_DEV_BSG is not set
109# CONFIG_BLK_DEV_INTEGRITY is not set
110
111#
112# IO Schedulers
113#
114CONFIG_IOSCHED_NOOP=y
115# CONFIG_IOSCHED_AS is not set
116# CONFIG_IOSCHED_DEADLINE is not set
117# CONFIG_IOSCHED_CFQ is not set
118# CONFIG_DEFAULT_AS is not set
119# CONFIG_DEFAULT_DEADLINE is not set
120# CONFIG_DEFAULT_CFQ is not set
121CONFIG_DEFAULT_NOOP=y
122CONFIG_DEFAULT_IOSCHED="noop"
123CONFIG_CLASSIC_RCU=y
124# CONFIG_FREEZER is not set
125
126#
127# System type
128#
129CONFIG_CPU_SH4=y
130CONFIG_CPU_SH4A=y
131CONFIG_CPU_SH4AL_DSP=y
132CONFIG_CPU_SHX2=y
133# CONFIG_CPU_SUBTYPE_SH7619 is not set
134# CONFIG_CPU_SUBTYPE_SH7203 is not set
135# CONFIG_CPU_SUBTYPE_SH7206 is not set
136# CONFIG_CPU_SUBTYPE_SH7263 is not set
137# CONFIG_CPU_SUBTYPE_MXG is not set
138# CONFIG_CPU_SUBTYPE_SH7705 is not set
139# CONFIG_CPU_SUBTYPE_SH7706 is not set
140# CONFIG_CPU_SUBTYPE_SH7707 is not set
141# CONFIG_CPU_SUBTYPE_SH7708 is not set
142# CONFIG_CPU_SUBTYPE_SH7709 is not set
143# CONFIG_CPU_SUBTYPE_SH7710 is not set
144# CONFIG_CPU_SUBTYPE_SH7712 is not set
145# CONFIG_CPU_SUBTYPE_SH7720 is not set
146# CONFIG_CPU_SUBTYPE_SH7721 is not set
147# CONFIG_CPU_SUBTYPE_SH7750 is not set
148# CONFIG_CPU_SUBTYPE_SH7091 is not set
149# CONFIG_CPU_SUBTYPE_SH7750R is not set
150# CONFIG_CPU_SUBTYPE_SH7750S is not set
151# CONFIG_CPU_SUBTYPE_SH7751 is not set
152# CONFIG_CPU_SUBTYPE_SH7751R is not set
153# CONFIG_CPU_SUBTYPE_SH7760 is not set
154# CONFIG_CPU_SUBTYPE_SH4_202 is not set
155# CONFIG_CPU_SUBTYPE_SH7723 is not set
156# CONFIG_CPU_SUBTYPE_SH7763 is not set
157# CONFIG_CPU_SUBTYPE_SH7770 is not set
158# CONFIG_CPU_SUBTYPE_SH7780 is not set
159# CONFIG_CPU_SUBTYPE_SH7785 is not set
160# CONFIG_CPU_SUBTYPE_SHX3 is not set
161# CONFIG_CPU_SUBTYPE_SH7343 is not set
162# CONFIG_CPU_SUBTYPE_SH7722 is not set
163CONFIG_CPU_SUBTYPE_SH7366=y
164# CONFIG_CPU_SUBTYPE_SH5_101 is not set
165# CONFIG_CPU_SUBTYPE_SH5_103 is not set
166
167#
168# Memory management options
169#
170CONFIG_QUICKLIST=y
171CONFIG_MMU=y
172CONFIG_PAGE_OFFSET=0x80000000
173CONFIG_MEMORY_START=0x08000000
174CONFIG_MEMORY_SIZE=0x01f00000
175CONFIG_29BIT=y
176# CONFIG_X2TLB is not set
177CONFIG_VSYSCALL=y
178CONFIG_NUMA=y
179CONFIG_NODES_SHIFT=1
180CONFIG_ARCH_SPARSEMEM_ENABLE=y
181CONFIG_ARCH_SPARSEMEM_DEFAULT=y
182CONFIG_MAX_ACTIVE_REGIONS=1
183CONFIG_ARCH_POPULATES_NODE_MAP=y
184CONFIG_ARCH_SELECT_MEMORY_MODEL=y
185CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
186CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
187CONFIG_PAGE_SIZE_4KB=y
188# CONFIG_PAGE_SIZE_8KB is not set
189# CONFIG_PAGE_SIZE_16KB is not set
190# CONFIG_PAGE_SIZE_64KB is not set
191CONFIG_ENTRY_OFFSET=0x00001000
192CONFIG_HUGETLB_PAGE_SIZE_64K=y
193# CONFIG_HUGETLB_PAGE_SIZE_256K is not set
194# CONFIG_HUGETLB_PAGE_SIZE_1MB is not set
195# CONFIG_HUGETLB_PAGE_SIZE_4MB is not set
196# CONFIG_HUGETLB_PAGE_SIZE_64MB is not set
197# CONFIG_HUGETLB_PAGE_SIZE_512MB is not set
198CONFIG_SELECT_MEMORY_MODEL=y
199# CONFIG_FLATMEM_MANUAL is not set
200# CONFIG_DISCONTIGMEM_MANUAL is not set
201CONFIG_SPARSEMEM_MANUAL=y
202CONFIG_SPARSEMEM=y
203CONFIG_NEED_MULTIPLE_NODES=y
204CONFIG_HAVE_MEMORY_PRESENT=y
205CONFIG_SPARSEMEM_STATIC=y
206# CONFIG_MEMORY_HOTPLUG is not set
207CONFIG_SPLIT_PTLOCK_CPUS=4
208# CONFIG_MIGRATION is not set
209# CONFIG_RESOURCES_64BIT is not set
210# CONFIG_PHYS_ADDR_T_64BIT is not set
211CONFIG_ZONE_DMA_FLAG=0
212CONFIG_NR_QUICK=2
213CONFIG_UNEVICTABLE_LRU=y
214
215#
216# Cache configuration
217#
218# CONFIG_SH_DIRECT_MAPPED is not set
219CONFIG_CACHE_WRITEBACK=y
220# CONFIG_CACHE_WRITETHROUGH is not set
221# CONFIG_CACHE_OFF is not set
222
223#
224# Processor features
225#
226CONFIG_CPU_LITTLE_ENDIAN=y
227# CONFIG_CPU_BIG_ENDIAN is not set
228# CONFIG_SH_FPU_EMU is not set
229# CONFIG_SH_DSP is not set
230# CONFIG_SH_STORE_QUEUES is not set
231CONFIG_CPU_HAS_INTEVT=y
232CONFIG_CPU_HAS_SR_RB=y
233CONFIG_CPU_HAS_PTEA=y
234CONFIG_CPU_HAS_DSP=y
235
236#
237# Board support
238#
239
240#
241# Timer and clock configuration
242#
243CONFIG_SH_TMU=y
244CONFIG_SH_TIMER_IRQ=16
245CONFIG_SH_PCLK_FREQ=33333333
246CONFIG_TICK_ONESHOT=y
247# CONFIG_NO_HZ is not set
248CONFIG_HIGH_RES_TIMERS=y
249CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
250
251#
252# CPU Frequency scaling
253#
254# CONFIG_CPU_FREQ is not set
255
256#
257# DMA support
258#
259# CONFIG_SH_DMA is not set
260
261#
262# Companion Chips
263#
264
265#
266# Additional SuperH Device Drivers
267#
268# CONFIG_HEARTBEAT is not set
269# CONFIG_PUSH_SWITCH is not set
270
271#
272# Kernel features
273#
274CONFIG_HZ_100=y
275# CONFIG_HZ_250 is not set
276# CONFIG_HZ_300 is not set
277# CONFIG_HZ_1000 is not set
278CONFIG_HZ=100
279CONFIG_SCHED_HRTICK=y
280CONFIG_KEXEC=y
281# CONFIG_CRASH_DUMP is not set
282# CONFIG_SECCOMP is not set
283# CONFIG_PREEMPT_NONE is not set
284# CONFIG_PREEMPT_VOLUNTARY is not set
285CONFIG_PREEMPT=y
286# CONFIG_PREEMPT_RCU is not set
287CONFIG_GUSA=y
288
289#
290# Boot options
291#
292CONFIG_ZERO_PAGE_OFFSET=0x00001000
293CONFIG_BOOT_LINK_OFFSET=0x00800000
294CONFIG_CMDLINE_BOOL=y
295CONFIG_CMDLINE="console=ttySC0,115200 root=/dev/nfs ip=dhcp"
296
297#
298# Bus options
299#
300# CONFIG_ARCH_SUPPORTS_MSI is not set
301# CONFIG_PCCARD is not set
302
303#
304# Executable file formats
305#
306CONFIG_BINFMT_ELF=y
307# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
308# CONFIG_HAVE_AOUT is not set
309# CONFIG_BINFMT_MISC is not set
310CONFIG_NET=y
311
312#
313# Networking options
314#
315CONFIG_PACKET=y
316CONFIG_PACKET_MMAP=y
317CONFIG_UNIX=y
318CONFIG_XFRM=y
319# CONFIG_XFRM_USER is not set
320# CONFIG_XFRM_SUB_POLICY is not set
321# CONFIG_XFRM_MIGRATE is not set
322# CONFIG_XFRM_STATISTICS is not set
323# CONFIG_NET_KEY is not set
324CONFIG_INET=y
325# CONFIG_IP_MULTICAST is not set
326# CONFIG_IP_ADVANCED_ROUTER is not set
327CONFIG_IP_FIB_HASH=y
328CONFIG_IP_PNP=y
329CONFIG_IP_PNP_DHCP=y
330# CONFIG_IP_PNP_BOOTP is not set
331# CONFIG_IP_PNP_RARP is not set
332# CONFIG_NET_IPIP is not set
333# CONFIG_NET_IPGRE is not set
334# CONFIG_ARPD is not set
335# CONFIG_SYN_COOKIES is not set
336# CONFIG_INET_AH is not set
337# CONFIG_INET_ESP is not set
338# CONFIG_INET_IPCOMP is not set
339# CONFIG_INET_XFRM_TUNNEL is not set
340# CONFIG_INET_TUNNEL is not set
341CONFIG_INET_XFRM_MODE_TRANSPORT=y
342CONFIG_INET_XFRM_MODE_TUNNEL=y
343CONFIG_INET_XFRM_MODE_BEET=y
344# CONFIG_INET_LRO is not set
345CONFIG_INET_DIAG=y
346CONFIG_INET_TCP_DIAG=y
347# CONFIG_TCP_CONG_ADVANCED is not set
348CONFIG_TCP_CONG_CUBIC=y
349CONFIG_DEFAULT_TCP_CONG="cubic"
350# CONFIG_TCP_MD5SIG is not set
351# CONFIG_IPV6 is not set
352# CONFIG_NETWORK_SECMARK is not set
353# CONFIG_NETFILTER is not set
354# CONFIG_IP_DCCP is not set
355# CONFIG_IP_SCTP is not set
356# CONFIG_TIPC is not set
357# CONFIG_ATM is not set
358# CONFIG_BRIDGE is not set
359# CONFIG_NET_DSA is not set
360# CONFIG_VLAN_8021Q is not set
361# CONFIG_DECNET is not set
362# CONFIG_LLC2 is not set
363# CONFIG_IPX is not set
364# CONFIG_ATALK is not set
365# CONFIG_X25 is not set
366# CONFIG_LAPB is not set
367# CONFIG_ECONET is not set
368# CONFIG_WAN_ROUTER is not set
369# CONFIG_NET_SCHED is not set
370
371#
372# Network testing
373#
374# CONFIG_NET_PKTGEN is not set
375# CONFIG_HAMRADIO is not set
376# CONFIG_CAN is not set
377# CONFIG_IRDA is not set
378# CONFIG_BT is not set
379# CONFIG_AF_RXRPC is not set
380# CONFIG_PHONET is not set
381CONFIG_WIRELESS=y
382CONFIG_CFG80211=y
383CONFIG_NL80211=y
384# CONFIG_WIRELESS_OLD_REGULATORY is not set
385CONFIG_WIRELESS_EXT=y
386CONFIG_WIRELESS_EXT_SYSFS=y
387CONFIG_MAC80211=y
388
389#
390# Rate control algorithm selection
391#
392CONFIG_MAC80211_RC_PID=y
393# CONFIG_MAC80211_RC_MINSTREL is not set
394CONFIG_MAC80211_RC_DEFAULT_PID=y
395# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
396CONFIG_MAC80211_RC_DEFAULT="pid"
397# CONFIG_MAC80211_MESH is not set
398# CONFIG_MAC80211_LEDS is not set
399# CONFIG_MAC80211_DEBUG_MENU is not set
400CONFIG_IEEE80211=m
401CONFIG_IEEE80211_DEBUG=y
402CONFIG_IEEE80211_CRYPT_WEP=m
403CONFIG_IEEE80211_CRYPT_CCMP=m
404CONFIG_IEEE80211_CRYPT_TKIP=m
405# CONFIG_RFKILL is not set
406# CONFIG_NET_9P is not set
407
408#
409# Device Drivers
410#
411
412#
413# Generic Driver Options
414#
415CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
416CONFIG_STANDALONE=y
417CONFIG_PREVENT_FIRMWARE_BUILD=y
418CONFIG_FW_LOADER=y
419CONFIG_FIRMWARE_IN_KERNEL=y
420CONFIG_EXTRA_FIRMWARE=""
421# CONFIG_SYS_HYPERVISOR is not set
422# CONFIG_CONNECTOR is not set
423CONFIG_MTD=y
424# CONFIG_MTD_DEBUG is not set
425CONFIG_MTD_CONCAT=y
426CONFIG_MTD_PARTITIONS=y
427# CONFIG_MTD_REDBOOT_PARTS is not set
428# CONFIG_MTD_CMDLINE_PARTS is not set
429# CONFIG_MTD_AR7_PARTS is not set
430
431#
432# User Modules And Translation Layers
433#
434CONFIG_MTD_CHAR=y
435CONFIG_MTD_BLKDEVS=y
436CONFIG_MTD_BLOCK=y
437# CONFIG_FTL is not set
438# CONFIG_NFTL is not set
439# CONFIG_INFTL is not set
440# CONFIG_RFD_FTL is not set
441# CONFIG_SSFDC is not set
442# CONFIG_MTD_OOPS is not set
443
444#
445# RAM/ROM/Flash chip drivers
446#
447CONFIG_MTD_CFI=y
448# CONFIG_MTD_JEDECPROBE is not set
449CONFIG_MTD_GEN_PROBE=y
450# CONFIG_MTD_CFI_ADV_OPTIONS is not set
451CONFIG_MTD_MAP_BANK_WIDTH_1=y
452CONFIG_MTD_MAP_BANK_WIDTH_2=y
453CONFIG_MTD_MAP_BANK_WIDTH_4=y
454# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
455# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
456# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
457CONFIG_MTD_CFI_I1=y
458CONFIG_MTD_CFI_I2=y
459# CONFIG_MTD_CFI_I4 is not set
460# CONFIG_MTD_CFI_I8 is not set
461# CONFIG_MTD_CFI_INTELEXT is not set
462CONFIG_MTD_CFI_AMDSTD=y
463# CONFIG_MTD_CFI_STAA is not set
464CONFIG_MTD_CFI_UTIL=y
465CONFIG_MTD_RAM=y
466# CONFIG_MTD_ROM is not set
467# CONFIG_MTD_ABSENT is not set
468
469#
470# Mapping drivers for chip access
471#
472# CONFIG_MTD_COMPLEX_MAPPINGS is not set
473# CONFIG_MTD_PHYSMAP is not set
474# CONFIG_MTD_PLATRAM is not set
475
476#
477# Self-contained MTD device drivers
478#
479# CONFIG_MTD_SLRAM is not set
480# CONFIG_MTD_PHRAM is not set
481# CONFIG_MTD_MTDRAM is not set
482# CONFIG_MTD_BLOCK2MTD is not set
483
484#
485# Disk-On-Chip Device Drivers
486#
487# CONFIG_MTD_DOC2000 is not set
488# CONFIG_MTD_DOC2001 is not set
489# CONFIG_MTD_DOC2001PLUS is not set
490# CONFIG_MTD_NAND is not set
491# CONFIG_MTD_ONENAND is not set
492
493#
494# UBI - Unsorted block images
495#
496# CONFIG_MTD_UBI is not set
497# CONFIG_PARPORT is not set
498CONFIG_BLK_DEV=y
499# CONFIG_BLK_DEV_COW_COMMON is not set
500# CONFIG_BLK_DEV_LOOP is not set
501# CONFIG_BLK_DEV_NBD is not set
502# CONFIG_BLK_DEV_UB is not set
503CONFIG_BLK_DEV_RAM=y
504CONFIG_BLK_DEV_RAM_COUNT=16
505CONFIG_BLK_DEV_RAM_SIZE=4096
506# CONFIG_BLK_DEV_XIP is not set
507# CONFIG_CDROM_PKTCDVD is not set
508# CONFIG_ATA_OVER_ETH is not set
509# CONFIG_BLK_DEV_HD is not set
510CONFIG_MISC_DEVICES=y
511# CONFIG_EEPROM_93CX6 is not set
512# CONFIG_ENCLOSURE_SERVICES is not set
513CONFIG_HAVE_IDE=y
514# CONFIG_IDE is not set
515
516#
517# SCSI device support
518#
519# CONFIG_RAID_ATTRS is not set
520CONFIG_SCSI=y
521CONFIG_SCSI_DMA=y
522# CONFIG_SCSI_TGT is not set
523# CONFIG_SCSI_NETLINK is not set
524CONFIG_SCSI_PROC_FS=y
525
526#
527# SCSI support type (disk, tape, CD-ROM)
528#
529CONFIG_BLK_DEV_SD=y
530# CONFIG_CHR_DEV_ST is not set
531# CONFIG_CHR_DEV_OSST is not set
532# CONFIG_BLK_DEV_SR is not set
533# CONFIG_CHR_DEV_SG is not set
534# CONFIG_CHR_DEV_SCH is not set
535
536#
537# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
538#
539# CONFIG_SCSI_MULTI_LUN is not set
540# CONFIG_SCSI_CONSTANTS is not set
541# CONFIG_SCSI_LOGGING is not set
542# CONFIG_SCSI_SCAN_ASYNC is not set
543CONFIG_SCSI_WAIT_SCAN=m
544
545#
546# SCSI Transports
547#
548# CONFIG_SCSI_SPI_ATTRS is not set
549# CONFIG_SCSI_FC_ATTRS is not set
550# CONFIG_SCSI_ISCSI_ATTRS is not set
551# CONFIG_SCSI_SAS_LIBSAS is not set
552# CONFIG_SCSI_SRP_ATTRS is not set
553CONFIG_SCSI_LOWLEVEL=y
554# CONFIG_ISCSI_TCP is not set
555# CONFIG_SCSI_DEBUG is not set
556# CONFIG_SCSI_DH is not set
557CONFIG_ATA=y
558# CONFIG_ATA_NONSTANDARD is not set
559CONFIG_SATA_PMP=y
560CONFIG_ATA_SFF=y
561# CONFIG_SATA_MV is not set
562CONFIG_PATA_PLATFORM=y
563# CONFIG_MD is not set
564CONFIG_NETDEVICES=y
565# CONFIG_DUMMY is not set
566# CONFIG_BONDING is not set
567# CONFIG_MACVLAN is not set
568# CONFIG_EQUALIZER is not set
569# CONFIG_TUN is not set
570# CONFIG_VETH is not set
571# CONFIG_PHYLIB is not set
572CONFIG_NET_ETHERNET=y
573CONFIG_MII=y
574# CONFIG_AX88796 is not set
575# CONFIG_STNIC is not set
576# CONFIG_SMC91X is not set
577# CONFIG_SMC911X is not set
578# CONFIG_IBM_NEW_EMAC_ZMII is not set
579# CONFIG_IBM_NEW_EMAC_RGMII is not set
580# CONFIG_IBM_NEW_EMAC_TAH is not set
581# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
582# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
583# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
584# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
585# CONFIG_B44 is not set
586# CONFIG_NETDEV_1000 is not set
587# CONFIG_NETDEV_10000 is not set
588
589#
590# Wireless LAN
591#
592# CONFIG_WLAN_PRE80211 is not set
593CONFIG_WLAN_80211=y
594CONFIG_LIBERTAS=m
595# CONFIG_LIBERTAS_USB is not set
596CONFIG_LIBERTAS_SDIO=m
597CONFIG_LIBERTAS_DEBUG=y
598# CONFIG_LIBERTAS_THINFIRM is not set
599# CONFIG_USB_ZD1201 is not set
600# CONFIG_USB_NET_RNDIS_WLAN is not set
601# CONFIG_RTL8187 is not set
602# CONFIG_MAC80211_HWSIM is not set
603# CONFIG_P54_COMMON is not set
604# CONFIG_IWLWIFI_LEDS is not set
605# CONFIG_HOSTAP is not set
606# CONFIG_B43 is not set
607# CONFIG_B43LEGACY is not set
608# CONFIG_ZD1211RW is not set
609# CONFIG_RT2X00 is not set
610
611#
612# USB Network Adapters
613#
614# CONFIG_USB_CATC is not set
615# CONFIG_USB_KAWETH is not set
616# CONFIG_USB_PEGASUS is not set
617# CONFIG_USB_RTL8150 is not set
618CONFIG_USB_USBNET=y
619CONFIG_USB_NET_AX8817X=y
620CONFIG_USB_NET_CDCETHER=y
621# CONFIG_USB_NET_DM9601 is not set
622# CONFIG_USB_NET_SMSC95XX is not set
623# CONFIG_USB_NET_GL620A is not set
624# CONFIG_USB_NET_NET1080 is not set
625# CONFIG_USB_NET_PLUSB is not set
626# CONFIG_USB_NET_MCS7830 is not set
627# CONFIG_USB_NET_RNDIS_HOST is not set
628# CONFIG_USB_NET_CDC_SUBSET is not set
629# CONFIG_USB_NET_ZAURUS is not set
630# CONFIG_WAN is not set
631# CONFIG_PPP is not set
632# CONFIG_SLIP is not set
633# CONFIG_NETCONSOLE is not set
634# CONFIG_NETPOLL is not set
635# CONFIG_NET_POLL_CONTROLLER is not set
636# CONFIG_ISDN is not set
637# CONFIG_PHONE is not set
638
639#
640# Input device support
641#
642CONFIG_INPUT=y
643# CONFIG_INPUT_FF_MEMLESS is not set
644# CONFIG_INPUT_POLLDEV is not set
645
646#
647# Userland interfaces
648#
649# CONFIG_INPUT_MOUSEDEV is not set
650# CONFIG_INPUT_JOYDEV is not set
651# CONFIG_INPUT_EVDEV is not set
652# CONFIG_INPUT_EVBUG is not set
653
654#
655# Input Device Drivers
656#
657# CONFIG_INPUT_KEYBOARD is not set
658# CONFIG_INPUT_MOUSE is not set
659# CONFIG_INPUT_JOYSTICK is not set
660# CONFIG_INPUT_TABLET is not set
661# CONFIG_INPUT_TOUCHSCREEN is not set
662# CONFIG_INPUT_MISC is not set
663
664#
665# Hardware I/O ports
666#
667# CONFIG_SERIO is not set
668# CONFIG_GAMEPORT is not set
669
670#
671# Character devices
672#
673# CONFIG_VT is not set
674CONFIG_DEVKMEM=y
675# CONFIG_SERIAL_NONSTANDARD is not set
676
677#
678# Serial drivers
679#
680# CONFIG_SERIAL_8250 is not set
681
682#
683# Non-8250 serial port support
684#
685CONFIG_SERIAL_SH_SCI=y
686CONFIG_SERIAL_SH_SCI_NR_UARTS=1
687CONFIG_SERIAL_SH_SCI_CONSOLE=y
688CONFIG_SERIAL_CORE=y
689CONFIG_SERIAL_CORE_CONSOLE=y
690# CONFIG_UNIX98_PTYS is not set
691# CONFIG_LEGACY_PTYS is not set
692# CONFIG_IPMI_HANDLER is not set
693# CONFIG_HW_RANDOM is not set
694# CONFIG_R3964 is not set
695# CONFIG_RAW_DRIVER is not set
696# CONFIG_TCG_TPM is not set
697# CONFIG_I2C is not set
698# CONFIG_SPI is not set
699# CONFIG_W1 is not set
700# CONFIG_POWER_SUPPLY is not set
701CONFIG_HWMON=y
702# CONFIG_HWMON_VID is not set
703# CONFIG_SENSORS_F71805F is not set
704# CONFIG_SENSORS_F71882FG is not set
705# CONFIG_SENSORS_IT87 is not set
706# CONFIG_SENSORS_PC87360 is not set
707# CONFIG_SENSORS_PC87427 is not set
708# CONFIG_SENSORS_SMSC47M1 is not set
709# CONFIG_SENSORS_SMSC47B397 is not set
710# CONFIG_SENSORS_VT1211 is not set
711# CONFIG_SENSORS_W83627HF is not set
712# CONFIG_SENSORS_W83627EHF is not set
713# CONFIG_HWMON_DEBUG_CHIP is not set
714# CONFIG_THERMAL is not set
715# CONFIG_THERMAL_HWMON is not set
716# CONFIG_WATCHDOG is not set
717
718#
719# Sonics Silicon Backplane
720#
721CONFIG_SSB_POSSIBLE=y
722# CONFIG_SSB is not set
723
724#
725# Multifunction device drivers
726#
727# CONFIG_MFD_CORE is not set
728# CONFIG_MFD_SM501 is not set
729# CONFIG_HTC_PASIC3 is not set
730# CONFIG_MFD_TMIO is not set
731
732#
733# Multimedia devices
734#
735
736#
737# Multimedia core support
738#
739# CONFIG_VIDEO_DEV is not set
740# CONFIG_DVB_CORE is not set
741# CONFIG_VIDEO_MEDIA is not set
742
743#
744# Multimedia drivers
745#
746# CONFIG_DAB is not set
747
748#
749# Graphics support
750#
751# CONFIG_VGASTATE is not set
752# CONFIG_VIDEO_OUTPUT_CONTROL is not set
753# CONFIG_FB is not set
754# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
755
756#
757# Display device support
758#
759# CONFIG_DISPLAY_SUPPORT is not set
760# CONFIG_SOUND is not set
761# CONFIG_HID_SUPPORT is not set
762CONFIG_USB_SUPPORT=y
763CONFIG_USB_ARCH_HAS_HCD=y
764# CONFIG_USB_ARCH_HAS_OHCI is not set
765# CONFIG_USB_ARCH_HAS_EHCI is not set
766CONFIG_USB=y
767# CONFIG_USB_DEBUG is not set
768# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
769
770#
771# Miscellaneous USB options
772#
773# CONFIG_USB_DEVICEFS is not set
774CONFIG_USB_DEVICE_CLASS=y
775# CONFIG_USB_DYNAMIC_MINORS is not set
776# CONFIG_USB_OTG is not set
777# CONFIG_USB_OTG_WHITELIST is not set
778# CONFIG_USB_OTG_BLACKLIST_HUB is not set
779CONFIG_USB_MON=y
780# CONFIG_USB_WUSB is not set
781# CONFIG_USB_WUSB_CBAF is not set
782
783#
784# USB Host Controller Drivers
785#
786# CONFIG_USB_C67X00_HCD is not set
787# CONFIG_USB_ISP116X_HCD is not set
788# CONFIG_USB_ISP1760_HCD is not set
789# CONFIG_USB_SL811_HCD is not set
790CONFIG_USB_R8A66597_HCD=y
791# CONFIG_SUPERH_ON_CHIP_R8A66597 is not set
792# CONFIG_USB_HWA_HCD is not set
793
794#
795# USB Device Class drivers
796#
797# CONFIG_USB_ACM is not set
798# CONFIG_USB_PRINTER is not set
799# CONFIG_USB_WDM is not set
800# CONFIG_USB_TMC is not set
801
802#
803# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
804#
805
806#
807# may also be needed; see USB_STORAGE Help for more information
808#
809CONFIG_USB_STORAGE=y
810# CONFIG_USB_STORAGE_DEBUG is not set
811# CONFIG_USB_STORAGE_DATAFAB is not set
812# CONFIG_USB_STORAGE_FREECOM is not set
813# CONFIG_USB_STORAGE_ISD200 is not set
814# CONFIG_USB_STORAGE_DPCM is not set
815# CONFIG_USB_STORAGE_USBAT is not set
816# CONFIG_USB_STORAGE_SDDR09 is not set
817# CONFIG_USB_STORAGE_SDDR55 is not set
818# CONFIG_USB_STORAGE_JUMPSHOT is not set
819# CONFIG_USB_STORAGE_ALAUDA is not set
820# CONFIG_USB_STORAGE_ONETOUCH is not set
821# CONFIG_USB_STORAGE_KARMA is not set
822# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
823# CONFIG_USB_LIBUSUAL is not set
824
825#
826# USB Imaging devices
827#
828# CONFIG_USB_MDC800 is not set
829# CONFIG_USB_MICROTEK is not set
830
831#
832# USB port drivers
833#
834# CONFIG_USB_SERIAL is not set
835
836#
837# USB Miscellaneous drivers
838#
839# CONFIG_USB_EMI62 is not set
840# CONFIG_USB_EMI26 is not set
841# CONFIG_USB_ADUTUX is not set
842# CONFIG_USB_SEVSEG is not set
843# CONFIG_USB_RIO500 is not set
844# CONFIG_USB_LEGOTOWER is not set
845# CONFIG_USB_LCD is not set
846# CONFIG_USB_BERRY_CHARGE is not set
847# CONFIG_USB_LED is not set
848# CONFIG_USB_CYPRESS_CY7C63 is not set
849# CONFIG_USB_CYTHERM is not set
850# CONFIG_USB_PHIDGET is not set
851# CONFIG_USB_IDMOUSE is not set
852# CONFIG_USB_FTDI_ELAN is not set
853# CONFIG_USB_APPLEDISPLAY is not set
854# CONFIG_USB_LD is not set
855# CONFIG_USB_TRANCEVIBRATOR is not set
856# CONFIG_USB_IOWARRIOR is not set
857# CONFIG_USB_ISIGHTFW is not set
858# CONFIG_USB_VST is not set
859# CONFIG_USB_GADGET is not set
860CONFIG_MMC=y
861# CONFIG_MMC_DEBUG is not set
862# CONFIG_MMC_UNSAFE_RESUME is not set
863
864#
865# MMC/SD/SDIO Card Drivers
866#
867CONFIG_MMC_BLOCK=y
868CONFIG_MMC_BLOCK_BOUNCE=y
869# CONFIG_SDIO_UART is not set
870# CONFIG_MMC_TEST is not set
871
872#
873# MMC/SD/SDIO Host Controller Drivers
874#
875# CONFIG_MMC_SDHCI is not set
876# CONFIG_MEMSTICK is not set
877# CONFIG_NEW_LEDS is not set
878# CONFIG_ACCESSIBILITY is not set
879# CONFIG_RTC_CLASS is not set
880# CONFIG_DMADEVICES is not set
881# CONFIG_UIO is not set
882# CONFIG_STAGING is not set
883
884#
885# File systems
886#
887CONFIG_EXT2_FS=y
888# CONFIG_EXT2_FS_XATTR is not set
889# CONFIG_EXT2_FS_XIP is not set
890CONFIG_EXT3_FS=y
891CONFIG_EXT3_FS_XATTR=y
892# CONFIG_EXT3_FS_POSIX_ACL is not set
893# CONFIG_EXT3_FS_SECURITY is not set
894# CONFIG_EXT4_FS is not set
895CONFIG_JBD=y
896CONFIG_FS_MBCACHE=y
897# CONFIG_REISERFS_FS is not set
898# CONFIG_JFS_FS is not set
899# CONFIG_FS_POSIX_ACL is not set
900CONFIG_FILE_LOCKING=y
901# CONFIG_XFS_FS is not set
902# CONFIG_OCFS2_FS is not set
903CONFIG_DNOTIFY=y
904CONFIG_INOTIFY=y
905CONFIG_INOTIFY_USER=y
906# CONFIG_QUOTA is not set
907# CONFIG_AUTOFS_FS is not set
908# CONFIG_AUTOFS4_FS is not set
909# CONFIG_FUSE_FS is not set
910
911#
912# CD-ROM/DVD Filesystems
913#
914# CONFIG_ISO9660_FS is not set
915# CONFIG_UDF_FS is not set
916
917#
918# DOS/FAT/NT Filesystems
919#
920CONFIG_FAT_FS=y
921# CONFIG_MSDOS_FS is not set
922CONFIG_VFAT_FS=y
923CONFIG_FAT_DEFAULT_CODEPAGE=437
924CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
925# CONFIG_NTFS_FS is not set
926
927#
928# Pseudo filesystems
929#
930CONFIG_PROC_FS=y
931CONFIG_PROC_KCORE=y
932CONFIG_PROC_SYSCTL=y
933CONFIG_PROC_PAGE_MONITOR=y
934CONFIG_SYSFS=y
935CONFIG_TMPFS=y
936# CONFIG_TMPFS_POSIX_ACL is not set
937CONFIG_HUGETLBFS=y
938CONFIG_HUGETLB_PAGE=y
939# CONFIG_CONFIGFS_FS is not set
940
941#
942# Miscellaneous filesystems
943#
944# CONFIG_ADFS_FS is not set
945# CONFIG_AFFS_FS is not set
946# CONFIG_HFS_FS is not set
947# CONFIG_HFSPLUS_FS is not set
948# CONFIG_BEFS_FS is not set
949# CONFIG_BFS_FS is not set
950# CONFIG_EFS_FS is not set
951# CONFIG_JFFS2_FS is not set
952CONFIG_CRAMFS=y
953# CONFIG_VXFS_FS is not set
954# CONFIG_MINIX_FS is not set
955# CONFIG_OMFS_FS is not set
956# CONFIG_HPFS_FS is not set
957# CONFIG_QNX4FS_FS is not set
958# CONFIG_ROMFS_FS is not set
959# CONFIG_SYSV_FS is not set
960# CONFIG_UFS_FS is not set
961CONFIG_NETWORK_FILESYSTEMS=y
962CONFIG_NFS_FS=y
963# CONFIG_NFS_V3 is not set
964# CONFIG_NFS_V4 is not set
965CONFIG_ROOT_NFS=y
966CONFIG_NFSD=y
967# CONFIG_NFSD_V3 is not set
968# CONFIG_NFSD_V4 is not set
969CONFIG_LOCKD=y
970CONFIG_EXPORTFS=y
971CONFIG_NFS_COMMON=y
972CONFIG_SUNRPC=y
973# CONFIG_SUNRPC_REGISTER_V4 is not set
974# CONFIG_RPCSEC_GSS_KRB5 is not set
975# CONFIG_RPCSEC_GSS_SPKM3 is not set
976# CONFIG_SMB_FS is not set
977# CONFIG_CIFS is not set
978# CONFIG_NCP_FS is not set
979# CONFIG_CODA_FS is not set
980# CONFIG_AFS_FS is not set
981
982#
983# Partition Types
984#
985# CONFIG_PARTITION_ADVANCED is not set
986CONFIG_MSDOS_PARTITION=y
987CONFIG_NLS=y
988CONFIG_NLS_DEFAULT="iso8859-1"
989CONFIG_NLS_CODEPAGE_437=y
990# CONFIG_NLS_CODEPAGE_737 is not set
991# CONFIG_NLS_CODEPAGE_775 is not set
992# CONFIG_NLS_CODEPAGE_850 is not set
993# CONFIG_NLS_CODEPAGE_852 is not set
994# CONFIG_NLS_CODEPAGE_855 is not set
995# CONFIG_NLS_CODEPAGE_857 is not set
996# CONFIG_NLS_CODEPAGE_860 is not set
997# CONFIG_NLS_CODEPAGE_861 is not set
998# CONFIG_NLS_CODEPAGE_862 is not set
999# CONFIG_NLS_CODEPAGE_863 is not set
1000# CONFIG_NLS_CODEPAGE_864 is not set
1001# CONFIG_NLS_CODEPAGE_865 is not set
1002# CONFIG_NLS_CODEPAGE_866 is not set
1003# CONFIG_NLS_CODEPAGE_869 is not set
1004# CONFIG_NLS_CODEPAGE_936 is not set
1005# CONFIG_NLS_CODEPAGE_950 is not set
1006CONFIG_NLS_CODEPAGE_932=y
1007# CONFIG_NLS_CODEPAGE_949 is not set
1008# CONFIG_NLS_CODEPAGE_874 is not set
1009# CONFIG_NLS_ISO8859_8 is not set
1010# CONFIG_NLS_CODEPAGE_1250 is not set
1011# CONFIG_NLS_CODEPAGE_1251 is not set
1012# CONFIG_NLS_ASCII is not set
1013CONFIG_NLS_ISO8859_1=y
1014# CONFIG_NLS_ISO8859_2 is not set
1015# CONFIG_NLS_ISO8859_3 is not set
1016# CONFIG_NLS_ISO8859_4 is not set
1017# CONFIG_NLS_ISO8859_5 is not set
1018# CONFIG_NLS_ISO8859_6 is not set
1019# CONFIG_NLS_ISO8859_7 is not set
1020# CONFIG_NLS_ISO8859_9 is not set
1021# CONFIG_NLS_ISO8859_13 is not set
1022# CONFIG_NLS_ISO8859_14 is not set
1023# CONFIG_NLS_ISO8859_15 is not set
1024# CONFIG_NLS_KOI8_R is not set
1025# CONFIG_NLS_KOI8_U is not set
1026# CONFIG_NLS_UTF8 is not set
1027# CONFIG_DLM is not set
1028
1029#
1030# Kernel hacking
1031#
1032CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1033# CONFIG_PRINTK_TIME is not set
1034# CONFIG_ENABLE_WARN_DEPRECATED is not set
1035# CONFIG_ENABLE_MUST_CHECK is not set
1036CONFIG_FRAME_WARN=1024
1037# CONFIG_MAGIC_SYSRQ is not set
1038# CONFIG_UNUSED_SYMBOLS is not set
1039# CONFIG_DEBUG_FS is not set
1040# CONFIG_HEADERS_CHECK is not set
1041# CONFIG_DEBUG_KERNEL is not set
1042# CONFIG_SLUB_DEBUG_ON is not set
1043# CONFIG_SLUB_STATS is not set
1044# CONFIG_DEBUG_BUGVERBOSE is not set
1045# CONFIG_DEBUG_MEMORY_INIT is not set
1046# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1047# CONFIG_LATENCYTOP is not set
1048# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1049CONFIG_NOP_TRACER=y
1050CONFIG_HAVE_FTRACE=y
1051# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
1052# CONFIG_SAMPLES is not set
1053# CONFIG_SH_STANDARD_BIOS is not set
1054# CONFIG_EARLY_SCIF_CONSOLE is not set
1055# CONFIG_SH_KGDB is not set
1056
1057#
1058# Security options
1059#
1060# CONFIG_KEYS is not set
1061# CONFIG_SECURITY is not set
1062# CONFIG_SECURITYFS is not set
1063# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1064CONFIG_CRYPTO=y
1065
1066#
1067# Crypto core or helper
1068#
1069# CONFIG_CRYPTO_FIPS is not set
1070CONFIG_CRYPTO_ALGAPI=y
1071CONFIG_CRYPTO_AEAD=y
1072CONFIG_CRYPTO_BLKCIPHER=y
1073CONFIG_CRYPTO_HASH=y
1074CONFIG_CRYPTO_RNG=y
1075CONFIG_CRYPTO_MANAGER=y
1076# CONFIG_CRYPTO_GF128MUL is not set
1077# CONFIG_CRYPTO_NULL is not set
1078# CONFIG_CRYPTO_CRYPTD is not set
1079# CONFIG_CRYPTO_AUTHENC is not set
1080# CONFIG_CRYPTO_TEST is not set
1081
1082#
1083# Authenticated Encryption with Associated Data
1084#
1085# CONFIG_CRYPTO_CCM is not set
1086# CONFIG_CRYPTO_GCM is not set
1087# CONFIG_CRYPTO_SEQIV is not set
1088
1089#
1090# Block modes
1091#
1092# CONFIG_CRYPTO_CBC is not set
1093# CONFIG_CRYPTO_CTR is not set
1094# CONFIG_CRYPTO_CTS is not set
1095CONFIG_CRYPTO_ECB=y
1096# CONFIG_CRYPTO_LRW is not set
1097# CONFIG_CRYPTO_PCBC is not set
1098# CONFIG_CRYPTO_XTS is not set
1099
1100#
1101# Hash modes
1102#
1103# CONFIG_CRYPTO_HMAC is not set
1104# CONFIG_CRYPTO_XCBC is not set
1105
1106#
1107# Digest
1108#
1109# CONFIG_CRYPTO_CRC32C is not set
1110# CONFIG_CRYPTO_MD4 is not set
1111# CONFIG_CRYPTO_MD5 is not set
1112CONFIG_CRYPTO_MICHAEL_MIC=y
1113# CONFIG_CRYPTO_RMD128 is not set
1114# CONFIG_CRYPTO_RMD160 is not set
1115# CONFIG_CRYPTO_RMD256 is not set
1116# CONFIG_CRYPTO_RMD320 is not set
1117# CONFIG_CRYPTO_SHA1 is not set
1118# CONFIG_CRYPTO_SHA256 is not set
1119# CONFIG_CRYPTO_SHA512 is not set
1120# CONFIG_CRYPTO_TGR192 is not set
1121# CONFIG_CRYPTO_WP512 is not set
1122
1123#
1124# Ciphers
1125#
1126CONFIG_CRYPTO_AES=y
1127# CONFIG_CRYPTO_ANUBIS is not set
1128CONFIG_CRYPTO_ARC4=y
1129# CONFIG_CRYPTO_BLOWFISH is not set
1130# CONFIG_CRYPTO_CAMELLIA is not set
1131# CONFIG_CRYPTO_CAST5 is not set
1132# CONFIG_CRYPTO_CAST6 is not set
1133# CONFIG_CRYPTO_DES is not set
1134# CONFIG_CRYPTO_FCRYPT is not set
1135# CONFIG_CRYPTO_KHAZAD is not set
1136# CONFIG_CRYPTO_SALSA20 is not set
1137# CONFIG_CRYPTO_SEED is not set
1138# CONFIG_CRYPTO_SERPENT is not set
1139# CONFIG_CRYPTO_TEA is not set
1140# CONFIG_CRYPTO_TWOFISH is not set
1141
1142#
1143# Compression
1144#
1145# CONFIG_CRYPTO_DEFLATE is not set
1146# CONFIG_CRYPTO_LZO is not set
1147
1148#
1149# Random Number Generation
1150#
1151# CONFIG_CRYPTO_ANSI_CPRNG is not set
1152CONFIG_CRYPTO_HW=y
1153
1154#
1155# Library routines
1156#
1157CONFIG_BITREVERSE=y
1158# CONFIG_CRC_CCITT is not set
1159# CONFIG_CRC16 is not set
1160# CONFIG_CRC_T10DIF is not set
1161# CONFIG_CRC_ITU_T is not set
1162CONFIG_CRC32=y
1163# CONFIG_CRC7 is not set
1164# CONFIG_LIBCRC32C is not set
1165CONFIG_ZLIB_INFLATE=y
1166CONFIG_PLIST=y
1167CONFIG_HAS_IOMEM=y
1168CONFIG_HAS_IOPORT=y
1169CONFIG_HAS_DMA=y
diff --git a/arch/sh/include/asm/byteorder.h b/arch/sh/include/asm/byteorder.h
index 4c13e6117563..f5fa0653ebc6 100644
--- a/arch/sh/include/asm/byteorder.h
+++ b/arch/sh/include/asm/byteorder.h
@@ -8,7 +8,15 @@
8#include <linux/compiler.h> 8#include <linux/compiler.h>
9#include <linux/types.h> 9#include <linux/types.h>
10 10
11static inline __attribute_const__ __u32 ___arch__swab32(__u32 x) 11#ifdef __LITTLE_ENDIAN__
12# define __LITTLE_ENDIAN
13#else
14# define __BIG_ENDIAN
15#endif
16
17#define __SWAB_64_THRU_32__
18
19static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
12{ 20{
13 __asm__( 21 __asm__(
14#ifdef __SH5__ 22#ifdef __SH5__
@@ -24,8 +32,9 @@ static inline __attribute_const__ __u32 ___arch__swab32(__u32 x)
24 32
25 return x; 33 return x;
26} 34}
35#define __arch_swab32 __arch_swab32
27 36
28static inline __attribute_const__ __u16 ___arch__swab16(__u16 x) 37static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
29{ 38{
30 __asm__( 39 __asm__(
31#ifdef __SH5__ 40#ifdef __SH5__
@@ -39,32 +48,21 @@ static inline __attribute_const__ __u16 ___arch__swab16(__u16 x)
39 48
40 return x; 49 return x;
41} 50}
51#define __arch_swab16 __arch_swab16
42 52
43static inline __u64 ___arch__swab64(__u64 val) 53static inline __u64 __arch_swab64(__u64 val)
44{ 54{
45 union { 55 union {
46 struct { __u32 a,b; } s; 56 struct { __u32 a,b; } s;
47 __u64 u; 57 __u64 u;
48 } v, w; 58 } v, w;
49 v.u = val; 59 v.u = val;
50 w.s.b = ___arch__swab32(v.s.a); 60 w.s.b = __arch_swab32(v.s.a);
51 w.s.a = ___arch__swab32(v.s.b); 61 w.s.a = __arch_swab32(v.s.b);
52 return w.u; 62 return w.u;
53} 63}
64#define __arch_swab64 __arch_swab64
54 65
55#define __arch__swab64(x) ___arch__swab64(x) 66#include <linux/byteorder.h>
56#define __arch__swab32(x) ___arch__swab32(x)
57#define __arch__swab16(x) ___arch__swab16(x)
58
59#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
60# define __BYTEORDER_HAS_U64__
61# define __SWAB_64_THRU_32__
62#endif
63
64#ifdef __LITTLE_ENDIAN__
65#include <linux/byteorder/little_endian.h>
66#else
67#include <linux/byteorder/big_endian.h>
68#endif
69 67
70#endif /* __ASM_SH_BYTEORDER_H */ 68#endif /* __ASM_SH_BYTEORDER_H */
diff --git a/arch/sh/include/asm/hd64465/gpio.h b/arch/sh/include/asm/hd64465/gpio.h
deleted file mode 100644
index a3cdca2713dd..000000000000
--- a/arch/sh/include/asm/hd64465/gpio.h
+++ /dev/null
@@ -1,46 +0,0 @@
1#ifndef _ASM_SH_HD64465_GPIO_
2#define _ASM_SH_HD64465_GPIO_ 1
3/*
4 * $Id: gpio.h,v 1.3 2003/05/04 19:30:14 lethal Exp $
5 *
6 * Hitachi HD64465 companion chip: General Purpose IO pins support.
7 * This layer enables other device drivers to configure GPIO
8 * pins, get and set their values, and register an interrupt
9 * routine for when input pins change in hardware.
10 *
11 * by Greg Banks <gbanks@pocketpenguins.com>
12 * (c) 2000 PocketPenguins Inc.
13 */
14#include <asm/hd64465.h>
15
16/* Macro to construct a portpin number (used in all
17 * subsequent functions) from a port letter and a pin
18 * number, e.g. HD64465_GPIO_PORTPIN('A', 5).
19 */
20#define HD64465_GPIO_PORTPIN(port,pin) (((port)-'A')<<3|(pin))
21
22/* Pin configuration constants for _configure() */
23#define HD64465_GPIO_FUNCTION2 0 /* use the pin's *other* function */
24#define HD64465_GPIO_OUT 1 /* output */
25#define HD64465_GPIO_IN_PULLUP 2 /* input, pull-up MOS on */
26#define HD64465_GPIO_IN 3 /* input */
27
28/* Configure a pin's direction */
29extern void hd64465_gpio_configure(int portpin, int direction);
30
31/* Get, set value */
32extern void hd64465_gpio_set_pin(int portpin, unsigned int value);
33extern unsigned int hd64465_gpio_get_pin(int portpin);
34extern void hd64465_gpio_set_port(int port, unsigned int value);
35extern unsigned int hd64465_gpio_get_port(int port);
36
37/* mode constants for _register_irq() */
38#define HD64465_GPIO_FALLING 0
39#define HD64465_GPIO_RISING 1
40
41/* Interrupt on external value change */
42extern void hd64465_gpio_register_irq(int portpin, int mode,
43 void (*handler)(int portpin, void *dev), void *dev);
44extern void hd64465_gpio_unregister_irq(int portpin);
45
46#endif /* _ASM_SH_HD64465_GPIO_ */
diff --git a/arch/sh/include/asm/hd64465/hd64465.h b/arch/sh/include/asm/hd64465/hd64465.h
deleted file mode 100644
index cfd0e803d2a2..000000000000
--- a/arch/sh/include/asm/hd64465/hd64465.h
+++ /dev/null
@@ -1,256 +0,0 @@
1#ifndef _ASM_SH_HD64465_
2#define _ASM_SH_HD64465_ 1
3/*
4 * $Id: hd64465.h,v 1.3 2003/05/04 19:30:15 lethal Exp $
5 *
6 * Hitachi HD64465 companion chip support
7 *
8 * by Greg Banks <gbanks@pocketpenguins.com>
9 * (c) 2000 PocketPenguins Inc.
10 *
11 * Derived from <asm/hd64461.h> which bore the message:
12 * Copyright (C) 2000 YAEGASHI Takeshi
13 */
14#include <asm/io.h>
15#include <asm/irq.h>
16
17/*
18 * Note that registers are defined here as virtual port numbers,
19 * which have no meaning except to get translated by hd64465_isa_port2addr()
20 * to an address in the range 0xb0000000-0xb3ffffff. Note that
21 * this translation happens to consist of adding the lower 16 bits
22 * of the virtual port number to 0xb0000000. Note also that the manual
23 * shows addresses as absolute physical addresses starting at 0x10000000,
24 * so e.g. the NIRR register is listed as 0x15000 here, 0x10005000 in the
25 * manual, and accessed using address 0xb0005000 - Greg.
26 */
27
28/* System registers */
29#define HD64465_REG_SRR 0x1000c /* System Revision Register */
30#define HD64465_REG_SDID 0x10010 /* System Device ID Reg */
31#define HD64465_SDID 0x8122 /* 64465 device ID */
32
33/* Power Management registers */
34#define HD64465_REG_SMSCR 0x10000 /* System Module Standby Control Reg */
35#define HD64465_SMSCR_PS2ST 0x4000 /* PS/2 Standby */
36#define HD64465_SMSCR_ADCST 0x1000 /* ADC Standby */
37#define HD64465_SMSCR_UARTST 0x0800 /* UART Standby */
38#define HD64465_SMSCR_SCDIST 0x0200 /* Serial Codec Standby */
39#define HD64465_SMSCR_PPST 0x0100 /* Parallel Port Standby */
40#define HD64465_SMSCR_PC0ST 0x0040 /* PCMCIA0 Standby */
41#define HD64465_SMSCR_PC1ST 0x0020 /* PCMCIA1 Standby */
42#define HD64465_SMSCR_AFEST 0x0010 /* AFE Standby */
43#define HD64465_SMSCR_TM0ST 0x0008 /* Timer0 Standby */
44#define HD64465_SMSCR_TM1ST 0x0004 /* Timer1 Standby */
45#define HD64465_SMSCR_IRDAST 0x0002 /* IRDA Standby */
46#define HD64465_SMSCR_KBCST 0x0001 /* Keyboard Controller Standby */
47
48/* Interrupt Controller registers */
49#define HD64465_REG_NIRR 0x15000 /* Interrupt Request Register */
50#define HD64465_REG_NIMR 0x15002 /* Interrupt Mask Register */
51#define HD64465_REG_NITR 0x15004 /* Interrupt Trigger Mode Register */
52
53/* Timer registers */
54#define HD64465_REG_TCVR1 0x16000 /* Timer 1 constant value register */
55#define HD64465_REG_TCVR0 0x16002 /* Timer 0 constant value register */
56#define HD64465_REG_TRVR1 0x16004 /* Timer 1 read value register */
57#define HD64465_REG_TRVR0 0x16006 /* Timer 0 read value register */
58#define HD64465_REG_TCR1 0x16008 /* Timer 1 control register */
59#define HD64465_REG_TCR0 0x1600A /* Timer 0 control register */
60#define HD64465_TCR_EADT 0x10 /* Enable ADTRIG# signal */
61#define HD64465_TCR_ETMO 0x08 /* Enable TMO signal */
62#define HD64465_TCR_PST_MASK 0x06 /* Clock Prescale */
63#define HD64465_TCR_PST_1 0x06 /* 1:1 */
64#define HD64465_TCR_PST_4 0x04 /* 1:4 */
65#define HD64465_TCR_PST_8 0x02 /* 1:8 */
66#define HD64465_TCR_PST_16 0x00 /* 1:16 */
67#define HD64465_TCR_TSTP 0x01 /* Start/Stop timer */
68#define HD64465_REG_TIRR 0x1600C /* Timer interrupt request register */
69#define HD64465_REG_TIDR 0x1600E /* Timer interrupt disable register */
70#define HD64465_REG_PWM1CS 0x16010 /* PWM 1 clock scale register */
71#define HD64465_REG_PWM1LPC 0x16012 /* PWM 1 low pulse width counter register */
72#define HD64465_REG_PWM1HPC 0x16014 /* PWM 1 high pulse width counter register */
73#define HD64465_REG_PWM0CS 0x16018 /* PWM 0 clock scale register */
74#define HD64465_REG_PWM0LPC 0x1601A /* PWM 0 low pulse width counter register */
75#define HD64465_REG_PWM0HPC 0x1601C /* PWM 0 high pulse width counter register */
76
77/* Analog/Digital Converter registers */
78#define HD64465_REG_ADDRA 0x1E000 /* A/D data register A */
79#define HD64465_REG_ADDRB 0x1E002 /* A/D data register B */
80#define HD64465_REG_ADDRC 0x1E004 /* A/D data register C */
81#define HD64465_REG_ADDRD 0x1E006 /* A/D data register D */
82#define HD64465_REG_ADCSR 0x1E008 /* A/D control/status register */
83#define HD64465_ADCSR_ADF 0x80 /* A/D End Flag */
84#define HD64465_ADCSR_ADST 0x40 /* A/D Start Flag */
85#define HD64465_ADCSR_ADIS 0x20 /* A/D Interrupt Status */
86#define HD64465_ADCSR_TRGE 0x10 /* A/D Trigger Enable */
87#define HD64465_ADCSR_ADIE 0x08 /* A/D Interrupt Enable */
88#define HD64465_ADCSR_SCAN 0x04 /* A/D Scan Mode */
89#define HD64465_ADCSR_CH_MASK 0x03 /* A/D Channel */
90#define HD64465_REG_ADCALCR 0x1E00A /* A/D calibration sample control */
91#define HD64465_REG_ADCAL 0x1E00C /* A/D calibration data register */
92
93
94/* General Purpose I/O ports registers */
95#define HD64465_REG_GPACR 0x14000 /* Port A Control Register */
96#define HD64465_REG_GPBCR 0x14002 /* Port B Control Register */
97#define HD64465_REG_GPCCR 0x14004 /* Port C Control Register */
98#define HD64465_REG_GPDCR 0x14006 /* Port D Control Register */
99#define HD64465_REG_GPECR 0x14008 /* Port E Control Register */
100#define HD64465_REG_GPADR 0x14010 /* Port A Data Register */
101#define HD64465_REG_GPBDR 0x14012 /* Port B Data Register */
102#define HD64465_REG_GPCDR 0x14014 /* Port C Data Register */
103#define HD64465_REG_GPDDR 0x14016 /* Port D Data Register */
104#define HD64465_REG_GPEDR 0x14018 /* Port E Data Register */
105#define HD64465_REG_GPAICR 0x14020 /* Port A Interrupt Control Register */
106#define HD64465_REG_GPBICR 0x14022 /* Port B Interrupt Control Register */
107#define HD64465_REG_GPCICR 0x14024 /* Port C Interrupt Control Register */
108#define HD64465_REG_GPDICR 0x14026 /* Port D Interrupt Control Register */
109#define HD64465_REG_GPEICR 0x14028 /* Port E Interrupt Control Register */
110#define HD64465_REG_GPAISR 0x14040 /* Port A Interrupt Status Register */
111#define HD64465_REG_GPBISR 0x14042 /* Port B Interrupt Status Register */
112#define HD64465_REG_GPCISR 0x14044 /* Port C Interrupt Status Register */
113#define HD64465_REG_GPDISR 0x14046 /* Port D Interrupt Status Register */
114#define HD64465_REG_GPEISR 0x14048 /* Port E Interrupt Status Register */
115
116/* PCMCIA bridge interface */
117#define HD64465_REG_PCC0ISR 0x12000 /* socket 0 interface status */
118#define HD64465_PCCISR_PREADY 0x80 /* mem card ready / io card IREQ */
119#define HD64465_PCCISR_PIREQ 0x80
120#define HD64465_PCCISR_PMWP 0x40 /* mem card write-protected */
121#define HD64465_PCCISR_PVS2 0x20 /* voltage select pin 2 */
122#define HD64465_PCCISR_PVS1 0x10 /* voltage select pin 1 */
123#define HD64465_PCCISR_PCD_MASK 0x0c /* card detect */
124#define HD64465_PCCISR_PBVD_MASK 0x03 /* battery voltage */
125#define HD64465_PCCISR_PBVD_BATGOOD 0x03 /* battery good */
126#define HD64465_PCCISR_PBVD_BATWARN 0x01 /* battery low warning */
127#define HD64465_PCCISR_PBVD_BATDEAD1 0x02 /* battery dead */
128#define HD64465_PCCISR_PBVD_BATDEAD2 0x00 /* battery dead */
129#define HD64465_REG_PCC0GCR 0x12002 /* socket 0 general control */
130#define HD64465_PCCGCR_PDRV 0x80 /* output drive */
131#define HD64465_PCCGCR_PCCR 0x40 /* PC card reset */
132#define HD64465_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */
133#define HD64465_PCCGCR_PVCC0 0x10 /* voltage control pin VCC0SEL0 */
134#define HD64465_PCCGCR_PMMOD 0x08 /* memory mode */
135#define HD64465_PCCGCR_PPA25 0x04 /* pin A25 */
136#define HD64465_PCCGCR_PPA24 0x02 /* pin A24 */
137#define HD64465_PCCGCR_PREG 0x01 /* ping PCC0REG# */
138#define HD64465_REG_PCC0CSCR 0x12004 /* socket 0 card status change */
139#define HD64465_PCCCSCR_PSCDI 0x80 /* sw card detect intr */
140#define HD64465_PCCCSCR_PSWSEL 0x40 /* power select */
141#define HD64465_PCCCSCR_PIREQ 0x20 /* IREQ intr req */
142#define HD64465_PCCCSCR_PSC 0x10 /* STSCHG (status change) pin */
143#define HD64465_PCCCSCR_PCDC 0x08 /* CD (card detect) change */
144#define HD64465_PCCCSCR_PRC 0x04 /* ready change */
145#define HD64465_PCCCSCR_PBW 0x02 /* battery warning change */
146#define HD64465_PCCCSCR_PBD 0x01 /* battery dead change */
147#define HD64465_REG_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */
148#define HD64465_PCCCSCIER_PCRE 0x80 /* change reset enable */
149#define HD64465_PCCCSCIER_PIREQE_MASK 0x60 /* IREQ enable */
150#define HD64465_PCCCSCIER_PIREQE_DISABLED 0x00 /* IREQ disabled */
151#define HD64465_PCCCSCIER_PIREQE_LEVEL 0x20 /* IREQ level-triggered */
152#define HD64465_PCCCSCIER_PIREQE_FALLING 0x40 /* IREQ falling-edge-trig */
153#define HD64465_PCCCSCIER_PIREQE_RISING 0x60 /* IREQ rising-edge-trig */
154#define HD64465_PCCCSCIER_PSCE 0x10 /* status change enable */
155#define HD64465_PCCCSCIER_PCDE 0x08 /* card detect change enable */
156#define HD64465_PCCCSCIER_PRE 0x04 /* ready change enable */
157#define HD64465_PCCCSCIER_PBWE 0x02 /* battery warn change enable */
158#define HD64465_PCCCSCIER_PBDE 0x01 /* battery dead change enable*/
159#define HD64465_REG_PCC0SCR 0x12008 /* socket 0 software control */
160#define HD64465_PCCSCR_SHDN 0x10 /* TPS2206 SHutDowN pin */
161#define HD64465_PCCSCR_SWP 0x01 /* write protect */
162#define HD64465_REG_PCCPSR 0x1200A /* serial power switch control */
163#define HD64465_REG_PCC1ISR 0x12010 /* socket 1 interface status */
164#define HD64465_REG_PCC1GCR 0x12012 /* socket 1 general control */
165#define HD64465_REG_PCC1CSCR 0x12014 /* socket 1 card status change */
166#define HD64465_REG_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */
167#define HD64465_REG_PCC1SCR 0x12018 /* socket 1 software control */
168
169
170/* PS/2 Keyboard and mouse controller -- *not* register compatible */
171#define HD64465_REG_KBCSR 0x1dc00 /* Keyboard Control/Status reg */
172#define HD64465_KBCSR_KBCIE 0x8000 /* KBCK Input Enable */
173#define HD64465_KBCSR_KBCOE 0x4000 /* KBCK Output Enable */
174#define HD64465_KBCSR_KBDOE 0x2000 /* KB DATA Output Enable */
175#define HD64465_KBCSR_KBCD 0x1000 /* KBCK Driven */
176#define HD64465_KBCSR_KBDD 0x0800 /* KB DATA Driven */
177#define HD64465_KBCSR_KBCS 0x0400 /* KBCK pin Status */
178#define HD64465_KBCSR_KBDS 0x0200 /* KB DATA pin Status */
179#define HD64465_KBCSR_KBDP 0x0100 /* KB DATA Parity bit */
180#define HD64465_KBCSR_KBD_MASK 0x00ff /* KD DATA shift reg */
181#define HD64465_REG_KBISR 0x1dc04 /* Keyboard Interrupt Status reg */
182#define HD64465_KBISR_KBRDF 0x0001 /* KB Received Data Full */
183#define HD64465_REG_MSCSR 0x1dc10 /* Mouse Control/Status reg */
184#define HD64465_REG_MSISR 0x1dc14 /* Mouse Interrupt Status reg */
185
186
187/*
188 * Logical address at which the HD64465 is mapped. Note that this
189 * should always be in the P2 segment (uncached and untranslated).
190 */
191#ifndef CONFIG_HD64465_IOBASE
192#define CONFIG_HD64465_IOBASE 0xb0000000
193#endif
194/*
195 * The HD64465 multiplexes all its modules' interrupts onto
196 * this single interrupt.
197 */
198#ifndef CONFIG_HD64465_IRQ
199#define CONFIG_HD64465_IRQ 5
200#endif
201
202
203#define _HD64465_IO_MASK 0xf8000000
204#define is_hd64465_addr(addr) \
205 ((addr & _HD64465_IO_MASK) == (CONFIG_HD64465_IOBASE & _HD64465_IO_MASK))
206
207/*
208 * A range of 16 virtual interrupts generated by
209 * demuxing the HD64465 muxed interrupt.
210 */
211#define HD64465_IRQ_BASE OFFCHIP_IRQ_BASE
212#define HD64465_IRQ_NUM 16
213#define HD64465_IRQ_ADC (HD64465_IRQ_BASE+0)
214#define HD64465_IRQ_USB (HD64465_IRQ_BASE+1)
215#define HD64465_IRQ_SCDI (HD64465_IRQ_BASE+2)
216#define HD64465_IRQ_PARALLEL (HD64465_IRQ_BASE+3)
217/* bit 4 is reserved */
218#define HD64465_IRQ_UART (HD64465_IRQ_BASE+5)
219#define HD64465_IRQ_IRDA (HD64465_IRQ_BASE+6)
220#define HD64465_IRQ_PS2MOUSE (HD64465_IRQ_BASE+7)
221#define HD64465_IRQ_KBC (HD64465_IRQ_BASE+8)
222#define HD64465_IRQ_TIMER1 (HD64465_IRQ_BASE+9)
223#define HD64465_IRQ_TIMER0 (HD64465_IRQ_BASE+10)
224#define HD64465_IRQ_GPIO (HD64465_IRQ_BASE+11)
225#define HD64465_IRQ_AFE (HD64465_IRQ_BASE+12)
226#define HD64465_IRQ_PCMCIA1 (HD64465_IRQ_BASE+13)
227#define HD64465_IRQ_PCMCIA0 (HD64465_IRQ_BASE+14)
228#define HD64465_IRQ_PS2KBD (HD64465_IRQ_BASE+15)
229
230/* Constants for PCMCIA mappings */
231#define HD64465_PCC_WINDOW 0x01000000
232
233#define HD64465_PCC0_BASE 0xb8000000 /* area 6 */
234#define HD64465_PCC0_ATTR (HD64465_PCC0_BASE)
235#define HD64465_PCC0_COMM (HD64465_PCC0_BASE+HD64465_PCC_WINDOW)
236#define HD64465_PCC0_IO (HD64465_PCC0_BASE+2*HD64465_PCC_WINDOW)
237
238#define HD64465_PCC1_BASE 0xb4000000 /* area 5 */
239#define HD64465_PCC1_ATTR (HD64465_PCC1_BASE)
240#define HD64465_PCC1_COMM (HD64465_PCC1_BASE+HD64465_PCC_WINDOW)
241#define HD64465_PCC1_IO (HD64465_PCC1_BASE+2*HD64465_PCC_WINDOW)
242
243/*
244 * Base of USB controller interface (as memory)
245 */
246#define HD64465_USB_BASE (CONFIG_HD64465_IOBASE+0xb000)
247#define HD64465_USB_LEN 0x1000
248/*
249 * Base of embedded SRAM, used for USB controller.
250 */
251#define HD64465_SRAM_BASE (CONFIG_HD64465_IOBASE+0x9000)
252#define HD64465_SRAM_LEN 0x1000
253
254
255
256#endif /* _ASM_SH_HD64465_ */
diff --git a/arch/sh/include/asm/hd64465/io.h b/arch/sh/include/asm/hd64465/io.h
deleted file mode 100644
index 139f1472e5bb..000000000000
--- a/arch/sh/include/asm/hd64465/io.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * include/asm-sh/hd64465/io.h
3 *
4 * By Greg Banks <gbanks@pocketpenguins.com>
5 * (c) 2000 PocketPenguins Inc.
6 *
7 * Derived from io_hd64461.h, which bore the message:
8 * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
9 *
10 * May be copied or modified under the terms of the GNU General Public
11 * License. See linux/COPYING for more information.
12 *
13 * IO functions for an HD64465 "Windows CE Intelligent Peripheral Controller".
14 */
15
16#ifndef _ASM_SH_IO_HD64465_H
17#define _ASM_SH_IO_HD64465_H
18
19extern unsigned char hd64465_inb(unsigned long port);
20extern unsigned short hd64465_inw(unsigned long port);
21extern unsigned int hd64465_inl(unsigned long port);
22
23extern void hd64465_outb(unsigned char value, unsigned long port);
24extern void hd64465_outw(unsigned short value, unsigned long port);
25extern void hd64465_outl(unsigned int value, unsigned long port);
26
27extern unsigned char hd64465_inb_p(unsigned long port);
28extern void hd64465_outb_p(unsigned char value, unsigned long port);
29
30extern unsigned long hd64465_isa_port2addr(unsigned long offset);
31extern int hd64465_irq_demux(int irq);
32/* Provision for generic secondary demux step -- used by PCMCIA code */
33extern void hd64465_register_irq_demux(int irq,
34 int (*demux)(int irq, void *dev), void *dev);
35extern void hd64465_unregister_irq_demux(int irq);
36/* Set this variable to 1 to see port traffic */
37extern int hd64465_io_debug;
38/* Map a range of ports to a range of kernel virtual memory.
39 */
40extern void hd64465_port_map(unsigned short baseport, unsigned int nports,
41 unsigned long addr, unsigned char shift);
42extern void hd64465_port_unmap(unsigned short baseport, unsigned int nports);
43
44#endif /* _ASM_SH_IO_HD64465_H */
diff --git a/arch/sh/include/asm/serial.h b/arch/sh/include/asm/serial.h
index e13cc948ee60..11f854dd1363 100644
--- a/arch/sh/include/asm/serial.h
+++ b/arch/sh/include/asm/serial.h
@@ -7,8 +7,6 @@
7#ifndef _ASM_SERIAL_H 7#ifndef _ASM_SERIAL_H
8#define _ASM_SERIAL_H 8#define _ASM_SERIAL_H
9 9
10#include <linux/kernel.h>
11
12/* 10/*
13 * This assumes you have a 1.8432 MHz clock for your UART. 11 * This assumes you have a 1.8432 MHz clock for your UART.
14 * 12 *
@@ -18,19 +16,4 @@
18 */ 16 */
19#define BASE_BAUD ( 1843200 / 16 ) 17#define BASE_BAUD ( 1843200 / 16 )
20 18
21#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
22
23#ifdef CONFIG_HD64465
24#include <asm/hd64465/hd64465.h>
25
26#define SERIAL_PORT_DFNS \
27 /* UART CLK PORT IRQ FLAGS */ \
28 { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */
29
30#else
31
32#define SERIAL_PORT_DFNS
33
34#endif
35
36#endif /* _ASM_SERIAL_H */ 19#endif /* _ASM_SERIAL_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/rtc.h b/arch/sh/include/cpu-sh4/cpu/rtc.h
index 25b1e6adfe8c..95e6fb76c24d 100644
--- a/arch/sh/include/cpu-sh4/cpu/rtc.h
+++ b/arch/sh/include/cpu-sh4/cpu/rtc.h
@@ -1,7 +1,7 @@
1#ifndef __ASM_SH_CPU_SH4_RTC_H 1#ifndef __ASM_SH_CPU_SH4_RTC_H
2#define __ASM_SH_CPU_SH4_RTC_H 2#define __ASM_SH_CPU_SH4_RTC_H
3 3
4#ifdef CONFIG_CPU_SUBTYPE_SH7723 4#if defined(CONFIG_CPU_SUBTYPE_SH7722) || defined(CONFIG_CPU_SUBTYPE_SH7723)
5#define rtc_reg_size sizeof(u16) 5#define rtc_reg_size sizeof(u16)
6#else 6#else
7#define rtc_reg_size sizeof(u32) 7#define rtc_reg_size sizeof(u32)
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 6851dba02f31..e17db39b97aa 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -36,6 +36,32 @@ static struct platform_device iic_device = {
36 .resource = iic_resources, 36 .resource = iic_resources,
37}; 37};
38 38
39static struct resource usb_host_resources[] = {
40 [0] = {
41 .name = "r8a66597_hcd",
42 .start = 0xa4d80000,
43 .end = 0xa4d800ff,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = {
47 .name = "r8a66597_hcd",
48 .start = 65,
49 .end = 65,
50 .flags = IORESOURCE_IRQ,
51 },
52};
53
54static struct platform_device usb_host_device = {
55 .name = "r8a66597_hcd",
56 .id = -1,
57 .dev = {
58 .dma_mask = NULL,
59 .coherent_dma_mask = 0xffffffff,
60 },
61 .num_resources = ARRAY_SIZE(usb_host_resources),
62 .resource = usb_host_resources,
63};
64
39static struct uio_info vpu_platform_data = { 65static struct uio_info vpu_platform_data = {
40 .name = "VPU5", 66 .name = "VPU5",
41 .version = "0", 67 .version = "0",
@@ -142,6 +168,7 @@ static struct platform_device sci_device = {
142static struct platform_device *sh7366_devices[] __initdata = { 168static struct platform_device *sh7366_devices[] __initdata = {
143 &iic_device, 169 &iic_device,
144 &sci_device, 170 &sci_device,
171 &usb_host_device,
145 &vpu_device, 172 &vpu_device,
146 &veu0_device, 173 &veu0_device,
147 &veu1_device, 174 &veu1_device,
@@ -158,6 +185,7 @@ static int __init sh7366_devices_setup(void)
158 clk_always_enable("mstp022"); /* INTC */ 185 clk_always_enable("mstp022"); /* INTC */
159 clk_always_enable("mstp020"); /* SuperHyway */ 186 clk_always_enable("mstp020"); /* SuperHyway */
160 clk_always_enable("mstp109"); /* I2C */ 187 clk_always_enable("mstp109"); /* I2C */
188 clk_always_enable("mstp211"); /* USB */
161 clk_always_enable("mstp207"); /* VEU-2 */ 189 clk_always_enable("mstp207"); /* VEU-2 */
162 clk_always_enable("mstp202"); /* VEU-1 */ 190 clk_always_enable("mstp202"); /* VEU-1 */
163 clk_always_enable("mstp201"); /* VPU */ 191 clk_always_enable("mstp201"); /* VPU */
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index de1ede92176e..ef77ee1d9f53 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH7722 Setup 2 * SH7722 Setup
3 * 3 *
4 * Copyright (C) 2006 - 2007 Paul Mundt 4 * Copyright (C) 2006 - 2008 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
@@ -16,6 +16,36 @@
16#include <asm/clock.h> 16#include <asm/clock.h>
17#include <asm/mmzone.h> 17#include <asm/mmzone.h>
18 18
19static struct resource rtc_resources[] = {
20 [0] = {
21 .start = 0xa465fec0,
22 .end = 0xa465fec0 + 0x58 - 1,
23 .flags = IORESOURCE_IO,
24 },
25 [1] = {
26 /* Period IRQ */
27 .start = 45,
28 .flags = IORESOURCE_IRQ,
29 },
30 [2] = {
31 /* Carry IRQ */
32 .start = 46,
33 .flags = IORESOURCE_IRQ,
34 },
35 [3] = {
36 /* Alarm IRQ */
37 .start = 44,
38 .flags = IORESOURCE_IRQ,
39 },
40};
41
42static struct platform_device rtc_device = {
43 .name = "sh-rtc",
44 .id = -1,
45 .num_resources = ARRAY_SIZE(rtc_resources),
46 .resource = rtc_resources,
47};
48
19static struct resource usbf_resources[] = { 49static struct resource usbf_resources[] = {
20 [0] = { 50 [0] = {
21 .name = "m66592_udc", 51 .name = "m66592_udc",
@@ -150,6 +180,7 @@ static struct platform_device sci_device = {
150}; 180};
151 181
152static struct platform_device *sh7722_devices[] __initdata = { 182static struct platform_device *sh7722_devices[] __initdata = {
183 &rtc_device,
153 &usbf_device, 184 &usbf_device,
154 &iic_device, 185 &iic_device,
155 &sci_device, 186 &sci_device,
@@ -202,7 +233,6 @@ enum {
202 IRDA, JPU, LCDC, 233 IRDA, JPU, LCDC,
203 234
204 /* interrupt groups */ 235 /* interrupt groups */
205
206 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI, 236 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
207}; 237};
208 238
diff --git a/arch/sh/kernel/entry-common.S b/arch/sh/kernel/entry-common.S
index 1a5cf9dd82de..5b7efc4016fa 100644
--- a/arch/sh/kernel/entry-common.S
+++ b/arch/sh/kernel/entry-common.S
@@ -372,7 +372,7 @@ syscall_exit:
3727: .long do_syscall_trace_enter 3727: .long do_syscall_trace_enter
3738: .long do_syscall_trace_leave 3738: .long do_syscall_trace_leave
374 374
375#ifdef CONFIG_FTRACE 375#ifdef CONFIG_FUNCTION_TRACER
376 .align 2 376 .align 2
377 .globl _mcount 377 .globl _mcount
378 .type _mcount,@function 378 .type _mcount,@function
@@ -414,4 +414,4 @@ skip_trace:
414ftrace_stub: 414ftrace_stub:
415 rts 415 rts
416 nop 416 nop
417#endif /* CONFIG_FTRACE */ 417#endif /* CONFIG_FUNCTION_TRACER */
diff --git a/arch/sh/kernel/sh_ksyms_32.c b/arch/sh/kernel/sh_ksyms_32.c
index d366a7443720..92ae5e6c099e 100644
--- a/arch/sh/kernel/sh_ksyms_32.c
+++ b/arch/sh/kernel/sh_ksyms_32.c
@@ -50,7 +50,10 @@ EXPORT_SYMBOL(__udelay);
50EXPORT_SYMBOL(__ndelay); 50EXPORT_SYMBOL(__ndelay);
51EXPORT_SYMBOL(__const_udelay); 51EXPORT_SYMBOL(__const_udelay);
52 52
53#define DECLARE_EXPORT(name) extern void name(void);EXPORT_SYMBOL(name) 53#define DECLARE_EXPORT(name) \
54 extern void name(void);EXPORT_SYMBOL(name)
55#define MAYBE_DECLARE_EXPORT(name) \
56 extern void name(void) __weak;EXPORT_SYMBOL(name)
54 57
55/* These symbols are generated by the compiler itself */ 58/* These symbols are generated by the compiler itself */
56DECLARE_EXPORT(__udivsi3); 59DECLARE_EXPORT(__udivsi3);
@@ -109,10 +112,8 @@ DECLARE_EXPORT(__movmemSI12_i4);
109 * compiler which include backported patches. 112 * compiler which include backported patches.
110 */ 113 */
111DECLARE_EXPORT(__udiv_qrnnd_16); 114DECLARE_EXPORT(__udiv_qrnnd_16);
112#if !defined(CONFIG_CPU_SH2) 115MAYBE_DECLARE_EXPORT(__sdivsi3_i4i);
113DECLARE_EXPORT(__sdivsi3_i4i); 116MAYBE_DECLARE_EXPORT(__udivsi3_i4i);
114DECLARE_EXPORT(__udivsi3_i4i);
115#endif
116#endif 117#endif
117#else /* GCC 3.x */ 118#else /* GCC 3.x */
118DECLARE_EXPORT(__movstr_i4_even); 119DECLARE_EXPORT(__movstr_i4_even);
@@ -133,7 +134,7 @@ EXPORT_SYMBOL(flush_dcache_page);
133EXPORT_SYMBOL(clear_user_page); 134EXPORT_SYMBOL(clear_user_page);
134#endif 135#endif
135 136
136#ifdef CONFIG_FTRACE 137#ifdef CONFIG_FUNCTION_TRACER
137EXPORT_SYMBOL(mcount); 138EXPORT_SYMBOL(mcount);
138#endif 139#endif
139EXPORT_SYMBOL(csum_partial); 140EXPORT_SYMBOL(csum_partial);
diff --git a/arch/sh/mm/cache-sh2a.c b/arch/sh/mm/cache-sh2a.c
index 62c0c5f35120..24d86a794065 100644
--- a/arch/sh/mm/cache-sh2a.c
+++ b/arch/sh/mm/cache-sh2a.c
@@ -59,7 +59,7 @@ void __flush_purge_region(void *start, int size)
59 59
60 for (v = begin; v < end; v+=L1_CACHE_BYTES) { 60 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
61 ctrl_outl((v & CACHE_PHYSADDR_MASK), 61 ctrl_outl((v & CACHE_PHYSADDR_MASK),
62 CACHE_OC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008); 62 CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
63 } 63 }
64 back_to_cached(); 64 back_to_cached();
65 local_irq_restore(flags); 65 local_irq_restore(flags);
@@ -82,14 +82,14 @@ void __flush_invalidate_region(void *start, int size)
82 /* I-cache invalidate */ 82 /* I-cache invalidate */
83 for (v = begin; v < end; v+=L1_CACHE_BYTES) { 83 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
84 ctrl_outl((v & CACHE_PHYSADDR_MASK), 84 ctrl_outl((v & CACHE_PHYSADDR_MASK),
85 CACHE_IC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008); 85 CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
86 } 86 }
87#else 87#else
88 for (v = begin; v < end; v+=L1_CACHE_BYTES) { 88 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
89 ctrl_outl((v & CACHE_PHYSADDR_MASK), 89 ctrl_outl((v & CACHE_PHYSADDR_MASK),
90 CACHE_IC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008); 90 CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
91 ctrl_outl((v & CACHE_PHYSADDR_MASK), 91 ctrl_outl((v & CACHE_PHYSADDR_MASK),
92 CACHE_OC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008); 92 CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
93 } 93 }
94#endif 94#endif
95 back_to_cached(); 95 back_to_cached();
diff --git a/arch/sh/oprofile/op_model_sh7750.c b/arch/sh/oprofile/op_model_sh7750.c
index 6b9a98e07004..008b3b03750a 100644
--- a/arch/sh/oprofile/op_model_sh7750.c
+++ b/arch/sh/oprofile/op_model_sh7750.c
@@ -255,10 +255,9 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
255 return -ENODEV; 255 return -ENODEV;
256 256
257 ops = &sh7750_perf_counter_ops; 257 ops = &sh7750_perf_counter_ops;
258 ops->cpu_type = (char *)get_cpu_subtype(&current_cpu_data); 258 ops->cpu_type = "sh/sh7750";
259 259
260 printk(KERN_INFO "oprofile: using SH-4 (%s) performance monitoring.\n", 260 printk(KERN_INFO "oprofile: using SH-4 performance monitoring.\n");
261 sh7750_perf_counter_ops.cpu_type);
262 261
263 /* Clear the counters */ 262 /* Clear the counters */
264 ctrl_outw(ctrl_inw(PMCR1) | PMCR_PMCLR, PMCR1); 263 ctrl_outw(ctrl_inw(PMCR1) | PMCR_PMCLR, PMCR1);
@@ -270,4 +269,3 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
270void oprofile_arch_exit(void) 269void oprofile_arch_exit(void)
271{ 270{
272} 271}
273
diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types
index d4fb11f7e2ee..d0c2928d1066 100644
--- a/arch/sh/tools/mach-types
+++ b/arch/sh/tools/mach-types
@@ -13,7 +13,6 @@ RTS7751R2D SH_RTS7751R2D
13# List of companion chips / MFDs. 13# List of companion chips / MFDs.
14# 14#
15HD64461 HD64461 15HD64461 HD64461
16HD64465 HD64465
17 16
18# 17#
19# List of boards. 18# List of boards.
diff --git a/drivers/cdrom/gdrom.c b/drivers/cdrom/gdrom.c
index 9aaa86b232b1..2eecb779437b 100644
--- a/drivers/cdrom/gdrom.c
+++ b/drivers/cdrom/gdrom.c
@@ -495,9 +495,10 @@ static int gdrom_bdops_open(struct block_device *bdev, fmode_t mode)
495 return cdrom_open(gd.cd_info, bdev, mode); 495 return cdrom_open(gd.cd_info, bdev, mode);
496} 496}
497 497
498static int gdrom_bdops_release(struct block_device *bdev, fmode_t mode) 498static int gdrom_bdops_release(struct gendisk *disk, fmode_t mode)
499{ 499{
500 return cdrom_release(gd.cd_info, mode); 500 cdrom_release(gd.cd_info, mode);
501 return 0;
501} 502}
502 503
503static int gdrom_bdops_mediachanged(struct gendisk *disk) 504static int gdrom_bdops_mediachanged(struct gendisk *disk)
diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
index f57eeae3830a..222904411a13 100644
--- a/drivers/pcmcia/Kconfig
+++ b/drivers/pcmcia/Kconfig
@@ -188,10 +188,6 @@ config PCMCIA_M8XX
188 188
189 This driver is also available as a module called m8xx_pcmcia. 189 This driver is also available as a module called m8xx_pcmcia.
190 190
191config HD64465_PCMCIA
192 tristate "HD64465 host bridge support"
193 depends on HD64465 && PCMCIA
194
195config PCMCIA_AU1X00 191config PCMCIA_AU1X00
196 tristate "Au1x00 pcmcia support" 192 tristate "Au1x00 pcmcia support"
197 depends on SOC_AU1X00 && PCMCIA 193 depends on SOC_AU1X00 && PCMCIA
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
index 23e492bf75cf..238629ad7f7c 100644
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -22,7 +22,6 @@ obj-$(CONFIG_I82365) += i82365.o
22obj-$(CONFIG_I82092) += i82092.o 22obj-$(CONFIG_I82092) += i82092.o
23obj-$(CONFIG_TCIC) += tcic.o 23obj-$(CONFIG_TCIC) += tcic.o
24obj-$(CONFIG_PCMCIA_M8XX) += m8xx_pcmcia.o 24obj-$(CONFIG_PCMCIA_M8XX) += m8xx_pcmcia.o
25obj-$(CONFIG_HD64465_PCMCIA) += hd64465_ss.o
26obj-$(CONFIG_PCMCIA_SA1100) += sa11xx_core.o sa1100_cs.o 25obj-$(CONFIG_PCMCIA_SA1100) += sa11xx_core.o sa1100_cs.o
27obj-$(CONFIG_PCMCIA_SA1111) += sa11xx_core.o sa1111_cs.o 26obj-$(CONFIG_PCMCIA_SA1111) += sa11xx_core.o sa1111_cs.o
28obj-$(CONFIG_M32R_PCC) += m32r_pcc.o 27obj-$(CONFIG_M32R_PCC) += m32r_pcc.o
diff --git a/drivers/pcmcia/hd64465_ss.c b/drivers/pcmcia/hd64465_ss.c
deleted file mode 100644
index 9ef69cdb3183..000000000000
--- a/drivers/pcmcia/hd64465_ss.c
+++ /dev/null
@@ -1,939 +0,0 @@
1/*
2 * Device driver for the PCMCIA controller module of the
3 * Hitachi HD64465 handheld companion chip.
4 *
5 * Note that the HD64465 provides a very thin PCMCIA host bridge
6 * layer, requiring a lot of the work of supporting cards to be
7 * performed by the processor. For example: mapping of card
8 * interrupts to processor IRQs is done by IRQ demuxing software;
9 * IO and memory mappings are fixed; setting voltages according
10 * to card Voltage Select pins etc is done in software.
11 *
12 * Note also that this driver uses only the simple, fixed,
13 * 16MB, 16-bit wide mappings to PCMCIA spaces defined by the
14 * HD64465. Larger mappings, smaller mappings, or mappings of
15 * different width to the same socket, are all possible only by
16 * involving the SH7750's MMU, which is considered unnecessary here.
17 * The downside is that it may be possible for some drivers to
18 * break because they need or expect 8-bit mappings.
19 *
20 * This driver currently supports only the following configuration:
21 * SH7750 CPU, HD64465, TPS2206 voltage control chip.
22 *
23 * by Greg Banks <gbanks@pocketpenguins.com>
24 * (c) 2000 PocketPenguins Inc
25 */
26
27#include <linux/types.h>
28#include <linux/module.h>
29#include <linux/init.h>
30#include <linux/string.h>
31#include <linux/kernel.h>
32#include <linux/ioport.h>
33#include <linux/mm.h>
34#include <linux/vmalloc.h>
35#include <asm/errno.h>
36#include <linux/irq.h>
37#include <linux/interrupt.h>
38#include <linux/platform_device.h>
39
40#include <asm/io.h>
41#include <asm/hd64465/hd64465.h>
42#include <asm/hd64465/io.h>
43
44#include <pcmcia/cs_types.h>
45#include <pcmcia/cs.h>
46#include <pcmcia/cistpl.h>
47#include <pcmcia/ds.h>
48#include <pcmcia/ss.h>
49
50#define MODNAME "hd64465_ss"
51
52/* #define HD64465_DEBUG 1 */
53
54#if HD64465_DEBUG
55#define DPRINTK(args...) printk(MODNAME ": " args)
56#else
57#define DPRINTK(args...)
58#endif
59
60extern int hd64465_io_debug;
61extern void * p3_ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags);
62extern void p3_iounmap(void *addr);
63
64/*============================================================*/
65
66#define HS_IO_MAP_SIZE (64*1024)
67
68typedef struct hs_socket_t
69{
70 unsigned int number;
71 u_int irq;
72 u_long mem_base;
73 void *io_base;
74 u_long mem_length;
75 u_int ctrl_base;
76 socket_state_t state;
77 pccard_io_map io_maps[MAX_IO_WIN];
78 pccard_mem_map mem_maps[MAX_WIN];
79 struct pcmcia_socket socket;
80} hs_socket_t;
81
82
83
84#define HS_MAX_SOCKETS 2
85static hs_socket_t hs_sockets[HS_MAX_SOCKETS];
86
87#define hs_in(sp, r) inb((sp)->ctrl_base + (r))
88#define hs_out(sp, v, r) outb(v, (sp)->ctrl_base + (r))
89
90
91/* translate a boolean value to a bit in a register */
92#define bool_to_regbit(sp, r, bi, bo) \
93 do { \
94 unsigned short v = hs_in(sp, r); \
95 if (bo) \
96 v |= (bi); \
97 else \
98 v &= ~(bi); \
99 hs_out(sp, v, r); \
100 } while(0)
101
102/* register offsets from HD64465_REG_PCC[01]ISR */
103#define ISR 0x0
104#define GCR 0x2
105#define CSCR 0x4
106#define CSCIER 0x6
107#define SCR 0x8
108
109
110/* Mask and values for CSCIER register */
111#define IER_MASK 0x80
112#define IER_ON 0x3f /* interrupts on */
113#define IER_OFF 0x00 /* interrupts off */
114
115/*============================================================*/
116
117#if HD64465_DEBUG > 10
118
119static void cis_hex_dump(const unsigned char *x, int len)
120{
121 int i;
122
123 for (i=0 ; i<len ; i++)
124 {
125 if (!(i & 0xf))
126 printk("\n%08x", (unsigned)(x + i));
127 printk(" %02x", *(volatile unsigned short*)x);
128 x += 2;
129 }
130 printk("\n");
131}
132
133#endif
134/*============================================================*/
135
136/*
137 * This code helps create the illusion that the IREQ line from
138 * the PC card is mapped to one of the CPU's IRQ lines by the
139 * host bridge hardware (which is how every host bridge *except*
140 * the HD64465 works). In particular, it supports enabling
141 * and disabling the IREQ line by code which knows nothing
142 * about the host bridge (e.g. device drivers, IDE code) using
143 * the request_irq(), free_irq(), probe_irq_on() and probe_irq_off()
144 * functions. Also, it supports sharing the mapped IRQ with
145 * real hardware IRQs from the -IRL0-3 lines.
146 */
147
148#define HS_NUM_MAPPED_IRQS 16 /* Limitation of the PCMCIA code */
149static struct
150{
151 /* index is mapped irq number */
152 hs_socket_t *sock;
153 hw_irq_controller *old_handler;
154} hs_mapped_irq[HS_NUM_MAPPED_IRQS];
155
156static void hs_socket_enable_ireq(hs_socket_t *sp)
157{
158 unsigned short cscier;
159
160 DPRINTK("hs_socket_enable_ireq(sock=%d)\n", sp->number);
161
162 cscier = hs_in(sp, CSCIER);
163 cscier &= ~HD64465_PCCCSCIER_PIREQE_MASK;
164 cscier |= HD64465_PCCCSCIER_PIREQE_LEVEL;
165 hs_out(sp, cscier, CSCIER);
166}
167
168static void hs_socket_disable_ireq(hs_socket_t *sp)
169{
170 unsigned short cscier;
171
172 DPRINTK("hs_socket_disable_ireq(sock=%d)\n", sp->number);
173
174 cscier = hs_in(sp, CSCIER);
175 cscier &= ~HD64465_PCCCSCIER_PIREQE_MASK;
176 hs_out(sp, cscier, CSCIER);
177}
178
179static unsigned int hs_startup_irq(unsigned int irq)
180{
181 hs_socket_enable_ireq(hs_mapped_irq[irq].sock);
182 hs_mapped_irq[irq].old_handler->startup(irq);
183 return 0;
184}
185
186static void hs_shutdown_irq(unsigned int irq)
187{
188 hs_socket_disable_ireq(hs_mapped_irq[irq].sock);
189 hs_mapped_irq[irq].old_handler->shutdown(irq);
190}
191
192static void hs_enable_irq(unsigned int irq)
193{
194 hs_socket_enable_ireq(hs_mapped_irq[irq].sock);
195 hs_mapped_irq[irq].old_handler->enable(irq);
196}
197
198static void hs_disable_irq(unsigned int irq)
199{
200 hs_socket_disable_ireq(hs_mapped_irq[irq].sock);
201 hs_mapped_irq[irq].old_handler->disable(irq);
202}
203
204extern struct hw_interrupt_type no_irq_type;
205
206static void hs_mask_and_ack_irq(unsigned int irq)
207{
208 hs_socket_disable_ireq(hs_mapped_irq[irq].sock);
209 /* ack_none() spuriously complains about an unexpected IRQ */
210 if (hs_mapped_irq[irq].old_handler != &no_irq_type)
211 hs_mapped_irq[irq].old_handler->ack(irq);
212}
213
214static void hs_end_irq(unsigned int irq)
215{
216 hs_socket_enable_ireq(hs_mapped_irq[irq].sock);
217 hs_mapped_irq[irq].old_handler->end(irq);
218}
219
220
221static struct hw_interrupt_type hd64465_ss_irq_type = {
222 .typename = "PCMCIA-IRQ",
223 .startup = hs_startup_irq,
224 .shutdown = hs_shutdown_irq,
225 .enable = hs_enable_irq,
226 .disable = hs_disable_irq,
227 .ack = hs_mask_and_ack_irq,
228 .end = hs_end_irq
229};
230
231/*
232 * This function should only ever be called with interrupts disabled.
233 */
234static void hs_map_irq(hs_socket_t *sp, unsigned int irq)
235{
236 struct irq_desc *desc;
237
238 DPRINTK("hs_map_irq(sock=%d irq=%d)\n", sp->number, irq);
239
240 if (irq >= HS_NUM_MAPPED_IRQS)
241 return;
242
243 desc = irq_to_desc(irq);
244 hs_mapped_irq[irq].sock = sp;
245 /* insert ourselves as the irq controller */
246 hs_mapped_irq[irq].old_handler = desc->chip;
247 desc->chip = &hd64465_ss_irq_type;
248}
249
250
251/*
252 * This function should only ever be called with interrupts disabled.
253 */
254static void hs_unmap_irq(hs_socket_t *sp, unsigned int irq)
255{
256 struct irq_desc *desc;
257
258 DPRINTK("hs_unmap_irq(sock=%d irq=%d)\n", sp->number, irq);
259
260 if (irq >= HS_NUM_MAPPED_IRQS)
261 return;
262
263 desc = irq_to_desc(irq);
264 /* restore the original irq controller */
265 desc->chip = hs_mapped_irq[irq].old_handler;
266}
267
268/*============================================================*/
269
270
271/*
272 * Set Vpp and Vcc (in tenths of a Volt). Does not
273 * support the hi-Z state.
274 *
275 * Note, this assumes the board uses a TPS2206 chip to control
276 * the Vcc and Vpp voltages to the hs_sockets. If your board
277 * uses the MIC2563 (also supported by the HD64465) then you
278 * will have to modify this function.
279 */
280 /* 0V 3.3V 5.5V */
281static const u_char hs_tps2206_avcc[3] = { 0x00, 0x04, 0x08 };
282static const u_char hs_tps2206_bvcc[3] = { 0x00, 0x80, 0x40 };
283
284static int hs_set_voltages(hs_socket_t *sp, int Vcc, int Vpp)
285{
286 u_int psr;
287 u_int vcci = 0;
288 u_int sock = sp->number;
289
290 DPRINTK("hs_set_voltage(%d, %d, %d)\n", sock, Vcc, Vpp);
291
292 switch (Vcc)
293 {
294 case 0: vcci = 0; break;
295 case 33: vcci = 1; break;
296 case 50: vcci = 2; break;
297 default: return 0;
298 }
299
300 /* Note: Vpp = 120 not supported -- Greg Banks */
301 if (Vpp != 0 && Vpp != Vcc)
302 return 0;
303
304 /* The PSR register holds 8 of the 9 bits which control
305 * the TPS2206 via its serial interface.
306 */
307 psr = inw(HD64465_REG_PCCPSR);
308 switch (sock)
309 {
310 case 0:
311 psr &= 0x0f;
312 psr |= hs_tps2206_avcc[vcci];
313 psr |= (Vpp == 0 ? 0x00 : 0x02);
314 break;
315 case 1:
316 psr &= 0xf0;
317 psr |= hs_tps2206_bvcc[vcci];
318 psr |= (Vpp == 0 ? 0x00 : 0x20);
319 break;
320 };
321 outw(psr, HD64465_REG_PCCPSR);
322
323 return 1;
324}
325
326
327/*============================================================*/
328
329/*
330 * Drive the RESET line to the card.
331 */
332static void hs_reset_socket(hs_socket_t *sp, int on)
333{
334 unsigned short v;
335
336 v = hs_in(sp, GCR);
337 if (on)
338 v |= HD64465_PCCGCR_PCCR;
339 else
340 v &= ~HD64465_PCCGCR_PCCR;
341 hs_out(sp, v, GCR);
342}
343
344/*============================================================*/
345
346static int hs_init(struct pcmcia_socket *s)
347{
348 hs_socket_t *sp = container_of(s, struct hs_socket_t, socket);
349
350 DPRINTK("hs_init(%d)\n", sp->number);
351
352 return 0;
353}
354
355/*============================================================*/
356
357
358static int hs_get_status(struct pcmcia_socket *s, u_int *value)
359{
360 hs_socket_t *sp = container_of(s, struct hs_socket_t, socket);
361 unsigned int isr;
362 u_int status = 0;
363
364
365 isr = hs_in(sp, ISR);
366
367 /* Card is seated and powered when *both* CD pins are low */
368 if ((isr & HD64465_PCCISR_PCD_MASK) == 0)
369 {
370 status |= SS_DETECT; /* card present */
371
372 switch (isr & HD64465_PCCISR_PBVD_MASK)
373 {
374 case HD64465_PCCISR_PBVD_BATGOOD:
375 break;
376 case HD64465_PCCISR_PBVD_BATWARN:
377 status |= SS_BATWARN;
378 break;
379 default:
380 status |= SS_BATDEAD;
381 break;
382 }
383
384 if (isr & HD64465_PCCISR_PREADY)
385 status |= SS_READY;
386
387 if (isr & HD64465_PCCISR_PMWP)
388 status |= SS_WRPROT;
389
390 /* Voltage Select pins interpreted as per Table 4-5 of the std.
391 * Assuming we have the TPS2206, the socket is a "Low Voltage
392 * key, 3.3V and 5V available, no X.XV available".
393 */
394 switch (isr & (HD64465_PCCISR_PVS2|HD64465_PCCISR_PVS1))
395 {
396 case HD64465_PCCISR_PVS1:
397 printk(KERN_NOTICE MODNAME ": cannot handle X.XV card, ignored\n");
398 status = 0;
399 break;
400 case 0:
401 case HD64465_PCCISR_PVS2:
402 /* 3.3V */
403 status |= SS_3VCARD;
404 break;
405 case HD64465_PCCISR_PVS2|HD64465_PCCISR_PVS1:
406 /* 5V */
407 break;
408 }
409
410 /* TODO: SS_POWERON */
411 /* TODO: SS_STSCHG */
412 }
413
414 DPRINTK("hs_get_status(%d) = %x\n", sock, status);
415
416 *value = status;
417 return 0;
418}
419
420/*============================================================*/
421
422static int hs_set_socket(struct pcmcia_socket *s, socket_state_t *state)
423{
424 hs_socket_t *sp = container_of(s, struct hs_socket_t, socket);
425 u_long flags;
426 u_int changed;
427 unsigned short cscier;
428
429 DPRINTK("hs_set_socket(sock=%d, flags=%x, csc_mask=%x, Vcc=%d, Vpp=%d, io_irq=%d)\n",
430 sock, state->flags, state->csc_mask, state->Vcc, state->Vpp, state->io_irq);
431
432 local_irq_save(flags); /* Don't want interrupts happening here */
433
434 if (state->Vpp != sp->state.Vpp ||
435 state->Vcc != sp->state.Vcc) {
436 if (!hs_set_voltages(sp, state->Vcc, state->Vpp)) {
437 local_irq_restore(flags);
438 return -EINVAL;
439 }
440 }
441
442/* hd64465_io_debug = 1; */
443 /*
444 * Handle changes in the Card Status Change mask,
445 * by propagating to the CSCR register
446 */
447 changed = sp->state.csc_mask ^ state->csc_mask;
448 cscier = hs_in(sp, CSCIER);
449
450 if (changed & SS_DETECT) {
451 if (state->csc_mask & SS_DETECT)
452 cscier |= HD64465_PCCCSCIER_PCDE;
453 else
454 cscier &= ~HD64465_PCCCSCIER_PCDE;
455 }
456
457 if (changed & SS_READY) {
458 if (state->csc_mask & SS_READY)
459 cscier |= HD64465_PCCCSCIER_PRE;
460 else
461 cscier &= ~HD64465_PCCCSCIER_PRE;
462 }
463
464 if (changed & SS_BATDEAD) {
465 if (state->csc_mask & SS_BATDEAD)
466 cscier |= HD64465_PCCCSCIER_PBDE;
467 else
468 cscier &= ~HD64465_PCCCSCIER_PBDE;
469 }
470
471 if (changed & SS_BATWARN) {
472 if (state->csc_mask & SS_BATWARN)
473 cscier |= HD64465_PCCCSCIER_PBWE;
474 else
475 cscier &= ~HD64465_PCCCSCIER_PBWE;
476 }
477
478 if (changed & SS_STSCHG) {
479 if (state->csc_mask & SS_STSCHG)
480 cscier |= HD64465_PCCCSCIER_PSCE;
481 else
482 cscier &= ~HD64465_PCCCSCIER_PSCE;
483 }
484
485 hs_out(sp, cscier, CSCIER);
486
487 if (sp->state.io_irq && !state->io_irq)
488 hs_unmap_irq(sp, sp->state.io_irq);
489 else if (!sp->state.io_irq && state->io_irq)
490 hs_map_irq(sp, state->io_irq);
491
492
493 /*
494 * Handle changes in the flags field,
495 * by propagating to config registers.
496 */
497 changed = sp->state.flags ^ state->flags;
498
499 if (changed & SS_IOCARD) {
500 DPRINTK("card type: %s\n",
501 (state->flags & SS_IOCARD ? "i/o" : "memory" ));
502 bool_to_regbit(sp, GCR, HD64465_PCCGCR_PCCT,
503 state->flags & SS_IOCARD);
504 }
505
506 if (changed & SS_RESET) {
507 DPRINTK("%s reset card\n",
508 (state->flags & SS_RESET ? "start" : "stop"));
509 bool_to_regbit(sp, GCR, HD64465_PCCGCR_PCCR,
510 state->flags & SS_RESET);
511 }
512
513 if (changed & SS_OUTPUT_ENA) {
514 DPRINTK("%sabling card output\n",
515 (state->flags & SS_OUTPUT_ENA ? "en" : "dis"));
516 bool_to_regbit(sp, GCR, HD64465_PCCGCR_PDRV,
517 state->flags & SS_OUTPUT_ENA);
518 }
519
520 /* TODO: SS_SPKR_ENA */
521
522/* hd64465_io_debug = 0; */
523 sp->state = *state;
524
525 local_irq_restore(flags);
526
527#if HD64465_DEBUG > 10
528 if (state->flags & SS_OUTPUT_ENA)
529 cis_hex_dump((const unsigned char*)sp->mem_base, 0x100);
530#endif
531 return 0;
532}
533
534/*============================================================*/
535
536static int hs_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
537{
538 hs_socket_t *sp = container_of(s, struct hs_socket_t, socket);
539 int map = io->map;
540 int sock = sp->number;
541 struct pccard_io_map *sio;
542 pgprot_t prot;
543
544 DPRINTK("hs_set_io_map(sock=%d, map=%d, flags=0x%x, speed=%dns, start=%#lx, stop=%#lx)\n",
545 sock, map, io->flags, io->speed, io->start, io->stop);
546 if (map >= MAX_IO_WIN)
547 return -EINVAL;
548 sio = &sp->io_maps[map];
549
550 /* check for null changes */
551 if (io->flags == sio->flags &&
552 io->start == sio->start &&
553 io->stop == sio->stop)
554 return 0;
555
556 if (io->flags & MAP_AUTOSZ)
557 prot = PAGE_KERNEL_PCC(sock, _PAGE_PCC_IODYN);
558 else if (io->flags & MAP_16BIT)
559 prot = PAGE_KERNEL_PCC(sock, _PAGE_PCC_IO16);
560 else
561 prot = PAGE_KERNEL_PCC(sock, _PAGE_PCC_IO8);
562
563 /* TODO: handle MAP_USE_WAIT */
564 if (io->flags & MAP_USE_WAIT)
565 printk(KERN_INFO MODNAME ": MAP_USE_WAIT unimplemented\n");
566 /* TODO: handle MAP_PREFETCH */
567 if (io->flags & MAP_PREFETCH)
568 printk(KERN_INFO MODNAME ": MAP_PREFETCH unimplemented\n");
569 /* TODO: handle MAP_WRPROT */
570 if (io->flags & MAP_WRPROT)
571 printk(KERN_INFO MODNAME ": MAP_WRPROT unimplemented\n");
572 /* TODO: handle MAP_0WS */
573 if (io->flags & MAP_0WS)
574 printk(KERN_INFO MODNAME ": MAP_0WS unimplemented\n");
575
576 if (io->flags & MAP_ACTIVE) {
577 unsigned long pstart, psize, paddrbase;
578
579 paddrbase = virt_to_phys((void*)(sp->mem_base + 2 * HD64465_PCC_WINDOW));
580 pstart = io->start & PAGE_MASK;
581 psize = ((io->stop + PAGE_SIZE) & PAGE_MASK) - pstart;
582
583 /*
584 * Change PTEs in only that portion of the mapping requested
585 * by the caller. This means that most of the time, most of
586 * the PTEs in the io_vma will be unmapped and only the bottom
587 * page will be mapped. But the code allows for weird cards
588 * that might want IO ports > 4K.
589 */
590 sp->io_base = p3_ioremap(paddrbase + pstart, psize, pgprot_val(prot));
591
592 /*
593 * Change the mapping used by inb() outb() etc
594 */
595 hd64465_port_map(io->start,
596 io->stop - io->start + 1,
597 (unsigned long)sp->io_base + io->start, 0);
598 } else {
599 hd64465_port_unmap(sio->start, sio->stop - sio->start + 1);
600 p3_iounmap(sp->io_base);
601 }
602
603 *sio = *io;
604 return 0;
605}
606
607/*============================================================*/
608
609static int hs_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem)
610{
611 hs_socket_t *sp = container_of(s, struct hs_socket_t, socket);
612 struct pccard_mem_map *smem;
613 int map = mem->map;
614 unsigned long paddr;
615
616#if 0
617 DPRINTK("hs_set_mem_map(sock=%d, map=%d, flags=0x%x, card_start=0x%08x)\n",
618 sock, map, mem->flags, mem->card_start);
619#endif
620
621 if (map >= MAX_WIN)
622 return -EINVAL;
623 smem = &sp->mem_maps[map];
624
625 paddr = sp->mem_base; /* base of Attribute mapping */
626 if (!(mem->flags & MAP_ATTRIB))
627 paddr += HD64465_PCC_WINDOW; /* base of Common mapping */
628 paddr += mem->card_start;
629
630 /* Because we specified SS_CAP_STATIC_MAP, we are obliged
631 * at this time to report the system address corresponding
632 * to the card address requested. This is how Socket Services
633 * queries our fixed mapping. I wish this fact had been
634 * documented - Greg Banks.
635 */
636 mem->static_start = paddr;
637
638 *smem = *mem;
639
640 return 0;
641}
642
643/* TODO: do we need to use the MMU to access Common memory ??? */
644
645/*============================================================*/
646
647/*
648 * This function is registered with the HD64465 glue code to do a
649 * secondary demux step on the PCMCIA interrupts. It handles
650 * mapping the IREQ request from the card to a standard Linux
651 * IRQ, as requested by SocketServices.
652 */
653static int hs_irq_demux(int irq, void *dev)
654{
655 hs_socket_t *sp = dev;
656 u_int cscr;
657
658 DPRINTK("hs_irq_demux(irq=%d)\n", irq);
659
660 if (sp->state.io_irq &&
661 (cscr = hs_in(sp, CSCR)) & HD64465_PCCCSCR_PIREQ) {
662 cscr &= ~HD64465_PCCCSCR_PIREQ;
663 hs_out(sp, cscr, CSCR);
664 return sp->state.io_irq;
665 }
666
667 return irq;
668}
669
670/*============================================================*/
671
672/*
673 * Interrupt handling routine.
674 */
675
676static irqreturn_t hs_interrupt(int irq, void *dev)
677{
678 hs_socket_t *sp = dev;
679 u_int events = 0;
680 u_int cscr;
681
682 cscr = hs_in(sp, CSCR);
683
684 DPRINTK("hs_interrupt, cscr=%04x\n", cscr);
685
686 /* check for bus-related changes to be reported to Socket Services */
687 if (cscr & HD64465_PCCCSCR_PCDC) {
688 /* double-check for a 16-bit card, as we don't support CardBus */
689 if ((hs_in(sp, ISR) & HD64465_PCCISR_PCD_MASK) != 0) {
690 printk(KERN_NOTICE MODNAME
691 ": socket %d, card not a supported card type or not inserted correctly\n",
692 sp->number);
693 /* Don't do the rest unless a card is present */
694 cscr &= ~(HD64465_PCCCSCR_PCDC|
695 HD64465_PCCCSCR_PRC|
696 HD64465_PCCCSCR_PBW|
697 HD64465_PCCCSCR_PBD|
698 HD64465_PCCCSCR_PSC);
699 } else {
700 cscr &= ~HD64465_PCCCSCR_PCDC;
701 events |= SS_DETECT; /* card insertion or removal */
702 }
703 }
704 if (cscr & HD64465_PCCCSCR_PRC) {
705 cscr &= ~HD64465_PCCCSCR_PRC;
706 events |= SS_READY; /* ready signal changed */
707 }
708 if (cscr & HD64465_PCCCSCR_PBW) {
709 cscr &= ~HD64465_PCCCSCR_PSC;
710 events |= SS_BATWARN; /* battery warning */
711 }
712 if (cscr & HD64465_PCCCSCR_PBD) {
713 cscr &= ~HD64465_PCCCSCR_PSC;
714 events |= SS_BATDEAD; /* battery dead */
715 }
716 if (cscr & HD64465_PCCCSCR_PSC) {
717 cscr &= ~HD64465_PCCCSCR_PSC;
718 events |= SS_STSCHG; /* STSCHG (status changed) signal */
719 }
720
721 if (cscr & HD64465_PCCCSCR_PIREQ) {
722 cscr &= ~HD64465_PCCCSCR_PIREQ;
723
724 /* This should have been dealt with during irq demux */
725 printk(KERN_NOTICE MODNAME ": unexpected IREQ from card\n");
726 }
727
728 hs_out(sp, cscr, CSCR);
729
730 if (events)
731 pcmcia_parse_events(&sp->socket, events);
732
733 return IRQ_HANDLED;
734}
735
736/*============================================================*/
737
738static struct pccard_operations hs_operations = {
739 .init = hs_init,
740 .get_status = hs_get_status,
741 .set_socket = hs_set_socket,
742 .set_io_map = hs_set_io_map,
743 .set_mem_map = hs_set_mem_map,
744};
745
746static int hs_init_socket(hs_socket_t *sp, int irq, unsigned long mem_base,
747 unsigned int ctrl_base)
748{
749 unsigned short v;
750 int i, err;
751
752 memset(sp, 0, sizeof(*sp));
753 sp->irq = irq;
754 sp->mem_base = mem_base;
755 sp->mem_length = 4*HD64465_PCC_WINDOW; /* 16MB */
756 sp->ctrl_base = ctrl_base;
757
758 for (i=0 ; i<MAX_IO_WIN ; i++)
759 sp->io_maps[i].map = i;
760 for (i=0 ; i<MAX_WIN ; i++)
761 sp->mem_maps[i].map = i;
762
763 hd64465_register_irq_demux(sp->irq, hs_irq_demux, sp);
764
765 if ((err = request_irq(sp->irq, hs_interrupt, IRQF_DISABLED, MODNAME, sp)) < 0)
766 return err;
767 if (request_mem_region(sp->mem_base, sp->mem_length, MODNAME) == 0) {
768 sp->mem_base = 0;
769 return -ENOMEM;
770 }
771
772
773 /* According to section 3.2 of the PCMCIA standard, low-voltage
774 * capable cards must implement cold insertion, i.e. Vpp and
775 * Vcc set to 0 before card is inserted.
776 */
777 /*hs_set_voltages(sp, 0, 0);*/
778
779 /* hi-Z the outputs to the card and set 16MB map mode */
780 v = hs_in(sp, GCR);
781 v &= ~HD64465_PCCGCR_PCCT; /* memory-only card */
782 hs_out(sp, v, GCR);
783
784 v = hs_in(sp, GCR);
785 v |= HD64465_PCCGCR_PDRV; /* enable outputs to card */
786 hs_out(sp, v, GCR);
787
788 v = hs_in(sp, GCR);
789 v |= HD64465_PCCGCR_PMMOD; /* 16MB mapping mode */
790 hs_out(sp, v, GCR);
791
792 v = hs_in(sp, GCR);
793 /* lowest 16MB of Common */
794 v &= ~(HD64465_PCCGCR_PPA25|HD64465_PCCGCR_PPA24);
795 hs_out(sp, v, GCR);
796
797 hs_reset_socket(sp, 1);
798
799 printk(KERN_INFO "HD64465 PCMCIA bridge socket %d at 0x%08lx irq %d\n",
800 i, sp->mem_base, sp->irq);
801
802 return 0;
803}
804
805static void hs_exit_socket(hs_socket_t *sp)
806{
807 unsigned short cscier, gcr;
808 unsigned long flags;
809
810 local_irq_save(flags);
811
812 /* turn off interrupts in hardware */
813 cscier = hs_in(sp, CSCIER);
814 cscier = (cscier & IER_MASK) | IER_OFF;
815 hs_out(sp, cscier, CSCIER);
816
817 /* hi-Z the outputs to the card */
818 gcr = hs_in(sp, GCR);
819 gcr &= HD64465_PCCGCR_PDRV;
820 hs_out(sp, gcr, GCR);
821
822 /* power the card down */
823 hs_set_voltages(sp, 0, 0);
824
825 if (sp->mem_base != 0)
826 release_mem_region(sp->mem_base, sp->mem_length);
827 if (sp->irq != 0) {
828 free_irq(sp->irq, hs_interrupt);
829 hd64465_unregister_irq_demux(sp->irq);
830 }
831
832 local_irq_restore(flags);
833}
834
835static struct device_driver hd64465_driver = {
836 .name = "hd64465-pcmcia",
837 .bus = &platform_bus_type,
838 .suspend = pcmcia_socket_dev_suspend,
839 .resume = pcmcia_socket_dev_resume,
840};
841
842static struct platform_device hd64465_device = {
843 .name = "hd64465-pcmcia",
844 .id = 0,
845};
846
847static int __init init_hs(void)
848{
849 int i;
850 unsigned short v;
851
852/* hd64465_io_debug = 1; */
853 if (driver_register(&hd64465_driver))
854 return -EINVAL;
855
856 /* Wake both sockets out of STANDBY mode */
857 /* TODO: wait 15ms */
858 v = inw(HD64465_REG_SMSCR);
859 v &= ~(HD64465_SMSCR_PC0ST|HD64465_SMSCR_PC1ST);
860 outw(v, HD64465_REG_SMSCR);
861
862 /* keep power controller out of shutdown mode */
863 v = inb(HD64465_REG_PCC0SCR);
864 v |= HD64465_PCCSCR_SHDN;
865 outb(v, HD64465_REG_PCC0SCR);
866
867 /* use serial (TPS2206) power controller */
868 v = inb(HD64465_REG_PCC0CSCR);
869 v |= HD64465_PCCCSCR_PSWSEL;
870 outb(v, HD64465_REG_PCC0CSCR);
871
872 /*
873 * Setup hs_sockets[] structures and request system resources.
874 * TODO: on memory allocation failure, power down the socket
875 * before quitting.
876 */
877 for (i=0; i<HS_MAX_SOCKETS; i++) {
878 hs_set_voltages(&hs_sockets[i], 0, 0);
879
880 hs_sockets[i].socket.features |= SS_CAP_PCCARD | SS_CAP_STATIC_MAP; /* mappings are fixed in host memory */
881 hs_sockets[i].socket.resource_ops = &pccard_static_ops;
882 hs_sockets[i].socket.irq_mask = 0xffde;/*0xffff*/ /* IRQs mapped in s/w so can do any, really */
883 hs_sockets[i].socket.map_size = HD64465_PCC_WINDOW; /* 16MB fixed window size */
884
885 hs_sockets[i].socket.owner = THIS_MODULE;
886 hs_sockets[i].socket.ss_entry = &hs_operations;
887 }
888
889 i = hs_init_socket(&hs_sockets[0],
890 HD64465_IRQ_PCMCIA0,
891 HD64465_PCC0_BASE,
892 HD64465_REG_PCC0ISR);
893 if (i < 0) {
894 unregister_driver(&hd64465_driver);
895 return i;
896 }
897 i = hs_init_socket(&hs_sockets[1],
898 HD64465_IRQ_PCMCIA1,
899 HD64465_PCC1_BASE,
900 HD64465_REG_PCC1ISR);
901 if (i < 0) {
902 unregister_driver(&hd64465_driver);
903 return i;
904 }
905
906/* hd64465_io_debug = 0; */
907
908 platform_device_register(&hd64465_device);
909
910 for (i=0; i<HS_MAX_SOCKETS; i++) {
911 unsigned int ret;
912 hs_sockets[i].socket.dev.parent = &hd64465_device.dev;
913 hs_sockets[i].number = i;
914 ret = pcmcia_register_socket(&hs_sockets[i].socket);
915 if (ret && i)
916 pcmcia_unregister_socket(&hs_sockets[0].socket);
917 }
918
919 return 0;
920}
921
922static void __exit exit_hs(void)
923{
924 int i;
925
926 for (i=0 ; i<HS_MAX_SOCKETS ; i++) {
927 pcmcia_unregister_socket(&hs_sockets[i].socket);
928 hs_exit_socket(&hs_sockets[i]);
929 }
930
931 platform_device_unregister(&hd64465_device);
932 unregister_driver(&hd64465_driver);
933}
934
935module_init(init_hs);
936module_exit(exit_hs);
937
938/*============================================================*/
939/*END*/
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index f0658d2c45b2..5c0f32c7fbf6 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -250,8 +250,7 @@ static inline void h8300_sci_disable(struct uart_port *port)
250} 250}
251#endif 251#endif
252 252
253#if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \ 253#if defined(__H8300H__) || defined(__H8300S__)
254 defined(__H8300H__) || defined(__H8300S__)
255static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag) 254static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
256{ 255{
257 int ch = (port->mapbase - SMR0) >> 3; 256 int ch = (port->mapbase - SMR0) >> 3;
@@ -285,11 +284,6 @@ static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
285#define sci_init_pins_irda NULL 284#define sci_init_pins_irda NULL
286#endif 285#endif
287 286
288#ifdef SCI_ONLY
289#define sci_init_pins_scif NULL
290#endif
291
292#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
293#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 287#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
294static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag) 288static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
295{ 289{
@@ -449,7 +443,6 @@ static inline int scif_rxroom(struct uart_port *port)
449 return sci_in(port, SCFDR) & SCIF_RFDC_MASK; 443 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
450} 444}
451#endif 445#endif
452#endif /* SCIF_ONLY || SCI_AND_SCIF */
453 446
454static inline int sci_txroom(struct uart_port *port) 447static inline int sci_txroom(struct uart_port *port)
455{ 448{
@@ -485,11 +478,9 @@ static void sci_transmit_chars(struct uart_port *port)
485 return; 478 return;
486 } 479 }
487 480
488#ifndef SCI_ONLY
489 if (port->type == PORT_SCIF) 481 if (port->type == PORT_SCIF)
490 count = scif_txroom(port); 482 count = scif_txroom(port);
491 else 483 else
492#endif
493 count = sci_txroom(port); 484 count = sci_txroom(port);
494 485
495 do { 486 do {
@@ -519,12 +510,10 @@ static void sci_transmit_chars(struct uart_port *port)
519 } else { 510 } else {
520 ctrl = sci_in(port, SCSCR); 511 ctrl = sci_in(port, SCSCR);
521 512
522#if !defined(SCI_ONLY)
523 if (port->type == PORT_SCIF) { 513 if (port->type == PORT_SCIF) {
524 sci_in(port, SCxSR); /* Dummy read */ 514 sci_in(port, SCxSR); /* Dummy read */
525 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 515 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
526 } 516 }
527#endif
528 517
529 ctrl |= SCI_CTRL_FLAGS_TIE; 518 ctrl |= SCI_CTRL_FLAGS_TIE;
530 sci_out(port, SCSCR, ctrl); 519 sci_out(port, SCSCR, ctrl);
@@ -547,11 +536,9 @@ static inline void sci_receive_chars(struct uart_port *port)
547 return; 536 return;
548 537
549 while (1) { 538 while (1) {
550#if !defined(SCI_ONLY)
551 if (port->type == PORT_SCIF) 539 if (port->type == PORT_SCIF)
552 count = scif_rxroom(port); 540 count = scif_rxroom(port);
553 else 541 else
554#endif
555 count = sci_rxroom(port); 542 count = sci_rxroom(port);
556 543
557 /* Don't copy more bytes than there is room for in the buffer */ 544 /* Don't copy more bytes than there is room for in the buffer */
@@ -810,26 +797,27 @@ static irqreturn_t sci_br_interrupt(int irq, void *ptr)
810 797
811static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 798static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
812{ 799{
813 unsigned short ssr_status, scr_status; 800 unsigned short ssr_status, scr_status;
814 struct uart_port *port = ptr; 801 struct uart_port *port = ptr;
802 irqreturn_t ret = IRQ_NONE;
815 803
816 ssr_status = sci_in(port,SCxSR); 804 ssr_status = sci_in(port,SCxSR);
817 scr_status = sci_in(port,SCSCR); 805 scr_status = sci_in(port,SCSCR);
818 806
819 /* Tx Interrupt */ 807 /* Tx Interrupt */
820 if ((ssr_status & 0x0020) && (scr_status & 0x0080)) 808 if ((ssr_status & 0x0020) && (scr_status & SCI_CTRL_FLAGS_TIE))
821 sci_tx_interrupt(irq, ptr); 809 ret = sci_tx_interrupt(irq, ptr);
822 /* Rx Interrupt */ 810 /* Rx Interrupt */
823 if ((ssr_status & 0x0002) && (scr_status & 0x0040)) 811 if ((ssr_status & 0x0002) && (scr_status & SCI_CTRL_FLAGS_RIE))
824 sci_rx_interrupt(irq, ptr); 812 ret = sci_rx_interrupt(irq, ptr);
825 /* Error Interrupt */ 813 /* Error Interrupt */
826 if ((ssr_status & 0x0080) && (scr_status & 0x0400)) 814 if ((ssr_status & 0x0080) && (scr_status & SCI_CTRL_FLAGS_REIE))
827 sci_er_interrupt(irq, ptr); 815 ret = sci_er_interrupt(irq, ptr);
828 /* Break Interrupt */ 816 /* Break Interrupt */
829 if ((ssr_status & 0x0010) && (scr_status & 0x0200)) 817 if ((ssr_status & 0x0010) && (scr_status & SCI_CTRL_FLAGS_REIE))
830 sci_br_interrupt(irq, ptr); 818 ret = sci_br_interrupt(irq, ptr);
831 819
832 return IRQ_HANDLED; 820 return ret;
833} 821}
834 822
835#if defined(CONFIG_CPU_FREQ) && defined(CONFIG_HAVE_CLK) 823#if defined(CONFIG_CPU_FREQ) && defined(CONFIG_HAVE_CLK)
@@ -1054,10 +1042,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1054 1042
1055 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 1043 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1056 1044
1057#if !defined(SCI_ONLY)
1058 if (port->type == PORT_SCIF) 1045 if (port->type == PORT_SCIF)
1059 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 1046 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1060#endif
1061 1047
1062 smr_val = sci_in(port, SCSMR) & 3; 1048 smr_val = sci_in(port, SCSMR) & 3;
1063 if ((termios->c_cflag & CSIZE) == CS7) 1049 if ((termios->c_cflag & CSIZE) == CS7)
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index 7cd28b226800..6163a45f968f 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -16,7 +16,6 @@
16# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ 16# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ 17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 18# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
19# define SCI_AND_SCIF
20#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 19#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
21# define SCIF0 0xA4400000 20# define SCIF0 0xA4400000
22# define SCIF2 0xA4410000 21# define SCIF2 0xA4410000
@@ -30,17 +29,15 @@
30 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output 29 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
31 */ 30 */
32# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 31# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
33# define SCIF_ONLY
34#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 32#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
35 defined(CONFIG_CPU_SUBTYPE_SH7721) 33 defined(CONFIG_CPU_SUBTYPE_SH7721)
36# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 34# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
37# define SCIF_ONLY
38#define SCIF_ORER 0x0200 /* overrun error bit */ 35#define SCIF_ORER 0x0200 /* overrun error bit */
39#elif defined(CONFIG_SH_RTS7751R2D) 36#elif defined(CONFIG_SH_RTS7751R2D)
37# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
40# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 38# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
41# define SCIF_ORER 0x0001 /* overrun error bit */ 39# define SCIF_ORER 0x0001 /* overrun error bit */
42# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 40# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
43# define SCIF_ONLY
44#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 41#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
45 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 42 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
46 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 43 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
@@ -53,28 +50,24 @@
53# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ 50# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
54 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 51 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
55 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) 52 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
56# define SCI_AND_SCIF
57#elif defined(CONFIG_CPU_SUBTYPE_SH7760) 53#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
58# define SCSPTR0 0xfe600024 /* 16 bit SCIF */ 54# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
59# define SCSPTR1 0xfe610024 /* 16 bit SCIF */ 55# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
60# define SCSPTR2 0xfe620024 /* 16 bit SCIF */ 56# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
61# define SCIF_ORER 0x0001 /* overrun error bit */ 57# define SCIF_ORER 0x0001 /* overrun error bit */
62# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 58# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
63# define SCIF_ONLY
64#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 59#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
65# define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 60# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
66# define SCIF_ORER 0x0001 /* overrun error bit */ 61# define SCIF_ORER 0x0001 /* overrun error bit */
67# define PACR 0xa4050100 62# define PACR 0xa4050100
68# define PBCR 0xa4050102 63# define PBCR 0xa4050102
69# define SCSCR_INIT(port) 0x3B 64# define SCSCR_INIT(port) 0x3B
70# define SCIF_ONLY
71#elif defined(CONFIG_CPU_SUBTYPE_SH7343) 65#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
72# define SCSPTR0 0xffe00010 /* 16 bit SCIF */ 66# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
73# define SCSPTR1 0xffe10010 /* 16 bit SCIF */ 67# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
74# define SCSPTR2 0xffe20010 /* 16 bit SCIF */ 68# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
75# define SCSPTR3 0xffe30010 /* 16 bit SCIF */ 69# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
76# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ 70# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
77# define SCIF_ONLY
78#elif defined(CONFIG_CPU_SUBTYPE_SH7722) 71#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
79# define PADR 0xA4050120 72# define PADR 0xA4050120
80# define PSDR 0xA405013e 73# define PSDR 0xA405013e
@@ -82,7 +75,6 @@
82# define PSCR 0xA405011E 75# define PSCR 0xA405011E
83# define SCIF_ORER 0x0001 /* overrun error bit */ 76# define SCIF_ORER 0x0001 /* overrun error bit */
84# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 77# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
85# define SCIF_ONLY
86#elif defined(CONFIG_CPU_SUBTYPE_SH7366) 78#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
87# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 79# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
88# define SCSPTR0 SCPDR0 80# define SCSPTR0 SCPDR0
@@ -97,12 +89,10 @@
97# define SCSPTR5 0xa4050128 89# define SCSPTR5 0xa4050128
98# define SCIF_ORER 0x0001 /* overrun error bit */ 90# define SCIF_ORER 0x0001 /* overrun error bit */
99# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 91# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
100# define SCIF_ONLY
101#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) 92#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
102# define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 93# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
103# define SCIF_ORER 0x0001 /* overrun error bit */ 94# define SCIF_ORER 0x0001 /* overrun error bit */
104# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 95# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
105# define SCIF_ONLY
106#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) 96#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
107# define SCIF_BASE_ADDR 0x01030000 97# define SCIF_BASE_ADDR 0x01030000
108# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR 98# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
@@ -111,14 +101,11 @@
111# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ 101# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
112# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ 102# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
113# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ 103# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
114# define SCIF_ONLY
115#elif defined(CONFIG_H83007) || defined(CONFIG_H83068) 104#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
116# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 105# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
117# define SCI_ONLY
118# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 106# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
119#elif defined(CONFIG_H8S2678) 107#elif defined(CONFIG_H8S2678)
120# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 108# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
121# define SCI_ONLY
122# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 109# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
123#elif defined(CONFIG_CPU_SUBTYPE_SH7763) 110#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
124# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 111# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
@@ -126,20 +113,17 @@
126# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ 113# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
127# define SCIF_ORER 0x0001 /* overrun error bit */ 114# define SCIF_ORER 0x0001 /* overrun error bit */
128# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 115# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
129# define SCIF_ONLY
130#elif defined(CONFIG_CPU_SUBTYPE_SH7770) 116#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
131# define SCSPTR0 0xff923020 /* 16 bit SCIF */ 117# define SCSPTR0 0xff923020 /* 16 bit SCIF */
132# define SCSPTR1 0xff924020 /* 16 bit SCIF */ 118# define SCSPTR1 0xff924020 /* 16 bit SCIF */
133# define SCSPTR2 0xff925020 /* 16 bit SCIF */ 119# define SCSPTR2 0xff925020 /* 16 bit SCIF */
134# define SCIF_ORER 0x0001 /* overrun error bit */ 120# define SCIF_ORER 0x0001 /* overrun error bit */
135# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ 121# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
136# define SCIF_ONLY
137#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 122#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
138# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 123# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
139# define SCSPTR1 0xffe10024 /* 16 bit SCIF */ 124# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
140# define SCIF_ORER 0x0001 /* Overrun error bit */ 125# define SCIF_ORER 0x0001 /* Overrun error bit */
141# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 126# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
142# define SCIF_ONLY
143#elif defined(CONFIG_CPU_SUBTYPE_SH7785) 127#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
144# define SCSPTR0 0xffea0024 /* 16 bit SCIF */ 128# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
145# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ 129# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
@@ -149,7 +133,6 @@
149# define SCSPTR5 0xffef0024 /* 16 bit SCIF */ 133# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
150# define SCIF_OPER 0x0001 /* Overrun error bit */ 134# define SCIF_OPER 0x0001 /* Overrun error bit */
151# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 135# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
152# define SCIF_ONLY
153#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ 136#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
154 defined(CONFIG_CPU_SUBTYPE_SH7206) || \ 137 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
155 defined(CONFIG_CPU_SUBTYPE_SH7263) 138 defined(CONFIG_CPU_SUBTYPE_SH7263)
@@ -158,14 +141,12 @@
158# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ 141# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
159# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ 142# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
160# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 143# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
161# define SCIF_ONLY
162#elif defined(CONFIG_CPU_SUBTYPE_SH7619) 144#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
163# define SCSPTR0 0xf8400020 /* 16 bit SCIF */ 145# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
164# define SCSPTR1 0xf8410020 /* 16 bit SCIF */ 146# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
165# define SCSPTR2 0xf8420020 /* 16 bit SCIF */ 147# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
166# define SCIF_ORER 0x0001 /* overrun error bit */ 148# define SCIF_ORER 0x0001 /* overrun error bit */
167# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 149# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
168# define SCIF_ONLY
169#elif defined(CONFIG_CPU_SUBTYPE_SHX3) 150#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
170# define SCSPTR0 0xffc30020 /* 16 bit SCIF */ 151# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
171# define SCSPTR1 0xffc40020 /* 16 bit SCIF */ 152# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
@@ -173,7 +154,6 @@
173# define SCSPTR3 0xffc60020 /* 16 bit SCIF */ 154# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
174# define SCIF_ORER 0x0001 /* Overrun error bit */ 155# define SCIF_ORER 0x0001 /* Overrun error bit */
175# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 156# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
176# define SCIF_ONLY
177#else 157#else
178# error CPU subtype not defined 158# error CPU subtype not defined
179#endif 159#endif
@@ -186,6 +166,7 @@
186#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 166#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
187 defined(CONFIG_CPU_SUBTYPE_SH7091) || \ 167 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
188 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 168 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
169 defined(CONFIG_CPU_SUBTYPE_SH7722) || \
189 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 170 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
190 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 171 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
191 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ 172 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
@@ -244,55 +225,28 @@
244# define SCIF_TXROOM_MAX 16 225# define SCIF_TXROOM_MAX 16
245#endif 226#endif
246 227
247#if defined(SCI_ONLY) 228#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
248# define SCxSR_TEND(port) SCI_TEND 229#define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
249# define SCxSR_ERRORS(port) SCI_ERRORS 230#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
250# define SCxSR_RDxF(port) SCI_RDRF 231#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
251# define SCxSR_TDxE(port) SCI_TDRE 232#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
252# define SCxSR_ORER(port) SCI_ORER 233#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
253# define SCxSR_FER(port) SCI_FER 234#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
254# define SCxSR_PER(port) SCI_PER 235
255# define SCxSR_BRK(port) 0x00
256# define SCxSR_RDxF_CLEAR(port) 0xbc
257# define SCxSR_ERROR_CLEAR(port) 0xc4
258# define SCxSR_TDxE_CLEAR(port) 0x78
259# define SCxSR_BREAK_CLEAR(port) 0xc4
260#elif defined(SCIF_ONLY)
261# define SCxSR_TEND(port) SCIF_TEND
262# define SCxSR_ERRORS(port) SCIF_ERRORS
263# define SCxSR_RDxF(port) SCIF_RDF
264# define SCxSR_TDxE(port) SCIF_TDFE
265#if defined(CONFIG_CPU_SUBTYPE_SH7705) 236#if defined(CONFIG_CPU_SUBTYPE_SH7705)
266# define SCxSR_ORER(port) SCIF_ORER 237# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
267#else 238#else
268# define SCxSR_ORER(port) 0x0000 239# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
269#endif 240#endif
270# define SCxSR_FER(port) SCIF_FER 241
271# define SCxSR_PER(port) SCIF_PER
272# define SCxSR_BRK(port) SCIF_BRK
273#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 242#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
274 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 243 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
275 defined(CONFIG_CPU_SUBTYPE_SH7721) 244 defined(CONFIG_CPU_SUBTYPE_SH7721)
276# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc) 245# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
277# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73) 246# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
278# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf) 247# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
279# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3) 248# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
280#else
281/* SH7705 can also use this, clearing is same between 7705 and 7709 */
282# define SCxSR_RDxF_CLEAR(port) 0x00fc
283# define SCxSR_ERROR_CLEAR(port) 0x0073
284# define SCxSR_TDxE_CLEAR(port) 0x00df
285# define SCxSR_BREAK_CLEAR(port) 0x00e3
286#endif
287#else 249#else
288# define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
289# define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
290# define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
291# define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
292# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
293# define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
294# define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
295# define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
296# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) 250# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
297# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) 251# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
298# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) 252# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
@@ -574,18 +528,20 @@ static inline int sci_rxd_in(struct uart_port *port)
574 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ 528 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
575 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 529 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
576 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 530 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
577 defined(CONFIG_CPU_SUBTYPE_SH7091) || \ 531 defined(CONFIG_CPU_SUBTYPE_SH7091)
578 defined(CONFIG_CPU_SUBTYPE_SH4_202)
579static inline int sci_rxd_in(struct uart_port *port) 532static inline int sci_rxd_in(struct uart_port *port)
580{ 533{
581#ifndef SCIF_ONLY
582 if (port->mapbase == 0xffe00000) 534 if (port->mapbase == 0xffe00000)
583 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ 535 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
584#endif
585#ifndef SCI_ONLY
586 if (port->mapbase == 0xffe80000) 536 if (port->mapbase == 0xffe80000)
587 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ 537 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
588#endif 538 return 1;
539}
540#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
541static inline int sci_rxd_in(struct uart_port *port)
542{
543 if (port->mapbase == 0xffe80000)
544 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
589 return 1; 545 return 1;
590} 546}
591#elif defined(CONFIG_CPU_SUBTYPE_SH7760) 547#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
@@ -651,7 +607,7 @@ static inline int sci_rxd_in(struct uart_port *port)
651#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) 607#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
652static inline int sci_rxd_in(struct uart_port *port) 608static inline int sci_rxd_in(struct uart_port *port)
653{ 609{
654 return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */ 610 return sci_in(port, SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
655} 611}
656#elif defined(__H8300H__) || defined(__H8300S__) 612#elif defined(__H8300H__) || defined(__H8300S__)
657static inline int sci_rxd_in(struct uart_port *port) 613static inline int sci_rxd_in(struct uart_port *port)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-04 13:52:32 -0500