diff options
author | Eric Miao <eric.miao@marvell.com> | 2008-09-08 03:37:50 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-10-07 14:12:56 -0400 |
commit | 52358ba3a89012c54712c24074ceb4b1c669af52 (patch) | |
tree | 856804ad95548a3e1dcf577366308cf0ebcc1369 | |
parent | 87f3dd77974cba1ba0798abd741ede50f56b3eb3 (diff) |
[ARM] pxa: move I2S register and bit definitions into pxa2xx-i2s.c
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r-- | arch/arm/mach-pxa/include/mach/pxa-regs.h | 39 | ||||
-rw-r--r-- | sound/soc/pxa/pxa2xx-i2s.c | 40 |
2 files changed, 41 insertions, 38 deletions
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h index 4cac9269fdf2..98ded450d0fe 100644 --- a/arch/arm/mach-pxa/include/mach/pxa-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h | |||
@@ -269,46 +269,9 @@ | |||
269 | */ | 269 | */ |
270 | 270 | ||
271 | /* | 271 | /* |
272 | * Serial Audio Controller | 272 | * Serial Audio Controller - moved into sound/soc/pxa/pxa2xx-i2s.c |
273 | */ | 273 | */ |
274 | 274 | ||
275 | #define SACR0 __REG(0x40400000) /* Global Control Register */ | ||
276 | #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */ | ||
277 | #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ | ||
278 | #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */ | ||
279 | #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */ | ||
280 | #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */ | ||
281 | #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */ | ||
282 | |||
283 | #define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */ | ||
284 | #define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */ | ||
285 | #define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */ | ||
286 | #define SACR0_EFWR (1 << 4) /* Enable EFWR Function */ | ||
287 | #define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */ | ||
288 | #define SACR0_BCKD (1 << 2) /* Bit Clock Direction */ | ||
289 | #define SACR0_ENB (1 << 0) /* Enable I2S Link */ | ||
290 | #define SACR1_ENLBF (1 << 5) /* Enable Loopback */ | ||
291 | #define SACR1_DRPL (1 << 4) /* Disable Replaying Function */ | ||
292 | #define SACR1_DREC (1 << 3) /* Disable Recording Function */ | ||
293 | #define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */ | ||
294 | |||
295 | #define SASR0_I2SOFF (1 << 7) /* Controller Status */ | ||
296 | #define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */ | ||
297 | #define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */ | ||
298 | #define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */ | ||
299 | #define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */ | ||
300 | #define SASR0_BSY (1 << 2) /* I2S Busy */ | ||
301 | #define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */ | ||
302 | #define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */ | ||
303 | |||
304 | #define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */ | ||
305 | #define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */ | ||
306 | |||
307 | #define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */ | ||
308 | #define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */ | ||
309 | #define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */ | ||
310 | #define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */ | ||
311 | |||
312 | /* | 275 | /* |
313 | * AC97 Controller registers | 276 | * AC97 Controller registers |
314 | */ | 277 | */ |
diff --git a/sound/soc/pxa/pxa2xx-i2s.c b/sound/soc/pxa/pxa2xx-i2s.c index 2dbe612fdddc..ad4c31ddb3d4 100644 --- a/sound/soc/pxa/pxa2xx-i2s.c +++ b/sound/soc/pxa/pxa2xx-i2s.c | |||
@@ -30,6 +30,46 @@ | |||
30 | #include "pxa2xx-pcm.h" | 30 | #include "pxa2xx-pcm.h" |
31 | #include "pxa2xx-i2s.h" | 31 | #include "pxa2xx-i2s.h" |
32 | 32 | ||
33 | /* | ||
34 | * I2S Controller Register and Bit Definitions | ||
35 | */ | ||
36 | #define SACR0 __REG(0x40400000) /* Global Control Register */ | ||
37 | #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */ | ||
38 | #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ | ||
39 | #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */ | ||
40 | #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */ | ||
41 | #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */ | ||
42 | #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */ | ||
43 | |||
44 | #define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */ | ||
45 | #define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */ | ||
46 | #define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */ | ||
47 | #define SACR0_EFWR (1 << 4) /* Enable EFWR Function */ | ||
48 | #define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */ | ||
49 | #define SACR0_BCKD (1 << 2) /* Bit Clock Direction */ | ||
50 | #define SACR0_ENB (1 << 0) /* Enable I2S Link */ | ||
51 | #define SACR1_ENLBF (1 << 5) /* Enable Loopback */ | ||
52 | #define SACR1_DRPL (1 << 4) /* Disable Replaying Function */ | ||
53 | #define SACR1_DREC (1 << 3) /* Disable Recording Function */ | ||
54 | #define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */ | ||
55 | |||
56 | #define SASR0_I2SOFF (1 << 7) /* Controller Status */ | ||
57 | #define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */ | ||
58 | #define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */ | ||
59 | #define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */ | ||
60 | #define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */ | ||
61 | #define SASR0_BSY (1 << 2) /* I2S Busy */ | ||
62 | #define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */ | ||
63 | #define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */ | ||
64 | |||
65 | #define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */ | ||
66 | #define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */ | ||
67 | |||
68 | #define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */ | ||
69 | #define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */ | ||
70 | #define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */ | ||
71 | #define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */ | ||
72 | |||
33 | struct pxa_i2s_port { | 73 | struct pxa_i2s_port { |
34 | u32 sadiv; | 74 | u32 sadiv; |
35 | u32 sacr0; | 75 | u32 sacr0; |