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authorDave Jiang <djiang@mvista.com>2007-05-10 13:03:05 -0400
committerPaul Mackerras <paulus@samba.org>2007-05-17 07:10:16 -0400
commit50cf67075ba071e0532ccc657ad64cfbb2da3c7a (patch)
treee729f62706c1b3846549adf43b500c42f1aa004f
parent1c2de47cd47daa033251dbb4a3643e7e87a681b0 (diff)
[POWERPC] 85xx: Add device nodes for error reporting devices used by EDAC
Adding memory-controller and l2-cache-controller entries to be used by EDAC as of_devices for MPC8540 ADS, MPC8548 CDS, and MPC8560 ADS. Also fixed up the size of the PCI node on MPC8560 ADS. Signed-off-by: Dave Jiang <djiang@mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts16
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts16
-rw-r--r--arch/powerpc/boot/dts/mpc8560ads.dts18
3 files changed, 49 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index f261d647ac85..d91e81c009f5 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -48,6 +48,22 @@
48 reg = <e0000000 00100000>; // CCSRBAR 1M 48 reg = <e0000000 00100000>; // CCSRBAR 1M
49 bus-frequency = <0>; 49 bus-frequency = <0>;
50 50
51 memory-controller@2000 {
52 compatible = "fsl,8540-memory-controller";
53 reg = <2000 1000>;
54 interrupt-parent = <&mpic>;
55 interrupts = <2 2>;
56 };
57
58 l2-cache-controller@20000 {
59 compatible = "fsl,8540-l2-cache-controller";
60 reg = <20000 1000>;
61 cache-line-size = <20>; // 32 bytes
62 cache-size = <40000>; // L2, 256K
63 interrupt-parent = <&mpic>;
64 interrupts = <0 2>;
65 };
66
51 i2c@3000 { 67 i2c@3000 {
52 device_type = "i2c"; 68 device_type = "i2c";
53 compatible = "fsl-i2c"; 69 compatible = "fsl-i2c";
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index b2b2200d0425..ad96381033c0 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -48,6 +48,22 @@
48 reg = <e0000000 00100000>; // CCSRBAR 1M 48 reg = <e0000000 00100000>; // CCSRBAR 1M
49 bus-frequency = <0>; 49 bus-frequency = <0>;
50 50
51 memory-controller@2000 {
52 compatible = "fsl,8548-memory-controller";
53 reg = <2000 1000>;
54 interrupt-parent = <&mpic>;
55 interrupts = <2 2>;
56 };
57
58 l2-cache-controller@20000 {
59 compatible = "fsl,8548-l2-cache-controller";
60 reg = <20000 1000>;
61 cache-line-size = <20>; // 32 bytes
62 cache-size = <80000>; // L2, 512K
63 interrupt-parent = <&mpic>;
64 interrupts = <0 2>;
65 };
66
51 i2c@3000 { 67 i2c@3000 {
52 device_type = "i2c"; 68 device_type = "i2c";
53 compatible = "fsl-i2c"; 69 compatible = "fsl-i2c";
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index 1f2afe9291d2..80682152b0cf 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -48,6 +48,22 @@
48 reg = <e0000000 00000200>; 48 reg = <e0000000 00000200>;
49 bus-frequency = <13ab6680>; 49 bus-frequency = <13ab6680>;
50 50
51 memory-controller@2000 {
52 compatible = "fsl,8540-memory-controller";
53 reg = <2000 1000>;
54 interrupt-parent = <&mpic>;
55 interrupts = <2 2>;
56 };
57
58 l2-cache-controller@20000 {
59 compatible = "fsl,8540-l2-cache-controller";
60 reg = <20000 1000>;
61 cache-line-size = <20>; // 32 bytes
62 cache-size = <40000>; // L2, 256K
63 interrupt-parent = <&mpic>;
64 interrupts = <0 2>;
65 };
66
51 mdio@24520 { 67 mdio@24520 {
52 device_type = "mdio"; 68 device_type = "mdio";
53 compatible = "gianfar"; 69 compatible = "gianfar";
@@ -110,7 +126,7 @@
110 #address-cells = <3>; 126 #address-cells = <3>;
111 compatible = "85xx"; 127 compatible = "85xx";
112 device_type = "pci"; 128 device_type = "pci";
113 reg = <8000 400>; 129 reg = <8000 1000>;
114 clock-frequency = <3f940aa>; 130 clock-frequency = <3f940aa>;
115 interrupt-map-mask = <f800 0 0 7>; 131 interrupt-map-mask = <f800 0 0 7>;
116 interrupt-map = < 132 interrupt-map = <