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authorEliezer Tamir <eliezert@broadcom.com>2007-11-15 13:09:02 -0500
committerDavid S. Miller <davem@davemloft.net>2008-01-28 18:03:53 -0500
commita2fbb9ea235467b0be6db3cec0132b6c83c0b9fb (patch)
treef6717161d5f374e84553f579eb3102bcf9ffdc0f
parentfaa4f7969f3340606f46515560ce193d9bd74ea4 (diff)
add bnx2x driver for BCM57710
Signed-off-by: Eliezer Tamir <eliezert@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/Kconfig9
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/bnx2x.c9065
-rw-r--r--drivers/net/bnx2x.h1071
-rw-r--r--drivers/net/bnx2x_fw_defs.h198
-rw-r--r--drivers/net/bnx2x_hsi.h2176
-rw-r--r--drivers/net/bnx2x_init.h564
-rw-r--r--drivers/net/bnx2x_init_values.h6368
-rw-r--r--drivers/net/bnx2x_reg.h4394
-rw-r--r--include/linux/pci_ids.h1
10 files changed, 23847 insertions, 0 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 7ae9024b5833..b034410b7ab6 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2597,6 +2597,15 @@ config TEHUTI
2597 help 2597 help
2598 Tehuti Networks 10G Ethernet NIC 2598 Tehuti Networks 10G Ethernet NIC
2599 2599
2600config BNX2X
2601 tristate "Broadcom NetXtremeII 10Gb support"
2602 depends on PCI
2603 help
2604 This driver supports Broadcom NetXtremeII 10 gigabit Ethernet cards.
2605 To compile this driver as a module, choose M here: the module
2606 will be called bnx2x. This is recommended.
2607
2608
2600endif # NETDEV_10000 2609endif # NETDEV_10000
2601 2610
2602source "drivers/net/tokenring/Kconfig" 2611source "drivers/net/tokenring/Kconfig"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 5dd2d5eb1918..5e36f203ce5c 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -65,6 +65,7 @@ obj-$(CONFIG_STNIC) += stnic.o 8390.o
65obj-$(CONFIG_FEALNX) += fealnx.o 65obj-$(CONFIG_FEALNX) += fealnx.o
66obj-$(CONFIG_TIGON3) += tg3.o 66obj-$(CONFIG_TIGON3) += tg3.o
67obj-$(CONFIG_BNX2) += bnx2.o 67obj-$(CONFIG_BNX2) += bnx2.o
68obj-$(CONFIG_BNX2X) += bnx2x.o
68spidernet-y += spider_net.o spider_net_ethtool.o 69spidernet-y += spider_net.o spider_net_ethtool.o
69obj-$(CONFIG_SPIDER_NET) += spidernet.o sungem_phy.o 70obj-$(CONFIG_SPIDER_NET) += spidernet.o sungem_phy.o
70obj-$(CONFIG_GELIC_NET) += ps3_gelic.o 71obj-$(CONFIG_GELIC_NET) += ps3_gelic.o
diff --git a/drivers/net/bnx2x.c b/drivers/net/bnx2x.c
new file mode 100644
index 000000000000..e8c5754798ea
--- /dev/null
+++ b/drivers/net/bnx2x.c
@@ -0,0 +1,9065 @@
1/* bnx2x.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Eliezer Tamir <eliezert@broadcom.com>
10 * Based on code from Michael Chan's bnx2 driver
11 * UDP CSUM errata workaround by Arik Gendelman
12 * Slowpath rework by Vladislav Zolotarov
13 * Statistics and Link managment by Yitchak Gertner
14 *
15 */
16
17/* define this to make the driver freeze on error
18 * to allow getting debug info
19 * (you will need to reboot afterwords)
20 */
21/*#define BNX2X_STOP_ON_ERROR*/
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/kernel.h>
26#include <linux/device.h> /* for dev_info() */
27#include <linux/timer.h>
28#include <linux/errno.h>
29#include <linux/ioport.h>
30#include <linux/slab.h>
31#include <linux/vmalloc.h>
32#include <linux/interrupt.h>
33#include <linux/pci.h>
34#include <linux/init.h>
35#include <linux/netdevice.h>
36#include <linux/etherdevice.h>
37#include <linux/skbuff.h>
38#include <linux/dma-mapping.h>
39#include <linux/bitops.h>
40#include <linux/irq.h>
41#include <linux/delay.h>
42#include <asm/byteorder.h>
43#include <linux/time.h>
44#include <linux/ethtool.h>
45#include <linux/mii.h>
46#ifdef NETIF_F_HW_VLAN_TX
47 #include <linux/if_vlan.h>
48 #define BCM_VLAN 1
49#endif
50#include <net/ip.h>
51#include <net/tcp.h>
52#include <net/checksum.h>
53#include <linux/workqueue.h>
54#include <linux/crc32.h>
55#include <linux/prefetch.h>
56#include <linux/zlib.h>
57#include <linux/version.h>
58#include <linux/io.h>
59
60#include "bnx2x_reg.h"
61#include "bnx2x_fw_defs.h"
62#include "bnx2x_hsi.h"
63#include "bnx2x.h"
64#include "bnx2x_init.h"
65
66#define DRV_MODULE_VERSION "0.40.15"
67#define DRV_MODULE_RELDATE "$DateTime: 2007/11/15 07:28:37 $"
68#define BNX2X_BC_VER 0x040009
69
70/* Time in jiffies before concluding the transmitter is hung. */
71#define TX_TIMEOUT (5*HZ)
72
73static const char version[] __devinitdata =
74 "Broadcom NetXtreme II 577xx 10Gigabit Ethernet Driver "
75 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
76
77MODULE_AUTHOR("Eliezer Tamir <eliezert@broadcom.com>");
78MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710 Driver");
79MODULE_LICENSE("GPL");
80MODULE_VERSION(DRV_MODULE_VERSION);
81MODULE_INFO(cvs_version, "$Revision: #356 $");
82
83static int use_inta;
84static int poll;
85static int onefunc;
86static int nomcp;
87static int debug;
88static int use_multi;
89
90module_param(use_inta, int, 0);
91module_param(poll, int, 0);
92module_param(onefunc, int, 0);
93module_param(debug, int, 0);
94MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X");
95MODULE_PARM_DESC(poll, "use polling (for debug)");
96MODULE_PARM_DESC(onefunc, "enable only first function");
97MODULE_PARM_DESC(nomcp, "ignore managment CPU (Implies onefunc)");
98MODULE_PARM_DESC(debug, "defualt debug msglevel");
99
100#ifdef BNX2X_MULTI
101module_param(use_multi, int, 0);
102MODULE_PARM_DESC(use_multi, "use per-CPU queues");
103#endif
104
105enum bnx2x_board_type {
106 BCM57710 = 0,
107};
108
109/* indexed by board_t, above */
110static const struct {
111 char *name;
112} board_info[] __devinitdata = {
113 { "Broadcom NetXtreme II BCM57710 XGb" }
114};
115
116static const struct pci_device_id bnx2x_pci_tbl[] = {
117 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57710,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57710 },
119 { 0 }
120};
121
122MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
123
124/****************************************************************************
125* General service functions
126****************************************************************************/
127
128/* used only at init
129 * locking is done by mcp
130 */
131static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
132{
133 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
134 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
135 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
136 PCICFG_VENDOR_ID_OFFSET);
137}
138
139#ifdef BNX2X_IND_RD
140static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
141{
142 u32 val;
143
144 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
145 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
146 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
147 PCICFG_VENDOR_ID_OFFSET);
148
149 return val;
150}
151#endif
152
153static const u32 dmae_reg_go_c[] = {
154 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
155 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
156 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
157 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
158};
159
160/* copy command into DMAE command memory and set DMAE command go */
161static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
162 int idx)
163{
164 u32 cmd_offset;
165 int i;
166
167 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
168 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
169 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
170
171/* DP(NETIF_MSG_DMAE, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
172 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); */
173 }
174 REG_WR(bp, dmae_reg_go_c[idx], 1);
175}
176
177static void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
178 u32 dst_addr, u32 len32)
179{
180 struct dmae_command *dmae = &bp->dmae;
181 int port = bp->port;
182 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
183 int timeout = 200;
184
185 memset(dmae, 0, sizeof(struct dmae_command));
186
187 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
188 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
189 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
190#ifdef __BIG_ENDIAN
191 DMAE_CMD_ENDIANITY_B_DW_SWAP |
192#else
193 DMAE_CMD_ENDIANITY_DW_SWAP |
194#endif
195 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
196 dmae->src_addr_lo = U64_LO(dma_addr);
197 dmae->src_addr_hi = U64_HI(dma_addr);
198 dmae->dst_addr_lo = dst_addr >> 2;
199 dmae->dst_addr_hi = 0;
200 dmae->len = len32;
201 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
202 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
203 dmae->comp_val = BNX2X_WB_COMP_VAL;
204
205/*
206 DP(NETIF_MSG_DMAE, "dmae: opcode 0x%08x\n"
207 DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
208 "dst_addr [%x:%08x (%08x)]\n"
209 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
210 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
211 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr,
212 dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
213*/
214/*
215 DP(NETIF_MSG_DMAE, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
216 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
217 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
218*/
219
220 *wb_comp = 0;
221
222 bnx2x_post_dmae(bp, dmae, port * 8);
223
224 udelay(5);
225 /* adjust timeout for emulation/FPGA */
226 if (CHIP_REV_IS_SLOW(bp))
227 timeout *= 100;
228 while (*wb_comp != BNX2X_WB_COMP_VAL) {
229/* DP(NETIF_MSG_DMAE, "wb_comp 0x%08x\n", *wb_comp); */
230 udelay(5);
231 if (!timeout) {
232 BNX2X_ERR("dmae timeout!\n");
233 break;
234 }
235 timeout--;
236 }
237}
238
239#ifdef BNX2X_DMAE_RD
240static void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
241{
242 struct dmae_command *dmae = &bp->dmae;
243 int port = bp->port;
244 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
245 int timeout = 200;
246
247 memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
248 memset(dmae, 0, sizeof(struct dmae_command));
249
250 dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
251 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
252 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
253#ifdef __BIG_ENDIAN
254 DMAE_CMD_ENDIANITY_B_DW_SWAP |
255#else
256 DMAE_CMD_ENDIANITY_DW_SWAP |
257#endif
258 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
259 dmae->src_addr_lo = src_addr >> 2;
260 dmae->src_addr_hi = 0;
261 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
262 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
263 dmae->len = len32;
264 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
265 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
266 dmae->comp_val = BNX2X_WB_COMP_VAL;
267
268/*
269 DP(NETIF_MSG_DMAE, "dmae: opcode 0x%08x\n"
270 DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
271 "dst_addr [%x:%08x (%08x)]\n"
272 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
273 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
274 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr,
275 dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
276*/
277
278 *wb_comp = 0;
279
280 bnx2x_post_dmae(bp, dmae, port * 8);
281
282 udelay(5);
283 while (*wb_comp != BNX2X_WB_COMP_VAL) {
284 udelay(5);
285 if (!timeout) {
286 BNX2X_ERR("dmae timeout!\n");
287 break;
288 }
289 timeout--;
290 }
291/*
292 DP(NETIF_MSG_DMAE, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
293 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
294 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
295*/
296}
297#endif
298
299static int bnx2x_mc_assert(struct bnx2x *bp)
300{
301 int i, j;
302 int rc = 0;
303 char last_idx;
304 const char storm[] = {"XTCU"};
305 const u32 intmem_base[] = {
306 BAR_XSTRORM_INTMEM,
307 BAR_TSTRORM_INTMEM,
308 BAR_CSTRORM_INTMEM,
309 BAR_USTRORM_INTMEM
310 };
311
312 /* Go through all instances of all SEMIs */
313 for (i = 0; i < 4; i++) {
314 last_idx = REG_RD8(bp, XSTORM_ASSERT_LIST_INDEX_OFFSET +
315 intmem_base[i]);
316 BNX2X_ERR("DATA %cSTORM_ASSERT_LIST_INDEX 0x%x\n",
317 storm[i], last_idx);
318
319 /* print the asserts */
320 for (j = 0; j < STROM_ASSERT_ARRAY_SIZE; j++) {
321 u32 row0, row1, row2, row3;
322
323 row0 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) +
324 intmem_base[i]);
325 row1 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) + 4 +
326 intmem_base[i]);
327 row2 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) + 8 +
328 intmem_base[i]);
329 row3 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) + 12 +
330 intmem_base[i]);
331
332 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
333 BNX2X_ERR("DATA %cSTORM_ASSERT_INDEX 0x%x ="
334 " 0x%08x 0x%08x 0x%08x 0x%08x\n",
335 storm[i], j, row3, row2, row1, row0);
336 rc++;
337 } else {
338 break;
339 }
340 }
341 }
342 return rc;
343}
344static void bnx2x_fw_dump(struct bnx2x *bp)
345{
346 u32 mark, offset;
347 u32 data[9];
348 int word;
349
350 mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104);
351 printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n", mark);
352
353 for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) {
354 for (word = 0; word < 8; word++)
355 data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
356 offset + 4*word));
357 data[8] = 0x0;
358 printk(KERN_ERR PFX "%s", (char *)data);
359 }
360 for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) {
361 for (word = 0; word < 8; word++)
362 data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
363 offset + 4*word));
364 data[8] = 0x0;
365 printk(KERN_ERR PFX "%s", (char *)data);
366 }
367 printk("\n" KERN_ERR PFX "end of fw dump\n");
368}
369
370static void bnx2x_panic_dump(struct bnx2x *bp)
371{
372 int i;
373 u16 j, start, end;
374
375 BNX2X_ERR("begin crash dump -----------------\n");
376
377 for_each_queue(bp, i) {
378 struct bnx2x_fastpath *fp = &bp->fp[i];
379 struct eth_tx_db_data *hw_prods = fp->hw_tx_prods;
380
381 BNX2X_ERR("queue[%d]: tx_pkt_prod(%x) tx_pkt_cons(%x)"
382 " tx_bd_prod(%x) tx_bd_cons(%x) *tx_cons_sb(%x)"
383 " *rx_cons_sb(%x) rx_comp_prod(%x)"
384 " rx_comp_cons(%x) fp_c_idx(%x) fp_u_idx(%x)"
385 " bd data(%x,%x)\n",
386 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
387 fp->tx_bd_cons, *fp->tx_cons_sb, *fp->rx_cons_sb,
388 fp->rx_comp_prod, fp->rx_comp_cons, fp->fp_c_idx,
389 fp->fp_u_idx, hw_prods->packets_prod,
390 hw_prods->bds_prod);
391
392 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
393 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
394 for (j = start; j < end; j++) {
395 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
396
397 BNX2X_ERR("packet[%x]=[%p,%x]\n", j,
398 sw_bd->skb, sw_bd->first_bd);
399 }
400
401 start = TX_BD(fp->tx_bd_cons - 10);
402 end = TX_BD(fp->tx_bd_cons + 254);
403 for (j = start; j < end; j++) {
404 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
405
406 BNX2X_ERR("tx_bd[%x]=[%x:%x:%x:%x]\n",
407 j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
408 }
409
410 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
411 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
412 for (j = start; j < end; j++) {
413 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
414 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
415
416 BNX2X_ERR("rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
417 j, rx_bd[0], rx_bd[1], sw_bd->skb);
418 }
419
420 start = RCQ_BD(fp->rx_comp_cons - 10);
421 end = RCQ_BD(fp->rx_comp_cons + 503);
422 for (j = start; j < end; j++) {
423 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
424
425 BNX2X_ERR("cqe[%x]=[%x:%x:%x:%x]\n",
426 j, cqe[0], cqe[1], cqe[2], cqe[3]);
427 }
428 }
429
430 BNX2X_ERR("def_c_idx(%u) def_u_idx(%u) def_t_idx(%u)"
431 " def_x_idx(%u) def_att_idx(%u) attn_state(%u)"
432 " spq_prod_idx(%u)\n",
433 bp->def_c_idx, bp->def_u_idx, bp->def_t_idx, bp->def_x_idx,
434 bp->def_att_idx, bp->attn_state, bp->spq_prod_idx);
435
436
437 bnx2x_mc_assert(bp);
438 BNX2X_ERR("end crash dump -----------------\n");
439
440 bp->stats_state = STATS_STATE_DISABLE;
441 DP(BNX2X_MSG_STATS, "stats_state - DISABLE\n");
442}
443
444static void bnx2x_enable_int(struct bnx2x *bp)
445{
446 int port = bp->port;
447 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
448 u32 val = REG_RD(bp, addr);
449 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
450
451 if (msix) {
452 val &= ~HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
453 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
454 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
455 } else {
456 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
457 HC_CONFIG_0_REG_INT_LINE_EN_0 |
458 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
459 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
460 }
461
462 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) msi %d\n",
463 val, port, addr, msix);
464
465 REG_WR(bp, addr, val);
466}
467
468static void bnx2x_disable_int(struct bnx2x *bp)
469{
470 int port = bp->port;
471 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
472 u32 val = REG_RD(bp, addr);
473
474 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
475 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
476 HC_CONFIG_0_REG_INT_LINE_EN_0 |
477 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
478
479 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
480 val, port, addr);
481
482 REG_WR(bp, addr, val);
483 if (REG_RD(bp, addr) != val)
484 BNX2X_ERR("BUG! proper val not read from IGU!\n");
485}
486
487static void bnx2x_disable_int_sync(struct bnx2x *bp)
488{
489
490 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
491 int i;
492
493 atomic_inc(&bp->intr_sem);
494 /* prevent the HW from sending interrupts*/
495 bnx2x_disable_int(bp);
496
497 /* make sure all ISRs are done */
498 if (msix) {
499 for_each_queue(bp, i)
500 synchronize_irq(bp->msix_table[i].vector);
501
502 /* one more for the Slow Path IRQ */
503 synchronize_irq(bp->msix_table[i].vector);
504 } else
505 synchronize_irq(bp->pdev->irq);
506
507 /* make sure sp_task is not running */
508 cancel_work_sync(&bp->sp_task);
509
510}
511
512/* fast path code */
513
514/*
515 * general service functions
516 */
517
518static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 id,
519 u8 storm, u16 index, u8 op, u8 update)
520{
521 u32 igu_addr = (IGU_ADDR_INT_ACK + IGU_PORT_BASE * bp->port) * 8;
522 struct igu_ack_register igu_ack;
523
524 igu_ack.status_block_index = index;
525 igu_ack.sb_id_and_flags =
526 ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
527 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
528 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
529 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
530
531/* DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
532 (*(u32 *)&igu_ack), BAR_IGU_INTMEM + igu_addr); */
533 REG_WR(bp, BAR_IGU_INTMEM + igu_addr, (*(u32 *)&igu_ack));
534}
535
536static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
537{
538 struct host_status_block *fpsb = fp->status_blk;
539 u16 rc = 0;
540
541 barrier(); /* status block is written to by the chip */
542 if (fp->fp_c_idx != fpsb->c_status_block.status_block_index) {
543 fp->fp_c_idx = fpsb->c_status_block.status_block_index;
544 rc |= 1;
545 }
546 if (fp->fp_u_idx != fpsb->u_status_block.status_block_index) {
547 fp->fp_u_idx = fpsb->u_status_block.status_block_index;
548 rc |= 2;
549 }
550 return rc;
551}
552
553static inline int bnx2x_has_work(struct bnx2x_fastpath *fp)
554{
555 u16 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
556
557 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
558 rx_cons_sb++;
559
560 if ((rx_cons_sb != fp->rx_comp_cons) ||
561 (le16_to_cpu(*fp->tx_cons_sb) != fp->tx_pkt_cons))
562 return 1;
563
564 return 0;
565}
566
567static u16 bnx2x_ack_int(struct bnx2x *bp)
568{
569 u32 igu_addr = (IGU_ADDR_SIMD_MASK + IGU_PORT_BASE * bp->port) * 8;
570 u32 result = REG_RD(bp, BAR_IGU_INTMEM + igu_addr);
571
572/* DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n",
573 result, BAR_IGU_INTMEM + igu_addr); */
574
575#ifdef IGU_DEBUG
576#warning IGU_DEBUG active
577 if (result == 0) {
578 BNX2X_ERR("read %x from IGU\n", result);
579 REG_WR(bp, TM_REG_TIMER_SOFT_RST, 0);
580 }
581#endif
582 return result;
583}
584
585
586/*
587 * fast path service functions
588 */
589
590/* free skb in the packet ring at pos idx
591 * return idx of last bd freed
592 */
593static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp,
594 u16 idx)
595{
596 struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx];
597 struct eth_tx_bd *tx_bd;
598 struct sk_buff *skb = tx_buf->skb;
599 u16 bd_idx = tx_buf->first_bd;
600 int nbd;
601
602 DP(BNX2X_MSG_OFF, "pkt_idx %d buff @(%p)->skb %p\n",
603 idx, tx_buf, skb);
604
605 /* unmap first bd */
606 DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx);
607 tx_bd = &fp->tx_desc_ring[bd_idx];
608 pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_bd),
609 BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
610
611 nbd = le16_to_cpu(tx_bd->nbd) - 1;
612#ifdef BNX2X_STOP_ON_ERROR
613 if (nbd > (MAX_SKB_FRAGS + 2)) {
614 BNX2X_ERR("bad nbd!\n");
615 bnx2x_panic();
616 }
617#endif
618
619 /* Skip a parse bd and the TSO split header bd
620 since they have no mapping */
621 if (nbd)
622 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
623
624 if (tx_bd->bd_flags.as_bitfield & (ETH_TX_BD_FLAGS_IP_CSUM |
625 ETH_TX_BD_FLAGS_TCP_CSUM |
626 ETH_TX_BD_FLAGS_SW_LSO)) {
627 if (--nbd)
628 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
629 tx_bd = &fp->tx_desc_ring[bd_idx];
630 /* is this a TSO split header bd? */
631 if (tx_bd->bd_flags.as_bitfield & ETH_TX_BD_FLAGS_SW_LSO) {
632 if (--nbd)
633 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
634 }
635 }
636
637 /* now free frags */
638 while (nbd > 0) {
639
640 DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx);
641 tx_bd = &fp->tx_desc_ring[bd_idx];
642 pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_bd),
643 BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
644 if (--nbd)
645 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
646 }
647
648 /* release skb */
649 BUG_TRAP(skb);
650 dev_kfree_skb(skb);
651 tx_buf->first_bd = 0;
652 tx_buf->skb = NULL;
653
654 return bd_idx;
655}
656
657static inline u32 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
658{
659 u16 used;
660 u32 prod;
661 u32 cons;
662
663 /* Tell compiler that prod and cons can change */
664 barrier();
665 prod = fp->tx_bd_prod;
666 cons = fp->tx_bd_cons;
667
668 used = (NUM_TX_BD - NUM_TX_RINGS + prod - cons +
669 (cons / TX_DESC_CNT) - (prod / TX_DESC_CNT));
670
671 if (prod >= cons) {
672 /* used = prod - cons - prod/size + cons/size */
673 used -= NUM_TX_BD - NUM_TX_RINGS;
674 }
675
676 BUG_TRAP(used <= fp->bp->tx_ring_size);
677 BUG_TRAP((fp->bp->tx_ring_size - used) <= MAX_TX_AVAIL);
678
679 return (fp->bp->tx_ring_size - used);
680}
681
682static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work)
683{
684 struct bnx2x *bp = fp->bp;
685 u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons;
686 int done = 0;
687
688#ifdef BNX2X_STOP_ON_ERROR
689 if (unlikely(bp->panic))
690 return;
691#endif
692
693 hw_cons = le16_to_cpu(*fp->tx_cons_sb);
694 sw_cons = fp->tx_pkt_cons;
695
696 while (sw_cons != hw_cons) {
697 u16 pkt_cons;
698
699 pkt_cons = TX_BD(sw_cons);
700
701 /* prefetch(bp->tx_buf_ring[pkt_cons].skb); */
702
703 DP(NETIF_MSG_TX_DONE, "hw_cons %u sw_cons %u pkt_cons %d\n",
704 hw_cons, sw_cons, pkt_cons);
705
706/* if (NEXT_TX_IDX(sw_cons) != hw_cons) {
707 rmb();
708 prefetch(fp->tx_buf_ring[NEXT_TX_IDX(sw_cons)].skb);
709 }
710*/
711 bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons);
712 sw_cons++;
713 done++;
714
715 if (done == work)
716 break;
717 }
718
719 fp->tx_pkt_cons = sw_cons;
720 fp->tx_bd_cons = bd_cons;
721
722 /* Need to make the tx_cons update visible to start_xmit()
723 * before checking for netif_queue_stopped(). Without the
724 * memory barrier, there is a small possibility that start_xmit()
725 * will miss it and cause the queue to be stopped forever.
726 */
727 smp_mb();
728
729 /* TBD need a thresh? */
730 if (unlikely(netif_queue_stopped(bp->dev))) {
731
732 netif_tx_lock(bp->dev);
733
734 if (netif_queue_stopped(bp->dev) &&
735 (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
736 netif_wake_queue(bp->dev);
737
738 netif_tx_unlock(bp->dev);
739
740 }
741}
742
743static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
744 union eth_rx_cqe *rr_cqe)
745{
746 struct bnx2x *bp = fp->bp;
747 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
748 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
749
750 DP(NETIF_MSG_RX_STATUS,
751 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
752 fp->index, cid, command, bp->state, rr_cqe->ramrod_cqe.type);
753
754 bp->spq_left++;
755
756 if (fp->index) {
757 switch (command | fp->state) {
758 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP |
759 BNX2X_FP_STATE_OPENING):
760 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n",
761 cid);
762 fp->state = BNX2X_FP_STATE_OPEN;
763 break;
764
765 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
766 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n",
767 cid);
768 fp->state = BNX2X_FP_STATE_HALTED;
769 break;
770
771 default:
772 BNX2X_ERR("unexpected MC reply(%d) state is %x\n",
773 command, fp->state);
774 }
775 mb(); /* force bnx2x_wait_ramrod to see the change */
776 return;
777 }
778 switch (command | bp->state) {
779 case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
780 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
781 bp->state = BNX2X_STATE_OPEN;
782 break;
783
784 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT):
785 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
786 bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE;
787 fp->state = BNX2X_FP_STATE_HALTED;
788 break;
789
790 case (RAMROD_CMD_ID_ETH_PORT_DEL | BNX2X_STATE_CLOSING_WAIT4_DELETE):
791 DP(NETIF_MSG_IFDOWN, "got delete ramrod\n");
792 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
793 break;
794
795 case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT):
796 DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n", cid);
797 bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_DELETED;
798 break;
799
800 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
801 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
802 break;
803
804 default:
805 BNX2X_ERR("unexpected ramrod (%d) state is %x\n",
806 command, bp->state);
807 }
808
809 mb(); /* force bnx2x_wait_ramrod to see the change */
810}
811
812static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
813 struct bnx2x_fastpath *fp, u16 index)
814{
815 struct sk_buff *skb;
816 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
817 struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
818 dma_addr_t mapping;
819
820 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
821 if (unlikely(skb == NULL))
822 return -ENOMEM;
823
824 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
825 PCI_DMA_FROMDEVICE);
826 if (unlikely(dma_mapping_error(mapping))) {
827
828 dev_kfree_skb(skb);
829 return -ENOMEM;
830 }
831
832 rx_buf->skb = skb;
833 pci_unmap_addr_set(rx_buf, mapping, mapping);
834
835 rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
836 rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
837
838 return 0;
839}
840
841/* note that we are not allocating a new skb,
842 * we are just moving one from cons to prod
843 * we are not creating a new mapping,
844 * so there is no need to check for dma_mapping_error().
845 */
846static void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
847 struct sk_buff *skb, u16 cons, u16 prod)
848{
849 struct bnx2x *bp = fp->bp;
850 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
851 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
852 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
853 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
854
855 pci_dma_sync_single_for_device(bp->pdev,
856 pci_unmap_addr(cons_rx_buf, mapping),
857 bp->rx_offset + RX_COPY_THRESH,
858 PCI_DMA_FROMDEVICE);
859
860 prod_rx_buf->skb = cons_rx_buf->skb;
861 pci_unmap_addr_set(prod_rx_buf, mapping,
862 pci_unmap_addr(cons_rx_buf, mapping));
863 *prod_bd = *cons_bd;
864}
865
866static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
867{
868 struct bnx2x *bp = fp->bp;
869 u16 bd_cons, bd_prod, comp_ring_cons;
870 u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
871 int rx_pkt = 0;
872
873#ifdef BNX2X_STOP_ON_ERROR
874 if (unlikely(bp->panic))
875 return 0;
876#endif
877
878 hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb);
879 if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
880 hw_comp_cons++;
881
882 bd_cons = fp->rx_bd_cons;
883 bd_prod = fp->rx_bd_prod;
884 sw_comp_cons = fp->rx_comp_cons;
885 sw_comp_prod = fp->rx_comp_prod;
886
887 /* Memory barrier necessary as speculative reads of the rx
888 * buffer can be ahead of the index in the status block
889 */
890 rmb();
891
892 DP(NETIF_MSG_RX_STATUS,
893 "queue[%d]: hw_comp_cons %u sw_comp_cons %u\n",
894 fp->index, hw_comp_cons, sw_comp_cons);
895
896 while (sw_comp_cons != hw_comp_cons) {
897 unsigned int len, pad;
898 struct sw_rx_bd *rx_buf;
899 struct sk_buff *skb;
900 union eth_rx_cqe *cqe;
901
902 comp_ring_cons = RCQ_BD(sw_comp_cons);
903 bd_prod = RX_BD(bd_prod);
904 bd_cons = RX_BD(bd_cons);
905
906 cqe = &fp->rx_comp_ring[comp_ring_cons];
907
908 DP(NETIF_MSG_RX_STATUS, "hw_comp_cons %u sw_comp_cons %u"
909 " comp_ring (%u) bd_ring (%u,%u)\n",
910 hw_comp_cons, sw_comp_cons,
911 comp_ring_cons, bd_prod, bd_cons);
912 DP(NETIF_MSG_RX_STATUS, "CQE type %x err %x status %x"
913 " queue %x vlan %x len %x\n",
914 cqe->fast_path_cqe.type,
915 cqe->fast_path_cqe.error_type_flags,
916 cqe->fast_path_cqe.status_flags,
917 cqe->fast_path_cqe.rss_hash_result,
918 cqe->fast_path_cqe.vlan_tag, cqe->fast_path_cqe.pkt_len);
919
920 /* is this a slowpath msg? */
921 if (unlikely(cqe->fast_path_cqe.type)) {
922 bnx2x_sp_event(fp, cqe);
923 goto next_cqe;
924
925 /* this is an rx packet */
926 } else {
927 rx_buf = &fp->rx_buf_ring[bd_cons];
928 skb = rx_buf->skb;
929
930 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
931 pad = cqe->fast_path_cqe.placement_offset;
932
933 pci_dma_sync_single_for_device(bp->pdev,
934 pci_unmap_addr(rx_buf, mapping),
935 pad + RX_COPY_THRESH,
936 PCI_DMA_FROMDEVICE);
937 prefetch(skb);
938 prefetch(((char *)(skb)) + 128);
939
940 /* is this an error packet? */
941 if (unlikely(cqe->fast_path_cqe.error_type_flags &
942 ETH_RX_ERROR_FALGS)) {
943 /* do we sometimes forward error packets anyway? */
944 DP(NETIF_MSG_RX_ERR,
945 "ERROR flags(%u) Rx packet(%u)\n",
946 cqe->fast_path_cqe.error_type_flags,
947 sw_comp_cons);
948 /* TBD make sure MC counts this as a drop */
949 goto reuse_rx;
950 }
951
952 /* Since we don't have a jumbo ring
953 * copy small packets if mtu > 1500
954 */
955 if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
956 (len <= RX_COPY_THRESH)) {
957 struct sk_buff *new_skb;
958
959 new_skb = netdev_alloc_skb(bp->dev,
960 len + pad);
961 if (new_skb == NULL) {
962 DP(NETIF_MSG_RX_ERR,
963 "ERROR packet dropped "
964 "because of alloc failure\n");
965 /* TBD count this as a drop? */
966 goto reuse_rx;
967 }
968
969 /* aligned copy */
970 skb_copy_from_linear_data_offset(skb, pad,
971 new_skb->data + pad, len);
972 skb_reserve(new_skb, pad);
973 skb_put(new_skb, len);
974
975 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
976
977 skb = new_skb;
978
979 } else if (bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0) {
980 pci_unmap_single(bp->pdev,
981 pci_unmap_addr(rx_buf, mapping),
982 bp->rx_buf_use_size,
983 PCI_DMA_FROMDEVICE);
984 skb_reserve(skb, pad);
985 skb_put(skb, len);
986
987 } else {
988 DP(NETIF_MSG_RX_ERR,
989 "ERROR packet dropped because "
990 "of alloc failure\n");
991reuse_rx:
992 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
993 goto next_rx;
994 }
995
996 skb->protocol = eth_type_trans(skb, bp->dev);
997
998 skb->ip_summed = CHECKSUM_NONE;
999 if (bp->rx_csum && BNX2X_RX_SUM_OK(cqe))
1000 skb->ip_summed = CHECKSUM_UNNECESSARY;
1001
1002 /* TBD do we pass bad csum packets in promisc */
1003 }
1004
1005#ifdef BCM_VLAN
1006 if ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags)
1007 & PARSING_FLAGS_NUMBER_OF_NESTED_VLANS)
1008 && (bp->vlgrp != NULL))
1009 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1010 le16_to_cpu(cqe->fast_path_cqe.vlan_tag));
1011 else
1012#endif
1013 netif_receive_skb(skb);
1014
1015 bp->dev->last_rx = jiffies;
1016
1017next_rx:
1018 rx_buf->skb = NULL;
1019
1020 bd_cons = NEXT_RX_IDX(bd_cons);
1021 bd_prod = NEXT_RX_IDX(bd_prod);
1022next_cqe:
1023 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1024 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1025 rx_pkt++;
1026
1027 if ((rx_pkt == budget))
1028 break;
1029 } /* while */
1030
1031 fp->rx_bd_cons = bd_cons;
1032 fp->rx_bd_prod = bd_prod;
1033 fp->rx_comp_cons = sw_comp_cons;
1034 fp->rx_comp_prod = sw_comp_prod;
1035
1036 REG_WR(bp, BAR_TSTRORM_INTMEM +
1037 TSTORM_RCQ_PROD_OFFSET(bp->port, fp->index), sw_comp_prod);
1038
1039 mmiowb(); /* keep prod updates ordered */
1040
1041 fp->rx_pkt += rx_pkt;
1042 fp->rx_calls++;
1043
1044 return rx_pkt;
1045}
1046
1047static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1048{
1049 struct bnx2x_fastpath *fp = fp_cookie;
1050 struct bnx2x *bp = fp->bp;
1051 struct net_device *dev = bp->dev;
1052 int index = fp->index;
1053
1054 DP(NETIF_MSG_INTR, "got an msix interrupt on [%d]\n", index);
1055 bnx2x_ack_sb(bp, index, USTORM_ID, 0, IGU_INT_DISABLE, 0);
1056
1057#ifdef BNX2X_STOP_ON_ERROR
1058 if (unlikely(bp->panic))
1059 return IRQ_HANDLED;
1060#endif
1061
1062 prefetch(fp->rx_cons_sb);
1063 prefetch(fp->tx_cons_sb);
1064 prefetch(&fp->status_blk->c_status_block.status_block_index);
1065 prefetch(&fp->status_blk->u_status_block.status_block_index);
1066
1067 netif_rx_schedule(dev, &bnx2x_fp(bp, index, napi));
1068 return IRQ_HANDLED;
1069}
1070
1071static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1072{
1073 struct net_device *dev = dev_instance;
1074 struct bnx2x *bp = netdev_priv(dev);
1075 u16 status = bnx2x_ack_int(bp);
1076
1077 if (unlikely(status == 0)) {
1078 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1079 return IRQ_NONE;
1080 }
1081
1082 DP(NETIF_MSG_INTR, "got an interrupt status is %u\n", status);
1083
1084#ifdef BNX2X_STOP_ON_ERROR
1085 if (unlikely(bp->panic))
1086 return IRQ_HANDLED;
1087#endif
1088
1089 /* Return here if interrupt is shared and is disabled */
1090 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1091 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1092 return IRQ_HANDLED;
1093 }
1094
1095 if (status & 0x2) {
1096 struct bnx2x_fastpath *fp = &bp->fp[0];
1097
1098 prefetch(fp->rx_cons_sb);
1099 prefetch(fp->tx_cons_sb);
1100 prefetch(&fp->status_blk->c_status_block.status_block_index);
1101 prefetch(&fp->status_blk->u_status_block.status_block_index);
1102
1103 netif_rx_schedule(dev, &bnx2x_fp(bp, 0, napi));
1104
1105 status &= ~0x2;
1106 if (!status)
1107 return IRQ_HANDLED;
1108 }
1109
1110 if (unlikely(status & 0x1)) {
1111
1112 schedule_work(&bp->sp_task);
1113
1114 status &= ~0x1;
1115 if (!status)
1116 return IRQ_HANDLED;
1117 }
1118
1119 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status is %u)\n",
1120 status);
1121
1122 return IRQ_HANDLED;
1123}
1124
1125/* end of fast path */
1126
1127/* PHY/MAC */
1128
1129/*
1130 * General service functions
1131 */
1132
1133static void bnx2x_leds_set(struct bnx2x *bp, unsigned int speed)
1134{
1135 int port = bp->port;
1136
1137 NIG_WR(NIG_REG_LED_MODE_P0 + port*4,
1138 ((bp->hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
1139 SHARED_HW_CFG_LED_MODE_SHIFT));
1140 NIG_WR(NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
1141
1142 /* Set blinking rate to ~15.9Hz */
1143 NIG_WR(NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
1144 LED_BLINK_RATE_VAL);
1145 NIG_WR(NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port*4, 1);
1146
1147 /* On Ax chip versions for speeds less than 10G
1148 LED scheme is different */
1149 if ((CHIP_REV(bp) == CHIP_REV_Ax) && (speed < SPEED_10000)) {
1150 NIG_WR(NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 1);
1151 NIG_WR(NIG_REG_LED_CONTROL_TRAFFIC_P0 + port*4, 0);
1152 NIG_WR(NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + port*4, 1);
1153 }
1154}
1155
1156static void bnx2x_leds_unset(struct bnx2x *bp)
1157{
1158 int port = bp->port;
1159
1160 NIG_WR(NIG_REG_LED_10G_P0 + port*4, 0);
1161 NIG_WR(NIG_REG_LED_MODE_P0 + port*4, SHARED_HW_CFG_LED_MAC1);
1162}
1163
1164static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
1165{
1166 u32 val = REG_RD(bp, reg);
1167
1168 val |= bits;
1169 REG_WR(bp, reg, val);
1170 return val;
1171}
1172
1173static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
1174{
1175 u32 val = REG_RD(bp, reg);
1176
1177 val &= ~bits;
1178 REG_WR(bp, reg, val);
1179 return val;
1180}
1181
1182static int bnx2x_mdio22_write(struct bnx2x *bp, u32 reg, u32 val)
1183{
1184 int rc;
1185 u32 tmp, i;
1186 int port = bp->port;
1187 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1188
1189/* DP(NETIF_MSG_HW, "phy_addr 0x%x reg 0x%x val 0x%08x\n",
1190 bp->phy_addr, reg, val); */
1191
1192 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1193
1194 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1195 tmp &= ~EMAC_MDIO_MODE_AUTO_POLL;
1196 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
1197 REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1198 udelay(40);
1199 }
1200
1201 tmp = ((bp->phy_addr << 21) | (reg << 16) |
1202 (val & EMAC_MDIO_COMM_DATA) |
1203 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
1204 EMAC_MDIO_COMM_START_BUSY);
1205 EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, tmp);
1206
1207 for (i = 0; i < 50; i++) {
1208 udelay(10);
1209
1210 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM);
1211 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1212 udelay(5);
1213 break;
1214 }
1215 }
1216
1217 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1218 BNX2X_ERR("write phy register failed\n");
1219
1220 rc = -EBUSY;
1221 } else {
1222 rc = 0;
1223 }
1224
1225 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1226
1227 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1228 tmp |= EMAC_MDIO_MODE_AUTO_POLL;
1229 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
1230 }
1231
1232 return rc;
1233}
1234
1235static int bnx2x_mdio22_read(struct bnx2x *bp, u32 reg, u32 *ret_val)
1236{
1237 int port = bp->port;
1238 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1239 u32 val, i;
1240 int rc;
1241
1242 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1243
1244 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1245 val &= ~EMAC_MDIO_MODE_AUTO_POLL;
1246 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
1247 REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1248 udelay(40);
1249 }
1250
1251 val = ((bp->phy_addr << 21) | (reg << 16) |
1252 EMAC_MDIO_COMM_COMMAND_READ_22 |
1253 EMAC_MDIO_COMM_START_BUSY);
1254 EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, val);
1255
1256 for (i = 0; i < 50; i++) {
1257 udelay(10);
1258
1259 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM);
1260 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1261 val &= EMAC_MDIO_COMM_DATA;
1262 break;
1263 }
1264 }
1265
1266 if (val & EMAC_MDIO_COMM_START_BUSY) {
1267 BNX2X_ERR("read phy register failed\n");
1268
1269 *ret_val = 0x0;
1270 rc = -EBUSY;
1271 } else {
1272 *ret_val = val;
1273 rc = 0;
1274 }
1275
1276 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1277
1278 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1279 val |= EMAC_MDIO_MODE_AUTO_POLL;
1280 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
1281 }
1282
1283/* DP(NETIF_MSG_HW, "phy_addr 0x%x reg 0x%x ret_val 0x%08x\n",
1284 bp->phy_addr, reg, *ret_val); */
1285
1286 return rc;
1287}
1288
1289static int bnx2x_mdio45_write(struct bnx2x *bp, u32 reg, u32 addr, u32 val)
1290{
1291 int rc = 0;
1292 u32 tmp, i;
1293 int port = bp->port;
1294 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1295
1296 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1297
1298 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1299 tmp &= ~EMAC_MDIO_MODE_AUTO_POLL;
1300 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
1301 REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1302 udelay(40);
1303 }
1304
1305 /* set clause 45 mode */
1306 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1307 tmp |= EMAC_MDIO_MODE_CLAUSE_45;
1308 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
1309
1310 /* address */
1311 tmp = ((bp->phy_addr << 21) | (reg << 16) | addr |
1312 EMAC_MDIO_COMM_COMMAND_ADDRESS |
1313 EMAC_MDIO_COMM_START_BUSY);
1314 EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, tmp);
1315
1316 for (i = 0; i < 50; i++) {
1317 udelay(10);
1318
1319 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM);
1320 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1321 udelay(5);
1322 break;
1323 }
1324 }
1325
1326 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1327 BNX2X_ERR("write phy register failed\n");
1328
1329 rc = -EBUSY;
1330 } else {
1331 /* data */
1332 tmp = ((bp->phy_addr << 21) | (reg << 16) | val |
1333 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
1334 EMAC_MDIO_COMM_START_BUSY);
1335 EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, tmp);
1336
1337 for (i = 0; i < 50; i++) {
1338 udelay(10);
1339
1340 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM);
1341 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1342 udelay(5);
1343 break;
1344 }
1345 }
1346
1347 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1348 BNX2X_ERR("write phy register failed\n");
1349
1350 rc = -EBUSY;
1351 }
1352 }
1353
1354 /* unset clause 45 mode */
1355 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1356 tmp &= ~EMAC_MDIO_MODE_CLAUSE_45;
1357 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
1358
1359 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1360
1361 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1362 tmp |= EMAC_MDIO_MODE_AUTO_POLL;
1363 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
1364 }
1365
1366 return rc;
1367}
1368
1369static int bnx2x_mdio45_read(struct bnx2x *bp, u32 reg, u32 addr,
1370 u32 *ret_val)
1371{
1372 int port = bp->port;
1373 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1374 u32 val, i;
1375 int rc = 0;
1376
1377 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1378
1379 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1380 val &= ~EMAC_MDIO_MODE_AUTO_POLL;
1381 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
1382 REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1383 udelay(40);
1384 }
1385
1386 /* set clause 45 mode */
1387 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1388 val |= EMAC_MDIO_MODE_CLAUSE_45;
1389 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
1390
1391 /* address */
1392 val = ((bp->phy_addr << 21) | (reg << 16) | addr |
1393 EMAC_MDIO_COMM_COMMAND_ADDRESS |
1394 EMAC_MDIO_COMM_START_BUSY);
1395 EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, val);
1396
1397 for (i = 0; i < 50; i++) {
1398 udelay(10);
1399
1400 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM);
1401 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1402 udelay(5);
1403 break;
1404 }
1405 }
1406
1407 if (val & EMAC_MDIO_COMM_START_BUSY) {
1408 BNX2X_ERR("read phy register failed\n");
1409
1410 *ret_val = 0;
1411 rc = -EBUSY;
1412 } else {
1413 /* data */
1414 val = ((bp->phy_addr << 21) | (reg << 16) |
1415 EMAC_MDIO_COMM_COMMAND_READ_45 |
1416 EMAC_MDIO_COMM_START_BUSY);
1417 EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, val);
1418
1419 for (i = 0; i < 50; i++) {
1420 udelay(10);
1421
1422 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM);
1423 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1424 val &= EMAC_MDIO_COMM_DATA;
1425 break;
1426 }
1427 }
1428
1429 if (val & EMAC_MDIO_COMM_START_BUSY) {
1430 BNX2X_ERR("read phy register failed\n");
1431
1432 val = 0;
1433 rc = -EBUSY;
1434 }
1435
1436 *ret_val = val;
1437 }
1438
1439 /* unset clause 45 mode */
1440 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1441 val &= ~EMAC_MDIO_MODE_CLAUSE_45;
1442 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
1443
1444 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1445
1446 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1447 val |= EMAC_MDIO_MODE_AUTO_POLL;
1448 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
1449 }
1450
1451 return rc;
1452}
1453
1454static int bnx2x_mdio45_vwrite(struct bnx2x *bp, u32 reg, u32 addr, u32 val)
1455{
1456 int i;
1457 u32 rd_val;
1458
1459 might_sleep();
1460 for (i = 0; i < 10; i++) {
1461 bnx2x_mdio45_write(bp, reg, addr, val);
1462 msleep(5);
1463 bnx2x_mdio45_read(bp, reg, addr, &rd_val);
1464 /* if the read value is not the same as the value we wrote,
1465 we should write it again */
1466 if (rd_val == val)
1467 return 0;
1468 }
1469 BNX2X_ERR("MDIO write in CL45 failed\n");
1470 return -EBUSY;
1471}
1472
1473/*
1474 * link managment
1475 */
1476
1477static void bnx2x_flow_ctrl_resolve(struct bnx2x *bp, u32 gp_status)
1478{
1479 u32 ld_pause; /* local driver */
1480 u32 lp_pause; /* link partner */
1481 u32 pause_result;
1482
1483 bp->flow_ctrl = 0;
1484
1485 /* reolve from gp_status in case of AN complete and not sgmii */
1486 if ((bp->req_autoneg & AUTONEG_FLOW_CTRL) &&
1487 (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
1488 (!(bp->phy_flags & PHY_SGMII_FLAG)) &&
1489 (XGXS_EXT_PHY_TYPE(bp) == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
1490
1491 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
1492 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
1493 &ld_pause);
1494 bnx2x_mdio22_read(bp,
1495 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
1496 &lp_pause);
1497 pause_result = (ld_pause &
1498 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
1499 pause_result |= (lp_pause &
1500 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
1501 DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result);
1502
1503 switch (pause_result) { /* ASYM P ASYM P */
1504 case 0xb: /* 1 0 1 1 */
1505 bp->flow_ctrl = FLOW_CTRL_TX;
1506 break;
1507
1508 case 0xe: /* 1 1 1 0 */
1509 bp->flow_ctrl = FLOW_CTRL_RX;
1510 break;
1511
1512 case 0x5: /* 0 1 0 1 */
1513 case 0x7: /* 0 1 1 1 */
1514 case 0xd: /* 1 1 0 1 */
1515 case 0xf: /* 1 1 1 1 */
1516 bp->flow_ctrl = FLOW_CTRL_BOTH;
1517 break;
1518
1519 default:
1520 break;
1521 }
1522
1523 } else { /* forced mode */
1524 switch (bp->req_flow_ctrl) {
1525 case FLOW_CTRL_AUTO:
1526 if (bp->dev->mtu <= 4500)
1527 bp->flow_ctrl = FLOW_CTRL_BOTH;
1528 else
1529 bp->flow_ctrl = FLOW_CTRL_TX;
1530 break;
1531
1532 case FLOW_CTRL_TX:
1533 case FLOW_CTRL_RX:
1534 case FLOW_CTRL_BOTH:
1535 bp->flow_ctrl = bp->req_flow_ctrl;
1536 break;
1537
1538 case FLOW_CTRL_NONE:
1539 default:
1540 break;
1541 }
1542 }
1543 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", bp->flow_ctrl);
1544}
1545
1546static void bnx2x_link_settings_status(struct bnx2x *bp, u32 gp_status)
1547{
1548 bp->link_status = 0;
1549
1550 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
1551 DP(NETIF_MSG_LINK, "link up\n");
1552
1553 bp->link_up = 1;
1554 bp->link_status |= LINK_STATUS_LINK_UP;
1555
1556 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
1557 bp->duplex = DUPLEX_FULL;
1558 else
1559 bp->duplex = DUPLEX_HALF;
1560
1561 bnx2x_flow_ctrl_resolve(bp, gp_status);
1562
1563 switch (gp_status & GP_STATUS_SPEED_MASK) {
1564 case GP_STATUS_10M:
1565 bp->line_speed = SPEED_10;
1566 if (bp->duplex == DUPLEX_FULL)
1567 bp->link_status |= LINK_10TFD;
1568 else
1569 bp->link_status |= LINK_10THD;
1570 break;
1571
1572 case GP_STATUS_100M:
1573 bp->line_speed = SPEED_100;
1574 if (bp->duplex == DUPLEX_FULL)
1575 bp->link_status |= LINK_100TXFD;
1576 else
1577 bp->link_status |= LINK_100TXHD;
1578 break;
1579
1580 case GP_STATUS_1G:
1581 case GP_STATUS_1G_KX:
1582 bp->line_speed = SPEED_1000;
1583 if (bp->duplex == DUPLEX_FULL)
1584 bp->link_status |= LINK_1000TFD;
1585 else
1586 bp->link_status |= LINK_1000THD;
1587 break;
1588
1589 case GP_STATUS_2_5G:
1590 bp->line_speed = SPEED_2500;
1591 if (bp->duplex == DUPLEX_FULL)
1592 bp->link_status |= LINK_2500TFD;
1593 else
1594 bp->link_status |= LINK_2500THD;
1595 break;
1596
1597 case GP_STATUS_5G:
1598 case GP_STATUS_6G:
1599 BNX2X_ERR("link speed unsupported gp_status 0x%x\n",
1600 gp_status);
1601 break;
1602
1603 case GP_STATUS_10G_KX4:
1604 case GP_STATUS_10G_HIG:
1605 case GP_STATUS_10G_CX4:
1606 bp->line_speed = SPEED_10000;
1607 bp->link_status |= LINK_10GTFD;
1608 break;
1609
1610 case GP_STATUS_12G_HIG:
1611 bp->line_speed = SPEED_12000;
1612 bp->link_status |= LINK_12GTFD;
1613 break;
1614
1615 case GP_STATUS_12_5G:
1616 bp->line_speed = SPEED_12500;
1617 bp->link_status |= LINK_12_5GTFD;
1618 break;
1619
1620 case GP_STATUS_13G:
1621 bp->line_speed = SPEED_13000;
1622 bp->link_status |= LINK_13GTFD;
1623 break;
1624
1625 case GP_STATUS_15G:
1626 bp->line_speed = SPEED_15000;
1627 bp->link_status |= LINK_15GTFD;
1628 break;
1629
1630 case GP_STATUS_16G:
1631 bp->line_speed = SPEED_16000;
1632 bp->link_status |= LINK_16GTFD;
1633 break;
1634
1635 default:
1636 BNX2X_ERR("link speed unsupported gp_status 0x%x\n",
1637 gp_status);
1638 break;
1639 }
1640
1641 bp->link_status |= LINK_STATUS_SERDES_LINK;
1642
1643 if (bp->req_autoneg & AUTONEG_SPEED) {
1644 bp->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
1645
1646 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
1647 bp->link_status |=
1648 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
1649
1650 if (bp->autoneg & AUTONEG_PARALLEL)
1651 bp->link_status |=
1652 LINK_STATUS_PARALLEL_DETECTION_USED;
1653 }
1654
1655 if (bp->flow_ctrl & FLOW_CTRL_TX)
1656 bp->link_status |= LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
1657
1658 if (bp->flow_ctrl & FLOW_CTRL_RX)
1659 bp->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
1660
1661 } else { /* link_down */
1662 DP(NETIF_MSG_LINK, "link down\n");
1663
1664 bp->link_up = 0;
1665
1666 bp->line_speed = 0;
1667 bp->duplex = DUPLEX_FULL;
1668 bp->flow_ctrl = 0;
1669 }
1670
1671 DP(NETIF_MSG_LINK, "gp_status 0x%x link_up %d\n"
1672 DP_LEVEL " line_speed %d duplex %d flow_ctrl 0x%x"
1673 " link_status 0x%x\n",
1674 gp_status, bp->link_up, bp->line_speed, bp->duplex, bp->flow_ctrl,
1675 bp->link_status);
1676}
1677
1678static void bnx2x_link_int_ack(struct bnx2x *bp, int is_10g)
1679{
1680 int port = bp->port;
1681
1682 /* first reset all status
1683 * we asume only one line will be change at a time */
1684 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1685 (NIG_XGXS0_LINK_STATUS |
1686 NIG_SERDES0_LINK_STATUS |
1687 NIG_STATUS_INTERRUPT_XGXS0_LINK10G));
1688 if (bp->link_up) {
1689 if (is_10g) {
1690 /* Disable the 10G link interrupt
1691 * by writing 1 to the status register
1692 */
1693 DP(NETIF_MSG_LINK, "10G XGXS link up\n");
1694 bnx2x_bits_en(bp,
1695 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1696 NIG_STATUS_INTERRUPT_XGXS0_LINK10G);
1697
1698 } else if (bp->phy_flags & PHY_XGXS_FLAG) {
1699 /* Disable the link interrupt
1700 * by writing 1 to the relevant lane
1701 * in the status register
1702 */
1703 DP(NETIF_MSG_LINK, "1G XGXS link up\n");
1704 bnx2x_bits_en(bp,
1705 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1706 ((1 << bp->ser_lane) <<
1707 NIG_XGXS0_LINK_STATUS_SIZE));
1708
1709 } else { /* SerDes */
1710 DP(NETIF_MSG_LINK, "SerDes link up\n");
1711 /* Disable the link interrupt
1712 * by writing 1 to the status register
1713 */
1714 bnx2x_bits_en(bp,
1715 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1716 NIG_SERDES0_LINK_STATUS);
1717 }
1718
1719 } else { /* link_down */
1720 }
1721}
1722
1723static int bnx2x_ext_phy_is_link_up(struct bnx2x *bp)
1724{
1725 u32 ext_phy_type;
1726 u32 ext_phy_addr;
1727 u32 local_phy;
1728 u32 val = 0;
1729 u32 rx_sd, pcs_status;
1730
1731 if (bp->phy_flags & PHY_XGXS_FLAG) {
1732 local_phy = bp->phy_addr;
1733 ext_phy_addr = ((bp->ext_phy_config &
1734 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1735 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1736 bp->phy_addr = (u8)ext_phy_addr;
1737
1738 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
1739 switch (ext_phy_type) {
1740 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
1741 DP(NETIF_MSG_LINK, "XGXS Direct\n");
1742 val = 1;
1743 break;
1744
1745 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
1746 DP(NETIF_MSG_LINK, "XGXS 8705\n");
1747 bnx2x_mdio45_read(bp, EXT_PHY_OPT_WIS_DEVAD,
1748 EXT_PHY_OPT_LASI_STATUS, &val);
1749 DP(NETIF_MSG_LINK, "8705 LASI status is %d\n", val);
1750
1751 bnx2x_mdio45_read(bp, EXT_PHY_OPT_WIS_DEVAD,
1752 EXT_PHY_OPT_LASI_STATUS, &val);
1753 DP(NETIF_MSG_LINK, "8705 LASI status is %d\n", val);
1754
1755 bnx2x_mdio45_read(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
1756 EXT_PHY_OPT_PMD_RX_SD, &rx_sd);
1757 val = (rx_sd & 0x1);
1758 break;
1759
1760 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
1761 DP(NETIF_MSG_LINK, "XGXS 8706\n");
1762 bnx2x_mdio45_read(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
1763 EXT_PHY_OPT_LASI_STATUS, &val);
1764 DP(NETIF_MSG_LINK, "8706 LASI status is %d\n", val);
1765
1766 bnx2x_mdio45_read(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
1767 EXT_PHY_OPT_LASI_STATUS, &val);
1768 DP(NETIF_MSG_LINK, "8706 LASI status is %d\n", val);
1769
1770 bnx2x_mdio45_read(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
1771 EXT_PHY_OPT_PMD_RX_SD, &rx_sd);
1772 bnx2x_mdio45_read(bp, EXT_PHY_OPT_PCS_DEVAD,
1773 EXT_PHY_OPT_PCS_STATUS, &pcs_status);
1774 DP(NETIF_MSG_LINK, "8706 rx_sd 0x%x"
1775 " pcs_status 0x%x\n", rx_sd, pcs_status);
1776 /* link is up if both bit 0 of pmd_rx and
1777 * bit 0 of pcs_status are set
1778 */
1779 val = (rx_sd & pcs_status);
1780 break;
1781
1782 default:
1783 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
1784 bp->ext_phy_config);
1785 val = 0;
1786 break;
1787 }
1788 bp->phy_addr = local_phy;
1789
1790 } else { /* SerDes */
1791 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
1792 switch (ext_phy_type) {
1793 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
1794 DP(NETIF_MSG_LINK, "SerDes Direct\n");
1795 val = 1;
1796 break;
1797
1798 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
1799 DP(NETIF_MSG_LINK, "SerDes 5482\n");
1800 val = 1;
1801 break;
1802
1803 default:
1804 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
1805 bp->ext_phy_config);
1806 val = 0;
1807 break;
1808 }
1809 }
1810
1811 return val;
1812}
1813
1814static void bnx2x_bmac_enable(struct bnx2x *bp, int is_lb)
1815{
1816 int port = bp->port;
1817 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1818 NIG_REG_INGRESS_BMAC0_MEM;
1819 u32 wb_write[2];
1820 u32 val;
1821
1822 DP(NETIF_MSG_LINK, "enableing BigMAC\n");
1823 /* reset and unreset the BigMac */
1824 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1825 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1826 msleep(5);
1827 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1828 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1829
1830 /* enable access for bmac registers */
1831 NIG_WR(NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
1832
1833 /* XGXS control */
1834 wb_write[0] = 0x3c;
1835 wb_write[1] = 0;
1836 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
1837 wb_write, 2);
1838
1839 /* tx MAC SA */
1840 wb_write[0] = ((bp->dev->dev_addr[2] << 24) |
1841 (bp->dev->dev_addr[3] << 16) |
1842 (bp->dev->dev_addr[4] << 8) |
1843 bp->dev->dev_addr[5]);
1844 wb_write[1] = ((bp->dev->dev_addr[0] << 8) |
1845 bp->dev->dev_addr[1]);
1846 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
1847 wb_write, 2);
1848
1849 /* tx control */
1850 val = 0xc0;
1851 if (bp->flow_ctrl & FLOW_CTRL_TX)
1852 val |= 0x800000;
1853 wb_write[0] = val;
1854 wb_write[1] = 0;
1855 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_write, 2);
1856
1857 /* set tx mtu */
1858 wb_write[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; /* -CRC */
1859 wb_write[1] = 0;
1860 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_write, 2);
1861
1862 /* mac control */
1863 val = 0x3;
1864 if (is_lb) {
1865 val |= 0x4;
1866 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1867 }
1868 wb_write[0] = val;
1869 wb_write[1] = 0;
1870 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
1871 wb_write, 2);
1872
1873 /* rx control set to don't strip crc */
1874 val = 0x14;
1875 if (bp->flow_ctrl & FLOW_CTRL_RX)
1876 val |= 0x20;
1877 wb_write[0] = val;
1878 wb_write[1] = 0;
1879 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_write, 2);
1880
1881 /* set rx mtu */
1882 wb_write[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1883 wb_write[1] = 0;
1884 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_write, 2);
1885
1886 /* set cnt max size */
1887 wb_write[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; /* -VLAN */
1888 wb_write[1] = 0;
1889 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
1890 wb_write, 2);
1891
1892 /* configure safc */
1893 wb_write[0] = 0x1000200;
1894 wb_write[1] = 0;
1895 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
1896 wb_write, 2);
1897
1898 /* fix for emulation */
1899 if (CHIP_REV(bp) == CHIP_REV_EMUL) {
1900 wb_write[0] = 0xf000;
1901 wb_write[1] = 0;
1902 REG_WR_DMAE(bp,
1903 bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
1904 wb_write, 2);
1905 }
1906
1907 /* reset old bmac stats */
1908 memset(&bp->old_bmac, 0, sizeof(struct bmac_stats));
1909
1910 NIG_WR(NIG_REG_XCM0_OUT_EN + port*4, 0x0);
1911
1912 /* select XGXS */
1913 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
1914 NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
1915
1916 /* disable the NIG in/out to the emac */
1917 NIG_WR(NIG_REG_EMAC0_IN_EN + port*4, 0x0);
1918 NIG_WR(NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
1919 NIG_WR(NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
1920
1921 /* enable the NIG in/out to the bmac */
1922 NIG_WR(NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
1923
1924 NIG_WR(NIG_REG_BMAC0_IN_EN + port*4, 0x1);
1925 val = 0;
1926 if (bp->flow_ctrl & FLOW_CTRL_TX)
1927 val = 1;
1928 NIG_WR(NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
1929 NIG_WR(NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
1930
1931 bp->phy_flags |= PHY_BMAC_FLAG;
1932
1933 bp->stats_state = STATS_STATE_ENABLE;
1934}
1935
1936static void bnx2x_emac_enable(struct bnx2x *bp)
1937{
1938 int port = bp->port;
1939 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1940 u32 val;
1941 int timeout;
1942
1943 DP(NETIF_MSG_LINK, "enableing EMAC\n");
1944 /* reset and unreset the emac core */
1945 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1946 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1947 msleep(5);
1948 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1949 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1950
1951 /* enable emac and not bmac */
1952 NIG_WR(NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1953
1954 /* for paladium */
1955 if (CHIP_REV(bp) == CHIP_REV_EMUL) {
1956 /* Use lane 1 (of lanes 0-3) */
1957 NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
1958 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1959 }
1960 /* for fpga */
1961 else if (CHIP_REV(bp) == CHIP_REV_FPGA) {
1962 /* Use lane 1 (of lanes 0-3) */
1963 NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
1964 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1965 }
1966 /* ASIC */
1967 else {
1968 if (bp->phy_flags & PHY_XGXS_FLAG) {
1969 DP(NETIF_MSG_LINK, "XGXS\n");
1970 /* select the master lanes (out of 0-3) */
1971 NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4,
1972 bp->ser_lane);
1973 /* select XGXS */
1974 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1975
1976 } else { /* SerDes */
1977 DP(NETIF_MSG_LINK, "SerDes\n");
1978 /* select SerDes */
1979 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1980 }
1981 }
1982
1983 /* enable emac */
1984 NIG_WR(NIG_REG_NIG_EMAC0_EN + port*4, 1);
1985
1986 /* init emac - use read-modify-write */
1987 /* self clear reset */
1988 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1989 EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1990
1991 timeout = 200;
1992 while (val & EMAC_MODE_RESET) {
1993 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1994 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1995 if (!timeout) {
1996 BNX2X_ERR("EMAC timeout!\n");
1997 break;
1998 }
1999 timeout--;
2000 }
2001
2002 /* reset tx part */
2003 EMAC_WR(EMAC_REG_EMAC_TX_MODE, EMAC_TX_MODE_RESET);
2004
2005 timeout = 200;
2006 while (val & EMAC_TX_MODE_RESET) {
2007 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_TX_MODE);
2008 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
2009 if (!timeout) {
2010 BNX2X_ERR("EMAC timeout!\n");
2011 break;
2012 }
2013 timeout--;
2014 }
2015
2016 if (CHIP_REV_IS_SLOW(bp)) {
2017 /* config GMII mode */
2018 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
2019 EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
2020
2021 } else { /* ASIC */
2022 /* pause enable/disable */
2023 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
2024 EMAC_RX_MODE_FLOW_EN);
2025 if (bp->flow_ctrl & FLOW_CTRL_RX)
2026 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
2027 EMAC_RX_MODE_FLOW_EN);
2028
2029 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
2030 EMAC_TX_MODE_EXT_PAUSE_EN);
2031 if (bp->flow_ctrl & FLOW_CTRL_TX)
2032 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
2033 EMAC_TX_MODE_EXT_PAUSE_EN);
2034 }
2035
2036 /* KEEP_VLAN_TAG, promiscous */
2037 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
2038 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
2039 EMAC_WR(EMAC_REG_EMAC_RX_MODE, val);
2040
2041 /* identify magic packets */
2042 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
2043 EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_MPKT));
2044
2045 /* enable emac for jumbo packets */
2046 EMAC_WR(EMAC_REG_EMAC_RX_MTU_SIZE,
2047 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
2048 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); /* -VLAN */
2049
2050 /* strip CRC */
2051 NIG_WR(NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
2052
2053 val = ((bp->dev->dev_addr[0] << 8) |
2054 bp->dev->dev_addr[1]);
2055 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH, val);
2056
2057 val = ((bp->dev->dev_addr[2] << 24) |
2058 (bp->dev->dev_addr[3] << 16) |
2059 (bp->dev->dev_addr[4] << 8) |
2060 bp->dev->dev_addr[5]);
2061 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + 4, val);
2062
2063 /* disable the NIG in/out to the bmac */
2064 NIG_WR(NIG_REG_BMAC0_IN_EN + port*4, 0x0);
2065 NIG_WR(NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
2066 NIG_WR(NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
2067
2068 /* enable the NIG in/out to the emac */
2069 NIG_WR(NIG_REG_EMAC0_IN_EN + port*4, 0x1);
2070 val = 0;
2071 if (bp->flow_ctrl & FLOW_CTRL_TX)
2072 val = 1;
2073 NIG_WR(NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
2074 NIG_WR(NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
2075
2076 if (CHIP_REV(bp) == CHIP_REV_FPGA) {
2077 /* take the BigMac out of reset */
2078 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2079 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2080
2081 /* enable access for bmac registers */
2082 NIG_WR(NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2083 }
2084
2085 bp->phy_flags |= PHY_EMAC_FLAG;
2086
2087 bp->stats_state = STATS_STATE_ENABLE;
2088}
2089
2090static void bnx2x_emac_program(struct bnx2x *bp)
2091{
2092 u16 mode = 0;
2093 int port = bp->port;
2094
2095 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2096 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2097 (EMAC_MODE_25G_MODE |
2098 EMAC_MODE_PORT_MII_10M |
2099 EMAC_MODE_HALF_DUPLEX));
2100 switch (bp->line_speed) {
2101 case SPEED_10:
2102 mode |= EMAC_MODE_PORT_MII_10M;
2103 break;
2104
2105 case SPEED_100:
2106 mode |= EMAC_MODE_PORT_MII;
2107 break;
2108
2109 case SPEED_1000:
2110 mode |= EMAC_MODE_PORT_GMII;
2111 break;
2112
2113 case SPEED_2500:
2114 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
2115 break;
2116
2117 default:
2118 /* 10G not valid for EMAC */
2119 BNX2X_ERR("Invalid line_speed 0x%x\n", bp->line_speed);
2120 break;
2121 }
2122
2123 if (bp->duplex == DUPLEX_HALF)
2124 mode |= EMAC_MODE_HALF_DUPLEX;
2125 bnx2x_bits_en(bp, GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2126 mode);
2127
2128 bnx2x_leds_set(bp, bp->line_speed);
2129}
2130
2131static void bnx2x_set_sgmii_tx_driver(struct bnx2x *bp)
2132{
2133 u32 lp_up2;
2134 u32 tx_driver;
2135
2136 /* read precomp */
2137 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_OVER_1G);
2138 bnx2x_mdio22_read(bp, MDIO_OVER_1G_LP_UP2, &lp_up2);
2139
2140 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_TX0);
2141 bnx2x_mdio22_read(bp, MDIO_TX0_TX_DRIVER, &tx_driver);
2142
2143 /* bits [10:7] at lp_up2, positioned at [15:12] */
2144 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
2145 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
2146 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
2147
2148 if ((lp_up2 != 0) &&
2149 (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK))) {
2150 /* replace tx_driver bits [15:12] */
2151 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2152 tx_driver |= lp_up2;
2153 bnx2x_mdio22_write(bp, MDIO_TX0_TX_DRIVER, tx_driver);
2154 }
2155}
2156
2157static void bnx2x_pbf_update(struct bnx2x *bp)
2158{
2159 int port = bp->port;
2160 u32 init_crd, crd;
2161 u32 count = 1000;
2162 u32 pause = 0;
2163
2164
2165 /* disable port */
2166 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2167
2168 /* wait for init credit */
2169 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2170 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2171 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2172
2173 while ((init_crd != crd) && count) {
2174 msleep(5);
2175
2176 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2177 count--;
2178 }
2179 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2180 if (init_crd != crd)
2181 BNX2X_ERR("BUG! init_crd 0x%x != crd 0x%x\n", init_crd, crd);
2182
2183 if (bp->flow_ctrl & FLOW_CTRL_RX)
2184 pause = 1;
2185 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, pause);
2186 if (pause) {
2187 /* update threshold */
2188 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2189 /* update init credit */
2190 init_crd = 778; /* (800-18-4) */
2191
2192 } else {
2193 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)/16;
2194
2195 /* update threshold */
2196 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2197 /* update init credit */
2198 switch (bp->line_speed) {
2199 case SPEED_10:
2200 case SPEED_100:
2201 case SPEED_1000:
2202 init_crd = thresh + 55 - 22;
2203 break;
2204
2205 case SPEED_2500:
2206 init_crd = thresh + 138 - 22;
2207 break;
2208
2209 case SPEED_10000:
2210 init_crd = thresh + 553 - 22;
2211 break;
2212
2213 default:
2214 BNX2X_ERR("Invalid line_speed 0x%x\n",
2215 bp->line_speed);
2216 break;
2217 }
2218 }
2219 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2220 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2221 bp->line_speed, init_crd);
2222
2223 /* probe the credit changes */
2224 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2225 msleep(5);
2226 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2227
2228 /* enable port */
2229 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2230}
2231
2232static void bnx2x_update_mng(struct bnx2x *bp)
2233{
2234 if (!nomcp)
2235 SHMEM_WR(bp, drv_fw_mb[bp->port].link_status,
2236 bp->link_status);
2237}
2238
2239static void bnx2x_link_report(struct bnx2x *bp)
2240{
2241 if (bp->link_up) {
2242 netif_carrier_on(bp->dev);
2243 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
2244
2245 printk("%d Mbps ", bp->line_speed);
2246
2247 if (bp->duplex == DUPLEX_FULL)
2248 printk("full duplex");
2249 else
2250 printk("half duplex");
2251
2252 if (bp->flow_ctrl) {
2253 if (bp->flow_ctrl & FLOW_CTRL_RX) {
2254 printk(", receive ");
2255 if (bp->flow_ctrl & FLOW_CTRL_TX)
2256 printk("& transmit ");
2257 } else {
2258 printk(", transmit ");
2259 }
2260 printk("flow control ON");
2261 }
2262 printk("\n");
2263
2264 } else { /* link_down */
2265 netif_carrier_off(bp->dev);
2266 printk(KERN_INFO PFX "%s NIC Link is Down\n", bp->dev->name);
2267 }
2268}
2269
2270static void bnx2x_link_up(struct bnx2x *bp)
2271{
2272 int port = bp->port;
2273
2274 /* PBF - link up */
2275 bnx2x_pbf_update(bp);
2276
2277 /* disable drain */
2278 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
2279
2280 /* update shared memory */
2281 bnx2x_update_mng(bp);
2282
2283 /* indicate link up */
2284 bnx2x_link_report(bp);
2285}
2286
2287static void bnx2x_link_down(struct bnx2x *bp)
2288{
2289 int port = bp->port;
2290
2291 /* notify stats */
2292 if (bp->stats_state != STATS_STATE_DISABLE) {
2293 bp->stats_state = STATS_STATE_STOP;
2294 DP(BNX2X_MSG_STATS, "stats_state - STOP\n");
2295 }
2296
2297 /* indicate link down */
2298 bp->phy_flags &= ~(PHY_BMAC_FLAG | PHY_EMAC_FLAG);
2299
2300 /* reset BigMac */
2301 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2302 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2303
2304 /* ignore drain flag interrupt */
2305 /* activate nig drain */
2306 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
2307
2308 /* update shared memory */
2309 bnx2x_update_mng(bp);
2310
2311 /* indicate link down */
2312 bnx2x_link_report(bp);
2313}
2314
2315static void bnx2x_init_mac_stats(struct bnx2x *bp);
2316
2317/* This function is called upon link interrupt */
2318static void bnx2x_link_update(struct bnx2x *bp)
2319{
2320 u32 gp_status;
2321 int port = bp->port;
2322 int i;
2323 int link_10g;
2324
2325 DP(NETIF_MSG_LINK, "port %x, is xgxs %x, stat_mask 0x%x,"
2326 " int_mask 0x%x, saved_mask 0x%x, MI_INT %x, SERDES_LINK %x,"
2327 " 10G %x, XGXS_LINK %x\n", port, (bp->phy_flags & PHY_XGXS_FLAG),
2328 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4),
2329 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), bp->nig_mask,
2330 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
2331 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c),
2332 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
2333 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)
2334 );
2335
2336 might_sleep();
2337 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_GP_STATUS);
2338 /* avoid fast toggling */
2339 for (i = 0 ; i < 10 ; i++) {
2340 msleep(10);
2341 bnx2x_mdio22_read(bp, MDIO_GP_STATUS_TOP_AN_STATUS1,
2342 &gp_status);
2343 }
2344
2345 bnx2x_link_settings_status(bp, gp_status);
2346
2347 /* anything 10 and over uses the bmac */
2348 link_10g = ((bp->line_speed >= SPEED_10000) &&
2349 (bp->line_speed <= SPEED_16000));
2350
2351 bnx2x_link_int_ack(bp, link_10g);
2352
2353 /* link is up only if both local phy and external phy are up */
2354 if (bp->link_up && bnx2x_ext_phy_is_link_up(bp)) {
2355 if (link_10g) {
2356 bnx2x_bmac_enable(bp, 0);
2357 bnx2x_leds_set(bp, SPEED_10000);
2358
2359 } else {
2360 bnx2x_emac_enable(bp);
2361 bnx2x_emac_program(bp);
2362
2363 /* AN complete? */
2364 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
2365 if (!(bp->phy_flags & PHY_SGMII_FLAG))
2366 bnx2x_set_sgmii_tx_driver(bp);
2367 }
2368 }
2369 bnx2x_link_up(bp);
2370
2371 } else { /* link down */
2372 bnx2x_leds_unset(bp);
2373 bnx2x_link_down(bp);
2374 }
2375
2376 bnx2x_init_mac_stats(bp);
2377}
2378
2379/*
2380 * Init service functions
2381 */
2382
2383static void bnx2x_set_aer_mmd(struct bnx2x *bp)
2384{
2385 u16 offset = (bp->phy_flags & PHY_XGXS_FLAG) ?
2386 (bp->phy_addr + bp->ser_lane) : 0;
2387
2388 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_AER_BLOCK);
2389 bnx2x_mdio22_write(bp, MDIO_AER_BLOCK_AER_REG, 0x3800 + offset);
2390}
2391
2392static void bnx2x_set_master_ln(struct bnx2x *bp)
2393{
2394 u32 new_master_ln;
2395
2396 /* set the master_ln for AN */
2397 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_XGXS_BLOCK2);
2398 bnx2x_mdio22_read(bp, MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
2399 &new_master_ln);
2400 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
2401 (new_master_ln | bp->ser_lane));
2402}
2403
2404static void bnx2x_reset_unicore(struct bnx2x *bp)
2405{
2406 u32 mii_control;
2407 int i;
2408
2409 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2410 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
2411 /* reset the unicore */
2412 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
2413 (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_RESET));
2414
2415 /* wait for the reset to self clear */
2416 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
2417 udelay(5);
2418
2419 /* the reset erased the previous bank value */
2420 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2421 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
2422 &mii_control);
2423
2424 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
2425 udelay(5);
2426 return;
2427 }
2428 }
2429
2430 BNX2X_ERR("BUG! unicore is still in reset!\n");
2431}
2432
2433static void bnx2x_set_swap_lanes(struct bnx2x *bp)
2434{
2435 /* Each two bits represents a lane number:
2436 No swap is 0123 => 0x1b no need to enable the swap */
2437
2438 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_XGXS_BLOCK2);
2439 if (bp->rx_lane_swap != 0x1b) {
2440 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_RX_LN_SWAP,
2441 (bp->rx_lane_swap |
2442 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
2443 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
2444 } else {
2445 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
2446 }
2447
2448 if (bp->tx_lane_swap != 0x1b) {
2449 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_TX_LN_SWAP,
2450 (bp->tx_lane_swap |
2451 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
2452 } else {
2453 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
2454 }
2455}
2456
2457static void bnx2x_set_parallel_detection(struct bnx2x *bp)
2458{
2459 u32 control2;
2460
2461 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
2462 bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
2463 &control2);
2464
2465 if (bp->autoneg & AUTONEG_PARALLEL) {
2466 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
2467 } else {
2468 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
2469 }
2470 bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
2471 control2);
2472
2473 if (bp->phy_flags & PHY_XGXS_FLAG) {
2474 DP(NETIF_MSG_LINK, "XGXS\n");
2475 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_10G_PARALLEL_DETECT);
2476
2477 bnx2x_mdio22_write(bp,
2478 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
2479 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
2480
2481 bnx2x_mdio22_read(bp,
2482 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
2483 &control2);
2484
2485 if (bp->autoneg & AUTONEG_PARALLEL) {
2486 control2 |=
2487 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
2488 } else {
2489 control2 &=
2490 ~MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
2491 }
2492 bnx2x_mdio22_write(bp,
2493 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
2494 control2);
2495 }
2496}
2497
2498static void bnx2x_set_autoneg(struct bnx2x *bp)
2499{
2500 u32 reg_val;
2501
2502 /* CL37 Autoneg */
2503 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2504 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2505 if ((bp->req_autoneg & AUTONEG_SPEED) &&
2506 (bp->autoneg & AUTONEG_CL37)) {
2507 /* CL37 Autoneg Enabled */
2508 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
2509 } else {
2510 /* CL37 Autoneg Disabled */
2511 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2512 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
2513 }
2514 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2515
2516 /* Enable/Disable Autodetection */
2517 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
2518 bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
2519 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN;
2520
2521 if ((bp->req_autoneg & AUTONEG_SPEED) &&
2522 (bp->autoneg & AUTONEG_SGMII_FIBER_AUTODET)) {
2523 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
2524 } else {
2525 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
2526 }
2527 bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
2528
2529 /* Enable TetonII and BAM autoneg */
2530 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_BAM_NEXT_PAGE);
2531 bnx2x_mdio22_read(bp, MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
2532 &reg_val);
2533 if ((bp->req_autoneg & AUTONEG_SPEED) &&
2534 (bp->autoneg & AUTONEG_CL37) && (bp->autoneg & AUTONEG_BAM)) {
2535 /* Enable BAM aneg Mode and TetonII aneg Mode */
2536 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
2537 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
2538 } else {
2539 /* TetonII and BAM Autoneg Disabled */
2540 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
2541 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
2542 }
2543 bnx2x_mdio22_write(bp, MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
2544 reg_val);
2545
2546 /* Enable Clause 73 Aneg */
2547 if ((bp->req_autoneg & AUTONEG_SPEED) &&
2548 (bp->autoneg & AUTONEG_CL73)) {
2549 /* Enable BAM Station Manager */
2550 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_USERB0);
2551 bnx2x_mdio22_write(bp, MDIO_CL73_USERB0_CL73_BAM_CTRL1,
2552 (MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
2553 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
2554 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN));
2555
2556 /* Merge CL73 and CL37 aneg resolution */
2557 bnx2x_mdio22_read(bp, MDIO_CL73_USERB0_CL73_BAM_CTRL3,
2558 &reg_val);
2559 bnx2x_mdio22_write(bp, MDIO_CL73_USERB0_CL73_BAM_CTRL3,
2560 (reg_val |
2561 MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR));
2562
2563 /* Set the CL73 AN speed */
2564 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB1);
2565 bnx2x_mdio22_read(bp, MDIO_CL73_IEEEB1_AN_ADV2, &reg_val);
2566 /* In the SerDes we support only the 1G.
2567 In the XGXS we support the 10G KX4
2568 but we currently do not support the KR */
2569 if (bp->phy_flags & PHY_XGXS_FLAG) {
2570 DP(NETIF_MSG_LINK, "XGXS\n");
2571 /* 10G KX4 */
2572 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
2573 } else {
2574 DP(NETIF_MSG_LINK, "SerDes\n");
2575 /* 1000M KX */
2576 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
2577 }
2578 bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB1_AN_ADV2, reg_val);
2579
2580 /* CL73 Autoneg Enabled */
2581 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
2582 } else {
2583 /* CL73 Autoneg Disabled */
2584 reg_val = 0;
2585 }
2586 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB0);
2587 bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
2588}
2589
2590/* program SerDes, forced speed */
2591static void bnx2x_program_serdes(struct bnx2x *bp)
2592{
2593 u32 reg_val;
2594
2595 /* program duplex, disable autoneg */
2596 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2597 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2598 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
2599 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN);
2600 if (bp->req_duplex == DUPLEX_FULL)
2601 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2602 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2603
2604 /* program speed
2605 - needed only if the speed is greater than 1G (2.5G or 10G) */
2606 if (bp->req_line_speed > SPEED_1000) {
2607 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
2608 bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_MISC1, &reg_val);
2609 /* clearing the speed value before setting the right speed */
2610 reg_val &= ~MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK;
2611 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
2612 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2613 if (bp->req_line_speed == SPEED_10000)
2614 reg_val |=
2615 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
2616 bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_MISC1, reg_val);
2617 }
2618}
2619
2620static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x *bp)
2621{
2622 u32 val = 0;
2623
2624 /* configure the 48 bits for BAM AN */
2625 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_OVER_1G);
2626
2627 /* set extended capabilities */
2628 if (bp->advertising & ADVERTISED_2500baseT_Full)
2629 val |= MDIO_OVER_1G_UP1_2_5G;
2630 if (bp->advertising & ADVERTISED_10000baseT_Full)
2631 val |= MDIO_OVER_1G_UP1_10G;
2632 bnx2x_mdio22_write(bp, MDIO_OVER_1G_UP1, val);
2633
2634 bnx2x_mdio22_write(bp, MDIO_OVER_1G_UP3, 0);
2635}
2636
2637static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x *bp)
2638{
2639 u32 an_adv;
2640
2641 /* for AN, we are always publishing full duplex */
2642 an_adv = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
2643
2644 /* set pause */
2645 switch (bp->pause_mode) {
2646 case PAUSE_SYMMETRIC:
2647 an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
2648 break;
2649 case PAUSE_ASYMMETRIC:
2650 an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2651 break;
2652 case PAUSE_BOTH:
2653 an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2654 break;
2655 case PAUSE_NONE:
2656 an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
2657 break;
2658 }
2659
2660 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2661 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_AUTO_NEG_ADV, an_adv);
2662}
2663
2664static void bnx2x_restart_autoneg(struct bnx2x *bp)
2665{
2666 if (bp->autoneg & AUTONEG_CL73) {
2667 /* enable and restart clause 73 aneg */
2668 u32 an_ctrl;
2669
2670 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB0);
2671 bnx2x_mdio22_read(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2672 &an_ctrl);
2673 bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2674 (an_ctrl |
2675 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
2676 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
2677
2678 } else {
2679 /* Enable and restart BAM/CL37 aneg */
2680 u32 mii_control;
2681
2682 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2683 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
2684 &mii_control);
2685 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
2686 (mii_control |
2687 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2688 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
2689 }
2690}
2691
2692static void bnx2x_initialize_sgmii_process(struct bnx2x *bp)
2693{
2694 u32 control1;
2695
2696 /* in SGMII mode, the unicore is always slave */
2697 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
2698 bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2699 &control1);
2700 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
2701 /* set sgmii mode (and not fiber) */
2702 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
2703 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
2704 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
2705 bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2706 control1);
2707
2708 /* if forced speed */
2709 if (!(bp->req_autoneg & AUTONEG_SPEED)) {
2710 /* set speed, disable autoneg */
2711 u32 mii_control;
2712
2713 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2714 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
2715 &mii_control);
2716 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2717 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK |
2718 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
2719
2720 switch (bp->req_line_speed) {
2721 case SPEED_100:
2722 mii_control |=
2723 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
2724 break;
2725 case SPEED_1000:
2726 mii_control |=
2727 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
2728 break;
2729 case SPEED_10:
2730 /* there is nothing to set for 10M */
2731 break;
2732 default:
2733 /* invalid speed for SGMII */
2734 DP(NETIF_MSG_LINK, "Invalid req_line_speed 0x%x\n",
2735 bp->req_line_speed);
2736 break;
2737 }
2738
2739 /* setting the full duplex */
2740 if (bp->req_duplex == DUPLEX_FULL)
2741 mii_control |=
2742 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2743 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
2744 mii_control);
2745
2746 } else { /* AN mode */
2747 /* enable and restart AN */
2748 bnx2x_restart_autoneg(bp);
2749 }
2750}
2751
2752static void bnx2x_link_int_enable(struct bnx2x *bp)
2753{
2754 int port = bp->port;
2755
2756 /* setting the status to report on link up
2757 for either XGXS or SerDes */
2758 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2759 (NIG_XGXS0_LINK_STATUS |
2760 NIG_STATUS_INTERRUPT_XGXS0_LINK10G |
2761 NIG_SERDES0_LINK_STATUS));
2762
2763 if (bp->phy_flags & PHY_XGXS_FLAG) {
2764 /* TBD -
2765 * in force mode (not AN) we can enable just the relevant
2766 * interrupt
2767 * Even in AN we might enable only one according to the AN
2768 * speed mask
2769 */
2770 bnx2x_bits_en(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2771 (NIG_MASK_XGXS0_LINK_STATUS |
2772 NIG_MASK_XGXS0_LINK10G));
2773 DP(NETIF_MSG_LINK, "enable XGXS interrupt\n");
2774
2775 } else { /* SerDes */
2776 bnx2x_bits_en(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2777 NIG_MASK_SERDES0_LINK_STATUS);
2778 DP(NETIF_MSG_LINK, "enable SerDes interrupt\n");
2779 }
2780}
2781
2782static void bnx2x_ext_phy_init(struct bnx2x *bp)
2783{
2784 int port = bp->port;
2785 u32 ext_phy_type;
2786 u32 ext_phy_addr;
2787 u32 local_phy;
2788
2789 if (bp->phy_flags & PHY_XGXS_FLAG) {
2790 local_phy = bp->phy_addr;
2791 ext_phy_addr = ((bp->ext_phy_config &
2792 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2793 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2794
2795 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
2796 switch (ext_phy_type) {
2797 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
2798 DP(NETIF_MSG_LINK, "XGXS Direct\n");
2799 break;
2800
2801 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
2802 DP(NETIF_MSG_LINK, "XGXS 8705\n");
2803 bnx2x_bits_en(bp,
2804 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2805 NIG_MASK_MI_INT);
2806 DP(NETIF_MSG_LINK, "enabled extenal phy int\n");
2807
2808 bp->phy_addr = ext_phy_type;
2809 bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
2810 EXT_PHY_OPT_PMD_MISC_CNTL,
2811 0x8288);
2812 bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
2813 EXT_PHY_OPT_PHY_IDENTIFIER,
2814 0x7fbf);
2815 bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
2816 EXT_PHY_OPT_CMU_PLL_BYPASS,
2817 0x0100);
2818 bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_WIS_DEVAD,
2819 EXT_PHY_OPT_LASI_CNTL, 0x1);
2820 break;
2821
2822 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
2823 DP(NETIF_MSG_LINK, "XGXS 8706\n");
2824 bnx2x_bits_en(bp,
2825 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2826 NIG_MASK_MI_INT);
2827 DP(NETIF_MSG_LINK, "enabled extenal phy int\n");
2828
2829 bp->phy_addr = ext_phy_type;
2830 bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
2831 EXT_PHY_OPT_PMD_DIGITAL_CNT,
2832 0x400);
2833 bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
2834 EXT_PHY_OPT_LASI_CNTL, 0x1);
2835 break;
2836
2837 default:
2838 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
2839 bp->ext_phy_config);
2840 break;
2841 }
2842 bp->phy_addr = local_phy;
2843
2844 } else { /* SerDes */
2845/* ext_phy_addr = ((bp->ext_phy_config &
2846 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK) >>
2847 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT);
2848*/
2849 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
2850 switch (ext_phy_type) {
2851 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
2852 DP(NETIF_MSG_LINK, "SerDes Direct\n");
2853 break;
2854
2855 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
2856 DP(NETIF_MSG_LINK, "SerDes 5482\n");
2857 bnx2x_bits_en(bp,
2858 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2859 NIG_MASK_MI_INT);
2860 DP(NETIF_MSG_LINK, "enabled extenal phy int\n");
2861 break;
2862
2863 default:
2864 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
2865 bp->ext_phy_config);
2866 break;
2867 }
2868 }
2869}
2870
2871static void bnx2x_ext_phy_reset(struct bnx2x *bp)
2872{
2873 u32 ext_phy_type;
2874 u32 ext_phy_addr;
2875 u32 local_phy;
2876
2877 if (bp->phy_flags & PHY_XGXS_FLAG) {
2878 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
2879 switch (ext_phy_type) {
2880 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
2881 DP(NETIF_MSG_LINK, "XGXS Direct\n");
2882 break;
2883
2884 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
2885 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
2886 DP(NETIF_MSG_LINK, "XGXS 8705/6\n");
2887 local_phy = bp->phy_addr;
2888 ext_phy_addr = ((bp->ext_phy_config &
2889 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2890 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2891 bp->phy_addr = (u8)ext_phy_addr;
2892 bnx2x_mdio45_write(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
2893 EXT_PHY_OPT_CNTL, 0xa040);
2894 bp->phy_addr = local_phy;
2895 break;
2896
2897 default:
2898 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
2899 bp->ext_phy_config);
2900 break;
2901 }
2902
2903 } else { /* SerDes */
2904 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
2905 switch (ext_phy_type) {
2906 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
2907 DP(NETIF_MSG_LINK, "SerDes Direct\n");
2908 break;
2909
2910 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
2911 DP(NETIF_MSG_LINK, "SerDes 5482\n");
2912 break;
2913
2914 default:
2915 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
2916 bp->ext_phy_config);
2917 break;
2918 }
2919 }
2920}
2921
2922static void bnx2x_link_initialize(struct bnx2x *bp)
2923{
2924 int port = bp->port;
2925
2926 /* disable attentions */
2927 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2928 (NIG_MASK_XGXS0_LINK_STATUS |
2929 NIG_MASK_XGXS0_LINK10G |
2930 NIG_MASK_SERDES0_LINK_STATUS |
2931 NIG_MASK_MI_INT));
2932
2933 bnx2x_ext_phy_reset(bp);
2934
2935 bnx2x_set_aer_mmd(bp);
2936
2937 if (bp->phy_flags & PHY_XGXS_FLAG)
2938 bnx2x_set_master_ln(bp);
2939
2940 /* reset the SerDes and wait for reset bit return low */
2941 bnx2x_reset_unicore(bp);
2942
2943 bnx2x_set_aer_mmd(bp);
2944
2945 /* setting the masterLn_def again after the reset */
2946 if (bp->phy_flags & PHY_XGXS_FLAG) {
2947 bnx2x_set_master_ln(bp);
2948 bnx2x_set_swap_lanes(bp);
2949 }
2950
2951 /* Set Parallel Detect */
2952 if (bp->req_autoneg & AUTONEG_SPEED)
2953 bnx2x_set_parallel_detection(bp);
2954
2955 if (bp->phy_flags & PHY_XGXS_FLAG) {
2956 if (bp->req_line_speed &&
2957 bp->req_line_speed < SPEED_1000) {
2958 bp->phy_flags |= PHY_SGMII_FLAG;
2959 } else {
2960 bp->phy_flags &= ~PHY_SGMII_FLAG;
2961 }
2962 }
2963
2964 if (!(bp->phy_flags & PHY_SGMII_FLAG)) {
2965 u16 bank, rx_eq;
2966
2967 rx_eq = ((bp->serdes_config &
2968 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK) >>
2969 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT);
2970
2971 DP(NETIF_MSG_LINK, "setting rx eq to %d\n", rx_eq);
2972 for (bank = MDIO_REG_BANK_RX0; bank <= MDIO_REG_BANK_RX_ALL;
2973 bank += (MDIO_REG_BANK_RX1 - MDIO_REG_BANK_RX0)) {
2974 MDIO_SET_REG_BANK(bp, bank);
2975 bnx2x_mdio22_write(bp, MDIO_RX0_RX_EQ_BOOST,
2976 ((rx_eq &
2977 MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK) |
2978 MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL));
2979 }
2980
2981 /* forced speed requested? */
2982 if (!(bp->req_autoneg & AUTONEG_SPEED)) {
2983 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
2984
2985 /* disable autoneg */
2986 bnx2x_set_autoneg(bp);
2987
2988 /* program speed and duplex */
2989 bnx2x_program_serdes(bp);
2990
2991 } else { /* AN_mode */
2992 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
2993
2994 /* AN enabled */
2995 bnx2x_set_brcm_cl37_advertisment(bp);
2996
2997 /* program duplex & pause advertisment (for aneg) */
2998 bnx2x_set_ieee_aneg_advertisment(bp);
2999
3000 /* enable autoneg */
3001 bnx2x_set_autoneg(bp);
3002
3003 /* enalbe and restart AN */
3004 bnx2x_restart_autoneg(bp);
3005 }
3006
3007 } else { /* SGMII mode */
3008 DP(NETIF_MSG_LINK, "SGMII\n");
3009
3010 bnx2x_initialize_sgmii_process(bp);
3011 }
3012
3013 /* enable the interrupt */
3014 bnx2x_link_int_enable(bp);
3015
3016 /* init ext phy and enable link state int */
3017 bnx2x_ext_phy_init(bp);
3018}
3019
3020static void bnx2x_phy_deassert(struct bnx2x *bp)
3021{
3022 int port = bp->port;
3023 u32 val;
3024
3025 if (bp->phy_flags & PHY_XGXS_FLAG) {
3026 DP(NETIF_MSG_LINK, "XGXS\n");
3027 val = XGXS_RESET_BITS;
3028
3029 } else { /* SerDes */
3030 DP(NETIF_MSG_LINK, "SerDes\n");
3031 val = SERDES_RESET_BITS;
3032 }
3033
3034 val = val << (port*16);
3035
3036 /* reset and unreset the SerDes/XGXS */
3037 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3038 msleep(5);
3039 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3040}
3041
3042static int bnx2x_phy_init(struct bnx2x *bp)
3043{
3044 DP(NETIF_MSG_LINK, "started\n");
3045 if (CHIP_REV(bp) == CHIP_REV_FPGA) {
3046 bp->phy_flags |= PHY_EMAC_FLAG;
3047 bp->link_up = 1;
3048 bp->line_speed = SPEED_10000;
3049 bp->duplex = DUPLEX_FULL;
3050 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + bp->port*4, 0);
3051 bnx2x_emac_enable(bp);
3052 bnx2x_link_report(bp);
3053 return 0;
3054
3055 } else if (CHIP_REV(bp) == CHIP_REV_EMUL) {
3056 bp->phy_flags |= PHY_BMAC_FLAG;
3057 bp->link_up = 1;
3058 bp->line_speed = SPEED_10000;
3059 bp->duplex = DUPLEX_FULL;
3060 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + bp->port*4, 0);
3061 bnx2x_bmac_enable(bp, 0);
3062 bnx2x_link_report(bp);
3063 return 0;
3064
3065 } else {
3066 bnx2x_phy_deassert(bp);
3067 bnx2x_link_initialize(bp);
3068 }
3069
3070 return 0;
3071}
3072
3073static void bnx2x_link_reset(struct bnx2x *bp)
3074{
3075 int port = bp->port;
3076
3077 /* disable attentions */
3078 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
3079 (NIG_MASK_XGXS0_LINK_STATUS |
3080 NIG_MASK_XGXS0_LINK10G |
3081 NIG_MASK_SERDES0_LINK_STATUS |
3082 NIG_MASK_MI_INT));
3083
3084 bnx2x_ext_phy_reset(bp);
3085
3086 /* reset the SerDes/XGXS */
3087 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
3088 (0x1ff << (port*16)));
3089
3090 /* reset EMAC / BMAC and disable NIG interfaces */
3091 NIG_WR(NIG_REG_BMAC0_IN_EN + port*4, 0);
3092 NIG_WR(NIG_REG_BMAC0_OUT_EN + port*4, 0);
3093
3094 NIG_WR(NIG_REG_NIG_EMAC0_EN + port*4, 0);
3095 NIG_WR(NIG_REG_EMAC0_IN_EN + port*4, 0);
3096 NIG_WR(NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
3097
3098 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
3099}
3100
3101#ifdef BNX2X_XGXS_LB
3102static void bnx2x_set_xgxs_loopback(struct bnx2x *bp, int is_10g)
3103{
3104 int port = bp->port;
3105
3106 if (is_10g) {
3107 u32 md_devad;
3108
3109 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
3110
3111 /* change the uni_phy_addr in the nig */
3112 REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18),
3113 &md_devad);
3114 NIG_WR(NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
3115
3116 /* change the aer mmd */
3117 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_AER_BLOCK);
3118 bnx2x_mdio22_write(bp, MDIO_AER_BLOCK_AER_REG, 0x2800);
3119
3120 /* config combo IEEE0 control reg for loopback */
3121 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB0);
3122 bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
3123 0x6041);
3124
3125 /* set aer mmd back */
3126 bnx2x_set_aer_mmd(bp);
3127
3128 /* and md_devad */
3129 NIG_WR(NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, md_devad);
3130
3131 } else {
3132 u32 mii_control;
3133
3134 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
3135
3136 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
3137 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3138 &mii_control);
3139 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3140 (mii_control |
3141 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK));
3142 }
3143}
3144#endif
3145
3146/* end of PHY/MAC */
3147
3148/* slow path */
3149
3150/*
3151 * General service functions
3152 */
3153
3154/* the slow path queue is odd since completions arrive on the fastpath ring */
3155static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3156 u32 data_hi, u32 data_lo, int common)
3157{
3158 int port = bp->port;
3159
3160 DP(NETIF_MSG_TIMER,
3161 "spe (%x:%x) command %x hw_cid %x data (%x:%x) left %x\n",
3162 (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) +
3163 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
3164 HW_CID(bp, cid), data_hi, data_lo, bp->spq_left);
3165
3166#ifdef BNX2X_STOP_ON_ERROR
3167 if (unlikely(bp->panic))
3168 return -EIO;
3169#endif
3170
3171 spin_lock(&bp->spq_lock);
3172
3173 if (!bp->spq_left) {
3174 BNX2X_ERR("BUG! SPQ ring full!\n");
3175 spin_unlock(&bp->spq_lock);
3176 bnx2x_panic();
3177 return -EBUSY;
3178 }
3179 /* CID needs port number to be encoded int it */
3180 bp->spq_prod_bd->hdr.conn_and_cmd_data =
3181 cpu_to_le32(((command << SPE_HDR_CMD_ID_SHIFT) |
3182 HW_CID(bp, cid)));
3183 bp->spq_prod_bd->hdr.type = cpu_to_le16(ETH_CONNECTION_TYPE);
3184 if (common)
3185 bp->spq_prod_bd->hdr.type |=
3186 cpu_to_le16((1 << SPE_HDR_COMMON_RAMROD_SHIFT));
3187
3188 bp->spq_prod_bd->data.mac_config_addr.hi = cpu_to_le32(data_hi);
3189 bp->spq_prod_bd->data.mac_config_addr.lo = cpu_to_le32(data_lo);
3190
3191 bp->spq_left--;
3192
3193 if (bp->spq_prod_bd == bp->spq_last_bd) {
3194 bp->spq_prod_bd = bp->spq;
3195 bp->spq_prod_idx = 0;
3196 DP(NETIF_MSG_TIMER, "end of spq\n");
3197
3198 } else {
3199 bp->spq_prod_bd++;
3200 bp->spq_prod_idx++;
3201 }
3202
3203 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(port),
3204 bp->spq_prod_idx);
3205
3206 spin_unlock(&bp->spq_lock);
3207 return 0;
3208}
3209
3210/* acquire split MCP access lock register */
3211static int bnx2x_lock_alr(struct bnx2x *bp)
3212{
3213 int rc = 0;
3214 u32 i, j, val;
3215
3216 might_sleep();
3217 i = 100;
3218 for (j = 0; j < i*10; j++) {
3219 val = (1UL << 31);
3220 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3221 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3222 if (val & (1L << 31))
3223 break;
3224
3225 msleep(5);
3226 }
3227
3228 if (!(val & (1L << 31))) {
3229 BNX2X_ERR("Cannot acquire nvram interface\n");
3230
3231 rc = -EBUSY;
3232 }
3233
3234 return rc;
3235}
3236
3237/* Release split MCP access lock register */
3238static void bnx2x_unlock_alr(struct bnx2x *bp)
3239{
3240 u32 val = 0;
3241
3242 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3243}
3244
3245static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3246{
3247 struct host_def_status_block *def_sb = bp->def_status_blk;
3248 u16 rc = 0;
3249
3250 barrier(); /* status block is written to by the chip */
3251
3252 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3253 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3254 rc |= 1;
3255 }
3256 if (bp->def_c_idx != def_sb->c_def_status_block.status_block_index) {
3257 bp->def_c_idx = def_sb->c_def_status_block.status_block_index;
3258 rc |= 2;
3259 }
3260 if (bp->def_u_idx != def_sb->u_def_status_block.status_block_index) {
3261 bp->def_u_idx = def_sb->u_def_status_block.status_block_index;
3262 rc |= 4;
3263 }
3264 if (bp->def_x_idx != def_sb->x_def_status_block.status_block_index) {
3265 bp->def_x_idx = def_sb->x_def_status_block.status_block_index;
3266 rc |= 8;
3267 }
3268 if (bp->def_t_idx != def_sb->t_def_status_block.status_block_index) {
3269 bp->def_t_idx = def_sb->t_def_status_block.status_block_index;
3270 rc |= 16;
3271 }
3272 return rc;
3273}
3274
3275/*
3276 * slow path service functions
3277 */
3278
3279static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3280{
3281 int port = bp->port;
3282 u32 igu_addr = (IGU_ADDR_ATTN_BITS_SET + IGU_PORT_BASE * port) * 8;
3283 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3284 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3285 u32 nig_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3286 NIG_REG_MASK_INTERRUPT_PORT0;
3287
3288 if (~bp->aeu_mask & (asserted & 0xff))
3289 BNX2X_ERR("IGU ERROR\n");
3290 if (bp->attn_state & asserted)
3291 BNX2X_ERR("IGU ERROR\n");
3292
3293 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3294 bp->aeu_mask, asserted);
3295 bp->aeu_mask &= ~(asserted & 0xff);
3296 DP(NETIF_MSG_HW, "after masking: aeu_mask %x\n", bp->aeu_mask);
3297
3298 REG_WR(bp, aeu_addr, bp->aeu_mask);
3299
3300 bp->attn_state |= asserted;
3301
3302 if (asserted & ATTN_HARD_WIRED_MASK) {
3303 if (asserted & ATTN_NIG_FOR_FUNC) {
3304 u32 nig_status_port;
3305 u32 nig_int_addr = port ?
3306 NIG_REG_STATUS_INTERRUPT_PORT1 :
3307 NIG_REG_STATUS_INTERRUPT_PORT0;
3308
3309 bp->nig_mask = REG_RD(bp, nig_mask_addr);
3310 REG_WR(bp, nig_mask_addr, 0);
3311
3312 nig_status_port = REG_RD(bp, nig_int_addr);
3313 bnx2x_link_update(bp);
3314
3315 /* handle unicore attn? */
3316 }
3317 if (asserted & ATTN_SW_TIMER_4_FUNC)
3318 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3319
3320 if (asserted & GPIO_2_FUNC)
3321 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3322
3323 if (asserted & GPIO_3_FUNC)
3324 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3325
3326 if (asserted & GPIO_4_FUNC)
3327 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3328
3329 if (port == 0) {
3330 if (asserted & ATTN_GENERAL_ATTN_1) {
3331 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3332 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3333 }
3334 if (asserted & ATTN_GENERAL_ATTN_2) {
3335 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3336 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3337 }
3338 if (asserted & ATTN_GENERAL_ATTN_3) {
3339 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3340 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3341 }
3342 } else {
3343 if (asserted & ATTN_GENERAL_ATTN_4) {
3344 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3345 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3346 }
3347 if (asserted & ATTN_GENERAL_ATTN_5) {
3348 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3349 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3350 }
3351 if (asserted & ATTN_GENERAL_ATTN_6) {
3352 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3353 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3354 }
3355 }
3356
3357 } /* if hardwired */
3358
3359 DP(NETIF_MSG_HW, "about to mask 0x%08x at IGU addr 0x%x\n",
3360 asserted, BAR_IGU_INTMEM + igu_addr);
3361 REG_WR(bp, BAR_IGU_INTMEM + igu_addr, asserted);
3362
3363 /* now set back the mask */
3364 if (asserted & ATTN_NIG_FOR_FUNC)
3365 REG_WR(bp, nig_mask_addr, bp->nig_mask);
3366}
3367
3368static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
3369{
3370 int port = bp->port;
3371 int index;
3372 struct attn_route attn;
3373 struct attn_route group_mask;
3374 u32 reg_addr;
3375 u32 val;
3376
3377 /* need to take HW lock because MCP or other port might also
3378 try to handle this event */
3379 bnx2x_lock_alr(bp);
3380
3381 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
3382 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
3383 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
3384 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
3385 DP(NETIF_MSG_HW, "attn %llx\n", (unsigned long long)attn.sig[0]);
3386
3387 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
3388 if (deasserted & (1 << index)) {
3389 group_mask = bp->attn_group[index];
3390
3391 DP(NETIF_MSG_HW, "group[%d]: %llx\n", index,
3392 (unsigned long long)group_mask.sig[0]);
3393
3394 if (attn.sig[3] & group_mask.sig[3] &
3395 EVEREST_GEN_ATTN_IN_USE_MASK) {
3396
3397 if (attn.sig[3] & BNX2X_MC_ASSERT_BITS) {
3398
3399 BNX2X_ERR("MC assert!\n");
3400 bnx2x_panic();
3401
3402 } else if (attn.sig[3] & BNX2X_MCP_ASSERT) {
3403
3404 BNX2X_ERR("MCP assert!\n");
3405 REG_WR(bp,
3406 MISC_REG_AEU_GENERAL_ATTN_11, 0);
3407 bnx2x_mc_assert(bp);
3408
3409 } else {
3410 BNX2X_ERR("UNKOWEN HW ASSERT!\n");
3411 }
3412 }
3413
3414 if (attn.sig[1] & group_mask.sig[1] &
3415 BNX2X_DOORQ_ASSERT) {
3416
3417 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3418 BNX2X_ERR("DB hw attention 0x%x\n", val);
3419 /* DORQ discard attention */
3420 if (val & 0x2)
3421 BNX2X_ERR("FATAL error from DORQ\n");
3422 }
3423
3424 if (attn.sig[2] & group_mask.sig[2] &
3425 AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3426
3427 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3428 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3429 /* CFC error attention */
3430 if (val & 0x2)
3431 BNX2X_ERR("FATAL error from CFC\n");
3432 }
3433
3434 if (attn.sig[2] & group_mask.sig[2] &
3435 AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3436
3437 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3438 BNX2X_ERR("PXP hw attention 0x%x\n", val);
3439 /* RQ_USDMDP_FIFO_OVERFLOW */
3440 if (val & 0x18000)
3441 BNX2X_ERR("FATAL error from PXP\n");
3442 }
3443
3444 if (attn.sig[3] & group_mask.sig[3] &
3445 EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3446
3447 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
3448 0x7ff);
3449 DP(NETIF_MSG_HW, "got latched bits 0x%x\n",
3450 attn.sig[3]);
3451 }
3452
3453 if ((attn.sig[0] & group_mask.sig[0] &
3454 HW_INTERRUT_ASSERT_SET_0) ||
3455 (attn.sig[1] & group_mask.sig[1] &
3456 HW_INTERRUT_ASSERT_SET_1) ||
3457 (attn.sig[2] & group_mask.sig[2] &
3458 HW_INTERRUT_ASSERT_SET_2))
3459 BNX2X_ERR("FATAL HW block attention\n");
3460
3461 if ((attn.sig[0] & group_mask.sig[0] &
3462 HW_PRTY_ASSERT_SET_0) ||
3463 (attn.sig[1] & group_mask.sig[1] &
3464 HW_PRTY_ASSERT_SET_1) ||
3465 (attn.sig[2] & group_mask.sig[2] &
3466 HW_PRTY_ASSERT_SET_2))
3467 BNX2X_ERR("FATAL HW block parity atention\n");
3468 }
3469 }
3470
3471 bnx2x_unlock_alr(bp);
3472
3473 reg_addr = (IGU_ADDR_ATTN_BITS_CLR + IGU_PORT_BASE * port) * 8;
3474
3475 val = ~deasserted;
3476/* DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
3477 val, BAR_IGU_INTMEM + reg_addr); */
3478 REG_WR(bp, BAR_IGU_INTMEM + reg_addr, val);
3479
3480 if (bp->aeu_mask & (deasserted & 0xff))
3481 BNX2X_ERR("IGU BUG\n");
3482 if (~bp->attn_state & deasserted)
3483 BNX2X_ERR("IGU BUG\n");
3484
3485 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3486 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3487
3488 DP(NETIF_MSG_HW, "aeu_mask %x\n", bp->aeu_mask);
3489 bp->aeu_mask |= (deasserted & 0xff);
3490
3491 DP(NETIF_MSG_HW, "new mask %x\n", bp->aeu_mask);
3492 REG_WR(bp, reg_addr, bp->aeu_mask);
3493
3494 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3495 bp->attn_state &= ~deasserted;
3496 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3497}
3498
3499static void bnx2x_attn_int(struct bnx2x *bp)
3500{
3501 /* read local copy of bits */
3502 u32 attn_bits = bp->def_status_blk->atten_status_block.attn_bits;
3503 u32 attn_ack = bp->def_status_blk->atten_status_block.attn_bits_ack;
3504 u32 attn_state = bp->attn_state;
3505
3506 /* look for changed bits */
3507 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
3508 u32 deasserted = ~attn_bits & attn_ack & attn_state;
3509
3510 DP(NETIF_MSG_HW,
3511 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
3512 attn_bits, attn_ack, asserted, deasserted);
3513
3514 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
3515 BNX2X_ERR("bad attention state\n");
3516
3517 /* handle bits that were raised */
3518 if (asserted)
3519 bnx2x_attn_int_asserted(bp, asserted);
3520
3521 if (deasserted)
3522 bnx2x_attn_int_deasserted(bp, deasserted);
3523}
3524
3525static void bnx2x_sp_task(struct work_struct *work)
3526{
3527 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task);
3528 u16 status;
3529
3530 /* Return here if interrupt is disabled */
3531 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3532 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
3533 return;
3534 }
3535
3536 status = bnx2x_update_dsb_idx(bp);
3537 if (status == 0)
3538 BNX2X_ERR("spurious slowpath interrupt!\n");
3539
3540 DP(NETIF_MSG_INTR, "got a slowpath interrupt (updated %x)\n", status);
3541
3542 if (status & 0x1) {
3543 /* HW attentions */
3544 bnx2x_attn_int(bp);
3545 }
3546
3547 /* CStorm events: query_stats, cfc delete ramrods */
3548 if (status & 0x2)
3549 bp->stat_pending = 0;
3550
3551 bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, bp->def_att_idx,
3552 IGU_INT_NOP, 1);
3553 bnx2x_ack_sb(bp, DEF_SB_ID, USTORM_ID, le16_to_cpu(bp->def_u_idx),
3554 IGU_INT_NOP, 1);
3555 bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, le16_to_cpu(bp->def_c_idx),
3556 IGU_INT_NOP, 1);
3557 bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, le16_to_cpu(bp->def_x_idx),
3558 IGU_INT_NOP, 1);
3559 bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx),
3560 IGU_INT_ENABLE, 1);
3561}
3562
3563static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
3564{
3565 struct net_device *dev = dev_instance;
3566 struct bnx2x *bp = netdev_priv(dev);
3567
3568 /* Return here if interrupt is disabled */
3569 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3570 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
3571 return IRQ_HANDLED;
3572 }
3573
3574 bnx2x_ack_sb(bp, 16, XSTORM_ID, 0, IGU_INT_DISABLE, 0);
3575
3576#ifdef BNX2X_STOP_ON_ERROR
3577 if (unlikely(bp->panic))
3578 return IRQ_HANDLED;
3579#endif
3580
3581 schedule_work(&bp->sp_task);
3582
3583 return IRQ_HANDLED;
3584}
3585
3586/* end of slow path */
3587
3588/* Statistics */
3589
3590/****************************************************************************
3591* Macros
3592****************************************************************************/
3593
3594#define UPDATE_STAT(s, t) \
3595 do { \
3596 estats->t += new->s - old->s; \
3597 old->s = new->s; \
3598 } while (0)
3599
3600/* sum[hi:lo] += add[hi:lo] */
3601#define ADD_64(s_hi, a_hi, s_lo, a_lo) \
3602 do { \
3603 s_lo += a_lo; \
3604 s_hi += a_hi + (s_lo < a_lo) ? 1 : 0; \
3605 } while (0)
3606
3607/* difference = minuend - subtrahend */
3608#define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
3609 do { \
3610 if (m_lo < s_lo) { /* underflow */ \
3611 d_hi = m_hi - s_hi; \
3612 if (d_hi > 0) { /* we can 'loan' 1 */ \
3613 d_hi--; \
3614 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
3615 } else { /* m_hi <= s_hi */ \
3616 d_hi = 0; \
3617 d_lo = 0; \
3618 } \
3619 } else { /* m_lo >= s_lo */ \
3620 if (m_hi < s_hi) { \
3621 d_hi = 0; \
3622 d_lo = 0; \
3623 } else { /* m_hi >= s_hi */ \
3624 d_hi = m_hi - s_hi; \
3625 d_lo = m_lo - s_lo; \
3626 } \
3627 } \
3628 } while (0)
3629
3630/* minuend -= subtrahend */
3631#define SUB_64(m_hi, s_hi, m_lo, s_lo) \
3632 do { \
3633 DIFF_64(m_hi, m_hi, s_hi, m_lo, m_lo, s_lo); \
3634 } while (0)
3635
3636#define UPDATE_STAT64(s_hi, t_hi, s_lo, t_lo) \
3637 do { \
3638 DIFF_64(diff.hi, new->s_hi, old->s_hi, \
3639 diff.lo, new->s_lo, old->s_lo); \
3640 old->s_hi = new->s_hi; \
3641 old->s_lo = new->s_lo; \
3642 ADD_64(estats->t_hi, diff.hi, \
3643 estats->t_lo, diff.lo); \
3644 } while (0)
3645
3646/* sum[hi:lo] += add */
3647#define ADD_EXTEND_64(s_hi, s_lo, a) \
3648 do { \
3649 s_lo += a; \
3650 s_hi += (s_lo < a) ? 1 : 0; \
3651 } while (0)
3652
3653#define UPDATE_EXTEND_STAT(s, t_hi, t_lo) \
3654 do { \
3655 ADD_EXTEND_64(estats->t_hi, estats->t_lo, new->s); \
3656 } while (0)
3657
3658#define UPDATE_EXTEND_TSTAT(s, t_hi, t_lo) \
3659 do { \
3660 diff = le32_to_cpu(tclient->s) - old_tclient->s; \
3661 old_tclient->s = le32_to_cpu(tclient->s); \
3662 ADD_EXTEND_64(estats->t_hi, estats->t_lo, diff); \
3663 } while (0)
3664
3665/*
3666 * General service functions
3667 */
3668
3669static inline long bnx2x_hilo(u32 *hiref)
3670{
3671 u32 lo = *(hiref + 1);
3672#if (BITS_PER_LONG == 64)
3673 u32 hi = *hiref;
3674
3675 return HILO_U64(hi, lo);
3676#else
3677 return lo;
3678#endif
3679}
3680
3681/*
3682 * Init service functions
3683 */
3684
3685static void bnx2x_init_mac_stats(struct bnx2x *bp)
3686{
3687 struct dmae_command *dmae;
3688 int port = bp->port;
3689 int loader_idx = port * 8;
3690 u32 opcode;
3691 u32 mac_addr;
3692
3693 bp->executer_idx = 0;
3694 if (bp->fw_mb) {
3695 /* MCP */
3696 opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3697 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3698#ifdef __BIG_ENDIAN
3699 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3700#else
3701 DMAE_CMD_ENDIANITY_DW_SWAP |
3702#endif
3703 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
3704
3705 if (bp->link_up)
3706 opcode |= (DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE);
3707
3708 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3709 dmae->opcode = opcode;
3710 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, eth_stats) +
3711 sizeof(u32));
3712 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, eth_stats) +
3713 sizeof(u32));
3714 dmae->dst_addr_lo = bp->fw_mb >> 2;
3715 dmae->dst_addr_hi = 0;
3716 dmae->len = (offsetof(struct bnx2x_eth_stats, mac_stx_end) -
3717 sizeof(u32)) >> 2;
3718 if (bp->link_up) {
3719 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3720 dmae->comp_addr_hi = 0;
3721 dmae->comp_val = 1;
3722 } else {
3723 dmae->comp_addr_lo = 0;
3724 dmae->comp_addr_hi = 0;
3725 dmae->comp_val = 0;
3726 }
3727 }
3728
3729 if (!bp->link_up) {
3730 /* no need to collect statistics in link down */
3731 return;
3732 }
3733
3734 opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3735 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3736 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3737#ifdef __BIG_ENDIAN
3738 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3739#else
3740 DMAE_CMD_ENDIANITY_DW_SWAP |
3741#endif
3742 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
3743
3744 if (bp->phy_flags & PHY_BMAC_FLAG) {
3745
3746 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
3747 NIG_REG_INGRESS_BMAC0_MEM);
3748
3749 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
3750 BIGMAC_REGISTER_TX_STAT_GTBYT */
3751 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3752 dmae->opcode = opcode;
3753 dmae->src_addr_lo = (mac_addr +
3754 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3755 dmae->src_addr_hi = 0;
3756 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3757 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3758 dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
3759 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3760 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3761 dmae->comp_addr_hi = 0;
3762 dmae->comp_val = 1;
3763
3764 /* BIGMAC_REGISTER_RX_STAT_GR64 ..
3765 BIGMAC_REGISTER_RX_STAT_GRIPJ */
3766 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3767 dmae->opcode = opcode;
3768 dmae->src_addr_lo = (mac_addr +
3769 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3770 dmae->src_addr_hi = 0;
3771 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3772 offsetof(struct bmac_stats, rx_gr64));
3773 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3774 offsetof(struct bmac_stats, rx_gr64));
3775 dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
3776 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3777 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3778 dmae->comp_addr_hi = 0;
3779 dmae->comp_val = 1;
3780
3781 } else if (bp->phy_flags & PHY_EMAC_FLAG) {
3782
3783 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
3784
3785 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
3786 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3787 dmae->opcode = opcode;
3788 dmae->src_addr_lo = (mac_addr +
3789 EMAC_REG_EMAC_RX_STAT_AC) >> 2;
3790 dmae->src_addr_hi = 0;
3791 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3792 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3793 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
3794 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3795 dmae->comp_addr_hi = 0;
3796 dmae->comp_val = 1;
3797
3798 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
3799 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3800 dmae->opcode = opcode;
3801 dmae->src_addr_lo = (mac_addr +
3802 EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
3803 dmae->src_addr_hi = 0;
3804 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3805 offsetof(struct emac_stats,
3806 rx_falsecarriererrors));
3807 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3808 offsetof(struct emac_stats,
3809 rx_falsecarriererrors));
3810 dmae->len = 1;
3811 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3812 dmae->comp_addr_hi = 0;
3813 dmae->comp_val = 1;
3814
3815 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
3816 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3817 dmae->opcode = opcode;
3818 dmae->src_addr_lo = (mac_addr +
3819 EMAC_REG_EMAC_TX_STAT_AC) >> 2;
3820 dmae->src_addr_hi = 0;
3821 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3822 offsetof(struct emac_stats,
3823 tx_ifhcoutoctets));
3824 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3825 offsetof(struct emac_stats,
3826 tx_ifhcoutoctets));
3827 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
3828 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3829 dmae->comp_addr_hi = 0;
3830 dmae->comp_val = 1;
3831 }
3832
3833 /* NIG */
3834 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3835 dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3836 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
3837 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3838#ifdef __BIG_ENDIAN
3839 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3840#else
3841 DMAE_CMD_ENDIANITY_DW_SWAP |
3842#endif
3843 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
3844 dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
3845 NIG_REG_STAT0_BRB_DISCARD) >> 2;
3846 dmae->src_addr_hi = 0;
3847 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig));
3848 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig));
3849 dmae->len = (sizeof(struct nig_stats) - 2*sizeof(u32)) >> 2;
3850 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig) +
3851 offsetof(struct nig_stats, done));
3852 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig) +
3853 offsetof(struct nig_stats, done));
3854 dmae->comp_val = 0xffffffff;
3855}
3856
3857static void bnx2x_init_stats(struct bnx2x *bp)
3858{
3859 int port = bp->port;
3860
3861 bp->stats_state = STATS_STATE_DISABLE;
3862 bp->executer_idx = 0;
3863
3864 bp->old_brb_discard = REG_RD(bp,
3865 NIG_REG_STAT0_BRB_DISCARD + port*0x38);
3866
3867 memset(&bp->old_bmac, 0, sizeof(struct bmac_stats));
3868 memset(&bp->old_tclient, 0, sizeof(struct tstorm_per_client_stats));
3869 memset(&bp->dev->stats, 0, sizeof(struct net_device_stats));
3870
3871 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(port), 1);
3872 REG_WR(bp, BAR_XSTRORM_INTMEM +
3873 XSTORM_STATS_FLAGS_OFFSET(port) + 4, 0);
3874
3875 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(port), 1);
3876 REG_WR(bp, BAR_TSTRORM_INTMEM +
3877 TSTORM_STATS_FLAGS_OFFSET(port) + 4, 0);
3878
3879 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(port), 0);
3880 REG_WR(bp, BAR_CSTRORM_INTMEM +
3881 CSTORM_STATS_FLAGS_OFFSET(port) + 4, 0);
3882
3883 REG_WR(bp, BAR_XSTRORM_INTMEM +
3884 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port),
3885 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
3886 REG_WR(bp, BAR_XSTRORM_INTMEM +
3887 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port) + 4,
3888 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
3889
3890 REG_WR(bp, BAR_TSTRORM_INTMEM +
3891 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port),
3892 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
3893 REG_WR(bp, BAR_TSTRORM_INTMEM +
3894 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port) + 4,
3895 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
3896}
3897
3898static void bnx2x_stop_stats(struct bnx2x *bp)
3899{
3900 might_sleep();
3901 if (bp->stats_state != STATS_STATE_DISABLE) {
3902 int timeout = 10;
3903
3904 bp->stats_state = STATS_STATE_STOP;
3905 DP(BNX2X_MSG_STATS, "stats_state - STOP\n");
3906
3907 while (bp->stats_state != STATS_STATE_DISABLE) {
3908 if (!timeout) {
3909 BNX2X_ERR("timeout wating for stats stop\n");
3910 break;
3911 }
3912 timeout--;
3913 msleep(100);
3914 }
3915 }
3916 DP(BNX2X_MSG_STATS, "stats_state - DISABLE\n");
3917}
3918
3919/*
3920 * Statistics service functions
3921 */
3922
3923static void bnx2x_update_bmac_stats(struct bnx2x *bp)
3924{
3925 struct regp diff;
3926 struct regp sum;
3927 struct bmac_stats *new = bnx2x_sp(bp, mac_stats.bmac);
3928 struct bmac_stats *old = &bp->old_bmac;
3929 struct bnx2x_eth_stats *estats = bnx2x_sp(bp, eth_stats);
3930
3931 sum.hi = 0;
3932 sum.lo = 0;
3933
3934 UPDATE_STAT64(tx_gtbyt.hi, total_bytes_transmitted_hi,
3935 tx_gtbyt.lo, total_bytes_transmitted_lo);
3936
3937 UPDATE_STAT64(tx_gtmca.hi, total_multicast_packets_transmitted_hi,
3938 tx_gtmca.lo, total_multicast_packets_transmitted_lo);
3939 ADD_64(sum.hi, diff.hi, sum.lo, diff.lo);
3940
3941 UPDATE_STAT64(tx_gtgca.hi, total_broadcast_packets_transmitted_hi,
3942 tx_gtgca.lo, total_broadcast_packets_transmitted_lo);
3943 ADD_64(sum.hi, diff.hi, sum.lo, diff.lo);
3944
3945 UPDATE_STAT64(tx_gtpkt.hi, total_unicast_packets_transmitted_hi,
3946 tx_gtpkt.lo, total_unicast_packets_transmitted_lo);
3947 SUB_64(estats->total_unicast_packets_transmitted_hi, sum.hi,
3948 estats->total_unicast_packets_transmitted_lo, sum.lo);
3949
3950 UPDATE_STAT(tx_gtxpf.lo, pause_xoff_frames_transmitted);
3951 UPDATE_STAT(tx_gt64.lo, frames_transmitted_64_bytes);
3952 UPDATE_STAT(tx_gt127.lo, frames_transmitted_65_127_bytes);
3953 UPDATE_STAT(tx_gt255.lo, frames_transmitted_128_255_bytes);
3954 UPDATE_STAT(tx_gt511.lo, frames_transmitted_256_511_bytes);
3955 UPDATE_STAT(tx_gt1023.lo, frames_transmitted_512_1023_bytes);
3956 UPDATE_STAT(tx_gt1518.lo, frames_transmitted_1024_1522_bytes);
3957 UPDATE_STAT(tx_gt2047.lo, frames_transmitted_1523_9022_bytes);
3958 UPDATE_STAT(tx_gt4095.lo, frames_transmitted_1523_9022_bytes);
3959 UPDATE_STAT(tx_gt9216.lo, frames_transmitted_1523_9022_bytes);
3960 UPDATE_STAT(tx_gt16383.lo, frames_transmitted_1523_9022_bytes);
3961
3962 UPDATE_STAT(rx_grfcs.lo, crc_receive_errors);
3963 UPDATE_STAT(rx_grund.lo, runt_packets_received);
3964 UPDATE_STAT(rx_grovr.lo, stat_Dot3statsFramesTooLong);
3965 UPDATE_STAT(rx_grxpf.lo, pause_xoff_frames_received);
3966 UPDATE_STAT(rx_grxcf.lo, control_frames_received);
3967 /* UPDATE_STAT(rx_grxpf.lo, control_frames_received); */
3968 UPDATE_STAT(rx_grfrg.lo, error_runt_packets_received);
3969 UPDATE_STAT(rx_grjbr.lo, error_jabber_packets_received);
3970
3971 UPDATE_STAT64(rx_grerb.hi, stat_IfHCInBadOctets_hi,
3972 rx_grerb.lo, stat_IfHCInBadOctets_lo);
3973 UPDATE_STAT64(tx_gtufl.hi, stat_IfHCOutBadOctets_hi,
3974 tx_gtufl.lo, stat_IfHCOutBadOctets_lo);
3975 UPDATE_STAT(tx_gterr.lo, stat_Dot3statsInternalMacTransmitErrors);
3976 /* UPDATE_STAT(rx_grxpf.lo, stat_XoffStateEntered); */
3977 estats->stat_XoffStateEntered = estats->pause_xoff_frames_received;
3978}
3979
3980static void bnx2x_update_emac_stats(struct bnx2x *bp)
3981{
3982 struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac);
3983 struct bnx2x_eth_stats *estats = bnx2x_sp(bp, eth_stats);
3984
3985 UPDATE_EXTEND_STAT(tx_ifhcoutoctets, total_bytes_transmitted_hi,
3986 total_bytes_transmitted_lo);
3987 UPDATE_EXTEND_STAT(tx_ifhcoutucastpkts,
3988 total_unicast_packets_transmitted_hi,
3989 total_unicast_packets_transmitted_lo);
3990 UPDATE_EXTEND_STAT(tx_ifhcoutmulticastpkts,
3991 total_multicast_packets_transmitted_hi,
3992 total_multicast_packets_transmitted_lo);
3993 UPDATE_EXTEND_STAT(tx_ifhcoutbroadcastpkts,
3994 total_broadcast_packets_transmitted_hi,
3995 total_broadcast_packets_transmitted_lo);
3996
3997 estats->pause_xon_frames_transmitted += new->tx_outxonsent;
3998 estats->pause_xoff_frames_transmitted += new->tx_outxoffsent;
3999 estats->single_collision_transmit_frames +=
4000 new->tx_dot3statssinglecollisionframes;
4001 estats->multiple_collision_transmit_frames +=
4002 new->tx_dot3statsmultiplecollisionframes;
4003 estats->late_collision_frames += new->tx_dot3statslatecollisions;
4004 estats->excessive_collision_frames +=
4005 new->tx_dot3statsexcessivecollisions;
4006 estats->frames_transmitted_64_bytes += new->tx_etherstatspkts64octets;
4007 estats->frames_transmitted_65_127_bytes +=
4008 new->tx_etherstatspkts65octetsto127octets;
4009 estats->frames_transmitted_128_255_bytes +=
4010 new->tx_etherstatspkts128octetsto255octets;
4011 estats->frames_transmitted_256_511_bytes +=
4012 new->tx_etherstatspkts256octetsto511octets;
4013 estats->frames_transmitted_512_1023_bytes +=
4014 new->tx_etherstatspkts512octetsto1023octets;
4015 estats->frames_transmitted_1024_1522_bytes +=
4016 new->tx_etherstatspkts1024octetsto1522octet;
4017 estats->frames_transmitted_1523_9022_bytes +=
4018 new->tx_etherstatspktsover1522octets;
4019
4020 estats->crc_receive_errors += new->rx_dot3statsfcserrors;
4021 estats->alignment_errors += new->rx_dot3statsalignmenterrors;
4022 estats->false_carrier_detections += new->rx_falsecarriererrors;
4023 estats->runt_packets_received += new->rx_etherstatsundersizepkts;
4024 estats->stat_Dot3statsFramesTooLong += new->rx_dot3statsframestoolong;
4025 estats->pause_xon_frames_received += new->rx_xonpauseframesreceived;
4026 estats->pause_xoff_frames_received += new->rx_xoffpauseframesreceived;
4027 estats->control_frames_received += new->rx_maccontrolframesreceived;
4028 estats->error_runt_packets_received += new->rx_etherstatsfragments;
4029 estats->error_jabber_packets_received += new->rx_etherstatsjabbers;
4030
4031 UPDATE_EXTEND_STAT(rx_ifhcinbadoctets, stat_IfHCInBadOctets_hi,
4032 stat_IfHCInBadOctets_lo);
4033 UPDATE_EXTEND_STAT(tx_ifhcoutbadoctets, stat_IfHCOutBadOctets_hi,
4034 stat_IfHCOutBadOctets_lo);
4035 estats->stat_Dot3statsInternalMacTransmitErrors +=
4036 new->tx_dot3statsinternalmactransmiterrors;
4037 estats->stat_Dot3StatsCarrierSenseErrors +=
4038 new->rx_dot3statscarriersenseerrors;
4039 estats->stat_Dot3StatsDeferredTransmissions +=
4040 new->tx_dot3statsdeferredtransmissions;
4041 estats->stat_FlowControlDone += new->tx_flowcontroldone;
4042 estats->stat_XoffStateEntered += new->rx_xoffstateentered;
4043}
4044
4045static int bnx2x_update_storm_stats(struct bnx2x *bp)
4046{
4047 struct eth_stats_query *stats = bnx2x_sp(bp, fw_stats);
4048 struct tstorm_common_stats *tstats = &stats->tstorm_common;
4049 struct tstorm_per_client_stats *tclient =
4050 &tstats->client_statistics[0];
4051 struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
4052 struct xstorm_common_stats *xstats = &stats->xstorm_common;
4053 struct nig_stats *nstats = bnx2x_sp(bp, nig);
4054 struct bnx2x_eth_stats *estats = bnx2x_sp(bp, eth_stats);
4055 u32 diff;
4056
4057 /* are DMAE stats valid? */
4058 if (nstats->done != 0xffffffff) {
4059 DP(BNX2X_MSG_STATS, "stats not updated by dmae\n");
4060 return -1;
4061 }
4062
4063 /* are storm stats valid? */
4064 if (tstats->done.hi != 0xffffffff) {
4065 DP(BNX2X_MSG_STATS, "stats not updated by tstorm\n");
4066 return -2;
4067 }
4068 if (xstats->done.hi != 0xffffffff) {
4069 DP(BNX2X_MSG_STATS, "stats not updated by xstorm\n");
4070 return -3;
4071 }
4072
4073 estats->total_bytes_received_hi =
4074 estats->valid_bytes_received_hi =
4075 le32_to_cpu(tclient->total_rcv_bytes.hi);
4076 estats->total_bytes_received_lo =
4077 estats->valid_bytes_received_lo =
4078 le32_to_cpu(tclient->total_rcv_bytes.lo);
4079 ADD_64(estats->total_bytes_received_hi,
4080 le32_to_cpu(tclient->rcv_error_bytes.hi),
4081 estats->total_bytes_received_lo,
4082 le32_to_cpu(tclient->rcv_error_bytes.lo));
4083
4084 UPDATE_EXTEND_TSTAT(rcv_unicast_pkts,
4085 total_unicast_packets_received_hi,
4086 total_unicast_packets_received_lo);
4087 UPDATE_EXTEND_TSTAT(rcv_multicast_pkts,
4088 total_multicast_packets_received_hi,
4089 total_multicast_packets_received_lo);
4090 UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts,
4091 total_broadcast_packets_received_hi,
4092 total_broadcast_packets_received_lo);
4093
4094 estats->frames_received_64_bytes = MAC_STX_NA;
4095 estats->frames_received_65_127_bytes = MAC_STX_NA;
4096 estats->frames_received_128_255_bytes = MAC_STX_NA;
4097 estats->frames_received_256_511_bytes = MAC_STX_NA;
4098 estats->frames_received_512_1023_bytes = MAC_STX_NA;
4099 estats->frames_received_1024_1522_bytes = MAC_STX_NA;
4100 estats->frames_received_1523_9022_bytes = MAC_STX_NA;
4101
4102 estats->x_total_sent_bytes_hi =
4103 le32_to_cpu(xstats->total_sent_bytes.hi);
4104 estats->x_total_sent_bytes_lo =
4105 le32_to_cpu(xstats->total_sent_bytes.lo);
4106 estats->x_total_sent_pkts = le32_to_cpu(xstats->total_sent_pkts);
4107
4108 estats->t_rcv_unicast_bytes_hi =
4109 le32_to_cpu(tclient->rcv_unicast_bytes.hi);
4110 estats->t_rcv_unicast_bytes_lo =
4111 le32_to_cpu(tclient->rcv_unicast_bytes.lo);
4112 estats->t_rcv_broadcast_bytes_hi =
4113 le32_to_cpu(tclient->rcv_broadcast_bytes.hi);
4114 estats->t_rcv_broadcast_bytes_lo =
4115 le32_to_cpu(tclient->rcv_broadcast_bytes.lo);
4116 estats->t_rcv_multicast_bytes_hi =
4117 le32_to_cpu(tclient->rcv_multicast_bytes.hi);
4118 estats->t_rcv_multicast_bytes_lo =
4119 le32_to_cpu(tclient->rcv_multicast_bytes.lo);
4120 estats->t_total_rcv_pkt = le32_to_cpu(tclient->total_rcv_pkts);
4121
4122 estats->checksum_discard = le32_to_cpu(tclient->checksum_discard);
4123 estats->packets_too_big_discard =
4124 le32_to_cpu(tclient->packets_too_big_discard);
4125 estats->jabber_packets_received = estats->packets_too_big_discard +
4126 estats->stat_Dot3statsFramesTooLong;
4127 estats->no_buff_discard = le32_to_cpu(tclient->no_buff_discard);
4128 estats->ttl0_discard = le32_to_cpu(tclient->ttl0_discard);
4129 estats->mac_discard = le32_to_cpu(tclient->mac_discard);
4130 estats->mac_filter_discard = le32_to_cpu(tstats->mac_filter_discard);
4131 estats->xxoverflow_discard = le32_to_cpu(tstats->xxoverflow_discard);
4132 estats->brb_truncate_discard =
4133 le32_to_cpu(tstats->brb_truncate_discard);
4134
4135 estats->brb_discard += nstats->brb_discard - bp->old_brb_discard;
4136 bp->old_brb_discard = nstats->brb_discard;
4137
4138 estats->brb_packet = nstats->brb_packet;
4139 estats->brb_truncate = nstats->brb_truncate;
4140 estats->flow_ctrl_discard = nstats->flow_ctrl_discard;
4141 estats->flow_ctrl_octets = nstats->flow_ctrl_octets;
4142 estats->flow_ctrl_packet = nstats->flow_ctrl_packet;
4143 estats->mng_discard = nstats->mng_discard;
4144 estats->mng_octet_inp = nstats->mng_octet_inp;
4145 estats->mng_octet_out = nstats->mng_octet_out;
4146 estats->mng_packet_inp = nstats->mng_packet_inp;
4147 estats->mng_packet_out = nstats->mng_packet_out;
4148 estats->pbf_octets = nstats->pbf_octets;
4149 estats->pbf_packet = nstats->pbf_packet;
4150 estats->safc_inp = nstats->safc_inp;
4151
4152 xstats->done.hi = 0;
4153 tstats->done.hi = 0;
4154 nstats->done = 0;
4155
4156 return 0;
4157}
4158
4159static void bnx2x_update_net_stats(struct bnx2x *bp)
4160{
4161 struct bnx2x_eth_stats *estats = bnx2x_sp(bp, eth_stats);
4162 struct net_device_stats *nstats = &bp->dev->stats;
4163
4164 nstats->rx_packets =
4165 bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
4166 bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
4167 bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
4168
4169 nstats->tx_packets =
4170 bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
4171 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
4172 bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
4173
4174 nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
4175
4176 nstats->tx_bytes =
4177 bnx2x_hilo(&estats->total_bytes_transmitted_hi);
4178
4179 nstats->rx_dropped = estats->checksum_discard +
4180 estats->mac_discard;
4181 nstats->tx_dropped = 0;
4182
4183 nstats->multicast =
4184 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi);
4185
4186 nstats->collisions =
4187 estats->single_collision_transmit_frames +
4188 estats->multiple_collision_transmit_frames +
4189 estats->late_collision_frames +
4190 estats->excessive_collision_frames;
4191
4192 nstats->rx_length_errors = estats->runt_packets_received +
4193 estats->jabber_packets_received;
4194 nstats->rx_over_errors = estats->no_buff_discard;
4195 nstats->rx_crc_errors = estats->crc_receive_errors;
4196 nstats->rx_frame_errors = estats->alignment_errors;
4197 nstats->rx_fifo_errors = estats->brb_discard +
4198 estats->brb_truncate_discard;
4199 nstats->rx_missed_errors = estats->xxoverflow_discard;
4200
4201 nstats->rx_errors = nstats->rx_length_errors +
4202 nstats->rx_over_errors +
4203 nstats->rx_crc_errors +
4204 nstats->rx_frame_errors +
4205 nstats->rx_fifo_errors;
4206
4207 nstats->tx_aborted_errors = estats->late_collision_frames +
4208 estats->excessive_collision_frames;
4209 nstats->tx_carrier_errors = estats->false_carrier_detections;
4210 nstats->tx_fifo_errors = 0;
4211 nstats->tx_heartbeat_errors = 0;
4212 nstats->tx_window_errors = 0;
4213
4214 nstats->tx_errors = nstats->tx_aborted_errors +
4215 nstats->tx_carrier_errors;
4216
4217 estats->mac_stx_start = ++estats->mac_stx_end;
4218}
4219
4220static void bnx2x_update_stats(struct bnx2x *bp)
4221{
4222 int i;
4223
4224 if (!bnx2x_update_storm_stats(bp)) {
4225
4226 if (bp->phy_flags & PHY_BMAC_FLAG) {
4227 bnx2x_update_bmac_stats(bp);
4228
4229 } else if (bp->phy_flags & PHY_EMAC_FLAG) {
4230 bnx2x_update_emac_stats(bp);
4231
4232 } else { /* unreached */
4233 BNX2X_ERR("no MAC active\n");
4234 return;
4235 }
4236
4237 bnx2x_update_net_stats(bp);
4238 }
4239
4240 if (bp->msglevel & NETIF_MSG_TIMER) {
4241 struct bnx2x_eth_stats *estats = bnx2x_sp(bp, eth_stats);
4242 struct net_device_stats *nstats = &bp->dev->stats;
4243
4244 printk(KERN_DEBUG "%s:\n", bp->dev->name);
4245 printk(KERN_DEBUG " tx avail (%4x) tx hc idx (%x)"
4246 " tx pkt (%lx)\n",
4247 bnx2x_tx_avail(bp->fp),
4248 *bp->fp->tx_cons_sb, nstats->tx_packets);
4249 printk(KERN_DEBUG " rx usage (%4x) rx hc idx (%x)"
4250 " rx pkt (%lx)\n",
4251 (u16)(*bp->fp->rx_cons_sb - bp->fp->rx_comp_cons),
4252 *bp->fp->rx_cons_sb, nstats->rx_packets);
4253 printk(KERN_DEBUG " %s (Xoff events %u) brb drops %u\n",
4254 netif_queue_stopped(bp->dev)? "Xoff" : "Xon",
4255 estats->driver_xoff, estats->brb_discard);
4256 printk(KERN_DEBUG "tstats: checksum_discard %u "
4257 "packets_too_big_discard %u no_buff_discard %u "
4258 "mac_discard %u mac_filter_discard %u "
4259 "xxovrflow_discard %u brb_truncate_discard %u "
4260 "ttl0_discard %u\n",
4261 estats->checksum_discard,
4262 estats->packets_too_big_discard,
4263 estats->no_buff_discard, estats->mac_discard,
4264 estats->mac_filter_discard, estats->xxoverflow_discard,
4265 estats->brb_truncate_discard, estats->ttl0_discard);
4266
4267 for_each_queue(bp, i) {
4268 printk(KERN_DEBUG "[%d]: %lu\t%lu\t%lu\n", i,
4269 bnx2x_fp(bp, i, tx_pkt),
4270 bnx2x_fp(bp, i, rx_pkt),
4271 bnx2x_fp(bp, i, rx_calls));
4272 }
4273 }
4274
4275 if (bp->state != BNX2X_STATE_OPEN) {
4276 DP(BNX2X_MSG_STATS, "state is %x, returning\n", bp->state);
4277 return;
4278 }
4279
4280#ifdef BNX2X_STOP_ON_ERROR
4281 if (unlikely(bp->panic))
4282 return;
4283#endif
4284
4285 /* loader */
4286 if (bp->executer_idx) {
4287 struct dmae_command *dmae = &bp->dmae;
4288 int port = bp->port;
4289 int loader_idx = port * 8;
4290
4291 memset(dmae, 0, sizeof(struct dmae_command));
4292
4293 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
4294 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
4295 DMAE_CMD_DST_RESET |
4296#ifdef __BIG_ENDIAN
4297 DMAE_CMD_ENDIANITY_B_DW_SWAP |
4298#else
4299 DMAE_CMD_ENDIANITY_DW_SWAP |
4300#endif
4301 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
4302 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
4303 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
4304 dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
4305 sizeof(struct dmae_command) *
4306 (loader_idx + 1)) >> 2;
4307 dmae->dst_addr_hi = 0;
4308 dmae->len = sizeof(struct dmae_command) >> 2;
4309 dmae->len--; /* !!! for A0/1 only */
4310 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
4311 dmae->comp_addr_hi = 0;
4312 dmae->comp_val = 1;
4313
4314 bnx2x_post_dmae(bp, dmae, loader_idx);
4315 }
4316
4317 if (bp->stats_state != STATS_STATE_ENABLE) {
4318 bp->stats_state = STATS_STATE_DISABLE;
4319 return;
4320 }
4321
4322 if (bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0, 0, 0, 0) == 0) {
4323 /* stats ramrod has it's own slot on the spe */
4324 bp->spq_left++;
4325 bp->stat_pending = 1;
4326 }
4327}
4328
4329static void bnx2x_timer(unsigned long data)
4330{
4331 struct bnx2x *bp = (struct bnx2x *) data;
4332
4333 if (!netif_running(bp->dev))
4334 return;
4335
4336 if (atomic_read(&bp->intr_sem) != 0)
4337 goto bnx2x_restart_timer;
4338
4339 if (poll) {
4340 struct bnx2x_fastpath *fp = &bp->fp[0];
4341 int rc;
4342
4343 bnx2x_tx_int(fp, 1000);
4344 rc = bnx2x_rx_int(fp, 1000);
4345 }
4346
4347 if (!nomcp && (bp->bc_ver >= 0x040003)) {
4348 int port = bp->port;
4349 u32 drv_pulse;
4350 u32 mcp_pulse;
4351
4352 ++bp->fw_drv_pulse_wr_seq;
4353 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4354 /* TBD - add SYSTEM_TIME */
4355 drv_pulse = bp->fw_drv_pulse_wr_seq;
4356 SHMEM_WR(bp, drv_fw_mb[port].drv_pulse_mb, drv_pulse);
4357
4358 mcp_pulse = (SHMEM_RD(bp, drv_fw_mb[port].mcp_pulse_mb) &
4359 MCP_PULSE_SEQ_MASK);
4360 /* The delta between driver pulse and mcp response
4361 * should be 1 (before mcp response) or 0 (after mcp response)
4362 */
4363 if ((drv_pulse != mcp_pulse) &&
4364 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4365 /* someone lost a heartbeat... */
4366 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4367 drv_pulse, mcp_pulse);
4368 }
4369 }
4370
4371 if (bp->stats_state == STATS_STATE_DISABLE)
4372 goto bnx2x_restart_timer;
4373
4374 bnx2x_update_stats(bp);
4375
4376bnx2x_restart_timer:
4377 mod_timer(&bp->timer, jiffies + bp->current_interval);
4378}
4379
4380/* end of Statistics */
4381
4382/* nic init */
4383
4384/*
4385 * nic init service functions
4386 */
4387
4388static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
4389 dma_addr_t mapping, int id)
4390{
4391 int port = bp->port;
4392 u64 section;
4393 int index;
4394
4395 /* USTORM */
4396 section = ((u64)mapping) + offsetof(struct host_status_block,
4397 u_status_block);
4398 sb->u_status_block.status_block_id = id;
4399
4400 REG_WR(bp, BAR_USTRORM_INTMEM +
4401 USTORM_SB_HOST_SB_ADDR_OFFSET(port, id), U64_LO(section));
4402 REG_WR(bp, BAR_USTRORM_INTMEM +
4403 ((USTORM_SB_HOST_SB_ADDR_OFFSET(port, id)) + 4),
4404 U64_HI(section));
4405
4406 for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
4407 REG_WR16(bp, BAR_USTRORM_INTMEM +
4408 USTORM_SB_HC_DISABLE_OFFSET(port, id, index), 0x1);
4409
4410 /* CSTORM */
4411 section = ((u64)mapping) + offsetof(struct host_status_block,
4412 c_status_block);
4413 sb->c_status_block.status_block_id = id;
4414
4415 REG_WR(bp, BAR_CSTRORM_INTMEM +
4416 CSTORM_SB_HOST_SB_ADDR_OFFSET(port, id), U64_LO(section));
4417 REG_WR(bp, BAR_CSTRORM_INTMEM +
4418 ((CSTORM_SB_HOST_SB_ADDR_OFFSET(port, id)) + 4),
4419 U64_HI(section));
4420
4421 for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++)
4422 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4423 CSTORM_SB_HC_DISABLE_OFFSET(port, id, index), 0x1);
4424
4425 bnx2x_ack_sb(bp, id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4426}
4427
4428static void bnx2x_init_def_sb(struct bnx2x *bp,
4429 struct host_def_status_block *def_sb,
4430 dma_addr_t mapping, int id)
4431{
4432 int port = bp->port;
4433 int index, val, reg_offset;
4434 u64 section;
4435
4436 /* ATTN */
4437 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4438 atten_status_block);
4439 def_sb->atten_status_block.status_block_id = id;
4440
4441 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4442 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4443
4444 for (index = 0; index < 3; index++) {
4445 bp->attn_group[index].sig[0] = REG_RD(bp,
4446 reg_offset + 0x10*index);
4447 bp->attn_group[index].sig[1] = REG_RD(bp,
4448 reg_offset + 0x4 + 0x10*index);
4449 bp->attn_group[index].sig[2] = REG_RD(bp,
4450 reg_offset + 0x8 + 0x10*index);
4451 bp->attn_group[index].sig[3] = REG_RD(bp,
4452 reg_offset + 0xc + 0x10*index);
4453 }
4454
4455 bp->aeu_mask = REG_RD(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4456 MISC_REG_AEU_MASK_ATTN_FUNC_0));
4457
4458 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4459 HC_REG_ATTN_MSG0_ADDR_L);
4460
4461 REG_WR(bp, reg_offset, U64_LO(section));
4462 REG_WR(bp, reg_offset + 4, U64_HI(section));
4463
4464 reg_offset = (port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0);
4465
4466 val = REG_RD(bp, reg_offset);
4467 val |= id;
4468 REG_WR(bp, reg_offset, val);
4469
4470 /* USTORM */
4471 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4472 u_def_status_block);
4473 def_sb->u_def_status_block.status_block_id = id;
4474
4475 REG_WR(bp, BAR_USTRORM_INTMEM +
4476 USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section));
4477 REG_WR(bp, BAR_USTRORM_INTMEM +
4478 ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)) + 4),
4479 U64_HI(section));
4480 REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(port),
4481 BNX2X_BTR);
4482
4483 for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
4484 REG_WR16(bp, BAR_USTRORM_INTMEM +
4485 USTORM_DEF_SB_HC_DISABLE_OFFSET(port, index), 0x1);
4486
4487 /* CSTORM */
4488 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4489 c_def_status_block);
4490 def_sb->c_def_status_block.status_block_id = id;
4491
4492 REG_WR(bp, BAR_CSTRORM_INTMEM +
4493 CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section));
4494 REG_WR(bp, BAR_CSTRORM_INTMEM +
4495 ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)) + 4),
4496 U64_HI(section));
4497 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(port),
4498 BNX2X_BTR);
4499
4500 for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
4501 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4502 CSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index), 0x1);
4503
4504 /* TSTORM */
4505 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4506 t_def_status_block);
4507 def_sb->t_def_status_block.status_block_id = id;
4508
4509 REG_WR(bp, BAR_TSTRORM_INTMEM +
4510 TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section));
4511 REG_WR(bp, BAR_TSTRORM_INTMEM +
4512 ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)) + 4),
4513 U64_HI(section));
4514 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port),
4515 BNX2X_BTR);
4516
4517 for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
4518 REG_WR16(bp, BAR_TSTRORM_INTMEM +
4519 TSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index), 0x1);
4520
4521 /* XSTORM */
4522 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4523 x_def_status_block);
4524 def_sb->x_def_status_block.status_block_id = id;
4525
4526 REG_WR(bp, BAR_XSTRORM_INTMEM +
4527 XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section));
4528 REG_WR(bp, BAR_XSTRORM_INTMEM +
4529 ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)) + 4),
4530 U64_HI(section));
4531 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port),
4532 BNX2X_BTR);
4533
4534 for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
4535 REG_WR16(bp, BAR_XSTRORM_INTMEM +
4536 XSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index), 0x1);
4537
4538 bnx2x_ack_sb(bp, id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4539}
4540
4541static void bnx2x_update_coalesce(struct bnx2x *bp)
4542{
4543 int port = bp->port;
4544 int i;
4545
4546 for_each_queue(bp, i) {
4547
4548 /* HC_INDEX_U_ETH_RX_CQ_CONS */
4549 REG_WR8(bp, BAR_USTRORM_INTMEM +
4550 USTORM_SB_HC_TIMEOUT_OFFSET(port, i,
4551 HC_INDEX_U_ETH_RX_CQ_CONS),
4552 bp->rx_ticks_int/12);
4553 REG_WR16(bp, BAR_USTRORM_INTMEM +
4554 USTORM_SB_HC_DISABLE_OFFSET(port, i,
4555 HC_INDEX_U_ETH_RX_CQ_CONS),
4556 bp->rx_ticks_int ? 0 : 1);
4557
4558 /* HC_INDEX_C_ETH_TX_CQ_CONS */
4559 REG_WR8(bp, BAR_CSTRORM_INTMEM +
4560 CSTORM_SB_HC_TIMEOUT_OFFSET(port, i,
4561 HC_INDEX_C_ETH_TX_CQ_CONS),
4562 bp->tx_ticks_int/12);
4563 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4564 CSTORM_SB_HC_DISABLE_OFFSET(port, i,
4565 HC_INDEX_C_ETH_TX_CQ_CONS),
4566 bp->tx_ticks_int ? 0 : 1);
4567 }
4568}
4569
4570static void bnx2x_init_rx_rings(struct bnx2x *bp)
4571{
4572 u16 ring_prod;
4573 int i, j;
4574 int port = bp->port;
4575
4576 bp->rx_buf_use_size = bp->dev->mtu;
4577
4578 bp->rx_buf_use_size += bp->rx_offset + ETH_OVREHEAD;
4579 bp->rx_buf_size = bp->rx_buf_use_size + 64;
4580
4581 for_each_queue(bp, j) {
4582 struct bnx2x_fastpath *fp = &bp->fp[j];
4583
4584 fp->rx_bd_cons = 0;
4585 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4586
4587 for (i = 1; i <= NUM_RX_RINGS; i++) {
4588 struct eth_rx_bd *rx_bd;
4589
4590 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
4591 rx_bd->addr_hi =
4592 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
4593 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4594 rx_bd->addr_lo =
4595 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
4596 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4597
4598 }
4599
4600 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
4601 struct eth_rx_cqe_next_page *nextpg;
4602
4603 nextpg = (struct eth_rx_cqe_next_page *)
4604 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
4605 nextpg->addr_hi =
4606 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
4607 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4608 nextpg->addr_lo =
4609 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
4610 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4611 }
4612
4613 /* rx completion queue */
4614 fp->rx_comp_cons = ring_prod = 0;
4615
4616 for (i = 0; i < bp->rx_ring_size; i++) {
4617 if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) {
4618 BNX2X_ERR("was only able to allocate "
4619 "%d rx skbs\n", i);
4620 break;
4621 }
4622 ring_prod = NEXT_RX_IDX(ring_prod);
4623 BUG_TRAP(ring_prod > i);
4624 }
4625
4626 fp->rx_bd_prod = fp->rx_comp_prod = ring_prod;
4627 fp->rx_pkt = fp->rx_calls = 0;
4628
4629 /* Warning! this will genrate an interrupt (to the TSTORM) */
4630 /* must only be done when chip is initialized */
4631 REG_WR(bp, BAR_TSTRORM_INTMEM +
4632 TSTORM_RCQ_PROD_OFFSET(port, j), ring_prod);
4633 if (j != 0)
4634 continue;
4635
4636 REG_WR(bp, BAR_USTRORM_INTMEM +
4637 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(port),
4638 U64_LO(fp->rx_comp_mapping));
4639 REG_WR(bp, BAR_USTRORM_INTMEM +
4640 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(port) + 4,
4641 U64_HI(fp->rx_comp_mapping));
4642 }
4643}
4644
4645static void bnx2x_init_tx_ring(struct bnx2x *bp)
4646{
4647 int i, j;
4648
4649 for_each_queue(bp, j) {
4650 struct bnx2x_fastpath *fp = &bp->fp[j];
4651
4652 for (i = 1; i <= NUM_TX_RINGS; i++) {
4653 struct eth_tx_bd *tx_bd =
4654 &fp->tx_desc_ring[TX_DESC_CNT * i - 1];
4655
4656 tx_bd->addr_hi =
4657 cpu_to_le32(U64_HI(fp->tx_desc_mapping +
4658 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4659 tx_bd->addr_lo =
4660 cpu_to_le32(U64_LO(fp->tx_desc_mapping +
4661 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4662 }
4663
4664 fp->tx_pkt_prod = 0;
4665 fp->tx_pkt_cons = 0;
4666 fp->tx_bd_prod = 0;
4667 fp->tx_bd_cons = 0;
4668 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4669 fp->tx_pkt = 0;
4670 }
4671}
4672
4673static void bnx2x_init_sp_ring(struct bnx2x *bp)
4674{
4675 int port = bp->port;
4676
4677 spin_lock_init(&bp->spq_lock);
4678
4679 bp->spq_left = MAX_SPQ_PENDING;
4680 bp->spq_prod_idx = 0;
4681 bp->dsb_sp_prod_idx = 0;
4682 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4683 bp->spq_prod_bd = bp->spq;
4684 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4685
4686 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PAGE_BASE_OFFSET(port),
4687 U64_LO(bp->spq_mapping));
4688 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PAGE_BASE_OFFSET(port) + 4,
4689 U64_HI(bp->spq_mapping));
4690
4691 REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(port),
4692 bp->spq_prod_idx);
4693}
4694
4695static void bnx2x_init_context(struct bnx2x *bp)
4696{
4697 int i;
4698
4699 for_each_queue(bp, i) {
4700 struct eth_context *context = bnx2x_sp(bp, context[i].eth);
4701 struct bnx2x_fastpath *fp = &bp->fp[i];
4702
4703 context->xstorm_st_context.tx_bd_page_base_hi =
4704 U64_HI(fp->tx_desc_mapping);
4705 context->xstorm_st_context.tx_bd_page_base_lo =
4706 U64_LO(fp->tx_desc_mapping);
4707 context->xstorm_st_context.db_data_addr_hi =
4708 U64_HI(fp->tx_prods_mapping);
4709 context->xstorm_st_context.db_data_addr_lo =
4710 U64_LO(fp->tx_prods_mapping);
4711
4712 context->ustorm_st_context.rx_bd_page_base_hi =
4713 U64_HI(fp->rx_desc_mapping);
4714 context->ustorm_st_context.rx_bd_page_base_lo =
4715 U64_LO(fp->rx_desc_mapping);
4716 context->ustorm_st_context.status_block_id = i;
4717 context->ustorm_st_context.sb_index_number =
4718 HC_INDEX_U_ETH_RX_CQ_CONS;
4719 context->ustorm_st_context.rcq_base_address_hi =
4720 U64_HI(fp->rx_comp_mapping);
4721 context->ustorm_st_context.rcq_base_address_lo =
4722 U64_LO(fp->rx_comp_mapping);
4723 context->ustorm_st_context.flags =
4724 USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT;
4725 context->ustorm_st_context.mc_alignment_size = 64;
4726 context->ustorm_st_context.num_rss = bp->num_queues;
4727
4728 context->cstorm_st_context.sb_index_number =
4729 HC_INDEX_C_ETH_TX_CQ_CONS;
4730 context->cstorm_st_context.status_block_id = i;
4731
4732 context->xstorm_ag_context.cdu_reserved =
4733 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4734 CDU_REGION_NUMBER_XCM_AG,
4735 ETH_CONNECTION_TYPE);
4736 context->ustorm_ag_context.cdu_usage =
4737 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4738 CDU_REGION_NUMBER_UCM_AG,
4739 ETH_CONNECTION_TYPE);
4740 }
4741}
4742
4743static void bnx2x_init_ind_table(struct bnx2x *bp)
4744{
4745 int port = bp->port;
4746 int i;
4747
4748 if (!is_multi(bp))
4749 return;
4750
4751 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4752 REG_WR8(bp, TSTORM_INDIRECTION_TABLE_OFFSET(port) + i,
4753 i % bp->num_queues);
4754
4755 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
4756}
4757
4758static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4759{
4760 int mode = bp->rx_mode;
4761 int port = bp->port;
4762 struct tstorm_eth_mac_filter_config tstorm_mac_filter = {0};
4763 int i;
4764
4765 DP(NETIF_MSG_RX_STATUS, "rx mode is %d\n", mode);
4766
4767 switch (mode) {
4768 case BNX2X_RX_MODE_NONE: /* no Rx */
4769 tstorm_mac_filter.ucast_drop_all = 1;
4770 tstorm_mac_filter.mcast_drop_all = 1;
4771 tstorm_mac_filter.bcast_drop_all = 1;
4772 break;
4773 case BNX2X_RX_MODE_NORMAL:
4774 tstorm_mac_filter.bcast_accept_all = 1;
4775 break;
4776 case BNX2X_RX_MODE_ALLMULTI:
4777 tstorm_mac_filter.mcast_accept_all = 1;
4778 tstorm_mac_filter.bcast_accept_all = 1;
4779 break;
4780 case BNX2X_RX_MODE_PROMISC:
4781 tstorm_mac_filter.ucast_accept_all = 1;
4782 tstorm_mac_filter.mcast_accept_all = 1;
4783 tstorm_mac_filter.bcast_accept_all = 1;
4784 break;
4785 default:
4786 BNX2X_ERR("bad rx mode (%d)\n", mode);
4787 }
4788
4789 for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) {
4790 REG_WR(bp, BAR_TSTRORM_INTMEM +
4791 TSTORM_MAC_FILTER_CONFIG_OFFSET(port) + i * 4,
4792 ((u32 *)&tstorm_mac_filter)[i]);
4793
4794/* DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i,
4795 ((u32 *)&tstorm_mac_filter)[i]); */
4796 }
4797}
4798
4799static void bnx2x_set_client_config(struct bnx2x *bp, int client_id)
4800{
4801#ifdef BCM_VLAN
4802 int mode = bp->rx_mode;
4803#endif
4804 int port = bp->port;
4805 struct tstorm_eth_client_config tstorm_client = {0};
4806
4807 tstorm_client.mtu = bp->dev->mtu;
4808 tstorm_client.statistics_counter_id = 0;
4809 tstorm_client.config_flags =
4810 TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE;
4811#ifdef BCM_VLAN
4812 if (mode && bp->vlgrp) {
4813 tstorm_client.config_flags |=
4814 TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE;
4815 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
4816 }
4817#endif
4818 tstorm_client.drop_flags = (TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR |
4819 TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR |
4820 TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR |
4821 TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR);
4822
4823 REG_WR(bp, BAR_TSTRORM_INTMEM +
4824 TSTORM_CLIENT_CONFIG_OFFSET(port, client_id),
4825 ((u32 *)&tstorm_client)[0]);
4826 REG_WR(bp, BAR_TSTRORM_INTMEM +
4827 TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) + 4,
4828 ((u32 *)&tstorm_client)[1]);
4829
4830/* DP(NETIF_MSG_IFUP, "tstorm_client: 0x%08x 0x%08x\n",
4831 ((u32 *)&tstorm_client)[0], ((u32 *)&tstorm_client)[1]); */
4832}
4833
4834static void bnx2x_init_internal(struct bnx2x *bp)
4835{
4836 int port = bp->port;
4837 struct tstorm_eth_function_common_config tstorm_config = {0};
4838 struct stats_indication_flags stats_flags = {0};
4839 int i;
4840
4841 if (is_multi(bp)) {
4842 tstorm_config.config_flags = MULTI_FLAGS;
4843 tstorm_config.rss_result_mask = MULTI_MASK;
4844 }
4845
4846 REG_WR(bp, BAR_TSTRORM_INTMEM +
4847 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(port),
4848 (*(u32 *)&tstorm_config));
4849
4850/* DP(NETIF_MSG_IFUP, "tstorm_config: 0x%08x\n",
4851 (*(u32 *)&tstorm_config)); */
4852
4853 bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx untill link is up */
4854 bnx2x_set_storm_rx_mode(bp);
4855
4856 for_each_queue(bp, i)
4857 bnx2x_set_client_config(bp, i);
4858
4859
4860 stats_flags.collect_eth = cpu_to_le32(1);
4861
4862 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(port),
4863 ((u32 *)&stats_flags)[0]);
4864 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(port) + 4,
4865 ((u32 *)&stats_flags)[1]);
4866
4867 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(port),
4868 ((u32 *)&stats_flags)[0]);
4869 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(port) + 4,
4870 ((u32 *)&stats_flags)[1]);
4871
4872 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(port),
4873 ((u32 *)&stats_flags)[0]);
4874 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(port) + 4,
4875 ((u32 *)&stats_flags)[1]);
4876
4877/* DP(NETIF_MSG_IFUP, "stats_flags: 0x%08x 0x%08x\n",
4878 ((u32 *)&stats_flags)[0], ((u32 *)&stats_flags)[1]); */
4879}
4880
4881static void bnx2x_nic_init(struct bnx2x *bp)
4882{
4883 int i;
4884
4885 for_each_queue(bp, i) {
4886 struct bnx2x_fastpath *fp = &bp->fp[i];
4887
4888 fp->state = BNX2X_FP_STATE_CLOSED;
4889 DP(NETIF_MSG_IFUP, "bnx2x_init_sb(%p,%p,%d);\n",
4890 bp, fp->status_blk, i);
4891 fp->index = i;
4892 bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping, i);
4893 }
4894
4895 bnx2x_init_def_sb(bp, bp->def_status_blk,
4896 bp->def_status_blk_mapping, 0x10);
4897 bnx2x_update_coalesce(bp);
4898 bnx2x_init_rx_rings(bp);
4899 bnx2x_init_tx_ring(bp);
4900 bnx2x_init_sp_ring(bp);
4901 bnx2x_init_context(bp);
4902 bnx2x_init_internal(bp);
4903 bnx2x_init_stats(bp);
4904 bnx2x_init_ind_table(bp);
4905 bnx2x_enable_int(bp);
4906
4907}
4908
4909/* end of nic init */
4910
4911/*
4912 * gzip service functions
4913 */
4914
4915static int bnx2x_gunzip_init(struct bnx2x *bp)
4916{
4917 bp->gunzip_buf = pci_alloc_consistent(bp->pdev, FW_BUF_SIZE,
4918 &bp->gunzip_mapping);
4919 if (bp->gunzip_buf == NULL)
4920 goto gunzip_nomem1;
4921
4922 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4923 if (bp->strm == NULL)
4924 goto gunzip_nomem2;
4925
4926 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4927 GFP_KERNEL);
4928 if (bp->strm->workspace == NULL)
4929 goto gunzip_nomem3;
4930
4931 return 0;
4932
4933gunzip_nomem3:
4934 kfree(bp->strm);
4935 bp->strm = NULL;
4936
4937gunzip_nomem2:
4938 pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
4939 bp->gunzip_mapping);
4940 bp->gunzip_buf = NULL;
4941
4942gunzip_nomem1:
4943 printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for"
4944 " uncompression\n", bp->dev->name);
4945 return -ENOMEM;
4946}
4947
4948static void bnx2x_gunzip_end(struct bnx2x *bp)
4949{
4950 kfree(bp->strm->workspace);
4951
4952 kfree(bp->strm);
4953 bp->strm = NULL;
4954
4955 if (bp->gunzip_buf) {
4956 pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
4957 bp->gunzip_mapping);
4958 bp->gunzip_buf = NULL;
4959 }
4960}
4961
4962static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len)
4963{
4964 int n, rc;
4965
4966 /* check gzip header */
4967 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
4968 return -EINVAL;
4969
4970 n = 10;
4971
4972#define FNAME 0x8
4973
4974 if (zbuf[3] & FNAME)
4975 while ((zbuf[n++] != 0) && (n < len));
4976
4977 bp->strm->next_in = zbuf + n;
4978 bp->strm->avail_in = len - n;
4979 bp->strm->next_out = bp->gunzip_buf;
4980 bp->strm->avail_out = FW_BUF_SIZE;
4981
4982 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4983 if (rc != Z_OK)
4984 return rc;
4985
4986 rc = zlib_inflate(bp->strm, Z_FINISH);
4987 if ((rc != Z_OK) && (rc != Z_STREAM_END))
4988 printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
4989 bp->dev->name, bp->strm->msg);
4990
4991 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4992 if (bp->gunzip_outlen & 0x3)
4993 printk(KERN_ERR PFX "%s: Firmware decompression error:"
4994 " gunzip_outlen (%d) not aligned\n",
4995 bp->dev->name, bp->gunzip_outlen);
4996 bp->gunzip_outlen >>= 2;
4997
4998 zlib_inflateEnd(bp->strm);
4999
5000 if (rc == Z_STREAM_END)
5001 return 0;
5002
5003 return rc;
5004}
5005
5006/* nic load/unload */
5007
5008/*
5009 * general service functions
5010 */
5011
5012/* send a NIG loopback debug packet */
5013static void bnx2x_lb_pckt(struct bnx2x *bp)
5014{
5015#ifdef USE_DMAE
5016 u32 wb_write[3];
5017#endif
5018
5019 /* Ethernet source and destination addresses */
5020#ifdef USE_DMAE
5021 wb_write[0] = 0x55555555;
5022 wb_write[1] = 0x55555555;
5023 wb_write[2] = 0x20; /* SOP */
5024 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5025#else
5026 REG_WR_IND(bp, NIG_REG_DEBUG_PACKET_LB, 0x55555555);
5027 REG_WR_IND(bp, NIG_REG_DEBUG_PACKET_LB + 4, 0x55555555);
5028 /* SOP */
5029 REG_WR_IND(bp, NIG_REG_DEBUG_PACKET_LB + 8, 0x20);
5030#endif
5031
5032 /* NON-IP protocol */
5033#ifdef USE_DMAE
5034 wb_write[0] = 0x09000000;
5035 wb_write[1] = 0x55555555;
5036 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5037 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5038#else
5039 REG_WR_IND(bp, NIG_REG_DEBUG_PACKET_LB, 0x09000000);
5040 REG_WR_IND(bp, NIG_REG_DEBUG_PACKET_LB + 4, 0x55555555);
5041 /* EOP, eop_bvalid = 0 */
5042 REG_WR_IND(bp, NIG_REG_DEBUG_PACKET_LB + 8, 0x10);
5043#endif
5044}
5045
5046/* some of the internal memories
5047 * are not directly readable from the driver
5048 * to test them we send debug packets
5049 */
5050static int bnx2x_int_mem_test(struct bnx2x *bp)
5051{
5052 int factor;
5053 int count, i;
5054 u32 val = 0;
5055
5056 switch (CHIP_REV(bp)) {
5057 case CHIP_REV_EMUL:
5058 factor = 200;
5059 break;
5060 case CHIP_REV_FPGA:
5061 factor = 120;
5062 break;
5063 default:
5064 factor = 1;
5065 break;
5066 }
5067
5068 DP(NETIF_MSG_HW, "start part1\n");
5069
5070 /* Disable inputs of parser neighbor blocks */
5071 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5072 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5073 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5074 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x0);
5075
5076 /* Write 0 to parser credits for CFC search request */
5077 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5078
5079 /* send Ethernet packet */
5080 bnx2x_lb_pckt(bp);
5081
5082 /* TODO do i reset NIG statistic? */
5083 /* Wait until NIG register shows 1 packet of size 0x10 */
5084 count = 1000 * factor;
5085 while (count) {
5086#ifdef BNX2X_DMAE_RD
5087 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5088 val = *bnx2x_sp(bp, wb_data[0]);
5089#else
5090 val = REG_RD(bp, NIG_REG_STAT2_BRB_OCTET);
5091 REG_RD(bp, NIG_REG_STAT2_BRB_OCTET + 4);
5092#endif
5093 if (val == 0x10)
5094 break;
5095
5096 msleep(10);
5097 count--;
5098 }
5099 if (val != 0x10) {
5100 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5101 return -1;
5102 }
5103
5104 /* Wait until PRS register shows 1 packet */
5105 count = 1000 * factor;
5106 while (count) {
5107 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5108
5109 if (val == 1)
5110 break;
5111
5112 msleep(10);
5113 count--;
5114 }
5115 if (val != 0x1) {
5116 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5117 return -2;
5118 }
5119
5120 /* Reset and init BRB, PRS */
5121 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x3);
5122 msleep(50);
5123 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x3);
5124 msleep(50);
5125 bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5126 bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5127
5128 DP(NETIF_MSG_HW, "part2\n");
5129
5130 /* Disable inputs of parser neighbor blocks */
5131 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5132 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5133 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5134 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x0);
5135
5136 /* Write 0 to parser credits for CFC search request */
5137 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5138
5139 /* send 10 Ethernet packets */
5140 for (i = 0; i < 10; i++)
5141 bnx2x_lb_pckt(bp);
5142
5143 /* Wait until NIG register shows 10 + 1
5144 packets of size 11*0x10 = 0xb0 */
5145 count = 1000 * factor;
5146 while (count) {
5147#ifdef BNX2X_DMAE_RD
5148 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5149 val = *bnx2x_sp(bp, wb_data[0]);
5150#else
5151 val = REG_RD(bp, NIG_REG_STAT2_BRB_OCTET);
5152 REG_RD(bp, NIG_REG_STAT2_BRB_OCTET + 4);
5153#endif
5154 if (val == 0xb0)
5155 break;
5156
5157 msleep(10);
5158 count--;
5159 }
5160 if (val != 0xb0) {
5161 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5162 return -3;
5163 }
5164
5165 /* Wait until PRS register shows 2 packets */
5166 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5167 if (val != 2)
5168 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5169
5170 /* Write 1 to parser credits for CFC search request */
5171 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5172
5173 /* Wait until PRS register shows 3 packets */
5174 msleep(10 * factor);
5175 /* Wait until NIG register shows 1 packet of size 0x10 */
5176 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5177 if (val != 3)
5178 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5179
5180 /* clear NIG EOP FIFO */
5181 for (i = 0; i < 11; i++)
5182 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5183 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5184 if (val != 1) {
5185 BNX2X_ERR("clear of NIG failed\n");
5186 return -4;
5187 }
5188
5189 /* Reset and init BRB, PRS, NIG */
5190 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5191 msleep(50);
5192 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5193 msleep(50);
5194 bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5195 bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5196#ifndef BCM_ISCSI
5197 /* set NIC mode */
5198 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5199#endif
5200
5201 /* Enable inputs of parser neighbor blocks */
5202 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5203 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5204 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5205 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x1);
5206
5207 DP(NETIF_MSG_HW, "done\n");
5208
5209 return 0; /* OK */
5210}
5211
5212static void enable_blocks_attention(struct bnx2x *bp)
5213{
5214 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5215 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5216 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5217 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5218 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5219 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5220 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5221 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5222 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5223/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5224/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5225 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5226 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5227 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5228/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5229/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5230 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5231 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5232 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5233 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5234/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5235/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5236 REG_WR(bp, PXP2_REG_PXP2_INT_MASK, 0x480000);
5237 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5238 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5239 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5240/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5241/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
5242 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5243 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5244/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5245 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18); /* bit 3,4 masked */
5246}
5247
5248static int bnx2x_function_init(struct bnx2x *bp, int mode)
5249{
5250 int func = bp->port;
5251 int port = func ? PORT1 : PORT0;
5252 u32 val, i;
5253#ifdef USE_DMAE
5254 u32 wb_write[2];
5255#endif
5256
5257 DP(BNX2X_MSG_MCP, "function is %d mode is %x\n", func, mode);
5258 if ((func != 0) && (func != 1)) {
5259 BNX2X_ERR("BAD function number (%d)\n", func);
5260 return -ENODEV;
5261 }
5262
5263 bnx2x_gunzip_init(bp);
5264
5265 if (mode & 0x1) { /* init common */
5266 DP(BNX2X_MSG_MCP, "starting common init func %d mode %x\n",
5267 func, mode);
5268 REG_WR(bp, MISC_REG_RESET_REG_1, 0xffffffff);
5269 REG_WR(bp, MISC_REG_RESET_REG_2, 0xfffc);
5270 bnx2x_init_block(bp, MISC_COMMON_START, MISC_COMMON_END);
5271
5272 REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100);
5273 msleep(30);
5274 REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x0);
5275
5276 bnx2x_init_block(bp, PXP_COMMON_START, PXP_COMMON_END);
5277 bnx2x_init_block(bp, PXP2_COMMON_START, PXP2_COMMON_END);
5278
5279 bnx2x_init_pxp(bp);
5280
5281 if (CHIP_REV(bp) == CHIP_REV_Ax) {
5282 /* enable HW interrupt from PXP on USDM
5283 overflow bit 16 on INT_MASK_0 */
5284 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5285 }
5286
5287#ifdef __BIG_ENDIAN
5288 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5289 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5290 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5291 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5292 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5293 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 1);
5294
5295/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5296 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5297 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5298 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5299 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5300#endif
5301
5302#ifndef BCM_ISCSI
5303 /* set NIC mode */
5304 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5305#endif
5306
5307 REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 5);
5308#ifdef BCM_ISCSI
5309 REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5);
5310 REG_WR(bp, PXP2_REG_RQ_QM_P_SIZE, 5);
5311 REG_WR(bp, PXP2_REG_RQ_SRC_P_SIZE, 5);
5312#endif
5313
5314 bnx2x_init_block(bp, DMAE_COMMON_START, DMAE_COMMON_END);
5315
5316 /* let the HW do it's magic ... */
5317 msleep(100);
5318 /* finish PXP init
5319 (can be moved up if we want to use the DMAE) */
5320 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5321 if (val != 1) {
5322 BNX2X_ERR("PXP2 CFG failed\n");
5323 return -EBUSY;
5324 }
5325
5326 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5327 if (val != 1) {
5328 BNX2X_ERR("PXP2 RD_INIT failed\n");
5329 return -EBUSY;
5330 }
5331
5332 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5333 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5334
5335 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
5336
5337 bnx2x_init_block(bp, TCM_COMMON_START, TCM_COMMON_END);
5338 bnx2x_init_block(bp, UCM_COMMON_START, UCM_COMMON_END);
5339 bnx2x_init_block(bp, CCM_COMMON_START, CCM_COMMON_END);
5340 bnx2x_init_block(bp, XCM_COMMON_START, XCM_COMMON_END);
5341
5342#ifdef BNX2X_DMAE_RD
5343 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5344 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5345 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5346 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5347#else
5348 REG_RD(bp, XSEM_REG_PASSIVE_BUFFER);
5349 REG_RD(bp, XSEM_REG_PASSIVE_BUFFER + 4);
5350 REG_RD(bp, XSEM_REG_PASSIVE_BUFFER + 8);
5351 REG_RD(bp, CSEM_REG_PASSIVE_BUFFER);
5352 REG_RD(bp, CSEM_REG_PASSIVE_BUFFER + 4);
5353 REG_RD(bp, CSEM_REG_PASSIVE_BUFFER + 8);
5354 REG_RD(bp, TSEM_REG_PASSIVE_BUFFER);
5355 REG_RD(bp, TSEM_REG_PASSIVE_BUFFER + 4);
5356 REG_RD(bp, TSEM_REG_PASSIVE_BUFFER + 8);
5357 REG_RD(bp, USEM_REG_PASSIVE_BUFFER);
5358 REG_RD(bp, USEM_REG_PASSIVE_BUFFER + 4);
5359 REG_RD(bp, USEM_REG_PASSIVE_BUFFER + 8);
5360#endif
5361 bnx2x_init_block(bp, QM_COMMON_START, QM_COMMON_END);
5362 /* softrest pulse */
5363 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5364 REG_WR(bp, QM_REG_SOFT_RESET, 0);
5365
5366#ifdef BCM_ISCSI
5367 bnx2x_init_block(bp, TIMERS_COMMON_START, TIMERS_COMMON_END);
5368#endif
5369 bnx2x_init_block(bp, DQ_COMMON_START, DQ_COMMON_END);
5370 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BCM_PAGE_BITS);
5371 if (CHIP_REV(bp) == CHIP_REV_Ax) {
5372 /* enable hw interrupt from doorbell Q */
5373 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5374 }
5375
5376 bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5377
5378 if (CHIP_REV_IS_SLOW(bp)) {
5379 /* fix for emulation and FPGA for no pause */
5380 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 513);
5381 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 513);
5382 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0);
5383 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0);
5384 }
5385
5386 bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5387
5388 bnx2x_init_block(bp, TSDM_COMMON_START, TSDM_COMMON_END);
5389 bnx2x_init_block(bp, CSDM_COMMON_START, CSDM_COMMON_END);
5390 bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END);
5391 bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END);
5392
5393 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE);
5394 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE);
5395 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE);
5396 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE);
5397
5398 bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END);
5399 bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END);
5400 bnx2x_init_block(bp, CSEM_COMMON_START, CSEM_COMMON_END);
5401 bnx2x_init_block(bp, XSEM_COMMON_START, XSEM_COMMON_END);
5402
5403 /* sync semi rtc */
5404 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5405 0x80000000);
5406 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5407 0x80000000);
5408
5409 bnx2x_init_block(bp, UPB_COMMON_START, UPB_COMMON_END);
5410 bnx2x_init_block(bp, XPB_COMMON_START, XPB_COMMON_END);
5411 bnx2x_init_block(bp, PBF_COMMON_START, PBF_COMMON_END);
5412
5413 REG_WR(bp, SRC_REG_SOFT_RST, 1);
5414 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) {
5415 REG_WR(bp, i, 0xc0cac01a);
5416 /* TODO: repleace with something meaningfull */
5417 }
5418 /* SRCH COMMON comes here */
5419 REG_WR(bp, SRC_REG_SOFT_RST, 0);
5420
5421 if (sizeof(union cdu_context) != 1024) {
5422 /* we currently assume that a context is 1024 bytes */
5423 printk(KERN_ALERT PFX "please adjust the size of"
5424 " cdu_context(%ld)\n",
5425 (long)sizeof(union cdu_context));
5426 }
5427 val = (4 << 24) + (0 << 12) + 1024;
5428 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5429 bnx2x_init_block(bp, CDU_COMMON_START, CDU_COMMON_END);
5430
5431 bnx2x_init_block(bp, CFC_COMMON_START, CFC_COMMON_END);
5432 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
5433
5434 bnx2x_init_block(bp, HC_COMMON_START, HC_COMMON_END);
5435 bnx2x_init_block(bp, MISC_AEU_COMMON_START,
5436 MISC_AEU_COMMON_END);
5437 /* RXPCS COMMON comes here */
5438 /* EMAC0 COMMON comes here */
5439 /* EMAC1 COMMON comes here */
5440 /* DBU COMMON comes here */
5441 /* DBG COMMON comes here */
5442 bnx2x_init_block(bp, NIG_COMMON_START, NIG_COMMON_END);
5443
5444 if (CHIP_REV_IS_SLOW(bp))
5445 msleep(200);
5446
5447 /* finish CFC init */
5448 val = REG_RD(bp, CFC_REG_LL_INIT_DONE);
5449 if (val != 1) {
5450 BNX2X_ERR("CFC LL_INIT failed\n");
5451 return -EBUSY;
5452 }
5453
5454 val = REG_RD(bp, CFC_REG_AC_INIT_DONE);
5455 if (val != 1) {
5456 BNX2X_ERR("CFC AC_INIT failed\n");
5457 return -EBUSY;
5458 }
5459
5460 val = REG_RD(bp, CFC_REG_CAM_INIT_DONE);
5461 if (val != 1) {
5462 BNX2X_ERR("CFC CAM_INIT failed\n");
5463 return -EBUSY;
5464 }
5465
5466 REG_WR(bp, CFC_REG_DEBUG0, 0);
5467
5468 /* read NIG statistic
5469 to see if this is our first up since powerup */
5470#ifdef BNX2X_DMAE_RD
5471 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5472 val = *bnx2x_sp(bp, wb_data[0]);
5473#else
5474 val = REG_RD(bp, NIG_REG_STAT2_BRB_OCTET);
5475 REG_RD(bp, NIG_REG_STAT2_BRB_OCTET + 4);
5476#endif
5477 /* do internal memory self test */
5478 if ((val == 0) && bnx2x_int_mem_test(bp)) {
5479 BNX2X_ERR("internal mem selftest failed\n");
5480 return -EBUSY;
5481 }
5482
5483 /* clear PXP2 attentions */
5484 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR);
5485
5486 enable_blocks_attention(bp);
5487 /* enable_blocks_parity(bp); */
5488
5489 } /* end of common init */
5490
5491 /* per port init */
5492
5493 /* the phys address is shifted right 12 bits and has an added
5494 1=valid bit added to the 53rd bit
5495 then since this is a wide register(TM)
5496 we split it into two 32 bit writes
5497 */
5498#define RQ_ONCHIP_AT_PORT_SIZE 384
5499#define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
5500#define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
5501#define PXP_ONE_ILT(x) ((x << 10) | x)
5502
5503 DP(BNX2X_MSG_MCP, "starting per-function init port is %x\n", func);
5504
5505 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + func*4, 0);
5506
5507 /* Port PXP comes here */
5508 /* Port PXP2 comes here */
5509
5510 /* Offset is
5511 * Port0 0
5512 * Port1 384 */
5513 i = func * RQ_ONCHIP_AT_PORT_SIZE;
5514#ifdef USE_DMAE
5515 wb_write[0] = ONCHIP_ADDR1(bnx2x_sp_mapping(bp, context));
5516 wb_write[1] = ONCHIP_ADDR2(bnx2x_sp_mapping(bp, context));
5517 REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5518#else
5519 REG_WR_IND(bp, PXP2_REG_RQ_ONCHIP_AT + i*8,
5520 ONCHIP_ADDR1(bnx2x_sp_mapping(bp, context)));
5521 REG_WR_IND(bp, PXP2_REG_RQ_ONCHIP_AT + i*8 + 4,
5522 ONCHIP_ADDR2(bnx2x_sp_mapping(bp, context)));
5523#endif
5524 REG_WR(bp, PXP2_REG_PSWRQ_CDU0_L2P + func*4, PXP_ONE_ILT(i));
5525
5526#ifdef BCM_ISCSI
5527 /* Port0 1
5528 * Port1 385 */
5529 i++;
5530 wb_write[0] = ONCHIP_ADDR1(bp->timers_mapping);
5531 wb_write[1] = ONCHIP_ADDR2(bp->timers_mapping);
5532 REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5533 REG_WR(bp, PXP2_REG_PSWRQ_TM0_L2P + func*4, PXP_ONE_ILT(i));
5534
5535 /* Port0 2
5536 * Port1 386 */
5537 i++;
5538 wb_write[0] = ONCHIP_ADDR1(bp->qm_mapping);
5539 wb_write[1] = ONCHIP_ADDR2(bp->qm_mapping);
5540 REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5541 REG_WR(bp, PXP2_REG_PSWRQ_QM0_L2P + func*4, PXP_ONE_ILT(i));
5542
5543 /* Port0 3
5544 * Port1 387 */
5545 i++;
5546 wb_write[0] = ONCHIP_ADDR1(bp->t1_mapping);
5547 wb_write[1] = ONCHIP_ADDR2(bp->t1_mapping);
5548 REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5549 REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i));
5550#endif
5551
5552 /* Port TCM comes here */
5553 /* Port UCM comes here */
5554 /* Port CCM comes here */
5555 bnx2x_init_block(bp, func ? XCM_PORT1_START : XCM_PORT0_START,
5556 func ? XCM_PORT1_END : XCM_PORT0_END);
5557
5558#ifdef USE_DMAE
5559 wb_write[0] = 0;
5560 wb_write[1] = 0;
5561#endif
5562 for (i = 0; i < 32; i++) {
5563 REG_WR(bp, QM_REG_BASEADDR + (func*32 + i)*4, 1024 * 4 * i);
5564#ifdef USE_DMAE
5565 REG_WR_DMAE(bp, QM_REG_PTRTBL + (func*32 + i)*8, wb_write, 2);
5566#else
5567 REG_WR_IND(bp, QM_REG_PTRTBL + (func*32 + i)*8, 0);
5568 REG_WR_IND(bp, QM_REG_PTRTBL + (func*32 + i)*8 + 4, 0);
5569#endif
5570 }
5571 REG_WR(bp, QM_REG_CONNNUM_0 + func*4, 1024/16 - 1);
5572
5573 /* Port QM comes here */
5574
5575#ifdef BCM_ISCSI
5576 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + func*4, 1024/64*20);
5577 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + func*4, 31);
5578
5579 bnx2x_init_block(bp, func ? TIMERS_PORT1_START : TIMERS_PORT0_START,
5580 func ? TIMERS_PORT1_END : TIMERS_PORT0_END);
5581#endif
5582 /* Port DQ comes here */
5583 /* Port BRB1 comes here */
5584 bnx2x_init_block(bp, func ? PRS_PORT1_START : PRS_PORT0_START,
5585 func ? PRS_PORT1_END : PRS_PORT0_END);
5586 /* Port TSDM comes here */
5587 /* Port CSDM comes here */
5588 /* Port USDM comes here */
5589 /* Port XSDM comes here */
5590 bnx2x_init_block(bp, func ? TSEM_PORT1_START : TSEM_PORT0_START,
5591 func ? TSEM_PORT1_END : TSEM_PORT0_END);
5592 bnx2x_init_block(bp, func ? USEM_PORT1_START : USEM_PORT0_START,
5593 func ? USEM_PORT1_END : USEM_PORT0_END);
5594 bnx2x_init_block(bp, func ? CSEM_PORT1_START : CSEM_PORT0_START,
5595 func ? CSEM_PORT1_END : CSEM_PORT0_END);
5596 bnx2x_init_block(bp, func ? XSEM_PORT1_START : XSEM_PORT0_START,
5597 func ? XSEM_PORT1_END : XSEM_PORT0_END);
5598 /* Port UPB comes here */
5599 /* Port XSDM comes here */
5600 bnx2x_init_block(bp, func ? PBF_PORT1_START : PBF_PORT0_START,
5601 func ? PBF_PORT1_END : PBF_PORT0_END);
5602
5603 /* configure PBF to work without PAUSE mtu 9000 */
5604 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + func*4, 0);
5605
5606 /* update threshold */
5607 REG_WR(bp, PBF_REG_P0_ARB_THRSH + func*4, (9040/16));
5608 /* update init credit */
5609 REG_WR(bp, PBF_REG_P0_INIT_CRD + func*4, (9040/16) + 553 - 22);
5610
5611 /* probe changes */
5612 REG_WR(bp, PBF_REG_INIT_P0 + func*4, 1);
5613 msleep(5);
5614 REG_WR(bp, PBF_REG_INIT_P0 + func*4, 0);
5615
5616#ifdef BCM_ISCSI
5617 /* tell the searcher where the T2 table is */
5618 REG_WR(bp, SRC_REG_COUNTFREE0 + func*4, 16*1024/64);
5619
5620 wb_write[0] = U64_LO(bp->t2_mapping);
5621 wb_write[1] = U64_HI(bp->t2_mapping);
5622 REG_WR_DMAE(bp, SRC_REG_FIRSTFREE0 + func*4, wb_write, 2);
5623 wb_write[0] = U64_LO((u64)bp->t2_mapping + 16*1024 - 64);
5624 wb_write[1] = U64_HI((u64)bp->t2_mapping + 16*1024 - 64);
5625 REG_WR_DMAE(bp, SRC_REG_LASTFREE0 + func*4, wb_write, 2);
5626
5627 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + func*4, 10);
5628 /* Port SRCH comes here */
5629#endif
5630 /* Port CDU comes here */
5631 /* Port CFC comes here */
5632 bnx2x_init_block(bp, func ? HC_PORT1_START : HC_PORT0_START,
5633 func ? HC_PORT1_END : HC_PORT0_END);
5634 bnx2x_init_block(bp, func ? MISC_AEU_PORT1_START :
5635 MISC_AEU_PORT0_START,
5636 func ? MISC_AEU_PORT1_END : MISC_AEU_PORT0_END);
5637 /* Port PXPCS comes here */
5638 /* Port EMAC0 comes here */
5639 /* Port EMAC1 comes here */
5640 /* Port DBU comes here */
5641 /* Port DBG comes here */
5642 bnx2x_init_block(bp, func ? NIG_PORT1_START : NIG_PORT0_START,
5643 func ? NIG_PORT1_END : NIG_PORT0_END);
5644 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + func*4, 1);
5645 /* Port MCP comes here */
5646 /* Port DMAE comes here */
5647
5648 bnx2x_link_reset(bp);
5649
5650 /* Reset pciex errors for debug */
5651 REG_WR(bp, 0x2114, 0xffffffff);
5652 REG_WR(bp, 0x2120, 0xffffffff);
5653 REG_WR(bp, 0x2814, 0xffffffff);
5654
5655 /* !!! move to init_values.h */
5656 REG_WR(bp, XSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1);
5657 REG_WR(bp, USDM_REG_INIT_CREDIT_PXP_CTRL, 0x1);
5658 REG_WR(bp, CSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1);
5659 REG_WR(bp, TSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1);
5660
5661 REG_WR(bp, DBG_REG_PCI_REQ_CREDIT, 0x1);
5662 REG_WR(bp, TM_REG_PCIARB_CRDCNT_VAL, 0x1);
5663 REG_WR(bp, CDU_REG_CDU_DEBUG, 0x264);
5664 REG_WR(bp, CDU_REG_CDU_DEBUG, 0x0);
5665
5666 bnx2x_gunzip_end(bp);
5667
5668 if (!nomcp) {
5669 port = bp->port;
5670
5671 bp->fw_drv_pulse_wr_seq =
5672 (SHMEM_RD(bp, drv_fw_mb[port].drv_pulse_mb) &
5673 DRV_PULSE_SEQ_MASK);
5674 bp->fw_mb = SHMEM_RD(bp, drv_fw_mb[port].fw_mb_param);
5675 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x fw_mb 0x%x\n",
5676 bp->fw_drv_pulse_wr_seq, bp->fw_mb);
5677 } else {
5678 bp->fw_mb = 0;
5679 }
5680
5681 return 0;
5682}
5683
5684
5685/* send the MCP a request, block untill there is a reply */
5686static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
5687{
5688 u32 rc = 0;
5689 u32 seq = ++bp->fw_seq;
5690 int port = bp->port;
5691
5692 SHMEM_WR(bp, drv_fw_mb[port].drv_mb_header, command|seq);
5693 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", command|seq);
5694
5695 /* let the FW do it's magic ... */
5696 msleep(100); /* TBD */
5697
5698 if (CHIP_REV_IS_SLOW(bp))
5699 msleep(900);
5700
5701 rc = SHMEM_RD(bp, drv_fw_mb[port].fw_mb_header);
5702
5703 DP(BNX2X_MSG_MCP, "read (%x) seq is (%x) from FW MB\n", rc, seq);
5704
5705 /* is this a reply to our command? */
5706 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
5707 rc &= FW_MSG_CODE_MASK;
5708 } else {
5709 /* FW BUG! */
5710 BNX2X_ERR("FW failed to respond!\n");
5711 bnx2x_fw_dump(bp);
5712 rc = 0;
5713 }
5714 return rc;
5715}
5716
5717static void bnx2x_free_mem(struct bnx2x *bp)
5718{
5719
5720#define BNX2X_PCI_FREE(x, y, size) \
5721 do { \
5722 if (x) { \
5723 pci_free_consistent(bp->pdev, size, x, y); \
5724 x = NULL; \
5725 y = 0; \
5726 } \
5727 } while (0)
5728
5729#define BNX2X_FREE(x) \
5730 do { \
5731 if (x) { \
5732 vfree(x); \
5733 x = NULL; \
5734 } \
5735 } while (0)
5736
5737 int i;
5738
5739 /* fastpath */
5740 for_each_queue(bp, i) {
5741
5742 /* Status blocks */
5743 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk),
5744 bnx2x_fp(bp, i, status_blk_mapping),
5745 sizeof(struct host_status_block) +
5746 sizeof(struct eth_tx_db_data));
5747
5748 /* fast path rings: tx_buf tx_desc rx_buf rx_desc rx_comp */
5749 BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
5750 BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
5751 bnx2x_fp(bp, i, tx_desc_mapping),
5752 sizeof(struct eth_tx_bd) * NUM_TX_BD);
5753
5754 BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));
5755 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),
5756 bnx2x_fp(bp, i, rx_desc_mapping),
5757 sizeof(struct eth_rx_bd) * NUM_RX_BD);
5758
5759 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),
5760 bnx2x_fp(bp, i, rx_comp_mapping),
5761 sizeof(struct eth_fast_path_rx_cqe) *
5762 NUM_RCQ_BD);
5763 }
5764
5765 BNX2X_FREE(bp->fp);
5766
5767 /* end of fastpath */
5768
5769 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
5770 (sizeof(struct host_def_status_block)));
5771
5772 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
5773 (sizeof(struct bnx2x_slowpath)));
5774
5775#ifdef BCM_ISCSI
5776 BNX2X_PCI_FREE(bp->t1, bp->t1_mapping, 64*1024);
5777 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, 16*1024);
5778 BNX2X_PCI_FREE(bp->timers, bp->timers_mapping, 8*1024);
5779 BNX2X_PCI_FREE(bp->qm, bp->qm_mapping, 128*1024);
5780#endif
5781 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, PAGE_SIZE);
5782
5783#undef BNX2X_PCI_FREE
5784#undef BNX2X_KFREE
5785}
5786
5787static int bnx2x_alloc_mem(struct bnx2x *bp)
5788{
5789
5790#define BNX2X_PCI_ALLOC(x, y, size) \
5791 do { \
5792 x = pci_alloc_consistent(bp->pdev, size, y); \
5793 if (x == NULL) \
5794 goto alloc_mem_err; \
5795 memset(x, 0, size); \
5796 } while (0)
5797
5798#define BNX2X_ALLOC(x, size) \
5799 do { \
5800 x = vmalloc(size); \
5801 if (x == NULL) \
5802 goto alloc_mem_err; \
5803 memset(x, 0, size); \
5804 } while (0)
5805
5806 int i;
5807
5808 /* fastpath */
5809 BNX2X_ALLOC(bp->fp, sizeof(struct bnx2x_fastpath) * bp->num_queues);
5810
5811 for_each_queue(bp, i) {
5812 bnx2x_fp(bp, i, bp) = bp;
5813
5814 /* Status blocks */
5815 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, status_blk),
5816 &bnx2x_fp(bp, i, status_blk_mapping),
5817 sizeof(struct host_status_block) +
5818 sizeof(struct eth_tx_db_data));
5819
5820 bnx2x_fp(bp, i, hw_tx_prods) =
5821 (void *)(bnx2x_fp(bp, i, status_blk) + 1);
5822
5823 bnx2x_fp(bp, i, tx_prods_mapping) =
5824 bnx2x_fp(bp, i, status_blk_mapping) +
5825 sizeof(struct host_status_block);
5826
5827 /* fast path rings: tx_buf tx_desc rx_buf rx_desc rx_comp */
5828 BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
5829 sizeof(struct sw_tx_bd) * NUM_TX_BD);
5830 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
5831 &bnx2x_fp(bp, i, tx_desc_mapping),
5832 sizeof(struct eth_tx_bd) * NUM_TX_BD);
5833
5834 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),
5835 sizeof(struct sw_rx_bd) * NUM_RX_BD);
5836 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),
5837 &bnx2x_fp(bp, i, rx_desc_mapping),
5838 sizeof(struct eth_rx_bd) * NUM_RX_BD);
5839
5840 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),
5841 &bnx2x_fp(bp, i, rx_comp_mapping),
5842 sizeof(struct eth_fast_path_rx_cqe) *
5843 NUM_RCQ_BD);
5844
5845 }
5846 /* end of fastpath */
5847
5848 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
5849 sizeof(struct host_def_status_block));
5850
5851 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
5852 sizeof(struct bnx2x_slowpath));
5853
5854#ifdef BCM_ISCSI
5855 BNX2X_PCI_ALLOC(bp->t1, &bp->t1_mapping, 64*1024);
5856
5857 /* Initialize T1 */
5858 for (i = 0; i < 64*1024; i += 64) {
5859 *(u64 *)((char *)bp->t1 + i + 56) = 0x0UL;
5860 *(u64 *)((char *)bp->t1 + i + 3) = 0x0UL;
5861 }
5862
5863 /* allocate searcher T2 table
5864 we allocate 1/4 of alloc num for T2
5865 (which is not entered into the ILT) */
5866 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, 16*1024);
5867
5868 /* Initialize T2 */
5869 for (i = 0; i < 16*1024; i += 64)
5870 * (u64 *)((char *)bp->t2 + i + 56) = bp->t2_mapping + i + 64;
5871
5872 /* now sixup the last line in the block to point to the next block */
5873 *(u64 *)((char *)bp->t2 + 1024*16-8) = bp->t2_mapping;
5874
5875 /* Timer block array (MAX_CONN*8) phys uncached for now 1024 conns */
5876 BNX2X_PCI_ALLOC(bp->timers, &bp->timers_mapping, 8*1024);
5877
5878 /* QM queues (128*MAX_CONN) */
5879 BNX2X_PCI_ALLOC(bp->qm, &bp->qm_mapping, 128*1024);
5880#endif
5881
5882 /* Slow path ring */
5883 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
5884
5885 return 0;
5886
5887alloc_mem_err:
5888 bnx2x_free_mem(bp);
5889 return -ENOMEM;
5890
5891#undef BNX2X_PCI_ALLOC
5892#undef BNX2X_ALLOC
5893}
5894
5895static void bnx2x_free_tx_skbs(struct bnx2x *bp)
5896{
5897 int i;
5898
5899 for_each_queue(bp, i) {
5900 struct bnx2x_fastpath *fp = &bp->fp[i];
5901
5902 u16 bd_cons = fp->tx_bd_cons;
5903 u16 sw_prod = fp->tx_pkt_prod;
5904 u16 sw_cons = fp->tx_pkt_cons;
5905
5906 BUG_TRAP(fp->tx_buf_ring != NULL);
5907
5908 while (sw_cons != sw_prod) {
5909 bd_cons = bnx2x_free_tx_pkt(bp, fp, TX_BD(sw_cons));
5910 sw_cons++;
5911 }
5912 }
5913}
5914
5915static void bnx2x_free_rx_skbs(struct bnx2x *bp)
5916{
5917 int i, j;
5918
5919 for_each_queue(bp, j) {
5920 struct bnx2x_fastpath *fp = &bp->fp[j];
5921
5922 BUG_TRAP(fp->rx_buf_ring != NULL);
5923
5924 for (i = 0; i < NUM_RX_BD; i++) {
5925 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
5926 struct sk_buff *skb = rx_buf->skb;
5927
5928 if (skb == NULL)
5929 continue;
5930
5931 pci_unmap_single(bp->pdev,
5932 pci_unmap_addr(rx_buf, mapping),
5933 bp->rx_buf_use_size,
5934 PCI_DMA_FROMDEVICE);
5935
5936 rx_buf->skb = NULL;
5937 dev_kfree_skb(skb);
5938 }
5939 }
5940}
5941
5942static void bnx2x_free_skbs(struct bnx2x *bp)
5943{
5944 bnx2x_free_tx_skbs(bp);
5945 bnx2x_free_rx_skbs(bp);
5946}
5947
5948static void bnx2x_free_msix_irqs(struct bnx2x *bp)
5949{
5950 int i;
5951
5952 free_irq(bp->msix_table[0].vector, bp->dev);
5953 DP(NETIF_MSG_IFDOWN, "rleased sp irq (%d)\n",
5954 bp->msix_table[0].vector);
5955
5956 for_each_queue(bp, i) {
5957 DP(NETIF_MSG_IFDOWN, "about to rlease fp #%d->%d irq "
5958 "state(%x)\n", i, bp->msix_table[i + 1].vector,
5959 bnx2x_fp(bp, i, state));
5960
5961 if (bnx2x_fp(bp, i, state) != BNX2X_FP_STATE_CLOSED) {
5962
5963 free_irq(bp->msix_table[i + 1].vector, &bp->fp[i]);
5964 bnx2x_fp(bp, i, state) = BNX2X_FP_STATE_CLOSED;
5965
5966 } else
5967 DP(NETIF_MSG_IFDOWN, "irq not freed\n");
5968
5969 }
5970
5971}
5972
5973static void bnx2x_free_irq(struct bnx2x *bp)
5974{
5975
5976 if (bp->flags & USING_MSIX_FLAG) {
5977
5978 bnx2x_free_msix_irqs(bp);
5979 pci_disable_msix(bp->pdev);
5980
5981 bp->flags &= ~USING_MSIX_FLAG;
5982
5983 } else
5984 free_irq(bp->pdev->irq, bp->dev);
5985}
5986
5987static int bnx2x_enable_msix(struct bnx2x *bp)
5988{
5989
5990 int i;
5991
5992 bp->msix_table[0].entry = 0;
5993 for_each_queue(bp, i)
5994 bp->msix_table[i + 1].entry = i + 1;
5995
5996 if (pci_enable_msix(bp->pdev, &bp->msix_table[0],
5997 bp->num_queues + 1)){
5998 BNX2X_ERR("failed to enable msix\n");
5999 return -1;
6000
6001 }
6002
6003 bp->flags |= USING_MSIX_FLAG;
6004
6005 return 0;
6006
6007}
6008
6009
6010static int bnx2x_req_msix_irqs(struct bnx2x *bp)
6011{
6012
6013
6014 int i, rc;
6015
6016 DP(NETIF_MSG_IFUP, "about to request sp irq\n");
6017
6018 rc = request_irq(bp->msix_table[0].vector, bnx2x_msix_sp_int, 0,
6019 bp->dev->name, bp->dev);
6020
6021 if (rc) {
6022 BNX2X_ERR("request sp irq failed\n");
6023 return -EBUSY;
6024 }
6025
6026 for_each_queue(bp, i) {
6027 rc = request_irq(bp->msix_table[i + 1].vector,
6028 bnx2x_msix_fp_int, 0,
6029 bp->dev->name, &bp->fp[i]);
6030
6031 if (rc) {
6032 BNX2X_ERR("request fp #%d irq failed\n", i);
6033 bnx2x_free_msix_irqs(bp);
6034 return -EBUSY;
6035 }
6036
6037 bnx2x_fp(bp, i, state) = BNX2X_FP_STATE_IRQ;
6038
6039 }
6040
6041 return 0;
6042
6043}
6044
6045static int bnx2x_req_irq(struct bnx2x *bp)
6046{
6047
6048 int rc = request_irq(bp->pdev->irq, bnx2x_interrupt,
6049 IRQF_SHARED, bp->dev->name, bp->dev);
6050 if (!rc)
6051 bnx2x_fp(bp, 0, state) = BNX2X_FP_STATE_IRQ;
6052
6053 return rc;
6054
6055}
6056
6057/*
6058 * Init service functions
6059 */
6060
6061static void bnx2x_set_mac_addr(struct bnx2x *bp)
6062{
6063 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
6064
6065 /* CAM allocation
6066 * unicasts 0-31:port0 32-63:port1
6067 * multicast 64-127:port0 128-191:port1
6068 */
6069 config->hdr.length_6b = 2;
6070 config->hdr.offset = bp->port ? 31 : 0;
6071 config->hdr.reserved0 = 0;
6072 config->hdr.reserved1 = 0;
6073
6074 /* primary MAC */
6075 config->config_table[0].cam_entry.msb_mac_addr =
6076 swab16(*(u16 *)&bp->dev->dev_addr[0]);
6077 config->config_table[0].cam_entry.middle_mac_addr =
6078 swab16(*(u16 *)&bp->dev->dev_addr[2]);
6079 config->config_table[0].cam_entry.lsb_mac_addr =
6080 swab16(*(u16 *)&bp->dev->dev_addr[4]);
6081 config->config_table[0].cam_entry.flags = cpu_to_le16(bp->port);
6082 config->config_table[0].target_table_entry.flags = 0;
6083 config->config_table[0].target_table_entry.client_id = 0;
6084 config->config_table[0].target_table_entry.vlan_id = 0;
6085
6086 DP(NETIF_MSG_IFUP, "setting MAC (%04x:%04x:%04x)\n",
6087 config->config_table[0].cam_entry.msb_mac_addr,
6088 config->config_table[0].cam_entry.middle_mac_addr,
6089 config->config_table[0].cam_entry.lsb_mac_addr);
6090
6091 /* broadcast */
6092 config->config_table[1].cam_entry.msb_mac_addr = 0xffff;
6093 config->config_table[1].cam_entry.middle_mac_addr = 0xffff;
6094 config->config_table[1].cam_entry.lsb_mac_addr = 0xffff;
6095 config->config_table[1].cam_entry.flags = cpu_to_le16(bp->port);
6096 config->config_table[1].target_table_entry.flags =
6097 TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST;
6098 config->config_table[1].target_table_entry.client_id = 0;
6099 config->config_table[1].target_table_entry.vlan_id = 0;
6100
6101 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
6102 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
6103 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
6104}
6105
6106static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6107 int *state_p, int poll)
6108{
6109 /* can take a while if any port is running */
6110 int timeout = 500;
6111
6112 /* DP("waiting for state to become %d on IDX [%d]\n",
6113 state, sb_idx); */
6114
6115 might_sleep();
6116
6117 while (timeout) {
6118
6119 if (poll) {
6120 bnx2x_rx_int(bp->fp, 10);
6121 /* If index is different from 0
6122 * The reply for some commands will
6123 * be on the none default queue
6124 */
6125 if (idx)
6126 bnx2x_rx_int(&bp->fp[idx], 10);
6127 }
6128
6129 mb(); /* state is changed by bnx2x_sp_event()*/
6130
6131 if (*state_p != state)
6132 return 0;
6133
6134 timeout--;
6135 msleep(1);
6136
6137 }
6138
6139
6140 /* timeout! */
6141 BNX2X_ERR("timeout waiting for ramrod %d on %d\n", state, idx);
6142 return -EBUSY;
6143
6144}
6145
6146static int bnx2x_setup_leading(struct bnx2x *bp)
6147{
6148
6149 /* reset IGU staae */
6150 bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
6151
6152 /* SETUP ramrod */
6153 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_SETUP, 0, 0, 0, 0);
6154
6155 return bnx2x_wait_ramrod(bp, BNX2X_STATE_OPEN, 0, &(bp->state), 0);
6156
6157}
6158
6159static int bnx2x_setup_multi(struct bnx2x *bp, int index)
6160{
6161
6162 /* reset IGU state */
6163 bnx2x_ack_sb(bp, index, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
6164
6165 bp->fp[index].state = BNX2X_FP_STATE_OPENING;
6166 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_SETUP, index, 0, index, 0);
6167
6168 /* Wait for completion */
6169 return bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_OPEN, index,
6170 &(bp->fp[index].state), 1);
6171
6172}
6173
6174
6175static int bnx2x_poll(struct napi_struct *napi, int budget);
6176static void bnx2x_set_rx_mode(struct net_device *dev);
6177
6178static int bnx2x_nic_load(struct bnx2x *bp, int req_irq)
6179{
6180 int rc;
6181 int i = 0;
6182
6183 bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
6184
6185 /* Send LOAD_REQUEST command to MCP.
6186 Returns the type of LOAD command: if it is the
6187 first port to be initialized common blocks should be
6188 initialized, otherwise - not.
6189 */
6190 if (!nomcp) {
6191 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ);
6192 if (rc == FW_MSG_CODE_DRV_LOAD_REFUSED) {
6193 return -EBUSY; /* other port in diagnostic mode */
6194 }
6195 } else {
6196 rc = FW_MSG_CODE_DRV_LOAD_COMMON;
6197 }
6198
6199 DP(NETIF_MSG_IFUP, "set number of queues to %d\n", bp->num_queues);
6200
6201 /* if we can't use msix we only need one fp,
6202 * so try to enable msix with the requested number of fp's
6203 * and fallback to inta with one fp
6204 */
6205 if (req_irq) {
6206
6207 if (use_inta) {
6208 bp->num_queues = 1;
6209 } else {
6210 if (use_multi > 1 && use_multi <= 16)
6211 /* user requested number */
6212 bp->num_queues = use_multi;
6213 else if (use_multi == 1)
6214 bp->num_queues = num_online_cpus();
6215 else
6216 bp->num_queues = 1;
6217
6218 if (bnx2x_enable_msix(bp)) {
6219 /* faild to enable msix */
6220 bp->num_queues = 1;
6221 if (use_multi)
6222 BNX2X_ERR("Muti requested but failed"
6223 " to enable MSI-X\n");
6224 }
6225 }
6226 }
6227
6228 if (bnx2x_alloc_mem(bp))
6229 return -ENOMEM;
6230
6231 if (req_irq) {
6232 if (bp->flags & USING_MSIX_FLAG) {
6233 if (bnx2x_req_msix_irqs(bp)) {
6234 pci_disable_msix(bp->pdev);
6235 goto out_error;
6236 }
6237
6238 } else {
6239 if (bnx2x_req_irq(bp)) {
6240 BNX2X_ERR("IRQ request failed, aborting\n");
6241 goto out_error;
6242 }
6243 }
6244 }
6245
6246 for_each_queue(bp, i)
6247 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
6248 bnx2x_poll, 128);
6249
6250
6251 /* Initialize HW */
6252 if (bnx2x_function_init(bp, (rc == FW_MSG_CODE_DRV_LOAD_COMMON))) {
6253 BNX2X_ERR("HW init failed, aborting\n");
6254 goto out_error;
6255 }
6256
6257
6258 atomic_set(&bp->intr_sem, 0);
6259
6260 /* Reenable SP tasklet */
6261 /*if (bp->sp_task_en) { */
6262 /* tasklet_enable(&bp->sp_task);*/
6263 /*} else { */
6264 /* bp->sp_task_en = 1; */
6265 /*} */
6266
6267 /* Setup NIC internals and enable interrupts */
6268 bnx2x_nic_init(bp);
6269
6270 /* Send LOAD_DONE command to MCP */
6271 if (!nomcp) {
6272 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE);
6273 DP(NETIF_MSG_IFUP, "rc = 0x%x\n", rc);
6274 if (!rc) {
6275 BNX2X_ERR("MCP response failure, unloading\n");
6276 goto int_disable;
6277 }
6278 }
6279
6280 bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
6281
6282 /* Enable Rx interrupt handling before sending the ramrod
6283 as it's completed on Rx FP queue */
6284 for_each_queue(bp, i)
6285 napi_enable(&bnx2x_fp(bp, i, napi));
6286
6287 if (bnx2x_setup_leading(bp))
6288 goto stop_netif;
6289
6290 for_each_nondefault_queue(bp, i)
6291 if (bnx2x_setup_multi(bp, i))
6292 goto stop_netif;
6293
6294 bnx2x_set_mac_addr(bp);
6295
6296 bnx2x_phy_init(bp);
6297
6298 /* Start fast path */
6299 if (req_irq) { /* IRQ is only requested from bnx2x_open */
6300 netif_start_queue(bp->dev);
6301 if (bp->flags & USING_MSIX_FLAG)
6302 printk(KERN_INFO PFX "%s: using MSI-X\n",
6303 bp->dev->name);
6304
6305 /* Otherwise Tx queue should be only reenabled */
6306 } else if (netif_running(bp->dev)) {
6307 netif_wake_queue(bp->dev);
6308 bnx2x_set_rx_mode(bp->dev);
6309 }
6310
6311 /* start the timer */
6312 mod_timer(&bp->timer, jiffies + bp->current_interval);
6313
6314 return 0;
6315
6316stop_netif:
6317 for_each_queue(bp, i)
6318 napi_disable(&bnx2x_fp(bp, i, napi));
6319
6320int_disable:
6321 bnx2x_disable_int_sync(bp);
6322
6323 bnx2x_free_skbs(bp);
6324 bnx2x_free_irq(bp);
6325
6326out_error:
6327 bnx2x_free_mem(bp);
6328
6329 /* TBD we really need to reset the chip
6330 if we want to recover from this */
6331 return rc;
6332}
6333
6334static void bnx2x_netif_stop(struct bnx2x *bp)
6335{
6336 int i;
6337
6338 bp->rx_mode = BNX2X_RX_MODE_NONE;
6339 bnx2x_set_storm_rx_mode(bp);
6340
6341 bnx2x_disable_int_sync(bp);
6342 bnx2x_link_reset(bp);
6343
6344 for_each_queue(bp, i)
6345 napi_disable(&bnx2x_fp(bp, i, napi));
6346
6347 if (netif_running(bp->dev)) {
6348 netif_tx_disable(bp->dev);
6349 bp->dev->trans_start = jiffies; /* prevent tx timeout */
6350 }
6351}
6352
6353static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
6354{
6355 int port = bp->port;
6356#ifdef USE_DMAE
6357 u32 wb_write[2];
6358#endif
6359 int base, i;
6360
6361 DP(NETIF_MSG_IFDOWN, "reset called with code %x\n", reset_code);
6362
6363 /* Do not rcv packets to BRB */
6364 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
6365 /* Do not direct rcv packets that are not for MCP to the BRB */
6366 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
6367 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
6368
6369 /* Configure IGU and AEU */
6370 REG_WR(bp, HC_REG_CONFIG_0 + port*4, 0x1000);
6371 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
6372
6373 /* TODO: Close Doorbell port? */
6374
6375 /* Clear ILT */
6376#ifdef USE_DMAE
6377 wb_write[0] = 0;
6378 wb_write[1] = 0;
6379#endif
6380 base = port * RQ_ONCHIP_AT_PORT_SIZE;
6381 for (i = base; i < base + RQ_ONCHIP_AT_PORT_SIZE; i++) {
6382#ifdef USE_DMAE
6383 REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
6384#else
6385 REG_WR_IND(bp, PXP2_REG_RQ_ONCHIP_AT, 0);
6386 REG_WR_IND(bp, PXP2_REG_RQ_ONCHIP_AT + 4, 0);
6387#endif
6388 }
6389
6390 if (reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
6391 /* reset_common */
6392 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6393 0xd3ffff7f);
6394 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6395 0x1403);
6396 }
6397}
6398
6399static int bnx2x_stop_multi(struct bnx2x *bp, int index)
6400{
6401
6402 int rc;
6403
6404 /* halt the connnection */
6405 bp->fp[index].state = BNX2X_FP_STATE_HALTING;
6406 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, index, 0, 0, 0);
6407
6408
6409 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, index,
6410 &(bp->fp[index].state), 1);
6411 if (rc) /* timout */
6412 return rc;
6413
6414 /* delete cfc entry */
6415 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CFC_DEL, index, 0, 0, 1);
6416
6417 return bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_DELETED, index,
6418 &(bp->fp[index].state), 1);
6419
6420}
6421
6422
6423static void bnx2x_stop_leading(struct bnx2x *bp)
6424{
6425
6426 /* if the other port is hadling traffic,
6427 this can take a lot of time */
6428 int timeout = 500;
6429
6430 might_sleep();
6431
6432 /* Send HALT ramrod */
6433 bp->fp[0].state = BNX2X_FP_STATE_HALTING;
6434 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, 0, 0, 0, 0);
6435
6436 if (bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, 0,
6437 &(bp->fp[0].state), 1))
6438 return;
6439
6440 bp->dsb_sp_prod_idx = *bp->dsb_sp_prod;
6441
6442 /* Send CFC_DELETE ramrod */
6443 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_DEL, 0, 0, 0, 1);
6444
6445 /*
6446 Wait for completion.
6447 we are going to reset the chip anyway
6448 so there is not much to do if this times out
6449 */
6450 while (bp->dsb_sp_prod_idx == *bp->dsb_sp_prod && timeout) {
6451 timeout--;
6452 msleep(1);
6453 }
6454
6455}
6456
6457static int bnx2x_nic_unload(struct bnx2x *bp, int fre_irq)
6458{
6459 u32 reset_code = 0;
6460 int rc;
6461 int i;
6462
6463 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
6464
6465 /* Calling flush_scheduled_work() may deadlock because
6466 * linkwatch_event() may be on the workqueue and it will try to get
6467 * the rtnl_lock which we are holding.
6468 */
6469
6470 while (bp->in_reset_task)
6471 msleep(1);
6472
6473 /* Delete the timer: do it before disabling interrupts, as it
6474 may be stil STAT_QUERY ramrod pending after stopping the timer */
6475 del_timer_sync(&bp->timer);
6476
6477 /* Wait until stat ramrod returns and all SP tasks complete */
6478 while (bp->stat_pending && (bp->spq_left != MAX_SPQ_PENDING))
6479 msleep(1);
6480
6481 /* Stop fast path, disable MAC, disable interrupts, disable napi */
6482 bnx2x_netif_stop(bp);
6483
6484 if (bp->flags & NO_WOL_FLAG)
6485 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
6486 else if (bp->wol) {
6487 u32 emac_base = bp->port ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
6488 u8 *mac_addr = bp->dev->dev_addr;
6489 u32 val = (EMAC_MODE_MPKT | EMAC_MODE_MPKT_RCVD |
6490 EMAC_MODE_ACPI_RCVD);
6491
6492 EMAC_WR(EMAC_REG_EMAC_MODE, val);
6493
6494 val = (mac_addr[0] << 8) | mac_addr[1];
6495 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH, val);
6496
6497 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
6498 (mac_addr[4] << 8) | mac_addr[5];
6499 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + 4, val);
6500
6501 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
6502 } else
6503 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6504
6505 for_each_nondefault_queue(bp, i)
6506 if (bnx2x_stop_multi(bp, i))
6507 goto error;
6508
6509
6510 bnx2x_stop_leading(bp);
6511
6512error:
6513 if (!nomcp)
6514 rc = bnx2x_fw_command(bp, reset_code);
6515 else
6516 rc = FW_MSG_CODE_DRV_UNLOAD_COMMON;
6517
6518 /* Release IRQs */
6519 if (fre_irq)
6520 bnx2x_free_irq(bp);
6521
6522 /* Reset the chip */
6523 bnx2x_reset_chip(bp, rc);
6524
6525 /* Report UNLOAD_DONE to MCP */
6526 if (!nomcp)
6527 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
6528
6529 /* Free SKBs and driver internals */
6530 bnx2x_free_skbs(bp);
6531 bnx2x_free_mem(bp);
6532
6533 bp->state = BNX2X_STATE_CLOSED;
6534 /* Set link down */
6535 bp->link_up = 0;
6536 netif_carrier_off(bp->dev);
6537
6538 return 0;
6539}
6540
6541/* end of nic load/unload */
6542
6543/* ethtool_ops */
6544
6545/*
6546 * Init service functions
6547 */
6548
6549static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
6550{
6551 int port = bp->port;
6552 u32 ext_phy_type;
6553
6554 bp->phy_flags = 0;
6555
6556 switch (switch_cfg) {
6557 case SWITCH_CFG_1G:
6558 BNX2X_DEV_INFO("switch_cfg 0x%x (1G)\n", switch_cfg);
6559
6560 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
6561 switch (ext_phy_type) {
6562 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
6563 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
6564 ext_phy_type);
6565
6566 bp->supported |= (SUPPORTED_10baseT_Half |
6567 SUPPORTED_10baseT_Full |
6568 SUPPORTED_100baseT_Half |
6569 SUPPORTED_100baseT_Full |
6570 SUPPORTED_1000baseT_Full |
6571 SUPPORTED_2500baseT_Full |
6572 SUPPORTED_TP | SUPPORTED_FIBRE |
6573 SUPPORTED_Autoneg |
6574 SUPPORTED_Pause |
6575 SUPPORTED_Asym_Pause);
6576 break;
6577
6578 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
6579 BNX2X_DEV_INFO("ext_phy_type 0x%x (5482)\n",
6580 ext_phy_type);
6581
6582 bp->phy_flags |= PHY_SGMII_FLAG;
6583
6584 bp->supported |= (/* SUPPORTED_10baseT_Half |
6585 SUPPORTED_10baseT_Full |
6586 SUPPORTED_100baseT_Half |
6587 SUPPORTED_100baseT_Full |*/
6588 SUPPORTED_1000baseT_Full |
6589 SUPPORTED_TP | SUPPORTED_FIBRE |
6590 SUPPORTED_Autoneg |
6591 SUPPORTED_Pause |
6592 SUPPORTED_Asym_Pause);
6593 break;
6594
6595 default:
6596 BNX2X_ERR("NVRAM config error. "
6597 "BAD SerDes ext_phy_config 0x%x\n",
6598 bp->ext_phy_config);
6599 return;
6600 }
6601
6602 bp->phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
6603 port*0x10);
6604 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->phy_addr);
6605 break;
6606
6607 case SWITCH_CFG_10G:
6608 BNX2X_DEV_INFO("switch_cfg 0x%x (10G)\n", switch_cfg);
6609
6610 bp->phy_flags |= PHY_XGXS_FLAG;
6611
6612 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
6613 switch (ext_phy_type) {
6614 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
6615 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
6616 ext_phy_type);
6617
6618 bp->supported |= (SUPPORTED_10baseT_Half |
6619 SUPPORTED_10baseT_Full |
6620 SUPPORTED_100baseT_Half |
6621 SUPPORTED_100baseT_Full |
6622 SUPPORTED_1000baseT_Full |
6623 SUPPORTED_2500baseT_Full |
6624 SUPPORTED_10000baseT_Full |
6625 SUPPORTED_TP | SUPPORTED_FIBRE |
6626 SUPPORTED_Autoneg |
6627 SUPPORTED_Pause |
6628 SUPPORTED_Asym_Pause);
6629 break;
6630
6631 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
6632 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
6633 BNX2X_DEV_INFO("ext_phy_type 0x%x (8705/6)\n",
6634 ext_phy_type);
6635
6636 bp->supported |= (SUPPORTED_10000baseT_Full |
6637 SUPPORTED_FIBRE |
6638 SUPPORTED_Pause |
6639 SUPPORTED_Asym_Pause);
6640 break;
6641
6642 default:
6643 BNX2X_ERR("NVRAM config error. "
6644 "BAD XGXS ext_phy_config 0x%x\n",
6645 bp->ext_phy_config);
6646 return;
6647 }
6648
6649 bp->phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
6650 port*0x18);
6651 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->phy_addr);
6652
6653 bp->ser_lane = ((bp->lane_config &
6654 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6655 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6656 bp->rx_lane_swap = ((bp->lane_config &
6657 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
6658 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
6659 bp->tx_lane_swap = ((bp->lane_config &
6660 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
6661 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
6662 BNX2X_DEV_INFO("rx_lane_swap 0x%x tx_lane_swap 0x%x\n",
6663 bp->rx_lane_swap, bp->tx_lane_swap);
6664 break;
6665
6666 default:
6667 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
6668 bp->link_config);
6669 return;
6670 }
6671
6672 /* mask what we support according to speed_cap_mask */
6673 if (!(bp->speed_cap_mask &
6674 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
6675 bp->supported &= ~SUPPORTED_10baseT_Half;
6676
6677 if (!(bp->speed_cap_mask &
6678 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
6679 bp->supported &= ~SUPPORTED_10baseT_Full;
6680
6681 if (!(bp->speed_cap_mask &
6682 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
6683 bp->supported &= ~SUPPORTED_100baseT_Half;
6684
6685 if (!(bp->speed_cap_mask &
6686 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
6687 bp->supported &= ~SUPPORTED_100baseT_Full;
6688
6689 if (!(bp->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
6690 bp->supported &= ~(SUPPORTED_1000baseT_Half |
6691 SUPPORTED_1000baseT_Full);
6692
6693 if (!(bp->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
6694 bp->supported &= ~SUPPORTED_2500baseT_Full;
6695
6696 if (!(bp->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
6697 bp->supported &= ~SUPPORTED_10000baseT_Full;
6698
6699 BNX2X_DEV_INFO("supported 0x%x\n", bp->supported);
6700}
6701
6702static void bnx2x_link_settings_requested(struct bnx2x *bp)
6703{
6704 bp->req_autoneg = 0;
6705 bp->req_duplex = DUPLEX_FULL;
6706
6707 switch (bp->link_config & PORT_FEATURE_LINK_SPEED_MASK) {
6708 case PORT_FEATURE_LINK_SPEED_AUTO:
6709 if (bp->supported & SUPPORTED_Autoneg) {
6710 bp->req_autoneg |= AUTONEG_SPEED;
6711 bp->req_line_speed = 0;
6712 bp->advertising = bp->supported;
6713 } else {
6714 u32 ext_phy_type;
6715
6716 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
6717 if ((ext_phy_type ==
6718 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
6719 (ext_phy_type ==
6720 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706)) {
6721 /* force 10G, no AN */
6722 bp->req_line_speed = SPEED_10000;
6723 bp->advertising =
6724 (ADVERTISED_10000baseT_Full |
6725 ADVERTISED_FIBRE);
6726 break;
6727 }
6728 BNX2X_ERR("NVRAM config error. "
6729 "Invalid link_config 0x%x"
6730 " Autoneg not supported\n",
6731 bp->link_config);
6732 return;
6733 }
6734 break;
6735
6736 case PORT_FEATURE_LINK_SPEED_10M_FULL:
6737 if (bp->speed_cap_mask &
6738 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) {
6739 bp->req_line_speed = SPEED_10;
6740 bp->advertising = (ADVERTISED_10baseT_Full |
6741 ADVERTISED_TP);
6742 } else {
6743 BNX2X_ERR("NVRAM config error. "
6744 "Invalid link_config 0x%x"
6745 " speed_cap_mask 0x%x\n",
6746 bp->link_config, bp->speed_cap_mask);
6747 return;
6748 }
6749 break;
6750
6751 case PORT_FEATURE_LINK_SPEED_10M_HALF:
6752 if (bp->speed_cap_mask &
6753 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
6754 bp->req_line_speed = SPEED_10;
6755 bp->req_duplex = DUPLEX_HALF;
6756 bp->advertising = (ADVERTISED_10baseT_Half |
6757 ADVERTISED_TP);
6758 } else {
6759 BNX2X_ERR("NVRAM config error. "
6760 "Invalid link_config 0x%x"
6761 " speed_cap_mask 0x%x\n",
6762 bp->link_config, bp->speed_cap_mask);
6763 return;
6764 }
6765 break;
6766
6767 case PORT_FEATURE_LINK_SPEED_100M_FULL:
6768 if (bp->speed_cap_mask &
6769 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
6770 bp->req_line_speed = SPEED_100;
6771 bp->advertising = (ADVERTISED_100baseT_Full |
6772 ADVERTISED_TP);
6773 } else {
6774 BNX2X_ERR("NVRAM config error. "
6775 "Invalid link_config 0x%x"
6776 " speed_cap_mask 0x%x\n",
6777 bp->link_config, bp->speed_cap_mask);
6778 return;
6779 }
6780 break;
6781
6782 case PORT_FEATURE_LINK_SPEED_100M_HALF:
6783 if (bp->speed_cap_mask &
6784 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
6785 bp->req_line_speed = SPEED_100;
6786 bp->req_duplex = DUPLEX_HALF;
6787 bp->advertising = (ADVERTISED_100baseT_Half |
6788 ADVERTISED_TP);
6789 } else {
6790 BNX2X_ERR("NVRAM config error. "
6791 "Invalid link_config 0x%x"
6792 " speed_cap_mask 0x%x\n",
6793 bp->link_config, bp->speed_cap_mask);
6794 return;
6795 }
6796 break;
6797
6798 case PORT_FEATURE_LINK_SPEED_1G:
6799 if (bp->speed_cap_mask &
6800 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) {
6801 bp->req_line_speed = SPEED_1000;
6802 bp->advertising = (ADVERTISED_1000baseT_Full |
6803 ADVERTISED_TP);
6804 } else {
6805 BNX2X_ERR("NVRAM config error. "
6806 "Invalid link_config 0x%x"
6807 " speed_cap_mask 0x%x\n",
6808 bp->link_config, bp->speed_cap_mask);
6809 return;
6810 }
6811 break;
6812
6813 case PORT_FEATURE_LINK_SPEED_2_5G:
6814 if (bp->speed_cap_mask &
6815 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) {
6816 bp->req_line_speed = SPEED_2500;
6817 bp->advertising = (ADVERTISED_2500baseT_Full |
6818 ADVERTISED_TP);
6819 } else {
6820 BNX2X_ERR("NVRAM config error. "
6821 "Invalid link_config 0x%x"
6822 " speed_cap_mask 0x%x\n",
6823 bp->link_config, bp->speed_cap_mask);
6824 return;
6825 }
6826 break;
6827
6828 case PORT_FEATURE_LINK_SPEED_10G_CX4:
6829 case PORT_FEATURE_LINK_SPEED_10G_KX4:
6830 case PORT_FEATURE_LINK_SPEED_10G_KR:
6831 if (!(bp->phy_flags & PHY_XGXS_FLAG)) {
6832 BNX2X_ERR("NVRAM config error. "
6833 "Invalid link_config 0x%x"
6834 " phy_flags 0x%x\n",
6835 bp->link_config, bp->phy_flags);
6836 return;
6837 }
6838 if (bp->speed_cap_mask &
6839 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
6840 bp->req_line_speed = SPEED_10000;
6841 bp->advertising = (ADVERTISED_10000baseT_Full |
6842 ADVERTISED_FIBRE);
6843 } else {
6844 BNX2X_ERR("NVRAM config error. "
6845 "Invalid link_config 0x%x"
6846 " speed_cap_mask 0x%x\n",
6847 bp->link_config, bp->speed_cap_mask);
6848 return;
6849 }
6850 break;
6851
6852 default:
6853 BNX2X_ERR("NVRAM config error. "
6854 "BAD link speed link_config 0x%x\n",
6855 bp->link_config);
6856 bp->req_autoneg |= AUTONEG_SPEED;
6857 bp->req_line_speed = 0;
6858 bp->advertising = bp->supported;
6859 break;
6860 }
6861 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d\n",
6862 bp->req_line_speed, bp->req_duplex);
6863
6864 bp->req_flow_ctrl = (bp->link_config &
6865 PORT_FEATURE_FLOW_CONTROL_MASK);
6866 /* Please refer to Table 28B-3 of the 802.3ab-1999 spec */
6867 switch (bp->req_flow_ctrl) {
6868 case FLOW_CTRL_AUTO:
6869 bp->req_autoneg |= AUTONEG_FLOW_CTRL;
6870 if (bp->dev->mtu <= 4500) {
6871 bp->pause_mode = PAUSE_BOTH;
6872 bp->advertising |= (ADVERTISED_Pause |
6873 ADVERTISED_Asym_Pause);
6874 } else {
6875 bp->pause_mode = PAUSE_ASYMMETRIC;
6876 bp->advertising |= ADVERTISED_Asym_Pause;
6877 }
6878 break;
6879
6880 case FLOW_CTRL_TX:
6881 bp->pause_mode = PAUSE_ASYMMETRIC;
6882 bp->advertising |= ADVERTISED_Asym_Pause;
6883 break;
6884
6885 case FLOW_CTRL_RX:
6886 case FLOW_CTRL_BOTH:
6887 bp->pause_mode = PAUSE_BOTH;
6888 bp->advertising |= (ADVERTISED_Pause |
6889 ADVERTISED_Asym_Pause);
6890 break;
6891
6892 case FLOW_CTRL_NONE:
6893 default:
6894 bp->pause_mode = PAUSE_NONE;
6895 bp->advertising &= ~(ADVERTISED_Pause |
6896 ADVERTISED_Asym_Pause);
6897 break;
6898 }
6899 BNX2X_DEV_INFO("req_autoneg 0x%x req_flow_ctrl 0x%x\n"
6900 KERN_INFO " pause_mode %d advertising 0x%x\n",
6901 bp->req_autoneg, bp->req_flow_ctrl,
6902 bp->pause_mode, bp->advertising);
6903}
6904
6905static void bnx2x_get_hwinfo(struct bnx2x *bp)
6906{
6907 u32 val, val2, val3, val4, id;
6908 int port = bp->port;
6909 u32 switch_cfg;
6910
6911 bp->shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
6912 BNX2X_DEV_INFO("shmem offset is %x\n", bp->shmem_base);
6913
6914 /* Get the chip revision id and number. */
6915 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
6916 val = REG_RD(bp, MISC_REG_CHIP_NUM);
6917 id = ((val & 0xffff) << 16);
6918 val = REG_RD(bp, MISC_REG_CHIP_REV);
6919 id |= ((val & 0xf) << 12);
6920 val = REG_RD(bp, MISC_REG_CHIP_METAL);
6921 id |= ((val & 0xff) << 4);
6922 REG_RD(bp, MISC_REG_BOND_ID);
6923 id |= (val & 0xf);
6924 bp->chip_id = id;
6925 BNX2X_DEV_INFO("chip ID is %x\n", id);
6926
6927 if (!bp->shmem_base || (bp->shmem_base != 0xAF900)) {
6928 BNX2X_DEV_INFO("MCP not active\n");
6929 nomcp = 1;
6930 goto set_mac;
6931 }
6932
6933 val = SHMEM_RD(bp, validity_map[port]);
6934 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
6935 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
6936 BNX2X_ERR("MCP validity signature bad\n");
6937
6938 bp->fw_seq = (SHMEM_RD(bp, drv_fw_mb[port].drv_mb_header) &
6939 DRV_MSG_SEQ_NUMBER_MASK);
6940
6941 bp->hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
6942
6943 bp->serdes_config =
6944 SHMEM_RD(bp, dev_info.port_hw_config[bp->port].serdes_config);
6945 bp->lane_config =
6946 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
6947 bp->ext_phy_config =
6948 SHMEM_RD(bp,
6949 dev_info.port_hw_config[port].external_phy_config);
6950 bp->speed_cap_mask =
6951 SHMEM_RD(bp,
6952 dev_info.port_hw_config[port].speed_capability_mask);
6953
6954 bp->link_config =
6955 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
6956
6957 BNX2X_DEV_INFO("hw_config (%08x) serdes_config (%08x)\n"
6958 KERN_INFO " lane_config (%08x) ext_phy_config (%08x)\n"
6959 KERN_INFO " speed_cap_mask (%08x) link_config (%08x)"
6960 " fw_seq (%08x)\n",
6961 bp->hw_config, bp->serdes_config, bp->lane_config,
6962 bp->ext_phy_config, bp->speed_cap_mask,
6963 bp->link_config, bp->fw_seq);
6964
6965 switch_cfg = (bp->link_config & PORT_FEATURE_CONNECTED_SWITCH_MASK);
6966 bnx2x_link_settings_supported(bp, switch_cfg);
6967
6968 bp->autoneg = (bp->hw_config & SHARED_HW_CFG_AN_ENABLE_MASK);
6969 /* for now disable cl73 */
6970 bp->autoneg &= ~SHARED_HW_CFG_AN_ENABLE_CL73;
6971 BNX2X_DEV_INFO("autoneg 0x%x\n", bp->autoneg);
6972
6973 bnx2x_link_settings_requested(bp);
6974
6975 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
6976 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
6977 bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff);
6978 bp->dev->dev_addr[1] = (u8)(val2 & 0xff);
6979 bp->dev->dev_addr[2] = (u8)(val >> 24 & 0xff);
6980 bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
6981 bp->dev->dev_addr[4] = (u8)(val >> 8 & 0xff);
6982 bp->dev->dev_addr[5] = (u8)(val & 0xff);
6983
6984 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, 6);
6985
6986
6987 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
6988 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
6989 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
6990 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
6991
6992 printk(KERN_INFO PFX "part number %X-%X-%X-%X\n",
6993 val, val2, val3, val4);
6994
6995 /* bc ver */
6996 if (!nomcp) {
6997 bp->bc_ver = val = ((SHMEM_RD(bp, dev_info.bc_rev)) >> 8);
6998 BNX2X_DEV_INFO("bc_ver %X\n", val);
6999 if (val < BNX2X_BC_VER) {
7000 /* for now only warn
7001 * later we might need to enforce this */
7002 BNX2X_ERR("This driver needs bc_ver %X but found %X,"
7003 " please upgrade BC\n", BNX2X_BC_VER, val);
7004 }
7005 } else {
7006 bp->bc_ver = 0;
7007 }
7008
7009 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
7010 bp->flash_size = (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
7011 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
7012 bp->flash_size, bp->flash_size);
7013
7014 return;
7015
7016set_mac: /* only supposed to happen on emulation/FPGA */
7017 BNX2X_ERR("warning constant MAC workaround active\n");
7018 bp->dev->dev_addr[0] = 0;
7019 bp->dev->dev_addr[1] = 0x50;
7020 bp->dev->dev_addr[2] = 0xc2;
7021 bp->dev->dev_addr[3] = 0x2c;
7022 bp->dev->dev_addr[4] = 0x71;
7023 bp->dev->dev_addr[5] = port ? 0x0d : 0x0e;
7024
7025 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, 6);
7026
7027}
7028
7029/*
7030 * ethtool service functions
7031 */
7032
7033/* All ethtool functions called with rtnl_lock */
7034
7035static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7036{
7037 struct bnx2x *bp = netdev_priv(dev);
7038
7039 cmd->supported = bp->supported;
7040 cmd->advertising = bp->advertising;
7041
7042 if (netif_carrier_ok(dev)) {
7043 cmd->speed = bp->line_speed;
7044 cmd->duplex = bp->duplex;
7045 } else {
7046 cmd->speed = bp->req_line_speed;
7047 cmd->duplex = bp->req_duplex;
7048 }
7049
7050 if (bp->phy_flags & PHY_XGXS_FLAG) {
7051 cmd->port = PORT_FIBRE;
7052 } else {
7053 cmd->port = PORT_TP;
7054 }
7055
7056 cmd->phy_address = bp->phy_addr;
7057 cmd->transceiver = XCVR_INTERNAL;
7058
7059 if (bp->req_autoneg & AUTONEG_SPEED) {
7060 cmd->autoneg = AUTONEG_ENABLE;
7061 } else {
7062 cmd->autoneg = AUTONEG_DISABLE;
7063 }
7064
7065 cmd->maxtxpkt = 0;
7066 cmd->maxrxpkt = 0;
7067
7068 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
7069 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
7070 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
7071 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
7072 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
7073 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
7074 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
7075
7076 return 0;
7077}
7078
7079static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7080{
7081 struct bnx2x *bp = netdev_priv(dev);
7082 u32 advertising;
7083
7084 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
7085 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
7086 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
7087 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
7088 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
7089 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
7090 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
7091
7092 switch (cmd->port) {
7093 case PORT_TP:
7094 if (!(bp->supported & SUPPORTED_TP))
7095 return -EINVAL;
7096
7097 if (bp->phy_flags & PHY_XGXS_FLAG) {
7098 bnx2x_link_reset(bp);
7099 bnx2x_link_settings_supported(bp, SWITCH_CFG_1G);
7100 bnx2x_phy_deassert(bp);
7101 }
7102 break;
7103
7104 case PORT_FIBRE:
7105 if (!(bp->supported & SUPPORTED_FIBRE))
7106 return -EINVAL;
7107
7108 if (!(bp->phy_flags & PHY_XGXS_FLAG)) {
7109 bnx2x_link_reset(bp);
7110 bnx2x_link_settings_supported(bp, SWITCH_CFG_10G);
7111 bnx2x_phy_deassert(bp);
7112 }
7113 break;
7114
7115 default:
7116 return -EINVAL;
7117 }
7118
7119 if (cmd->autoneg == AUTONEG_ENABLE) {
7120 if (!(bp->supported & SUPPORTED_Autoneg))
7121 return -EINVAL;
7122
7123 /* advertise the requested speed and duplex if supported */
7124 cmd->advertising &= bp->supported;
7125
7126 bp->req_autoneg |= AUTONEG_SPEED;
7127 bp->req_line_speed = 0;
7128 bp->req_duplex = DUPLEX_FULL;
7129 bp->advertising |= (ADVERTISED_Autoneg | cmd->advertising);
7130
7131 } else { /* forced speed */
7132 /* advertise the requested speed and duplex if supported */
7133 switch (cmd->speed) {
7134 case SPEED_10:
7135 if (cmd->duplex == DUPLEX_FULL) {
7136 if (!(bp->supported & SUPPORTED_10baseT_Full))
7137 return -EINVAL;
7138
7139 advertising = (ADVERTISED_10baseT_Full |
7140 ADVERTISED_TP);
7141 } else {
7142 if (!(bp->supported & SUPPORTED_10baseT_Half))
7143 return -EINVAL;
7144
7145 advertising = (ADVERTISED_10baseT_Half |
7146 ADVERTISED_TP);
7147 }
7148 break;
7149
7150 case SPEED_100:
7151 if (cmd->duplex == DUPLEX_FULL) {
7152 if (!(bp->supported &
7153 SUPPORTED_100baseT_Full))
7154 return -EINVAL;
7155
7156 advertising = (ADVERTISED_100baseT_Full |
7157 ADVERTISED_TP);
7158 } else {
7159 if (!(bp->supported &
7160 SUPPORTED_100baseT_Half))
7161 return -EINVAL;
7162
7163 advertising = (ADVERTISED_100baseT_Half |
7164 ADVERTISED_TP);
7165 }
7166 break;
7167
7168 case SPEED_1000:
7169 if (cmd->duplex != DUPLEX_FULL)
7170 return -EINVAL;
7171
7172 if (!(bp->supported & SUPPORTED_1000baseT_Full))
7173 return -EINVAL;
7174
7175 advertising = (ADVERTISED_1000baseT_Full |
7176 ADVERTISED_TP);
7177 break;
7178
7179 case SPEED_2500:
7180 if (cmd->duplex != DUPLEX_FULL)
7181 return -EINVAL;
7182
7183 if (!(bp->supported & SUPPORTED_2500baseT_Full))
7184 return -EINVAL;
7185
7186 advertising = (ADVERTISED_2500baseT_Full |
7187 ADVERTISED_TP);
7188 break;
7189
7190 case SPEED_10000:
7191 if (cmd->duplex != DUPLEX_FULL)
7192 return -EINVAL;
7193
7194 if (!(bp->supported & SUPPORTED_10000baseT_Full))
7195 return -EINVAL;
7196
7197 advertising = (ADVERTISED_10000baseT_Full |
7198 ADVERTISED_FIBRE);
7199 break;
7200
7201 default:
7202 return -EINVAL;
7203 }
7204
7205 bp->req_autoneg &= ~AUTONEG_SPEED;
7206 bp->req_line_speed = cmd->speed;
7207 bp->req_duplex = cmd->duplex;
7208 bp->advertising = advertising;
7209 }
7210
7211 DP(NETIF_MSG_LINK, "req_autoneg 0x%x req_line_speed %d\n"
7212 DP_LEVEL " req_duplex %d advertising 0x%x\n",
7213 bp->req_autoneg, bp->req_line_speed, bp->req_duplex,
7214 bp->advertising);
7215
7216 bnx2x_stop_stats(bp);
7217 bnx2x_link_initialize(bp);
7218
7219 return 0;
7220}
7221
7222static void bnx2x_get_drvinfo(struct net_device *dev,
7223 struct ethtool_drvinfo *info)
7224{
7225 struct bnx2x *bp = netdev_priv(dev);
7226
7227 strcpy(info->driver, DRV_MODULE_NAME);
7228 strcpy(info->version, DRV_MODULE_VERSION);
7229 snprintf(info->fw_version, 32, "%d.%d.%d:%d (BC VER %x)",
7230 BCM_5710_FW_MAJOR_VERSION, BCM_5710_FW_MINOR_VERSION,
7231 BCM_5710_FW_REVISION_VERSION, BCM_5710_FW_COMPILE_FLAGS,
7232 bp->bc_ver);
7233 strcpy(info->bus_info, pci_name(bp->pdev));
7234 info->n_stats = BNX2X_NUM_STATS;
7235 info->testinfo_len = BNX2X_NUM_TESTS;
7236 info->eedump_len = bp->flash_size;
7237 info->regdump_len = 0;
7238}
7239
7240static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7241{
7242 struct bnx2x *bp = netdev_priv(dev);
7243
7244 if (bp->flags & NO_WOL_FLAG) {
7245 wol->supported = 0;
7246 wol->wolopts = 0;
7247 } else {
7248 wol->supported = WAKE_MAGIC;
7249 if (bp->wol)
7250 wol->wolopts = WAKE_MAGIC;
7251 else
7252 wol->wolopts = 0;
7253 }
7254 memset(&wol->sopass, 0, sizeof(wol->sopass));
7255}
7256
7257static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7258{
7259 struct bnx2x *bp = netdev_priv(dev);
7260
7261 if (wol->wolopts & ~WAKE_MAGIC)
7262 return -EINVAL;
7263
7264 if (wol->wolopts & WAKE_MAGIC) {
7265 if (bp->flags & NO_WOL_FLAG)
7266 return -EINVAL;
7267
7268 bp->wol = 1;
7269 } else {
7270 bp->wol = 0;
7271 }
7272 return 0;
7273}
7274
7275static u32 bnx2x_get_msglevel(struct net_device *dev)
7276{
7277 struct bnx2x *bp = netdev_priv(dev);
7278
7279 return bp->msglevel;
7280}
7281
7282static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
7283{
7284 struct bnx2x *bp = netdev_priv(dev);
7285
7286 if (capable(CAP_NET_ADMIN))
7287 bp->msglevel = level;
7288}
7289
7290static int bnx2x_nway_reset(struct net_device *dev)
7291{
7292 struct bnx2x *bp = netdev_priv(dev);
7293
7294 if (bp->state != BNX2X_STATE_OPEN) {
7295 DP(NETIF_MSG_PROBE, "state is %x, returning\n", bp->state);
7296 return -EAGAIN;
7297 }
7298
7299 bnx2x_stop_stats(bp);
7300 bnx2x_link_initialize(bp);
7301
7302 return 0;
7303}
7304
7305static int bnx2x_get_eeprom_len(struct net_device *dev)
7306{
7307 struct bnx2x *bp = netdev_priv(dev);
7308
7309 return bp->flash_size;
7310}
7311
7312static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
7313{
7314 int port = bp->port;
7315 int count, i;
7316 u32 val = 0;
7317
7318 /* adjust timeout for emulation/FPGA */
7319 count = NVRAM_TIMEOUT_COUNT;
7320 if (CHIP_REV_IS_SLOW(bp))
7321 count *= 100;
7322
7323 /* request access to nvram interface */
7324 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
7325 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
7326
7327 for (i = 0; i < count*10; i++) {
7328 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
7329 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
7330 break;
7331
7332 udelay(5);
7333 }
7334
7335 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
7336 DP(NETIF_MSG_NVM, "cannot get access to nvram interface\n");
7337 return -EBUSY;
7338 }
7339
7340 return 0;
7341}
7342
7343static int bnx2x_release_nvram_lock(struct bnx2x *bp)
7344{
7345 int port = bp->port;
7346 int count, i;
7347 u32 val = 0;
7348
7349 /* adjust timeout for emulation/FPGA */
7350 count = NVRAM_TIMEOUT_COUNT;
7351 if (CHIP_REV_IS_SLOW(bp))
7352 count *= 100;
7353
7354 /* relinquish nvram interface */
7355 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
7356 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
7357
7358 for (i = 0; i < count*10; i++) {
7359 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
7360 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
7361 break;
7362
7363 udelay(5);
7364 }
7365
7366 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
7367 DP(NETIF_MSG_NVM, "cannot free access to nvram interface\n");
7368 return -EBUSY;
7369 }
7370
7371 return 0;
7372}
7373
7374static void bnx2x_enable_nvram_access(struct bnx2x *bp)
7375{
7376 u32 val;
7377
7378 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
7379
7380 /* enable both bits, even on read */
7381 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
7382 (val | MCPR_NVM_ACCESS_ENABLE_EN |
7383 MCPR_NVM_ACCESS_ENABLE_WR_EN));
7384}
7385
7386static void bnx2x_disable_nvram_access(struct bnx2x *bp)
7387{
7388 u32 val;
7389
7390 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
7391
7392 /* disable both bits, even after read */
7393 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
7394 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
7395 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
7396}
7397
7398static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, u32 *ret_val,
7399 u32 cmd_flags)
7400{
7401 int rc;
7402 int count, i;
7403 u32 val;
7404
7405 /* build the command word */
7406 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
7407
7408 /* need to clear DONE bit separately */
7409 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
7410
7411 /* address of the NVRAM to read from */
7412 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
7413 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
7414
7415 /* issue a read command */
7416 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
7417
7418 /* adjust timeout for emulation/FPGA */
7419 count = NVRAM_TIMEOUT_COUNT;
7420 if (CHIP_REV_IS_SLOW(bp))
7421 count *= 100;
7422
7423 /* wait for completion */
7424 *ret_val = 0;
7425 rc = -EBUSY;
7426 for (i = 0; i < count; i++) {
7427 udelay(5);
7428 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
7429
7430 if (val & MCPR_NVM_COMMAND_DONE) {
7431 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
7432 DP(NETIF_MSG_NVM, "val 0x%08x\n", val);
7433 /* we read nvram data in cpu order
7434 * but ethtool sees it as an array of bytes
7435 * converting to big-endian will do the work */
7436 val = cpu_to_be32(val);
7437 *ret_val = val;
7438 rc = 0;
7439 break;
7440 }
7441 }
7442
7443 return rc;
7444}
7445
7446static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
7447 int buf_size)
7448{
7449 int rc;
7450 u32 cmd_flags;
7451 u32 val;
7452
7453 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
7454 DP(NETIF_MSG_NVM,
7455 "Invalid paramter: offset 0x%x buf_size 0x%x\n",
7456 offset, buf_size);
7457 return -EINVAL;
7458 }
7459
7460 if (offset + buf_size > bp->flash_size) {
7461 DP(NETIF_MSG_NVM, "Invalid paramter: offset (0x%x) +"
7462 " buf_size (0x%x) > flash_size (0x%x)\n",
7463 offset, buf_size, bp->flash_size);
7464 return -EINVAL;
7465 }
7466
7467 /* request access to nvram interface */
7468 rc = bnx2x_acquire_nvram_lock(bp);
7469 if (rc)
7470 return rc;
7471
7472 /* enable access to nvram interface */
7473 bnx2x_enable_nvram_access(bp);
7474
7475 /* read the first word(s) */
7476 cmd_flags = MCPR_NVM_COMMAND_FIRST;
7477 while ((buf_size > sizeof(u32)) && (rc == 0)) {
7478 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
7479 memcpy(ret_buf, &val, 4);
7480
7481 /* advance to the next dword */
7482 offset += sizeof(u32);
7483 ret_buf += sizeof(u32);
7484 buf_size -= sizeof(u32);
7485 cmd_flags = 0;
7486 }
7487
7488 if (rc == 0) {
7489 cmd_flags |= MCPR_NVM_COMMAND_LAST;
7490 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
7491 memcpy(ret_buf, &val, 4);
7492 }
7493
7494 /* disable access to nvram interface */
7495 bnx2x_disable_nvram_access(bp);
7496 bnx2x_release_nvram_lock(bp);
7497
7498 return rc;
7499}
7500
7501static int bnx2x_get_eeprom(struct net_device *dev,
7502 struct ethtool_eeprom *eeprom, u8 *eebuf)
7503{
7504 struct bnx2x *bp = netdev_priv(dev);
7505 int rc;
7506
7507 DP(NETIF_MSG_NVM, "ethtool_eeprom: cmd %d\n"
7508 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
7509 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
7510 eeprom->len, eeprom->len);
7511
7512 /* parameters already validated in ethtool_get_eeprom */
7513
7514 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
7515
7516 return rc;
7517}
7518
7519static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
7520 u32 cmd_flags)
7521{
7522 int rc;
7523 int count, i;
7524
7525 /* build the command word */
7526 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
7527
7528 /* need to clear DONE bit separately */
7529 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
7530
7531 /* write the data */
7532 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
7533
7534 /* address of the NVRAM to write to */
7535 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
7536 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
7537
7538 /* issue the write command */
7539 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
7540
7541 /* adjust timeout for emulation/FPGA */
7542 count = NVRAM_TIMEOUT_COUNT;
7543 if (CHIP_REV_IS_SLOW(bp))
7544 count *= 100;
7545
7546 /* wait for completion */
7547 rc = -EBUSY;
7548 for (i = 0; i < count; i++) {
7549 udelay(5);
7550 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
7551 if (val & MCPR_NVM_COMMAND_DONE) {
7552 rc = 0;
7553 break;
7554 }
7555 }
7556
7557 return rc;
7558}
7559
7560#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
7561
7562static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
7563 int buf_size)
7564{
7565 int rc;
7566 u32 cmd_flags;
7567 u32 align_offset;
7568 u32 val;
7569
7570 if (offset + buf_size > bp->flash_size) {
7571 DP(NETIF_MSG_NVM, "Invalid paramter: offset (0x%x) +"
7572 " buf_size (0x%x) > flash_size (0x%x)\n",
7573 offset, buf_size, bp->flash_size);
7574 return -EINVAL;
7575 }
7576
7577 /* request access to nvram interface */
7578 rc = bnx2x_acquire_nvram_lock(bp);
7579 if (rc)
7580 return rc;
7581
7582 /* enable access to nvram interface */
7583 bnx2x_enable_nvram_access(bp);
7584
7585 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
7586 align_offset = (offset & ~0x03);
7587 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
7588
7589 if (rc == 0) {
7590 val &= ~(0xff << BYTE_OFFSET(offset));
7591 val |= (*data_buf << BYTE_OFFSET(offset));
7592
7593 /* nvram data is returned as an array of bytes
7594 * convert it back to cpu order */
7595 val = be32_to_cpu(val);
7596
7597 DP(NETIF_MSG_NVM, "val 0x%08x\n", val);
7598
7599 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
7600 cmd_flags);
7601 }
7602
7603 /* disable access to nvram interface */
7604 bnx2x_disable_nvram_access(bp);
7605 bnx2x_release_nvram_lock(bp);
7606
7607 return rc;
7608}
7609
7610static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
7611 int buf_size)
7612{
7613 int rc;
7614 u32 cmd_flags;
7615 u32 val;
7616 u32 written_so_far;
7617
7618 if (buf_size == 1) { /* ethtool */
7619 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
7620 }
7621
7622 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
7623 DP(NETIF_MSG_NVM,
7624 "Invalid paramter: offset 0x%x buf_size 0x%x\n",
7625 offset, buf_size);
7626 return -EINVAL;
7627 }
7628
7629 if (offset + buf_size > bp->flash_size) {
7630 DP(NETIF_MSG_NVM, "Invalid paramter: offset (0x%x) +"
7631 " buf_size (0x%x) > flash_size (0x%x)\n",
7632 offset, buf_size, bp->flash_size);
7633 return -EINVAL;
7634 }
7635
7636 /* request access to nvram interface */
7637 rc = bnx2x_acquire_nvram_lock(bp);
7638 if (rc)
7639 return rc;
7640
7641 /* enable access to nvram interface */
7642 bnx2x_enable_nvram_access(bp);
7643
7644 written_so_far = 0;
7645 cmd_flags = MCPR_NVM_COMMAND_FIRST;
7646 while ((written_so_far < buf_size) && (rc == 0)) {
7647 if (written_so_far == (buf_size - sizeof(u32)))
7648 cmd_flags |= MCPR_NVM_COMMAND_LAST;
7649 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
7650 cmd_flags |= MCPR_NVM_COMMAND_LAST;
7651 else if ((offset % NVRAM_PAGE_SIZE) == 0)
7652 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
7653
7654 memcpy(&val, data_buf, 4);
7655 DP(NETIF_MSG_NVM, "val 0x%08x\n", val);
7656
7657 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
7658
7659 /* advance to the next dword */
7660 offset += sizeof(u32);
7661 data_buf += sizeof(u32);
7662 written_so_far += sizeof(u32);
7663 cmd_flags = 0;
7664 }
7665
7666 /* disable access to nvram interface */
7667 bnx2x_disable_nvram_access(bp);
7668 bnx2x_release_nvram_lock(bp);
7669
7670 return rc;
7671}
7672
7673static int bnx2x_set_eeprom(struct net_device *dev,
7674 struct ethtool_eeprom *eeprom, u8 *eebuf)
7675{
7676 struct bnx2x *bp = netdev_priv(dev);
7677 int rc;
7678
7679 DP(NETIF_MSG_NVM, "ethtool_eeprom: cmd %d\n"
7680 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
7681 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
7682 eeprom->len, eeprom->len);
7683
7684 /* parameters already validated in ethtool_set_eeprom */
7685
7686 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
7687
7688 return rc;
7689}
7690
7691static int bnx2x_get_coalesce(struct net_device *dev,
7692 struct ethtool_coalesce *coal)
7693{
7694 struct bnx2x *bp = netdev_priv(dev);
7695
7696 memset(coal, 0, sizeof(struct ethtool_coalesce));
7697
7698 coal->rx_coalesce_usecs = bp->rx_ticks;
7699 coal->tx_coalesce_usecs = bp->tx_ticks;
7700 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7701
7702 return 0;
7703}
7704
7705static int bnx2x_set_coalesce(struct net_device *dev,
7706 struct ethtool_coalesce *coal)
7707{
7708 struct bnx2x *bp = netdev_priv(dev);
7709
7710 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7711 if (bp->rx_ticks > 3000)
7712 bp->rx_ticks = 3000;
7713
7714 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7715 if (bp->tx_ticks > 0x3000)
7716 bp->tx_ticks = 0x3000;
7717
7718 bp->stats_ticks = coal->stats_block_coalesce_usecs;
7719 if (bp->stats_ticks > 0xffff00)
7720 bp->stats_ticks = 0xffff00;
7721 bp->stats_ticks &= 0xffff00;
7722
7723 if (netif_running(bp->dev))
7724 bnx2x_update_coalesce(bp);
7725
7726 return 0;
7727}
7728
7729static void bnx2x_get_ringparam(struct net_device *dev,
7730 struct ethtool_ringparam *ering)
7731{
7732 struct bnx2x *bp = netdev_priv(dev);
7733
7734 ering->rx_max_pending = MAX_RX_AVAIL;
7735 ering->rx_mini_max_pending = 0;
7736 ering->rx_jumbo_max_pending = 0;
7737
7738 ering->rx_pending = bp->rx_ring_size;
7739 ering->rx_mini_pending = 0;
7740 ering->rx_jumbo_pending = 0;
7741
7742 ering->tx_max_pending = MAX_TX_AVAIL;
7743 ering->tx_pending = bp->tx_ring_size;
7744}
7745
7746static int bnx2x_set_ringparam(struct net_device *dev,
7747 struct ethtool_ringparam *ering)
7748{
7749 struct bnx2x *bp = netdev_priv(dev);
7750
7751 if ((ering->rx_pending > MAX_RX_AVAIL) ||
7752 (ering->tx_pending > MAX_TX_AVAIL) ||
7753 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
7754 return -EINVAL;
7755
7756 bp->rx_ring_size = ering->rx_pending;
7757 bp->tx_ring_size = ering->tx_pending;
7758
7759 if (netif_running(bp->dev)) {
7760 bnx2x_nic_unload(bp, 0);
7761 bnx2x_nic_load(bp, 0);
7762 }
7763
7764 return 0;
7765}
7766
7767static void bnx2x_get_pauseparam(struct net_device *dev,
7768 struct ethtool_pauseparam *epause)
7769{
7770 struct bnx2x *bp = netdev_priv(dev);
7771
7772 epause->autoneg =
7773 ((bp->req_autoneg & AUTONEG_FLOW_CTRL) == AUTONEG_FLOW_CTRL);
7774 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) == FLOW_CTRL_RX);
7775 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) == FLOW_CTRL_TX);
7776
7777 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
7778 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
7779 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
7780}
7781
7782static int bnx2x_set_pauseparam(struct net_device *dev,
7783 struct ethtool_pauseparam *epause)
7784{
7785 struct bnx2x *bp = netdev_priv(dev);
7786
7787 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
7788 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
7789 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
7790
7791 bp->req_flow_ctrl = FLOW_CTRL_AUTO;
7792 if (epause->autoneg) {
7793 bp->req_autoneg |= AUTONEG_FLOW_CTRL;
7794 if (bp->dev->mtu <= 4500) {
7795 bp->pause_mode = PAUSE_BOTH;
7796 bp->advertising |= (ADVERTISED_Pause |
7797 ADVERTISED_Asym_Pause);
7798 } else {
7799 bp->pause_mode = PAUSE_ASYMMETRIC;
7800 bp->advertising |= ADVERTISED_Asym_Pause;
7801 }
7802
7803 } else {
7804 bp->req_autoneg &= ~AUTONEG_FLOW_CTRL;
7805
7806 if (epause->rx_pause)
7807 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7808 if (epause->tx_pause)
7809 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7810
7811 switch (bp->req_flow_ctrl) {
7812 case FLOW_CTRL_AUTO:
7813 bp->req_flow_ctrl = FLOW_CTRL_NONE;
7814 bp->pause_mode = PAUSE_NONE;
7815 bp->advertising &= ~(ADVERTISED_Pause |
7816 ADVERTISED_Asym_Pause);
7817 break;
7818
7819 case FLOW_CTRL_TX:
7820 bp->pause_mode = PAUSE_ASYMMETRIC;
7821 bp->advertising |= ADVERTISED_Asym_Pause;
7822 break;
7823
7824 case FLOW_CTRL_RX:
7825 case FLOW_CTRL_BOTH:
7826 bp->pause_mode = PAUSE_BOTH;
7827 bp->advertising |= (ADVERTISED_Pause |
7828 ADVERTISED_Asym_Pause);
7829 break;
7830 }
7831 }
7832
7833 DP(NETIF_MSG_LINK, "req_autoneg 0x%x req_flow_ctrl 0x%x\n"
7834 DP_LEVEL " pause_mode %d advertising 0x%x\n",
7835 bp->req_autoneg, bp->req_flow_ctrl, bp->pause_mode,
7836 bp->advertising);
7837
7838 bnx2x_stop_stats(bp);
7839 bnx2x_link_initialize(bp);
7840
7841 return 0;
7842}
7843
7844static u32 bnx2x_get_rx_csum(struct net_device *dev)
7845{
7846 struct bnx2x *bp = netdev_priv(dev);
7847
7848 return bp->rx_csum;
7849}
7850
7851static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
7852{
7853 struct bnx2x *bp = netdev_priv(dev);
7854
7855 bp->rx_csum = data;
7856 return 0;
7857}
7858
7859static int bnx2x_set_tso(struct net_device *dev, u32 data)
7860{
7861 if (data)
7862 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
7863 else
7864 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
7865 return 0;
7866}
7867
7868static struct {
7869 char string[ETH_GSTRING_LEN];
7870} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
7871 { "MC Errors (online)" }
7872};
7873
7874static int bnx2x_self_test_count(struct net_device *dev)
7875{
7876 return BNX2X_NUM_TESTS;
7877}
7878
7879static void bnx2x_self_test(struct net_device *dev,
7880 struct ethtool_test *etest, u64 *buf)
7881{
7882 struct bnx2x *bp = netdev_priv(dev);
7883 int stats_state;
7884
7885 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
7886
7887 if (bp->state != BNX2X_STATE_OPEN) {
7888 DP(NETIF_MSG_PROBE, "state is %x, returning\n", bp->state);
7889 return;
7890 }
7891
7892 stats_state = bp->stats_state;
7893 bnx2x_stop_stats(bp);
7894
7895 if (bnx2x_mc_assert(bp) != 0) {
7896 buf[0] = 1;
7897 etest->flags |= ETH_TEST_FL_FAILED;
7898 }
7899
7900#ifdef BNX2X_EXTRA_DEBUG
7901 bnx2x_panic_dump(bp);
7902#endif
7903 bp->stats_state = stats_state;
7904}
7905
7906static struct {
7907 char string[ETH_GSTRING_LEN];
7908} bnx2x_stats_str_arr[BNX2X_NUM_STATS] = {
7909 { "rx_bytes"}, /* 0 */
7910 { "rx_error_bytes"}, /* 1 */
7911 { "tx_bytes"}, /* 2 */
7912 { "tx_error_bytes"}, /* 3 */
7913 { "rx_ucast_packets"}, /* 4 */
7914 { "rx_mcast_packets"}, /* 5 */
7915 { "rx_bcast_packets"}, /* 6 */
7916 { "tx_ucast_packets"}, /* 7 */
7917 { "tx_mcast_packets"}, /* 8 */
7918 { "tx_bcast_packets"}, /* 9 */
7919 { "tx_mac_errors"}, /* 10 */
7920 { "tx_carrier_errors"}, /* 11 */
7921 { "rx_crc_errors"}, /* 12 */
7922 { "rx_align_errors"}, /* 13 */
7923 { "tx_single_collisions"}, /* 14 */
7924 { "tx_multi_collisions"}, /* 15 */
7925 { "tx_deferred"}, /* 16 */
7926 { "tx_excess_collisions"}, /* 17 */
7927 { "tx_late_collisions"}, /* 18 */
7928 { "tx_total_collisions"}, /* 19 */
7929 { "rx_fragments"}, /* 20 */
7930 { "rx_jabbers"}, /* 21 */
7931 { "rx_undersize_packets"}, /* 22 */
7932 { "rx_oversize_packets"}, /* 23 */
7933 { "rx_xon_frames"}, /* 24 */
7934 { "rx_xoff_frames"}, /* 25 */
7935 { "tx_xon_frames"}, /* 26 */
7936 { "tx_xoff_frames"}, /* 27 */
7937 { "rx_mac_ctrl_frames"}, /* 28 */
7938 { "rx_filtered_packets"}, /* 29 */
7939 { "rx_discards"}, /* 30 */
7940};
7941
7942#define STATS_OFFSET32(offset_name) \
7943 (offsetof(struct bnx2x_eth_stats, offset_name) / 4)
7944
7945static unsigned long bnx2x_stats_offset_arr[BNX2X_NUM_STATS] = {
7946 STATS_OFFSET32(total_bytes_received_hi), /* 0 */
7947 STATS_OFFSET32(stat_IfHCInBadOctets_hi), /* 1 */
7948 STATS_OFFSET32(total_bytes_transmitted_hi), /* 2 */
7949 STATS_OFFSET32(stat_IfHCOutBadOctets_hi), /* 3 */
7950 STATS_OFFSET32(total_unicast_packets_received_hi), /* 4 */
7951 STATS_OFFSET32(total_multicast_packets_received_hi), /* 5 */
7952 STATS_OFFSET32(total_broadcast_packets_received_hi), /* 6 */
7953 STATS_OFFSET32(total_unicast_packets_transmitted_hi), /* 7 */
7954 STATS_OFFSET32(total_multicast_packets_transmitted_hi), /* 8 */
7955 STATS_OFFSET32(total_broadcast_packets_transmitted_hi), /* 9 */
7956 STATS_OFFSET32(stat_Dot3statsInternalMacTransmitErrors), /* 10 */
7957 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors), /* 11 */
7958 STATS_OFFSET32(crc_receive_errors), /* 12 */
7959 STATS_OFFSET32(alignment_errors), /* 13 */
7960 STATS_OFFSET32(single_collision_transmit_frames), /* 14 */
7961 STATS_OFFSET32(multiple_collision_transmit_frames), /* 15 */
7962 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions), /* 16 */
7963 STATS_OFFSET32(excessive_collision_frames), /* 17 */
7964 STATS_OFFSET32(late_collision_frames), /* 18 */
7965 STATS_OFFSET32(number_of_bugs_found_in_stats_spec), /* 19 */
7966 STATS_OFFSET32(runt_packets_received), /* 20 */
7967 STATS_OFFSET32(jabber_packets_received), /* 21 */
7968 STATS_OFFSET32(error_runt_packets_received), /* 22 */
7969 STATS_OFFSET32(error_jabber_packets_received), /* 23 */
7970 STATS_OFFSET32(pause_xon_frames_received), /* 24 */
7971 STATS_OFFSET32(pause_xoff_frames_received), /* 25 */
7972 STATS_OFFSET32(pause_xon_frames_transmitted), /* 26 */
7973 STATS_OFFSET32(pause_xoff_frames_transmitted), /* 27 */
7974 STATS_OFFSET32(control_frames_received), /* 28 */
7975 STATS_OFFSET32(mac_filter_discard), /* 29 */
7976 STATS_OFFSET32(no_buff_discard), /* 30 */
7977};
7978
7979static u8 bnx2x_stats_len_arr[BNX2X_NUM_STATS] = {
7980 8, 0, 8, 0, 8, 8, 8, 8, 8, 8,
7981 4, 0, 4, 4, 4, 4, 4, 4, 4, 4,
7982 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
7983 4,
7984};
7985
7986static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7987{
7988 switch (stringset) {
7989 case ETH_SS_STATS:
7990 memcpy(buf, bnx2x_stats_str_arr, sizeof(bnx2x_stats_str_arr));
7991 break;
7992
7993 case ETH_SS_TEST:
7994 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
7995 break;
7996 }
7997}
7998
7999static int bnx2x_get_stats_count(struct net_device *dev)
8000{
8001 return BNX2X_NUM_STATS;
8002}
8003
8004static void bnx2x_get_ethtool_stats(struct net_device *dev,
8005 struct ethtool_stats *stats, u64 *buf)
8006{
8007 struct bnx2x *bp = netdev_priv(dev);
8008 u32 *hw_stats = (u32 *)bnx2x_sp_check(bp, eth_stats);
8009 int i;
8010
8011 for (i = 0; i < BNX2X_NUM_STATS; i++) {
8012 if (bnx2x_stats_len_arr[i] == 0) {
8013 /* skip this counter */
8014 buf[i] = 0;
8015 continue;
8016 }
8017 if (!hw_stats) {
8018 buf[i] = 0;
8019 continue;
8020 }
8021 if (bnx2x_stats_len_arr[i] == 4) {
8022 /* 4-byte counter */
8023 buf[i] = (u64) *(hw_stats + bnx2x_stats_offset_arr[i]);
8024 continue;
8025 }
8026 /* 8-byte counter */
8027 buf[i] = HILO_U64(*(hw_stats + bnx2x_stats_offset_arr[i]),
8028 *(hw_stats + bnx2x_stats_offset_arr[i] + 1));
8029 }
8030}
8031
8032static int bnx2x_phys_id(struct net_device *dev, u32 data)
8033{
8034 struct bnx2x *bp = netdev_priv(dev);
8035 int i;
8036
8037 if (data == 0)
8038 data = 2;
8039
8040 for (i = 0; i < (data * 2); i++) {
8041 if ((i % 2) == 0) {
8042 bnx2x_leds_set(bp, SPEED_1000);
8043 } else {
8044 bnx2x_leds_unset(bp);
8045 }
8046 msleep_interruptible(500);
8047 if (signal_pending(current))
8048 break;
8049 }
8050
8051 if (bp->link_up)
8052 bnx2x_leds_set(bp, bp->line_speed);
8053
8054 return 0;
8055}
8056
8057static struct ethtool_ops bnx2x_ethtool_ops = {
8058 .get_settings = bnx2x_get_settings,
8059 .set_settings = bnx2x_set_settings,
8060 .get_drvinfo = bnx2x_get_drvinfo,
8061 .get_wol = bnx2x_get_wol,
8062 .set_wol = bnx2x_set_wol,
8063 .get_msglevel = bnx2x_get_msglevel,
8064 .set_msglevel = bnx2x_set_msglevel,
8065 .nway_reset = bnx2x_nway_reset,
8066 .get_link = ethtool_op_get_link,
8067 .get_eeprom_len = bnx2x_get_eeprom_len,
8068 .get_eeprom = bnx2x_get_eeprom,
8069 .set_eeprom = bnx2x_set_eeprom,
8070 .get_coalesce = bnx2x_get_coalesce,
8071 .set_coalesce = bnx2x_set_coalesce,
8072 .get_ringparam = bnx2x_get_ringparam,
8073 .set_ringparam = bnx2x_set_ringparam,
8074 .get_pauseparam = bnx2x_get_pauseparam,
8075 .set_pauseparam = bnx2x_set_pauseparam,
8076 .get_rx_csum = bnx2x_get_rx_csum,
8077 .set_rx_csum = bnx2x_set_rx_csum,
8078 .get_tx_csum = ethtool_op_get_tx_csum,
8079 .set_tx_csum = ethtool_op_set_tx_csum,
8080 .get_sg = ethtool_op_get_sg,
8081 .set_sg = ethtool_op_set_sg,
8082 .get_tso = ethtool_op_get_tso,
8083 .set_tso = bnx2x_set_tso,
8084 .self_test_count = bnx2x_self_test_count,
8085 .self_test = bnx2x_self_test,
8086 .get_strings = bnx2x_get_strings,
8087 .phys_id = bnx2x_phys_id,
8088 .get_stats_count = bnx2x_get_stats_count,
8089 .get_ethtool_stats = bnx2x_get_ethtool_stats
8090};
8091
8092/* end of ethtool_ops */
8093
8094/****************************************************************************
8095* General service functions
8096****************************************************************************/
8097
8098static int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
8099{
8100 u16 pmcsr;
8101
8102 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
8103
8104 switch (state) {
8105 case PCI_D0:
8106 pci_write_config_word(bp->pdev,
8107 bp->pm_cap + PCI_PM_CTRL,
8108 ((pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
8109 PCI_PM_CTRL_PME_STATUS));
8110
8111 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
8112 /* delay required during transition out of D3hot */
8113 msleep(20);
8114 break;
8115
8116 case PCI_D3hot:
8117 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
8118 pmcsr |= 3;
8119
8120 if (bp->wol)
8121 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
8122
8123 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
8124 pmcsr);
8125
8126 /* No more memory access after this point until
8127 * device is brought back to D0.
8128 */
8129 break;
8130
8131 default:
8132 return -EINVAL;
8133 }
8134 return 0;
8135}
8136
8137/*
8138 * net_device service functions
8139 */
8140
8141/* Called with rtnl_lock from vlan functions and also netif_tx_lock
8142 * from set_multicast.
8143 */
8144static void bnx2x_set_rx_mode(struct net_device *dev)
8145{
8146 struct bnx2x *bp = netdev_priv(dev);
8147 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
8148
8149 DP(NETIF_MSG_IFUP, "called dev->flags = %x\n", dev->flags);
8150
8151 if (dev->flags & IFF_PROMISC)
8152 rx_mode = BNX2X_RX_MODE_PROMISC;
8153
8154 else if ((dev->flags & IFF_ALLMULTI) ||
8155 (dev->mc_count > BNX2X_MAX_MULTICAST))
8156 rx_mode = BNX2X_RX_MODE_ALLMULTI;
8157
8158 else { /* some multicasts */
8159 int i, old, offset;
8160 struct dev_mc_list *mclist;
8161 struct mac_configuration_cmd *config =
8162 bnx2x_sp(bp, mcast_config);
8163
8164 for (i = 0, mclist = dev->mc_list;
8165 mclist && (i < dev->mc_count);
8166 i++, mclist = mclist->next) {
8167
8168 config->config_table[i].cam_entry.msb_mac_addr =
8169 swab16(*(u16 *)&mclist->dmi_addr[0]);
8170 config->config_table[i].cam_entry.middle_mac_addr =
8171 swab16(*(u16 *)&mclist->dmi_addr[2]);
8172 config->config_table[i].cam_entry.lsb_mac_addr =
8173 swab16(*(u16 *)&mclist->dmi_addr[4]);
8174 config->config_table[i].cam_entry.flags =
8175 cpu_to_le16(bp->port);
8176 config->config_table[i].target_table_entry.flags = 0;
8177 config->config_table[i].target_table_entry.
8178 client_id = 0;
8179 config->config_table[i].target_table_entry.
8180 vlan_id = 0;
8181
8182 DP(NETIF_MSG_IFUP,
8183 "setting MCAST[%d] (%04x:%04x:%04x)\n",
8184 i, config->config_table[i].cam_entry.msb_mac_addr,
8185 config->config_table[i].cam_entry.middle_mac_addr,
8186 config->config_table[i].cam_entry.lsb_mac_addr);
8187 }
8188 old = config->hdr.length_6b;
8189 if (old > i) {
8190 for (; i < old; i++) {
8191 if (CAM_IS_INVALID(config->config_table[i])) {
8192 i--; /* already invalidated */
8193 break;
8194 }
8195 /* invalidate */
8196 CAM_INVALIDATE(config->config_table[i]);
8197 }
8198 }
8199
8200 if (CHIP_REV_IS_SLOW(bp))
8201 offset = BNX2X_MAX_EMUL_MULTI*(1 + bp->port);
8202 else
8203 offset = BNX2X_MAX_MULTICAST*(1 + bp->port);
8204
8205 config->hdr.length_6b = i;
8206 config->hdr.offset = offset;
8207 config->hdr.reserved0 = 0;
8208 config->hdr.reserved1 = 0;
8209
8210 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
8211 U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
8212 U64_LO(bnx2x_sp_mapping(bp, mcast_config)), 0);
8213 }
8214
8215 bp->rx_mode = rx_mode;
8216 bnx2x_set_storm_rx_mode(bp);
8217}
8218
8219static int bnx2x_poll(struct napi_struct *napi, int budget)
8220{
8221 struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath,
8222 napi);
8223 struct bnx2x *bp = fp->bp;
8224 int work_done = 0;
8225
8226#ifdef BNX2X_STOP_ON_ERROR
8227 if (unlikely(bp->panic))
8228 goto out_panic;
8229#endif
8230
8231 prefetch(fp->tx_buf_ring[TX_BD(fp->tx_pkt_cons)].skb);
8232 prefetch(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb);
8233 prefetch((char *)(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb) + 256);
8234
8235 bnx2x_update_fpsb_idx(fp);
8236
8237 if (le16_to_cpu(*fp->tx_cons_sb) != fp->tx_pkt_cons)
8238 bnx2x_tx_int(fp, budget);
8239
8240
8241 if (le16_to_cpu(*fp->rx_cons_sb) != fp->rx_comp_cons)
8242 work_done = bnx2x_rx_int(fp, budget);
8243
8244
8245 rmb(); /* bnx2x_has_work() reads the status block */
8246
8247 /* must not complete if we consumed full budget */
8248 if ((work_done < budget) && !bnx2x_has_work(fp)) {
8249
8250#ifdef BNX2X_STOP_ON_ERROR
8251out_panic:
8252#endif
8253 netif_rx_complete(bp->dev, napi);
8254
8255 bnx2x_ack_sb(bp, fp->index, USTORM_ID,
8256 le16_to_cpu(fp->fp_u_idx), IGU_INT_NOP, 1);
8257 bnx2x_ack_sb(bp, fp->index, CSTORM_ID,
8258 le16_to_cpu(fp->fp_c_idx), IGU_INT_ENABLE, 1);
8259 }
8260
8261 return work_done;
8262}
8263
8264/* Called with netif_tx_lock.
8265 * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call
8266 * netif_wake_queue().
8267 */
8268static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
8269{
8270 struct bnx2x *bp = netdev_priv(dev);
8271 struct bnx2x_fastpath *fp;
8272 struct sw_tx_bd *tx_buf;
8273 struct eth_tx_bd *tx_bd;
8274 struct eth_tx_parse_bd *pbd = NULL;
8275 u16 pkt_prod, bd_prod;
8276 int nbd, fp_index = 0;
8277 dma_addr_t mapping;
8278
8279#ifdef BNX2X_STOP_ON_ERROR
8280 if (unlikely(bp->panic))
8281 return NETDEV_TX_BUSY;
8282#endif
8283
8284 fp_index = smp_processor_id() % (bp->num_queues);
8285
8286 fp = &bp->fp[fp_index];
8287 if (unlikely(bnx2x_tx_avail(bp->fp) <
8288 (skb_shinfo(skb)->nr_frags + 3))) {
8289 bp->slowpath->eth_stats.driver_xoff++,
8290 netif_stop_queue(dev);
8291 BNX2X_ERR("BUG! Tx ring full when queue awake!\n");
8292 return NETDEV_TX_BUSY;
8293 }
8294
8295 /*
8296 This is a bit ugly. First we use one BD which we mark as start,
8297 then for TSO or xsum we have a parsing info BD,
8298 and only then we have the rest of the TSO bds.
8299 (don't forget to mark the last one as last,
8300 and to unmap only AFTER you write to the BD ...)
8301 I would like to thank DovH for this mess.
8302 */
8303
8304 pkt_prod = fp->tx_pkt_prod++;
8305 bd_prod = fp->tx_bd_prod;
8306 bd_prod = TX_BD(bd_prod);
8307
8308 /* get a tx_buff and first bd */
8309 tx_buf = &fp->tx_buf_ring[TX_BD(pkt_prod)];
8310 tx_bd = &fp->tx_desc_ring[bd_prod];
8311
8312 tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
8313 tx_bd->general_data = (UNICAST_ADDRESS <<
8314 ETH_TX_BD_ETH_ADDR_TYPE_SHIFT);
8315 tx_bd->general_data |= 1; /* header nbd */
8316
8317 /* remeber the first bd of the packet */
8318 tx_buf->first_bd = bd_prod;
8319
8320 DP(NETIF_MSG_TX_QUEUED,
8321 "sending pkt %u @%p next_idx %u bd %u @%p\n",
8322 pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_bd);
8323
8324 if (skb->ip_summed == CHECKSUM_PARTIAL) {
8325 struct iphdr *iph = ip_hdr(skb);
8326 u8 len;
8327
8328 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IP_CSUM;
8329
8330 /* turn on parsing and get a bd */
8331 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
8332 pbd = (void *)&fp->tx_desc_ring[bd_prod];
8333 len = ((u8 *)iph - (u8 *)skb->data) / 2;
8334
8335 /* for now NS flag is not used in Linux */
8336 pbd->global_data = (len |
8337 ((skb->protocol == ETH_P_8021Q) <<
8338 ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT));
8339 pbd->ip_hlen = ip_hdrlen(skb) / 2;
8340 pbd->total_hlen = cpu_to_le16(len + pbd->ip_hlen);
8341 if (iph->protocol == IPPROTO_TCP) {
8342 struct tcphdr *th = tcp_hdr(skb);
8343
8344 tx_bd->bd_flags.as_bitfield |=
8345 ETH_TX_BD_FLAGS_TCP_CSUM;
8346 pbd->tcp_flags = htonl(tcp_flag_word(skb)) & 0xFFFF;
8347 pbd->total_hlen += cpu_to_le16(tcp_hdrlen(skb) / 2);
8348 pbd->tcp_pseudo_csum = swab16(th->check);
8349
8350 } else if (iph->protocol == IPPROTO_UDP) {
8351 struct udphdr *uh = udp_hdr(skb);
8352
8353 tx_bd->bd_flags.as_bitfield |=
8354 ETH_TX_BD_FLAGS_TCP_CSUM;
8355 pbd->total_hlen += cpu_to_le16(4);
8356 pbd->global_data |= ETH_TX_PARSE_BD_CS_ANY_FLG;
8357 pbd->cs_offset = 5; /* 10 >> 1 */
8358 pbd->tcp_pseudo_csum = 0;
8359 /* HW bug: we need to subtract 10 bytes before the
8360 * UDP header from the csum
8361 */
8362 uh->check = (u16) ~csum_fold(csum_sub(uh->check,
8363 csum_partial(((u8 *)(uh)-10), 10, 0)));
8364 }
8365 }
8366
8367 if ((bp->vlgrp != NULL) && vlan_tx_tag_present(skb)) {
8368 tx_bd->vlan = cpu_to_le16(vlan_tx_tag_get(skb));
8369 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_VLAN_TAG;
8370 } else {
8371 tx_bd->vlan = cpu_to_le16(pkt_prod);
8372 }
8373
8374 mapping = pci_map_single(bp->pdev, skb->data,
8375 skb->len, PCI_DMA_TODEVICE);
8376
8377 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
8378 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
8379 nbd = skb_shinfo(skb)->nr_frags + ((pbd == NULL)? 1 : 2);
8380 tx_bd->nbd = cpu_to_le16(nbd);
8381 tx_bd->nbytes = cpu_to_le16(skb_headlen(skb));
8382
8383 DP(NETIF_MSG_TX_QUEUED, "first bd @%p addr (%x:%x) nbd %d"
8384 " nbytes %d flags %x vlan %u\n",
8385 tx_bd, tx_bd->addr_hi, tx_bd->addr_lo, tx_bd->nbd,
8386 tx_bd->nbytes, tx_bd->bd_flags.as_bitfield, tx_bd->vlan);
8387
8388 if (skb_shinfo(skb)->gso_size &&
8389 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
8390 int hlen = 2 * le32_to_cpu(pbd->total_hlen);
8391
8392 DP(NETIF_MSG_TX_QUEUED,
8393 "TSO packet len %d hlen %d total len %d tso size %d\n",
8394 skb->len, hlen, skb_headlen(skb),
8395 skb_shinfo(skb)->gso_size);
8396
8397 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
8398
8399 if (tx_bd->nbytes > cpu_to_le16(hlen)) {
8400 /* we split the first bd into headers and data bds
8401 * to ease the pain of our fellow micocode engineers
8402 * we use one mapping for both bds
8403 * So far this has only been observed to happen
8404 * in Other Operating Systems(TM)
8405 */
8406
8407 /* first fix first bd */
8408 nbd++;
8409 tx_bd->nbd = cpu_to_le16(nbd);
8410 tx_bd->nbytes = cpu_to_le16(hlen);
8411
8412 /* we only print this as an error
8413 * because we don't think this will ever happen.
8414 */
8415 BNX2X_ERR("TSO split header size is %d (%x:%x)"
8416 " nbd %d\n", tx_bd->nbytes, tx_bd->addr_hi,
8417 tx_bd->addr_lo, tx_bd->nbd);
8418
8419 /* now get a new data bd
8420 * (after the pbd) and fill it */
8421 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
8422 tx_bd = &fp->tx_desc_ring[bd_prod];
8423
8424 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
8425 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping) + hlen);
8426 tx_bd->nbytes = cpu_to_le16(skb_headlen(skb) - hlen);
8427 tx_bd->vlan = cpu_to_le16(pkt_prod);
8428 /* this marks the bd
8429 * as one that has no individual mapping
8430 * the FW ignors this flag in a bd not maked start
8431 */
8432 tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_SW_LSO;
8433 DP(NETIF_MSG_TX_QUEUED,
8434 "TSO split data size is %d (%x:%x)\n",
8435 tx_bd->nbytes, tx_bd->addr_hi, tx_bd->addr_lo);
8436 }
8437
8438 if (!pbd) {
8439 /* supposed to be unreached
8440 * (and therefore not handled properly...)
8441 */
8442 BNX2X_ERR("LSO with no PBD\n");
8443 BUG();
8444 }
8445
8446 pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
8447 pbd->tcp_send_seq = swab32(tcp_hdr(skb)->seq);
8448 pbd->ip_id = swab16(ip_hdr(skb)->id);
8449 pbd->tcp_pseudo_csum =
8450 swab16(~csum_tcpudp_magic(ip_hdr(skb)->saddr,
8451 ip_hdr(skb)->daddr,
8452 0, IPPROTO_TCP, 0));
8453 pbd->global_data |= ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN;
8454 }
8455
8456 {
8457 int i;
8458
8459 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
8460 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8461
8462 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
8463 tx_bd = &fp->tx_desc_ring[bd_prod];
8464
8465 mapping = pci_map_page(bp->pdev, frag->page,
8466 frag->page_offset,
8467 frag->size, PCI_DMA_TODEVICE);
8468
8469 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
8470 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
8471 tx_bd->nbytes = cpu_to_le16(frag->size);
8472 tx_bd->vlan = cpu_to_le16(pkt_prod);
8473 tx_bd->bd_flags.as_bitfield = 0;
8474 DP(NETIF_MSG_TX_QUEUED, "frag %d bd @%p"
8475 " addr (%x:%x) nbytes %d flags %x\n",
8476 i, tx_bd, tx_bd->addr_hi, tx_bd->addr_lo,
8477 tx_bd->nbytes, tx_bd->bd_flags.as_bitfield);
8478 } /* for */
8479 }
8480
8481 /* now at last mark the bd as the last bd */
8482 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_END_BD;
8483
8484 DP(NETIF_MSG_TX_QUEUED, "last bd @%p flags %x\n",
8485 tx_bd, tx_bd->bd_flags.as_bitfield);
8486
8487 tx_buf->skb = skb;
8488
8489 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
8490
8491 /* now send a tx doorbell, counting the next bd
8492 * if the packet contains or ends with it
8493 */
8494 if (TX_BD_POFF(bd_prod) < nbd)
8495 nbd++;
8496
8497 if (pbd)
8498 DP(NETIF_MSG_TX_QUEUED,
8499 "PBD @%p ip_data %x ip_hlen %u ip_id %u lso_mss %u"
8500 " tcp_flags %x xsum %x seq %u hlen %u\n",
8501 pbd, pbd->global_data, pbd->ip_hlen, pbd->ip_id,
8502 pbd->lso_mss, pbd->tcp_flags, pbd->tcp_pseudo_csum,
8503 pbd->tcp_send_seq, pbd->total_hlen);
8504
8505 DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %u bd %d\n", nbd, bd_prod);
8506
8507 fp->hw_tx_prods->bds_prod += cpu_to_le16(nbd);
8508 mb(); /* FW restriction: must not reorder writing nbd and packets */
8509 fp->hw_tx_prods->packets_prod += cpu_to_le32(1);
8510 DOORBELL(bp, fp_index, 0);
8511
8512 mmiowb();
8513
8514 fp->tx_bd_prod = bd_prod;
8515 dev->trans_start = jiffies;
8516
8517 if (unlikely(bnx2x_tx_avail(fp) < MAX_SKB_FRAGS + 3)) {
8518 netif_stop_queue(dev);
8519 bp->slowpath->eth_stats.driver_xoff++;
8520 if (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3)
8521 netif_wake_queue(dev);
8522 }
8523 fp->tx_pkt++;
8524
8525 return NETDEV_TX_OK;
8526}
8527
8528static struct net_device_stats *bnx2x_get_stats(struct net_device *dev)
8529{
8530 return &dev->stats;
8531}
8532
8533/* Called with rtnl_lock */
8534static int bnx2x_open(struct net_device *dev)
8535{
8536 struct bnx2x *bp = netdev_priv(dev);
8537
8538 bnx2x_set_power_state(bp, PCI_D0);
8539
8540 return bnx2x_nic_load(bp, 1);
8541}
8542
8543/* Called with rtnl_lock */
8544static int bnx2x_close(struct net_device *dev)
8545{
8546 int rc;
8547 struct bnx2x *bp = netdev_priv(dev);
8548
8549 /* Unload the driver, release IRQs */
8550 rc = bnx2x_nic_unload(bp, 1);
8551 if (rc) {
8552 BNX2X_ERR("bnx2x_nic_unload failed: %d\n", rc);
8553 return rc;
8554 }
8555 bnx2x_set_power_state(bp, PCI_D3hot);
8556
8557 return 0;
8558}
8559
8560/* Called with rtnl_lock */
8561static int bnx2x_change_mac_addr(struct net_device *dev, void *p)
8562{
8563 struct sockaddr *addr = p;
8564 struct bnx2x *bp = netdev_priv(dev);
8565
8566 if (!is_valid_ether_addr(addr->sa_data))
8567 return -EINVAL;
8568
8569 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
8570 if (netif_running(dev))
8571 bnx2x_set_mac_addr(bp);
8572
8573 return 0;
8574}
8575
8576/* Called with rtnl_lock */
8577static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8578{
8579 struct mii_ioctl_data *data = if_mii(ifr);
8580 struct bnx2x *bp = netdev_priv(dev);
8581 int err;
8582
8583 switch (cmd) {
8584 case SIOCGMIIPHY:
8585 data->phy_id = bp->phy_addr;
8586
8587 /* fallthru */
8588 case SIOCGMIIREG: {
8589 u32 mii_regval;
8590
8591 spin_lock_bh(&bp->phy_lock);
8592 if (bp->state == BNX2X_STATE_OPEN) {
8593 err = bnx2x_mdio22_read(bp, data->reg_num & 0x1f,
8594 &mii_regval);
8595
8596 data->val_out = mii_regval;
8597 } else {
8598 err = -EAGAIN;
8599 }
8600 spin_unlock_bh(&bp->phy_lock);
8601 return err;
8602 }
8603
8604 case SIOCSMIIREG:
8605 if (!capable(CAP_NET_ADMIN))
8606 return -EPERM;
8607
8608 spin_lock_bh(&bp->phy_lock);
8609 if (bp->state == BNX2X_STATE_OPEN) {
8610 err = bnx2x_mdio22_write(bp, data->reg_num & 0x1f,
8611 data->val_in);
8612 } else {
8613 err = -EAGAIN;
8614 }
8615 spin_unlock_bh(&bp->phy_lock);
8616 return err;
8617
8618 default:
8619 /* do nothing */
8620 break;
8621 }
8622
8623 return -EOPNOTSUPP;
8624}
8625
8626/* Called with rtnl_lock */
8627static int bnx2x_change_mtu(struct net_device *dev, int new_mtu)
8628{
8629 struct bnx2x *bp = netdev_priv(dev);
8630
8631 if ((new_mtu > ETH_MAX_JUMBO_PACKET_SIZE) ||
8632 ((new_mtu + ETH_HLEN) < ETH_MIN_PACKET_SIZE))
8633 return -EINVAL;
8634
8635 /* This does not race with packet allocation
8636 * because the actuall alloc size is
8637 * only updated as part of load
8638 */
8639 dev->mtu = new_mtu;
8640
8641 if (netif_running(dev)) {
8642 bnx2x_nic_unload(bp, 0);
8643 bnx2x_nic_load(bp, 0);
8644 }
8645 return 0;
8646}
8647
8648static void bnx2x_tx_timeout(struct net_device *dev)
8649{
8650 struct bnx2x *bp = netdev_priv(dev);
8651
8652#ifdef BNX2X_STOP_ON_ERROR
8653 if (!bp->panic)
8654 bnx2x_panic();
8655#endif
8656 /* This allows the netif to be shutdown gracefully before resetting */
8657 schedule_work(&bp->reset_task);
8658}
8659
8660#ifdef BCM_VLAN
8661/* Called with rtnl_lock */
8662static void bnx2x_vlan_rx_register(struct net_device *dev,
8663 struct vlan_group *vlgrp)
8664{
8665 struct bnx2x *bp = netdev_priv(dev);
8666
8667 bp->vlgrp = vlgrp;
8668 if (netif_running(dev))
8669 bnx2x_set_rx_mode(dev);
8670}
8671#endif
8672
8673#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
8674static void poll_bnx2x(struct net_device *dev)
8675{
8676 struct bnx2x *bp = netdev_priv(dev);
8677
8678 disable_irq(bp->pdev->irq);
8679 bnx2x_interrupt(bp->pdev->irq, dev);
8680 enable_irq(bp->pdev->irq);
8681}
8682#endif
8683
8684static void bnx2x_reset_task(struct work_struct *work)
8685{
8686 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task);
8687
8688#ifdef BNX2X_STOP_ON_ERROR
8689 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
8690 " so reset not done to allow debug dump,\n"
8691 KERN_ERR " you will need to reboot when done\n");
8692 return;
8693#endif
8694
8695 if (!netif_running(bp->dev))
8696 return;
8697
8698 bp->in_reset_task = 1;
8699
8700 bnx2x_netif_stop(bp);
8701
8702 bnx2x_nic_unload(bp, 0);
8703 bnx2x_nic_load(bp, 0);
8704
8705 bp->in_reset_task = 0;
8706}
8707
8708static int __devinit bnx2x_init_board(struct pci_dev *pdev,
8709 struct net_device *dev)
8710{
8711 struct bnx2x *bp;
8712 int rc;
8713
8714 SET_NETDEV_DEV(dev, &pdev->dev);
8715 bp = netdev_priv(dev);
8716
8717 bp->flags = 0;
8718 bp->port = PCI_FUNC(pdev->devfn);
8719
8720 rc = pci_enable_device(pdev);
8721 if (rc) {
8722 printk(KERN_ERR PFX "Cannot enable PCI device, aborting\n");
8723 goto err_out;
8724 }
8725
8726 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
8727 printk(KERN_ERR PFX "Cannot find PCI device base address,"
8728 " aborting\n");
8729 rc = -ENODEV;
8730 goto err_out_disable;
8731 }
8732
8733 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
8734 printk(KERN_ERR PFX "Cannot find second PCI device"
8735 " base address, aborting\n");
8736 rc = -ENODEV;
8737 goto err_out_disable;
8738 }
8739
8740 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
8741 if (rc) {
8742 printk(KERN_ERR PFX "Cannot obtain PCI resources,"
8743 " aborting\n");
8744 goto err_out_disable;
8745 }
8746
8747 pci_set_master(pdev);
8748
8749 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
8750 if (bp->pm_cap == 0) {
8751 printk(KERN_ERR PFX "Cannot find power management"
8752 " capability, aborting\n");
8753 rc = -EIO;
8754 goto err_out_release;
8755 }
8756
8757 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
8758 if (bp->pcie_cap == 0) {
8759 printk(KERN_ERR PFX "Cannot find PCI Express capability,"
8760 " aborting\n");
8761 rc = -EIO;
8762 goto err_out_release;
8763 }
8764
8765 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
8766 bp->flags |= USING_DAC_FLAG;
8767 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
8768 printk(KERN_ERR PFX "pci_set_consistent_dma_mask"
8769 " failed, aborting\n");
8770 rc = -EIO;
8771 goto err_out_release;
8772 }
8773
8774 } else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
8775 printk(KERN_ERR PFX "System does not support DMA,"
8776 " aborting\n");
8777 rc = -EIO;
8778 goto err_out_release;
8779 }
8780
8781 bp->dev = dev;
8782 bp->pdev = pdev;
8783
8784 spin_lock_init(&bp->phy_lock);
8785
8786 bp->in_reset_task = 0;
8787
8788 INIT_WORK(&bp->reset_task, bnx2x_reset_task);
8789 INIT_WORK(&bp->sp_task, bnx2x_sp_task);
8790
8791 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
8792 dev->mem_end = pci_resource_end(pdev, 0);
8793
8794 dev->irq = pdev->irq;
8795
8796 bp->regview = ioremap_nocache(dev->base_addr,
8797 pci_resource_len(pdev, 0));
8798 if (!bp->regview) {
8799 printk(KERN_ERR PFX "Cannot map register space, aborting\n");
8800 rc = -ENOMEM;
8801 goto err_out_release;
8802 }
8803
8804 bp->doorbells = ioremap_nocache(pci_resource_start(pdev , 2),
8805 pci_resource_len(pdev, 2));
8806 if (!bp->doorbells) {
8807 printk(KERN_ERR PFX "Cannot map doorbell space, aborting\n");
8808 rc = -ENOMEM;
8809 goto err_out_unmap;
8810 }
8811
8812 bnx2x_set_power_state(bp, PCI_D0);
8813
8814 bnx2x_get_hwinfo(bp);
8815
8816 if (CHIP_REV(bp) == CHIP_REV_FPGA) {
8817 printk(KERN_ERR PFX "FPGA detacted. MCP disabled,"
8818 " will only init first device\n");
8819 onefunc = 1;
8820 nomcp = 1;
8821 }
8822
8823 if (nomcp) {
8824 printk(KERN_ERR PFX "MCP disabled, will only"
8825 " init first device\n");
8826 onefunc = 1;
8827 }
8828
8829 if (onefunc && bp->port) {
8830 printk(KERN_ERR PFX "Second device disabled, exiting\n");
8831 rc = -ENODEV;
8832 goto err_out_unmap;
8833 }
8834
8835 bp->tx_ring_size = MAX_TX_AVAIL;
8836 bp->rx_ring_size = MAX_RX_AVAIL;
8837
8838 bp->rx_csum = 1;
8839
8840 bp->rx_offset = 0;
8841
8842 bp->tx_quick_cons_trip_int = 0xff;
8843 bp->tx_quick_cons_trip = 0xff;
8844 bp->tx_ticks_int = 50;
8845 bp->tx_ticks = 50;
8846
8847 bp->rx_quick_cons_trip_int = 0xff;
8848 bp->rx_quick_cons_trip = 0xff;
8849 bp->rx_ticks_int = 25;
8850 bp->rx_ticks = 25;
8851
8852 bp->stats_ticks = 1000000 & 0xffff00;
8853
8854 bp->timer_interval = HZ;
8855 bp->current_interval = (poll ? poll : HZ);
8856
8857 init_timer(&bp->timer);
8858 bp->timer.expires = jiffies + bp->current_interval;
8859 bp->timer.data = (unsigned long) bp;
8860 bp->timer.function = bnx2x_timer;
8861
8862 return 0;
8863
8864err_out_unmap:
8865 if (bp->regview) {
8866 iounmap(bp->regview);
8867 bp->regview = NULL;
8868 }
8869
8870 if (bp->doorbells) {
8871 iounmap(bp->doorbells);
8872 bp->doorbells = NULL;
8873 }
8874
8875err_out_release:
8876 pci_release_regions(pdev);
8877
8878err_out_disable:
8879 pci_disable_device(pdev);
8880 pci_set_drvdata(pdev, NULL);
8881
8882err_out:
8883 return rc;
8884}
8885
8886static int __devinit bnx2x_init_one(struct pci_dev *pdev,
8887 const struct pci_device_id *ent)
8888{
8889 static int version_printed;
8890 struct net_device *dev = NULL;
8891 struct bnx2x *bp;
8892 int rc, i;
8893 int port = PCI_FUNC(pdev->devfn);
8894
8895 if (version_printed++ == 0)
8896 printk(KERN_INFO "%s", version);
8897
8898 /* dev zeroed in init_etherdev */
8899 dev = alloc_etherdev(sizeof(*bp));
8900 if (!dev)
8901 return -ENOMEM;
8902
8903 netif_carrier_off(dev);
8904
8905 bp = netdev_priv(dev);
8906 bp->msglevel = debug;
8907
8908 if (port && onefunc) {
8909 printk(KERN_ERR PFX "second function disabled. exiting\n");
8910 return 0;
8911 }
8912
8913 rc = bnx2x_init_board(pdev, dev);
8914 if (rc < 0) {
8915 free_netdev(dev);
8916 return rc;
8917 }
8918
8919 dev->hard_start_xmit = bnx2x_start_xmit;
8920 dev->watchdog_timeo = TX_TIMEOUT;
8921
8922 dev->get_stats = bnx2x_get_stats;
8923 dev->ethtool_ops = &bnx2x_ethtool_ops;
8924 dev->open = bnx2x_open;
8925 dev->stop = bnx2x_close;
8926 dev->set_multicast_list = bnx2x_set_rx_mode;
8927 dev->set_mac_address = bnx2x_change_mac_addr;
8928 dev->do_ioctl = bnx2x_ioctl;
8929 dev->change_mtu = bnx2x_change_mtu;
8930 dev->tx_timeout = bnx2x_tx_timeout;
8931#ifdef BCM_VLAN
8932 dev->vlan_rx_register = bnx2x_vlan_rx_register;
8933#endif
8934#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
8935 dev->poll_controller = poll_bnx2x;
8936#endif
8937 dev->features |= NETIF_F_SG;
8938 if (bp->flags & USING_DAC_FLAG)
8939 dev->features |= NETIF_F_HIGHDMA;
8940 dev->features |= NETIF_F_IP_CSUM;
8941#ifdef BCM_VLAN
8942 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8943#endif
8944 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
8945
8946 rc = register_netdev(dev);
8947 if (rc) {
8948 printk(KERN_ERR PFX "Cannot register net device\n");
8949 if (bp->regview)
8950 iounmap(bp->regview);
8951 if (bp->doorbells)
8952 iounmap(bp->doorbells);
8953 pci_release_regions(pdev);
8954 pci_disable_device(pdev);
8955 pci_set_drvdata(pdev, NULL);
8956 free_netdev(dev);
8957 return rc;
8958 }
8959
8960 pci_set_drvdata(pdev, dev);
8961
8962 bp->name = board_info[ent->driver_data].name;
8963 printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz "
8964 "found at mem %lx, IRQ %d, ",
8965 dev->name, bp->name,
8966 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8967 ((CHIP_ID(bp) & 0x0ff0) >> 4),
8968 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
8969 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
8970 bp->bus_speed_mhz,
8971 dev->base_addr,
8972 bp->pdev->irq);
8973
8974 printk("node addr ");
8975 for (i = 0; i < 6; i++)
8976 printk("%2.2x", dev->dev_addr[i]);
8977 printk("\n");
8978
8979 return 0;
8980}
8981
8982static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
8983{
8984 struct net_device *dev = pci_get_drvdata(pdev);
8985 struct bnx2x *bp = netdev_priv(dev);
8986
8987 flush_scheduled_work();
8988 /*tasklet_kill(&bp->sp_task);*/
8989 unregister_netdev(dev);
8990
8991 if (bp->regview)
8992 iounmap(bp->regview);
8993
8994 if (bp->doorbells)
8995 iounmap(bp->doorbells);
8996
8997 free_netdev(dev);
8998 pci_release_regions(pdev);
8999 pci_disable_device(pdev);
9000 pci_set_drvdata(pdev, NULL);
9001}
9002
9003static int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state)
9004{
9005 struct net_device *dev = pci_get_drvdata(pdev);
9006 struct bnx2x *bp = netdev_priv(dev);
9007 int rc;
9008
9009 if (!netif_running(dev))
9010 return 0;
9011
9012 rc = bnx2x_nic_unload(bp, 0);
9013 if (!rc)
9014 return rc;
9015
9016 netif_device_detach(dev);
9017 pci_save_state(pdev);
9018
9019 bnx2x_set_power_state(bp, pci_choose_state(pdev, state));
9020 return 0;
9021}
9022
9023static int bnx2x_resume(struct pci_dev *pdev)
9024{
9025 struct net_device *dev = pci_get_drvdata(pdev);
9026 struct bnx2x *bp = netdev_priv(dev);
9027 int rc;
9028
9029 if (!netif_running(dev))
9030 return 0;
9031
9032 pci_restore_state(pdev);
9033
9034 bnx2x_set_power_state(bp, PCI_D0);
9035 netif_device_attach(dev);
9036
9037 rc = bnx2x_nic_load(bp, 0);
9038 if (rc)
9039 return rc;
9040
9041 return 0;
9042}
9043
9044static struct pci_driver bnx2x_pci_driver = {
9045 .name = DRV_MODULE_NAME,
9046 .id_table = bnx2x_pci_tbl,
9047 .probe = bnx2x_init_one,
9048 .remove = __devexit_p(bnx2x_remove_one),
9049 .suspend = bnx2x_suspend,
9050 .resume = bnx2x_resume,
9051};
9052
9053static int __init bnx2x_init(void)
9054{
9055 return pci_register_driver(&bnx2x_pci_driver);
9056}
9057
9058static void __exit bnx2x_cleanup(void)
9059{
9060 pci_unregister_driver(&bnx2x_pci_driver);
9061}
9062
9063module_init(bnx2x_init);
9064module_exit(bnx2x_cleanup);
9065
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
new file mode 100644
index 000000000000..4f7ae6f77452
--- /dev/null
+++ b/drivers/net/bnx2x.h
@@ -0,0 +1,1071 @@
1/* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Eliezer Tamir <eliezert@broadcom.com>
10 * Based on code from Michael Chan's bnx2 driver
11 */
12
13#ifndef BNX2X_H
14#define BNX2X_H
15
16/* error/debug prints */
17
18#define DRV_MODULE_NAME "bnx2x"
19#define PFX DRV_MODULE_NAME ": "
20
21/* for messages that are currently off */
22#define BNX2X_MSG_OFF 0
23#define BNX2X_MSG_MCP 0x10000 /* was: NETIF_MSG_HW */
24#define BNX2X_MSG_STATS 0x20000 /* was: NETIF_MSG_TIMER */
25#define NETIF_MSG_NVM 0x40000 /* was: NETIF_MSG_HW */
26#define NETIF_MSG_DMAE 0x80000 /* was: NETIF_MSG_HW */
27
28#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
29
30/* regular debug print */
31#define DP(__mask, __fmt, __args...) do { \
32 if (bp->msglevel & (__mask)) \
33 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __FUNCTION__, \
34 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
35 } while (0)
36
37/* for errors (never masked) */
38#define BNX2X_ERR(__fmt, __args...) do { \
39 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __FUNCTION__, \
40 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
41 } while (0)
42
43/* before we have a dev->name use dev_info() */
44#define BNX2X_DEV_INFO(__fmt, __args...) do { \
45 if (bp->msglevel & NETIF_MSG_PROBE) \
46 dev_info(&bp->pdev->dev, __fmt, ##__args); \
47 } while (0)
48
49
50#ifdef BNX2X_STOP_ON_ERROR
51#define bnx2x_panic() do { \
52 bp->panic = 1; \
53 BNX2X_ERR("driver assert\n"); \
54 bnx2x_disable_int(bp); \
55 bnx2x_panic_dump(bp); \
56 } while (0)
57#else
58#define bnx2x_panic() do { \
59 BNX2X_ERR("driver assert\n"); \
60 bnx2x_panic_dump(bp); \
61 } while (0)
62#endif
63
64
65#define U64_LO(x) (((u64)x) & 0xffffffff)
66#define U64_HI(x) (((u64)x) >> 32)
67#define HILO_U64(hi, lo) (((u64)hi << 32) + lo)
68
69
70#define REG_ADDR(bp, offset) (bp->regview + offset)
71
72#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
73#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
74#define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset))
75
76#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
77#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
78#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
79#define REG_WR32(bp, offset, val) REG_WR(bp, offset, val)
80
81#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
82#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
83
84#define REG_WR_DMAE(bp, offset, val, len32) \
85 do { \
86 memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \
87 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
88 offset, len32); \
89 } while (0)
90
91#define SHMEM_RD(bp, type) \
92 REG_RD(bp, bp->shmem_base + offsetof(struct shmem_region, type))
93#define SHMEM_WR(bp, type, val) \
94 REG_WR(bp, bp->shmem_base + offsetof(struct shmem_region, type), val)
95
96#define NIG_WR(reg, val) REG_WR(bp, reg, val)
97#define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val)
98#define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)
99
100
101#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
102
103#define for_each_nondefault_queue(bp, var) \
104 for (var = 1; var < bp->num_queues; var++)
105#define is_multi(bp) (bp->num_queues > 1)
106
107
108struct regp {
109 u32 lo;
110 u32 hi;
111};
112
113struct bmac_stats {
114 struct regp tx_gtpkt;
115 struct regp tx_gtxpf;
116 struct regp tx_gtfcs;
117 struct regp tx_gtmca;
118 struct regp tx_gtgca;
119 struct regp tx_gtfrg;
120 struct regp tx_gtovr;
121 struct regp tx_gt64;
122 struct regp tx_gt127;
123 struct regp tx_gt255; /* 10 */
124 struct regp tx_gt511;
125 struct regp tx_gt1023;
126 struct regp tx_gt1518;
127 struct regp tx_gt2047;
128 struct regp tx_gt4095;
129 struct regp tx_gt9216;
130 struct regp tx_gt16383;
131 struct regp tx_gtmax;
132 struct regp tx_gtufl;
133 struct regp tx_gterr; /* 20 */
134 struct regp tx_gtbyt;
135
136 struct regp rx_gr64;
137 struct regp rx_gr127;
138 struct regp rx_gr255;
139 struct regp rx_gr511;
140 struct regp rx_gr1023;
141 struct regp rx_gr1518;
142 struct regp rx_gr2047;
143 struct regp rx_gr4095;
144 struct regp rx_gr9216; /* 30 */
145 struct regp rx_gr16383;
146 struct regp rx_grmax;
147 struct regp rx_grpkt;
148 struct regp rx_grfcs;
149 struct regp rx_grmca;
150 struct regp rx_grbca;
151 struct regp rx_grxcf;
152 struct regp rx_grxpf;
153 struct regp rx_grxuo;
154 struct regp rx_grjbr; /* 40 */
155 struct regp rx_grovr;
156 struct regp rx_grflr;
157 struct regp rx_grmeg;
158 struct regp rx_grmeb;
159 struct regp rx_grbyt;
160 struct regp rx_grund;
161 struct regp rx_grfrg;
162 struct regp rx_grerb;
163 struct regp rx_grfre;
164 struct regp rx_gripj; /* 50 */
165};
166
167struct emac_stats {
168 u32 rx_ifhcinoctets ;
169 u32 rx_ifhcinbadoctets ;
170 u32 rx_etherstatsfragments ;
171 u32 rx_ifhcinucastpkts ;
172 u32 rx_ifhcinmulticastpkts ;
173 u32 rx_ifhcinbroadcastpkts ;
174 u32 rx_dot3statsfcserrors ;
175 u32 rx_dot3statsalignmenterrors ;
176 u32 rx_dot3statscarriersenseerrors ;
177 u32 rx_xonpauseframesreceived ; /* 10 */
178 u32 rx_xoffpauseframesreceived ;
179 u32 rx_maccontrolframesreceived ;
180 u32 rx_xoffstateentered ;
181 u32 rx_dot3statsframestoolong ;
182 u32 rx_etherstatsjabbers ;
183 u32 rx_etherstatsundersizepkts ;
184 u32 rx_etherstatspkts64octets ;
185 u32 rx_etherstatspkts65octetsto127octets ;
186 u32 rx_etherstatspkts128octetsto255octets ;
187 u32 rx_etherstatspkts256octetsto511octets ; /* 20 */
188 u32 rx_etherstatspkts512octetsto1023octets ;
189 u32 rx_etherstatspkts1024octetsto1522octets;
190 u32 rx_etherstatspktsover1522octets ;
191
192 u32 rx_falsecarriererrors ;
193
194 u32 tx_ifhcoutoctets ;
195 u32 tx_ifhcoutbadoctets ;
196 u32 tx_etherstatscollisions ;
197 u32 tx_outxonsent ;
198 u32 tx_outxoffsent ;
199 u32 tx_flowcontroldone ; /* 30 */
200 u32 tx_dot3statssinglecollisionframes ;
201 u32 tx_dot3statsmultiplecollisionframes ;
202 u32 tx_dot3statsdeferredtransmissions ;
203 u32 tx_dot3statsexcessivecollisions ;
204 u32 tx_dot3statslatecollisions ;
205 u32 tx_ifhcoutucastpkts ;
206 u32 tx_ifhcoutmulticastpkts ;
207 u32 tx_ifhcoutbroadcastpkts ;
208 u32 tx_etherstatspkts64octets ;
209 u32 tx_etherstatspkts65octetsto127octets ; /* 40 */
210 u32 tx_etherstatspkts128octetsto255octets ;
211 u32 tx_etherstatspkts256octetsto511octets ;
212 u32 tx_etherstatspkts512octetsto1023octets ;
213 u32 tx_etherstatspkts1024octetsto1522octet ;
214 u32 tx_etherstatspktsover1522octets ;
215 u32 tx_dot3statsinternalmactransmiterrors ; /* 46 */
216};
217
218union mac_stats {
219 struct emac_stats emac;
220 struct bmac_stats bmac;
221};
222
223struct nig_stats {
224 u32 brb_discard;
225 u32 brb_packet;
226 u32 brb_truncate;
227 u32 flow_ctrl_discard;
228 u32 flow_ctrl_octets;
229 u32 flow_ctrl_packet;
230 u32 mng_discard;
231 u32 mng_octet_inp;
232 u32 mng_octet_out;
233 u32 mng_packet_inp;
234 u32 mng_packet_out;
235 u32 pbf_octets;
236 u32 pbf_packet;
237 u32 safc_inp;
238 u32 done;
239 u32 pad;
240};
241
242struct bnx2x_eth_stats {
243 u32 pad; /* to make long counters u64 aligned */
244 u32 mac_stx_start;
245 u32 total_bytes_received_hi;
246 u32 total_bytes_received_lo;
247 u32 total_bytes_transmitted_hi;
248 u32 total_bytes_transmitted_lo;
249 u32 total_unicast_packets_received_hi;
250 u32 total_unicast_packets_received_lo;
251 u32 total_multicast_packets_received_hi;
252 u32 total_multicast_packets_received_lo;
253 u32 total_broadcast_packets_received_hi;
254 u32 total_broadcast_packets_received_lo;
255 u32 total_unicast_packets_transmitted_hi;
256 u32 total_unicast_packets_transmitted_lo;
257 u32 total_multicast_packets_transmitted_hi;
258 u32 total_multicast_packets_transmitted_lo;
259 u32 total_broadcast_packets_transmitted_hi;
260 u32 total_broadcast_packets_transmitted_lo;
261 u32 crc_receive_errors;
262 u32 alignment_errors;
263 u32 false_carrier_detections;
264 u32 runt_packets_received;
265 u32 jabber_packets_received;
266 u32 pause_xon_frames_received;
267 u32 pause_xoff_frames_received;
268 u32 pause_xon_frames_transmitted;
269 u32 pause_xoff_frames_transmitted;
270 u32 single_collision_transmit_frames;
271 u32 multiple_collision_transmit_frames;
272 u32 late_collision_frames;
273 u32 excessive_collision_frames;
274 u32 control_frames_received;
275 u32 frames_received_64_bytes;
276 u32 frames_received_65_127_bytes;
277 u32 frames_received_128_255_bytes;
278 u32 frames_received_256_511_bytes;
279 u32 frames_received_512_1023_bytes;
280 u32 frames_received_1024_1522_bytes;
281 u32 frames_received_1523_9022_bytes;
282 u32 frames_transmitted_64_bytes;
283 u32 frames_transmitted_65_127_bytes;
284 u32 frames_transmitted_128_255_bytes;
285 u32 frames_transmitted_256_511_bytes;
286 u32 frames_transmitted_512_1023_bytes;
287 u32 frames_transmitted_1024_1522_bytes;
288 u32 frames_transmitted_1523_9022_bytes;
289 u32 valid_bytes_received_hi;
290 u32 valid_bytes_received_lo;
291 u32 error_runt_packets_received;
292 u32 error_jabber_packets_received;
293 u32 mac_stx_end;
294
295 u32 pad2;
296 u32 stat_IfHCInBadOctets_hi;
297 u32 stat_IfHCInBadOctets_lo;
298 u32 stat_IfHCOutBadOctets_hi;
299 u32 stat_IfHCOutBadOctets_lo;
300 u32 stat_Dot3statsFramesTooLong;
301 u32 stat_Dot3statsInternalMacTransmitErrors;
302 u32 stat_Dot3StatsCarrierSenseErrors;
303 u32 stat_Dot3StatsDeferredTransmissions;
304 u32 stat_FlowControlDone;
305 u32 stat_XoffStateEntered;
306
307 u32 x_total_sent_bytes_hi;
308 u32 x_total_sent_bytes_lo;
309 u32 x_total_sent_pkts;
310
311 u32 t_rcv_unicast_bytes_hi;
312 u32 t_rcv_unicast_bytes_lo;
313 u32 t_rcv_broadcast_bytes_hi;
314 u32 t_rcv_broadcast_bytes_lo;
315 u32 t_rcv_multicast_bytes_hi;
316 u32 t_rcv_multicast_bytes_lo;
317 u32 t_total_rcv_pkt;
318
319 u32 checksum_discard;
320 u32 packets_too_big_discard;
321 u32 no_buff_discard;
322 u32 ttl0_discard;
323 u32 mac_discard;
324 u32 mac_filter_discard;
325 u32 xxoverflow_discard;
326 u32 brb_truncate_discard;
327
328 u32 brb_discard;
329 u32 brb_packet;
330 u32 brb_truncate;
331 u32 flow_ctrl_discard;
332 u32 flow_ctrl_octets;
333 u32 flow_ctrl_packet;
334 u32 mng_discard;
335 u32 mng_octet_inp;
336 u32 mng_octet_out;
337 u32 mng_packet_inp;
338 u32 mng_packet_out;
339 u32 pbf_octets;
340 u32 pbf_packet;
341 u32 safc_inp;
342 u32 driver_xoff;
343 u32 number_of_bugs_found_in_stats_spec; /* just kidding */
344};
345
346#define MAC_STX_NA 0xffffffff
347
348#ifdef BNX2X_MULTI
349#define MAX_CONTEXT 16
350#else
351#define MAX_CONTEXT 1
352#endif
353
354union cdu_context {
355 struct eth_context eth;
356 char pad[1024];
357};
358
359#define MAX_DMAE_C 5
360
361/* DMA memory not used in fastpath */
362struct bnx2x_slowpath {
363 union cdu_context context[MAX_CONTEXT];
364 struct eth_stats_query fw_stats;
365 struct mac_configuration_cmd mac_config;
366 struct mac_configuration_cmd mcast_config;
367
368 /* used by dmae command executer */
369 struct dmae_command dmae[MAX_DMAE_C];
370
371 union mac_stats mac_stats;
372 struct nig_stats nig;
373 struct bnx2x_eth_stats eth_stats;
374
375 u32 wb_comp;
376#define BNX2X_WB_COMP_VAL 0xe0d0d0ae
377 u32 wb_data[4];
378};
379
380#define bnx2x_sp(bp, var) (&bp->slowpath->var)
381#define bnx2x_sp_check(bp, var) ((bp->slowpath) ? (&bp->slowpath->var) : NULL)
382#define bnx2x_sp_mapping(bp, var) \
383 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
384
385
386struct sw_rx_bd {
387 struct sk_buff *skb;
388 DECLARE_PCI_UNMAP_ADDR(mapping)
389};
390
391struct sw_tx_bd {
392 struct sk_buff *skb;
393 u16 first_bd;
394};
395
396struct bnx2x_fastpath {
397
398 struct napi_struct napi;
399
400 struct host_status_block *status_blk;
401 dma_addr_t status_blk_mapping;
402
403 struct eth_tx_db_data *hw_tx_prods;
404 dma_addr_t tx_prods_mapping;
405
406 struct sw_tx_bd *tx_buf_ring;
407
408 struct eth_tx_bd *tx_desc_ring;
409 dma_addr_t tx_desc_mapping;
410
411 struct sw_rx_bd *rx_buf_ring;
412
413 struct eth_rx_bd *rx_desc_ring;
414 dma_addr_t rx_desc_mapping;
415
416 union eth_rx_cqe *rx_comp_ring;
417 dma_addr_t rx_comp_mapping;
418
419 int state;
420#define BNX2X_FP_STATE_CLOSED 0
421#define BNX2X_FP_STATE_IRQ 0x80000
422#define BNX2X_FP_STATE_OPENING 0x90000
423#define BNX2X_FP_STATE_OPEN 0xa0000
424#define BNX2X_FP_STATE_HALTING 0xb0000
425#define BNX2X_FP_STATE_HALTED 0xc0000
426#define BNX2X_FP_STATE_DELETED 0xd0000
427#define BNX2X_FP_STATE_CLOSE_IRQ 0xe0000
428
429 int index;
430
431 u16 tx_pkt_prod;
432 u16 tx_pkt_cons;
433 u16 tx_bd_prod;
434 u16 tx_bd_cons;
435 u16 *tx_cons_sb;
436
437 u16 fp_c_idx;
438 u16 fp_u_idx;
439
440 u16 rx_bd_prod;
441 u16 rx_bd_cons;
442 u16 rx_comp_prod;
443 u16 rx_comp_cons;
444 u16 *rx_cons_sb;
445
446 unsigned long tx_pkt,
447 rx_pkt,
448 rx_calls;
449
450 struct bnx2x *bp; /* parent */
451};
452
453#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
454
455
456/* attn group wiring */
457#define MAX_DYNAMIC_ATTN_GRPS 8
458
459struct attn_route {
460 u32 sig[4];
461};
462
463struct bnx2x {
464 /* Fields used in the tx and intr/napi performance paths
465 * are grouped together in the beginning of the structure
466 */
467 struct bnx2x_fastpath *fp;
468 void __iomem *regview;
469 void __iomem *doorbells;
470
471 struct net_device *dev;
472 struct pci_dev *pdev;
473
474 atomic_t intr_sem;
475 struct msix_entry msix_table[MAX_CONTEXT+1];
476
477 int tx_ring_size;
478
479#ifdef BCM_VLAN
480 struct vlan_group *vlgrp;
481#endif
482
483 u32 rx_csum;
484 u32 rx_offset;
485 u32 rx_buf_use_size; /* useable size */
486 u32 rx_buf_size; /* with alignment */
487#define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
488#define ETH_MIN_PACKET_SIZE 60
489#define ETH_MAX_PACKET_SIZE 1500
490#define ETH_MAX_JUMBO_PACKET_SIZE 9600
491
492 struct host_def_status_block *def_status_blk;
493#define DEF_SB_ID 16
494 u16 def_c_idx;
495 u16 def_u_idx;
496 u16 def_t_idx;
497 u16 def_x_idx;
498 u16 def_att_idx;
499 u32 attn_state;
500 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
501 u32 aeu_mask;
502 u32 nig_mask;
503
504 /* slow path ring */
505 struct eth_spe *spq;
506 dma_addr_t spq_mapping;
507 u16 spq_prod_idx;
508 u16 dsb_sp_prod_idx;
509 struct eth_spe *spq_prod_bd;
510 struct eth_spe *spq_last_bd;
511 u16 *dsb_sp_prod;
512 u16 spq_left; /* serialize spq */
513 spinlock_t spq_lock;
514
515 /* Flag for marking that there is either
516 * STAT_QUERY or CFC DELETE ramrod pending
517 */
518 u8 stat_pending;
519
520 /* End of fileds used in the performance code paths */
521
522 int panic;
523 int msglevel;
524
525 u32 flags;
526#define PCIX_FLAG 1
527#define PCI_32BIT_FLAG 2
528#define ONE_TDMA_FLAG 4 /* no longer used */
529#define NO_WOL_FLAG 8
530#define USING_DAC_FLAG 0x10
531#define USING_MSIX_FLAG 0x20
532#define ASF_ENABLE_FLAG 0x40
533
534 int port;
535
536 int pm_cap;
537 int pcie_cap;
538
539 /* Used to synchronize phy accesses */
540 spinlock_t phy_lock;
541
542 struct work_struct reset_task;
543 u16 in_reset_task;
544
545 struct work_struct sp_task;
546
547 struct timer_list timer;
548 int timer_interval;
549 int current_interval;
550
551 u32 shmem_base;
552
553 u32 chip_id;
554/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
555#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0)
556
557#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000)
558#define CHIP_NUM_5710 0x57100000
559
560#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
561#define CHIP_REV_Ax 0x00000000
562#define CHIP_REV_Bx 0x00001000
563#define CHIP_REV_Cx 0x00002000
564#define CHIP_REV_EMUL 0x0000e000
565#define CHIP_REV_FPGA 0x0000f000
566#define CHIP_REV_IS_SLOW(bp) ((CHIP_REV(bp) == CHIP_REV_EMUL) || \
567 (CHIP_REV(bp) == CHIP_REV_FPGA))
568
569#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0)
570#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0x0000000f)
571
572 u16 fw_seq;
573 u16 fw_drv_pulse_wr_seq;
574 u32 fw_mb;
575
576 u32 hw_config;
577 u32 serdes_config;
578 u32 lane_config;
579 u32 ext_phy_config;
580#define XGXS_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \
581 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
582#define SERDES_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \
583 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
584
585 u32 speed_cap_mask;
586 u32 link_config;
587#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
588#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
589#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
590#define SWITCH_CFG_ONE_TIME_DETECT \
591 PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT
592
593 u8 ser_lane;
594 u8 rx_lane_swap;
595 u8 tx_lane_swap;
596
597 u8 link_up;
598
599 u32 supported;
600/* link settings - missing defines */
601#define SUPPORTED_2500baseT_Full (1 << 15)
602#define SUPPORTED_CX4 (1 << 16)
603
604 u32 phy_flags;
605/*#define PHY_SERDES_FLAG 0x1*/
606#define PHY_BMAC_FLAG 0x2
607#define PHY_EMAC_FLAG 0x4
608#define PHY_XGXS_FLAG 0x8
609#define PHY_SGMII_FLAG 0x10
610#define PHY_INT_MODE_MASK_FLAG 0x300
611#define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
612#define PHY_INT_MODE_LINK_READY_FLAG 0x200
613
614 u32 phy_addr;
615 u32 phy_id;
616
617 u32 autoneg;
618#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
619#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
620#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
621#define AUTONEG_PARALLEL \
622 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
623#define AUTONEG_SGMII_FIBER_AUTODET \
624 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
625#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
626
627 u32 req_autoneg;
628#define AUTONEG_SPEED 0x1
629#define AUTONEG_FLOW_CTRL 0x2
630
631 u32 req_line_speed;
632/* link settings - missing defines */
633#define SPEED_12000 12000
634#define SPEED_12500 12500
635#define SPEED_13000 13000
636#define SPEED_15000 15000
637#define SPEED_16000 16000
638
639 u32 req_duplex;
640 u32 req_flow_ctrl;
641#define FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
642#define FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
643#define FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
644#define FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
645#define FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
646
647 u32 pause_mode;
648#define PAUSE_NONE 0
649#define PAUSE_SYMMETRIC 1
650#define PAUSE_ASYMMETRIC 2
651#define PAUSE_BOTH 3
652
653 u32 advertising;
654/* link settings - missing defines */
655#define ADVERTISED_2500baseT_Full (1 << 15)
656#define ADVERTISED_CX4 (1 << 16)
657
658 u32 link_status;
659 u32 line_speed;
660 u32 duplex;
661 u32 flow_ctrl;
662
663 u32 bc_ver;
664
665 int flash_size;
666#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
667#define NVRAM_TIMEOUT_COUNT 30000
668#define NVRAM_PAGE_SIZE 256
669
670 int rx_ring_size;
671
672 u16 tx_quick_cons_trip_int;
673 u16 tx_quick_cons_trip;
674 u16 tx_ticks_int;
675 u16 tx_ticks;
676
677 u16 rx_quick_cons_trip_int;
678 u16 rx_quick_cons_trip;
679 u16 rx_ticks_int;
680 u16 rx_ticks;
681
682 u32 stats_ticks;
683
684 int state;
685#define BNX2X_STATE_CLOSED 0x0
686#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
687#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
688#define BNX2X_STATE_OPEN 0x3000
689#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
690#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
691#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
692#define BNX2X_STATE_ERROR 0xF000
693
694 int num_queues;
695
696 u32 rx_mode;
697#define BNX2X_RX_MODE_NONE 0
698#define BNX2X_RX_MODE_NORMAL 1
699#define BNX2X_RX_MODE_ALLMULTI 2
700#define BNX2X_RX_MODE_PROMISC 3
701#define BNX2X_MAX_MULTICAST 64
702#define BNX2X_MAX_EMUL_MULTI 16
703
704 dma_addr_t def_status_blk_mapping;
705
706 struct bnx2x_slowpath *slowpath;
707 dma_addr_t slowpath_mapping;
708
709#ifdef BCM_ISCSI
710 void *t1;
711 dma_addr_t t1_mapping;
712 void *t2;
713 dma_addr_t t2_mapping;
714 void *timers;
715 dma_addr_t timers_mapping;
716 void *qm;
717 dma_addr_t qm_mapping;
718#endif
719
720 char *name;
721 u16 bus_speed_mhz;
722 u8 wol;
723 u8 pad;
724
725 /* used to synchronize stats collecting */
726 int stats_state;
727#define STATS_STATE_DISABLE 0
728#define STATS_STATE_ENABLE 1
729#define STATS_STATE_STOP 2 /* stop stats on next iteration */
730
731 /* used by dmae command loader */
732 struct dmae_command dmae;
733 int executer_idx;
734
735 u32 old_brb_discard;
736 struct bmac_stats old_bmac;
737 struct tstorm_per_client_stats old_tclient;
738 struct z_stream_s *strm;
739 void *gunzip_buf;
740 dma_addr_t gunzip_mapping;
741 int gunzip_outlen;
742#define FW_BUF_SIZE 0x8000
743
744};
745
746
747/* DMAE command defines */
748#define DMAE_CMD_SRC_PCI 0
749#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
750
751#define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
752#define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
753
754#define DMAE_CMD_C_DST_PCI 0
755#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
756
757#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
758
759#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
760#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
761#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
762#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
763
764#define DMAE_CMD_PORT_0 0
765#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
766
767#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
768#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
769
770#define DMAE_LEN32_MAX 0x400
771
772
773/* MC hsi */
774#define RX_COPY_THRESH 92
775#define BCM_PAGE_BITS 12
776#define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS)
777
778#define NUM_TX_RINGS 16
779#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
780#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
781#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
782#define MAX_TX_BD (NUM_TX_BD - 1)
783#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
784#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
785 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
786#define TX_BD(x) ((x) & MAX_TX_BD)
787#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
788
789/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
790#define NUM_RX_RINGS 8
791#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
792#define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
793#define RX_DESC_MASK (RX_DESC_CNT - 1)
794#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
795#define MAX_RX_BD (NUM_RX_BD - 1)
796#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
797#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
798 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
799#define RX_BD(x) ((x) & MAX_RX_BD)
800
801#define NUM_RCQ_RINGS (NUM_RX_RINGS * 2)
802#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
803#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
804#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
805#define MAX_RCQ_BD (NUM_RCQ_BD - 1)
806#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
807#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
808 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
809#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
810
811
812/* used on a CID received from the HW */
813#define SW_CID(x) (le32_to_cpu(x) & \
814 (COMMON_RAMROD_ETH_RX_CQE_CID >> 1))
815#define CQE_CMD(x) (le32_to_cpu(x) >> \
816 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
817
818#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
819 le32_to_cpu((bd)->addr_lo))
820#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
821
822
823#define STROM_ASSERT_ARRAY_SIZE 50
824
825
826#define MDIO_INDIRECT_REG_ADDR 0x1f
827#define MDIO_SET_REG_BANK(bp, reg_bank) \
828 bnx2x_mdio22_write(bp, MDIO_INDIRECT_REG_ADDR, reg_bank)
829
830#define MDIO_ACCESS_TIMEOUT 1000
831
832
833/* must be used on a CID before placing it on a HW ring */
834#define HW_CID(bp, x) (x | (bp->port << 23))
835
836#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
837#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
838
839#define ATTN_NIG_FOR_FUNC (1L << 8)
840#define ATTN_SW_TIMER_4_FUNC (1L << 9)
841#define GPIO_2_FUNC (1L << 10)
842#define GPIO_3_FUNC (1L << 11)
843#define GPIO_4_FUNC (1L << 12)
844#define ATTN_GENERAL_ATTN_1 (1L << 13)
845#define ATTN_GENERAL_ATTN_2 (1L << 14)
846#define ATTN_GENERAL_ATTN_3 (1L << 15)
847#define ATTN_GENERAL_ATTN_4 (1L << 13)
848#define ATTN_GENERAL_ATTN_5 (1L << 14)
849#define ATTN_GENERAL_ATTN_6 (1L << 15)
850
851#define ATTN_HARD_WIRED_MASK 0xff00
852#define ATTENTION_ID 4
853
854
855#define BNX2X_BTR 3
856#define MAX_SPQ_PENDING 8
857
858
859#define BNX2X_NUM_STATS 31
860#define BNX2X_NUM_TESTS 2
861
862
863#define DPM_TRIGER_TYPE 0x40
864#define DOORBELL(bp, cid, val) \
865 do { \
866 writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
867 DPM_TRIGER_TYPE); \
868 } while (0)
869
870
871/* stuff added to make the code fit 80Col */
872
873#define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
874#define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
875#define TPA_TYPE(cqe) (cqe->fast_path_cqe.error_type_flags & \
876 (TPA_TYPE_START | TPA_TYPE_END))
877#define BNX2X_RX_SUM_OK(cqe) \
878 (!(cqe->fast_path_cqe.status_flags & \
879 (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \
880 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)))
881
882#define BNX2X_RX_SUM_FIX(cqe) \
883 ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
884 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
885 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
886
887
888#define MDIO_AN_CL73_OR_37_COMPLETE \
889 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
890 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
891
892#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
893 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
894#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
895 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
896#define GP_STATUS_SPEED_MASK \
897 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
898#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
899#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
900#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
901#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
902#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
903#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
904#define GP_STATUS_10G_HIG \
905 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
906#define GP_STATUS_10G_CX4 \
907 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
908#define GP_STATUS_12G_HIG \
909 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
910#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
911#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
912#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
913#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
914#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
915#define GP_STATUS_10G_KX4 \
916 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
917
918#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
919#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
920#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
921#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
922#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
923#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
924#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
925#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
926#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
927#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
928#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
929#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
930#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
931#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
932#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
933#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
934#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
935#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
936#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
937#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
938#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
939#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
940#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
941
942#define NIG_STATUS_INTERRUPT_XGXS0_LINK10G \
943 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
944#define NIG_XGXS0_LINK_STATUS \
945 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
946#define NIG_XGXS0_LINK_STATUS_SIZE \
947 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
948#define NIG_SERDES0_LINK_STATUS \
949 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
950#define NIG_MASK_MI_INT \
951 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
952#define NIG_MASK_XGXS0_LINK10G \
953 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
954#define NIG_MASK_XGXS0_LINK_STATUS \
955 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
956#define NIG_MASK_SERDES0_LINK_STATUS \
957 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
958
959#define XGXS_RESET_BITS \
960 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
961 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
962 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
963 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
964 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
965
966#define SERDES_RESET_BITS \
967 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
968 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
969 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
970 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
971
972
973#define BNX2X_MC_ASSERT_BITS \
974 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
975 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
976 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
977 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
978
979#define BNX2X_MCP_ASSERT \
980 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
981
982#define BNX2X_DOORQ_ASSERT \
983 AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
984
985#define HW_INTERRUT_ASSERT_SET_0 \
986 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
987 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
988 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
989 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
990#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
991 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
992 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
993 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
994 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
995#define HW_INTERRUT_ASSERT_SET_1 \
996 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
997 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
998 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
999 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1000 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1001 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1002 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1003 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1004 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1005 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1006 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1007#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1008 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1009 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1010 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1011 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1012 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1013 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1014 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1015 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1016 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1017 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1018#define HW_INTERRUT_ASSERT_SET_2 \
1019 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1020 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1021 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1022 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1023 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1024#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1025 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1026 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1027 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1028 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1029 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1030 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1031
1032
1033#define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \
1034 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \
1035 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)
1036
1037
1038#define MULTI_FLAGS \
1039 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1040 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1041 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1042 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1043 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE)
1044
1045#define MULTI_MASK 0x7f
1046
1047
1048#define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
1049#define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
1050#define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
1051
1052#define BNX2X_RX_SB_INDEX \
1053 &fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX]
1054
1055#define BNX2X_TX_SB_INDEX \
1056 &fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX]
1057
1058#define BNX2X_SP_DSB_INDEX \
1059&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX]
1060
1061
1062#define CAM_IS_INVALID(x) \
1063(x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1064
1065#define CAM_INVALIDATE(x) \
1066x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE
1067
1068
1069/* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1070
1071#endif /* bnx2x.h */
diff --git a/drivers/net/bnx2x_fw_defs.h b/drivers/net/bnx2x_fw_defs.h
new file mode 100644
index 000000000000..62a6eb81025a
--- /dev/null
+++ b/drivers/net/bnx2x_fw_defs.h
@@ -0,0 +1,198 @@
1/* bnx2x_fw_defs.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10
11#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
12 (0x1922 + (port * 0x40) + (index * 0x4))
13#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
14 (0x1900 + (port * 0x40))
15#define CSTORM_HC_BTR_OFFSET(port)\
16 (0x1984 + (port * 0xc0))
17#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index)\
18 (0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
19#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index)\
20 (0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
21#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id)\
22 (0x1400 + (port * 0x280) + (cpu_id * 0x28))
23#define CSTORM_STATS_FLAGS_OFFSET(port) (0x5108 + (port * 0x8))
24#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id)\
25 (0x1510 + (port * 0x240) + (client_id * 0x20))
26#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
27 (0x138a + (port * 0x28) + (index * 0x4))
28#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
29 (0x1370 + (port * 0x28))
30#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port)\
31 (0x4b70 + (port * 0x8))
32#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function)\
33 (0x1418 + (function * 0x30))
34#define TSTORM_HC_BTR_OFFSET(port)\
35 (0x13c4 + (port * 0x18))
36#define TSTORM_INDIRECTION_TABLE_OFFSET(port)\
37 (0x22c8 + (port * 0x80))
38#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
39#define TSTORM_MAC_FILTER_CONFIG_OFFSET(port)\
40 (0x1420 + (port * 0x30))
41#define TSTORM_RCQ_PROD_OFFSET(port, client_id)\
42 (0x1508 + (port * 0x240) + (client_id * 0x20))
43#define TSTORM_STATS_FLAGS_OFFSET(port) (0x4b90 + (port * 0x8))
44#define USTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
45 (0x191a + (port * 0x28) + (index * 0x4))
46#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
47 (0x1900 + (port * 0x28))
48#define USTORM_HC_BTR_OFFSET(port)\
49 (0x1954 + (port * 0xb8))
50#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(port)\
51 (0x5408 + (port * 0x8))
52#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index)\
53 (0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
54#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index)\
55 (0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
56#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id)\
57 (0x1400 + (port * 0x280) + (cpu_id * 0x28))
58#define XSTORM_ASSERT_LIST_INDEX_OFFSET 0x1000
59#define XSTORM_ASSERT_LIST_OFFSET(idx) (0x1020 + (idx * 0x10))
60#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
61 (0x141a + (port * 0x28) + (index * 0x4))
62#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
63 (0x1400 + (port * 0x28))
64#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port)\
65 (0x5408 + (port * 0x8))
66#define XSTORM_HC_BTR_OFFSET(port)\
67 (0x1454 + (port * 0x18))
68#define XSTORM_SPQ_PAGE_BASE_OFFSET(port)\
69 (0x5328 + (port * 0x18))
70#define XSTORM_SPQ_PROD_OFFSET(port)\
71 (0x5330 + (port * 0x18))
72#define XSTORM_STATS_FLAGS_OFFSET(port) (0x53f8 + (port * 0x8))
73#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
74
75/**
76* This file defines HSI constatnts for the ETH flow
77*/
78
79/* hash types */
80#define DEFAULT_HASH_TYPE 0
81#define IPV4_HASH_TYPE 1
82#define TCP_IPV4_HASH_TYPE 2
83#define IPV6_HASH_TYPE 3
84#define TCP_IPV6_HASH_TYPE 4
85
86/* values of command IDs in the ramrod message */
87#define RAMROD_CMD_ID_ETH_PORT_SETUP (80)
88#define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85)
89#define RAMROD_CMD_ID_ETH_STAT_QUERY (90)
90#define RAMROD_CMD_ID_ETH_UPDATE (100)
91#define RAMROD_CMD_ID_ETH_HALT (105)
92#define RAMROD_CMD_ID_ETH_SET_MAC (110)
93#define RAMROD_CMD_ID_ETH_CFC_DEL (115)
94#define RAMROD_CMD_ID_ETH_PORT_DEL (120)
95#define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125)
96
97
98/* command values for set mac command */
99#define T_ETH_MAC_COMMAND_SET 0
100#define T_ETH_MAC_COMMAND_INVALIDATE 1
101
102#define T_ETH_INDIRECTION_TABLE_SIZE 128
103
104/* Maximal L2 clients supported */
105#define ETH_MAX_RX_CLIENTS (18)
106
107/**
108* This file defines HSI constatnts common to all microcode flows
109*/
110
111/* Connection types */
112#define ETH_CONNECTION_TYPE 0
113
114#define PROTOCOL_STATE_BIT_OFFSET 6
115
116#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
117
118/* microcode fixed page page size 4K (chains and ring segments) */
119#define MC_PAGE_SIZE (4096)
120
121/* Host coalescing constants */
122
123/* IGU constants */
124#define IGU_PORT_BASE 0x0400
125
126#define IGU_ADDR_MSIX 0x0000
127#define IGU_ADDR_INT_ACK 0x0200
128#define IGU_ADDR_PROD_UPD 0x0201
129#define IGU_ADDR_ATTN_BITS_UPD 0x0202
130#define IGU_ADDR_ATTN_BITS_SET 0x0203
131#define IGU_ADDR_ATTN_BITS_CLR 0x0204
132#define IGU_ADDR_COALESCE_NOW 0x0205
133#define IGU_ADDR_SIMD_MASK 0x0206
134#define IGU_ADDR_SIMD_NOMASK 0x0207
135#define IGU_ADDR_MSI_CTL 0x0210
136#define IGU_ADDR_MSI_ADDR_LO 0x0211
137#define IGU_ADDR_MSI_ADDR_HI 0x0212
138#define IGU_ADDR_MSI_DATA 0x0213
139
140#define IGU_INT_ENABLE 0
141#define IGU_INT_DISABLE 1
142#define IGU_INT_NOP 2
143#define IGU_INT_NOP2 3
144
145/* index numbers */
146#define HC_USTORM_DEF_SB_NUM_INDICES 4
147#define HC_CSTORM_DEF_SB_NUM_INDICES 8
148#define HC_XSTORM_DEF_SB_NUM_INDICES 4
149#define HC_TSTORM_DEF_SB_NUM_INDICES 4
150#define HC_USTORM_SB_NUM_INDICES 4
151#define HC_CSTORM_SB_NUM_INDICES 4
152
153/* index values - which counterto update */
154
155#define HC_INDEX_U_ETH_RX_CQ_CONS 1
156
157#define HC_INDEX_C_ETH_TX_CQ_CONS 1
158
159#define HC_INDEX_DEF_X_SPQ_CONS 0
160
161#define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
162#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
163
164/* used by the driver to get the SB offset */
165#define USTORM_ID 0
166#define CSTORM_ID 1
167#define XSTORM_ID 2
168#define TSTORM_ID 3
169#define ATTENTION_ID 4
170
171/* max number of slow path commands per port */
172#define MAX_RAMRODS_PER_PORT (8)
173
174/* values for RX ETH CQE type field */
175#define RX_ETH_CQE_TYPE_ETH_FASTPATH (0)
176#define RX_ETH_CQE_TYPE_ETH_RAMROD (1)
177
178/* MAC address list size */
179#define T_MAC_ADDRESS_LIST_SIZE (96)
180
181#define XSTORM_IP_ID_ROLL_HALF 0x8000
182#define XSTORM_IP_ID_ROLL_ALL 0
183
184#define FW_LOG_LIST_SIZE (50)
185
186#define NUM_OF_PROTOCOLS 4
187#define MAX_COS_NUMBER 16
188#define MAX_T_STAT_COUNTER_ID 18
189
190#define T_FAIR 1
191#define FAIR_MEM 2
192#define RS_PERIODIC_TIMEOUT_IN_SDM_TICS 25
193
194#define UNKNOWN_ADDRESS 0
195#define UNICAST_ADDRESS 1
196#define MULTICAST_ADDRESS 2
197#define BROADCAST_ADDRESS 3
198
diff --git a/drivers/net/bnx2x_hsi.h b/drivers/net/bnx2x_hsi.h
new file mode 100644
index 000000000000..6fd959c34d1f
--- /dev/null
+++ b/drivers/net/bnx2x_hsi.h
@@ -0,0 +1,2176 @@
1/* bnx2x_hsi.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10
11#define FUNC_0 0
12#define FUNC_1 1
13#define FUNC_MAX 2
14
15
16/* This value (in milliseconds) determines the frequency of the driver
17 * issuing the PULSE message code. The firmware monitors this periodic
18 * pulse to determine when to switch to an OS-absent mode. */
19#define DRV_PULSE_PERIOD_MS 250
20
21/* This value (in milliseconds) determines how long the driver should
22 * wait for an acknowledgement from the firmware before timing out. Once
23 * the firmware has timed out, the driver will assume there is no firmware
24 * running and there won't be any firmware-driver synchronization during a
25 * driver reset. */
26#define FW_ACK_TIME_OUT_MS 5000
27
28#define FW_ACK_POLL_TIME_MS 1
29
30#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
31
32/* LED Blink rate that will achieve ~15.9Hz */
33#define LED_BLINK_RATE_VAL 480
34
35/****************************************************************************
36 * Driver <-> FW Mailbox *
37 ****************************************************************************/
38struct drv_fw_mb {
39 u32 drv_mb_header;
40#define DRV_MSG_CODE_MASK 0xffff0000
41#define DRV_MSG_CODE_LOAD_REQ 0x10000000
42#define DRV_MSG_CODE_LOAD_DONE 0x11000000
43#define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
44#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
45#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
46#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
47#define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
48#define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
49#define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
50#define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
51#define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
52#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
53#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
54
55#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
56
57 u32 drv_mb_param;
58
59 u32 fw_mb_header;
60#define FW_MSG_CODE_MASK 0xffff0000
61#define FW_MSG_CODE_DRV_LOAD_COMMON 0x11000000
62#define FW_MSG_CODE_DRV_LOAD_PORT 0x12000000
63#define FW_MSG_CODE_DRV_LOAD_REFUSED 0x13000000
64#define FW_MSG_CODE_DRV_LOAD_DONE 0x14000000
65#define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x21000000
66#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x22000000
67#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x23000000
68#define FW_MSG_CODE_DIAG_ENTER_DONE 0x50000000
69#define FW_MSG_CODE_DIAG_REFUSE 0x51000000
70#define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70000000
71#define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x71000000
72#define FW_MSG_CODE_GET_KEY_DONE 0x80000000
73#define FW_MSG_CODE_NO_KEY 0x8f000000
74#define FW_MSG_CODE_LIC_INFO_NOT_READY 0x8f800000
75#define FW_MSG_CODE_L2B_PRAM_LOADED 0x90000000
76#define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x91000000
77#define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x92000000
78#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x93000000
79#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x94000000
80
81#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
82
83 u32 fw_mb_param;
84
85 u32 link_status;
86 /* Driver should update this field on any link change event */
87
88#define LINK_STATUS_LINK_FLAG_MASK 0x00000001
89#define LINK_STATUS_LINK_UP 0x00000001
90#define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
91#define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
92#define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
93#define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
94#define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
95#define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
96#define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
97#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
98#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
99#define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
100#define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
101#define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
102#define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
103#define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
104#define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
105#define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1)
106#define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1)
107#define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1)
108#define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1)
109#define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1)
110#define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1)
111#define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1)
112#define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1)
113#define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1)
114#define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1)
115
116#define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
117#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
118
119#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
120#define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
121#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
122
123#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
124#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
125#define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
126#define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
127#define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
128#define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
129#define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
130
131#define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
132#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
133
134#define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
135#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
136
137#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
138#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
139#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
140#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
141#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
142
143#define LINK_STATUS_SERDES_LINK 0x00100000
144
145#define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
146#define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
147#define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
148#define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000
149#define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000
150#define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000
151#define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
152#define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
153
154 u32 drv_pulse_mb;
155#define DRV_PULSE_SEQ_MASK 0x00007fff
156#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
157 /* The system time is in the format of
158 * (year-2001)*12*32 + month*32 + day. */
159#define DRV_PULSE_ALWAYS_ALIVE 0x00008000
160 /* Indicate to the firmware not to go into the
161 * OS-absent when it is not getting driver pulse.
162 * This is used for debugging as well for PXE(MBA). */
163
164 u32 mcp_pulse_mb;
165#define MCP_PULSE_SEQ_MASK 0x00007fff
166#define MCP_PULSE_ALWAYS_ALIVE 0x00008000
167 /* Indicates to the driver not to assert due to lack
168 * of MCP response */
169#define MCP_EVENT_MASK 0xffff0000
170#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
171
172};
173
174
175/****************************************************************************
176 * Shared HW configuration *
177 ****************************************************************************/
178struct shared_hw_cfg { /* NVRAM Offset */
179 /* Up to 16 bytes of NULL-terminated string */
180 u8 part_num[16]; /* 0x104 */
181
182 u32 config; /* 0x114 */
183#define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
184#define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
185#define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
186#define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
187#define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
188
189#define SHARED_HW_CFG_PORT_SWAP 0x00000004
190
191#define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
192
193#define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
194#define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
195 /* Whatever MFW found in NVM
196 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
197#define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
198#define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
199#define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
200#define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
201 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
202 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
203#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
204 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
205 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
206#define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
207 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
208 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
209#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
210
211#define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
212#define SHARED_HW_CFG_LED_MODE_SHIFT 16
213#define SHARED_HW_CFG_LED_MAC1 0x00000000
214#define SHARED_HW_CFG_LED_PHY1 0x00010000
215#define SHARED_HW_CFG_LED_PHY2 0x00020000
216#define SHARED_HW_CFG_LED_PHY3 0x00030000
217#define SHARED_HW_CFG_LED_MAC2 0x00040000
218#define SHARED_HW_CFG_LED_PHY4 0x00050000
219#define SHARED_HW_CFG_LED_PHY5 0x00060000
220#define SHARED_HW_CFG_LED_PHY6 0x00070000
221#define SHARED_HW_CFG_LED_MAC3 0x00080000
222#define SHARED_HW_CFG_LED_PHY7 0x00090000
223#define SHARED_HW_CFG_LED_PHY9 0x000a0000
224#define SHARED_HW_CFG_LED_PHY11 0x000b0000
225#define SHARED_HW_CFG_LED_MAC4 0x000c0000
226#define SHARED_HW_CFG_LED_PHY8 0x000d0000
227
228#define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
229#define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
230#define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
231#define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
232#define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
233#define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
234#define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
235#define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
236
237 u32 config2; /* 0x118 */
238 /* one time auto detect grace period (in sec) */
239#define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
240#define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
241
242#define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
243
244 /* The default value for the core clock is 250MHz and it is
245 achieved by setting the clock change to 4 */
246#define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
247#define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
248
249#define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
250#define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
251
252#define SHARED_HW_CFG_HIDE_FUNC1 0x00002000
253
254 u32 power_dissipated; /* 0x11c */
255#define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
256#define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
257
258#define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
259#define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
260#define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
261#define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
262#define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
263#define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
264
265 u32 ump_nc_si_config; /* 0x120 */
266#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
267#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
268#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
269#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
270#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
271#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
272
273#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
274#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
275
276#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
277#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
278#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
279#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
280
281 u32 board; /* 0x124 */
282#define SHARED_HW_CFG_BOARD_TYPE_MASK 0x0000ffff
283#define SHARED_HW_CFG_BOARD_TYPE_SHIFT 0
284#define SHARED_HW_CFG_BOARD_TYPE_NONE 0x00000000
285#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1000 0x00000001
286#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1001 0x00000002
287#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G 0x00000003
288#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1004G 0x00000004
289#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1007G 0x00000005
290#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1015G 0x00000006
291#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1020G 0x00000007
292#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008
293
294#define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000
295#define SHARED_HW_CFG_BOARD_VER_SHIFT 16
296#define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0xf0000000
297#define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 28
298#define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0x0f000000
299#define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 24
300#define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
301#define SHARED_HW_CFG_BOARD_REV_SHIFT 16
302
303 u32 reserved; /* 0x128 */
304
305};
306
307/****************************************************************************
308 * Port HW configuration *
309 ****************************************************************************/
310struct port_hw_cfg { /* function 0: 0x12c-0x2bb, function 1: 0x2bc-0x44b */
311
312 /* Fields below are port specific (in anticipation of dual port
313 devices */
314 u32 pci_id;
315#define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
316#define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
317
318 u32 pci_sub_id;
319#define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
320#define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
321
322 u32 power_dissipated;
323#define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
324#define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
325#define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
326#define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
327#define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
328#define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
329#define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
330#define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
331
332 u32 power_consumed;
333#define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
334#define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
335#define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
336#define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
337#define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
338#define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
339#define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
340#define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
341
342 u32 mac_upper;
343#define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
344#define PORT_HW_CFG_UPPERMAC_SHIFT 0
345 u32 mac_lower;
346
347 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */
348 u32 iscsi_mac_lower;
349
350 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */
351 u32 rdma_mac_lower;
352
353 u32 serdes_config;
354 /* for external PHY, or forced mode or during AN */
355#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
356#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 16
357
358#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0x0000ffff
359#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 0
360
361 u16 serdes_tx_driver_pre_emphasis[16];
362 u16 serdes_rx_driver_equalizer[16];
363
364 u32 xgxs_config_lane0;
365 u32 xgxs_config_lane1;
366 u32 xgxs_config_lane2;
367 u32 xgxs_config_lane3;
368 /* for external PHY, or forced mode or during AN */
369#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
370#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_SHIFT 16
371
372#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_MASK 0x0000ffff
373#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_SHIFT 0
374
375 u16 xgxs_tx_driver_pre_emphasis_lane0[16];
376 u16 xgxs_tx_driver_pre_emphasis_lane1[16];
377 u16 xgxs_tx_driver_pre_emphasis_lane2[16];
378 u16 xgxs_tx_driver_pre_emphasis_lane3[16];
379
380 u16 xgxs_rx_driver_equalizer_lane0[16];
381 u16 xgxs_rx_driver_equalizer_lane1[16];
382 u16 xgxs_rx_driver_equalizer_lane2[16];
383 u16 xgxs_rx_driver_equalizer_lane3[16];
384
385 u32 lane_config;
386#define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
387#define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
388#define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
389#define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
390#define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
391#define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
392#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
393#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
394 /* AN and forced */
395#define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
396 /* forced only */
397#define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
398 /* forced only */
399#define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
400 /* forced only */
401#define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
402
403 u32 external_phy_config;
404#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
405#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
406#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
407#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
408#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
409
410#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
411#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
412
413#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
414#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
415#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
416#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
417#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
418#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
419#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
420#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
421#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8276 0x00000600
422#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
423#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
424
425#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
426#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
427
428 u32 speed_capability_mask;
429#define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
430#define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
431#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
432#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
433#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
434#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
435#define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
436#define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
437#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
438#define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G 0x00800000
439#define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G 0x01000000
440#define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G 0x02000000
441#define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G 0x04000000
442#define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G 0x08000000
443#define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
444
445#define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
446#define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
447#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
448#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
449#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
450#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
451#define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
452#define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
453#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
454#define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G 0x00000080
455#define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G 0x00000100
456#define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G 0x00000200
457#define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G 0x00000400
458#define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800
459#define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
460
461 u32 reserved[2];
462
463};
464
465/****************************************************************************
466 * Shared Feature configuration *
467 ****************************************************************************/
468struct shared_feat_cfg { /* NVRAM Offset */
469 u32 bmc_common; /* 0x450 */
470#define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
471
472};
473
474
475/****************************************************************************
476 * Port Feature configuration *
477 ****************************************************************************/
478struct port_feat_cfg { /* function 0: 0x454-0x4c7, function 1: 0x4c8-0x53b */
479 u32 config;
480#define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
481#define PORT_FEATURE_BAR1_SIZE_SHIFT 0
482#define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
483#define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
484#define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
485#define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
486#define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
487#define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
488#define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
489#define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
490#define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
491#define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
492#define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
493#define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
494#define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
495#define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
496#define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
497#define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
498#define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
499#define PORT_FEATURE_BAR2_SIZE_SHIFT 4
500#define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
501#define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
502#define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
503#define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
504#define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
505#define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
506#define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
507#define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
508#define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
509#define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
510#define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
511#define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
512#define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
513#define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
514#define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
515#define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
516#define PORT_FEATURE_EN_SIZE_MASK 0x07000000
517#define PORT_FEATURE_EN_SIZE_SHIFT 24
518#define PORT_FEATURE_WOL_ENABLED 0x01000000
519#define PORT_FEATURE_MBA_ENABLED 0x02000000
520#define PORT_FEATURE_MFW_ENABLED 0x04000000
521
522 u32 wol_config;
523 /* Default is used when driver sets to "auto" mode */
524#define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
525#define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
526#define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
527#define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
528#define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
529#define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
530#define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
531#define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
532#define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
533
534 u32 mba_config;
535#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000003
536#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
537#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
538#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
539#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
540#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
541#define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
542#define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
543#define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
544#define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
545#define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
546#define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
547#define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
548#define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
549#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
550#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
551#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
552#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
553#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
554#define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
555#define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
556#define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
557#define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
558#define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
559#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
560#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
561#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
562#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
563#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
564#define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
565#define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
566#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
567#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
568#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
569#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
570#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
571#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
572#define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
573#define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
574#define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
575#define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
576#define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
577#define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
578#define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
579#define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
580#define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
581#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
582#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4 0x20000000
583#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR 0x24000000
584#define PORT_FEATURE_MBA_LINK_SPEED_12GBPS 0x28000000
585#define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS 0x2c000000
586#define PORT_FEATURE_MBA_LINK_SPEED_13GBPS 0x30000000
587#define PORT_FEATURE_MBA_LINK_SPEED_15GBPS 0x34000000
588#define PORT_FEATURE_MBA_LINK_SPEED_16GBPS 0x38000000
589
590 u32 bmc_config;
591#define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
592#define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
593
594 u32 mba_vlan_cfg;
595#define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
596#define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
597#define PORT_FEATURE_MBA_VLAN_EN 0x00010000
598
599 u32 resource_cfg;
600#define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
601#define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
602#define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
603#define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
604#define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
605
606 u32 smbus_config;
607 /* Obsolete */
608#define PORT_FEATURE_SMBUS_EN 0x00000001
609#define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
610#define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
611
612 u32 iscsib_boot_cfg;
613#define PORT_FEATURE_ISCSIB_SKIP_TARGET_BOOT 0x00000001
614
615 u32 link_config; /* Used as HW defaults for the driver */
616#define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
617#define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
618 /* (forced) low speed switch (< 10G) */
619#define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
620 /* (forced) high speed switch (>= 10G) */
621#define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
622#define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
623#define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
624
625#define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
626#define PORT_FEATURE_LINK_SPEED_SHIFT 16
627#define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
628#define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
629#define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
630#define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
631#define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
632#define PORT_FEATURE_LINK_SPEED_1G 0x00050000
633#define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
634#define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
635#define PORT_FEATURE_LINK_SPEED_10G_KX4 0x00080000
636#define PORT_FEATURE_LINK_SPEED_10G_KR 0x00090000
637#define PORT_FEATURE_LINK_SPEED_12G 0x000a0000
638#define PORT_FEATURE_LINK_SPEED_12_5G 0x000b0000
639#define PORT_FEATURE_LINK_SPEED_13G 0x000c0000
640#define PORT_FEATURE_LINK_SPEED_15G 0x000d0000
641#define PORT_FEATURE_LINK_SPEED_16G 0x000e0000
642
643#define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
644#define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
645#define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
646#define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
647#define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
648#define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
649#define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
650
651 /* The default for MCP link configuration,
652 uses the same defines as link_config */
653 u32 mfw_wol_link_cfg;
654
655 u32 reserved[19];
656
657};
658
659
660/****************************************************************************
661 * Device Information *
662 ****************************************************************************/
663struct dev_info { /* size */
664
665 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
666
667 struct shared_hw_cfg shared_hw_config; /* 40 */
668
669 struct port_hw_cfg port_hw_config[FUNC_MAX]; /* 400*2=800 */
670
671 struct shared_feat_cfg shared_feature_config; /* 4 */
672
673 struct port_feat_cfg port_feature_config[FUNC_MAX];/* 116*2=232 */
674
675};
676
677
678/****************************************************************************
679 * Management firmware state *
680 ****************************************************************************/
681/* Allocate 320 bytes for management firmware: still not known exactly
682 * how much IMD needs. */
683#define MGMTFW_STATE_WORD_SIZE 80
684
685struct mgmtfw_state {
686 u32 opaque[MGMTFW_STATE_WORD_SIZE];
687};
688
689
690/****************************************************************************
691 * Shared Memory Region *
692 ****************************************************************************/
693struct shmem_region { /* SharedMem Offset (size) */
694 u32 validity_map[FUNC_MAX]; /* 0x0 (4 * 2 = 0x8) */
695#define SHR_MEM_VALIDITY_PCI_CFG 0x00000001
696#define SHR_MEM_VALIDITY_MB 0x00000002
697#define SHR_MEM_VALIDITY_DEV_INFO 0x00000004
698 /* One licensing bit should be set */
699#define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
700#define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
701#define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
702#define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
703
704 struct drv_fw_mb drv_fw_mb[FUNC_MAX]; /* 0x8 (28 * 2 = 0x38) */
705
706 struct dev_info dev_info; /* 0x40 (0x438) */
707
708#ifdef _LICENSE_H
709 license_key_t drv_lic_key[FUNC_MAX]; /* 0x478 (52 * 2 = 0x68) */
710#else /* Linux! */
711 u8 reserved[52*FUNC_MAX];
712#endif
713
714 /* FW information (for internal FW use) */
715 u32 fw_info_fio_offset; /* 0x4e0 (0x4) */
716 struct mgmtfw_state mgmtfw_state; /* 0x4e4 (0x140) */
717
718}; /* 0x624 */
719
720
721#define BCM_5710_FW_MAJOR_VERSION 4
722#define BCM_5710_FW_MINOR_VERSION 0
723#define BCM_5710_FW_REVISION_VERSION 14
724#define BCM_5710_FW_COMPILE_FLAGS 1
725
726
727/*
728 * attention bits
729 */
730struct atten_def_status_block {
731 u32 attn_bits;
732 u32 attn_bits_ack;
733#if defined(__BIG_ENDIAN)
734 u16 attn_bits_index;
735 u8 reserved0;
736 u8 status_block_id;
737#elif defined(__LITTLE_ENDIAN)
738 u8 status_block_id;
739 u8 reserved0;
740 u16 attn_bits_index;
741#endif
742 u32 reserved1;
743};
744
745
746/*
747 * common data for all protocols
748 */
749struct doorbell_hdr {
750 u8 header;
751#define DOORBELL_HDR_RX (0x1<<0)
752#define DOORBELL_HDR_RX_SHIFT 0
753#define DOORBELL_HDR_DB_TYPE (0x1<<1)
754#define DOORBELL_HDR_DB_TYPE_SHIFT 1
755#define DOORBELL_HDR_DPM_SIZE (0x3<<2)
756#define DOORBELL_HDR_DPM_SIZE_SHIFT 2
757#define DOORBELL_HDR_CONN_TYPE (0xF<<4)
758#define DOORBELL_HDR_CONN_TYPE_SHIFT 4
759};
760
761/*
762 * doorbell message send to the chip
763 */
764struct doorbell {
765#if defined(__BIG_ENDIAN)
766 u16 zero_fill2;
767 u8 zero_fill1;
768 struct doorbell_hdr header;
769#elif defined(__LITTLE_ENDIAN)
770 struct doorbell_hdr header;
771 u8 zero_fill1;
772 u16 zero_fill2;
773#endif
774};
775
776
777/*
778 * IGU driver acknowlegement register
779 */
780struct igu_ack_register {
781#if defined(__BIG_ENDIAN)
782 u16 sb_id_and_flags;
783#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
784#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
785#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
786#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
787#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
788#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
789#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
790#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
791#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
792#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
793 u16 status_block_index;
794#elif defined(__LITTLE_ENDIAN)
795 u16 status_block_index;
796 u16 sb_id_and_flags;
797#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
798#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
799#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
800#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
801#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
802#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
803#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
804#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
805#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
806#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
807#endif
808};
809
810
811/*
812 * Parser parsing flags field
813 */
814struct parsing_flags {
815 u16 flags;
816#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
817#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
818#define PARSING_FLAGS_NUMBER_OF_NESTED_VLANS (0x3<<1)
819#define PARSING_FLAGS_NUMBER_OF_NESTED_VLANS_SHIFT 1
820#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
821#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
822#define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
823#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
824#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
825#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
826#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
827#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
828#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
829#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
830#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
831#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
832#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
833#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
834#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
835#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
836#define PARSING_FLAGS_LLC_SNAP (0x1<<13)
837#define PARSING_FLAGS_LLC_SNAP_SHIFT 13
838#define PARSING_FLAGS_RESERVED0 (0x3<<14)
839#define PARSING_FLAGS_RESERVED0_SHIFT 14
840};
841
842
843/*
844 * dmae command structure
845 */
846struct dmae_command {
847 u32 opcode;
848#define DMAE_COMMAND_SRC (0x1<<0)
849#define DMAE_COMMAND_SRC_SHIFT 0
850#define DMAE_COMMAND_DST (0x3<<1)
851#define DMAE_COMMAND_DST_SHIFT 1
852#define DMAE_COMMAND_C_DST (0x1<<3)
853#define DMAE_COMMAND_C_DST_SHIFT 3
854#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
855#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
856#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
857#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
858#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
859#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
860#define DMAE_COMMAND_ENDIANITY (0x3<<9)
861#define DMAE_COMMAND_ENDIANITY_SHIFT 9
862#define DMAE_COMMAND_PORT (0x1<<11)
863#define DMAE_COMMAND_PORT_SHIFT 11
864#define DMAE_COMMAND_CRC_RESET (0x1<<12)
865#define DMAE_COMMAND_CRC_RESET_SHIFT 12
866#define DMAE_COMMAND_SRC_RESET (0x1<<13)
867#define DMAE_COMMAND_SRC_RESET_SHIFT 13
868#define DMAE_COMMAND_DST_RESET (0x1<<14)
869#define DMAE_COMMAND_DST_RESET_SHIFT 14
870#define DMAE_COMMAND_RESERVED0 (0x1FFFF<<15)
871#define DMAE_COMMAND_RESERVED0_SHIFT 15
872 u32 src_addr_lo;
873 u32 src_addr_hi;
874 u32 dst_addr_lo;
875 u32 dst_addr_hi;
876#if defined(__BIG_ENDIAN)
877 u16 reserved1;
878 u16 len;
879#elif defined(__LITTLE_ENDIAN)
880 u16 len;
881 u16 reserved1;
882#endif
883 u32 comp_addr_lo;
884 u32 comp_addr_hi;
885 u32 comp_val;
886 u32 crc32;
887 u32 crc32_c;
888#if defined(__BIG_ENDIAN)
889 u16 crc16_c;
890 u16 crc16;
891#elif defined(__LITTLE_ENDIAN)
892 u16 crc16;
893 u16 crc16_c;
894#endif
895#if defined(__BIG_ENDIAN)
896 u16 reserved2;
897 u16 crc_t10;
898#elif defined(__LITTLE_ENDIAN)
899 u16 crc_t10;
900 u16 reserved2;
901#endif
902#if defined(__BIG_ENDIAN)
903 u16 xsum8;
904 u16 xsum16;
905#elif defined(__LITTLE_ENDIAN)
906 u16 xsum16;
907 u16 xsum8;
908#endif
909};
910
911
912struct double_regpair {
913 u32 regpair0_lo;
914 u32 regpair0_hi;
915 u32 regpair1_lo;
916 u32 regpair1_hi;
917};
918
919
920/*
921 * The eth Rx Buffer Descriptor
922 */
923struct eth_rx_bd {
924 u32 addr_lo;
925 u32 addr_hi;
926};
927
928/*
929 * The eth storm context of Ustorm
930 */
931struct ustorm_eth_st_context {
932#if defined(__BIG_ENDIAN)
933 u8 sb_index_number;
934 u8 status_block_id;
935 u8 __local_rx_bd_cons;
936 u8 __local_rx_bd_prod;
937#elif defined(__LITTLE_ENDIAN)
938 u8 __local_rx_bd_prod;
939 u8 __local_rx_bd_cons;
940 u8 status_block_id;
941 u8 sb_index_number;
942#endif
943#if defined(__BIG_ENDIAN)
944 u16 rcq_cons;
945 u16 rx_bd_cons;
946#elif defined(__LITTLE_ENDIAN)
947 u16 rx_bd_cons;
948 u16 rcq_cons;
949#endif
950 u32 rx_bd_page_base_lo;
951 u32 rx_bd_page_base_hi;
952 u32 rcq_base_address_lo;
953 u32 rcq_base_address_hi;
954#if defined(__BIG_ENDIAN)
955 u16 __num_of_returned_cqes;
956 u8 num_rss;
957 u8 flags;
958#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0)
959#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0
960#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
961#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
962#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA (0x1<<2)
963#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA_SHIFT 2
964#define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x1F<<3)
965#define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 3
966#elif defined(__LITTLE_ENDIAN)
967 u8 flags;
968#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0)
969#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0
970#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
971#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
972#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA (0x1<<2)
973#define USTORM_ETH_ST_CONTEXT_ENABLE_TPA_SHIFT 2
974#define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x1F<<3)
975#define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 3
976 u8 num_rss;
977 u16 __num_of_returned_cqes;
978#endif
979#if defined(__BIG_ENDIAN)
980 u16 mc_alignment_size;
981 u16 agg_threshold;
982#elif defined(__LITTLE_ENDIAN)
983 u16 agg_threshold;
984 u16 mc_alignment_size;
985#endif
986 struct eth_rx_bd __local_bd_ring[16];
987};
988
989/*
990 * The eth storm context of Tstorm
991 */
992struct tstorm_eth_st_context {
993 u32 __reserved0[28];
994};
995
996/*
997 * The eth aggregative context section of Xstorm
998 */
999struct xstorm_eth_extra_ag_context_section {
1000#if defined(__BIG_ENDIAN)
1001 u8 __tcp_agg_vars1;
1002 u8 __reserved50;
1003 u16 __mss;
1004#elif defined(__LITTLE_ENDIAN)
1005 u16 __mss;
1006 u8 __reserved50;
1007 u8 __tcp_agg_vars1;
1008#endif
1009 u32 __snd_nxt;
1010 u32 __tx_wnd;
1011 u32 __snd_una;
1012 u32 __reserved53;
1013#if defined(__BIG_ENDIAN)
1014 u8 __agg_val8_th;
1015 u8 __agg_val8;
1016 u16 __tcp_agg_vars2;
1017#elif defined(__LITTLE_ENDIAN)
1018 u16 __tcp_agg_vars2;
1019 u8 __agg_val8;
1020 u8 __agg_val8_th;
1021#endif
1022 u32 __reserved58;
1023 u32 __reserved59;
1024 u32 __reserved60;
1025 u32 __reserved61;
1026#if defined(__BIG_ENDIAN)
1027 u16 __agg_val7_th;
1028 u16 __agg_val7;
1029#elif defined(__LITTLE_ENDIAN)
1030 u16 __agg_val7;
1031 u16 __agg_val7_th;
1032#endif
1033#if defined(__BIG_ENDIAN)
1034 u8 __tcp_agg_vars5;
1035 u8 __tcp_agg_vars4;
1036 u8 __tcp_agg_vars3;
1037 u8 __reserved62;
1038#elif defined(__LITTLE_ENDIAN)
1039 u8 __reserved62;
1040 u8 __tcp_agg_vars3;
1041 u8 __tcp_agg_vars4;
1042 u8 __tcp_agg_vars5;
1043#endif
1044 u32 __tcp_agg_vars6;
1045#if defined(__BIG_ENDIAN)
1046 u16 __agg_misc6;
1047 u16 __tcp_agg_vars7;
1048#elif defined(__LITTLE_ENDIAN)
1049 u16 __tcp_agg_vars7;
1050 u16 __agg_misc6;
1051#endif
1052 u32 __agg_val10;
1053 u32 __agg_val10_th;
1054#if defined(__BIG_ENDIAN)
1055 u16 __reserved3;
1056 u8 __reserved2;
1057 u8 __agg_misc7;
1058#elif defined(__LITTLE_ENDIAN)
1059 u8 __agg_misc7;
1060 u8 __reserved2;
1061 u16 __reserved3;
1062#endif
1063};
1064
1065/*
1066 * The eth aggregative context of Xstorm
1067 */
1068struct xstorm_eth_ag_context {
1069#if defined(__BIG_ENDIAN)
1070 u16 __bd_prod;
1071 u8 __agg_vars1;
1072 u8 __state;
1073#elif defined(__LITTLE_ENDIAN)
1074 u8 __state;
1075 u8 __agg_vars1;
1076 u16 __bd_prod;
1077#endif
1078#if defined(__BIG_ENDIAN)
1079 u8 cdu_reserved;
1080 u8 __agg_vars4;
1081 u8 __agg_vars3;
1082 u8 __agg_vars2;
1083#elif defined(__LITTLE_ENDIAN)
1084 u8 __agg_vars2;
1085 u8 __agg_vars3;
1086 u8 __agg_vars4;
1087 u8 cdu_reserved;
1088#endif
1089 u32 __more_packets_to_send;
1090#if defined(__BIG_ENDIAN)
1091 u16 __agg_vars5;
1092 u16 __agg_val4_th;
1093#elif defined(__LITTLE_ENDIAN)
1094 u16 __agg_val4_th;
1095 u16 __agg_vars5;
1096#endif
1097 struct xstorm_eth_extra_ag_context_section __extra_section;
1098#if defined(__BIG_ENDIAN)
1099 u16 __agg_vars7;
1100 u8 __agg_val3_th;
1101 u8 __agg_vars6;
1102#elif defined(__LITTLE_ENDIAN)
1103 u8 __agg_vars6;
1104 u8 __agg_val3_th;
1105 u16 __agg_vars7;
1106#endif
1107#if defined(__BIG_ENDIAN)
1108 u16 __agg_val11_th;
1109 u16 __agg_val11;
1110#elif defined(__LITTLE_ENDIAN)
1111 u16 __agg_val11;
1112 u16 __agg_val11_th;
1113#endif
1114#if defined(__BIG_ENDIAN)
1115 u8 __reserved1;
1116 u8 __agg_val6_th;
1117 u16 __agg_val9;
1118#elif defined(__LITTLE_ENDIAN)
1119 u16 __agg_val9;
1120 u8 __agg_val6_th;
1121 u8 __reserved1;
1122#endif
1123#if defined(__BIG_ENDIAN)
1124 u16 __agg_val2_th;
1125 u16 __agg_val2;
1126#elif defined(__LITTLE_ENDIAN)
1127 u16 __agg_val2;
1128 u16 __agg_val2_th;
1129#endif
1130 u32 __agg_vars8;
1131#if defined(__BIG_ENDIAN)
1132 u16 __agg_misc0;
1133 u16 __agg_val4;
1134#elif defined(__LITTLE_ENDIAN)
1135 u16 __agg_val4;
1136 u16 __agg_misc0;
1137#endif
1138#if defined(__BIG_ENDIAN)
1139 u8 __agg_val3;
1140 u8 __agg_val6;
1141 u8 __agg_val5_th;
1142 u8 __agg_val5;
1143#elif defined(__LITTLE_ENDIAN)
1144 u8 __agg_val5;
1145 u8 __agg_val5_th;
1146 u8 __agg_val6;
1147 u8 __agg_val3;
1148#endif
1149#if defined(__BIG_ENDIAN)
1150 u16 __agg_misc1;
1151 u16 __bd_ind_max_val;
1152#elif defined(__LITTLE_ENDIAN)
1153 u16 __bd_ind_max_val;
1154 u16 __agg_misc1;
1155#endif
1156 u32 __reserved57;
1157 u32 __agg_misc4;
1158 u32 __agg_misc5;
1159};
1160
1161/*
1162 * The eth aggregative context section of Tstorm
1163 */
1164struct tstorm_eth_extra_ag_context_section {
1165 u32 __agg_val1;
1166#if defined(__BIG_ENDIAN)
1167 u8 __tcp_agg_vars2;
1168 u8 __agg_val3;
1169 u16 __agg_val2;
1170#elif defined(__LITTLE_ENDIAN)
1171 u16 __agg_val2;
1172 u8 __agg_val3;
1173 u8 __tcp_agg_vars2;
1174#endif
1175#if defined(__BIG_ENDIAN)
1176 u16 __agg_val5;
1177 u8 __agg_val6;
1178 u8 __tcp_agg_vars3;
1179#elif defined(__LITTLE_ENDIAN)
1180 u8 __tcp_agg_vars3;
1181 u8 __agg_val6;
1182 u16 __agg_val5;
1183#endif
1184 u32 __reserved63;
1185 u32 __reserved64;
1186 u32 __reserved65;
1187 u32 __reserved66;
1188 u32 __reserved67;
1189 u32 __tcp_agg_vars1;
1190 u32 __reserved61;
1191 u32 __reserved62;
1192 u32 __reserved2;
1193};
1194
1195/*
1196 * The eth aggregative context of Tstorm
1197 */
1198struct tstorm_eth_ag_context {
1199#if defined(__BIG_ENDIAN)
1200 u16 __reserved54;
1201 u8 __agg_vars1;
1202 u8 __state;
1203#elif defined(__LITTLE_ENDIAN)
1204 u8 __state;
1205 u8 __agg_vars1;
1206 u16 __reserved54;
1207#endif
1208#if defined(__BIG_ENDIAN)
1209 u16 __agg_val4;
1210 u16 __agg_vars2;
1211#elif defined(__LITTLE_ENDIAN)
1212 u16 __agg_vars2;
1213 u16 __agg_val4;
1214#endif
1215 struct tstorm_eth_extra_ag_context_section __extra_section;
1216};
1217
1218/*
1219 * The eth aggregative context of Cstorm
1220 */
1221struct cstorm_eth_ag_context {
1222 u32 __agg_vars1;
1223#if defined(__BIG_ENDIAN)
1224 u8 __aux1_th;
1225 u8 __aux1_val;
1226 u16 __agg_vars2;
1227#elif defined(__LITTLE_ENDIAN)
1228 u16 __agg_vars2;
1229 u8 __aux1_val;
1230 u8 __aux1_th;
1231#endif
1232 u32 __num_of_treated_packet;
1233 u32 __last_packet_treated;
1234#if defined(__BIG_ENDIAN)
1235 u16 __reserved58;
1236 u16 __reserved57;
1237#elif defined(__LITTLE_ENDIAN)
1238 u16 __reserved57;
1239 u16 __reserved58;
1240#endif
1241#if defined(__BIG_ENDIAN)
1242 u8 __reserved62;
1243 u8 __reserved61;
1244 u8 __reserved60;
1245 u8 __reserved59;
1246#elif defined(__LITTLE_ENDIAN)
1247 u8 __reserved59;
1248 u8 __reserved60;
1249 u8 __reserved61;
1250 u8 __reserved62;
1251#endif
1252#if defined(__BIG_ENDIAN)
1253 u16 __reserved64;
1254 u16 __reserved63;
1255#elif defined(__LITTLE_ENDIAN)
1256 u16 __reserved63;
1257 u16 __reserved64;
1258#endif
1259 u32 __reserved65;
1260#if defined(__BIG_ENDIAN)
1261 u16 __agg_vars3;
1262 u16 __rq_inv_cnt;
1263#elif defined(__LITTLE_ENDIAN)
1264 u16 __rq_inv_cnt;
1265 u16 __agg_vars3;
1266#endif
1267#if defined(__BIG_ENDIAN)
1268 u16 __packet_index_th;
1269 u16 __packet_index;
1270#elif defined(__LITTLE_ENDIAN)
1271 u16 __packet_index;
1272 u16 __packet_index_th;
1273#endif
1274};
1275
1276/*
1277 * The eth aggregative context of Ustorm
1278 */
1279struct ustorm_eth_ag_context {
1280#if defined(__BIG_ENDIAN)
1281 u8 __aux_counter_flags;
1282 u8 __agg_vars2;
1283 u8 __agg_vars1;
1284 u8 __state;
1285#elif defined(__LITTLE_ENDIAN)
1286 u8 __state;
1287 u8 __agg_vars1;
1288 u8 __agg_vars2;
1289 u8 __aux_counter_flags;
1290#endif
1291#if defined(__BIG_ENDIAN)
1292 u8 cdu_usage;
1293 u8 __agg_misc2;
1294 u16 __agg_misc1;
1295#elif defined(__LITTLE_ENDIAN)
1296 u16 __agg_misc1;
1297 u8 __agg_misc2;
1298 u8 cdu_usage;
1299#endif
1300 u32 __agg_misc4;
1301#if defined(__BIG_ENDIAN)
1302 u8 __agg_val3_th;
1303 u8 __agg_val3;
1304 u16 __agg_misc3;
1305#elif defined(__LITTLE_ENDIAN)
1306 u16 __agg_misc3;
1307 u8 __agg_val3;
1308 u8 __agg_val3_th;
1309#endif
1310 u32 __agg_val1;
1311 u32 __agg_misc4_th;
1312#if defined(__BIG_ENDIAN)
1313 u16 __agg_val2_th;
1314 u16 __agg_val2;
1315#elif defined(__LITTLE_ENDIAN)
1316 u16 __agg_val2;
1317 u16 __agg_val2_th;
1318#endif
1319#if defined(__BIG_ENDIAN)
1320 u16 __reserved2;
1321 u8 __decision_rules;
1322 u8 __decision_rule_enable_bits;
1323#elif defined(__LITTLE_ENDIAN)
1324 u8 __decision_rule_enable_bits;
1325 u8 __decision_rules;
1326 u16 __reserved2;
1327#endif
1328};
1329
1330/*
1331 * Timers connection context
1332 */
1333struct timers_block_context {
1334 u32 __reserved_0;
1335 u32 __reserved_1;
1336 u32 __reserved_2;
1337 u32 __reserved_flags;
1338};
1339
1340/*
1341 * structure for easy accessability to assembler
1342 */
1343struct eth_tx_bd_flags {
1344 u8 as_bitfield;
1345#define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0)
1346#define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
1347#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
1348#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
1349#define ETH_TX_BD_FLAGS_TCP_CSUM (0x1<<2)
1350#define ETH_TX_BD_FLAGS_TCP_CSUM_SHIFT 2
1351#define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
1352#define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
1353#define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
1354#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
1355#define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5)
1356#define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5
1357#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
1358#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
1359#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
1360#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
1361};
1362
1363/*
1364 * The eth Tx Buffer Descriptor
1365 */
1366struct eth_tx_bd {
1367 u32 addr_lo;
1368 u32 addr_hi;
1369 u16 nbd;
1370 u16 nbytes;
1371 u16 vlan;
1372 struct eth_tx_bd_flags bd_flags;
1373 u8 general_data;
1374#define ETH_TX_BD_HDR_NBDS (0x3F<<0)
1375#define ETH_TX_BD_HDR_NBDS_SHIFT 0
1376#define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6)
1377#define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6
1378};
1379
1380/*
1381 * Tx parsing BD structure for ETH,Relevant in START
1382 */
1383struct eth_tx_parse_bd {
1384 u8 global_data;
1385#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
1386#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
1387#define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4)
1388#define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4
1389#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
1390#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
1391#define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
1392#define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
1393#define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
1394#define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
1395 u8 tcp_flags;
1396#define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
1397#define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
1398#define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
1399#define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
1400#define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
1401#define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
1402#define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
1403#define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
1404#define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
1405#define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
1406#define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
1407#define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
1408#define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
1409#define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
1410#define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
1411#define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
1412 u8 ip_hlen;
1413 s8 cs_offset;
1414 u16 total_hlen;
1415 u16 lso_mss;
1416 u16 tcp_pseudo_csum;
1417 u16 ip_id;
1418 u32 tcp_send_seq;
1419};
1420
1421/*
1422 * The last BD in the BD memory will hold a pointer to the next BD memory
1423 */
1424struct eth_tx_next_bd {
1425 u32 addr_lo;
1426 u32 addr_hi;
1427 u8 reserved[8];
1428};
1429
1430/*
1431 * union for 3 Bd types
1432 */
1433union eth_tx_bd_types {
1434 struct eth_tx_bd reg_bd;
1435 struct eth_tx_parse_bd parse_bd;
1436 struct eth_tx_next_bd next_bd;
1437};
1438
1439/*
1440 * The eth storm context of Xstorm
1441 */
1442struct xstorm_eth_st_context {
1443 u32 tx_bd_page_base_lo;
1444 u32 tx_bd_page_base_hi;
1445#if defined(__BIG_ENDIAN)
1446 u16 tx_bd_cons;
1447 u8 __reserved0;
1448 u8 __local_tx_bd_prod;
1449#elif defined(__LITTLE_ENDIAN)
1450 u8 __local_tx_bd_prod;
1451 u8 __reserved0;
1452 u16 tx_bd_cons;
1453#endif
1454 u32 db_data_addr_lo;
1455 u32 db_data_addr_hi;
1456 u32 __pkt_cons;
1457 u32 __gso_next;
1458 u32 is_eth_conn_1b;
1459 union eth_tx_bd_types __bds[13];
1460};
1461
1462/*
1463 * The eth storm context of Cstorm
1464 */
1465struct cstorm_eth_st_context {
1466#if defined(__BIG_ENDIAN)
1467 u16 __reserved0;
1468 u8 sb_index_number;
1469 u8 status_block_id;
1470#elif defined(__LITTLE_ENDIAN)
1471 u8 status_block_id;
1472 u8 sb_index_number;
1473 u16 __reserved0;
1474#endif
1475 u32 __reserved1[3];
1476};
1477
1478/*
1479 * Ethernet connection context
1480 */
1481struct eth_context {
1482 struct ustorm_eth_st_context ustorm_st_context;
1483 struct tstorm_eth_st_context tstorm_st_context;
1484 struct xstorm_eth_ag_context xstorm_ag_context;
1485 struct tstorm_eth_ag_context tstorm_ag_context;
1486 struct cstorm_eth_ag_context cstorm_ag_context;
1487 struct ustorm_eth_ag_context ustorm_ag_context;
1488 struct timers_block_context timers_context;
1489 struct xstorm_eth_st_context xstorm_st_context;
1490 struct cstorm_eth_st_context cstorm_st_context;
1491};
1492
1493
1494/*
1495 * ethernet doorbell
1496 */
1497struct eth_tx_doorbell {
1498#if defined(__BIG_ENDIAN)
1499 u16 npackets;
1500 u8 params;
1501#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
1502#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
1503#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
1504#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
1505#define ETH_TX_DOORBELL_SPARE (0x1<<7)
1506#define ETH_TX_DOORBELL_SPARE_SHIFT 7
1507 struct doorbell_hdr hdr;
1508#elif defined(__LITTLE_ENDIAN)
1509 struct doorbell_hdr hdr;
1510 u8 params;
1511#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
1512#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
1513#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
1514#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
1515#define ETH_TX_DOORBELL_SPARE (0x1<<7)
1516#define ETH_TX_DOORBELL_SPARE_SHIFT 7
1517 u16 npackets;
1518#endif
1519};
1520
1521
1522/*
1523 * ustorm status block
1524 */
1525struct ustorm_def_status_block {
1526 u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
1527 u16 status_block_index;
1528 u8 reserved0;
1529 u8 status_block_id;
1530 u32 __flags;
1531};
1532
1533/*
1534 * cstorm status block
1535 */
1536struct cstorm_def_status_block {
1537 u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
1538 u16 status_block_index;
1539 u8 reserved0;
1540 u8 status_block_id;
1541 u32 __flags;
1542};
1543
1544/*
1545 * xstorm status block
1546 */
1547struct xstorm_def_status_block {
1548 u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
1549 u16 status_block_index;
1550 u8 reserved0;
1551 u8 status_block_id;
1552 u32 __flags;
1553};
1554
1555/*
1556 * tstorm status block
1557 */
1558struct tstorm_def_status_block {
1559 u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
1560 u16 status_block_index;
1561 u8 reserved0;
1562 u8 status_block_id;
1563 u32 __flags;
1564};
1565
1566/*
1567 * host status block
1568 */
1569struct host_def_status_block {
1570 struct atten_def_status_block atten_status_block;
1571 struct ustorm_def_status_block u_def_status_block;
1572 struct cstorm_def_status_block c_def_status_block;
1573 struct xstorm_def_status_block x_def_status_block;
1574 struct tstorm_def_status_block t_def_status_block;
1575};
1576
1577
1578/*
1579 * ustorm status block
1580 */
1581struct ustorm_status_block {
1582 u16 index_values[HC_USTORM_SB_NUM_INDICES];
1583 u16 status_block_index;
1584 u8 reserved0;
1585 u8 status_block_id;
1586 u32 __flags;
1587};
1588
1589/*
1590 * cstorm status block
1591 */
1592struct cstorm_status_block {
1593 u16 index_values[HC_CSTORM_SB_NUM_INDICES];
1594 u16 status_block_index;
1595 u8 reserved0;
1596 u8 status_block_id;
1597 u32 __flags;
1598};
1599
1600/*
1601 * host status block
1602 */
1603struct host_status_block {
1604 struct ustorm_status_block u_status_block;
1605 struct cstorm_status_block c_status_block;
1606};
1607
1608
1609/*
1610 * The data for RSS setup ramrod
1611 */
1612struct eth_client_setup_ramrod_data {
1613 u32 client_id_5b;
1614 u8 is_rdma_1b;
1615 u8 reserved0;
1616 u16 reserved1;
1617};
1618
1619
1620/*
1621 * L2 dynamic host coalescing init parameters
1622 */
1623struct eth_dynamic_hc_config {
1624 u32 threshold[3];
1625 u8 hc_timeout[4];
1626};
1627
1628
1629/*
1630 * regular eth FP CQE parameters struct
1631 */
1632struct eth_fast_path_rx_cqe {
1633 u8 type;
1634 u8 error_type_flags;
1635#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<0)
1636#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 0
1637#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<1)
1638#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 1
1639#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<2)
1640#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 2
1641#define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<3)
1642#define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 3
1643#define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<4)
1644#define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 4
1645#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x7<<5)
1646#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 5
1647 u8 status_flags;
1648#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
1649#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
1650#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
1651#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
1652#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
1653#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
1654#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
1655#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
1656#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
1657#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
1658#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
1659#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
1660 u8 placement_offset;
1661 u32 rss_hash_result;
1662 u16 vlan_tag;
1663 u16 pkt_len;
1664 u16 queue_index;
1665 struct parsing_flags pars_flags;
1666};
1667
1668
1669/*
1670 * The data for RSS setup ramrod
1671 */
1672struct eth_halt_ramrod_data {
1673 u32 client_id_5b;
1674 u32 reserved0;
1675};
1676
1677
1678/*
1679 * Place holder for ramrods protocol specific data
1680 */
1681struct ramrod_data {
1682 u32 data_lo;
1683 u32 data_hi;
1684};
1685
1686/*
1687 * union for ramrod data for ethernet protocol (CQE) (force size of 16 bits)
1688 */
1689union eth_ramrod_data {
1690 struct ramrod_data general;
1691};
1692
1693
1694/*
1695 * Rx Last BD in page (in ETH)
1696 */
1697struct eth_rx_bd_next_page {
1698 u32 addr_lo;
1699 u32 addr_hi;
1700 u8 reserved[8];
1701};
1702
1703
1704/*
1705 * Eth Rx Cqe structure- general structure for ramrods
1706 */
1707struct common_ramrod_eth_rx_cqe {
1708 u8 type;
1709 u8 conn_type_3b;
1710 u16 reserved;
1711 u32 conn_and_cmd_data;
1712#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
1713#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
1714#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
1715#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
1716 struct ramrod_data protocol_data;
1717};
1718
1719/*
1720 * Rx Last CQE in page (in ETH)
1721 */
1722struct eth_rx_cqe_next_page {
1723 u32 addr_lo;
1724 u32 addr_hi;
1725 u32 reserved0;
1726 u32 reserved1;
1727};
1728
1729/*
1730 * union for all eth rx cqe types (fix their sizes)
1731 */
1732union eth_rx_cqe {
1733 struct eth_fast_path_rx_cqe fast_path_cqe;
1734 struct common_ramrod_eth_rx_cqe ramrod_cqe;
1735 struct eth_rx_cqe_next_page next_page_cqe;
1736};
1737
1738
1739/*
1740 * common data for all protocols
1741 */
1742struct spe_hdr {
1743 u32 conn_and_cmd_data;
1744#define SPE_HDR_CID (0xFFFFFF<<0)
1745#define SPE_HDR_CID_SHIFT 0
1746#define SPE_HDR_CMD_ID (0xFF<<24)
1747#define SPE_HDR_CMD_ID_SHIFT 24
1748 u16 type;
1749#define SPE_HDR_CONN_TYPE (0xFF<<0)
1750#define SPE_HDR_CONN_TYPE_SHIFT 0
1751#define SPE_HDR_COMMON_RAMROD (0xFF<<8)
1752#define SPE_HDR_COMMON_RAMROD_SHIFT 8
1753 u16 reserved;
1754};
1755
1756struct regpair {
1757 u32 lo;
1758 u32 hi;
1759};
1760
1761/*
1762 * ethernet slow path element
1763 */
1764union eth_specific_data {
1765 u8 protocol_data[8];
1766 struct regpair mac_config_addr;
1767 struct eth_client_setup_ramrod_data client_setup_ramrod_data;
1768 struct eth_halt_ramrod_data halt_ramrod_data;
1769 struct regpair leading_cqe_addr;
1770 struct regpair update_data_addr;
1771};
1772
1773/*
1774 * ethernet slow path element
1775 */
1776struct eth_spe {
1777 struct spe_hdr hdr;
1778 union eth_specific_data data;
1779};
1780
1781
1782/*
1783 * doorbell data in host memory
1784 */
1785struct eth_tx_db_data {
1786 u32 packets_prod;
1787 u16 bds_prod;
1788 u16 reserved;
1789};
1790
1791
1792/*
1793 * Common configuration parameters per port in Tstorm
1794 */
1795struct tstorm_eth_function_common_config {
1796 u32 config_flags;
1797#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
1798#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
1799#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
1800#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
1801#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
1802#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
1803#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
1804#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
1805#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE (0x1<<4)
1806#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4
1807#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)
1808#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5
1809#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3FFFFFF<<6)
1810#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 6
1811#if defined(__BIG_ENDIAN)
1812 u16 __secondary_vlan_id;
1813 u8 leading_client_id;
1814 u8 rss_result_mask;
1815#elif defined(__LITTLE_ENDIAN)
1816 u8 rss_result_mask;
1817 u8 leading_client_id;
1818 u16 __secondary_vlan_id;
1819#endif
1820};
1821
1822/*
1823 * parameters for eth update ramrod
1824 */
1825struct eth_update_ramrod_data {
1826 struct tstorm_eth_function_common_config func_config;
1827 u8 indirectionTable[128];
1828};
1829
1830
1831/*
1832 * MAC filtering configuration command header
1833 */
1834struct mac_configuration_hdr {
1835 u8 length_6b;
1836 u8 offset;
1837 u16 reserved0;
1838 u32 reserved1;
1839};
1840
1841/*
1842 * MAC address in list for ramrod
1843 */
1844struct tstorm_cam_entry {
1845 u16 lsb_mac_addr;
1846 u16 middle_mac_addr;
1847 u16 msb_mac_addr;
1848 u16 flags;
1849#define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
1850#define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
1851#define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
1852#define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
1853#define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
1854#define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
1855};
1856
1857/*
1858 * MAC filtering: CAM target table entry
1859 */
1860struct tstorm_cam_target_table_entry {
1861 u8 flags;
1862#define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
1863#define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
1864#define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
1865#define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
1866#define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
1867#define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
1868#define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
1869#define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
1870#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
1871#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
1872 u8 client_id;
1873 u16 vlan_id;
1874};
1875
1876/*
1877 * MAC address in list for ramrod
1878 */
1879struct mac_configuration_entry {
1880 struct tstorm_cam_entry cam_entry;
1881 struct tstorm_cam_target_table_entry target_table_entry;
1882};
1883
1884/*
1885 * MAC filtering configuration command
1886 */
1887struct mac_configuration_cmd {
1888 struct mac_configuration_hdr hdr;
1889 struct mac_configuration_entry config_table[64];
1890};
1891
1892
1893/*
1894 * Configuration parameters per client in Tstorm
1895 */
1896struct tstorm_eth_client_config {
1897#if defined(__BIG_ENDIAN)
1898 u16 statistics_counter_id;
1899 u16 mtu;
1900#elif defined(__LITTLE_ENDIAN)
1901 u16 mtu;
1902 u16 statistics_counter_id;
1903#endif
1904#if defined(__BIG_ENDIAN)
1905 u16 drop_flags;
1906#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
1907#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
1908#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
1909#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
1910#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR (0x1<<2)
1911#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR_SHIFT 2
1912#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<3)
1913#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 3
1914#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<4)
1915#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 4
1916#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x7FF<<5)
1917#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 5
1918 u16 config_flags;
1919#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
1920#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
1921#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
1922#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
1923#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x3FFF<<2)
1924#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 2
1925#elif defined(__LITTLE_ENDIAN)
1926 u16 config_flags;
1927#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
1928#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
1929#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
1930#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
1931#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x3FFF<<2)
1932#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 2
1933 u16 drop_flags;
1934#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
1935#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
1936#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
1937#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
1938#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR (0x1<<2)
1939#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR_SHIFT 2
1940#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<3)
1941#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 3
1942#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<4)
1943#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 4
1944#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x7FF<<5)
1945#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 5
1946#endif
1947};
1948
1949
1950/*
1951 * MAC filtering configuration parameters per port in Tstorm
1952 */
1953struct tstorm_eth_mac_filter_config {
1954 u32 ucast_drop_all;
1955 u32 ucast_accept_all;
1956 u32 mcast_drop_all;
1957 u32 mcast_accept_all;
1958 u32 bcast_drop_all;
1959 u32 bcast_accept_all;
1960 u32 strict_vlan;
1961 u32 __secondary_vlan_clients;
1962};
1963
1964
1965struct rate_shaping_per_protocol {
1966#if defined(__BIG_ENDIAN)
1967 u16 reserved0;
1968 u16 protocol_rate;
1969#elif defined(__LITTLE_ENDIAN)
1970 u16 protocol_rate;
1971 u16 reserved0;
1972#endif
1973 u32 protocol_quota;
1974 s32 current_credit;
1975 u32 reserved;
1976};
1977
1978struct rate_shaping_vars {
1979 struct rate_shaping_per_protocol protocol_vars[NUM_OF_PROTOCOLS];
1980 u32 pause_mask;
1981 u32 periodic_stop;
1982 u32 rs_periodic_timeout;
1983 u32 rs_threshold;
1984 u32 last_periodic_time;
1985 u32 reserved;
1986};
1987
1988struct fairness_per_protocol {
1989 u32 credit_delta;
1990 s32 fair_credit;
1991#if defined(__BIG_ENDIAN)
1992 u16 reserved0;
1993 u8 state;
1994 u8 weight;
1995#elif defined(__LITTLE_ENDIAN)
1996 u8 weight;
1997 u8 state;
1998 u16 reserved0;
1999#endif
2000 u32 reserved1;
2001};
2002
2003struct fairness_vars {
2004 struct fairness_per_protocol protocol_vars[NUM_OF_PROTOCOLS];
2005 u32 upper_bound;
2006 u32 port_rate;
2007 u32 pause_mask;
2008 u32 fair_threshold;
2009};
2010
2011struct safc_struct {
2012 u32 cur_pause_mask;
2013 u32 expire_time;
2014#if defined(__BIG_ENDIAN)
2015 u16 reserved0;
2016 u8 cur_cos_types;
2017 u8 safc_timeout_usec;
2018#elif defined(__LITTLE_ENDIAN)
2019 u8 safc_timeout_usec;
2020 u8 cur_cos_types;
2021 u16 reserved0;
2022#endif
2023 u32 reserved1;
2024};
2025
2026struct demo_struct {
2027 u8 con_number[NUM_OF_PROTOCOLS];
2028#if defined(__BIG_ENDIAN)
2029 u8 reserved1;
2030 u8 fairness_enable;
2031 u8 rate_shaping_enable;
2032 u8 cmng_enable;
2033#elif defined(__LITTLE_ENDIAN)
2034 u8 cmng_enable;
2035 u8 rate_shaping_enable;
2036 u8 fairness_enable;
2037 u8 reserved1;
2038#endif
2039};
2040
2041struct cmng_struct {
2042 struct rate_shaping_vars rs_vars;
2043 struct fairness_vars fair_vars;
2044 struct safc_struct safc_vars;
2045 struct demo_struct demo_vars;
2046};
2047
2048
2049struct cos_to_protocol {
2050 u8 mask[MAX_COS_NUMBER];
2051};
2052
2053
2054/*
2055 * Common statistics collected by the Xstorm (per port)
2056 */
2057struct xstorm_common_stats {
2058 struct regpair total_sent_bytes;
2059 u32 total_sent_pkts;
2060 u32 unicast_pkts_sent;
2061 struct regpair unicast_bytes_sent;
2062 struct regpair multicast_bytes_sent;
2063 u32 multicast_pkts_sent;
2064 u32 broadcast_pkts_sent;
2065 struct regpair broadcast_bytes_sent;
2066 struct regpair done;
2067};
2068
2069/*
2070 * Protocol-common statistics collected by the Tstorm (per client)
2071 */
2072struct tstorm_per_client_stats {
2073 struct regpair total_rcv_bytes;
2074 struct regpair rcv_unicast_bytes;
2075 struct regpair rcv_broadcast_bytes;
2076 struct regpair rcv_multicast_bytes;
2077 struct regpair rcv_error_bytes;
2078 u32 checksum_discard;
2079 u32 packets_too_big_discard;
2080 u32 total_rcv_pkts;
2081 u32 rcv_unicast_pkts;
2082 u32 rcv_broadcast_pkts;
2083 u32 rcv_multicast_pkts;
2084 u32 no_buff_discard;
2085 u32 ttl0_discard;
2086 u32 mac_discard;
2087 u32 reserved;
2088};
2089
2090/*
2091 * Protocol-common statistics collected by the Tstorm (per port)
2092 */
2093struct tstorm_common_stats {
2094 struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID];
2095 u32 mac_filter_discard;
2096 u32 xxoverflow_discard;
2097 u32 brb_truncate_discard;
2098 u32 reserved;
2099 struct regpair done;
2100};
2101
2102/*
2103 * Eth statistics query sturcture for the eth_stats_quesry ramrod
2104 */
2105struct eth_stats_query {
2106 struct xstorm_common_stats xstorm_common;
2107 struct tstorm_common_stats tstorm_common;
2108};
2109
2110
2111/*
2112 * FW version stored in the Xstorm RAM
2113 */
2114struct fw_version {
2115#if defined(__BIG_ENDIAN)
2116 u16 patch;
2117 u8 primary;
2118 u8 client;
2119#elif defined(__LITTLE_ENDIAN)
2120 u8 client;
2121 u8 primary;
2122 u16 patch;
2123#endif
2124 u32 flags;
2125#define FW_VERSION_OPTIMIZED (0x1<<0)
2126#define FW_VERSION_OPTIMIZED_SHIFT 0
2127#define FW_VERSION_BIG_ENDIEN (0x1<<1)
2128#define FW_VERSION_BIG_ENDIEN_SHIFT 1
2129#define __FW_VERSION_RESERVED (0x3FFFFFFF<<2)
2130#define __FW_VERSION_RESERVED_SHIFT 2
2131};
2132
2133
2134/*
2135 * FW version stored in first line of pram
2136 */
2137struct pram_fw_version {
2138#if defined(__BIG_ENDIAN)
2139 u16 patch;
2140 u8 primary;
2141 u8 client;
2142#elif defined(__LITTLE_ENDIAN)
2143 u8 client;
2144 u8 primary;
2145 u16 patch;
2146#endif
2147 u8 flags;
2148#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
2149#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
2150#define PRAM_FW_VERSION_STORM_ID (0x3<<1)
2151#define PRAM_FW_VERSION_STORM_ID_SHIFT 1
2152#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
2153#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
2154#define __PRAM_FW_VERSION_RESERVED0 (0xF<<4)
2155#define __PRAM_FW_VERSION_RESERVED0_SHIFT 4
2156};
2157
2158
2159/*
2160 * The send queue element
2161 */
2162struct slow_path_element {
2163 struct spe_hdr hdr;
2164 u8 protocol_data[8];
2165};
2166
2167
2168/*
2169 * eth/toe flags that indicate if to query
2170 */
2171struct stats_indication_flags {
2172 u32 collect_eth;
2173 u32 collect_toe;
2174};
2175
2176
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
new file mode 100644
index 000000000000..04f93bff2ef4
--- /dev/null
+++ b/drivers/net/bnx2x_init.h
@@ -0,0 +1,564 @@
1/* bnx2x_init.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Eliezer Tamir <eliezert@broadcom.com>
10 */
11
12#ifndef BNX2X_INIT_H
13#define BNX2X_INIT_H
14
15#define COMMON 0x1
16#define PORT0 0x2
17#define PORT1 0x4
18
19#define INIT_EMULATION 0x1
20#define INIT_FPGA 0x2
21#define INIT_ASIC 0x4
22#define INIT_HARDWARE 0x7
23
24#define STORM_INTMEM_SIZE (0x5800 / 4)
25#define TSTORM_INTMEM_ADDR 0x1a0000
26#define CSTORM_INTMEM_ADDR 0x220000
27#define XSTORM_INTMEM_ADDR 0x2a0000
28#define USTORM_INTMEM_ADDR 0x320000
29
30
31/* Init operation types and structures */
32
33#define OP_RD 0x1 /* read single register */
34#define OP_WR 0x2 /* write single register */
35#define OP_IW 0x3 /* write single register using mailbox */
36#define OP_SW 0x4 /* copy a string to the device */
37#define OP_SI 0x5 /* copy a string using mailbox */
38#define OP_ZR 0x6 /* clear memory */
39#define OP_ZP 0x7 /* unzip then copy with DMAE */
40#define OP_WB 0x8 /* copy a string using DMAE */
41
42struct raw_op {
43 u32 op :8;
44 u32 offset :24;
45 u32 raw_data;
46};
47
48struct op_read {
49 u32 op :8;
50 u32 offset :24;
51 u32 pad;
52};
53
54struct op_write {
55 u32 op :8;
56 u32 offset :24;
57 u32 val;
58};
59
60struct op_string_write {
61 u32 op :8;
62 u32 offset :24;
63#ifdef __LITTLE_ENDIAN
64 u16 data_off;
65 u16 data_len;
66#else /* __BIG_ENDIAN */
67 u16 data_len;
68 u16 data_off;
69#endif
70};
71
72struct op_zero {
73 u32 op :8;
74 u32 offset :24;
75 u32 len;
76};
77
78union init_op {
79 struct op_read read;
80 struct op_write write;
81 struct op_string_write str_wr;
82 struct op_zero zero;
83 struct raw_op raw;
84};
85
86#include "bnx2x_init_values.h"
87
88static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
89
90static void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
91 u32 dst_addr, u32 len32);
92
93static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len);
94
95static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data,
96 u32 len)
97{
98 int i;
99
100 for (i = 0; i < len; i++) {
101 REG_WR(bp, addr + i*4, data[i]);
102 if (!(i % 10000)) {
103 touch_softlockup_watchdog();
104 cpu_relax();
105 }
106 }
107}
108
109#define INIT_MEM_WR(reg, data, reg_off, len) \
110 bnx2x_init_str_wr(bp, reg + reg_off*4, data, len)
111
112static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
113 u16 len)
114{
115 int i;
116
117 for (i = 0; i < len; i++) {
118 REG_WR_IND(bp, addr + i*4, data[i]);
119 if (!(i % 10000)) {
120 touch_softlockup_watchdog();
121 cpu_relax();
122 }
123 }
124}
125
126static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data,
127 u32 len, int gunzip)
128{
129 int offset = 0;
130
131 if (gunzip) {
132 int rc;
133#ifdef __BIG_ENDIAN
134 int i, size;
135 u32 *temp;
136
137 temp = kmalloc(len, GFP_KERNEL);
138 size = (len / 4) + ((len % 4) ? 1 : 0);
139 for (i = 0; i < size; i++)
140 temp[i] = swab32(data[i]);
141 data = temp;
142#endif
143 rc = bnx2x_gunzip(bp, (u8 *)data, len);
144 if (rc) {
145 DP(NETIF_MSG_HW, "gunzip failed ! rc %d\n", rc);
146 return;
147 }
148 len = bp->gunzip_outlen;
149#ifdef __BIG_ENDIAN
150 kfree(temp);
151 for (i = 0; i < len; i++)
152 ((u32 *)bp->gunzip_buf)[i] =
153 swab32(((u32 *)bp->gunzip_buf)[i]);
154#endif
155 } else {
156 if ((len * 4) > FW_BUF_SIZE) {
157 BNX2X_ERR("LARGE DMAE OPERATION ! len 0x%x\n", len*4);
158 return;
159 }
160 memcpy(bp->gunzip_buf, data, len * 4);
161 }
162
163 while (len > DMAE_LEN32_MAX) {
164 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
165 addr + offset, DMAE_LEN32_MAX);
166 offset += DMAE_LEN32_MAX * 4;
167 len -= DMAE_LEN32_MAX;
168 }
169 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, addr + offset, len);
170}
171
172#define INIT_MEM_WB(reg, data, reg_off, len) \
173 bnx2x_init_wr_wb(bp, reg + reg_off*4, data, len, 0)
174
175#define INIT_GUNZIP_DMAE(reg, data, reg_off, len) \
176 bnx2x_init_wr_wb(bp, reg + reg_off*4, data, len, 1)
177
178static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
179{
180 int offset = 0;
181
182 if ((len * 4) > FW_BUF_SIZE) {
183 BNX2X_ERR("LARGE DMAE OPERATION ! len 0x%x\n", len * 4);
184 return;
185 }
186 memset(bp->gunzip_buf, fill, len * 4);
187
188 while (len > DMAE_LEN32_MAX) {
189 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
190 addr + offset, DMAE_LEN32_MAX);
191 offset += DMAE_LEN32_MAX * 4;
192 len -= DMAE_LEN32_MAX;
193 }
194 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, addr + offset, len);
195}
196
197static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
198{
199 int i;
200 union init_op *op;
201 u32 op_type, addr, len;
202 const u32 *data;
203
204 for (i = op_start; i < op_end; i++) {
205
206 op = (union init_op *)&(init_ops[i]);
207
208 op_type = op->str_wr.op;
209 addr = op->str_wr.offset;
210 len = op->str_wr.data_len;
211 data = init_data + op->str_wr.data_off;
212
213 switch (op_type) {
214 case OP_RD:
215 REG_RD(bp, addr);
216 break;
217 case OP_WR:
218 REG_WR(bp, addr, op->write.val);
219 break;
220 case OP_SW:
221 bnx2x_init_str_wr(bp, addr, data, len);
222 break;
223 case OP_WB:
224 bnx2x_init_wr_wb(bp, addr, data, len, 0);
225 break;
226 case OP_SI:
227 bnx2x_init_ind_wr(bp, addr, data, len);
228 break;
229 case OP_ZR:
230 bnx2x_init_fill(bp, addr, 0, op->zero.len);
231 break;
232 case OP_ZP:
233 bnx2x_init_wr_wb(bp, addr, data, len, 1);
234 break;
235 default:
236 BNX2X_ERR("BAD init operation!\n");
237 }
238 }
239}
240
241
242/****************************************************************************
243* PXP
244****************************************************************************/
245/*
246 * This code configures the PCI read/write arbiter
247 * which implements a wighted round robin
248 * between the virtual queues in the chip.
249 *
250 * The values were derived for each PCI max payload and max request size.
251 * since max payload and max request size are only known at run time,
252 * this is done as a separate init stage.
253 */
254
255#define NUM_WR_Q 13
256#define NUM_RD_Q 29
257#define MAX_RD_ORD 3
258#define MAX_WR_ORD 2
259
260/* configuration for one arbiter queue */
261struct arb_line {
262 int l;
263 int add;
264 int ubound;
265};
266
267/* derived configuration for each read queue for each max request size */
268static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
269 {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} },
270 {{4 , 8 , 4}, {4 , 8 , 4}, {4 , 8 , 4}, {4 , 8 , 4} },
271 {{4 , 3 , 3}, {4 , 3 , 3}, {4 , 3 , 3}, {4 , 3 , 3} },
272 {{8 , 3 , 6}, {16 , 3 , 11}, {16 , 3 , 11}, {16 , 3 , 11} },
273 {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} },
274 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },
275 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },
276 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },
277 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },
278 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
279 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
280 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
281 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
282 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
283 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
284 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
285 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
286 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
287 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
288 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
289 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
290 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
291 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
292 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
293 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
294 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
295 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
296 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
297 {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81}, {64 , 64 , 120} }
298};
299
300/* derived configuration for each write queue for each max request size */
301static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
302 {{4 , 6 , 3}, {4 , 6 , 3}, {4 , 6 , 3} },
303 {{4 , 2 , 3}, {4 , 2 , 3}, {4 , 2 , 3} },
304 {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} },
305 {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} },
306 {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} },
307 {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} },
308 {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25} },
309 {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} },
310 {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} },
311 {{8 , 9 , 6}, {16 , 9 , 11}, {32 , 9 , 21} },
312 {{8 , 47 , 19}, {16 , 47 , 19}, {32 , 47 , 21} },
313 {{8 , 9 , 6}, {16 , 9 , 11}, {16 , 9 , 11} },
314 {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81} }
315};
316
317/* register adresses for read queues */
318static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
319 {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
320 PXP2_REG_RQ_BW_RD_UBOUND0},
321 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
322 PXP2_REG_PSWRQ_BW_UB1},
323 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
324 PXP2_REG_PSWRQ_BW_UB2},
325 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
326 PXP2_REG_PSWRQ_BW_UB3},
327 {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
328 PXP2_REG_RQ_BW_RD_UBOUND4},
329 {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
330 PXP2_REG_RQ_BW_RD_UBOUND5},
331 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
332 PXP2_REG_PSWRQ_BW_UB6},
333 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
334 PXP2_REG_PSWRQ_BW_UB7},
335 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
336 PXP2_REG_PSWRQ_BW_UB8},
337 {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
338 PXP2_REG_PSWRQ_BW_UB9},
339 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
340 PXP2_REG_PSWRQ_BW_UB10},
341 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
342 PXP2_REG_PSWRQ_BW_UB11},
343 {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
344 PXP2_REG_RQ_BW_RD_UBOUND12},
345 {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
346 PXP2_REG_RQ_BW_RD_UBOUND13},
347 {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
348 PXP2_REG_RQ_BW_RD_UBOUND14},
349 {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
350 PXP2_REG_RQ_BW_RD_UBOUND15},
351 {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
352 PXP2_REG_RQ_BW_RD_UBOUND16},
353 {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
354 PXP2_REG_RQ_BW_RD_UBOUND17},
355 {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
356 PXP2_REG_RQ_BW_RD_UBOUND18},
357 {PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
358 PXP2_REG_RQ_BW_RD_UBOUND19},
359 {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
360 PXP2_REG_RQ_BW_RD_UBOUND20},
361 {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
362 PXP2_REG_RQ_BW_RD_UBOUND22},
363 {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
364 PXP2_REG_RQ_BW_RD_UBOUND23},
365 {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
366 PXP2_REG_RQ_BW_RD_UBOUND24},
367 {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
368 PXP2_REG_RQ_BW_RD_UBOUND25},
369 {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
370 PXP2_REG_RQ_BW_RD_UBOUND26},
371 {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
372 PXP2_REG_RQ_BW_RD_UBOUND27},
373 {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
374 PXP2_REG_PSWRQ_BW_UB28}
375};
376
377/* register adresses for wrtie queues */
378static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
379 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
380 PXP2_REG_PSWRQ_BW_UB1},
381 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
382 PXP2_REG_PSWRQ_BW_UB2},
383 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
384 PXP2_REG_PSWRQ_BW_UB3},
385 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
386 PXP2_REG_PSWRQ_BW_UB6},
387 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
388 PXP2_REG_PSWRQ_BW_UB7},
389 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
390 PXP2_REG_PSWRQ_BW_UB8},
391 {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
392 PXP2_REG_PSWRQ_BW_UB9},
393 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
394 PXP2_REG_PSWRQ_BW_UB10},
395 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
396 PXP2_REG_PSWRQ_BW_UB11},
397 {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
398 PXP2_REG_PSWRQ_BW_UB28},
399 {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
400 PXP2_REG_RQ_BW_WR_UBOUND29},
401 {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
402 PXP2_REG_RQ_BW_WR_UBOUND30}
403};
404
405static void bnx2x_init_pxp(struct bnx2x *bp)
406{
407 int r_order, w_order;
408 u32 val, i;
409
410 pci_read_config_word(bp->pdev,
411 bp->pcie_cap + PCI_EXP_DEVCTL, (u16 *)&val);
412 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", val);
413 w_order = ((val & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
414 r_order = ((val & PCI_EXP_DEVCTL_READRQ) >> 12);
415
416 if (r_order > MAX_RD_ORD) {
417 DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n",
418 r_order, MAX_RD_ORD);
419 r_order = MAX_RD_ORD;
420 }
421 if (w_order > MAX_WR_ORD) {
422 DP(NETIF_MSG_HW, "write order of %d order adjusted to %d\n",
423 w_order, MAX_WR_ORD);
424 w_order = MAX_WR_ORD;
425 }
426 DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order);
427
428 for (i = 0; i < NUM_RD_Q-1; i++) {
429 REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l);
430 REG_WR(bp, read_arb_addr[i].add,
431 read_arb_data[i][r_order].add);
432 REG_WR(bp, read_arb_addr[i].ubound,
433 read_arb_data[i][r_order].ubound);
434 }
435
436 for (i = 0; i < NUM_WR_Q-1; i++) {
437 if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
438 (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
439
440 REG_WR(bp, write_arb_addr[i].l,
441 write_arb_data[i][w_order].l);
442
443 REG_WR(bp, write_arb_addr[i].add,
444 write_arb_data[i][w_order].add);
445
446 REG_WR(bp, write_arb_addr[i].ubound,
447 write_arb_data[i][w_order].ubound);
448 } else {
449
450 val = REG_RD(bp, write_arb_addr[i].l);
451 REG_WR(bp, write_arb_addr[i].l,
452 val | (write_arb_data[i][w_order].l << 10));
453
454 val = REG_RD(bp, write_arb_addr[i].add);
455 REG_WR(bp, write_arb_addr[i].add,
456 val | (write_arb_data[i][w_order].add << 10));
457
458 val = REG_RD(bp, write_arb_addr[i].ubound);
459 REG_WR(bp, write_arb_addr[i].ubound,
460 val | (write_arb_data[i][w_order].ubound << 7));
461 }
462 }
463
464 val = write_arb_data[NUM_WR_Q-1][w_order].add;
465 val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
466 val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
467 REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val);
468
469 val = read_arb_data[NUM_RD_Q-1][r_order].add;
470 val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
471 val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
472 REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val);
473
474 REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order);
475 REG_WR(bp, PXP2_REG_RQ_WR_MBS0 + 8, w_order);
476 REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order);
477 REG_WR(bp, PXP2_REG_RQ_RD_MBS0 + 8, r_order);
478
479 REG_WR(bp, PXP2_REG_WR_DMAE_TH, (128 << w_order)/16);
480}
481
482
483/****************************************************************************
484* CDU
485****************************************************************************/
486
487#define CDU_REGION_NUMBER_XCM_AG 2
488#define CDU_REGION_NUMBER_UCM_AG 4
489
490/**
491 * String-to-compress [31:8] = CID (all 24 bits)
492 * String-to-compress [7:4] = Region
493 * String-to-compress [3:0] = Type
494 */
495#define CDU_VALID_DATA(_cid, _region, _type) \
496 (((_cid) << 8) | (((_region) & 0xf) << 4) | (((_type) & 0xf)))
497#define CDU_CRC8(_cid, _region, _type) \
498 calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)
499#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \
500 (0x80 | (CDU_CRC8(_cid, _region, _type) & 0x7f))
501#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type) \
502 (0x80 | ((_type) & 0xf << 3) | (CDU_CRC8(_cid, _region, _type) & 0x7))
503#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
504
505/*****************************************************************************
506 * Description:
507 * Calculates crc 8 on a word value: polynomial 0-1-2-8
508 * Code was translated from Verilog.
509 ****************************************************************************/
510static u8 calc_crc8(u32 data, u8 crc)
511{
512 u8 D[32];
513 u8 NewCRC[8];
514 u8 C[8];
515 u8 crc_res;
516 u8 i;
517
518 /* split the data into 31 bits */
519 for (i = 0; i < 32; i++) {
520 D[i] = data & 1;
521 data = data >> 1;
522 }
523
524 /* split the crc into 8 bits */
525 for (i = 0; i < 8; i++) {
526 C[i] = crc & 1;
527 crc = crc >> 1;
528 }
529
530 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
531 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
532 C[6] ^ C[7];
533 NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
534 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
535 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6];
536 NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
537 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
538 C[0] ^ C[1] ^ C[4] ^ C[5];
539 NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
540 D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
541 C[1] ^ C[2] ^ C[5] ^ C[6];
542 NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
543 D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
544 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
545 NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
546 D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
547 C[3] ^ C[4] ^ C[7];
548 NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
549 D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
550 C[5];
551 NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
552 D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
553 C[6];
554
555 crc_res = 0;
556 for (i = 0; i < 8; i++)
557 crc_res |= (NewCRC[i] << i);
558
559 return crc_res;
560}
561
562
563#endif /* BNX2X_INIT_H */
564
diff --git a/drivers/net/bnx2x_init_values.h b/drivers/net/bnx2x_init_values.h
new file mode 100644
index 000000000000..bef0a9b19d68
--- /dev/null
+++ b/drivers/net/bnx2x_init_values.h
@@ -0,0 +1,6368 @@
1#ifndef __BNX2X_INIT_VALUES_H__
2#define __BNX2X_INIT_VALUES_H__
3
4/* This array contains the list of operations needed to initialize the chip.
5 *
6 * For each block in the chip there are three init stages:
7 * common - HW used by both ports,
8 * port1 and port2 - initialization for a specific Ethernet port.
9 * When a port is opened or closed, the management CPU tells the driver
10 * whether to init/disable common HW in addition to the port HW.
11 * This way the first port going up will first initializes the common HW,
12 * and the last port going down also resets the common HW
13 *
14 * For each init stage/block there is a list of actions needed in a format:
15 * {operation, register, data}
16 * where:
17 * OP_WR - write a value to the chip.
18 * OP_RD - read a register (usually a clear on read register).
19 * OP_SW - string write, write a section of consecutive addresses to the chip.
20 * OP_SI - copy a string using indirect writes.
21 * OP_ZR - clear a range of memory.
22 * OP_ZP - unzip and copy using DMAE.
23 * OP_WB - string copy using DMAE.
24 *
25 * The #defines mark the stages.
26 *
27 */
28
29static const struct raw_op init_ops[] = {
30#define PRS_COMMON_START 0
31 {OP_WR, PRS_REG_INC_VALUE, 0xf},
32 {OP_WR, PRS_REG_EVENT_ID_1, 0x45},
33 {OP_WR, PRS_REG_EVENT_ID_2, 0x84},
34 {OP_WR, PRS_REG_EVENT_ID_3, 0x6},
35 {OP_WR, PRS_REG_NO_MATCH_EVENT_ID, 0x4},
36 {OP_WR, PRS_REG_CM_HDR_TYPE_0, 0x0},
37 {OP_WR, PRS_REG_CM_HDR_TYPE_1, 0x12170000},
38 {OP_WR, PRS_REG_CM_HDR_TYPE_2, 0x22170000},
39 {OP_WR, PRS_REG_CM_HDR_TYPE_3, 0x32170000},
40 {OP_ZR, PRS_REG_CM_HDR_TYPE_4, 0x5},
41 {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_1, 0x12150000},
42 {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_2, 0x22150000},
43 {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_3, 0x32150000},
44 {OP_ZR, PRS_REG_CM_HDR_LOOPBACK_TYPE_4, 0x4},
45 {OP_WR, PRS_REG_CM_NO_MATCH_HDR, 0x2100000},
46 {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0, 0x100000},
47 {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1, 0x10100000},
48 {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2, 0x20100000},
49 {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3, 0x30100000},
50 {OP_ZR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x4},
51 {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0, 0x100000},
52 {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1, 0x12140000},
53 {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2, 0x22140000},
54 {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3, 0x32140000},
55 {OP_ZR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x4},
56 {OP_RD, PRS_REG_NUM_OF_PACKETS, 0x0},
57 {OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0},
58 {OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0},
59 {OP_RD, PRS_REG_NUM_OF_DEAD_CYCLES, 0x0},
60 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_0, 0xff},
61 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_1, 0xff},
62 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_2, 0xff},
63 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_3, 0xff},
64 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_4, 0xff},
65 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_5, 0xff},
66 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_6, 0xff},
67 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_7, 0xff},
68 {OP_WR, PRS_REG_PURE_REGIONS, 0x3e},
69 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_0, 0x0},
70 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_1, 0x3f},
71 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_2, 0x3f},
72 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_3, 0x3f},
73 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_4, 0x0},
74 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_5, 0x3f},
75 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_6, 0x3f},
76 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_7, 0x3f},
77#define PRS_COMMON_END 46
78#define PRS_PORT0_START 46
79 {OP_WR, PRS_REG_CID_PORT_0, 0x0},
80#define PRS_PORT0_END 47
81#define PRS_PORT1_START 47
82 {OP_WR, PRS_REG_CID_PORT_1, 0x800000},
83#define PRS_PORT1_END 48
84#define TSDM_COMMON_START 48
85 {OP_WR, TSDM_REG_CFC_RSP_START_ADDR, 0x411},
86 {OP_WR, TSDM_REG_CMP_COUNTER_START_ADDR, 0x400},
87 {OP_WR, TSDM_REG_Q_COUNTER_START_ADDR, 0x404},
88 {OP_WR, TSDM_REG_PCK_END_MSG_START_ADDR, 0x419},
89 {OP_WR, TSDM_REG_CMP_COUNTER_MAX0, 0xffff},
90 {OP_WR, TSDM_REG_CMP_COUNTER_MAX1, 0xffff},
91 {OP_WR, TSDM_REG_CMP_COUNTER_MAX2, 0xffff},
92 {OP_WR, TSDM_REG_CMP_COUNTER_MAX3, 0xffff},
93 {OP_ZR, TSDM_REG_AGG_INT_EVENT_0, 0x80},
94 {OP_WR, TSDM_REG_ENABLE_IN1, 0x7ffffff},
95 {OP_WR, TSDM_REG_ENABLE_IN2, 0x3f},
96 {OP_WR, TSDM_REG_ENABLE_OUT1, 0x7ffffff},
97 {OP_WR, TSDM_REG_ENABLE_OUT2, 0xf},
98 {OP_RD, TSDM_REG_NUM_OF_Q0_CMD, 0x0},
99 {OP_RD, TSDM_REG_NUM_OF_Q1_CMD, 0x0},
100 {OP_RD, TSDM_REG_NUM_OF_Q3_CMD, 0x0},
101 {OP_RD, TSDM_REG_NUM_OF_Q4_CMD, 0x0},
102 {OP_RD, TSDM_REG_NUM_OF_Q5_CMD, 0x0},
103 {OP_RD, TSDM_REG_NUM_OF_Q6_CMD, 0x0},
104 {OP_RD, TSDM_REG_NUM_OF_Q7_CMD, 0x0},
105 {OP_RD, TSDM_REG_NUM_OF_Q8_CMD, 0x0},
106 {OP_RD, TSDM_REG_NUM_OF_Q9_CMD, 0x0},
107 {OP_RD, TSDM_REG_NUM_OF_Q10_CMD, 0x0},
108 {OP_RD, TSDM_REG_NUM_OF_Q11_CMD, 0x0},
109 {OP_RD, TSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
110 {OP_RD, TSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
111 {OP_RD, TSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
112 {OP_WR, TSDM_REG_TIMER_TICK, 0x3e8},
113#define TSDM_COMMON_END 76
114#define TCM_COMMON_START 76
115 {OP_WR, TCM_REG_XX_MAX_LL_SZ, 0x20},
116 {OP_WR, TCM_REG_XX_OVFL_EVNT_ID, 0x32},
117 {OP_WR, TCM_REG_TQM_TCM_HDR_P, 0x2150020},
118 {OP_WR, TCM_REG_TQM_TCM_HDR_S, 0x2150020},
119 {OP_WR, TCM_REG_TM_TCM_HDR, 0x30},
120 {OP_WR, TCM_REG_ERR_TCM_HDR, 0x8100000},
121 {OP_WR, TCM_REG_ERR_EVNT_ID, 0x33},
122 {OP_WR, TCM_REG_EXPR_EVNT_ID, 0x30},
123 {OP_WR, TCM_REG_STOP_EVNT_ID, 0x31},
124 {OP_WR, TCM_REG_PRS_WEIGHT, 0x4},
125 {OP_WR, TCM_REG_PBF_WEIGHT, 0x5},
126 {OP_WR, TCM_REG_CP_WEIGHT, 0x0},
127 {OP_WR, TCM_REG_TSDM_WEIGHT, 0x4},
128 {OP_WR, TCM_REG_TCM_TQM_USE_Q, 0x1},
129 {OP_WR, TCM_REG_GR_ARB_TYPE, 0x1},
130 {OP_WR, TCM_REG_GR_LD0_PR, 0x1},
131 {OP_WR, TCM_REG_GR_LD1_PR, 0x2},
132 {OP_WR, TCM_REG_CFC_INIT_CRD, 0x1},
133 {OP_WR, TCM_REG_FIC0_INIT_CRD, 0x40},
134 {OP_WR, TCM_REG_FIC1_INIT_CRD, 0x40},
135 {OP_WR, TCM_REG_TQM_INIT_CRD, 0x20},
136 {OP_WR, TCM_REG_XX_INIT_CRD, 0x13},
137 {OP_WR, TCM_REG_XX_MSG_NUM, 0x20},
138 {OP_ZR, TCM_REG_XX_TABLE, 0xa},
139 {OP_SW, TCM_REG_XX_DESCR_TABLE, 0x200000},
140 {OP_WR, TCM_REG_N_SM_CTX_LD_0, 0x7},
141 {OP_WR, TCM_REG_N_SM_CTX_LD_1, 0x7},
142 {OP_WR, TCM_REG_N_SM_CTX_LD_2, 0x8},
143 {OP_WR, TCM_REG_N_SM_CTX_LD_3, 0x8},
144 {OP_ZR, TCM_REG_N_SM_CTX_LD_4, 0x4},
145 {OP_WR, TCM_REG_TCM_REG0_SZ, 0x6},
146 {OP_WR, TCM_REG_PHYS_QNUM0_0, 0xd},
147 {OP_WR, TCM_REG_PHYS_QNUM0_1, 0x2d},
148 {OP_ZR, TCM_REG_PHYS_QNUM1_0, 0x6},
149 {OP_WR, TCM_REG_TCM_STORM0_IFEN, 0x1},
150 {OP_WR, TCM_REG_TCM_STORM1_IFEN, 0x1},
151 {OP_WR, TCM_REG_TCM_TQM_IFEN, 0x1},
152 {OP_WR, TCM_REG_STORM_TCM_IFEN, 0x1},
153 {OP_WR, TCM_REG_TQM_TCM_IFEN, 0x1},
154 {OP_WR, TCM_REG_TSDM_IFEN, 0x1},
155 {OP_WR, TCM_REG_TM_TCM_IFEN, 0x1},
156 {OP_WR, TCM_REG_PRS_IFEN, 0x1},
157 {OP_WR, TCM_REG_PBF_IFEN, 0x1},
158 {OP_WR, TCM_REG_USEM_IFEN, 0x1},
159 {OP_WR, TCM_REG_CSEM_IFEN, 0x1},
160 {OP_WR, TCM_REG_CDU_AG_WR_IFEN, 0x1},
161 {OP_WR, TCM_REG_CDU_AG_RD_IFEN, 0x1},
162 {OP_WR, TCM_REG_CDU_SM_WR_IFEN, 0x1},
163 {OP_WR, TCM_REG_CDU_SM_RD_IFEN, 0x1},
164 {OP_WR, TCM_REG_TCM_CFC_IFEN, 0x1},
165#define TCM_COMMON_END 126
166#define BRB1_COMMON_START 126
167 {OP_SW, BRB1_REG_LL_RAM, 0x2000020},
168 {OP_WR, BRB1_REG_SOFT_RESET, 0x1},
169 {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_0, 0x0},
170 {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_1, 0x0},
171 {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_2, 0x0},
172 {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_3, 0x0},
173 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_0, 0x0},
174 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_1, 0x0},
175 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_2, 0x0},
176 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_3, 0x0},
177 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_4, 0x0},
178 {OP_SW, BRB1_REG_FREE_LIST_PRS_CRDT, 0x30220},
179 {OP_WR, BRB1_REG_SOFT_RESET, 0x0},
180#define BRB1_COMMON_END 139
181#define TSEM_COMMON_START 139
182 {OP_RD, TSEM_REG_MSG_NUM_FIC0, 0x0},
183 {OP_RD, TSEM_REG_MSG_NUM_FIC1, 0x0},
184 {OP_RD, TSEM_REG_MSG_NUM_FOC0, 0x0},
185 {OP_RD, TSEM_REG_MSG_NUM_FOC1, 0x0},
186 {OP_RD, TSEM_REG_MSG_NUM_FOC2, 0x0},
187 {OP_RD, TSEM_REG_MSG_NUM_FOC3, 0x0},
188 {OP_WR, TSEM_REG_ARB_ELEMENT0, 0x1},
189 {OP_WR, TSEM_REG_ARB_ELEMENT1, 0x2},
190 {OP_WR, TSEM_REG_ARB_ELEMENT2, 0x3},
191 {OP_WR, TSEM_REG_ARB_ELEMENT3, 0x0},
192 {OP_WR, TSEM_REG_ARB_ELEMENT4, 0x4},
193 {OP_WR, TSEM_REG_ARB_CYCLE_SIZE, 0x1},
194 {OP_WR, TSEM_REG_TS_0_AS, 0x0},
195 {OP_WR, TSEM_REG_TS_1_AS, 0x1},
196 {OP_WR, TSEM_REG_TS_2_AS, 0x4},
197 {OP_WR, TSEM_REG_TS_3_AS, 0x0},
198 {OP_WR, TSEM_REG_TS_4_AS, 0x1},
199 {OP_WR, TSEM_REG_TS_5_AS, 0x3},
200 {OP_WR, TSEM_REG_TS_6_AS, 0x0},
201 {OP_WR, TSEM_REG_TS_7_AS, 0x1},
202 {OP_WR, TSEM_REG_TS_8_AS, 0x4},
203 {OP_WR, TSEM_REG_TS_9_AS, 0x0},
204 {OP_WR, TSEM_REG_TS_10_AS, 0x1},
205 {OP_WR, TSEM_REG_TS_11_AS, 0x3},
206 {OP_WR, TSEM_REG_TS_12_AS, 0x0},
207 {OP_WR, TSEM_REG_TS_13_AS, 0x1},
208 {OP_WR, TSEM_REG_TS_14_AS, 0x4},
209 {OP_WR, TSEM_REG_TS_15_AS, 0x0},
210 {OP_WR, TSEM_REG_TS_16_AS, 0x4},
211 {OP_WR, TSEM_REG_TS_17_AS, 0x3},
212 {OP_ZR, TSEM_REG_TS_18_AS, 0x2},
213 {OP_WR, TSEM_REG_ENABLE_IN, 0x3fff},
214 {OP_WR, TSEM_REG_ENABLE_OUT, 0x3ff},
215 {OP_WR, TSEM_REG_FIC0_DISABLE, 0x0},
216 {OP_WR, TSEM_REG_FIC1_DISABLE, 0x0},
217 {OP_WR, TSEM_REG_PAS_DISABLE, 0x0},
218 {OP_WR, TSEM_REG_THREADS_LIST, 0xff},
219 {OP_ZR, TSEM_REG_PASSIVE_BUFFER, 0x400},
220 {OP_WR, TSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
221 {OP_WR, TSEM_REG_FAST_MEMORY + 0x18000, 0x34},
222 {OP_WR, TSEM_REG_FAST_MEMORY + 0x18040, 0x18},
223 {OP_WR, TSEM_REG_FAST_MEMORY + 0x18080, 0xc},
224 {OP_WR, TSEM_REG_FAST_MEMORY + 0x180c0, 0x20},
225 {OP_WR, TSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
226 {OP_WR, TSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
227 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2000, 0x1b3},
228 {OP_SW, TSEM_REG_FAST_MEMORY + 0x2000 + 0x6cc, 0x10223},
229 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
230 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1000, 0x2},
231 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x800, 0x2},
232 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x808, 0x2},
233 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x810, 0x4},
234 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1fa0, 0x4},
235 {OP_SW, TSEM_REG_FAST_MEMORY + 0x4cf0, 0x80224},
236 {OP_ZP, TSEM_REG_INT_TABLE, 0x8c022c},
237 {OP_ZP, TSEM_REG_PRAM, 0x3395024f},
238 {OP_ZP, TSEM_REG_PRAM + 0x8000, 0x2c760f35},
239 {OP_ZP, TSEM_REG_PRAM + 0x10000, 0x5e1a53},
240 {OP_ZP, TSEM_REG_PRAM + 0x18000, 0x5e1a6b},
241 {OP_ZP, TSEM_REG_PRAM + 0x20000, 0x5e1a83},
242 {OP_ZP, TSEM_REG_PRAM + 0x28000, 0x5e1a9b},
243 {OP_ZP, TSEM_REG_PRAM + 0x30000, 0x5e1ab3},
244 {OP_ZP, TSEM_REG_PRAM + 0x38000, 0x5e1acb},
245#define TSEM_COMMON_END 202
246#define TSEM_PORT0_START 202
247 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x4000, 0x16c},
248 {OP_SW, TSEM_REG_FAST_MEMORY + 0x4000 + 0x5b0, 0x21ae3},
249 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1370, 0xa},
250 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x13c0, 0x6},
251 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1418, 0xc},
252 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1478, 0x12},
253 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1508, 0x90},
254 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x800, 0x2},
255 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x820, 0x10},
256 {OP_SW, TSEM_REG_FAST_MEMORY + 0x820 + 0x40, 0x21ae5},
257 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2908, 0xa},
258#define TSEM_PORT0_END 213
259#define TSEM_PORT1_START 213
260 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x45b8, 0x16c},
261 {OP_SW, TSEM_REG_FAST_MEMORY + 0x45b8 + 0x5b0, 0x21ae7},
262 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1398, 0xa},
263 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x13d8, 0x6},
264 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1448, 0xc},
265 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x14c0, 0x12},
266 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1748, 0x90},
267 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x808, 0x2},
268 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x868, 0x10},
269 {OP_SW, TSEM_REG_FAST_MEMORY + 0x868 + 0x40, 0x21ae9},
270 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2930, 0xa},
271#define TSEM_PORT1_END 224
272#define MISC_COMMON_START 224
273 {OP_WR, MISC_REG_GRC_TIMEOUT_EN, 0x1},
274 {OP_WR, MISC_REG_PLL_STORM_CTRL_1, 0x71d2911},
275 {OP_WR, MISC_REG_PLL_STORM_CTRL_2, 0x0},
276 {OP_WR, MISC_REG_PLL_STORM_CTRL_3, 0x9c0424},
277 {OP_WR, MISC_REG_PLL_STORM_CTRL_4, 0x0},
278 {OP_WR, MISC_REG_LCPLL_CTRL_1, 0x209},
279#define MISC_COMMON_END 230
280#define NIG_COMMON_START 230
281 {OP_WR, NIG_REG_PBF_LB_IN_EN, 0x1},
282 {OP_WR, NIG_REG_PRS_REQ_IN_EN, 0x1},
283 {OP_WR, NIG_REG_EGRESS_DEBUG_IN_EN, 0x1},
284 {OP_WR, NIG_REG_BRB_LB_OUT_EN, 0x1},
285 {OP_WR, NIG_REG_PRS_EOP_OUT_EN, 0x1},
286#define NIG_COMMON_END 235
287#define NIG_PORT0_START 235
288 {OP_WR, NIG_REG_LLH0_CM_HEADER, 0x300000},
289 {OP_WR, NIG_REG_LLH0_EVENT_ID, 0x26},
290 {OP_WR, NIG_REG_LLH0_ERROR_MASK, 0x0},
291 {OP_WR, NIG_REG_LLH0_XCM_MASK, 0x4},
292 {OP_WR, NIG_REG_LLH0_BRB1_NOT_MCP, 0x1},
293 {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT0, 0x0},
294 {OP_WR, NIG_REG_LLH0_XCM_INIT_CREDIT, 0x30},
295 {OP_WR, NIG_REG_BRB0_PAUSE_IN_EN, 0x1},
296 {OP_WR, NIG_REG_EGRESS_PBF0_IN_EN, 0x1},
297 {OP_WR, NIG_REG_BRB0_OUT_EN, 0x1},
298 {OP_WR, NIG_REG_XCM0_OUT_EN, 0x1},
299#define NIG_PORT0_END 246
300#define NIG_PORT1_START 246
301 {OP_WR, NIG_REG_LLH1_CM_HEADER, 0x300000},
302 {OP_WR, NIG_REG_LLH1_EVENT_ID, 0x26},
303 {OP_WR, NIG_REG_LLH1_ERROR_MASK, 0x0},
304 {OP_WR, NIG_REG_LLH1_XCM_MASK, 0x4},
305 {OP_WR, NIG_REG_LLH1_BRB1_NOT_MCP, 0x1},
306 {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT1, 0x0},
307 {OP_WR, NIG_REG_LLH1_XCM_INIT_CREDIT, 0x30},
308 {OP_WR, NIG_REG_BRB1_PAUSE_IN_EN, 0x1},
309 {OP_WR, NIG_REG_EGRESS_PBF1_IN_EN, 0x1},
310 {OP_WR, NIG_REG_BRB1_OUT_EN, 0x1},
311 {OP_WR, NIG_REG_XCM1_OUT_EN, 0x1},
312#define NIG_PORT1_END 257
313#define UPB_COMMON_START 257
314 {OP_WR, GRCBASE_UPB + PB_REG_CONTROL, 0x20},
315#define UPB_COMMON_END 258
316#define CSDM_COMMON_START 258
317 {OP_WR, CSDM_REG_CFC_RSP_START_ADDR, 0xa11},
318 {OP_WR, CSDM_REG_CMP_COUNTER_START_ADDR, 0xa00},
319 {OP_WR, CSDM_REG_Q_COUNTER_START_ADDR, 0xa04},
320 {OP_WR, CSDM_REG_CMP_COUNTER_MAX0, 0xffff},
321 {OP_WR, CSDM_REG_CMP_COUNTER_MAX1, 0xffff},
322 {OP_WR, CSDM_REG_CMP_COUNTER_MAX2, 0xffff},
323 {OP_WR, CSDM_REG_CMP_COUNTER_MAX3, 0xffff},
324 {OP_ZR, CSDM_REG_AGG_INT_EVENT_0, 0x80},
325 {OP_WR, CSDM_REG_ENABLE_IN1, 0x7ffffff},
326 {OP_WR, CSDM_REG_ENABLE_IN2, 0x3f},
327 {OP_WR, CSDM_REG_ENABLE_OUT1, 0x7ffffff},
328 {OP_WR, CSDM_REG_ENABLE_OUT2, 0xf},
329 {OP_RD, CSDM_REG_NUM_OF_Q0_CMD, 0x0},
330 {OP_RD, CSDM_REG_NUM_OF_Q1_CMD, 0x0},
331 {OP_RD, CSDM_REG_NUM_OF_Q3_CMD, 0x0},
332 {OP_RD, CSDM_REG_NUM_OF_Q4_CMD, 0x0},
333 {OP_RD, CSDM_REG_NUM_OF_Q5_CMD, 0x0},
334 {OP_RD, CSDM_REG_NUM_OF_Q6_CMD, 0x0},
335 {OP_RD, CSDM_REG_NUM_OF_Q7_CMD, 0x0},
336 {OP_RD, CSDM_REG_NUM_OF_Q8_CMD, 0x0},
337 {OP_RD, CSDM_REG_NUM_OF_Q9_CMD, 0x0},
338 {OP_RD, CSDM_REG_NUM_OF_Q10_CMD, 0x0},
339 {OP_RD, CSDM_REG_NUM_OF_Q11_CMD, 0x0},
340 {OP_RD, CSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
341 {OP_RD, CSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
342 {OP_RD, CSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
343 {OP_WR, CSDM_REG_TIMER_TICK, 0x3e8},
344#define CSDM_COMMON_END 285
345#define USDM_COMMON_START 285
346 {OP_WR, USDM_REG_CFC_RSP_START_ADDR, 0xa11},
347 {OP_WR, USDM_REG_CMP_COUNTER_START_ADDR, 0xa00},
348 {OP_WR, USDM_REG_Q_COUNTER_START_ADDR, 0xa04},
349 {OP_WR, USDM_REG_PCK_END_MSG_START_ADDR, 0xa21},
350 {OP_WR, USDM_REG_CMP_COUNTER_MAX0, 0xffff},
351 {OP_WR, USDM_REG_CMP_COUNTER_MAX1, 0xffff},
352 {OP_WR, USDM_REG_CMP_COUNTER_MAX2, 0xffff},
353 {OP_WR, USDM_REG_CMP_COUNTER_MAX3, 0xffff},
354 {OP_WR, USDM_REG_AGG_INT_EVENT_0, 0x46},
355 {OP_ZR, USDM_REG_AGG_INT_EVENT_1, 0x5f},
356 {OP_WR, USDM_REG_AGG_INT_MODE_0, 0x1},
357 {OP_ZR, USDM_REG_AGG_INT_MODE_1, 0x1f},
358 {OP_WR, USDM_REG_ENABLE_IN1, 0x7ffffff},
359 {OP_WR, USDM_REG_ENABLE_IN2, 0x3f},
360 {OP_WR, USDM_REG_ENABLE_OUT1, 0x7ffffff},
361 {OP_WR, USDM_REG_ENABLE_OUT2, 0xf},
362 {OP_RD, USDM_REG_NUM_OF_Q0_CMD, 0x0},
363 {OP_RD, USDM_REG_NUM_OF_Q1_CMD, 0x0},
364 {OP_RD, USDM_REG_NUM_OF_Q2_CMD, 0x0},
365 {OP_RD, USDM_REG_NUM_OF_Q3_CMD, 0x0},
366 {OP_RD, USDM_REG_NUM_OF_Q4_CMD, 0x0},
367 {OP_RD, USDM_REG_NUM_OF_Q5_CMD, 0x0},
368 {OP_RD, USDM_REG_NUM_OF_Q6_CMD, 0x0},
369 {OP_RD, USDM_REG_NUM_OF_Q7_CMD, 0x0},
370 {OP_RD, USDM_REG_NUM_OF_Q8_CMD, 0x0},
371 {OP_RD, USDM_REG_NUM_OF_Q9_CMD, 0x0},
372 {OP_RD, USDM_REG_NUM_OF_Q10_CMD, 0x0},
373 {OP_RD, USDM_REG_NUM_OF_Q11_CMD, 0x0},
374 {OP_RD, USDM_REG_NUM_OF_PKT_END_MSG, 0x0},
375 {OP_RD, USDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
376 {OP_RD, USDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
377 {OP_WR, USDM_REG_TIMER_TICK, 0x3e8},
378#define USDM_COMMON_END 317
379#define CCM_COMMON_START 317
380 {OP_WR, CCM_REG_XX_OVFL_EVNT_ID, 0x32},
381 {OP_WR, CCM_REG_CQM_CCM_HDR_P, 0x2150020},
382 {OP_WR, CCM_REG_CQM_CCM_HDR_S, 0x2150020},
383 {OP_WR, CCM_REG_ERR_CCM_HDR, 0x8100000},
384 {OP_WR, CCM_REG_ERR_EVNT_ID, 0x33},
385 {OP_WR, CCM_REG_TSEM_WEIGHT, 0x0},
386 {OP_WR, CCM_REG_XSEM_WEIGHT, 0x4},
387 {OP_WR, CCM_REG_USEM_WEIGHT, 0x4},
388 {OP_ZR, CCM_REG_PBF_WEIGHT, 0x2},
389 {OP_WR, CCM_REG_CQM_P_WEIGHT, 0x2},
390 {OP_WR, CCM_REG_CCM_CQM_USE_Q, 0x1},
391 {OP_WR, CCM_REG_CNT_AUX1_Q, 0x2},
392 {OP_WR, CCM_REG_CNT_AUX2_Q, 0x2},
393 {OP_WR, CCM_REG_INV_DONE_Q, 0x1},
394 {OP_WR, CCM_REG_GR_ARB_TYPE, 0x1},
395 {OP_WR, CCM_REG_GR_LD0_PR, 0x1},
396 {OP_WR, CCM_REG_GR_LD1_PR, 0x2},
397 {OP_WR, CCM_REG_CFC_INIT_CRD, 0x1},
398 {OP_WR, CCM_REG_CQM_INIT_CRD, 0x20},
399 {OP_WR, CCM_REG_FIC0_INIT_CRD, 0x40},
400 {OP_WR, CCM_REG_FIC1_INIT_CRD, 0x40},
401 {OP_WR, CCM_REG_XX_INIT_CRD, 0x3},
402 {OP_WR, CCM_REG_XX_MSG_NUM, 0x18},
403 {OP_ZR, CCM_REG_XX_TABLE, 0x12},
404 {OP_SW, CCM_REG_XX_DESCR_TABLE, 0x241aeb},
405 {OP_WR, CCM_REG_N_SM_CTX_LD_0, 0x1},
406 {OP_WR, CCM_REG_N_SM_CTX_LD_1, 0x2},
407 {OP_WR, CCM_REG_N_SM_CTX_LD_2, 0x8},
408 {OP_WR, CCM_REG_N_SM_CTX_LD_3, 0x8},
409 {OP_ZR, CCM_REG_N_SM_CTX_LD_4, 0x4},
410 {OP_WR, CCM_REG_CCM_REG0_SZ, 0x4},
411 {OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x9},
412 {OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x29},
413 {OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0xa},
414 {OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a},
415 {OP_ZR, CCM_REG_QOS_PHYS_QNUM2_0, 0x4},
416 {OP_WR, CCM_REG_PHYS_QNUM1_0, 0xc},
417 {OP_WR, CCM_REG_PHYS_QNUM1_1, 0x2c},
418 {OP_WR, CCM_REG_PHYS_QNUM2_0, 0xb},
419 {OP_WR, CCM_REG_PHYS_QNUM2_1, 0x2b},
420 {OP_ZR, CCM_REG_PHYS_QNUM3_0, 0x2},
421 {OP_WR, CCM_REG_CCM_STORM0_IFEN, 0x1},
422 {OP_WR, CCM_REG_CCM_STORM1_IFEN, 0x1},
423 {OP_WR, CCM_REG_CCM_CQM_IFEN, 0x1},
424 {OP_WR, CCM_REG_STORM_CCM_IFEN, 0x1},
425 {OP_WR, CCM_REG_CQM_CCM_IFEN, 0x1},
426 {OP_WR, CCM_REG_CSDM_IFEN, 0x1},
427 {OP_WR, CCM_REG_TSEM_IFEN, 0x1},
428 {OP_WR, CCM_REG_XSEM_IFEN, 0x1},
429 {OP_WR, CCM_REG_USEM_IFEN, 0x1},
430 {OP_WR, CCM_REG_PBF_IFEN, 0x1},
431 {OP_WR, CCM_REG_CDU_AG_WR_IFEN, 0x1},
432 {OP_WR, CCM_REG_CDU_AG_RD_IFEN, 0x1},
433 {OP_WR, CCM_REG_CDU_SM_WR_IFEN, 0x1},
434 {OP_WR, CCM_REG_CDU_SM_RD_IFEN, 0x1},
435 {OP_WR, CCM_REG_CCM_CFC_IFEN, 0x1},
436#define CCM_COMMON_END 373
437#define UCM_COMMON_START 373
438 {OP_WR, UCM_REG_XX_OVFL_EVNT_ID, 0x32},
439 {OP_WR, UCM_REG_UQM_UCM_HDR_P, 0x2150020},
440 {OP_WR, UCM_REG_UQM_UCM_HDR_S, 0x2150020},
441 {OP_WR, UCM_REG_TM_UCM_HDR, 0x30},
442 {OP_WR, UCM_REG_ERR_UCM_HDR, 0x8100000},
443 {OP_WR, UCM_REG_ERR_EVNT_ID, 0x33},
444 {OP_WR, UCM_REG_EXPR_EVNT_ID, 0x30},
445 {OP_WR, UCM_REG_STOP_EVNT_ID, 0x31},
446 {OP_WR, UCM_REG_TSEM_WEIGHT, 0x3},
447 {OP_WR, UCM_REG_CSEM_WEIGHT, 0x0},
448 {OP_WR, UCM_REG_CP_WEIGHT, 0x0},
449 {OP_WR, UCM_REG_UQM_P_WEIGHT, 0x6},
450 {OP_WR, UCM_REG_UCM_UQM_USE_Q, 0x1},
451 {OP_WR, UCM_REG_INV_CFLG_Q, 0x1},
452 {OP_WR, UCM_REG_GR_ARB_TYPE, 0x1},
453 {OP_WR, UCM_REG_GR_LD0_PR, 0x1},
454 {OP_WR, UCM_REG_GR_LD1_PR, 0x2},
455 {OP_WR, UCM_REG_CFC_INIT_CRD, 0x1},
456 {OP_WR, UCM_REG_FIC0_INIT_CRD, 0x40},
457 {OP_WR, UCM_REG_FIC1_INIT_CRD, 0x40},
458 {OP_WR, UCM_REG_TM_INIT_CRD, 0x4},
459 {OP_WR, UCM_REG_UQM_INIT_CRD, 0x20},
460 {OP_WR, UCM_REG_XX_INIT_CRD, 0xc},
461 {OP_WR, UCM_REG_XX_MSG_NUM, 0x20},
462 {OP_ZR, UCM_REG_XX_TABLE, 0x12},
463 {OP_SW, UCM_REG_XX_DESCR_TABLE, 0x201b0f},
464 {OP_WR, UCM_REG_N_SM_CTX_LD_0, 0xa},
465 {OP_WR, UCM_REG_N_SM_CTX_LD_1, 0x7},
466 {OP_WR, UCM_REG_N_SM_CTX_LD_2, 0xf},
467 {OP_WR, UCM_REG_N_SM_CTX_LD_3, 0x10},
468 {OP_ZR, UCM_REG_N_SM_CTX_LD_4, 0x4},
469 {OP_WR, UCM_REG_UCM_REG0_SZ, 0x3},
470 {OP_WR, UCM_REG_PHYS_QNUM0_0, 0xf},
471 {OP_WR, UCM_REG_PHYS_QNUM0_1, 0x2f},
472 {OP_WR, UCM_REG_PHYS_QNUM1_0, 0xe},
473 {OP_WR, UCM_REG_PHYS_QNUM1_1, 0x2e},
474 {OP_WR, UCM_REG_UCM_STORM0_IFEN, 0x1},
475 {OP_WR, UCM_REG_UCM_STORM1_IFEN, 0x1},
476 {OP_WR, UCM_REG_UCM_UQM_IFEN, 0x1},
477 {OP_WR, UCM_REG_STORM_UCM_IFEN, 0x1},
478 {OP_WR, UCM_REG_UQM_UCM_IFEN, 0x1},
479 {OP_WR, UCM_REG_USDM_IFEN, 0x1},
480 {OP_WR, UCM_REG_TM_UCM_IFEN, 0x1},
481 {OP_WR, UCM_REG_UCM_TM_IFEN, 0x1},
482 {OP_WR, UCM_REG_TSEM_IFEN, 0x1},
483 {OP_WR, UCM_REG_CSEM_IFEN, 0x1},
484 {OP_WR, UCM_REG_XSEM_IFEN, 0x1},
485 {OP_WR, UCM_REG_DORQ_IFEN, 0x1},
486 {OP_WR, UCM_REG_CDU_AG_WR_IFEN, 0x1},
487 {OP_WR, UCM_REG_CDU_AG_RD_IFEN, 0x1},
488 {OP_WR, UCM_REG_CDU_SM_WR_IFEN, 0x1},
489 {OP_WR, UCM_REG_CDU_SM_RD_IFEN, 0x1},
490 {OP_WR, UCM_REG_UCM_CFC_IFEN, 0x1},
491#define UCM_COMMON_END 426
492#define USEM_COMMON_START 426
493 {OP_RD, USEM_REG_MSG_NUM_FIC0, 0x0},
494 {OP_RD, USEM_REG_MSG_NUM_FIC1, 0x0},
495 {OP_RD, USEM_REG_MSG_NUM_FOC0, 0x0},
496 {OP_RD, USEM_REG_MSG_NUM_FOC1, 0x0},
497 {OP_RD, USEM_REG_MSG_NUM_FOC2, 0x0},
498 {OP_RD, USEM_REG_MSG_NUM_FOC3, 0x0},
499 {OP_WR, USEM_REG_ARB_ELEMENT0, 0x1},
500 {OP_WR, USEM_REG_ARB_ELEMENT1, 0x2},
501 {OP_WR, USEM_REG_ARB_ELEMENT2, 0x3},
502 {OP_WR, USEM_REG_ARB_ELEMENT3, 0x0},
503 {OP_WR, USEM_REG_ARB_ELEMENT4, 0x4},
504 {OP_WR, USEM_REG_ARB_CYCLE_SIZE, 0x1},
505 {OP_WR, USEM_REG_TS_0_AS, 0x0},
506 {OP_WR, USEM_REG_TS_1_AS, 0x1},
507 {OP_WR, USEM_REG_TS_2_AS, 0x4},
508 {OP_WR, USEM_REG_TS_3_AS, 0x0},
509 {OP_WR, USEM_REG_TS_4_AS, 0x1},
510 {OP_WR, USEM_REG_TS_5_AS, 0x3},
511 {OP_WR, USEM_REG_TS_6_AS, 0x0},
512 {OP_WR, USEM_REG_TS_7_AS, 0x1},
513 {OP_WR, USEM_REG_TS_8_AS, 0x4},
514 {OP_WR, USEM_REG_TS_9_AS, 0x0},
515 {OP_WR, USEM_REG_TS_10_AS, 0x1},
516 {OP_WR, USEM_REG_TS_11_AS, 0x3},
517 {OP_WR, USEM_REG_TS_12_AS, 0x0},
518 {OP_WR, USEM_REG_TS_13_AS, 0x1},
519 {OP_WR, USEM_REG_TS_14_AS, 0x4},
520 {OP_WR, USEM_REG_TS_15_AS, 0x0},
521 {OP_WR, USEM_REG_TS_16_AS, 0x4},
522 {OP_WR, USEM_REG_TS_17_AS, 0x3},
523 {OP_ZR, USEM_REG_TS_18_AS, 0x2},
524 {OP_WR, USEM_REG_ENABLE_IN, 0x3fff},
525 {OP_WR, USEM_REG_ENABLE_OUT, 0x3ff},
526 {OP_WR, USEM_REG_FIC0_DISABLE, 0x0},
527 {OP_WR, USEM_REG_FIC1_DISABLE, 0x0},
528 {OP_WR, USEM_REG_PAS_DISABLE, 0x0},
529 {OP_WR, USEM_REG_THREADS_LIST, 0xffff},
530 {OP_ZR, USEM_REG_PASSIVE_BUFFER, 0x800},
531 {OP_WR, USEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
532 {OP_WR, USEM_REG_FAST_MEMORY + 0x18000, 0x1a},
533 {OP_WR, USEM_REG_FAST_MEMORY + 0x18040, 0x4e},
534 {OP_WR, USEM_REG_FAST_MEMORY + 0x18080, 0x10},
535 {OP_WR, USEM_REG_FAST_MEMORY + 0x180c0, 0x20},
536 {OP_WR, USEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
537 {OP_WR, USEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
538 {OP_WR, USEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
539 {OP_ZR, USEM_REG_FAST_MEMORY + 0x5000, 0x102},
540 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1020, 0xc8},
541 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1000, 0x2},
542 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1e20, 0x40},
543 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3000, 0x400},
544 {OP_ZR, USEM_REG_FAST_MEMORY + 0x2400, 0x2},
545 {OP_ZR, USEM_REG_FAST_MEMORY + 0x2408, 0x2},
546 {OP_ZR, USEM_REG_FAST_MEMORY + 0x2410, 0x6},
547 {OP_SW, USEM_REG_FAST_MEMORY + 0x2410 + 0x18, 0x21b2f},
548 {OP_ZR, USEM_REG_FAST_MEMORY + 0x4b68, 0x2},
549 {OP_SW, USEM_REG_FAST_MEMORY + 0x4b68 + 0x8, 0x21b31},
550 {OP_ZR, USEM_REG_FAST_MEMORY + 0x4b10, 0x2},
551 {OP_SW, USEM_REG_FAST_MEMORY + 0x2c30, 0x21b33},
552 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
553 {OP_SW, USEM_REG_FAST_MEMORY + 0x10c00, 0x101b35},
554 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0},
555 {OP_SW, USEM_REG_FAST_MEMORY + 0x10c40, 0x101b45},
556 {OP_ZP, USEM_REG_INT_TABLE, 0xb41b55},
557 {OP_ZP, USEM_REG_PRAM, 0x32d01b82},
558 {OP_ZP, USEM_REG_PRAM + 0x8000, 0x32172836},
559 {OP_ZP, USEM_REG_PRAM + 0x10000, 0x1a7a34bc},
560 {OP_ZP, USEM_REG_PRAM + 0x18000, 0x5f3b5b},
561 {OP_ZP, USEM_REG_PRAM + 0x20000, 0x5f3b73},
562 {OP_ZP, USEM_REG_PRAM + 0x28000, 0x5f3b8b},
563 {OP_ZP, USEM_REG_PRAM + 0x30000, 0x5f3ba3},
564 {OP_ZP, USEM_REG_PRAM + 0x38000, 0x5f3bbb},
565#define USEM_COMMON_END 498
566#define USEM_PORT0_START 498
567 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1400, 0xa0},
568 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1900, 0xa},
569 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1950, 0x2e},
570 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1d00, 0x24},
571 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3000, 0x20},
572 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3100, 0x20},
573 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3200, 0x20},
574 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3300, 0x20},
575 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3400, 0x20},
576 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3500, 0x20},
577 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3600, 0x20},
578 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3700, 0x20},
579 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3800, 0x20},
580 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3900, 0x20},
581 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3a00, 0x20},
582 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3b00, 0x20},
583 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3c00, 0x20},
584 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3d00, 0x20},
585 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3e00, 0x20},
586 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3f00, 0x20},
587 {OP_ZR, USEM_REG_FAST_MEMORY + 0x2400, 0x2},
588 {OP_ZR, USEM_REG_FAST_MEMORY + 0x4b78, 0x52},
589 {OP_ZR, USEM_REG_FAST_MEMORY + 0x4e08, 0xc},
590#define USEM_PORT0_END 521
591#define USEM_PORT1_START 521
592 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1680, 0xa0},
593 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1928, 0xa},
594 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1a08, 0x2e},
595 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1d90, 0x24},
596 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3080, 0x20},
597 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3180, 0x20},
598 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3280, 0x20},
599 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3380, 0x20},
600 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3480, 0x20},
601 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3580, 0x20},
602 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3680, 0x20},
603 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3780, 0x20},
604 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3880, 0x20},
605 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3980, 0x20},
606 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3a80, 0x20},
607 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3b80, 0x20},
608 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3c80, 0x20},
609 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3d80, 0x20},
610 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3e80, 0x20},
611 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3f80, 0x20},
612 {OP_ZR, USEM_REG_FAST_MEMORY + 0x2408, 0x2},
613 {OP_ZR, USEM_REG_FAST_MEMORY + 0x4cc0, 0x52},
614 {OP_ZR, USEM_REG_FAST_MEMORY + 0x4e38, 0xc},
615#define USEM_PORT1_END 544
616#define CSEM_COMMON_START 544
617 {OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0},
618 {OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0},
619 {OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0},
620 {OP_RD, CSEM_REG_MSG_NUM_FOC1, 0x0},
621 {OP_RD, CSEM_REG_MSG_NUM_FOC2, 0x0},
622 {OP_RD, CSEM_REG_MSG_NUM_FOC3, 0x0},
623 {OP_WR, CSEM_REG_ARB_ELEMENT0, 0x1},
624 {OP_WR, CSEM_REG_ARB_ELEMENT1, 0x2},
625 {OP_WR, CSEM_REG_ARB_ELEMENT2, 0x3},
626 {OP_WR, CSEM_REG_ARB_ELEMENT3, 0x0},
627 {OP_WR, CSEM_REG_ARB_ELEMENT4, 0x4},
628 {OP_WR, CSEM_REG_ARB_CYCLE_SIZE, 0x1},
629 {OP_WR, CSEM_REG_TS_0_AS, 0x0},
630 {OP_WR, CSEM_REG_TS_1_AS, 0x1},
631 {OP_WR, CSEM_REG_TS_2_AS, 0x4},
632 {OP_WR, CSEM_REG_TS_3_AS, 0x0},
633 {OP_WR, CSEM_REG_TS_4_AS, 0x1},
634 {OP_WR, CSEM_REG_TS_5_AS, 0x3},
635 {OP_WR, CSEM_REG_TS_6_AS, 0x0},
636 {OP_WR, CSEM_REG_TS_7_AS, 0x1},
637 {OP_WR, CSEM_REG_TS_8_AS, 0x4},
638 {OP_WR, CSEM_REG_TS_9_AS, 0x0},
639 {OP_WR, CSEM_REG_TS_10_AS, 0x1},
640 {OP_WR, CSEM_REG_TS_11_AS, 0x3},
641 {OP_WR, CSEM_REG_TS_12_AS, 0x0},
642 {OP_WR, CSEM_REG_TS_13_AS, 0x1},
643 {OP_WR, CSEM_REG_TS_14_AS, 0x4},
644 {OP_WR, CSEM_REG_TS_15_AS, 0x0},
645 {OP_WR, CSEM_REG_TS_16_AS, 0x4},
646 {OP_WR, CSEM_REG_TS_17_AS, 0x3},
647 {OP_ZR, CSEM_REG_TS_18_AS, 0x2},
648 {OP_WR, CSEM_REG_ENABLE_IN, 0x3fff},
649 {OP_WR, CSEM_REG_ENABLE_OUT, 0x3ff},
650 {OP_WR, CSEM_REG_FIC0_DISABLE, 0x0},
651 {OP_WR, CSEM_REG_FIC1_DISABLE, 0x0},
652 {OP_WR, CSEM_REG_PAS_DISABLE, 0x0},
653 {OP_WR, CSEM_REG_THREADS_LIST, 0xffff},
654 {OP_ZR, CSEM_REG_PASSIVE_BUFFER, 0x800},
655 {OP_WR, CSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
656 {OP_WR, CSEM_REG_FAST_MEMORY + 0x18000, 0x10},
657 {OP_WR, CSEM_REG_FAST_MEMORY + 0x18040, 0x12},
658 {OP_WR, CSEM_REG_FAST_MEMORY + 0x18080, 0x30},
659 {OP_WR, CSEM_REG_FAST_MEMORY + 0x180c0, 0xe},
660 {OP_WR, CSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
661 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x5000, 0x42},
662 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
663 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1000, 0x2},
664 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2000, 0xc0},
665 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3070, 0x80},
666 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x4280, 0x4},
667 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x25c0, 0x240},
668 {OP_SW, CSEM_REG_FAST_MEMORY + 0x25c0 + 0x900, 0x83bd3},
669 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff},
670 {OP_SW, CSEM_REG_FAST_MEMORY + 0x10c00, 0x103bdb},
671 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0},
672 {OP_SW, CSEM_REG_FAST_MEMORY + 0x10c40, 0x103beb},
673 {OP_ZP, CSEM_REG_INT_TABLE, 0x5f3bfb},
674 {OP_ZP, CSEM_REG_PRAM, 0x32423c13},
675 {OP_ZP, CSEM_REG_PRAM + 0x8000, 0xf2148a4},
676 {OP_ZP, CSEM_REG_PRAM + 0x10000, 0x5f4c6d},
677 {OP_ZP, CSEM_REG_PRAM + 0x18000, 0x5f4c85},
678 {OP_ZP, CSEM_REG_PRAM + 0x20000, 0x5f4c9d},
679 {OP_ZP, CSEM_REG_PRAM + 0x28000, 0x5f4cb5},
680 {OP_ZP, CSEM_REG_PRAM + 0x30000, 0x5f4ccd},
681 {OP_ZP, CSEM_REG_PRAM + 0x38000, 0x5f4ce5},
682#define CSEM_COMMON_END 609
683#define CSEM_PORT0_START 609
684 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1400, 0xa0},
685 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1900, 0x10},
686 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1980, 0x30},
687 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2300, 0x2},
688 {OP_SW, CSEM_REG_FAST_MEMORY + 0x2300 + 0x8, 0x24cfd},
689 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3040, 0x6},
690 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2410, 0x30},
691#define CSEM_PORT0_END 616
692#define CSEM_PORT1_START 616
693 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1680, 0xa0},
694 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1940, 0x10},
695 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1a40, 0x30},
696 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2310, 0x2},
697 {OP_SW, CSEM_REG_FAST_MEMORY + 0x2310 + 0x8, 0x24cff},
698 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3058, 0x6},
699 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x24d0, 0x30},
700#define CSEM_PORT1_END 623
701#define XPB_COMMON_START 623
702 {OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x20},
703#define XPB_COMMON_END 624
704#define DQ_COMMON_START 624
705 {OP_WR, DORQ_REG_MODE_ACT, 0x2},
706 {OP_WR, DORQ_REG_NORM_CID_OFST, 0x3},
707 {OP_WR, DORQ_REG_OUTST_REQ, 0x4},
708 {OP_WR, DORQ_REG_DPM_CID_ADDR, 0x8},
709 {OP_WR, DORQ_REG_RSP_INIT_CRD, 0x2},
710 {OP_WR, DORQ_REG_NORM_CMHEAD_TX, 0x90},
711 {OP_WR, DORQ_REG_CMHEAD_RX, 0x90},
712 {OP_WR, DORQ_REG_SHRT_CMHEAD, 0x800090},
713 {OP_WR, DORQ_REG_ERR_CMHEAD, 0x8140000},
714 {OP_WR, DORQ_REG_AGG_CMD0, 0x8a},
715 {OP_WR, DORQ_REG_AGG_CMD1, 0x80},
716 {OP_WR, DORQ_REG_AGG_CMD2, 0x90},
717 {OP_WR, DORQ_REG_AGG_CMD3, 0x80},
718 {OP_WR, DORQ_REG_SHRT_ACT_CNT, 0x6},
719 {OP_WR, DORQ_REG_DQ_FIFO_FULL_TH, 0x7d0},
720 {OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c},
721 {OP_WR, DORQ_REG_REGN, 0x7c1004},
722 {OP_WR, DORQ_REG_IF_EN, 0xf},
723#define DQ_COMMON_END 642
724#define TIMERS_COMMON_START 642
725 {OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2},
726 {OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c},
727 {OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1},
728 {OP_WR, TM_REG_CFC_CLD_CRDCNT_VAL, 0x1},
729 {OP_WR, TM_REG_CLOUT_CRDCNT0_VAL, 0x1},
730 {OP_WR, TM_REG_CLOUT_CRDCNT1_VAL, 0x1},
731 {OP_WR, TM_REG_CLOUT_CRDCNT2_VAL, 0x1},
732 {OP_WR, TM_REG_EXP_CRDCNT_VAL, 0x1},
733 {OP_WR, TM_REG_PCIARB_CRDCNT_VAL, 0x2},
734 {OP_WR, TM_REG_TIMER_TICK_SIZE, 0x3d090},
735 {OP_WR, TM_REG_CL0_CONT_REGION, 0x8},
736 {OP_WR, TM_REG_CL1_CONT_REGION, 0xc},
737 {OP_WR, TM_REG_CL2_CONT_REGION, 0x10},
738 {OP_WR, TM_REG_TM_CONTEXT_REGION, 0x20},
739 {OP_WR, TM_REG_EN_TIMERS, 0x1},
740 {OP_WR, TM_REG_EN_REAL_TIME_CNT, 0x1},
741 {OP_WR, TM_REG_EN_CL0_INPUT, 0x1},
742 {OP_WR, TM_REG_EN_CL1_INPUT, 0x1},
743 {OP_WR, TM_REG_EN_CL2_INPUT, 0x1},
744#define TIMERS_COMMON_END 661
745#define TIMERS_PORT0_START 661
746 {OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2},
747#define TIMERS_PORT0_END 662
748#define TIMERS_PORT1_START 662
749 {OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2},
750#define TIMERS_PORT1_END 663
751#define XSDM_COMMON_START 663
752 {OP_WR, XSDM_REG_CFC_RSP_START_ADDR, 0xa14},
753 {OP_WR, XSDM_REG_CMP_COUNTER_START_ADDR, 0xa00},
754 {OP_WR, XSDM_REG_Q_COUNTER_START_ADDR, 0xa04},
755 {OP_WR, XSDM_REG_CMP_COUNTER_MAX0, 0xffff},
756 {OP_WR, XSDM_REG_CMP_COUNTER_MAX1, 0xffff},
757 {OP_WR, XSDM_REG_CMP_COUNTER_MAX2, 0xffff},
758 {OP_WR, XSDM_REG_CMP_COUNTER_MAX3, 0xffff},
759 {OP_WR, XSDM_REG_AGG_INT_EVENT_0, 0x20},
760 {OP_WR, XSDM_REG_AGG_INT_EVENT_1, 0x20},
761 {OP_ZR, XSDM_REG_AGG_INT_EVENT_2, 0x5e},
762 {OP_WR, XSDM_REG_AGG_INT_MODE_0, 0x1},
763 {OP_ZR, XSDM_REG_AGG_INT_MODE_1, 0x1f},
764 {OP_WR, XSDM_REG_ENABLE_IN1, 0x7ffffff},
765 {OP_WR, XSDM_REG_ENABLE_IN2, 0x3f},
766 {OP_WR, XSDM_REG_ENABLE_OUT1, 0x7ffffff},
767 {OP_WR, XSDM_REG_ENABLE_OUT2, 0xf},
768 {OP_RD, XSDM_REG_NUM_OF_Q0_CMD, 0x0},
769 {OP_RD, XSDM_REG_NUM_OF_Q1_CMD, 0x0},
770 {OP_RD, XSDM_REG_NUM_OF_Q3_CMD, 0x0},
771 {OP_RD, XSDM_REG_NUM_OF_Q4_CMD, 0x0},
772 {OP_RD, XSDM_REG_NUM_OF_Q5_CMD, 0x0},
773 {OP_RD, XSDM_REG_NUM_OF_Q6_CMD, 0x0},
774 {OP_RD, XSDM_REG_NUM_OF_Q7_CMD, 0x0},
775 {OP_RD, XSDM_REG_NUM_OF_Q8_CMD, 0x0},
776 {OP_RD, XSDM_REG_NUM_OF_Q9_CMD, 0x0},
777 {OP_RD, XSDM_REG_NUM_OF_Q10_CMD, 0x0},
778 {OP_RD, XSDM_REG_NUM_OF_Q11_CMD, 0x0},
779 {OP_RD, XSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
780 {OP_RD, XSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
781 {OP_RD, XSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
782 {OP_WR, XSDM_REG_TIMER_TICK, 0x3e8},
783#define XSDM_COMMON_END 694
784#define QM_COMMON_START 694
785 {OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6},
786 {OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5},
787 {OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa},
788 {OP_WR, QM_REG_ACTCTRINITVAL_3, 0x5},
789 {OP_WR, QM_REG_PCIREQAT, 0x2},
790 {OP_WR, QM_REG_CMINITCRD_0, 0x4},
791 {OP_WR, QM_REG_CMINITCRD_1, 0x4},
792 {OP_WR, QM_REG_CMINITCRD_2, 0x4},
793 {OP_WR, QM_REG_CMINITCRD_3, 0x4},
794 {OP_WR, QM_REG_CMINITCRD_4, 0x4},
795 {OP_WR, QM_REG_CMINITCRD_5, 0x4},
796 {OP_WR, QM_REG_CMINITCRD_6, 0x4},
797 {OP_WR, QM_REG_CMINITCRD_7, 0x4},
798 {OP_WR, QM_REG_OUTLDREQ, 0x4},
799 {OP_WR, QM_REG_CTXREG_0, 0x7c},
800 {OP_WR, QM_REG_CTXREG_1, 0x3d},
801 {OP_WR, QM_REG_CTXREG_2, 0x3f},
802 {OP_WR, QM_REG_CTXREG_3, 0x9c},
803 {OP_WR, QM_REG_ENSEC, 0x7},
804 {OP_ZR, QM_REG_QVOQIDX_0, 0x5},
805 {OP_WR, QM_REG_WRRWEIGHTS_0, 0x1010101},
806 {OP_WR, QM_REG_QVOQIDX_5, 0x0},
807 {OP_WR, QM_REG_QVOQIDX_6, 0x4},
808 {OP_WR, QM_REG_QVOQIDX_7, 0x4},
809 {OP_WR, QM_REG_QVOQIDX_8, 0x2},
810 {OP_WR, QM_REG_WRRWEIGHTS_1, 0x8012004},
811 {OP_WR, QM_REG_QVOQIDX_9, 0x5},
812 {OP_WR, QM_REG_QVOQIDX_10, 0x5},
813 {OP_WR, QM_REG_QVOQIDX_11, 0x5},
814 {OP_WR, QM_REG_QVOQIDX_12, 0x5},
815 {OP_WR, QM_REG_WRRWEIGHTS_2, 0x20081001},
816 {OP_WR, QM_REG_QVOQIDX_13, 0x8},
817 {OP_WR, QM_REG_QVOQIDX_14, 0x6},
818 {OP_WR, QM_REG_QVOQIDX_15, 0x7},
819 {OP_WR, QM_REG_QVOQIDX_16, 0x0},
820 {OP_WR, QM_REG_WRRWEIGHTS_3, 0x1010120},
821 {OP_ZR, QM_REG_QVOQIDX_17, 0x4},
822 {OP_WR, QM_REG_WRRWEIGHTS_4, 0x1010101},
823 {OP_ZR, QM_REG_QVOQIDX_21, 0x4},
824 {OP_WR, QM_REG_WRRWEIGHTS_5, 0x1010101},
825 {OP_ZR, QM_REG_QVOQIDX_25, 0x4},
826 {OP_WR, QM_REG_WRRWEIGHTS_6, 0x1010101},
827 {OP_ZR, QM_REG_QVOQIDX_29, 0x3},
828 {OP_WR, QM_REG_QVOQIDX_32, 0x1},
829 {OP_WR, QM_REG_WRRWEIGHTS_7, 0x1010101},
830 {OP_WR, QM_REG_QVOQIDX_33, 0x1},
831 {OP_WR, QM_REG_QVOQIDX_34, 0x1},
832 {OP_WR, QM_REG_QVOQIDX_35, 0x1},
833 {OP_WR, QM_REG_QVOQIDX_36, 0x1},
834 {OP_WR, QM_REG_WRRWEIGHTS_8, 0x1010101},
835 {OP_WR, QM_REG_QVOQIDX_37, 0x1},
836 {OP_WR, QM_REG_QVOQIDX_38, 0x4},
837 {OP_WR, QM_REG_QVOQIDX_39, 0x4},
838 {OP_WR, QM_REG_QVOQIDX_40, 0x2},
839 {OP_WR, QM_REG_WRRWEIGHTS_9, 0x8012004},
840 {OP_WR, QM_REG_QVOQIDX_41, 0x5},
841 {OP_WR, QM_REG_QVOQIDX_42, 0x5},
842 {OP_WR, QM_REG_QVOQIDX_43, 0x5},
843 {OP_WR, QM_REG_QVOQIDX_44, 0x5},
844 {OP_WR, QM_REG_WRRWEIGHTS_10, 0x20081001},
845 {OP_WR, QM_REG_QVOQIDX_45, 0x8},
846 {OP_WR, QM_REG_QVOQIDX_46, 0x6},
847 {OP_WR, QM_REG_QVOQIDX_47, 0x7},
848 {OP_WR, QM_REG_QVOQIDX_48, 0x1},
849 {OP_WR, QM_REG_WRRWEIGHTS_11, 0x1010120},
850 {OP_WR, QM_REG_QVOQIDX_49, 0x1},
851 {OP_WR, QM_REG_QVOQIDX_50, 0x1},
852 {OP_WR, QM_REG_QVOQIDX_51, 0x1},
853 {OP_WR, QM_REG_QVOQIDX_52, 0x1},
854 {OP_WR, QM_REG_WRRWEIGHTS_12, 0x1010101},
855 {OP_WR, QM_REG_QVOQIDX_53, 0x1},
856 {OP_WR, QM_REG_QVOQIDX_54, 0x1},
857 {OP_WR, QM_REG_QVOQIDX_55, 0x1},
858 {OP_WR, QM_REG_QVOQIDX_56, 0x1},
859 {OP_WR, QM_REG_WRRWEIGHTS_13, 0x1010101},
860 {OP_WR, QM_REG_QVOQIDX_57, 0x1},
861 {OP_WR, QM_REG_QVOQIDX_58, 0x1},
862 {OP_WR, QM_REG_QVOQIDX_59, 0x1},
863 {OP_WR, QM_REG_QVOQIDX_60, 0x1},
864 {OP_WR, QM_REG_WRRWEIGHTS_14, 0x1010101},
865 {OP_WR, QM_REG_QVOQIDX_61, 0x1},
866 {OP_WR, QM_REG_QVOQIDX_62, 0x1},
867 {OP_WR, QM_REG_QVOQIDX_63, 0x1},
868 {OP_WR, QM_REG_WRRWEIGHTS_15, 0x1010101},
869 {OP_WR, QM_REG_VOQQMASK_0_LSB, 0xffff003f},
870 {OP_ZR, QM_REG_VOQQMASK_0_MSB, 0x2},
871 {OP_WR, QM_REG_VOQQMASK_1_MSB, 0xffff003f},
872 {OP_WR, QM_REG_VOQQMASK_2_LSB, 0x100},
873 {OP_WR, QM_REG_VOQQMASK_2_MSB, 0x100},
874 {OP_ZR, QM_REG_VOQQMASK_3_LSB, 0x2},
875 {OP_WR, QM_REG_VOQQMASK_4_LSB, 0xc0},
876 {OP_WR, QM_REG_VOQQMASK_4_MSB, 0xc0},
877 {OP_WR, QM_REG_VOQQMASK_5_LSB, 0x1e00},
878 {OP_WR, QM_REG_VOQQMASK_5_MSB, 0x1e00},
879 {OP_WR, QM_REG_VOQQMASK_6_LSB, 0x4000},
880 {OP_WR, QM_REG_VOQQMASK_6_MSB, 0x4000},
881 {OP_WR, QM_REG_VOQQMASK_7_LSB, 0x8000},
882 {OP_WR, QM_REG_VOQQMASK_7_MSB, 0x8000},
883 {OP_WR, QM_REG_VOQQMASK_8_LSB, 0x2000},
884 {OP_WR, QM_REG_VOQQMASK_8_MSB, 0x2000},
885 {OP_ZR, QM_REG_VOQQMASK_9_LSB, 0x7},
886 {OP_WR, QM_REG_VOQPORT_1, 0x1},
887 {OP_ZR, QM_REG_VOQPORT_2, 0xa},
888 {OP_WR, QM_REG_CMINTVOQMASK_0, 0xc08},
889 {OP_WR, QM_REG_CMINTVOQMASK_1, 0x40},
890 {OP_WR, QM_REG_CMINTVOQMASK_2, 0x100},
891 {OP_WR, QM_REG_CMINTVOQMASK_3, 0x20},
892 {OP_WR, QM_REG_CMINTVOQMASK_4, 0x17},
893 {OP_WR, QM_REG_CMINTVOQMASK_5, 0x80},
894 {OP_WR, QM_REG_CMINTVOQMASK_6, 0x200},
895 {OP_WR, QM_REG_CMINTVOQMASK_7, 0x0},
896 {OP_WR, QM_REG_HWAEMPTYMASK_LSB, 0xffff01ff},
897 {OP_WR, QM_REG_HWAEMPTYMASK_MSB, 0xffff01ff},
898 {OP_WR, QM_REG_ENBYPVOQMASK, 0x13},
899 {OP_WR, QM_REG_VOQCREDITAFULLTHR, 0x13f},
900 {OP_WR, QM_REG_VOQINITCREDIT_0, 0x140},
901 {OP_WR, QM_REG_VOQINITCREDIT_1, 0x140},
902 {OP_ZR, QM_REG_VOQINITCREDIT_2, 0x2},
903 {OP_WR, QM_REG_VOQINITCREDIT_4, 0xc0},
904 {OP_ZR, QM_REG_VOQINITCREDIT_5, 0x7},
905 {OP_WR, QM_REG_TASKCRDCOST_0, 0x48},
906 {OP_WR, QM_REG_TASKCRDCOST_1, 0x48},
907 {OP_ZR, QM_REG_TASKCRDCOST_2, 0x2},
908 {OP_WR, QM_REG_TASKCRDCOST_4, 0x48},
909 {OP_ZR, QM_REG_TASKCRDCOST_5, 0x7},
910 {OP_WR, QM_REG_BYTECRDINITVAL, 0x8000},
911 {OP_WR, QM_REG_BYTECRDCOST, 0x25e4},
912 {OP_WR, QM_REG_BYTECREDITAFULLTHR, 0x7fff},
913 {OP_WR, QM_REG_ENBYTECRD_LSB, 0x7},
914 {OP_WR, QM_REG_ENBYTECRD_MSB, 0x7},
915 {OP_WR, QM_REG_BYTECRDPORT_LSB, 0x0},
916 {OP_WR, QM_REG_BYTECRDPORT_MSB, 0xffffffff},
917 {OP_WR, QM_REG_FUNCNUMSEL_LSB, 0x0},
918 {OP_WR, QM_REG_FUNCNUMSEL_MSB, 0xffffffff},
919 {OP_WR, QM_REG_CMINTEN, 0xff},
920#define QM_COMMON_END 829
921#define PBF_COMMON_START 829
922 {OP_WR, PBF_REG_INIT, 0x1},
923 {OP_WR, PBF_REG_INIT_P4, 0x1},
924 {OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1},
925 {OP_WR, PBF_REG_IF_ENABLE_REG, 0x7fff},
926 {OP_WR, PBF_REG_INIT_P4, 0x0},
927 {OP_WR, PBF_REG_INIT, 0x0},
928 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0},
929#define PBF_COMMON_END 836
930#define PBF_PORT0_START 836
931 {OP_WR, PBF_REG_INIT_P0, 0x1},
932 {OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1},
933 {OP_WR, PBF_REG_INIT_P0, 0x0},
934 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0},
935#define PBF_PORT0_END 840
936#define PBF_PORT1_START 840
937 {OP_WR, PBF_REG_INIT_P1, 0x1},
938 {OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1},
939 {OP_WR, PBF_REG_INIT_P1, 0x0},
940 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0},
941#define PBF_PORT1_END 844
942#define XCM_COMMON_START 844
943 {OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32},
944 {OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020},
945 {OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020},
946 {OP_WR, XCM_REG_TM_XCM_HDR, 0x1000030},
947 {OP_WR, XCM_REG_ERR_XCM_HDR, 0x8100000},
948 {OP_WR, XCM_REG_ERR_EVNT_ID, 0x33},
949 {OP_WR, XCM_REG_EXPR_EVNT_ID, 0x30},
950 {OP_WR, XCM_REG_STOP_EVNT_ID, 0x31},
951 {OP_WR, XCM_REG_STORM_WEIGHT, 0x2},
952 {OP_WR, XCM_REG_TSEM_WEIGHT, 0x5},
953 {OP_WR, XCM_REG_CSEM_WEIGHT, 0x2},
954 {OP_WR, XCM_REG_USEM_WEIGHT, 0x2},
955 {OP_WR, XCM_REG_PBF_WEIGHT, 0x7},
956 {OP_WR, XCM_REG_NIG1_WEIGHT, 0x1},
957 {OP_WR, XCM_REG_CP_WEIGHT, 0x0},
958 {OP_WR, XCM_REG_XSDM_WEIGHT, 0x5},
959 {OP_WR, XCM_REG_XQM_P_WEIGHT, 0x3},
960 {OP_WR, XCM_REG_XCM_XQM_USE_Q, 0x1},
961 {OP_WR, XCM_REG_XQM_BYP_ACT_UPD, 0x6},
962 {OP_WR, XCM_REG_UNA_GT_NXT_Q, 0x0},
963 {OP_WR, XCM_REG_AUX1_Q, 0x2},
964 {OP_WR, XCM_REG_AUX_CNT_FLG_Q_19, 0x1},
965 {OP_WR, XCM_REG_GR_ARB_TYPE, 0x1},
966 {OP_WR, XCM_REG_GR_LD0_PR, 0x1},
967 {OP_WR, XCM_REG_GR_LD1_PR, 0x2},
968 {OP_WR, XCM_REG_CFC_INIT_CRD, 0x1},
969 {OP_WR, XCM_REG_FIC0_INIT_CRD, 0x40},
970 {OP_WR, XCM_REG_FIC1_INIT_CRD, 0x40},
971 {OP_WR, XCM_REG_TM_INIT_CRD, 0x4},
972 {OP_WR, XCM_REG_XQM_INIT_CRD, 0x20},
973 {OP_WR, XCM_REG_XX_INIT_CRD, 0x2},
974 {OP_WR, XCM_REG_XX_MSG_NUM, 0x1f},
975 {OP_ZR, XCM_REG_XX_TABLE, 0x12},
976 {OP_SW, XCM_REG_XX_DESCR_TABLE, 0x1f4d01},
977 {OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf},
978 {OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7},
979 {OP_WR, XCM_REG_N_SM_CTX_LD_2, 0xb},
980 {OP_WR, XCM_REG_N_SM_CTX_LD_3, 0xe},
981 {OP_ZR, XCM_REG_N_SM_CTX_LD_4, 0x4},
982 {OP_WR, XCM_REG_XCM_REG0_SZ, 0x4},
983 {OP_WR, XCM_REG_XCM_STORM0_IFEN, 0x1},
984 {OP_WR, XCM_REG_XCM_STORM1_IFEN, 0x1},
985 {OP_WR, XCM_REG_XCM_XQM_IFEN, 0x1},
986 {OP_WR, XCM_REG_STORM_XCM_IFEN, 0x1},
987 {OP_WR, XCM_REG_XQM_XCM_IFEN, 0x1},
988 {OP_WR, XCM_REG_XSDM_IFEN, 0x1},
989 {OP_WR, XCM_REG_TM_XCM_IFEN, 0x1},
990 {OP_WR, XCM_REG_XCM_TM_IFEN, 0x1},
991 {OP_WR, XCM_REG_TSEM_IFEN, 0x1},
992 {OP_WR, XCM_REG_CSEM_IFEN, 0x1},
993 {OP_WR, XCM_REG_USEM_IFEN, 0x1},
994 {OP_WR, XCM_REG_DORQ_IFEN, 0x1},
995 {OP_WR, XCM_REG_PBF_IFEN, 0x1},
996 {OP_WR, XCM_REG_NIG0_IFEN, 0x1},
997 {OP_WR, XCM_REG_NIG1_IFEN, 0x1},
998 {OP_WR, XCM_REG_CDU_AG_WR_IFEN, 0x1},
999 {OP_WR, XCM_REG_CDU_AG_RD_IFEN, 0x1},
1000 {OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1},
1001 {OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1},
1002 {OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1},
1003#define XCM_COMMON_END 904
1004#define XCM_PORT0_START 904
1005 {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1006 {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1007 {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
1008 {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
1009 {OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2},
1010 {OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2},
1011 {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1012 {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1013#define XCM_PORT0_END 912
1014#define XCM_PORT1_START 912
1015 {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1016 {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1017 {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
1018 {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
1019 {OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2},
1020 {OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2},
1021 {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1022 {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1023#define XCM_PORT1_END 920
1024#define XSEM_COMMON_START 920
1025 {OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0},
1026 {OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0},
1027 {OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0},
1028 {OP_RD, XSEM_REG_MSG_NUM_FOC1, 0x0},
1029 {OP_RD, XSEM_REG_MSG_NUM_FOC2, 0x0},
1030 {OP_RD, XSEM_REG_MSG_NUM_FOC3, 0x0},
1031 {OP_WR, XSEM_REG_ARB_ELEMENT0, 0x1},
1032 {OP_WR, XSEM_REG_ARB_ELEMENT1, 0x2},
1033 {OP_WR, XSEM_REG_ARB_ELEMENT2, 0x3},
1034 {OP_WR, XSEM_REG_ARB_ELEMENT3, 0x0},
1035 {OP_WR, XSEM_REG_ARB_ELEMENT4, 0x4},
1036 {OP_WR, XSEM_REG_ARB_CYCLE_SIZE, 0x1},
1037 {OP_WR, XSEM_REG_TS_0_AS, 0x0},
1038 {OP_WR, XSEM_REG_TS_1_AS, 0x1},
1039 {OP_WR, XSEM_REG_TS_2_AS, 0x4},
1040 {OP_WR, XSEM_REG_TS_3_AS, 0x0},
1041 {OP_WR, XSEM_REG_TS_4_AS, 0x1},
1042 {OP_WR, XSEM_REG_TS_5_AS, 0x3},
1043 {OP_WR, XSEM_REG_TS_6_AS, 0x0},
1044 {OP_WR, XSEM_REG_TS_7_AS, 0x1},
1045 {OP_WR, XSEM_REG_TS_8_AS, 0x4},
1046 {OP_WR, XSEM_REG_TS_9_AS, 0x0},
1047 {OP_WR, XSEM_REG_TS_10_AS, 0x1},
1048 {OP_WR, XSEM_REG_TS_11_AS, 0x3},
1049 {OP_WR, XSEM_REG_TS_12_AS, 0x0},
1050 {OP_WR, XSEM_REG_TS_13_AS, 0x1},
1051 {OP_WR, XSEM_REG_TS_14_AS, 0x4},
1052 {OP_WR, XSEM_REG_TS_15_AS, 0x0},
1053 {OP_WR, XSEM_REG_TS_16_AS, 0x4},
1054 {OP_WR, XSEM_REG_TS_17_AS, 0x3},
1055 {OP_ZR, XSEM_REG_TS_18_AS, 0x2},
1056 {OP_WR, XSEM_REG_ENABLE_IN, 0x3fff},
1057 {OP_WR, XSEM_REG_ENABLE_OUT, 0x3ff},
1058 {OP_WR, XSEM_REG_FIC0_DISABLE, 0x0},
1059 {OP_WR, XSEM_REG_FIC1_DISABLE, 0x0},
1060 {OP_WR, XSEM_REG_PAS_DISABLE, 0x0},
1061 {OP_WR, XSEM_REG_THREADS_LIST, 0xffff},
1062 {OP_ZR, XSEM_REG_PASSIVE_BUFFER, 0x800},
1063 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
1064 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18000, 0x0},
1065 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18040, 0x18},
1066 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18080, 0xc},
1067 {OP_WR, XSEM_REG_FAST_MEMORY + 0x180c0, 0x66},
1068 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
1069 {OP_WR, XSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
1070 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18340, 0x1f4},
1071 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
1072 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x55d8, 0x2},
1073 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5000, 0x48},
1074 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
1075 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1000, 0x2},
1076 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5128, 0x92},
1077 {OP_WR, XSEM_REG_FAST_MEMORY + 0x5378, 0x0},
1078 {OP_SW, XSEM_REG_FAST_MEMORY + 0x5380, 0x24d20},
1079 {OP_SW, XSEM_REG_FAST_MEMORY + 0x5428, 0x44d22},
1080 {OP_WR, XSEM_REG_FAST_MEMORY + 0x1518, 0x1},
1081 {OP_WR, XSEM_REG_FAST_MEMORY + 0x1830, 0x0},
1082 {OP_WR, XSEM_REG_FAST_MEMORY + 0x1838, 0x0},
1083 {OP_SW, XSEM_REG_FAST_MEMORY + 0x1820, 0x24d26},
1084 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4ac0, 0x2},
1085 {OP_SW, XSEM_REG_FAST_MEMORY + 0x4ad8, 0x24d28},
1086 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4b08, 0x4},
1087 {OP_SW, XSEM_REG_FAST_MEMORY + 0x1f50, 0x24d2a},
1088 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0},
1089 {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c00, 0x104d2c},
1090 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
1091 {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c40, 0x84d3c},
1092 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000},
1093 {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c60, 0x84d44},
1094 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x3000000},
1095 {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c80, 0x84d4c},
1096 {OP_ZP, XSEM_REG_INT_TABLE, 0x814d54},
1097 {OP_ZP, XSEM_REG_PRAM, 0x35774d75},
1098 {OP_ZP, XSEM_REG_PRAM + 0x8000, 0x36525ad3},
1099 {OP_ZP, XSEM_REG_PRAM + 0x10000, 0x27266868},
1100 {OP_ZP, XSEM_REG_PRAM + 0x18000, 0x5e7232},
1101 {OP_ZP, XSEM_REG_PRAM + 0x20000, 0x5e724a},
1102 {OP_ZP, XSEM_REG_PRAM + 0x28000, 0x5e7262},
1103 {OP_ZP, XSEM_REG_PRAM + 0x30000, 0x5e727a},
1104 {OP_ZP, XSEM_REG_PRAM + 0x38000, 0x5e7292},
1105#define XSEM_COMMON_END 1000
1106#define XSEM_PORT0_START 1000
1107 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1400, 0xa},
1108 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1450, 0x6},
1109 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5388, 0xc},
1110 {OP_SW, XSEM_REG_FAST_MEMORY + 0x5388 + 0x30, 0x272aa},
1111 {OP_SW, XSEM_REG_FAST_MEMORY + 0x55e0, 0x772ac},
1112 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5600, 0x7},
1113 {OP_WR, XSEM_REG_FAST_MEMORY + 0x1500, 0x0},
1114 {OP_WR, XSEM_REG_FAST_MEMORY + 0x1508, 0x1},
1115 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3020, 0x2},
1116 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3030, 0x2},
1117 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3000, 0x2},
1118 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3010, 0x2},
1119 {OP_WR, XSEM_REG_FAST_MEMORY + 0x3040, 0x0},
1120 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3048, 0xc},
1121 {OP_SW, XSEM_REG_FAST_MEMORY + 0x3048 + 0x30, 0x272b3},
1122 {OP_WR, XSEM_REG_FAST_MEMORY + 0x30b8, 0x1},
1123 {OP_SW, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x272b5},
1124 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4b18, 0x42},
1125 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4d28, 0x4},
1126#define XSEM_PORT0_END 1019
1127#define XSEM_PORT1_START 1019
1128 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1428, 0xa},
1129 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1468, 0x6},
1130 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x53c0, 0xc},
1131 {OP_SW, XSEM_REG_FAST_MEMORY + 0x53c0 + 0x30, 0x272b7},
1132 {OP_SW, XSEM_REG_FAST_MEMORY + 0x5620, 0x772b9},
1133 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5640, 0x7},
1134 {OP_WR, XSEM_REG_FAST_MEMORY + 0x1504, 0x0},
1135 {OP_WR, XSEM_REG_FAST_MEMORY + 0x150c, 0x1},
1136 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3028, 0x2},
1137 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3038, 0x2},
1138 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3008, 0x2},
1139 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3018, 0x2},
1140 {OP_WR, XSEM_REG_FAST_MEMORY + 0x3044, 0x0},
1141 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3080, 0xc},
1142 {OP_SW, XSEM_REG_FAST_MEMORY + 0x3080 + 0x30, 0x272c0},
1143 {OP_WR, XSEM_REG_FAST_MEMORY + 0x30bc, 0x1},
1144 {OP_SW, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x272c2},
1145 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4c20, 0x42},
1146 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4d38, 0x4},
1147#define XSEM_PORT1_END 1038
1148#define CDU_COMMON_START 1038
1149 {OP_WR, CDU_REG_CDU_CONTROL0, 0x1},
1150 {OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000},
1151 {OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d},
1152 {OP_WB, CDU_REG_L1TT, 0x20072c4},
1153 {OP_WB, CDU_REG_MATT, 0x2074c4},
1154 {OP_ZR, CDU_REG_MATT + 0x80, 0x20},
1155#define CDU_COMMON_END 1044
1156#define DMAE_COMMON_START 1044
1157 {OP_WR, DMAE_REG_CRC16C_INIT, 0x0},
1158 {OP_WR, DMAE_REG_CRC16T10_INIT, 0x1},
1159 {OP_WR, DMAE_REG_PXP_REQ_INIT_CRD, 0x2},
1160 {OP_WR, DMAE_REG_PCI_IFEN, 0x1},
1161 {OP_WR, DMAE_REG_GRC_IFEN, 0x1},
1162#define DMAE_COMMON_END 1049
1163#define PXP_COMMON_START 1049
1164 {OP_SI, PXP_REG_HST_INBOUND_INT + 0x400, 0x574e4},
1165 {OP_SI, PXP_REG_HST_INBOUND_INT + 0x420, 0x574e9},
1166 {OP_SI, PXP_REG_HST_INBOUND_INT, 0x574ee},
1167#define PXP_COMMON_END 1052
1168#define CFC_COMMON_START 1052
1169 {OP_WR, CFC_REG_CONTROL0, 0x10},
1170 {OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff},
1171 {OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a},
1172#define CFC_COMMON_END 1055
1173#define HC_COMMON_START 1055
1174 {OP_ZR, HC_REG_USTORM_ADDR_FOR_COALESCE, 0x4},
1175#define HC_COMMON_END 1056
1176#define HC_PORT0_START 1056
1177 {OP_WR, HC_REG_CONFIG_0, 0x1080},
1178 {OP_ZR, HC_REG_UC_RAM_ADDR_0, 0x2},
1179 {OP_WR, HC_REG_ATTN_NUM_P0, 0x10},
1180 {OP_WR, HC_REG_LEADING_EDGE_0, 0xffff},
1181 {OP_WR, HC_REG_TRAILING_EDGE_0, 0xffff},
1182 {OP_WR, HC_REG_AGG_INT_0, 0x0},
1183 {OP_WR, HC_REG_ATTN_IDX, 0x0},
1184 {OP_ZR, HC_REG_ATTN_BIT, 0x2},
1185 {OP_WR, HC_REG_VQID_0, 0x2b5},
1186 {OP_WR, HC_REG_PCI_CONFIG_0, 0x0},
1187 {OP_ZR, HC_REG_P0_PROD_CONS, 0x4a},
1188 {OP_ZR, HC_REG_PBA_COMMAND, 0x2},
1189 {OP_WR, HC_REG_INT_MASK, 0x1ffff},
1190 {OP_WR, HC_REG_CONFIG_0, 0x1a82},
1191 {OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24},
1192 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
1193 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
1194 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
1195#define HC_PORT0_END 1074
1196#define HC_PORT1_START 1074
1197 {OP_WR, HC_REG_CONFIG_1, 0x1080},
1198 {OP_ZR, HC_REG_UC_RAM_ADDR_1, 0x2},
1199 {OP_WR, HC_REG_ATTN_NUM_P1, 0x10},
1200 {OP_WR, HC_REG_LEADING_EDGE_1, 0xffff},
1201 {OP_WR, HC_REG_TRAILING_EDGE_1, 0xffff},
1202 {OP_WR, HC_REG_AGG_INT_1, 0x0},
1203 {OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0},
1204 {OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2},
1205 {OP_WR, HC_REG_VQID_1, 0x2b5},
1206 {OP_WR, HC_REG_PCI_CONFIG_1, 0x0},
1207 {OP_ZR, HC_REG_P1_PROD_CONS, 0x4a},
1208 {OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2},
1209 {OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff},
1210 {OP_WR, HC_REG_CONFIG_1, 0x1a82},
1211 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
1212 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
1213 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
1214 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
1215#define HC_PORT1_END 1092
1216#define PXP2_COMMON_START 1092
1217 {OP_WR, PXP2_REG_PGL_CONTROL0, 0xe38324},
1218 {OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10},
1219 {OP_WR, PXP2_REG_PGL_INT_TSDM_0, 0xffffffff},
1220 {OP_WR, PXP2_REG_PGL_INT_TSDM_1, 0xffffffff},
1221 {OP_WR, PXP2_REG_PGL_INT_TSDM_2, 0xffffffff},
1222 {OP_WR, PXP2_REG_PGL_INT_TSDM_3, 0xffffffff},
1223 {OP_WR, PXP2_REG_PGL_INT_TSDM_4, 0xffffffff},
1224 {OP_WR, PXP2_REG_PGL_INT_TSDM_5, 0xffffffff},
1225 {OP_WR, PXP2_REG_PGL_INT_TSDM_6, 0xffffffff},
1226 {OP_WR, PXP2_REG_PGL_INT_TSDM_7, 0xffffffff},
1227 {OP_WR, PXP2_REG_PGL_INT_USDM_1, 0xffffffff},
1228 {OP_WR, PXP2_REG_PGL_INT_USDM_2, 0xffffffff},
1229 {OP_WR, PXP2_REG_PGL_INT_USDM_3, 0xffffffff},
1230 {OP_WR, PXP2_REG_PGL_INT_USDM_4, 0xffffffff},
1231 {OP_WR, PXP2_REG_PGL_INT_USDM_5, 0xffffffff},
1232 {OP_WR, PXP2_REG_PGL_INT_USDM_6, 0xffffffff},
1233 {OP_WR, PXP2_REG_PGL_INT_USDM_7, 0xffffffff},
1234 {OP_WR, PXP2_REG_PGL_INT_XSDM_2, 0xffffffff},
1235 {OP_WR, PXP2_REG_PGL_INT_XSDM_3, 0xffffffff},
1236 {OP_WR, PXP2_REG_PGL_INT_XSDM_4, 0xffffffff},
1237 {OP_WR, PXP2_REG_PGL_INT_XSDM_5, 0xffffffff},
1238 {OP_WR, PXP2_REG_PGL_INT_XSDM_6, 0xffffffff},
1239 {OP_WR, PXP2_REG_PGL_INT_XSDM_7, 0xffffffff},
1240 {OP_WR, PXP2_REG_PGL_INT_CSDM_0, 0xffffffff},
1241 {OP_WR, PXP2_REG_PGL_INT_CSDM_1, 0xffffffff},
1242 {OP_WR, PXP2_REG_PGL_INT_CSDM_2, 0xffffffff},
1243 {OP_WR, PXP2_REG_PGL_INT_CSDM_3, 0xffffffff},
1244 {OP_WR, PXP2_REG_PGL_INT_CSDM_4, 0xffffffff},
1245 {OP_WR, PXP2_REG_PGL_INT_CSDM_5, 0xffffffff},
1246 {OP_WR, PXP2_REG_PGL_INT_CSDM_6, 0xffffffff},
1247 {OP_WR, PXP2_REG_PGL_INT_CSDM_7, 0xffffffff},
1248 {OP_WR, PXP2_REG_PGL_INT_XSDM_0, 0xffff5330},
1249 {OP_WR, PXP2_REG_PGL_INT_XSDM_1, 0xffff5348},
1250 {OP_WR, PXP2_REG_PGL_INT_USDM_0, 0xf0003000},
1251 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ6, 0x8},
1252 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ9, 0x8},
1253 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ10, 0x8},
1254 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ11, 0x2},
1255 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ17, 0x4},
1256 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ18, 0x5},
1257 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ19, 0x4},
1258 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ22, 0x0},
1259 {OP_WR, PXP2_REG_RD_START_INIT, 0x1},
1260 {OP_WR, PXP2_REG_RQ_BW_RD_ADD0, 0x40},
1261 {OP_WR, PXP2_REG_PSWRQ_BW_ADD1, 0x1808},
1262 {OP_WR, PXP2_REG_PSWRQ_BW_ADD2, 0x803},
1263 {OP_WR, PXP2_REG_PSWRQ_BW_ADD3, 0x803},
1264 {OP_WR, PXP2_REG_RQ_BW_RD_ADD4, 0x40},
1265 {OP_WR, PXP2_REG_RQ_BW_RD_ADD5, 0x3},
1266 {OP_WR, PXP2_REG_PSWRQ_BW_ADD6, 0x803},
1267 {OP_WR, PXP2_REG_PSWRQ_BW_ADD7, 0x803},
1268 {OP_WR, PXP2_REG_PSWRQ_BW_ADD8, 0x803},
1269 {OP_WR, PXP2_REG_PSWRQ_BW_ADD9, 0x10003},
1270 {OP_WR, PXP2_REG_PSWRQ_BW_ADD10, 0x803},
1271 {OP_WR, PXP2_REG_PSWRQ_BW_ADD11, 0x803},
1272 {OP_WR, PXP2_REG_RQ_BW_RD_ADD12, 0x3},
1273 {OP_WR, PXP2_REG_RQ_BW_RD_ADD13, 0x3},
1274 {OP_WR, PXP2_REG_RQ_BW_RD_ADD14, 0x3},
1275 {OP_WR, PXP2_REG_RQ_BW_RD_ADD15, 0x3},
1276 {OP_WR, PXP2_REG_RQ_BW_RD_ADD16, 0x3},
1277 {OP_WR, PXP2_REG_RQ_BW_RD_ADD17, 0x3},
1278 {OP_WR, PXP2_REG_RQ_BW_RD_ADD18, 0x3},
1279 {OP_WR, PXP2_REG_RQ_BW_RD_ADD19, 0x3},
1280 {OP_WR, PXP2_REG_RQ_BW_RD_ADD20, 0x3},
1281 {OP_WR, PXP2_REG_RQ_BW_RD_ADD22, 0x3},
1282 {OP_WR, PXP2_REG_RQ_BW_RD_ADD23, 0x3},
1283 {OP_WR, PXP2_REG_RQ_BW_RD_ADD24, 0x3},
1284 {OP_WR, PXP2_REG_RQ_BW_RD_ADD25, 0x3},
1285 {OP_WR, PXP2_REG_RQ_BW_RD_ADD26, 0x3},
1286 {OP_WR, PXP2_REG_RQ_BW_RD_ADD27, 0x3},
1287 {OP_WR, PXP2_REG_PSWRQ_BW_ADD28, 0x2403},
1288 {OP_WR, PXP2_REG_RQ_BW_WR_ADD29, 0x2f},
1289 {OP_WR, PXP2_REG_RQ_BW_WR_ADD30, 0x9},
1290 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND0, 0x19},
1291 {OP_WR, PXP2_REG_PSWRQ_BW_UB1, 0x184},
1292 {OP_WR, PXP2_REG_PSWRQ_BW_UB2, 0x183},
1293 {OP_WR, PXP2_REG_PSWRQ_BW_UB3, 0x306},
1294 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND4, 0x19},
1295 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND5, 0x6},
1296 {OP_WR, PXP2_REG_PSWRQ_BW_UB6, 0x306},
1297 {OP_WR, PXP2_REG_PSWRQ_BW_UB7, 0x306},
1298 {OP_WR, PXP2_REG_PSWRQ_BW_UB8, 0x306},
1299 {OP_WR, PXP2_REG_PSWRQ_BW_UB9, 0xc86},
1300 {OP_WR, PXP2_REG_PSWRQ_BW_UB10, 0x306},
1301 {OP_WR, PXP2_REG_PSWRQ_BW_UB11, 0x306},
1302 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND12, 0x6},
1303 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND13, 0x6},
1304 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND14, 0x6},
1305 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND15, 0x6},
1306 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND16, 0x6},
1307 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND17, 0x6},
1308 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND18, 0x6},
1309 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND19, 0x6},
1310 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND20, 0x6},
1311 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND22, 0x6},
1312 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND23, 0x6},
1313 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND24, 0x6},
1314 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND25, 0x6},
1315 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND26, 0x6},
1316 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND27, 0x6},
1317 {OP_WR, PXP2_REG_PSWRQ_BW_UB28, 0x306},
1318 {OP_WR, PXP2_REG_RQ_BW_WR_UBOUND29, 0x13},
1319 {OP_WR, PXP2_REG_RQ_BW_WR_UBOUND30, 0x6},
1320 {OP_WR, PXP2_REG_PSWRQ_BW_L1, 0x1004},
1321 {OP_WR, PXP2_REG_PSWRQ_BW_L2, 0x1004},
1322 {OP_WR, PXP2_REG_PSWRQ_BW_RD, 0x106440},
1323 {OP_WR, PXP2_REG_PSWRQ_BW_WR, 0x106440},
1324 {OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1},
1325#define PXP2_COMMON_END 1200
1326#define MISC_AEU_COMMON_START 1200
1327 {OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16},
1328#define MISC_AEU_COMMON_END 1201
1329#define MISC_AEU_PORT0_START 1201
1330 {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xbf5c0000},
1331 {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff51fef},
1332 {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0, 0xffff},
1333 {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 0x500003e0},
1334 {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1, 0x0},
1335 {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1, 0xa000},
1336 {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1, 0x5},
1337 {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2, 0xfe00000},
1338 {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3, 0x14},
1339 {OP_WR, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000},
1340 {OP_WR, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555},
1341 {OP_WR, MISC_REG_AEU_ENABLE3_NIG_0, 0x5555},
1342 {OP_WR, MISC_REG_AEU_ENABLE4_NIG_0, 0x0},
1343 {OP_WR, MISC_REG_AEU_ENABLE1_PXP_0, 0x55540000},
1344 {OP_WR, MISC_REG_AEU_ENABLE2_PXP_0, 0x55555555},
1345 {OP_WR, MISC_REG_AEU_ENABLE3_PXP_0, 0x5555},
1346 {OP_WR, MISC_REG_AEU_ENABLE4_PXP_0, 0x0},
1347 {OP_WR, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x0},
1348 {OP_ZR, MISC_REG_AEU_INVERTER_2_FUNC_0, 0x3},
1349 {OP_WR, MISC_REG_AEU_MASK_ATTN_FUNC_0, 0x7},
1350#define MISC_AEU_PORT0_END 1221
1351#define MISC_AEU_PORT1_START 1221
1352 {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xbf5c0000},
1353 {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff51fef},
1354 {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0, 0xffff},
1355 {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 0x500003e0},
1356 {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1, 0x0},
1357 {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1, 0xa000},
1358 {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1, 0x5},
1359 {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2, 0xfe00000},
1360 {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3, 0x14},
1361 {OP_WR, MISC_REG_AEU_ENABLE1_NIG_1, 0x55540000},
1362 {OP_WR, MISC_REG_AEU_ENABLE2_NIG_1, 0x55555555},
1363 {OP_WR, MISC_REG_AEU_ENABLE3_NIG_1, 0x5555},
1364 {OP_WR, MISC_REG_AEU_ENABLE4_NIG_1, 0x0},
1365 {OP_WR, MISC_REG_AEU_ENABLE1_PXP_1, 0x55540000},
1366 {OP_WR, MISC_REG_AEU_ENABLE2_PXP_1, 0x55555555},
1367 {OP_WR, MISC_REG_AEU_ENABLE3_PXP_1, 0x5555},
1368 {OP_WR, MISC_REG_AEU_ENABLE4_PXP_1, 0x0},
1369 {OP_WR, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x0},
1370 {OP_ZR, MISC_REG_AEU_INVERTER_2_FUNC_1, 0x3},
1371 {OP_WR, MISC_REG_AEU_MASK_ATTN_FUNC_1, 0x7}
1372#define MISC_AEU_PORT1_END 1241
1373};
1374
1375static const u32 init_data[] = {
1376 0x00010000, 0x000204c0, 0x00030980, 0x00040e40, 0x00051300, 0x000617c0,
1377 0x00071c80, 0x00082140, 0x00092600, 0x000a2ac0, 0x000b2f80, 0x000c3440,
1378 0x000d3900, 0x000e3dc0, 0x000f4280, 0x00104740, 0x00114c00, 0x001250c0,
1379 0x00135580, 0x00145a40, 0x00155f00, 0x001663c0, 0x00176880, 0x00186d40,
1380 0x00197200, 0x001a76c0, 0x001b7b80, 0x001c8040, 0x001d8500, 0x001e89c0,
1381 0x001f8e80, 0x00209340, 0x00002000, 0x00004000, 0x00006000, 0x00008000,
1382 0x0000a000, 0x0000c000, 0x0000e000, 0x00010000, 0x00012000, 0x00014000,
1383 0x00016000, 0x00018000, 0x0001a000, 0x0001c000, 0x0001e000, 0x00020000,
1384 0x00022000, 0x00024000, 0x00026000, 0x00028000, 0x0002a000, 0x0002c000,
1385 0x0002e000, 0x00030000, 0x00032000, 0x00034000, 0x00036000, 0x00038000,
1386 0x0003a000, 0x0003c000, 0x0003e000, 0x00040000, 0x00042000, 0x00044000,
1387 0x00046000, 0x00048000, 0x0004a000, 0x0004c000, 0x0004e000, 0x00050000,
1388 0x00052000, 0x00054000, 0x00056000, 0x00058000, 0x0005a000, 0x0005c000,
1389 0x0005e000, 0x00060000, 0x00062000, 0x00064000, 0x00066000, 0x00068000,
1390 0x0006a000, 0x0006c000, 0x0006e000, 0x00070000, 0x00072000, 0x00074000,
1391 0x00076000, 0x00078000, 0x0007a000, 0x0007c000, 0x0007e000, 0x00080000,
1392 0x00082000, 0x00084000, 0x00086000, 0x00088000, 0x0008a000, 0x0008c000,
1393 0x0008e000, 0x00090000, 0x00092000, 0x00094000, 0x00096000, 0x00098000,
1394 0x0009a000, 0x0009c000, 0x0009e000, 0x000a0000, 0x000a2000, 0x000a4000,
1395 0x000a6000, 0x000a8000, 0x000aa000, 0x000ac000, 0x000ae000, 0x000b0000,
1396 0x000b2000, 0x000b4000, 0x000b6000, 0x000b8000, 0x000ba000, 0x000bc000,
1397 0x000be000, 0x000c0000, 0x000c2000, 0x000c4000, 0x000c6000, 0x000c8000,
1398 0x000ca000, 0x000cc000, 0x000ce000, 0x000d0000, 0x000d2000, 0x000d4000,
1399 0x000d6000, 0x000d8000, 0x000da000, 0x000dc000, 0x000de000, 0x000e0000,
1400 0x000e2000, 0x000e4000, 0x000e6000, 0x000e8000, 0x000ea000, 0x000ec000,
1401 0x000ee000, 0x000f0000, 0x000f2000, 0x000f4000, 0x000f6000, 0x000f8000,
1402 0x000fa000, 0x000fc000, 0x000fe000, 0x00100000, 0x00102000, 0x00104000,
1403 0x00106000, 0x00108000, 0x0010a000, 0x0010c000, 0x0010e000, 0x00110000,
1404 0x00112000, 0x00114000, 0x00116000, 0x00118000, 0x0011a000, 0x0011c000,
1405 0x0011e000, 0x00120000, 0x00122000, 0x00124000, 0x00126000, 0x00128000,
1406 0x0012a000, 0x0012c000, 0x0012e000, 0x00130000, 0x00132000, 0x00134000,
1407 0x00136000, 0x00138000, 0x0013a000, 0x0013c000, 0x0013e000, 0x00140000,
1408 0x00142000, 0x00144000, 0x00146000, 0x00148000, 0x0014a000, 0x0014c000,
1409 0x0014e000, 0x00150000, 0x00152000, 0x00154000, 0x00156000, 0x00158000,
1410 0x0015a000, 0x0015c000, 0x0015e000, 0x00160000, 0x00162000, 0x00164000,
1411 0x00166000, 0x00168000, 0x0016a000, 0x0016c000, 0x0016e000, 0x00170000,
1412 0x00172000, 0x00174000, 0x00176000, 0x00178000, 0x0017a000, 0x0017c000,
1413 0x0017e000, 0x00180000, 0x00182000, 0x00184000, 0x00186000, 0x00188000,
1414 0x0018a000, 0x0018c000, 0x0018e000, 0x00190000, 0x00192000, 0x00194000,
1415 0x00196000, 0x00198000, 0x0019a000, 0x0019c000, 0x0019e000, 0x001a0000,
1416 0x001a2000, 0x001a4000, 0x001a6000, 0x001a8000, 0x001aa000, 0x001ac000,
1417 0x001ae000, 0x001b0000, 0x001b2000, 0x001b4000, 0x001b6000, 0x001b8000,
1418 0x001ba000, 0x001bc000, 0x001be000, 0x001c0000, 0x001c2000, 0x001c4000,
1419 0x001c6000, 0x001c8000, 0x001ca000, 0x001cc000, 0x001ce000, 0x001d0000,
1420 0x001d2000, 0x001d4000, 0x001d6000, 0x001d8000, 0x001da000, 0x001dc000,
1421 0x001de000, 0x001e0000, 0x001e2000, 0x001e4000, 0x001e6000, 0x001e8000,
1422 0x001ea000, 0x001ec000, 0x001ee000, 0x001f0000, 0x001f2000, 0x001f4000,
1423 0x001f6000, 0x001f8000, 0x001fa000, 0x001fc000, 0x001fe000, 0x00200000,
1424 0x00202000, 0x00204000, 0x00206000, 0x00208000, 0x0020a000, 0x0020c000,
1425 0x0020e000, 0x00210000, 0x00212000, 0x00214000, 0x00216000, 0x00218000,
1426 0x0021a000, 0x0021c000, 0x0021e000, 0x00220000, 0x00222000, 0x00224000,
1427 0x00226000, 0x00228000, 0x0022a000, 0x0022c000, 0x0022e000, 0x00230000,
1428 0x00232000, 0x00234000, 0x00236000, 0x00238000, 0x0023a000, 0x0023c000,
1429 0x0023e000, 0x00240000, 0x00242000, 0x00244000, 0x00246000, 0x00248000,
1430 0x0024a000, 0x0024c000, 0x0024e000, 0x00250000, 0x00252000, 0x00254000,
1431 0x00256000, 0x00258000, 0x0025a000, 0x0025c000, 0x0025e000, 0x00260000,
1432 0x00262000, 0x00264000, 0x00266000, 0x00268000, 0x0026a000, 0x0026c000,
1433 0x0026e000, 0x00270000, 0x00272000, 0x00274000, 0x00276000, 0x00278000,
1434 0x0027a000, 0x0027c000, 0x0027e000, 0x00280000, 0x00282000, 0x00284000,
1435 0x00286000, 0x00288000, 0x0028a000, 0x0028c000, 0x0028e000, 0x00290000,
1436 0x00292000, 0x00294000, 0x00296000, 0x00298000, 0x0029a000, 0x0029c000,
1437 0x0029e000, 0x002a0000, 0x002a2000, 0x002a4000, 0x002a6000, 0x002a8000,
1438 0x002aa000, 0x002ac000, 0x002ae000, 0x002b0000, 0x002b2000, 0x002b4000,
1439 0x002b6000, 0x002b8000, 0x002ba000, 0x002bc000, 0x002be000, 0x002c0000,
1440 0x002c2000, 0x002c4000, 0x002c6000, 0x002c8000, 0x002ca000, 0x002cc000,
1441 0x002ce000, 0x002d0000, 0x002d2000, 0x002d4000, 0x002d6000, 0x002d8000,
1442 0x002da000, 0x002dc000, 0x002de000, 0x002e0000, 0x002e2000, 0x002e4000,
1443 0x002e6000, 0x002e8000, 0x002ea000, 0x002ec000, 0x002ee000, 0x002f0000,
1444 0x002f2000, 0x002f4000, 0x002f6000, 0x002f8000, 0x002fa000, 0x002fc000,
1445 0x002fe000, 0x00300000, 0x00302000, 0x00304000, 0x00306000, 0x00308000,
1446 0x0030a000, 0x0030c000, 0x0030e000, 0x00310000, 0x00312000, 0x00314000,
1447 0x00316000, 0x00318000, 0x0031a000, 0x0031c000, 0x0031e000, 0x00320000,
1448 0x00322000, 0x00324000, 0x00326000, 0x00328000, 0x0032a000, 0x0032c000,
1449 0x0032e000, 0x00330000, 0x00332000, 0x00334000, 0x00336000, 0x00338000,
1450 0x0033a000, 0x0033c000, 0x0033e000, 0x00340000, 0x00342000, 0x00344000,
1451 0x00346000, 0x00348000, 0x0034a000, 0x0034c000, 0x0034e000, 0x00350000,
1452 0x00352000, 0x00354000, 0x00356000, 0x00358000, 0x0035a000, 0x0035c000,
1453 0x0035e000, 0x00360000, 0x00362000, 0x00364000, 0x00366000, 0x00368000,
1454 0x0036a000, 0x0036c000, 0x0036e000, 0x00370000, 0x00372000, 0x00374000,
1455 0x00376000, 0x00378000, 0x0037a000, 0x0037c000, 0x0037e000, 0x00380000,
1456 0x00382000, 0x00384000, 0x00386000, 0x00388000, 0x0038a000, 0x0038c000,
1457 0x0038e000, 0x00390000, 0x00392000, 0x00394000, 0x00396000, 0x00398000,
1458 0x0039a000, 0x0039c000, 0x0039e000, 0x003a0000, 0x003a2000, 0x003a4000,
1459 0x003a6000, 0x003a8000, 0x003aa000, 0x003ac000, 0x003ae000, 0x003b0000,
1460 0x003b2000, 0x003b4000, 0x003b6000, 0x003b8000, 0x003ba000, 0x003bc000,
1461 0x003be000, 0x003c0000, 0x003c2000, 0x003c4000, 0x003c6000, 0x003c8000,
1462 0x003ca000, 0x003cc000, 0x003ce000, 0x003d0000, 0x003d2000, 0x003d4000,
1463 0x003d6000, 0x003d8000, 0x003da000, 0x003dc000, 0x003de000, 0x003e0000,
1464 0x003e2000, 0x003e4000, 0x003e6000, 0x003e8000, 0x003ea000, 0x003ec000,
1465 0x003ee000, 0x003f0000, 0x003f2000, 0x003f4000, 0x003f6000, 0x003f8000,
1466 0x003fa000, 0x003fc000, 0x003fe000, 0x003fe001, 0x00000000, 0x000001ff,
1467 0x00000200, 0x00000001, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
1468 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00088b1f, 0x00000000,
1469 0x51fbff00, 0x03f0c0cf, 0x3130ef8a, 0x22b1c430, 0x3b0143f8, 0x02ecdd01,
1470 0xdc406ec4, 0x19b7c404, 0x23dfd348, 0xf1476080, 0x03343031, 0x032f3731,
1471 0x423f2483, 0x4d5011fc, 0x02ef9025, 0xa40cdb15, 0x77280475, 0xf2c060fb,
1472 0x77629812, 0x056c1144, 0x58c8f22c, 0x4dde4d11, 0x44af950c, 0xe340ff40,
1473 0xfca8b235, 0x6d081948, 0x8b5f150b, 0x95051f26, 0xd0849577, 0xe76964eb,
1474 0x00607a36, 0x2726b9d6, 0x00000400, 0x00088b1f, 0x00000000, 0x7dedff00,
1475 0xd554780b, 0x333ef0b5, 0x64ccce67, 0x093c991e, 0x20f264af, 0xf09c0682,
1476 0x93a8a808, 0x07be3040, 0x0e22a5e4, 0x27902018, 0xf5e8bd48, 0x620c19bf,
1477 0x2f06d6b4, 0x93a45a2a, 0xb6968a80, 0x6c1a06c1, 0x822203b4, 0x6b06f5bf,
1478 0x368b6d7b, 0x2062a28a, 0xa5ebd8b9, 0xaffadaf7, 0x99def6b5, 0x91332673,
1479 0xfebffdaa, 0x5fa7f7df, 0xf7b3ecdd, 0xf5ed7bd9, 0xb3ef6b5e, 0xa66e6547,
1480 0x97d8ce5d, 0x9be507f8, 0x232c630a, 0xa1bbd65a, 0xed58cc9c, 0x9ef8731e,
1481 0xec66c65c, 0x4f2e44b1, 0x12ab7a87, 0xf4dd42b6, 0x4fda9d92, 0x7af5e56f,
1482 0x9743f773, 0xb9fb3b40, 0x05053d99, 0x589bb1eb, 0x6c276309, 0xf2f5ff8c,
1483 0xaf3b72fa, 0x5feeb6d6, 0x557fa0cc, 0xe1d995a7, 0x661d13fd, 0x3cd7d63f,
1484 0xc01984a5, 0x3eefbb50, 0xbf8c046d, 0xdbb4ac22, 0x0a7f50bd, 0xcafb421e,
1485 0xfb18730e, 0x33bbb9f7, 0x4ec64e03, 0x5798da36, 0x937ef843, 0xd8c453d9,
1486 0x59eef0aa, 0xaadfa023, 0x04cf8a5d, 0xaadaacf3, 0x8c9f2e44, 0x19b095cf,
1487 0xe9dea886, 0x1cb1de60, 0xcd192f86, 0xf358eb4b, 0xe30bcc24, 0x0b45b532,
1488 0x4dbe70b8, 0xc515d79a, 0x0f46c9cf, 0xb5eb23cd, 0xf03cc2cf, 0x144fdd5e,
1489 0xceb12e1f, 0x30ed82c4, 0xf67de9ff, 0xb89ddb85, 0xa15af5be, 0x258ebf4b,
1490 0xab1d717b, 0x2cdaadc2, 0xaad5c227, 0x8e8a2f2d, 0xcd33bd57, 0xfc96d708,
1491 0x7b5d4161, 0x91b2796c, 0xb4616f31, 0x7f318abe, 0x0fe113bb, 0x47c7b36b,
1492 0x29641f9f, 0x9deacf44, 0x45b5e666, 0x442c67c7, 0x17cccdcf, 0x2eb2bc41,
1493 0xb74f4f97, 0xdd231e33, 0x7788a4d6, 0x7df3c013, 0x024d8741, 0xf843df4f,
1494 0x7bf64ca0, 0xfeb0abd6, 0xa3cc99e4, 0x26fef10c, 0x1ed85b0b, 0x900bbd67,
1495 0x1630a619, 0xb7822664, 0xc26f058e, 0x50d4cfb2, 0x5fc3c005, 0xeb002b24,
1496 0xefe14fbd, 0xd4bccf5f, 0x9ad1beff, 0xe9bae91f, 0xe6ed92ca, 0x7496b15c,
1497 0xfa7f2fac, 0xb5321801, 0xbf10cfc2, 0x88ade22a, 0x43321e16, 0xca576bbb,
1498 0x7abc07c4, 0xc72d95fc, 0x4d93dcf9, 0xa678fa06, 0xa9ea1927, 0xf0635333,
1499 0xb89cf4eb, 0x4e01d440, 0x827fa9ab, 0x6958cf9a, 0xedf88db6, 0xe48d6c8e,
1500 0x38cb8ee6, 0x3b64775c, 0x7fa821c3, 0x08b85f17, 0x42f05aea, 0xc07c1c4f,
1501 0x859626cc, 0xa6c4d065, 0x466f6e0d, 0x941f023c, 0xf8517ce5, 0xa6f5941e,
1502 0x2814c2fe, 0x21a52b57, 0xc446cbc4, 0x330e9423, 0x3b75c06b, 0xd4f08cac,
1503 0x7b64a63c, 0xfba78748, 0xb94f0173, 0xb7ef71d1, 0x1f316434, 0xca840f63,
1504 0xc070ea43, 0xf7102e6f, 0x3cb78462, 0xf7802a12, 0x42c8ef73, 0x9034da7c,
1505 0x1afcfd03, 0xf3445fcc, 0x1f1e20b7, 0x9d8c7415, 0xcd3856df, 0xaf3dbf30,
1506 0x5dbf30ca, 0x2781f983, 0x2b5d089f, 0x8e3c07e6, 0xec07ec60, 0x96df9a5a,
1507 0x6fe68eb7, 0x619558d6, 0xf981a4fe, 0xd3ef38c3, 0x2e6fe609, 0xfeb8d8bc,
1508 0xf5c655bc, 0xcffd7c6b, 0xf989e685, 0x3ffd6893, 0xfaf8f362, 0xebe2eef3,
1509 0xfab8c2b7, 0xf803ddf9, 0xefbc476f, 0xdb7f804d, 0xeb8dd379, 0xae31afcf,
1510 0x7fe7cadf, 0x988b7421, 0xfff349df, 0xd7c2dd82, 0xcd377f9f, 0xf836b56f,
1511 0xcd64d03c, 0x23086a49, 0x7fe17b5f, 0x802ca0c3, 0x5942a679, 0xbc18ca94,
1512 0x47961dff, 0x2923b878, 0xfff61e78, 0xcdf8093c, 0x2c0bd519, 0xb94151bc,
1513 0x5d3c13af, 0xf6896bb9, 0xb2a5783d, 0x064beb93, 0xc00c74fa, 0xb3f3ba77,
1514 0xf000ffcf, 0xf628ee56, 0x8f24bd99, 0x265bdf0c, 0xe66f5296, 0x902c60f8,
1515 0xfa85db3d, 0x673d9029, 0x59f9353c, 0x4645e826, 0xe3e20e30, 0x13962d65,
1516 0x5af93a3d, 0x5f58c5b1, 0x25d63619, 0x24c8a5dc, 0xd8ca8650, 0xf79806d8,
1517 0x0623e804, 0xd07df27a, 0x647e5847, 0xdda2b761, 0x15f400f8, 0xb572f4d3,
1518 0x4272e89e, 0xb13ff8e5, 0xf8f241c5, 0x1ad5a6f9, 0x1c7847cb, 0x7cdd6480,
1519 0x1156f621, 0x58be73ac, 0x04b9e127, 0xcf5f15f5, 0x6bdaaefc, 0xdc02c4c0,
1520 0x4ef78669, 0xd416225b, 0xf0b0b75b, 0xfe3059bd, 0xb6ee0f6d, 0xf8ff4904,
1521 0xae489a47, 0xc81348d9, 0x968582f5, 0xef747bf7, 0x64d8ec2d, 0x8de50919,
1522 0x9bf3e341, 0xd3f58cab, 0x84c5b096, 0xc2a57976, 0x5bfc615a, 0x72ed8c1a,
1523 0x54b13f9e, 0xdf31674e, 0xf0c5a07c, 0x06575c54, 0xe1e82fd1, 0x3ebb00eb,
1524 0x87da246b, 0x53df14db, 0xfb05bf50, 0x1e3a444d, 0xe2f9f0d6, 0x07be2965,
1525 0x997860d8, 0xdf40930a, 0x78dd8577, 0x743cb557, 0xfe183291, 0x7e1c979e,
1526 0xebc184d3, 0x56fb8588, 0xdc3a21e6, 0x7cf8ceba, 0x7d762849, 0x3bea0f9c,
1527 0xd03ed34b, 0xbf6daf3d, 0x1d03ed32, 0x9cef54bf, 0x0cafa86d, 0xbfe868df,
1528 0x4312cb62, 0x9596b2fb, 0x9adbf686, 0x4bea1b57, 0xfa1a7742, 0xbd6ebadf,
1529 0x8696fda1, 0x37ed0dfb, 0xd4326d57, 0x6e3e0c6f, 0x6160bfe8, 0x795da1ab,
1530 0xfa0e6569, 0x305af537, 0xfde03867, 0xacacefd4, 0xb1f2894d, 0x1b8ff3e4,
1531 0xd93ca8b3, 0x3d72a5e8, 0xbfc82bca, 0xeb2f1f69, 0xa0e496db, 0xffbe4b9c,
1532 0x8d90d2c8, 0xdfcb1272, 0xcb18f2b1, 0x6837c8c7, 0xf3d91287, 0x5005851a,
1533 0x6e14fbee, 0x77f3e48f, 0xec65fe84, 0x1ab7921e, 0xcd63cb8d, 0x50cbc3f3,
1534 0x48b46a5e, 0xf1338361, 0xa15dacb8, 0x46d63075, 0x830cace3, 0x9ae81854,
1535 0x77b3806f, 0xafe699bf, 0x22e3e743, 0x2581f7b4, 0x791fce0a, 0xf186fb39,
1536 0x297f8f08, 0x48333bd5, 0x5636f62f, 0x22a07da4, 0x7e5402fe, 0xca90b8dc,
1537 0x2a418d13, 0xa2ac683f, 0x06c6fdf2, 0xd71a7b2a, 0x636ef951, 0x8d63ca88,
1538 0xbefe54cd, 0xb7ca85b1, 0xf950b71b, 0x9530c6db, 0x54fd1ba7, 0xb5a9f00e,
1539 0x43fd10bf, 0x432b07f6, 0x0ebd9717, 0xcdc816fe, 0x7737e919, 0xe11afaf2,
1540 0x4bc22737, 0xe213dd2c, 0x434c858f, 0x89292dd1, 0xc4c923d3, 0xf9c8182a,
1541 0xfaf6e303, 0x8abaf296, 0xe008032a, 0x0397fbd3, 0x860d22e3, 0xde3d357d,
1542 0xf683bb41, 0xd93365ef, 0x99f9163f, 0x1e9706ef, 0xd423401f, 0x8474bf37,
1543 0x35fd029f, 0x7e72f14a, 0x9cbc0af9, 0x8dddbc39, 0x964d747a, 0xa4c1f3c9,
1544 0x6dabebc4, 0x7538f5cf, 0x1a77d4f0, 0x945a67eb, 0x7a0fee0a, 0x478ee793,
1545 0x3e78f07e, 0x65ba4028, 0x59c72951, 0x3e79a593, 0x617ec348, 0x95db0f5a,
1546 0xf105fc42, 0xb6fbf508, 0x4e3448e1, 0x760e8e14, 0x1f27de1c, 0xff713f3b,
1547 0xfea17c84, 0x9a3f4349, 0x473e5975, 0xff856abb, 0x1401897f, 0xc72ea953,
1548 0x87376fad, 0xf3e217ac, 0xe0f9865d, 0xf58caf3d, 0x8a1bccbe, 0x427654ff,
1549 0xa4a807f2, 0xacde22a3, 0x18f769de, 0xa18a75f5, 0xdc39df5e, 0xf8dfd063,
1550 0x3657900f, 0x5ed15153, 0xe8b608d5, 0x0acd9d53, 0xf90bb7c0, 0xaf52e806,
1551 0xb6b57ef0, 0x8f082d1e, 0xcd3474ce, 0x3d8bc4bf, 0xb1bd685b, 0x3c6c9df0,
1552 0xc4d555ec, 0xcf9b57f0, 0xe38811dc, 0xf0ae7f97, 0xc4c6a538, 0x0b665ffd,
1553 0x584e51b9, 0x873dc856, 0x07399bf8, 0x0b7143f0, 0xcbaba3cc, 0xe9afc071,
1554 0x7acf678f, 0x8dafdc4d, 0x526ad79d, 0x757f09ce, 0xc2ce8ebb, 0xb1e2c775,
1555 0xb43ff3ae, 0xcc8dc520, 0xdf894780, 0x6ac04a5d, 0xed57f182, 0xf9434f7c,
1556 0x2a12d8fa, 0xc4dce7fc, 0xbf0c19f8, 0x2384eb33, 0x7b35ceba, 0xad5fe45c,
1557 0xede224d9, 0x79c6eb10, 0x13134e97, 0x74bd017f, 0x62e58070, 0x26dfa826,
1558 0x5dee326a, 0xfe4d51da, 0xa42c87d5, 0x89f53fa1, 0xfd04a5b9, 0xaded5583,
1559 0x3ce01f9a, 0x88154cc5, 0x4dec53af, 0xbd1d24f7, 0xd11a4c8a, 0xa366b6e9,
1560 0xa6fe00df, 0xa6fe0ea1, 0xcd9cbea1, 0x7638c4c9, 0xb80b66f9, 0x434eb4be,
1561 0x879328fb, 0x3582b0e8, 0x7afb446c, 0xfcd263bc, 0x3f0e904b, 0xf104b27f,
1562 0x479a14bb, 0x8f1e22a6, 0xd6ff1e12, 0xfbe257f9, 0x1bcf0713, 0x7c98dbe5,
1563 0xed43c080, 0x8e1fc54e, 0x991737c3, 0xfe4abf38, 0x4ff080da, 0x2dcdfa89,
1564 0x4d6bf531, 0x6b724a8a, 0xe3a46666, 0x642d8f29, 0x5f76a64a, 0x7a12f004,
1565 0x026beade, 0x12a3fafe, 0xbb226d98, 0x74c0991e, 0x04a8fefd, 0xf2af79e9,
1566 0x013472fa, 0xc04c8d4c, 0x06d80b3c, 0xd04d3be2, 0x60f08ad7, 0x1aa59cbc,
1567 0x728f59d6, 0x9dd8e30d, 0xb7df0c1d, 0xf1da637b, 0xc637681f, 0x8e1bb232,
1568 0x2776c6b1, 0x87f219b0, 0xbe7c67cb, 0x180fc842, 0x4c3be222, 0xebdfa17b,
1569 0x662339b6, 0x34d94bf0, 0xce2077b5, 0xc878c3c8, 0xfe91813d, 0x645e52f3,
1570 0xaff787ad, 0xb5847913, 0x4b0d94ef, 0xa97fc21d, 0x84b61b3f, 0xb57574d3,
1571 0xa97e435f, 0x12c3bb3f, 0xf40df49e, 0x989617a0, 0x279b9519, 0xca236094,
1572 0xd49bc4ad, 0x3c3d517f, 0xcb97a3ca, 0xfef431ad, 0x03a470da, 0xec70753d,
1573 0x482d8252, 0xbe3858f7, 0x8359f8f6, 0xadfadfc6, 0x68305f8e, 0xf0f19dfc,
1574 0x631c7a78, 0x0337a4dd, 0xfee80cc9, 0xa8f3dd9f, 0x8ff7444c, 0x85233e41,
1575 0x58f84fe8, 0x4b79e344, 0xb8f8cbac, 0x59e5ebaa, 0x81575718, 0xfe05eb7f,
1576 0x485ac95d, 0x294c448f, 0xb335cfc2, 0x55de0e88, 0xfea6bf5d, 0xff783aab,
1577 0xfd4ed66a, 0x3119bf31, 0xe1927bac, 0x7def293d, 0x9cd49ec2, 0x1d11612d,
1578 0x790b763f, 0xe087bf00, 0x106bcf93, 0xb26bcc3e, 0xb6a79a6e, 0xcf30cd3d,
1579 0xf6735f80, 0xf9d11662, 0x376ab53d, 0xd9ed77f1, 0x019e68cb, 0x6afe067b,
1580 0xfc6a1b44, 0xa3b80691, 0xc0334fe3, 0x3a7f1d1b, 0xcfc72bcd, 0xca72039a,
1581 0x2be513f5, 0xc293cb42, 0xb7a7804d, 0x91f7c1ac, 0x9b5cb25f, 0x76415f73,
1582 0x04f1fa5a, 0x744fc7d4, 0x1d34df6c, 0xea09fae8, 0x9b975c39, 0x739eb9b9,
1583 0x92174c86, 0x7c853afe, 0x18bfa030, 0x43f1afe8, 0xb7e8c7b4, 0x8c0af851,
1584 0x28f59a3f, 0x3746dfa8, 0x8e50f518, 0xef84dd33, 0x3e33ace5, 0x019ea2f7,
1585 0x521b95bd, 0x9f5ce263, 0x6fcfc709, 0x9f4f3e36, 0xc73aba51, 0xd3516e07,
1586 0x2798a533, 0xba505f4a, 0xb187a47b, 0x7957d40b, 0xe2d299fd, 0x79ff50e1,
1587 0x1532bad3, 0x7ff4d5fc, 0x86ce2d2b, 0x91b2d3ba, 0xca15abd7, 0xb7cc592b,
1588 0x89be8594, 0xcac0081e, 0x6294728d, 0x0a9cfc06, 0xccbf9b1c, 0x5fb47a8b,
1589 0x9e8478e3, 0xd3d19f80, 0x39467e38, 0xfc46ed8f, 0xd67a98e4, 0xc3f973a3,
1590 0x052bff17, 0xe62f4643, 0x1e0f013d, 0xf483c1b6, 0xbed34781, 0x8ebfc21c,
1591 0x5f2533f5, 0xf305b14c, 0x4b938e10, 0x167f7ec7, 0xeaa27d3c, 0x5b0dc500,
1592 0x71f9fe44, 0xf46eb710, 0x326f55bb, 0x3364e3f2, 0x0965d7cf, 0x378ceebf,
1593 0xfd487937, 0xa195959e, 0x53eae0ea, 0x9fc8ddfb, 0x5f1c5f7d, 0xd6237e8c,
1594 0x13d08653, 0x32a359f5, 0xa3139254, 0x749e667e, 0xc14aa3e2, 0x5b378847,
1595 0xb6cf3466, 0x7e510942, 0xc0b5fa44, 0xbf5c1e01, 0x7f31aa12, 0x8edfc179,
1596 0xe0d6e3a7, 0x775866d5, 0x83c85985, 0xbdb0b98b, 0xf08f2ab7, 0xf6836e96,
1597 0x6b3d688c, 0xe809cee9, 0x0398a4e7, 0xc37be2d7, 0xc6cd9f97, 0x43d98e7a,
1598 0xb4a2dbf8, 0x00f8470c, 0xc3cfb48f, 0x569d82f6, 0xdcc93168, 0xcf26f64f,
1599 0x69ce2219, 0x1f4acc6b, 0x55cf2fca, 0xde718b83, 0xf7bebdfc, 0xf1fc619b,
1600 0xf70f9a95, 0x9bafc65b, 0xccf88e99, 0xc03d7132, 0x72f390ee, 0xf82f5f3d,
1601 0xf8aacfae, 0x77ded0fd, 0x8435a7bb, 0xda0b33ed, 0xb519afd1, 0xfdc3ebce,
1602 0x42873e80, 0x7a35f7ef, 0xe7282f29, 0x1c95dd1d, 0x9e49bbb1, 0xf3c8373f,
1603 0xd07d633a, 0x3b7a5f7c, 0x7fbc707b, 0x9c42f8f6, 0x1d0f949e, 0x67d9e82d,
1604 0x725dfbe6, 0xb42cd1be, 0x7391fd1f, 0xcc5fef9d, 0x7fda74ae, 0xba037410,
1605 0x925e9084, 0xfbdf402e, 0x121b5f10, 0x78bef7d3, 0x6b6e5df4, 0x5db946c8,
1606 0x659f6815, 0xe625e781, 0xafd883e0, 0x21f76166, 0x50decd0b, 0xe927fc88,
1607 0x70d0d4ce, 0x740353d4, 0xfc21497f, 0x7c717667, 0xb7361fd6, 0xcb1e7ee2,
1608 0x40b7ae0a, 0x42ca99fb, 0xa22627ca, 0xfe75f8f3, 0x017cbd74, 0xfce2b7dd,
1609 0x9a8ebbe3, 0xef493e10, 0x49de44c7, 0xffecadca, 0xbdfa598c, 0x0f76be62,
1610 0xfc55f7cd, 0x166eb457, 0x7c780b8d, 0x80dfcf56, 0xff9c76c7, 0x1fe166c7,
1611 0x3b63c60f, 0x3c073ff6, 0x3c1739ee, 0x939de87e, 0xcfe30799, 0x7f093b32,
1612 0x87329f2b, 0xbea4b0ad, 0xf52fd2d9, 0x333c335f, 0x5e5627aa, 0xd71fb0d4,
1613 0x8549f2b9, 0x6bb2acf8, 0xc26c35c5, 0xf96378e0, 0xe3e910c2, 0xd903b8d8,
1614 0x5ab2f912, 0x7f13178e, 0xff07b354, 0x734e4cc3, 0xf54ef498, 0xbffb634e,
1615 0x9b30f945, 0x24ce04f2, 0xf1b1b79e, 0xf1d0b2f1, 0xe248be47, 0x8b26717c,
1616 0x619e1c91, 0xd0f7c429, 0xbb608bee, 0x33fca2e6, 0xdc6291db, 0x314cac9f,
1617 0x6e8e4fec, 0x4ff21930, 0xc9b1f3b1, 0x5fec4cca, 0x6730e42a, 0x6fb0c99d,
1618 0xee321b97, 0xa737e5eb, 0x5a63ea1a, 0x9ffa1846, 0xd0cf25b7, 0xbe7c2e3e,
1619 0x9d82fda1, 0xf1f50d13, 0xfa1b17ed, 0x6659d85f, 0xae4717a8, 0x749ff432,
1620 0x3ea18e78, 0x4326fba5, 0x2f6fa9ff, 0xd45fb435, 0x7ed0cab3, 0x0c6bc7c9,
1621 0xeffb4bf5, 0x2c8ff432, 0x00ac38a9, 0xff025efd, 0xe086f314, 0x67c8a857,
1622 0x99acfe07, 0xfc0e4f90, 0xa8c4d0b9, 0x2bc867dd, 0xa673f81e, 0xf81f9f1f,
1623 0xfb1f8973, 0xe7cb3295, 0x5952e2f1, 0xdb19b0ce, 0x0be05553, 0xc0d96fb4,
1624 0x569a9817, 0x7203f28d, 0x39454235, 0x0fc3a7fb, 0x469d0215, 0x46482cac,
1625 0x34f20d3b, 0xbd373d42, 0x27ef8394, 0x962da792, 0x290f1b96, 0xac7ded83,
1626 0x38e590be, 0x5bade655, 0xbad37de8, 0x65a7616c, 0xb230f17d, 0x5f9f9233,
1627 0x7a1c5333, 0xe3d70366, 0x86a43667, 0xdf9efef9, 0x0fe75c39, 0x24e8399e,
1628 0x9efdcefe, 0xaf01db93, 0x892cebd3, 0x7f2901da, 0x323f22f9, 0x7945582a,
1629 0xe3fe418f, 0xb8f59ea2, 0x1ff573ce, 0x99c6fd63, 0xff021e92, 0x05d1d709,
1630 0xf1f68972, 0x27da1483, 0x7161e35a, 0x36b6eff7, 0x16770f36, 0x4b2e7e0c,
1631 0xdce1cd65, 0xb40f30fb, 0xe159f14f, 0x1fd86dfd, 0xbc587bec, 0xb5ea26d7,
1632 0xbd454d21, 0xebe22b56, 0x521e71d8, 0x7e466f4b, 0xdd96a1d8, 0xc5d14eac,
1633 0xdc5a0dd3, 0xd077c7bc, 0x0473c089, 0x0d80efaa, 0xcf5fefe6, 0xff306d7c,
1634 0x0ca78b1a, 0xf4ee6beb, 0x9af21d12, 0x7ae1667b, 0x5dc13a73, 0x73fbd9d7,
1635 0xc056a780, 0xd4f08b53, 0xa714fda9, 0xb0a8bff5, 0x879c5cb6, 0x5f66bb8f,
1636 0x487e432e, 0xd51ce704, 0x72057c42, 0x738e3770, 0x4ed09aa7, 0xf28e7ddf,
1637 0x638d5eb0, 0xf2ec065f, 0xf15bed52, 0x137072c7, 0x9eb44a78, 0xe196d0ff,
1638 0x9d39b728, 0xc0a89fa5, 0x60e039b7, 0x9f22a726, 0xd1bef632, 0xebef623f,
1639 0xf344d0fc, 0x7689557e, 0xf1157def, 0x0631f7ce, 0xc7231dc1, 0xe46f75de,
1640 0xebe9a417, 0x4c17e7af, 0x10950012, 0x306c14bc, 0xe5e2db88, 0x95f6738b,
1641 0x2427561e, 0xbdefe786, 0x377881ce, 0x4bfd5e46, 0x7c8f5ec7, 0xb311fb77,
1642 0xb2845562, 0xc84178c1, 0xe677b2eb, 0xf0e8a664, 0xe5b1b5b3, 0xaf27556a,
1643 0xf7f012a3, 0x9ff72a9b, 0x5c3635b6, 0xe380595d, 0x3d7a4c7a, 0xca13dd90,
1644 0xd27988dd, 0x8c2f870e, 0x9327acfa, 0x702b58f0, 0xbe0a6c90, 0xf4bcfc89,
1645 0xd7ca6ec2, 0xe97c88e6, 0x297e7168, 0x2ae3be76, 0x97f847cf, 0x8c2958da,
1646 0x16cda7fb, 0x34b277f2, 0x08e28798, 0x5a5b9d07, 0x0a6c0636, 0x93db2fb4,
1647 0x0c53f5c6, 0xd0c6e15c, 0xa20a1bd5, 0xc71c02f3, 0x3dbc1e51, 0x7f3859c1,
1648 0x4451c22e, 0xe11276f2, 0xe84d48fb, 0x473c9dcf, 0xd21beb79, 0x43c6c4fe,
1649 0xf0e2fd09, 0xa7e485fd, 0x7e4dffe6, 0xa1c3fa31, 0x0c3fa8a2, 0xd058b2eb,
1650 0xeb8c594e, 0x8b55d9d2, 0x95d6dce5, 0xaeda1964, 0x92416e3e, 0x32407389,
1651 0x9ae1230f, 0x57f2e169, 0xe618d1ef, 0x4e51ead3, 0x54d9f0e3, 0xbb88628b,
1652 0x3138adbf, 0xede6553f, 0x7887bda4, 0xe5c2e311, 0x33a3e24e, 0x0bfbd6de,
1653 0x877c7327, 0xc8f7c086, 0x04322375, 0x0f887d5e, 0x16f1c789, 0xbc069ea3,
1654 0xb5e2e2fa, 0x326af006, 0x57ca75e0, 0x95fc95e0, 0xa98f9daf, 0x9cefee34,
1655 0xa5dff816, 0xde703304, 0x5bbc3753, 0xbab0f982, 0x086b9f79, 0x679ed7d7,
1656 0xe7e9b32e, 0x981ef991, 0x9cf383c7, 0x9aafe1be, 0xe825a7d0, 0x39ed3667,
1657 0x35cf192f, 0x93f38ad4, 0xfd5af6a7, 0x3e5f8e8a, 0x1e70f2fd, 0x1b4fa5ea,
1658 0xf2c7ccaf, 0x5bcf2a54, 0xf53bda9e, 0xa9d5f210, 0xb12d1c9f, 0x9ea738c0,
1659 0xd2a25a3f, 0x60d85b3e, 0xef2f6a7f, 0x203b412e, 0x7c03daf3, 0xdfaf8b67,
1660 0xfcfe0b56, 0x4aafebda, 0xc8d5e788, 0xef1ca707, 0xebfae096, 0x0f09675c,
1661 0x7cb9db0f, 0x6da1923c, 0xd32332c4, 0x17fa10f4, 0x4fc1a45a, 0x5b8788db,
1662 0x75265822, 0x7971fbb7, 0x23bbb7ce, 0xfa7bba58, 0xbd7618fd, 0xe201fe05,
1663 0x67b1f3d5, 0xbe1fd63f, 0x33e504f2, 0x1ab017d9, 0x80916380, 0x3b59f7e3,
1664 0x3a04a91e, 0xf37d2efc, 0x7e86e423, 0xf685eb01, 0xa0dff19b, 0x1e818e87,
1665 0xdc6c80f2, 0x7cfb72a4, 0xb512a553, 0x191ff853, 0xe9187947, 0x8a3545d3,
1666 0xeea5aec1, 0xd3f94199, 0x6429af3e, 0x61a47581, 0xbff81a56, 0x66ceeb4f,
1667 0xc5cec0df, 0x3883bf96, 0x9d9d7de5, 0x0952acfa, 0x67df30a9, 0x7fac8f42,
1668 0xd3f1127d, 0x178a65e6, 0xfefb18f1, 0xcb5eeb63, 0x727a099f, 0xf3879dd8,
1669 0x6efc8267, 0x90027916, 0xa7cf0537, 0x80f22c3d, 0x877b866b, 0x9ae3ede9,
1670 0x8252f323, 0x46defaba, 0x89d6dfbe, 0x7ca15ee7, 0xed7b9c41, 0xfaa2cc6a,
1671 0x2a5e8d4b, 0xe9638d23, 0x434b66f9, 0x7bdf9e0a, 0x3342c2cd, 0x77bf97c1,
1672 0xe51bff78, 0x1ddb42e0, 0x699b2fbf, 0x33d6f187, 0xd6f8cf3a, 0x13ddefbd,
1673 0x1df00e9a, 0x1929a4f8, 0xd2a740ed, 0xa61c478e, 0x23fdbe2a, 0xcb5d4f51,
1674 0x75a54f48, 0x306e742a, 0x3611cbad, 0xb7d3fce9, 0x765edc2c, 0x72de785b,
1675 0xb442da2a, 0x7fa5b32f, 0xef413fd7, 0x0fea0cc7, 0x7b9e1f81, 0xa98f9d8e,
1676 0x4ecf94fd, 0x7c30def4, 0xbfb9fc6f, 0xad4c77d7, 0x2a89f3a0, 0x66a77fb7,
1677 0x903eb667, 0xcfebfbcb, 0x79e1f497, 0xfa7238ce, 0xbdef3117, 0xc7f74e16,
1678 0x64768d72, 0x8fdb9597, 0x1df316ff, 0xa392dc68, 0x9651bf3f, 0xffe8dfc0,
1679 0x335ff2a6, 0xe488ff68, 0x68f596be, 0x3f72bcfc, 0x11fc49e5, 0x3619af8e,
1680 0x577d470e, 0xca04b2b1, 0x97ae4e19, 0xe50eb0d2, 0xeb9c550c, 0x689cfc66,
1681 0x2b56455a, 0xe28e5f9e, 0x5a73af81, 0x1c16bf4f, 0x7dc3dfcf, 0x7c0fb4df,
1682 0x29ebf20a, 0x7fee39a4, 0xfd11b6cc, 0xaa825b67, 0xbc52f486, 0x9d22578f,
1683 0x3a238cf6, 0xec958fd9, 0x5c3a464f, 0xde4cf2cb, 0x2dec1f28, 0x9c627a05,
1684 0xb6f14fb4, 0xa73ee8b1, 0xe340bf9c, 0x23e595f8, 0xc877e04a, 0xea5a05e7,
1685 0x784fdc0c, 0x82581ec4, 0x7e113247, 0x678c165b, 0x478cde0f, 0x5debedd2,
1686 0xf4e0154d, 0x3b40b5ed, 0xba360bd4, 0xfe00369b, 0x4704a6f6, 0x6b9796e2,
1687 0x30e9a3bd, 0xb970a7b6, 0x68e8d828, 0xd1c8b942, 0xe61f3c3c, 0x5f22e7f4,
1688 0x503dd40d, 0xdbabaf1f, 0xaf2aea62, 0xbed575cb, 0xc843e7fc, 0x5c5d75a7,
1689 0xd6f006be, 0xfea0ac59, 0x7e135f3c, 0xf4398392, 0x547fddfb, 0xbe341382,
1690 0xedc85d8f, 0x4a07dc98, 0x81f62ed0, 0x828b58b2, 0x1e04767a, 0xff47cb60,
1691 0x6cca9bba, 0xdca54fd6, 0x59dbc8df, 0xea04607c, 0x76605353, 0x35e7d239,
1692 0x18f7970b, 0x72b1efbc, 0x2d6bdd3e, 0xf985659d, 0x63d01e1e, 0x46ba5f7c,
1693 0x81b669e8, 0xc15eedeb, 0x9b369fbb, 0xc9c01a42, 0x79e83876, 0x553f388d,
1694 0x4c81cef3, 0xd4f8d7dc, 0xc9e22acf, 0x7b085cc5, 0x5b5f8f11, 0xb946822e,
1695 0xef907fa8, 0xcc7c819b, 0x21d57c45, 0xd937505c, 0x847ce9ba, 0x87f69ee5,
1696 0xff3718cc, 0x73c1e2d8, 0xbeb9d58e, 0xa2fe78fd, 0x0fae5f7a, 0xc3bde555,
1697 0x9d577c79, 0xd1399ed2, 0xbacbe519, 0x21d94dce, 0xfb27f7c0, 0x95f2477f,
1698 0x61ec878f, 0xa38edafc, 0xd79e105a, 0xa1a7bc75, 0x4524fd61, 0xda3e81fa,
1699 0xb877bdb7, 0x9c12f92f, 0x3c6657ef, 0xa7803859, 0x14ee96d1, 0xc3c979fd,
1700 0xa0fde7a0, 0x3d035fcf, 0xd021e58f, 0xf3d07eff, 0xd7f8be47, 0xaf3fd44c,
1701 0xccd7c25a, 0xcd9e71c1, 0xe15e60f7, 0xc1f84f53, 0xb4ff5089, 0x3d6f8c60,
1702 0x6b3e57d4, 0x7fbc600e, 0x96716d44, 0x6083ff40, 0x9dfde847, 0xc2f4eaff,
1703 0xdb0583f3, 0xf471bd33, 0xd36795dd, 0x60981f99, 0x7cef997b, 0x36078f94,
1704 0x976c9bfa, 0xbeb9f802, 0xea18ac55, 0x0d93795a, 0xa99365e4, 0x1f62d1fd,
1705 0xc73867d5, 0xce597f81, 0xf2b187e5, 0x278e52a6, 0x71b4dfaa, 0xdfdc0cd3,
1706 0x8a7bbb5b, 0xc89a7c82, 0x7d9d56de, 0xc825ce8e, 0x6b263e7a, 0xd4aaef80,
1707 0xaa59e510, 0xce84fece, 0x271acc33, 0x61fe68f3, 0x1f2dc68c, 0x8edd7886,
1708 0x13177c7b, 0xbdf843c9, 0x68b2f6c2, 0xabc1f51d, 0xd0be02a9, 0x41334d8d,
1709 0x0cb11fbe, 0xdcf1fbb4, 0xe12b9aa0, 0x523c2167, 0xfb26aafc, 0x099a6e2f,
1710 0xcd76ea41, 0x36867e38, 0x02afdfd0, 0x249abe1f, 0xfc682beb, 0x6293fd41,
1711 0xf1c997fa, 0xf3c2e3eb, 0xb75a3d88, 0x2ff57f41, 0x59fbe8d6, 0x3b68ff88,
1712 0xc727978d, 0x56f0475f, 0xf6f3370f, 0xbf65e850, 0x4dcfa51a, 0xeb4dfdda,
1713 0xdaaf6f01, 0x97a8a57d, 0xa465affa, 0x7cff916f, 0x49b87e3a, 0xb3aad9e8,
1714 0x39fd3157, 0x58b49b92, 0x90c75cba, 0xde3ee76e, 0xa2f186f9, 0x7a604ce3,
1715 0x7e047ffa, 0x6fb7584d, 0xedd762bf, 0x03ce90b3, 0xc510b3f3, 0xf35b55f3,
1716 0x07a75859, 0x5f1c3ffe, 0x027f0e17, 0x5ffe6638, 0x61ac6386, 0x451c28be,
1717 0xfefef806, 0x80259470, 0x02b7d663, 0x959dac47, 0x67617ee5, 0x0d5452fb,
1718 0xbdb63bf7, 0x8ffda564, 0x96c85374, 0xceba7687, 0x5b7a7644, 0xbf1f8b6a,
1719 0xc6b6d8bf, 0x1ee1e74b, 0x722a04b1, 0xdd0a7fc1, 0xabfda269, 0x6ebe796d,
1720 0xf6dadfdc, 0x26be792f, 0x8b3d349c, 0x071662ec, 0x3c5b6d81, 0x087e2aff,
1721 0xa3efef8d, 0x3e3b44e9, 0xf646c532, 0xe59cdb72, 0x9f4fff94, 0xda1c7673,
1722 0x0a7e9d49, 0x66531d91, 0xf3353f93, 0x3c26d6be, 0x149191ef, 0x2ffd1c78,
1723 0x74dad425, 0x76bc7878, 0x58667fae, 0xbe6066db, 0xcf595b68, 0x73938c38,
1724 0x803e702e, 0xfcf5abaa, 0xff311311, 0xbc1adc73, 0xbb780ad6, 0x1bf22aca,
1725 0xf2852c29, 0xc9051562, 0x6dd2c2a8, 0x5a253ed0, 0xa7caf87f, 0x3191cf29,
1726 0xefc860af, 0xaf814b18, 0xa67a3abc, 0xf641ffa9, 0x461afeb9, 0x8bf47179,
1727 0x172feff5, 0x027d7d7e, 0xb4e81dff, 0xad1ce11c, 0xd4c21cf4, 0xd1e75d61,
1728 0xd45f18d9, 0x139955ae, 0xe46d496c, 0x8bffdc77, 0xfd6207f1, 0x22de595a,
1729 0x7c44acfc, 0xf3958cf1, 0x25ff80e5, 0xe40fadfc, 0xb3f0a37e, 0x1ea2ed2a,
1730 0x9e506e73, 0xfe13ec17, 0xfc62df4f, 0x37d61268, 0xd769978c, 0xee7ce904,
1731 0xe5deb172, 0xd1334a5b, 0x7fdca9bf, 0xd963ad23, 0xf7e4d9e6, 0x84bcdf2f,
1732 0x784a7bce, 0x9bfc632a, 0x51265acf, 0x1d112bbe, 0xfd221fa4, 0x273f5899,
1733 0xde157bd1, 0x41cfa256, 0x58edafcf, 0xe67cc36e, 0xf67fa8c4, 0x7367c42a,
1734 0xf1a6dca0, 0xb31e09ef, 0x1b6d38f3, 0xb6005f7e, 0x399650ff, 0xb957d715,
1735 0xdf092329, 0x716b623f, 0xf91e5ca2, 0x61d7d7e2, 0xf093f43f, 0x9529ccbc,
1736 0x9eb2a5fb, 0xb72b9e08, 0x55e93f70, 0xe1accf31, 0xeff3661f, 0x1879c4ab,
1737 0xe97ca696, 0xec7efc48, 0xa69d9879, 0xaf903bb2, 0x9d7810ef, 0x873e0b62,
1738 0x155793f5, 0x5ea79f12, 0xc7cdd079, 0x79d79e37, 0xd3a5c44c, 0xee4dc3fb,
1739 0xbfdf3a74, 0x71e5e1db, 0x23ac1946, 0x653e4fed, 0x7f1e8ea9, 0xaf8978b1,
1740 0xc528fe31, 0x47d7a438, 0x702ce0f1, 0x0579f82f, 0x7e48df23, 0xa6f3eafb,
1741 0x2dff066d, 0x69f4de7a, 0x8b4edbf2, 0xacf5e5b8, 0x724be6c8, 0x51ef6c31,
1742 0xdebd4e31, 0xbf416e99, 0x16bcc030, 0xf5ae4b8c, 0x16eb9cc5, 0x11aedae7,
1743 0x7dc209fa, 0xfa0daefa, 0xaf15f619, 0xcfac669f, 0x37eb1bf6, 0x7effc454,
1744 0xee374d8b, 0xdf169fdb, 0xf0299e75, 0xb10ca726, 0x002d82de, 0x3bbd6eb4,
1745 0xae127f54, 0x9bcb4777, 0x26fe7d6e, 0xb0584f36, 0x4f212345, 0x900eee34,
1746 0xbca43c0f, 0x9d688580, 0x99dda94f, 0xc0a0b8fa, 0xb579ce22, 0x12f33aff,
1747 0x36c391a0, 0x9fea266c, 0xe7eb955e, 0x4afefbbe, 0x4b18ebf1, 0xcefc0de4,
1748 0x168bcc78, 0x2853ee2f, 0xff285a2f, 0x4edb3f51, 0xa5bf03df, 0xf7a1935c,
1749 0x3900c7c7, 0x5d33ae10, 0x5f3c8663, 0x9bacf73a, 0xb79ec5fa, 0xe7cdfbff,
1750 0xcec73c24, 0xe23e5ec7, 0x16007bc6, 0xf9d1366c, 0x5c8b85ab, 0xa4889df4,
1751 0x6338ec6f, 0xe171a8b6, 0x84ff844e, 0xb8f4b774, 0x74e6ff71, 0x4af299bb,
1752 0x6de3edb1, 0x5f8b37ca, 0xbaf31a17, 0x43fd9ea7, 0x57d60461, 0x375cf4ab,
1753 0xd8e2972e, 0x638c36f1, 0x5f719d37, 0x3fbe7a49, 0xaefba033, 0x86fdb7a9,
1754 0xe3cf20a4, 0x4903be18, 0x2f128fc4, 0xea70f089, 0x7e16edf0, 0xd164327e,
1755 0x28c6d7e7, 0xef9439fe, 0xa7b2a4db, 0xd1a77ce2, 0x7be71364, 0xc44c9ed5,
1756 0xfda5dd57, 0x2f2ab714, 0x41eee87e, 0x7ef160bd, 0x23e0e29f, 0xe97b0710,
1757 0x3c775efb, 0xfc1bfdfb, 0xc4ec10ee, 0x8fb71b02, 0x12f3edb1, 0x17f8a39c,
1758 0xecdf8741, 0x9bd1e4ff, 0xd013e087, 0x6f30733c, 0xd551ef35, 0x3aaef983,
1759 0xdbc90f4b, 0x3718affc, 0x76fc7f11, 0xa0f29dbf, 0xe9da160b, 0xf9d888fe,
1760 0x8f3dab4e, 0x9df30cde, 0xff707806, 0x00a8f4ff, 0x66f4f1e1, 0xf6fb83d5,
1761 0x983ae7f3, 0x54ffd74d, 0x08f9f1c7, 0x0cce99df, 0xba701f3a, 0x49df3e2b,
1762 0xfb655d3c, 0x45c57986, 0xf209fcc6, 0x8eadca1f, 0x3c57feff, 0xc70abbfe,
1763 0xd7e1c29e, 0xd53a8b9f, 0x8f1c9f91, 0x7c1f72ae, 0x1cf18b4c, 0x2ee80955,
1764 0x775eb71e, 0xb180acb0, 0x0c8eb261, 0xa075f30e, 0x7071e39e, 0xfb24f104,
1765 0xdd7cd43f, 0x8577dc4c, 0x03f11fba, 0x9d5bf9ef, 0x7762bfd4, 0xe8cfc211,
1766 0x059ab9bb, 0x3b01e64e, 0x74a399f4, 0x54f00db3, 0x43407dd2, 0x6475857f,
1767 0xc46bfad0, 0x6ef0b1fb, 0x68fd8bb3, 0xe4ca87bb, 0xc23ffdb7, 0xba3a4a7b,
1768 0x49f8bc93, 0xfc6a4756, 0x5d9a0073, 0x60039c31, 0xf1e50f6a, 0x3cf06632,
1769 0x473eff6b, 0x87894db8, 0x3bfcf59f, 0x2abb18af, 0x8d46b7e5, 0x11ad7d90,
1770 0xe6abf5f6, 0x5bdf10ef, 0x9ac492be, 0x355df46d, 0xbfe013e0, 0xb41717fe,
1771 0x7af9403d, 0x1cac9dfe, 0xf31164a7, 0x47fae9b7, 0xe33cf26c, 0x833d7cc3,
1772 0xbd70e7de, 0xfb033a02, 0x4cf6a667, 0x01bff250, 0x7e316e1f, 0xeb6b5267,
1773 0xf43d4429, 0x15fc1284, 0xedfeadd2, 0x77ac4c9e, 0xfc9279bc, 0x67c573ae,
1774 0x7f3205ee, 0xeed0d114, 0x3a5dddac, 0xb57f286c, 0x9d40e306, 0x7de28c7e,
1775 0xf187c516, 0x5abcc3c6, 0x2c11d9cd, 0xdd143694, 0x126859b2, 0x9fdf33c7,
1776 0xdf8099e8, 0x6e3ac1ef, 0x2ff5039d, 0x3fccf462, 0x69e9fc2a, 0x574cffdc,
1777 0x730d41d9, 0xdd376a6c, 0x214bf0bf, 0xf214bf2f, 0x33dff1d2, 0x74fa46ae,
1778 0xdcf269bc, 0x97e3ab93, 0xc1b21624, 0x7b5bd77b, 0x8efe827e, 0xebf6cbac,
1779 0x869d2fc1, 0x72e36afc, 0x66b5e523, 0x7d397c51, 0xfe26e6d2, 0xc476f61c,
1780 0xc7ce798d, 0xff23e951, 0x7f271fb7, 0xccd3a3a1, 0x61cd93f0, 0xa0e6828b,
1781 0xc1ff8a33, 0x2a3d70e3, 0x96a21de5, 0xde425c0b, 0xe57bdf91, 0x951e59f7,
1782 0xc2b5c7fc, 0x3c65ec7f, 0xfb11a87e, 0xf02a7fac, 0x1afe39d3, 0x5c600b3b,
1783 0x3f8f27f7, 0x78fc8539, 0xdf2d9fa3, 0xbdf67e93, 0xa55e39eb, 0x38a362de,
1784 0xf266647f, 0xaf296bfd, 0xf687ab2c, 0x207f24b1, 0x03d3c4ff, 0xd47a0a97,
1785 0xe819359c, 0x46a7a51a, 0xdfcf94f4, 0xd2127b07, 0xfa5cc39d, 0x377d0171,
1786 0x51f31b73, 0x66b6e33e, 0xe4e90b07, 0x3e51e3b6, 0xc63dc76f, 0x798967f9,
1787 0x3e38925b, 0xf877c43b, 0x91dfaa1d, 0x37d5145a, 0xae075f80, 0xabcbfd4f,
1788 0x79498f14, 0x95dce390, 0x7ee1f7c4, 0xadf357f1, 0x2bb67db2, 0x76a5deba,
1789 0x2f24b7d3, 0x27de437e, 0x24999f8a, 0xc5e58947, 0x92f215f3, 0x4d05f84e,
1790 0xf97b46ea, 0x9f1ff09c, 0x68aa6c3b, 0xdb7fc38b, 0xe73d7c6d, 0xec01a867,
1791 0xdb844177, 0x32fd44b3, 0x15f9c553, 0x3c589781, 0x3fc7e7a4, 0xd056b2ff,
1792 0x7f8ca6a5, 0x22f78ccf, 0xca0c3e60, 0xd78c1f6c, 0xd10ce65b, 0xef22cbf3,
1793 0xcd493ee2, 0xca2f56f3, 0xf6f3ef6f, 0xf49bcc2a, 0x6aad6f3e, 0xc7a60e73,
1794 0x1e8d6fe6, 0xebfd6f7f, 0xf42bf49f, 0xbecd3b63, 0xf3c1de31, 0x845dd927,
1795 0x93bd019f, 0x68d83fc0, 0x3b3c7273, 0x792d9e38, 0x5ba78f5c, 0xb1ff788d,
1796 0x33748790, 0xd7a0b644, 0xfe7905a6, 0x90bb39e9, 0x5b87900f, 0x4eec2f90,
1797 0x2c7efe03, 0xafa969fc, 0xc6575f1e, 0x7ee1a78e, 0x6ff6886c, 0xc91f7e3b,
1798 0x4b7a79c6, 0xb56fdfe3, 0x6309f05b, 0xea6eff46, 0xfb42af4c, 0x678aede8,
1799 0x9ff68b0c, 0xe7bfceda, 0x061ddb35, 0xf02cdbbf, 0x7638e521, 0x3cc40f9e,
1800 0x90cfa81d, 0xc31ece2e, 0x03e4bb3e, 0x7ae4d7a9, 0xfd911da4, 0x67f82f7e,
1801 0x8ccfe0ba, 0xfc1f3e26, 0xca9ac2b3, 0xdeff01ed, 0x7841eb9d, 0x9da2b21e,
1802 0x78f34160, 0xaddd67a0, 0x16f7d18c, 0x33fc1f62, 0xbb2df047, 0x07e81d6e,
1803 0x7e16fe92, 0xd738875f, 0xd407fd28, 0x7a9d134f, 0x0e1c43b8, 0x55f5c2b3,
1804 0x70927e8c, 0x7cfc3ac0, 0x138d171c, 0x8edc6fb5, 0xb58f42a9, 0x6322ef8a,
1805 0xfe7fe6e5, 0x569b911f, 0xe9025e71, 0xbcdf4f10, 0xc96eec25, 0x0562fedb,
1806 0xc04c6bf8, 0x624fc3e9, 0x1ce7ba4a, 0xb0bd40b0, 0x37cb414b, 0x82855720,
1807 0x45bc70df, 0x18f8a3e3, 0xf032e49d, 0x3e2a3fdf, 0x0366df0a, 0xa3a2dff0,
1808 0x2e2494e7, 0xf32a19c7, 0xc3fedf13, 0x80381fc2, 0x00d4efdf, 0xdf34505d,
1809 0x969bf01a, 0xbf4763dc, 0x43e66de7, 0xfb74e9bf, 0x8c78d312, 0xbf70b75f,
1810 0x6e2f4065, 0xbd07ebe6, 0x6d7a8ed6, 0x477edbcc, 0x2167d411, 0x5bce30fd,
1811 0xd379f8c4, 0xe3185776, 0x198f2925, 0xe0667b73, 0xa39d473e, 0xf75dbd61,
1812 0x277fa07c, 0xca8dcff4, 0x35ca0d75, 0x82b53bcc, 0x2b4eb3b7, 0x8b160fdd,
1813 0x47bec62f, 0xeff226f3, 0x7ae24c6e, 0xd234f50d, 0x6ec21ca9, 0x4afdc03b,
1814 0x798cc86e, 0xe4c657d4, 0x957dc44e, 0xa2c14943, 0xa67ef035, 0x29983738,
1815 0x26669bce, 0x126b72f1, 0x0e99cbd7, 0x5c1d065e, 0x79ba67bf, 0xef79d8ff,
1816 0x54defd12, 0xed7f064c, 0x7c3c8204, 0x38af9f30, 0x327e88cb, 0xed42bf4f,
1817 0x8002cdff, 0x9997456f, 0x4d3b07f2, 0xea24fac1, 0xfb1d12a7, 0x0f8b3d4c,
1818 0x1ef10123, 0xf3128ba5, 0xb167d493, 0xa3ea34fe, 0xfcf20d9b, 0x3be3825d,
1819 0x9190afb8, 0xfafcbfd8, 0x027e7d7c, 0xb7c26b7f, 0xfa496fe2, 0x8c80bccb,
1820 0x307f25bf, 0x6bad20f6, 0xbfce4cea, 0x6177afa0, 0xbafa0afc, 0xebc91a68,
1821 0x6bbc780f, 0x719178e3, 0x4f66667c, 0xc0b7c61d, 0xbc9ef487, 0xe4f729f7,
1822 0xe41e749b, 0xf537248d, 0xb7f0e5db, 0x5bc9c526, 0x6869a88d, 0x8487fba2,
1823 0x42f795dd, 0xafdf6a8d, 0x19be3aa8, 0xfee1c555, 0x60c59269, 0x7d443a17,
1824 0xd3971277, 0xa5115551, 0xd88dfa00, 0x015143ba, 0xfced119e, 0x0688f77c,
1825 0x0c9ff746, 0xf0e61bcc, 0x95870d8e, 0x70a28adb, 0x17669b37, 0xe69e0079,
1826 0x09af874c, 0xe0ce699e, 0xcd77080b, 0x039d08b1, 0x5bac7a9d, 0xd32978c5,
1827 0xf205ffe9, 0x6bd7849b, 0xbcc08cf6, 0x8718e3bd, 0x9fc065b3, 0x79e6c9ef,
1828 0x3c0aefc9, 0xc9fb09b7, 0x4efdd30e, 0x336f6e4e, 0xa6db19ef, 0xfd26673f,
1829 0xccd7e858, 0x72e3ee28, 0x614f799e, 0xb8ba03db, 0xb03f3cb1, 0x0f979f03,
1830 0xbf11371b, 0x307fcfb7, 0xc73ee2a2, 0x154d5b0b, 0xf6fc38e1, 0xa75394b6,
1831 0x2eb8d7ff, 0xc957ff09, 0x4967ec87, 0x1def9a1a, 0xb7060f82, 0xa5ed443f,
1832 0x84dfa64f, 0xd06cd6f0, 0x48f16e18, 0x033a67bc, 0x239f1027, 0xc4155bda,
1833 0x9f8e63c9, 0xae0e7828, 0xce798aba, 0xaef6d203, 0x7bc1cb6b, 0x7cee6a97,
1834 0x79ef072e, 0x38c0f092, 0x98d6ef84, 0x0fd28b73, 0x67e11ff9, 0x67033b94,
1835 0xcebafc70, 0xb7bfb44d, 0x5fbf0772, 0xcfbae127, 0x9eb02f11, 0xd5bfc8f5,
1836 0x5478bfc0, 0x8dfb0147, 0x6859acf4, 0x6a26efa3, 0x63fe7176, 0x18f0b41b,
1837 0x8eefb7ac, 0xe47da098, 0xa61f7edd, 0xed77abef, 0xf0e99656, 0x4c26b235,
1838 0xb9e77bfb, 0x97227ee4, 0x4bed11f7, 0xb38f886a, 0x63e43e1c, 0x71d92fcc,
1839 0xfdcecf3f, 0x1e52deaa, 0x425af49f, 0xafd0bd63, 0x87c93737, 0xbabd3bdf,
1840 0xdefa0afb, 0x35bcf5d0, 0x7ca3b8a2, 0x6f7ac0f3, 0x40f9c229, 0xdf20f339,
1841 0x835fde80, 0x2726f2f5, 0x1a9fbe43, 0x77a9c743, 0x3bf6be73, 0xc31ef2dc,
1842 0x63d7c889, 0x81aedc1d, 0xeebf205d, 0xf3c38590, 0xdd74e33c, 0x75c8149a,
1843 0x87f7e064, 0x54f18611, 0x86bb454a, 0x387608f9, 0xbd5bf095, 0x37d683b5,
1844 0x7bf71772, 0x92b577aa, 0x82fd4a3c, 0x7b7bc0f8, 0x457be2a7, 0x47040fc4,
1845 0x943b93e9, 0x927fd0e3, 0xbcf3ccc3, 0xc7ec775b, 0xf019887b, 0xd02fc60b,
1846 0xce4affbe, 0xe96e2a3f, 0xce3dc80d, 0x59e7c453, 0x097b93a6, 0xbff91c77,
1847 0x1e77e118, 0xe5c83eeb, 0x6fefc23f, 0xe921fc12, 0xf5c1c330, 0x21c7a48f,
1848 0xe300e80d, 0xa24bca1c, 0xa23ca471, 0xfa11ccfc, 0xc68ce4c9, 0x090e1249,
1849 0xd9472ee7, 0xb8298e15, 0x775a6eee, 0xe09556ed, 0x0502d72e, 0x3b7c75ab,
1850 0xfbf9c1cf, 0xb57782c0, 0xf9be781e, 0x9f0947e7, 0x3f0a2db5, 0x5472dac7,
1851 0x3e7a879b, 0xe319acf4, 0xff19ab9d, 0x51cf747b, 0x7757cfd2, 0x76d7bc70,
1852 0x736f56ec, 0xf728f946, 0x74c581e4, 0x95bb751f, 0xe9923fa1, 0x788cde0c,
1853 0x024fc418, 0x25cf520f, 0xf4871392, 0xf91a4253, 0xe421e029, 0xf520dc62,
1854 0xdf1156e4, 0xfe7f2730, 0x515d624f, 0x41ac10fd, 0xf927947c, 0xdf50d80e,
1855 0x3ce8544d, 0xe933b487, 0xf51e3833, 0x37bdc4f0, 0xd287e64f, 0xb25f8c98,
1856 0x63bee8e7, 0xe2b7d018, 0x5d04bbfd, 0x3f8479e1, 0x37687967, 0x74b1dc25,
1857 0x6bf081fb, 0x1351f0e2, 0x476b1fc2, 0xfac05f24, 0xf73db19a, 0x41ec89a4,
1858 0x86d6c86d, 0x98af26fb, 0x75df90e6, 0xf09b8160, 0xdf90b357, 0x67f9bc63,
1859 0x84d4af5c, 0x777f749c, 0x256e704d, 0xdba543ed, 0xc50fb87d, 0x79b50782,
1860 0xf774c1ae, 0xce9fbf3e, 0xcedd5c31, 0x8f4060e5, 0x4bfa73b6, 0x1fd72efd,
1861 0xcfc7375d, 0xec858d2c, 0x6dbc51a9, 0x7d08f24d, 0xdfe5cc10, 0x3ccd7fa3,
1862 0x7b1666f7, 0x88b3d29f, 0xcf5b5a8f, 0x2faadc21, 0xd35fbb79, 0xf2c727ef,
1863 0xd7baf557, 0xac2ed10a, 0xa54c3aca, 0xb7a0ff3e, 0x7d057b57, 0x8be5149e,
1864 0xa7985f48, 0xc93b727a, 0x0d07f54d, 0x0ace6f24, 0xc79c67ae, 0xd6307a8c,
1865 0xb4772a5f, 0xdefdc2cf, 0x9e2a1ff2, 0x5ed89626, 0xde7850ac, 0x2fada3f3,
1866 0xc19cf1bb, 0xe26bbdc0, 0x0e1bf03c, 0x3bbdffce, 0x97c4e101, 0xfe50da0d,
1867 0xc78d57e2, 0x74296f22, 0x7dc0808f, 0x1719aeef, 0xd2e7887d, 0x7e532677,
1868 0x375dd3e7, 0xc021f9dc, 0x72e3bbdd, 0x4de943b2, 0xfe9fe201, 0xf70fbb0c,
1869 0xa97e20df, 0xebee8050, 0xe3765fdb, 0x3f27e4fe, 0xda2270ba, 0x9c050fb7,
1870 0x5e667f27, 0xe7b97887, 0x865e9f99, 0x2561d5ed, 0xef6cf50d, 0x15fe1fce,
1871 0x8ed570f5, 0x9a9f8a7a, 0x0d4bf47e, 0xe14d39f7, 0x677cfe56, 0x7dfb07b2,
1872 0x65d37db2, 0xf6a6ef88, 0xb93f6a26, 0x07ea95bd, 0x4be9f99e, 0x33f68dff,
1873 0xbf61f6e0, 0x4fdb3f93, 0xaa09a974, 0x04f0defc, 0xeee8fd7c, 0xa19f5cfd,
1874 0xb07287bf, 0xc919eb90, 0x3f7f92d7, 0x8bd6e679, 0xc6bbfaf4, 0x60a5181c,
1875 0x1f5661ff, 0x7d07d79e, 0x15fbfa4e, 0xc4ed533b, 0xce9cadf7, 0xaf74d5e6,
1876 0xd73e7943, 0xdc61883b, 0x72febaf7, 0x91477d07, 0x4afb10e1, 0x293f1176,
1877 0xbcc3ed0a, 0x6d05e972, 0x217dba4d, 0x9457bf49, 0x1756a3d9, 0x8b379f45,
1878 0xb8939b79, 0xf514f93d, 0xd539c430, 0xac1efc65, 0x5f6c7f4f, 0xd6b5fe48,
1879 0xd76bf743, 0x34be7114, 0x9a3d393b, 0xb7e57e45, 0x39630ee0, 0xcf02e41e,
1880 0x8eeb40d5, 0xfadf292f, 0x1a6fd913, 0xbed357c2, 0x784752da, 0x0e7f11f9,
1881 0x8ee7c658, 0x354b06a2, 0x1b592f3c, 0xe91c5e3f, 0x3dfd3274, 0x663a2376,
1882 0xde92f28f, 0xe8c6fab1, 0x5511d2fc, 0x27dc26c1, 0x906d6ab8, 0xe17ea9ee,
1883 0x5ee937e3, 0x2ac667e3, 0x30df8893, 0x2f76847f, 0x6a79a4e4, 0x70078f31,
1884 0x7114ef9e, 0x17a987a3, 0x32aff1eb, 0x75fb49d5, 0x6a97a4fd, 0xdc5d859b,
1885 0x5b19e221, 0x6bde367f, 0x2f39ef0a, 0xc09bedd6, 0xd5274e7b, 0x8fe7b3fb,
1886 0x5a143b47, 0xabc87648, 0xa527bc11, 0x09a161fe, 0xa1e2e8b7, 0xf51738d8,
1887 0xca77e61b, 0xe77ea59d, 0xe3296894, 0xdd3c58df, 0x3877da25, 0xea277efd,
1888 0x16e79dc7, 0x7a09d687, 0x2cf4aa3f, 0xed0e3e47, 0x2f907bb3, 0x29eb2eeb,
1889 0x3bb1ebd4, 0x0b4e9e04, 0x41dfc13e, 0x64cdb8a0, 0xb5df110a, 0xa4dad05d,
1890 0xe77bb60c, 0x44757f09, 0xba41e2a7, 0xc73ad88c, 0x9bf03f40, 0x7f686bd6,
1891 0xe4252ac6, 0x7eae76cf, 0x11e61c6d, 0xaf586e81, 0x495d98eb, 0x833b03f8,
1892 0xe75d6cfe, 0x73840eec, 0x3eb5fa64, 0x3f0797dc, 0xe77d1664, 0xa0a6c351,
1893 0xda3a3efc, 0xad246fbf, 0x1e786143, 0x384b51f3, 0xa3f7ed0b, 0x787d0ae3,
1894 0x582ea63e, 0x0af24359, 0x2f7d2d7e, 0xfe40dc15, 0x26f79d6b, 0xc6a7ed1f,
1895 0x853ef9ca, 0x1be054fc, 0xab8b1dfa, 0x7c2cbbf1, 0x7920ec3f, 0x2dccebaf,
1896 0x9eaef845, 0x9e60f3e9, 0x8fc494ed, 0xf4dd2d2c, 0xf7a7183b, 0x27485958,
1897 0x03eeaf97, 0xf80266bf, 0xafc17b35, 0x3fdf8099, 0x1571d9fa, 0x0d7a71c6,
1898 0x5deab779, 0xcdef74b9, 0x7f8ed129, 0x2d7ddd5e, 0xe21195b5, 0xcfe11acb,
1899 0xc5fd5ba6, 0x26e8ebb7, 0xfa5894fd, 0xf6e4ee3f, 0xe727bce8, 0x00463d12,
1900 0x239f103d, 0xa26e9ab6, 0x863485f5, 0x8aaabbeb, 0xbe01ea45, 0x229ab6ab,
1901 0xfa884f97, 0x3de3b131, 0x4f7114e9, 0xf518a05a, 0xa702f95b, 0xca87af4f,
1902 0xbb26fc93, 0x2c628fce, 0x92e31930, 0x845d338f, 0xaf4e1df7, 0x7e0c87f4,
1903 0xd3b8e0cf, 0xe1f8c3ee, 0x04d0969a, 0xaf0e87dc, 0xf2885a4f, 0x49d47a08,
1904 0x781eebfb, 0xb6d6e31f, 0xb8f3b64b, 0xf9d689b5, 0xc247a77d, 0xe301b937,
1905 0x5ac0fcdc, 0xbe5c7f6e, 0xe5d6fb78, 0x2ee7e94e, 0xbef3c62e, 0x3e9d7375,
1906 0xff36af8c, 0xe38a5942, 0x746c85d7, 0x705d6e39, 0xf2579bed, 0x5fdf8038,
1907 0xbaa2fc23, 0x347d1bf4, 0x7a7e20ff, 0x4e8ddb8f, 0x4ebaaf4e, 0x1c642f6e,
1908 0x5e217a8b, 0x29ca5ede, 0x6b8c63ea, 0x39497f24, 0x3c79573d, 0xfc90096d,
1909 0x2375869c, 0xe1f00e3f, 0x630f9c0b, 0xff8934e3, 0x8bc2f8d8, 0xef7506c2,
1910 0x8f7d0776, 0xe69af52f, 0x3d451c0c, 0x6476d754, 0xd0abb123, 0xdc2f7543,
1911 0x3f94385f, 0x78f95365, 0x3d2b9036, 0x1359e0df, 0x432a44d7, 0xc0df3a4e,
1912 0xc6df5fb8, 0x1d8e8fef, 0x4f42b7ef, 0xbf4a7c49, 0xcf82f319, 0xc29ff943,
1913 0xfa227d7e, 0xcf29d5fd, 0xfc0d8457, 0xdf0535e7, 0x44f17dc3, 0xf7be56fa,
1914 0x7226f34d, 0x63efa97c, 0x99f325e9, 0x45d98eb8, 0xecb5fb89, 0x0c48f117,
1915 0x3e0b14ff, 0x80e7037e, 0x07724f75, 0xbea0b917, 0xd3f99928, 0x7e8bdf00,
1916 0x29f7e569, 0xc42fed8c, 0x655aaa78, 0x5797cc21, 0xf584b4ef, 0xa1f736e7,
1917 0xf5ef040f, 0x33216cb9, 0x3bb95df0, 0x0671c1e8, 0xcbbd87ee, 0xc1e1e74e,
1918 0x7282994d, 0x481ed23b, 0xf7e06575, 0x4f743d89, 0x1e0e63ec, 0x311ff44f,
1919 0xc5cbcf87, 0xe87bbe7b, 0xacce84f7, 0xea7ca7cd, 0x61fc2f3b, 0xede01fcf,
1920 0x1a3e7b53, 0xd493cfad, 0x55364cd9, 0xad3c6f97, 0x2b67dfc4, 0x167d7176,
1921 0xf3f65bcd, 0x438be5bc, 0x63eb41e7, 0xf3d1fbf2, 0xfdf9b1b3, 0x6fa878e8,
1922 0xfbf263eb, 0x6f5c5d07, 0xf9e7df47, 0xf14c77fd, 0xc7bd6fbf, 0x8bafdc65,
1923 0xc5cfbf6d, 0x8f23abf9, 0xe3ff45cb, 0xe4fd184a, 0x115d6be5, 0x396b8fbc,
1924 0x63bf463c, 0x311427b9, 0xf9ae51b9, 0xcdfc323e, 0xbe5f81b5, 0xe807d844,
1925 0xbe474ea7, 0xff68790c, 0xd0f42831, 0xff57ce92, 0x72f4f18c, 0xc3a6d995,
1926 0xbe6d4b38, 0x13fbf843, 0xba673a1f, 0x7e56ed51, 0x744c86e7, 0x6a2d86e6,
1927 0xf455bca0, 0xf374f57c, 0xfabe72df, 0x57302bb0, 0x7fd21bf2, 0x5f5cedd1,
1928 0x9756fec8, 0xe467373c, 0xd01377b7, 0x665dc739, 0x3ababe46, 0xc698b029,
1929 0x4194fdbd, 0x7a569caf, 0xf201fe9e, 0x7bfe6ae3, 0xd7efb147, 0x8afaf98a,
1930 0xc53ee9bb, 0xc97fd5be, 0xebaebf26, 0xff51b7d5, 0x817bcad5, 0x7b862c3b,
1931 0xfc932b81, 0xf7efc4d5, 0xfba14f4d, 0x73c186ce, 0x1ab82782, 0xf6fe41e1,
1932 0xdbf9eba7, 0x2ce78c9b, 0xba01b5ea, 0x921ef7d0, 0xcb946c2e, 0x23ae8f48,
1933 0x36a58f44, 0x701bdd3f, 0xf0403f9b, 0x4c8e4a2d, 0x5ff018f1, 0xf7dd37f4,
1934 0xf6e42958, 0xfdfe2d1d, 0x3e09f7e2, 0x8dfb283c, 0x4efafce0, 0x1e7aab36,
1935 0xff234ccb, 0x2ce42c3e, 0x71cbde2c, 0xbc421ffb, 0x18795e80, 0x8e7400f1,
1936 0xcaf5e8a4, 0xe7ba7ee4, 0x374a6fa2, 0xae7d1f7d, 0x80ac66f8, 0x8e784bd6,
1937 0xd1385e73, 0xf0b56f7a, 0xb5df0075, 0x47af48b9, 0x87bfebc6, 0x5b80b9ff,
1938 0x493be5ca, 0x142cbc46, 0xe091fbeb, 0x87974a93, 0xfd7c1be7, 0x3bce38d9,
1939 0xb8f1f1a9, 0x768f8a28, 0x7fb583c2, 0x6fd01a71, 0x6d35d83e, 0x12a7e122,
1940 0x938a0f9f, 0x49ff228a, 0x5c6b6dfb, 0x0bc5ed0c, 0xfdc9be72, 0x963f8f3c,
1941 0x885a0bcf, 0x57d96eff, 0xc2bd6de0, 0x3145e77f, 0x2b6844c3, 0xdf2f32c7,
1942 0x7fce980f, 0x203ecaaf, 0x195c8797, 0xcec4fc51, 0xc09b0c7b, 0xc4bb779e,
1943 0xe63e40f7, 0x1f16f7c3, 0x8b75ccfd, 0xf43df0d7, 0xef4e385b, 0x1fc8479d,
1944 0x0a45a63b, 0xda719c5b, 0xc7b6c8b5, 0x6b3b6894, 0xadc17ee0, 0xbbe99acf,
1945 0x9ea66398, 0x2d7f7047, 0xfc99a6f4, 0x3dde3fa8, 0xfa2bbe83, 0xffa30ef4,
1946 0x45d0527a, 0x20309f7e, 0x830b783f, 0xc5eff079, 0xcb9ce6dc, 0x3ee629e5,
1947 0x14164af6, 0xfb13fbbf, 0xe103427d, 0x893df079, 0xe73c87eb, 0x7ce6e995,
1948 0xf38269f3, 0xebfb8a19, 0x3ee327da, 0xc4bed45d, 0xf1f1d3ee, 0x474e6edc,
1949 0xf6fea769, 0x304aaef9, 0xe77175df, 0xba7cf393, 0xb3bafe3c, 0xd58edcdc,
1950 0x461becc7, 0xb3e795c7, 0xa49fa85a, 0x2cd9fd77, 0xd2eb2e7a, 0x37be8a8f,
1951 0xfd8bc68a, 0x13e6472e, 0xa7beff25, 0x9efd1b30, 0xf224db11, 0x78099e86,
1952 0x687bd0bf, 0x06df412f, 0xf52f60af, 0xfe4b8800, 0x9aa17879, 0xd8efe517,
1953 0x9d5f0075, 0xd51effd4, 0x4fb8b704, 0x217642ef, 0xf821177d, 0xe59df179,
1954 0xf25aee74, 0x854f546f, 0x71adbc78, 0xa7319e3f, 0x18b3ff41, 0x13a4b0fb,
1955 0xb204c1ec, 0xfc0e74cb, 0x12378bf8, 0x5f32571f, 0x17d1e926, 0xe93f74ad,
1956 0x120bb5d7, 0x4b421b9e, 0x8adefc2c, 0x6bc7ba74, 0x86ff988e, 0x981fee2e,
1957 0xfbfe7e6c, 0xf5e67e55, 0x03dff264, 0xca05fb21, 0xa5fa855d, 0x00cc8eb2,
1958 0x3162e9f5, 0xf00fbe0a, 0xb64a2a5f, 0xf2859834, 0xb7ffef26, 0x961670b3,
1959 0xbcf9174d, 0x04ae5e58, 0xa7070e54, 0x30d62cf3, 0x6c9bfb0a, 0xff9c663d,
1960 0x58da7991, 0x4fa01fbc, 0xdf89f249, 0x74fba3fb, 0xf3f303ad, 0x9dd64bba,
1961 0x0eefc32e, 0x7dc5bbd4, 0xa366360f, 0x4673ebdf, 0x057da13e, 0x616cda51,
1962 0x0701ddfa, 0xcdba448b, 0x8c00fbf8, 0x614f9bbe, 0x3dfc112d, 0xff17be8c,
1963 0x1e1c518b, 0x76fc0fbd, 0xef2194f7, 0xc7b6370b, 0x2a9e17dc, 0x7e634ae0,
1964 0xad221fba, 0x635f78c2, 0x42ad7386, 0x3016e13f, 0xc444cf3e, 0x0b61ff43,
1965 0x6f0bef63, 0xe1fc7051, 0x1b73e341, 0x5f7a463b, 0xbeb20489, 0x93de8b4c,
1966 0xdf8920b4, 0x22eff44b, 0x115b9c8e, 0x6f015728, 0xafd88bf3, 0xe8de50fc,
1967 0xe1177e09, 0x4370f1bf, 0x17d40d6d, 0xe3c6cebe, 0xc9c530f7, 0x185dea9e,
1968 0xefcadd7f, 0x3efe2d6b, 0xec361d67, 0xf0c78a3c, 0xc9b51707, 0x2b2ace78,
1969 0xb17d718c, 0xd48fb443, 0x7f18bda8, 0x3fdf1100, 0x95f74bcf, 0x74f38bd4,
1970 0x9a7987f8, 0xc333f3d6, 0x67d30768, 0x7ac46ff4, 0xee8cfdff, 0x19f79059,
1971 0x408ec76d, 0xbf4afa9f, 0x87da0325, 0xe23e64cf, 0x03bed149, 0xebcf9dff,
1972 0xdf889797, 0x5d47c08d, 0x2733ca9b, 0xc6fa9b13, 0x5cfcc1b0, 0x18bb35df,
1973 0x73f954f3, 0x297f13a7, 0xba0a2f82, 0x7c51ff14, 0x3f68c22f, 0x972bbeb5,
1974 0x1c17dfce, 0x719e51f6, 0xd4e1a981, 0x1bdf5c1e, 0x13effe3c, 0xc84cc6fb,
1975 0x7918d4f3, 0xafca24b9, 0xe72c5ed4, 0x7accfb97, 0x3ce046be, 0xfc44a0f0,
1976 0xc7bd12c4, 0x1662ece5, 0x6671c3fd, 0xbd25c744, 0xbdb45332, 0x3fdf0b72,
1977 0xf646aa9b, 0x225e1ca3, 0x4e5162ca, 0xe2330166, 0x7f73c4ab, 0x5177ce13,
1978 0xf21a68e0, 0xaf9b74fd, 0x9f46af19, 0xb86150bb, 0x4e9cc4af, 0xffb17ebe,
1979 0x3d8af52d, 0xfb67e799, 0xddbab3dc, 0xdf997dba, 0x30df85ba, 0xb98d8d96,
1980 0x24f7ff67, 0x3bffa517, 0xdb18dc91, 0x4066e463, 0x7d3f313f, 0x7dfb18b7,
1981 0xff3f3ce1, 0xc05e6a6e, 0x7e3e7cf8, 0xe71f97d7, 0x15d0ec77, 0x0b8e8ccb,
1982 0x78416472, 0x6ec77f62, 0x2ab7f48e, 0xa2d6fe8c, 0x8522fa7f, 0xa7b0c0ec,
1983 0xc1ccbf6b, 0xe25ce67c, 0xb12ebacb, 0x43fc0f3f, 0xfd89e3df, 0xe34efaf9,
1984 0xd77d7cfe, 0x74337b92, 0x9d75f3fb, 0xcf3fb55f, 0x5bbfeeed, 0xd30f74c2,
1985 0xd604afbf, 0x165e7982, 0x7107c2fb, 0x9462783f, 0x3cc5aeee, 0xe35073af,
1986 0x3107f4fb, 0x4bcba37f, 0xfcf070cc, 0x340b8ce8, 0xe5573e7a, 0x2129f2fb,
1987 0x0b92f927, 0x665defc4, 0x7e41d998, 0x1fe7847e, 0xeb3e22c2, 0xb40d7e16,
1988 0x47fca06f, 0xa465dc8c, 0x6547ca31, 0xf2963cdc, 0x8abb0b3a, 0x0d3e6327,
1989 0x7fe533f4, 0x7a5eddbb, 0x98b0617f, 0x395723f2, 0x8af3a46f, 0x6aad5df5,
1990 0x7adf4ea5, 0xf5f78d93, 0x9a5df9c4, 0xfa29e482, 0xe019a5df, 0x489e7a27,
1991 0xa7dfcb0f, 0x9bbe62ac, 0x7de2e597, 0x9d774001, 0x3194b79d, 0x53fb4f7e,
1992 0x5d2b9d0a, 0x76483ce5, 0x630ed578, 0xd45b943f, 0x6bafd57b, 0xcd537f74,
1993 0x467c41ae, 0x5de52d72, 0xa1b517de, 0x3ee0afd4, 0xe611df4f, 0x77fa436b,
1994 0xc05b8cc4, 0xe04f98ed, 0xa5e858b3, 0x3666f349, 0x24e53ee1, 0x565f9713,
1995 0x7fc91be9, 0xe7917377, 0xc7551d84, 0xfe50cad3, 0x63eb9f40, 0x067dfcb3,
1996 0xc4531fd4, 0x717ab1f8, 0x2e03f08a, 0x137d6153, 0x0a7d76a3, 0xa683f5e3,
1997 0xbddd332e, 0x3c9ce02f, 0x9fdc4720, 0xd24a7a90, 0xc6e5ef03, 0x92cb5df3,
1998 0x63c87e85, 0x184f4879, 0xc157f89f, 0x8d2a73cc, 0xbca1521f, 0xf407cc44,
1999 0x84df210e, 0x9dfa364c, 0x034a8d8f, 0xfa1b79e9, 0xa03e508d, 0xfd7f4904,
2000 0x46642abc, 0x1ac45ebc, 0x1726b86e, 0x03b758f5, 0xb07c05e9, 0x4d1fcf52,
2001 0x5bbd922c, 0xb509f031, 0xe8c4a6f7, 0x3d12a61d, 0xc238304c, 0xa5ad7669,
2002 0xc42bf47d, 0x6e53a273, 0xc9d51fb4, 0x3fb4618f, 0x87c01fea, 0xf52fddb1,
2003 0x93ea3309, 0x8f05f65c, 0xf43feed3, 0xfb0f8c1d, 0x8c5fc22c, 0xa1dd4ba1,
2004 0x641f8b93, 0xbe49fa51, 0x983598ba, 0xca1f00b3, 0xf75e792f, 0x2a5ba462,
2005 0xfc8c51fa, 0x892c69a7, 0xe64d8be4, 0x57c907f9, 0xa2255e92, 0x4fa484f6,
2006 0x7841cb0e, 0x53b4ed2f, 0xa462e9de, 0x58bdd013, 0x4aed2f8c, 0x6af4e4c4,
2007 0xb0174879, 0x7ec1e61b, 0x97aa665e, 0xe4c933e8, 0x614cfa27, 0xdba434be,
2008 0xd7ddf6cf, 0xe8eb7084, 0xe3192db0, 0x80e80545, 0x3ed8357c, 0xe463db18,
2009 0x94bbe259, 0x2c9fc979, 0x9c394665, 0x670d04e1, 0x8dcafba2, 0xa0b363f7,
2010 0x7b94f08a, 0x6f8fdd06, 0x41b1d232, 0xc8ae7845, 0x444bf632, 0xa7a41ccf,
2011 0x89690fb4, 0x6ae529e9, 0xa9d39db7, 0xfa84e81e, 0xd2afd266, 0x34813867,
2012 0x25ccade7, 0xc53bb0fb, 0xfaf584db, 0xc5f4851a, 0xcbdf6ee4, 0x106fcf58,
2013 0x337eb9ed, 0xafd683ee, 0xde53ede5, 0x7ac0cc0a, 0x5ede3ac1, 0xc9b04f7c,
2014 0xaddfe385, 0x2fd8bdd0, 0xcbc7727c, 0x47be1ed8, 0xcfca5fbc, 0xe06fd6e1,
2015 0xf9847fef, 0x3cf10bde, 0x7c0ccb44, 0x9739ae3e, 0xf0b00eff, 0xfc172e67,
2016 0xe3695bb2, 0xc83c20f7, 0xc8715dc7, 0xce28c496, 0x65cafee1, 0x6f979d62,
2017 0x3f4cebe5, 0x1785557e, 0x37b2a9f8, 0x2d95d740, 0x1109c164, 0x3372ef58,
2018 0xf1f9f204, 0x10bc1be4, 0x0d288f28, 0x500aa744, 0x72fbf49d, 0xc0b67cd3,
2019 0xc7ef9e78, 0x92fa79ef, 0xf329bc79, 0x35ffb8e5, 0xfb4f675b, 0x469e7992,
2020 0x654ccbf6, 0x09ef3f7c, 0x91a3f917, 0x7c8298c7, 0xfec0b88f, 0x57faf289,
2021 0xbd9037e4, 0xe64722ba, 0xa5d47bf3, 0x97f15f30, 0x178acd9f, 0xcc9e7f07,
2022 0x62c7e4ed, 0xaf3e4f1f, 0xbdfdf30a, 0xf4cbc8dd, 0x30e9ad7d, 0xe19853d5,
2023 0xb9ddab1e, 0xfe7aaebc, 0x28f35f7a, 0x06b35dfc, 0x36ca8435, 0xcc7da15b,
2024 0x679fe0eb, 0xffe14627, 0x2830d93f, 0x00800092, 0x00000000, 0x00088b1f,
2025 0x00000000, 0x7dedff00, 0x45947c09, 0xf37f78b2, 0x093215cd, 0x87213b93,
2026 0x98884013, 0x861c2184, 0x4109264b, 0xe8098414, 0x720d7282, 0xeb22dc85,
2027 0x97f75763, 0xd9110441, 0x73d6f8dd, 0x0160763d, 0x18896151, 0xc3824830,
2028 0x12a20882, 0x75040411, 0x0844ae22, 0xf1e20c49, 0xabaf2e1e, 0xbe667bba,
2029 0xfc38666f, 0xddbf7ffb, 0xdb2e23f7, 0xaaefafa9, 0xeaeaeaea, 0x084c8eaa,
2030 0x908238b9, 0xadc4b45b, 0x9680a1cf, 0xc8401bfe, 0xd5fa25dc, 0x3f02242b,
2031 0x213c6376, 0x33fe1277, 0x192d7aec, 0xf01dc844, 0x289085bb, 0x2afda4b3,
2032 0x9fdefe83, 0xd328bff4, 0xf3bfcf72, 0xc84d94a3, 0x3a558caf, 0xd50a1dd2,
2033 0x8459ece8, 0x9c9b359c, 0x7c84be9a, 0xcce2392e, 0x7d690903, 0x965cff76,
2034 0x64beceef, 0x47e696be, 0xb048d4d0, 0xefde62df, 0x13d2e27c, 0x977cdfda,
2035 0x918f0bee, 0xfd22ed0d, 0xa43a6a57, 0xae9a1a27, 0x232f7e57, 0x41e93d1e,
2036 0xf2ad7948, 0xe271257b, 0xe57acaf7, 0x91d99277, 0x845efd06, 0xf69f8a1f,
2037 0x5907cb67, 0xcfff6932, 0xe6147fbc, 0xb9346c57, 0x97129a65, 0xc193d5ae,
2038 0x1e7ce1eb, 0x4e157f34, 0xc8fba793, 0x64246f17, 0x6cc89752, 0xbb9095d2,
2039 0xe67e8ecc, 0xf99c4238, 0x146529e6, 0xe1e9cebf, 0x5c5025d6, 0x4c396536,
2040 0x6308fdb4, 0x8bce9b96, 0x4cc588d8, 0x79f12df1, 0x9f0c0d4a, 0x3c52471f,
2041 0x4832f8c3, 0xe699e006, 0x14d1f53b, 0x8448e3ee, 0x93881bf1, 0x88c23e00,
2042 0x4252112b, 0xbf1846ac, 0x42475e1f, 0x2179adff, 0x57ccaef1, 0x1f027de1,
2043 0xd36244cf, 0x47137f41, 0xa775f12b, 0xfbd22169, 0xfbf2bb4e, 0xcb1388af,
2044 0xc2ac9a4f, 0x24c9b12f, 0xe0aed7de, 0xca1cbb93, 0x9e041372, 0x3cf1ab47,
2045 0xc515fccc, 0x01309d2f, 0x54d24c7c, 0x58c9e3fd, 0xb30d6f0a, 0x1cf6c5ae,
2046 0xb852178f, 0xbac12eb3, 0x4b44c002, 0xfdb409d7, 0x926c404a, 0x3d22ae8f,
2047 0xab189d58, 0xe707e9ed, 0x93761991, 0xee389e0f, 0x1499a0d8, 0xcfe5d22e,
2048 0x06913c03, 0x29837ffa, 0xd210c53f, 0xb2f80994, 0x18262574, 0x52d47107,
2049 0xde92d3b8, 0xd814da35, 0x132b488f, 0xfdb4e313, 0xdb4bf8fd, 0x3e066911,
2050 0xb0cf20b8, 0x2a383267, 0x53f552f3, 0xc131b4e2, 0x5acf37fa, 0x91787809,
2051 0xa38e81e1, 0xadf943de, 0x2b5f7d73, 0x2a7210e5, 0x942468ce, 0xa67467de,
2052 0x1f5f52e5, 0xea2ee63e, 0x4a95ed86, 0xd0b6efae, 0xc764836f, 0x52cf3023,
2053 0xf8cf5b8d, 0xa13a6aa9, 0x6f3f96ed, 0xf748adb0, 0xf8d43fcd, 0x2d23f008,
2054 0xc93bffa2, 0x1d7ad2d0, 0xeaeb1752, 0x0bdefc74, 0xddca2ce8, 0x2b17451f,
2055 0x9185ef5d, 0xdd60278e, 0xe8b8c3b7, 0xa309697a, 0xaf8e86eb, 0x01932245,
2056 0x74e2549f, 0x7e02ca2d, 0x04eba3bc, 0x951297ca, 0x81d1c953, 0x351856fd,
2057 0x5e1fb764, 0x757d78db, 0x096655b9, 0x9989f7c7, 0x4dc7ff60, 0xdf30d5b6,
2058 0xae293d16, 0xe96c78a5, 0x9a48d3c2, 0xa01bfad2, 0xcf2840fc, 0x70e0edea,
2059 0xabe5868b, 0xbee517db, 0xdd9236ac, 0x545fac74, 0xf29bb213, 0x4369e597,
2060 0x4bb68b95, 0x147fd2a6, 0xa2dbed2f, 0x453e0156, 0xbce67dbd, 0xdd1c604f,
2061 0x802df64d, 0xcd35d98f, 0xfb5f877a, 0xe01f30ed, 0x579b1d13, 0x454b187b,
2062 0x45ccfb7f, 0xef1e209f, 0xbcdd20f2, 0xdb0160f0, 0xe1f6fdb1, 0x1fd21e4c,
2063 0x72c3ac0d, 0xc5cb0ebe, 0xae53ab7a, 0x04a64937, 0x63f9468d, 0x5aa0b941,
2064 0xc67a957f, 0x17ef844f, 0x4ebac4d3, 0xfb42d089, 0x64535953, 0x1fbec35a,
2065 0xa64248a5, 0x64b2c91b, 0x21a33f9a, 0x7175e501, 0x1997b3a4, 0x0cd23ce9,
2066 0x0ce489fb, 0x5f862f97, 0xe4b4bf8a, 0xd93e312b, 0xa9ed6fc7, 0xf6cf384d,
2067 0x81a63f55, 0x786f2ebc, 0xa875e507, 0x191f3979, 0x48f38516, 0xd6e0fb60,
2068 0xd9391b6a, 0x059787d3, 0x428f3666, 0x0f40acb9, 0x313664f2, 0x7ea7e81b,
2069 0xc3d3fba4, 0x57b95c28, 0x6f285c47, 0x93901a6c, 0x9c63c397, 0x7e2c435d,
2070 0x72612df2, 0xf0c96217, 0x688e49c1, 0xdc5c9c05, 0xb53e514d, 0xff22bbaa,
2071 0x147d45ba, 0x1ccee9f9, 0xf963dc05, 0xebf94510, 0x7015f26b, 0x536e67ef,
2072 0x35c1bf94, 0xc2770141, 0x9e3f202f, 0xca4e5d97, 0xbfae37a7, 0xde7f515b,
2073 0xbf4859be, 0x895ebe3a, 0x4994d6d3, 0xd05b30f1, 0x80686e9f, 0x670e52c7,
2074 0x68a3ded5, 0xb725b89f, 0xe1cfcb44, 0x69bb31fc, 0xf94258ee, 0x897d6fa3,
2075 0x67221fa2, 0xd28e30ca, 0xa18912ed, 0x46a73eac, 0x7bcc4fb9, 0x37170946,
2076 0x992cbe3c, 0xf407ea04, 0xdb4b4327, 0xac5d2129, 0xf5a8dfa0, 0x11519e84,
2077 0xdd0fc8b1, 0x57c63748, 0x79303e6a, 0x074861f1, 0xf4f5e83e, 0x3e3e01b0,
2078 0x19ebe2f0, 0xb9d5f109, 0x7b8e07b7, 0xee3a36de, 0x18fc40f4, 0x10fc9512,
2079 0x43f25166, 0x1f928678, 0x7e4aac22, 0xe4ab9ae8, 0xa3be3507, 0x20fe4a6c,
2080 0x105ffa1e, 0x568cc77c, 0xbca94df2, 0xefe00f72, 0x5f9e7872, 0x1fe90abf,
2081 0xf0a987a0, 0x1af01e3a, 0xff6bc3ee, 0x2625b6dd, 0x61df660b, 0xe478041c,
2082 0x197620f8, 0x046c52e5, 0x3e561dea, 0xcca7a14e, 0x107ae288, 0xd69fa76f,
2083 0xf7d613bd, 0xa049c932, 0x967fd09e, 0xdcd3bae4, 0xc639df14, 0xd520a02a,
2084 0xa2b3ec6f, 0xd32c1ca8, 0xdf21b3bb, 0xefc1ef4f, 0x417bd2ad, 0xa7411ef5,
2085 0x7281c439, 0xa61f0025, 0x2f50f427, 0x3f40ff80, 0xff8411ed, 0xed077ea8,
2086 0x5179f256, 0x7234b93a, 0x06a4be20, 0x0d911dc9, 0x72106cd3, 0x3fb171d6,
2087 0x157ca366, 0x4a0da2f8, 0xe84772fe, 0x817da28f, 0x448f211f, 0x255206bb,
2088 0xab7f0227, 0x50c913e4, 0xa9371de2, 0x223ff841, 0x35e80bd8, 0x416f9bc4,
2089 0x0899037e, 0xbc4de94a, 0xd30f723f, 0x06a48d4b, 0xb242b2e9, 0x7f69972e,
2090 0x4be975f2, 0x7f4ba508, 0x64ffd533, 0xa69b42d8, 0xd18d77c0, 0x773ec329,
2091 0xfe60b91d, 0x3f5a06ea, 0xc5f95d61, 0xbff2d098, 0x5b8d8dfc, 0x281f549d,
2092 0x2464f4d9, 0x5afaf4a1, 0xa56f135b, 0x2ed6cbf5, 0xb4d1b48d, 0x7d44eb45,
2093 0x3c976bea, 0x7f6415da, 0xed8a3f7e, 0x264274df, 0x7c153f90, 0x795fa72a,
2094 0xd7ac1c6c, 0xccead6ef, 0xb9522d32, 0xd036e0de, 0x375151f5, 0x46c92c7f,
2095 0x8fc199b8, 0x54f8037c, 0x5e4a1b9f, 0x82de327a, 0x5933a3fb, 0x3ba90893,
2096 0x62b4d099, 0x81463fcd, 0x3a49567e, 0xd4b8c196, 0x1fffa0f5, 0x595afee8,
2097 0x77d4cf2b, 0xe11e720d, 0xb5d05aeb, 0x6fb1eeb2, 0xcdf848e4, 0x557e07a3,
2098 0xbd062f97, 0x3b67ea8e, 0x89bb3c84, 0x45eb04dc, 0xe2b883e0, 0xdf93ef50,
2099 0x99bb2178, 0xf66badc2, 0x787e4a47, 0xc421e422, 0xaced674f, 0x0969bcbf,
2100 0xaa36874d, 0xfe5e90d7, 0xcf585cf5, 0x9ee12f52, 0x5a581a4a, 0x0e4773a6,
2101 0xb654aca5, 0x687a874a, 0xaebfc6d9, 0x33c533fb, 0x5eb06639, 0xdd2fdb4f,
2102 0x43c7f6f8, 0xa6bfbe40, 0xa6cb1d8b, 0x7de29261, 0xffa4a974, 0xe8f8e516,
2103 0xdbfaf250, 0xfb164b7a, 0x8fb460fe, 0xedafa51e, 0x40ac93d4, 0xeed4147c,
2104 0x414c7bd4, 0x3cdb52e8, 0x1e02648a, 0xdd03d27e, 0x9121debf, 0xf820f484,
2105 0xa476f55c, 0xe909e383, 0xa5e4e9c8, 0x5cfabd5b, 0x412bf4c9, 0x2bbe7527,
2106 0x0afa8cca, 0xca7a87b4, 0xf6ff1b1b, 0xf14fc526, 0xcc2b0627, 0xf76ff8bf,
2107 0x4e3cc245, 0x5f18ab69, 0xde34b0bf, 0xd62dfb46, 0x98cde339, 0x2fc5efb2,
2108 0x6df91afe, 0x8ebf87de, 0xd93fa827, 0x38b93492, 0xdf9824cf, 0xc4efe79c,
2109 0x0e25cdf9, 0x17e2bbe4, 0x9fe83b64, 0xf464b5e7, 0x45d6416b, 0x175b3441,
2110 0x15d356a7, 0x4a77e74d, 0xf38044cf, 0x8b5aeca0, 0x517bd287, 0x28dafc18,
2111 0x8402ffd6, 0x9d191bcf, 0xf86b45ba, 0xdf4ba2ba, 0x3cd75f9f, 0x39f404d2,
2112 0x004b6a9d, 0x6892af3d, 0xd21f1c9d, 0xfcaeda45, 0xa3026161, 0x8568b10f,
2113 0xa8f2a47c, 0xf943be00, 0x2c2d9d26, 0x5c8f515b, 0xbff5f74c, 0xc74ff790,
2114 0xd0f405dd, 0xf5c1f153, 0xa668caf2, 0x269fd327, 0x7e5fc7e2, 0xf7ad9beb,
2115 0xf5b28f35, 0xabbbd62d, 0x7fe43468, 0x1fad887b, 0x839c97a8, 0x602772e3,
2116 0x243bcefe, 0xe2060794, 0xd7aeb60e, 0x56baf8e8, 0xa13e0be6, 0xb9c2d6e3,
2117 0x842fcbc7, 0xf14e6f9d, 0x27dcc8f3, 0x7dbf3d68, 0x8bfa12be, 0xac4f6c0c,
2118 0xfd7c79db, 0xf7cd1cdf, 0xc9febe5d, 0xcf4171f3, 0x5b73eabf, 0xeeb5ce99,
2119 0xe95eb0cf, 0x605a74fa, 0x30eceabd, 0x761b33ef, 0x5d377c7d, 0xc56a6727,
2120 0x4fca553a, 0xde2d3af5, 0xa7f236fc, 0xa99e9d7a, 0xe83e3b7d, 0xeded7d3a,
2121 0xb0664f78, 0x2bbffa75, 0xe6fe053f, 0xa7e52b46, 0xf0a18790, 0x728796a8,
2122 0xa9f105b4, 0xe7f48796, 0xc8141910, 0x04ef827f, 0x5abc95bf, 0x1dc81d7e,
2123 0xbe0a5f2f, 0xe0a5f2f3, 0x957cf53b, 0x5be753f8, 0xf9472ce1, 0xf0edbec4,
2124 0xcf4a64a8, 0x6ac906b2, 0x3dbd60b0, 0xd93c5300, 0x35231b70, 0xfd63927b,
2125 0xae0a9761, 0xa9b79555, 0xbcaabb60, 0xa9570543, 0x5c70bbca, 0xf4bbf565,
2126 0x5b81e504, 0x10f75e51, 0x3d804671, 0xad7651a1, 0xa76ca8a6, 0xeb465e63,
2127 0x47486fb7, 0x12697b7d, 0xc474dbb3, 0xfc8197e9, 0x4477376a, 0x75fc5346,
2128 0xb373f184, 0xca3223bd, 0xdcd32ecf, 0xf5fca320, 0xdae8c8b8, 0xaa1af620,
2129 0x3cfd2249, 0x62fe5424, 0x4d90bf66, 0xef408b69, 0xa0ad91af, 0x3c5ecd0b,
2130 0xcef41229, 0xe31e86f6, 0x73efd327, 0x43baa1f6, 0x903db9da, 0x49b4039e,
2131 0x38b3fe94, 0xe710b63f, 0x7ce8c353, 0xa2943566, 0xa57b3e3e, 0x4d735e92,
2132 0x9ccf510b, 0x1efd04fb, 0xe12fdf44, 0xaf3f14ed, 0x2b212fcc, 0x1d289f91,
2133 0x297760f5, 0x77cca359, 0x2ecffb70, 0x48fde7c1, 0x87b9c53f, 0x3942d5cb,
2134 0xb064fc73, 0x0995ec57, 0x836749f0, 0xdcef788c, 0x9e08b920, 0xa83d986b,
2135 0x3ca07482, 0x8569f813, 0x2d0fa0f5, 0x7cb75a6f, 0x5a01e83a, 0xf1eb6ca4,
2136 0xda68e7ec, 0xaf58f5ba, 0x71bf00ed, 0x0938ed24, 0x08ed3fb2, 0x64dda1b3,
2137 0x00cb8447, 0x3f7c6ff4, 0xa3b401ed, 0xce30ac18, 0x67df1df6, 0x3fb4df03,
2138 0x79062864, 0xecca9ed5, 0xbf1a4b23, 0xe57266cf, 0x5b57a461, 0x37e99eb4,
2139 0x99fdff0d, 0x06fae704, 0xf7d82b3a, 0xf9e38477, 0x30cdf2ad, 0xbff6c117,
2140 0xfd30e41f, 0xd0a9f372, 0x61f20713, 0x19bc9904, 0x704517c6, 0x07db953e,
2141 0xed3175ff, 0xa76ebcbf, 0x2fcd167e, 0x6ca7eb78, 0x37db0fd8, 0x4da67d33,
2142 0x5dd2b847, 0xad1e68f2, 0x61c616d7, 0x056eefe7, 0x160db77d, 0x9e423747,
2143 0xab70d98e, 0x4f0c14d3, 0x5e21a53f, 0xd13f10ae, 0xfbe47a31, 0x48fc7d7f,
2144 0x2bf28236, 0x609465c2, 0x767e3fde, 0x0ec1e41c, 0x98a9f203, 0xc5da99ef,
2145 0x6e5c7fa8, 0xfe62fdde, 0x4ae2f85d, 0xafb92de7, 0x7ff6de64, 0xe21f7a71,
2146 0x5d7aa8fb, 0xe379f204, 0x8c6f08fd, 0xaf78e2b0, 0xfeabdf90, 0x337dd1af,
2147 0xe5e47ba5, 0x7fc7fde7, 0xa68779f1, 0x9ce9befb, 0xc3b066ee, 0x13f5be55,
2148 0xe56aef8e, 0x537fa6dc, 0xba7a17be, 0x3890befa, 0xf0a5a225, 0x744f0e70,
2149 0xd2e79e4a, 0xc388f77d, 0xd2113a79, 0xdd475048, 0xcad38f27, 0x2a4b24c3,
2150 0xde132828, 0x7a071dec, 0x8aa932cb, 0x4737eca8, 0x6476d3b7, 0x940c474d,
2151 0x2d0e242b, 0x217217bb, 0x3c91df1e, 0x15f9d768, 0xb4852db1, 0x9a8ed482,
2152 0x3bdd6902, 0x97b42547, 0x923f2184, 0x9e3df57a, 0x0d11f516, 0x1de8019d,
2153 0xce2b00a5, 0xbe9f5a77, 0x8bc20722, 0xa293d8e9, 0x313f7f2f, 0xcfccd63a,
2154 0x58bd1d7d, 0xc46fd33e, 0xfbe8727d, 0x66f8e55c, 0x4ba76699, 0xf36f41dd,
2155 0x8c15c71b, 0x291e0093, 0x3ca6de9e, 0x7bfaa463, 0xd1d1dc12, 0x618fecf1,
2156 0x72ef2df4, 0x141b63e2, 0xe694d01b, 0xa9563f7f, 0xec193627, 0xae0d5b24,
2157 0xad4fd0b5, 0x1b4ddef2, 0xa1dbcecb, 0xef13d0f1, 0x421e0453, 0x3efaabf1,
2158 0x1be80665, 0x667c6103, 0x74c6f8c5, 0x29631bb1, 0xf3d47a9c, 0xd5f1a495,
2159 0xd75b942f, 0x60fa073d, 0x2b7fd33d, 0xf57bb386, 0xda326d8a, 0x0c1ada0f,
2160 0xb18e892e, 0xde177eb8, 0x1b56b4c7, 0x9eb7dc09, 0xab48eba6, 0x55fe04bd,
2161 0x371c0df3, 0xcd67075b, 0xea86a746, 0xee5896d5, 0xb24d908f, 0x3fd31e61,
2162 0xcd31173c, 0x9ede7682, 0x5e76feb1, 0xab37fdef, 0xedcf9017, 0xedef54c0,
2163 0xcce2f20a, 0x65ef04fd, 0x6d23b689, 0x1cbf9642, 0x23a3ce50, 0xa9e3d186,
2164 0xb4167b68, 0xf294dcd7, 0x2857b414, 0x06e9ec37, 0xcec859f8, 0xc40c2359,
2165 0x64e94619, 0x56b5ef90, 0xde95c9f9, 0x9cf196bf, 0xfbc2e9fd, 0xfa6567a2,
2166 0x692dedda, 0x741eecec, 0xa5bf67f3, 0x988ef4ed, 0xd3daf78a, 0x93bcec0c,
2167 0xbbb87f7e, 0x6f5f5d07, 0xf81189e9, 0xeabdd74b, 0x4e70ade0, 0xabad928a,
2168 0x32b17f69, 0x217c0919, 0xce1b1bc6, 0xe7be23e6, 0x0246b0bd, 0x8fbe22f9,
2169 0x7fd1d258, 0xb1f54d01, 0xf8c53f8c, 0xf4741446, 0xf0f932af, 0xe7e466de,
2170 0xd716b319, 0xb4c3b093, 0xec0979c1, 0xeb0e7024, 0x3db7c84b, 0x5e1f786d,
2171 0x20ec4611, 0xdb35bef7, 0x7ce146ba, 0xb66f782c, 0xb7acacd0, 0x04fcd3f0,
2172 0xa0571f28, 0xe91787bc, 0xc76658ac, 0x4341fb29, 0xe2767e9c, 0x0f5bad32,
2173 0x1fb281f6, 0x77e9c4f4, 0x9d05fc0f, 0x5cefd3b7, 0x4f4b4f7e, 0x22cc27b4,
2174 0xcc27b456, 0x9c4e1e5a, 0x3aa2e77e, 0xbd350e3e, 0x56fa71cf, 0x96896944,
2175 0x2242abce, 0xdb954bf6, 0x9f764ffe, 0x23ff1eaf, 0x70e36eb0, 0x779fb87e,
2176 0xab5c1a34, 0x9dcb03d3, 0xb8f6618b, 0x3dc51bf4, 0xc5cf07bf, 0x25e5b70b,
2177 0x8aed2090, 0x1b07e2b4, 0xa5e1f971, 0x7983d682, 0x9230fc56, 0x6f07fab8,
2178 0x66f982cf, 0x81cede05, 0x5fe81a7c, 0x4df1163f, 0xb091c44f, 0x97a95e7e,
2179 0xf13d8347, 0xd19abd95, 0x678c83ab, 0x9f679f03, 0xf5f22d38, 0x5b626e8d,
2180 0xa29e8415, 0xdb347c5c, 0x459f0117, 0xa8788159, 0x074cf7cb, 0x2469b87e,
2181 0xefeb05b1, 0xc42f9c2f, 0x19a2ebb8, 0x18762b7e, 0xdb405ed0, 0x011455ed,
2182 0x71733ddf, 0x74959b3d, 0x8d863cfb, 0x4f36eea3, 0x76d3f41a, 0x083ff72b,
2183 0xe173df41, 0xe018f68e, 0x30b449c3, 0xda4187e5, 0xb7ecc92a, 0xbe94ae3e,
2184 0xd6ac3f15, 0x102bd3f9, 0xae74ebef, 0xc576befe, 0x22f3643d, 0xe6def519,
2185 0x95fefc83, 0x62eee3db, 0x499a4cac, 0x97b02ed5, 0x68495734, 0x41dbbbc7,
2186 0xdeba22c8, 0x14b87aef, 0x97d34ded, 0x8234bebe, 0xca907f7f, 0x0912bb8d,
2187 0x77a699b9, 0x09da56cf, 0xb70596a6, 0x3f7839a7, 0xfa0748d3, 0xa85f4cf9,
2188 0xfb702fb2, 0xe541e383, 0x17e02ff7, 0xc60fd72a, 0x0e43bb72, 0xbd7901c9,
2189 0x3d39e960, 0xf8a109a8, 0xc3ca85ba, 0x8b905a9e, 0xab5b4c46, 0x157e98cd,
2190 0xf604fb6b, 0x8eb1f3a5, 0xb6ee414f, 0x52e4c87f, 0x4c73cae7, 0x418f2f9e,
2191 0x2ef2c73b, 0xd78dff6c, 0xd3ea3b58, 0x3e3efe41, 0x8fc51c71, 0xeb5a2fe1,
2192 0x9b878a12, 0xc0d3353c, 0x35e84525, 0x905aac8f, 0x127e8b11, 0xefc041d6,
2193 0x32deafb1, 0x7133ec1a, 0x00db86af, 0x5cf22b7f, 0x62b18f78, 0xe7f41771,
2194 0x0fcdd232, 0x0d8f7ae4, 0x3fb81a79, 0xb16ea1bd, 0xd76d1ba6, 0x0dd3b0dc,
2195 0x35cb0efe, 0x6b3da0df, 0xf984cdf9, 0x287ef17f, 0x6919fb3e, 0x4c13f13b,
2196 0x171d2f78, 0x50d44aee, 0xbd46ee38, 0x17ea0975, 0xe0a95f4c, 0x2c976834,
2197 0x7e0a1c7f, 0x8264fb64, 0x16b13e7e, 0x087daf94, 0x0b92bfb3, 0x0f945f14,
2198 0x8fc40c60, 0x2dab5aef, 0x92fc9f68, 0xd0fb29db, 0xce8ea1f3, 0x4f8a2be7,
2199 0x6a1ecb80, 0xebe3051a, 0xabac48d8, 0xb7d89169, 0x912df292, 0xea337780,
2200 0x13aba7bb, 0x16e31531, 0x6bd947fb, 0x3f41a36b, 0x9999229e, 0x43d7095f,
2201 0x10121f05, 0x4c9e1456, 0x8bbf9c98, 0xa8539feb, 0xe3a30dd8, 0xd35887bd,
2202 0x46dddea0, 0xf8a1a912, 0x3b50529f, 0x5299f710, 0xe7ec145d, 0xe30542a0,
2203 0x8bfa5087, 0x72ea2758, 0x81af41a7, 0xc98db8f5, 0x11758a83, 0x6bbbb44e,
2204 0xecffb03a, 0x7b1ebe38, 0xd22e3f31, 0xfd60d893, 0xbde8ec54, 0xa062e80a,
2205 0xa5e303fc, 0x9b98ca72, 0xd19cfa83, 0x7f3fe748, 0x8a5b987b, 0xd9a7a3f4,
2206 0xfa034fd6, 0x1c9484fc, 0x4a3a97f4, 0xd80447e5, 0xb8693c71, 0xeb47419e,
2207 0x7d5cc306, 0x54ebdc1b, 0xfb30dc50, 0xee0ccbce, 0x2d6761c6, 0x7978d383,
2208 0x777066e2, 0xdbddff51, 0xc743fec0, 0x621fcbcb, 0x1f011f70, 0x45b3e566,
2209 0xce0c63f9, 0x1927f911, 0x7fb4483c, 0x1843c18a, 0xd3c9fc7c, 0x0f4139b7,
2210 0x8ffae289, 0xaee783d5, 0x6b7b378a, 0xde96fdfc, 0xf3726389, 0x772b1874,
2211 0x98cc9d3a, 0x08cbf400, 0x5e55fe5e, 0x02c5e85e, 0x493ea27f, 0x266f5e0c,
2212 0x80bf37af, 0x64e129eb, 0x5bf31879, 0xba524675, 0xbde86eee, 0xc617ca1a,
2213 0xd03a7345, 0xdaf80676, 0xed11f411, 0x244b7e89, 0xe9b497a6, 0xbbd89d98,
2214 0xfdb1c66f, 0x30f3f684, 0xd293d3f6, 0x909bda15, 0x81f80fd2, 0xf39681f2,
2215 0x80f81681, 0x7c6c5590, 0xc028ddb4, 0x3fa3b9b9, 0xbeedbff8, 0xfba7cb40,
2216 0xcbe6adc6, 0xcddf3807, 0x81cec25f, 0x703d511d, 0xce1118bf, 0x403244f4,
2217 0x380f8f39, 0x8b89de1e, 0xd2f4f362, 0x7ec24125, 0xa63c7096, 0xc84d7a78,
2218 0xff79faba, 0x97e78f9e, 0xbd1fb79e, 0xd7e4326c, 0xcd9ab0df, 0xd60bd187,
2219 0x85ea3447, 0x3bda2b8f, 0x3f5558bd, 0x98702e97, 0xac0f746f, 0x311848ff,
2220 0xdab277e2, 0x9b3d2f5b, 0xc7a0abe9, 0x27ca2f96, 0x74ff6127, 0x85f78cde,
2221 0x952a5c65, 0xe3d26f2f, 0x64ad6bfd, 0xef3cbf43, 0xe00ec73c, 0x79f334f3,
2222 0x5d3cd99a, 0x87257e0a, 0x88eed23a, 0x2f63e408, 0x65edbdfe, 0x14f6f0e6,
2223 0x7b582372, 0xd1422720, 0xd34bfdc5, 0x85538c45, 0x559e2f4f, 0x84f813e3,
2224 0x32f58df5, 0xc6297c95, 0xf5a87af9, 0xfb33fe9d, 0xcaf563cb, 0x08e9437f,
2225 0xc945a7fa, 0xe975e5d7, 0x7d327b9a, 0xae8036f5, 0xf3f3e717, 0xfdc71939,
2226 0x0a485286, 0x7cce0fec, 0xfec37562, 0xfb80d9b9, 0xfd92e7fe, 0x505c5c54,
2227 0xaefc20ff, 0x47b6173e, 0x1bec09e9, 0x7b40fb6a, 0x06c9b59c, 0x0967e5f7,
2228 0x550edffa, 0x6fc033d9, 0x57c9b373, 0x295fb7cf, 0x4cf111e1, 0xc3b40cbf,
2229 0xe68a7dd0, 0xb868300f, 0x018dd73c, 0x5c203d79, 0xf0d57705, 0xe0c8c4fd,
2230 0x293b0e04, 0x2034f14c, 0x3187e459, 0x3f513af8, 0x51bf958c, 0x5f70e794,
2231 0xa208fe55, 0xfdb28784, 0xb0a9e624, 0x20ff7031, 0x78d8a0f4, 0x2e43ce0b,
2232 0x4be010d0, 0x80d53803, 0xc196f5be, 0xa08d7a05, 0xce94a853, 0x3dd82ab3,
2233 0xf0bc6a7e, 0x977e6033, 0xbb40f2e8, 0x047615ca, 0x4761568f, 0x3a348f68,
2234 0xc768aee5, 0xadf605eb, 0xf747788c, 0x32bf5a78, 0x3a7a75bc, 0xff0a1f85,
2235 0x256cfd0c, 0x258fd31b, 0xa54c998b, 0x575a95e3, 0x23df41d8, 0x16a35625,
2236 0x4aedc4e9, 0xe94bf770, 0xcbc77db1, 0x6eb3240f, 0xc18e30ec, 0xee54ae5c,
2237 0xe3bbf1f8, 0x369fffb0, 0x7dfae159, 0xf7b3c370, 0xb838be81, 0x4c8fff61,
2238 0x5fa1304f, 0x60f718ac, 0xdfa29bf0, 0x380deb73, 0x370dc1fe, 0x43f281cc,
2239 0x01e86a3f, 0x84fc377c, 0x9988097b, 0x9237c6f6, 0xb91f281d, 0x25392c9f,
2240 0xd5c19c41, 0x7c5e45ea, 0x7e8f43fc, 0x231f141e, 0xcc2e3e19, 0xc5b4fc05,
2241 0x41e65c1d, 0x8b0a62a3, 0xe9f5e067, 0xb9fd03b9, 0x2b17493b, 0x23db5dd8,
2242 0x3b6a3b58, 0x3a22d1e4, 0x787dfa3f, 0x9f811d07, 0x07e23fde, 0x3e4c1523,
2243 0x29448f38, 0x926302e0, 0x39a17ca2, 0x4b7f915d, 0xfc8a0de2, 0x14fd2d5b,
2244 0xc18c98f0, 0x5bb7f28a, 0xf8f014f3, 0xe5155bdc, 0x0a456c8b, 0x56bb9fb8,
2245 0xdeffbe51, 0x21fe657a, 0x721d0322, 0x41775a8e, 0x1b4bf03a, 0xb507359a,
2246 0x7482ed54, 0x1d0cb7f0, 0x90ec3b6a, 0xc1776a1f, 0x15876177, 0xce30f0fa,
2247 0x3b2ec22f, 0xf4b93649, 0x89afedc1, 0x959e9a5a, 0x649f283c, 0xafed1d8d,
2248 0x078e61c9, 0x473d29e2, 0x2814aa91, 0xb0ec0237, 0x33850894, 0xfc01fece,
2249 0x32a73aad, 0x2051dc7b, 0xbbbbc80c, 0x788ed022, 0xf1b55754, 0xce43ea38,
2250 0xc3a39054, 0xe62b263b, 0x8707e23d, 0x6479de62, 0xf74e8abe, 0xf342e02a,
2251 0x6fe5146f, 0xc8ac5c49, 0xa8f2d5bf, 0x2b8f4e8a, 0xcfaddbe0, 0x4ab4e8aa,
2252 0x1597a745, 0x1bbf82f9, 0x076c7db8, 0x3a68b5d8, 0x0054d3cc, 0xa5b9b874,
2253 0xdb91e903, 0x74005354, 0x16b4721a, 0x6dc035e9, 0x3bf1002f, 0x2ed56f68,
2254 0x5cf4dd48, 0x4efef503, 0xee9035cf, 0xb023e7a6, 0xcea9ed8f, 0xb56f74c0,
2255 0x5bbfbf15, 0x7be98b9d, 0x3f4c36d5, 0x698d1ea8, 0xd31db553, 0x2c5aeada,
2256 0x9ebab9bf, 0xf862d7d9, 0x0bf1473e, 0x38368c76, 0x9cbca253, 0x0db2f28a,
2257 0x5f2850ce, 0x177066ef, 0x0c29930e, 0xebe5648e, 0xf2829a9f, 0x8cf83f74,
2258 0x30bf81c4, 0xd824cf4b, 0xdd3409ec, 0x8186e70b, 0x5a89b8be, 0xe4a7688d,
2259 0xb1eb9031, 0x525fbc31, 0x4296c632, 0x5ec5d2c8, 0xc18431f8, 0x2307eb28,
2260 0x1bc1f8b3, 0xe21b6b61, 0xc61edfab, 0x97c6f7f2, 0x4173818c, 0xf330fae9,
2261 0x29747e97, 0xc0528daf, 0xe649f595, 0x88e8fd2f, 0x7654c97e, 0xe5091492,
2262 0x36c3d09f, 0x20438e48, 0x1e8dca7f, 0x1aa627f4, 0x6c2bfa30, 0x8044b16c,
2263 0x85e0ea5d, 0xcf8011de, 0x672edc83, 0x3374fd23, 0xeda79a69, 0xff7d83a7,
2264 0x124f4aa8, 0xef2941e9, 0x56b76853, 0xf413bd63, 0x3a6de724, 0x413ffc02,
2265 0x51007662, 0xa604ddee, 0x6edfb4af, 0x21e0f3c0, 0xc60e6d8d, 0x9f024811,
2266 0x149f718b, 0x11c2f7f3, 0x7489df22, 0xf9128f6b, 0xe5538e1c, 0x1d60a927,
2267 0x5f19df2b, 0x05fe748d, 0x904ff9f1, 0xca7c6a0b, 0x97a66609, 0xa0a96db9,
2268 0x50f808c7, 0xe41cad91, 0xdb3ca1c7, 0x83ef30f5, 0x17930376, 0xf5d708f6,
2269 0x0db33768, 0xfecfd3bc, 0xc3a09d55, 0x1f00777a, 0xddc4fdc3, 0x3515ca32,
2270 0x604a5ffe, 0x15f22afa, 0x0aefbb9c, 0x21cd73c7, 0x1cde290d, 0x387b5e84,
2271 0x0974ce1d, 0x277df76e, 0xf9fbed81, 0x6e37cb13, 0x85cf7b81, 0xbb74d861,
2272 0x93ea37bd, 0xf31255ed, 0x3aa96903, 0x560df2cb, 0x33f4128e, 0xd1bf029f,
2273 0xf70d8dfc, 0xcb4c3f9d, 0xdc30b67f, 0xb9967b8a, 0x6eefe20f, 0x8c5a785e,
2274 0x69bff511, 0x61f35213, 0xfdc29e1f, 0x6847a79a, 0x59bdd1e3, 0xd337a51b,
2275 0xfa9b6676, 0x2418a32d, 0xf48b6373, 0x4e2e1451, 0xa41977b9, 0xd71f3d25,
2276 0x595dd5c3, 0x40cb6be6, 0x22a72f0d, 0x5bca2063, 0x74d5fbcf, 0xc916335c,
2277 0xe51e7616, 0xf4adb8fb, 0x045de2aa, 0xf1e21fbf, 0x78091447, 0xf1cbdede,
2278 0xe5edea2d, 0xe0482af8, 0x245922f7, 0xb8aca2eb, 0x0125b8f7, 0xbda63dee,
2279 0xbdc42bdf, 0xeb9f3288, 0x59eb1fbf, 0x75eba5bf, 0xb9104f2e, 0x9d812fbc,
2280 0x89e90f9b, 0x9d55ee0d, 0x277db377, 0x87b9f27b, 0x67f9d206, 0xe8359837,
2281 0x7ca33457, 0xb3a1d00b, 0x4751d39e, 0x4dfd61ea, 0xecfcce74, 0x96261230,
2282 0x5e1fc7f8, 0x36b67f6e, 0xf7fc0b99, 0x7b1e01e7, 0x9cfeff81, 0x005351db,
2283 0x8fd8b0fb, 0xbba83dc5, 0x03ef98ba, 0x77bf2855, 0x78422f57, 0xd313b54f,
2284 0xf9cbd5bd, 0xf983503e, 0xc33f55ef, 0xdf1701f7, 0xf7e3d607, 0x98c9ea86,
2285 0x6076a8ee, 0xbd8ba63a, 0x1df4e402, 0x47c60746, 0x81acfdbe, 0x675e7dc0,
2286 0x47e30183, 0xf1788ae8, 0x538858b9, 0x58579832, 0xd495e302, 0x1f978afb,
2287 0xb3fb7e54, 0x0b7ed8bb, 0x99e378fd, 0x2ebd3f40, 0x241d3f34, 0xdf390e5c,
2288 0xd0743945, 0x07d6e42c, 0x7808b60c, 0xa2ad833f, 0xf72807fc, 0xbe78da0e,
2289 0xed833f73, 0x601c9f3c, 0xefc043b0, 0x944ab831, 0x73dac03f, 0x063df80a,
2290 0x4df288d7, 0x7831760c, 0xa21fd3ed, 0xd223cc5c, 0x056f586e, 0x2091f4c6,
2291 0x79cd0b62, 0xdd9d61bb, 0x24733892, 0x826333ac, 0x56fcf905, 0x00dde2cb,
2292 0xa558c98f, 0xcdba1305, 0xa861efd4, 0xa45b1f97, 0x53237a85, 0xea187dee,
2293 0xb8f9ea8d, 0xe8debfd6, 0x061ed7cc, 0x9575ac78, 0x236bf416, 0xbe81c5c8,
2294 0xf22c0476, 0xe2213ec5, 0xd836faf0, 0xaeca3f71, 0x247ee3b7, 0x477f9cf0,
2295 0x9c3352d1, 0xb325ea03, 0x43b8e304, 0x404f06f2, 0x05c5630c, 0x1e291aba,
2296 0xe13c12ea, 0x2b3ce98b, 0xf0821e01, 0xd97f8b63, 0x109dd5fd, 0xc2383f64,
2297 0x2be807e5, 0x23ffb445, 0x3f835d74, 0x4bc70442, 0x88ccc365, 0x755e7899,
2298 0x189e8044, 0x0490f5c3, 0x2dfe6948, 0xbfcb1d3c, 0xef6c941f, 0x30f8bc82,
2299 0x03b79f81, 0x1861cde5, 0x73279507, 0xe40238d9, 0xcb9f328d, 0xdf62239b,
2300 0xb2e2c01a, 0x8b0d49cb, 0x7c4cbee7, 0xb8dc405f, 0x84a71e2a, 0xa5b1eed4,
2301 0x6f178b07, 0x2e2f1a0a, 0xfd031bfc, 0xb0b9f96d, 0x93cf930b, 0xc3d17641,
2302 0xb9686760, 0xab971dfb, 0xcca0f0a1, 0xe0e285ff, 0xf90e2389, 0xbc3c5423,
2303 0xf9c08be0, 0xb6f3b0d5, 0xea9fe196, 0x81c4c69f, 0x8823bf20, 0x6794ab1c,
2304 0xcf212f87, 0x97f1f2d4, 0x6693bb92, 0xfdc1a794, 0x98b91043, 0xcb54e30a,
2305 0xc93e6745, 0x7505fb80, 0x0a68f42a, 0xd3de213b, 0xed0c23b9, 0x8e31f514,
2306 0x0fd0448c, 0x83be3bf3, 0xeb122d78, 0x371c3c41, 0xf6846e39, 0xbff33d25,
2307 0x2dcdf110, 0x753f7d5e, 0x7923c62c, 0xfb0a7bf5, 0x9efdf7e9, 0xf20b1d49,
2308 0xdec9bbad, 0x1921da1f, 0xc85d1fcc, 0xbef1508f, 0x3ed91343, 0xff92981f,
2309 0x8e5838b7, 0xae7a369f, 0xf4e74dda, 0x62bf86ce, 0x57d9ccdc, 0x56c1c79a,
2310 0x265dba5c, 0xb68f8a46, 0x0dc4110d, 0xe52d1be7, 0xd4969a3f, 0x2b8c36c9,
2311 0x4d07bad2, 0x5bd7f08c, 0xe974ff98, 0xcadc08a6, 0x5c1b364b, 0x92fd6963,
2312 0xd1b327ad, 0x0ea1f5af, 0xbe730fbc, 0x22d75922, 0x13d93cfa, 0x1b594fc1,
2313 0x353e4edc, 0xad87e991, 0x8327c2db, 0xbf5a56bd, 0x25deed13, 0x707493b5,
2314 0x4dca2a0f, 0x3e21d44c, 0xa7b43968, 0xb8965f3b, 0xe41eeb1e, 0xfc2caf7f,
2315 0x665f5bb7, 0x7a92a976, 0xc60c2b9d, 0x36b5feb7, 0x3929c788, 0x4dfb406a,
2316 0xf46ffae5, 0x4d82c740, 0x1f01231b, 0xd932f595, 0x550fbcad, 0x97ac41c6,
2317 0xe3f006dd, 0x7f472baf, 0x23370a6e, 0x1e3c1b5c, 0xfafe72e8, 0xb71a9ba5,
2318 0x4b0a293a, 0x12297f5f, 0x374e29e2, 0xbc048dad, 0x192f76d3, 0xf7101487,
2319 0x25e8fb50, 0x134e1ee3, 0x134b03c6, 0xeb237155, 0xcb71b863, 0x3fdfc83d,
2320 0x274787c9, 0xf3c6f3a3, 0x5e5c422f, 0x2f33e6eb, 0xfecb78c2, 0xf045ee79,
2321 0xc23b26cf, 0xad0f60cc, 0xc630e57c, 0x7f7a8935, 0x627a6449, 0xe12fcbdb,
2322 0x31db6a3d, 0x35b7afa6, 0x6dbe429e, 0x78c7ed7b, 0xd85af388, 0x0efe8858,
2323 0x2414b70b, 0x02e72090, 0xbadf0291, 0x4d1e20ae, 0x755daf4d, 0xfc8fd0bb,
2324 0xe837a52c, 0x9638dea1, 0x171672da, 0x2bf1e164, 0xfdc7821b, 0xd4abc405,
2325 0x1c3f1c4d, 0x3a75e2ec, 0x415c85ab, 0x4a21cadc, 0x4057bec7, 0x728f0dbf,
2326 0xf4e0fe7f, 0x50bf0b3b, 0x2a26353a, 0xd7ce56e3, 0x9fcbf9cd, 0x262eaf21,
2327 0xfb8adc64, 0xe226f00a, 0xda24570a, 0x6c3c82f6, 0xc62afcdd, 0xc6dd0109,
2328 0x6db689d2, 0xf1069f3c, 0x8eba2d98, 0xc1efdce9, 0x25acf70c, 0xfd70478d,
2329 0x10f96db4, 0x8f08f6e3, 0xde236bef, 0x258f161f, 0x89ae79f1, 0x1c2ef160,
2330 0x030f10ff, 0x3bf4d0f7, 0x7c617b8f, 0x4261e22c, 0x4c5cc1c5, 0x2df6ceec,
2331 0xbe58ef1e, 0x2b8f38e6, 0xca4bd1f1, 0x5f353a05, 0xe048be32, 0xb8780cc1,
2332 0x2bae3fc9, 0x3791bc78, 0x0bd38ffe, 0x5cf107e8, 0x0a2db8de, 0x3a58430f,
2333 0x83c88242, 0x1e2c55b6, 0xe3ff7d4c, 0x3843cfa3, 0xd152ffaf, 0xf433cc59,
2334 0xd3ad9239, 0x6aff8dcb, 0xd12673f1, 0x127388a2, 0x10bd6a78, 0x26a78e5c,
2335 0x67eafdb1, 0x00b6b7eb, 0x092536fd, 0x66badbf4, 0xe62b7e85, 0x05754adb,
2336 0xafadef90, 0x960c77b0, 0x3942eed5, 0x141796ae, 0xf760b62f, 0x98937d0d,
2337 0x67a8aa9c, 0xe6eb44fb, 0xb6899708, 0x6df7fad3, 0x1b15cfc8, 0x8fb0f59a,
2338 0xbaff59ef, 0xb317f99e, 0x84fb03f5, 0xadfc6fcb, 0x8d99db7f, 0x09fa1b72,
2339 0xbce1d742, 0xe086ca9f, 0xf86e54fd, 0xa94fd146, 0xfccf56b3, 0xdfdd2e8d,
2340 0x126dad69, 0x49ba77b4, 0x7269a607, 0x6df996ba, 0x24b7fba9, 0x4abdf8e9,
2341 0xa8f7d70d, 0xc83f47bc, 0x9c271e61, 0x51c3735b, 0xc5e6b63e, 0x35a45da3,
2342 0x6965af55, 0x7fff842f, 0x935bfbdb, 0xbfac8d72, 0x371f1851, 0xd6e8c62e,
2343 0x8073f5d0, 0xaf513fbf, 0x00fff677, 0x8707cfee, 0x78e3dfa1, 0x4dbefcc9,
2344 0x6827bc0a, 0xdf3537dd, 0x5f781d92, 0x91912ad0, 0x65279512, 0xf0a59acd,
2345 0x0fef6aed, 0x477d16ca, 0xa19d1de0, 0x78102e8b, 0xefeae7df, 0xb3a29a13,
2346 0x70b7602d, 0xfa6d812c, 0x829ad6a6, 0x597216ae, 0x0edcef3f, 0x67b012d7,
2347 0xdec0b88c, 0xba4a18b7, 0x4daae158, 0xfccfddca, 0xbeaa79be, 0x31ae9877,
2348 0x83ddf4b9, 0xe7909fbc, 0xdc82481e, 0x867b8837, 0x8ac730e4, 0xf71081a4,
2349 0xc01beecf, 0xe4f915f3, 0x3fa6c7b7, 0x3081e780, 0xe71573f4, 0x27f58d99,
2350 0x9fac60e3, 0xb93dc537, 0x34af7e9d, 0x79f8877f, 0x8f9f8932, 0xf28ac4ac,
2351 0xf50f7e4b, 0xfb25cff8, 0xfb8a49b3, 0x08b9ef58, 0x63efabbf, 0x8cee7f85,
2352 0xec276597, 0x0dbf85a3, 0xc608781b, 0x03961751, 0xc31fd8e3, 0x980641fd,
2353 0xf1401f6f, 0xf5cb7673, 0x5b3fe039, 0x9eefb5e4, 0x88bcbd47, 0x338963db,
2354 0xafd876f3, 0xd7bd848a, 0xdcf961e9, 0xd9febbde, 0x3ac3b7de, 0xa1c1fe14,
2355 0xa2c56de4, 0x421f9137, 0xda12cbe6, 0xa6e4c939, 0xbd3f22b4, 0x072e4df9,
2356 0x397efdc4, 0xa78b0bf7, 0xf68dc8d3, 0xbc5791f9, 0xba46e611, 0xcec4d97e,
2357 0xe976dbc5, 0x09af1d99, 0xa78f21cf, 0x7c02de3a, 0x81da2c55, 0x762626f8,
2358 0x6c96396e, 0x1d31fee6, 0x0eae5099, 0x6eb027ce, 0x7da184b6, 0xd1eb4136,
2359 0x2ab8e95b, 0x8bf4128e, 0x33c7c638, 0xd40be9a8, 0x70e6bff7, 0x37e67ad7,
2360 0xd7c3c6a1, 0xf1aa1149, 0xc60c37bf, 0x2231f02f, 0xfdc2d49c, 0x958f9d30,
2361 0x98aac7cf, 0x814fd78f, 0x6ff74bd6, 0xebf0a2d7, 0x5b2af312, 0xdffc49d4,
2362 0x1c5d6ad3, 0xe311df7c, 0x97dbdf56, 0x840f7698, 0x2ae4a37d, 0x02a7fafd,
2363 0x3e01c46f, 0x871eaa59, 0x7ee32d3a, 0x17efea1d, 0xf67dc492, 0x7fae3b2f,
2364 0x69bd7bb7, 0xf9153b55, 0xbbed1633, 0x713f7ba2, 0x75bff71f, 0xdeea17ff,
2365 0xf66ec1ef, 0x8e946ecc, 0x29fcdfe3, 0x9df108f3, 0x1105eddb, 0xbe51c718,
2366 0xc8156135, 0x7e470fe5, 0xc2f60f14, 0xf71231fd, 0x1cb4bde7, 0xf7bb52b9,
2367 0x717bd567, 0x393f625c, 0x5846ed51, 0x3a9f076d, 0xa7bc31e2, 0xdb2dfc1e,
2368 0xb05e8637, 0xf2c9b91d, 0xc231edf3, 0x32ec230e, 0xd4cf3b6a, 0xefe4666e,
2369 0xec29bfe9, 0x9417fcca, 0xac472e7c, 0xffdc83d1, 0x17ee7cb9, 0xd65d3347,
2370 0xe2877b40, 0xce89bda1, 0xb0475ee6, 0xc23de51d, 0x7b8e2e98, 0x73134e80,
2371 0x88863f99, 0x5b942a5b, 0x7a049c9f, 0xfb8c934e, 0x7ddfc2d7, 0x2ce7b7f4,
2372 0x34a8f481, 0x131ca277, 0x5eeb1774, 0x86a543f0, 0x14e7b1f9, 0x097fd058,
2373 0x57d811e4, 0x0d34746b, 0x299ee742, 0x3c600bf9, 0x0e3afded, 0x8abf024f,
2374 0x669dff2d, 0x09aebd41, 0xb39779cf, 0xbffd80df, 0xd73b105b, 0xe8393cb2,
2375 0x298977fb, 0x6aceff4c, 0xbbfbb0d6, 0x7aeb92f9, 0x347973b0, 0x39acaa88,
2376 0xe0192ee9, 0x559f963a, 0x2892e51e, 0x8c38359c, 0x851bdfe5, 0x88d3df71,
2377 0xf3fb0747, 0xa60af00c, 0xc1624ce9, 0xf1b11674, 0xba3ae5f7, 0x9cfeb44b,
2378 0x83f32306, 0x309e9e25, 0xfa10ec9f, 0xcc6eceef, 0x3bb7d3be, 0xf37ddf93,
2379 0x19fc7295, 0x726eff9e, 0xef9849fe, 0x67b66ee9, 0xdd1bed21, 0x704fe2b4,
2380 0x21a2dcde, 0x1a9df7a0, 0x9bb41bfc, 0x24df7a8a, 0x8dd8bfe7, 0x3124dbd6,
2381 0x23674aff, 0x1d22a78f, 0xb6f6fef1, 0xd60b93d7, 0x02af7b40, 0xae3c815f,
2382 0x29be462d, 0x935c3332, 0x457cec91, 0xca5da5eb, 0xf857d20e, 0x5c87c2f7,
2383 0x86e117ec, 0xfdba4f3f, 0xbeef3a61, 0x073dfa1a, 0x02d8e5c6, 0xf74beae3,
2384 0xff8c1373, 0x40a71e05, 0xdee0d2aa, 0x068bde6c, 0xc79bec0d, 0xbf03bca8,
2385 0xa7e0e3eb, 0xb94fd34d, 0xdce7f63f, 0xfc19bb1f, 0x927a69ba, 0xe7482dca,
2386 0x842560fc, 0x64c8e7f2, 0x95f2235b, 0x883bf82e, 0x21e726ef, 0xb4ebb31e,
2387 0xd7678fb8, 0xfae7227b, 0x377f65d1, 0xb59a1f16, 0x5848cbe5, 0xef666d4f,
2388 0xed126cbc, 0x73b71c6a, 0x0736efee, 0xb26ef5e7, 0xe7cc24ed, 0x01c764f5,
2389 0xa3feb76c, 0x753f04ff, 0x7fde3eda, 0x4f1d4bb4, 0xf102950d, 0xa37f9dea,
2390 0xe39fcd9e, 0xd3545379, 0x69bfa80a, 0x2cc0774b, 0x2c7ee2c9, 0x0527e804,
2391 0xe7b33fc3, 0x0c74378d, 0xf8d17380, 0xff50728b, 0x3fef3131, 0xf38b3a0a,
2392 0x286ba70e, 0xcf9287ba, 0x80cc78de, 0x442e1377, 0xe22f5c82, 0xbafa9376,
2393 0x6fd0079e, 0xe04caf7f, 0x27ca23dd, 0x498efe0a, 0x48807a66, 0xf8f51ab3,
2394 0xc6a6cf5e, 0x36ce7aaf, 0xce7a1d21, 0xe4e5e5a1, 0x507a15eb, 0xff1fe0d6,
2395 0x2c58a7fc, 0x92412f0f, 0x42aac8bb, 0x629af7b8, 0x4c36f9dc, 0xb9b99a61,
2396 0x66bdee10, 0x207b4a24, 0x1f49699d, 0xe25df705, 0x232b38dc, 0xecb00f6f,
2397 0xca116b58, 0xc4583ce1, 0x814bfb7e, 0x1eee1c31, 0x39a170bc, 0x92df0146,
2398 0x7f28ac98, 0x2287a5ab, 0x8dc64c7f, 0x9faf7c8a, 0xefbfb5bc, 0x47c0777b,
2399 0xc3b07747, 0x9ca079d3, 0xb4656b21, 0x396d66db, 0x148ddb74, 0x4eeeb71e,
2400 0x9b036c2b, 0xcdb8fe78, 0x4fd82e05, 0xb00a5de1, 0x3ee4b463, 0xa09fd4fa,
2401 0x5f7b2d31, 0x74611e63, 0xebfc6b28, 0x799b6028, 0x3da1e6c3, 0x8c9de036,
2402 0xd5dfc135, 0x52c1f610, 0x65e9ecc2, 0xbbf6d41b, 0x550ecc95, 0xe54faca7,
2403 0x3c827fd1, 0x0ef5bbea, 0x6e97f833, 0x3763fc1a, 0x64d6e790, 0x284bbc65,
2404 0xbff2f17e, 0x1fe03964, 0x17e6a1e7, 0xe9120761, 0x6e2c83b8, 0xc5e56ae1,
2405 0xf85e403f, 0xe57917c5, 0x31fb9e98, 0xc41278f1, 0x3f1f0f47, 0x628e4b4f,
2406 0x5aaf67e5, 0xd0b8ef0a, 0x13c4277c, 0x4b9db291, 0x85efaec1, 0xf32b3617,
2407 0x2996941f, 0x95d387e0, 0x65bccaf0, 0xad43f5fe, 0x66fa8abb, 0xefca83bd,
2408 0x39d8278a, 0x639f7024, 0x992ee8eb, 0x6fdb0554, 0x4a31fe44, 0x7853f40b,
2409 0xc70bed83, 0xfef47aba, 0xc96527fe, 0xbb3b4f4c, 0x7ddff1ed, 0x6de27607,
2410 0xce46fd04, 0x5cfb3146, 0x8d29dd76, 0x177ae406, 0xb36caf86, 0xec7e0347,
2411 0x4ee1c5ed, 0x9cac83f0, 0x24fe811f, 0x866ce17d, 0xbfedc9e7, 0x7843d1b7,
2412 0xbf09efe5, 0x03ff0f57, 0xd13f379c, 0x46fb1468, 0xff9589bb, 0x6cede48f,
2413 0xeb67c8df, 0x83d03a63, 0x974261cb, 0xe252e566, 0xeeb0cb95, 0xbf003e60,
2414 0xf78edcf6, 0xd37b009f, 0x5a3eb63e, 0x29e3fb89, 0x4cd8bfb8, 0x95a3ebfe,
2415 0x7e77b2d4, 0x427dec2d, 0x7218bf71, 0xd1aeecbd, 0xbf8dfbc3, 0x2279baf4,
2416 0x843bdf99, 0xc7071f5e, 0xdca93e50, 0x3b1afcc6, 0x4aefae1b, 0x804bd6fc,
2417 0x068cf69e, 0x6dc05af9, 0x3bfdfc0d, 0xd8a17c55, 0x17b58837, 0xf78b13fa,
2418 0x3ae80f3e, 0x541fa026, 0xc6fd16a3, 0x092ce816, 0x6fea9751, 0xfc5886b9,
2419 0x68dbebfa, 0xe62df940, 0x73666ed1, 0x3e78dbed, 0x8171de1a, 0xc3ea3174,
2420 0x87fd8a35, 0x58ba73ee, 0xec455810, 0x6370ec5e, 0xe1d03e42, 0x199c44b0,
2421 0x309a9839, 0x35fb9bce, 0x27fc244d, 0xffeb4331, 0x6fd0b6ae, 0xf3bc6cef,
2422 0x3e87d07a, 0xcee7bbae, 0x24fbf401, 0xe29b9778, 0xfb7740f7, 0x81df9834,
2423 0x73f4255f, 0xfa91fc2a, 0x77f7acfc, 0xf307e50b, 0x65dd80c6, 0xfe83312a,
2424 0xfa665e3c, 0xad8b7916, 0x2a37212b, 0xe868a6a5, 0x09e4f5ff, 0xbce99287,
2425 0x01fd1613, 0x3df569f5, 0x5bea95f3, 0x26b0f285, 0xebede81b, 0x6e7f1625,
2426 0x31577c65, 0x9393ccec, 0x7d508e40, 0xf28ff41e, 0x1ef89dfa, 0xe6dcfa81,
2427 0xe7d5abd5, 0xf38dabef, 0xedcbd00f, 0x7071c96d, 0x7877388e, 0xcfd40912,
2428 0xcd56f27d, 0x021f5477, 0xdc36b479, 0xa6aef8c5, 0x6fce94ad, 0xb364dac1,
2429 0xf6e78a13, 0xa2d6f162, 0xdba7f0fc, 0xcbf3437e, 0x83370a5e, 0x9d30bdda,
2430 0x818de138, 0xa37aab85, 0xdeafbbbd, 0xd006eaf2, 0xa1d65eaf, 0xe06bf45d,
2431 0xbd7f0a1d, 0xd81706f9, 0x2c69e783, 0x8cf7847f, 0xf9193ac9, 0x060bd4ed,
2432 0x1fe75fdc, 0x2bfb81e9, 0xa50b23ac, 0x4254a9cf, 0xfcdeb4cc, 0x5db193d7,
2433 0xaf7625f9, 0x02537f3b, 0xfa0aa1c6, 0x8610bcb6, 0xd9c591f1, 0xf4dcbdb5,
2434 0x47449edb, 0xbc1c4a54, 0x975ae7ff, 0xf054f144, 0xc01f4fd2, 0x537f36be,
2435 0x47cbd21c, 0x61fbe0e7, 0xb60f4367, 0x84be39ce, 0xef05fedc, 0x0653120f,
2436 0x87895f82, 0xeece77bf, 0x7db8720f, 0xd977cd4e, 0x7e32ffbc, 0xd840c3ce,
2437 0x67cff058, 0xdca24cf1, 0x628d14a8, 0x4f942d3f, 0x3e076c54, 0xf9e037ad,
2438 0xb82c35b2, 0x0a486a9d, 0x8c2b57db, 0x49ec2adf, 0x507e8b15, 0x322b13d8,
2439 0xe7bbde09, 0xbff4b12c, 0x71f7a697, 0xd9c4a7fc, 0x4a7cc387, 0xfadf1f6a,
2440 0xf9f1e21e, 0x7e813ffb, 0x3bd89af7, 0x7c31ef6f, 0x6f02ff0b, 0xbe0ec67b,
2441 0xf429570e, 0x476db6cb, 0x7f781db2, 0x382bfc77, 0x3c6d9f0f, 0x25a654f2,
2442 0xc7cc7ec8, 0x658cec2b, 0x60fede30, 0x4b8db487, 0xb473b3f1, 0x5efc1d7f,
2443 0xeeaff44b, 0x53646cf7, 0xb6dbbc36, 0x07698200, 0x46cff2fa, 0x3ec36537,
2444 0x4437fc2b, 0x14cccedc, 0x4a947fee, 0xfbc44352, 0x0b8949cc, 0xdf83ef1a,
2445 0xe7de3aaf, 0x19f78b3c, 0x7de333fe, 0x0c9f393a, 0xef1e0988, 0x5fcf04f2,
2446 0x43d96a42, 0x43ee5c72, 0x077f0dd8, 0x67bc5658, 0x8899e5c9, 0xc0da18f3,
2447 0xb943ffec, 0x6364ab1f, 0x88432e71, 0x7aa7b59b, 0xe5640597, 0x89119054,
2448 0x113ae237, 0xc606fdef, 0x7be13425, 0x0e9337cd, 0xacc46d4c, 0x1ba29485,
2449 0x8ec491d3, 0x855228e9, 0x835268e9, 0x16a46de9, 0x09a4b1d3, 0x8dc7d253,
2450 0xff78c7ef, 0xf3adc67e, 0x0cffb034, 0x6f5c1498, 0xbfaf837b, 0x5243e04b,
2451 0x9578afbc, 0xd84518f8, 0xf121c5fb, 0x7e819292, 0xea2f0258, 0x9c31bfbf,
2452 0x119db078, 0x80f651b0, 0xef0594f3, 0x0d880a4f, 0xc42bc2e1, 0xa1c7ae47,
2453 0x2532f665, 0xe0e9025e, 0x1bd4854c, 0x19ee4607, 0x2b038ca7, 0x5e718719,
2454 0x5cec39fd, 0xe26ff2c0, 0xb1f79de5, 0x2824507c, 0x82ca45fc, 0x5c71fe71,
2455 0xef190f72, 0xb187261d, 0x6ef17ab8, 0x4230e4c9, 0xb5bf809a, 0xcf9438ce,
2456 0xde297a8b, 0x392530f3, 0x355ca00e, 0x142d23ba, 0x16670b7f, 0xb1c6ffa2,
2457 0xdb8dcb38, 0x7e3c5f25, 0xd75b0a4b, 0xc4aaa547, 0x8f1e743e, 0x77dfa7e4,
2458 0xbfafba7f, 0x04e7e82b, 0x3f755bac, 0x3c3ac46f, 0xf6313fd0, 0x2cfcf3c2,
2459 0xde6cafbe, 0xaadb343c, 0xaccd7e81, 0xdd67dfdf, 0x32cd3f77, 0x424edaa7,
2460 0x821496f9, 0x5da44deb, 0xf02dece2, 0x893bc45d, 0xbf33edef, 0xbe26eadf,
2461 0x531faa38, 0x5ca1671c, 0xd693c6a5, 0x571d0e5f, 0x5c46c4b6, 0x655be47a,
2462 0x2e3a993c, 0x3df7b68b, 0xee52abcc, 0xd3fc0b98, 0xfe91f516, 0xcaefea2c,
2463 0x1dc6acb8, 0x687114fb, 0xe3781d62, 0x1c593ad0, 0x438850da, 0xbff1f48b,
2464 0x7c134388, 0x10c3d62c, 0x72c34388, 0xf281cc37, 0x813a3fc3, 0x4e236871,
2465 0xda1c7878, 0x9a1c6511, 0x159ffbed, 0xb1de2687, 0xbd85b058, 0xdb80bfa7,
2466 0xfd060077, 0x5f7894e2, 0xc4579f86, 0xdf7ca4b9, 0xdf9eecdb, 0x041bff49,
2467 0xa7ec907e, 0xe859f9f8, 0x0fe0122f, 0x0cb5c279, 0x0fe01dc6, 0x09aff2a9,
2468 0x568277fd, 0xe9fbf506, 0x2bcfca93, 0x5c219f7c, 0xcbc7997f, 0xaec0fcc0,
2469 0x8f51a0b5, 0x1782d1fa, 0xfe82b3ee, 0x64d520b4, 0xf2b77945, 0x514be43e,
2470 0xfccf3c9e, 0x9b7ac473, 0xdea09cbf, 0xac4f3de5, 0xeff0d833, 0x404bac23,
2471 0x3e7bcafd, 0x0814f6e7, 0xebfb84d3, 0xdd1d514d, 0x536ddee1, 0xf4158663,
2472 0x5b220fbb, 0x71b14256, 0x5e9f0ce1, 0x0e98797d, 0x9603aff5, 0x74888298,
2473 0xf3b13adf, 0xf99e4275, 0x3af98335, 0x7bb136b3, 0xf6a39c85, 0xdc0b4882,
2474 0x84fbb02b, 0xefc12d41, 0x4ae7c7a9, 0xc08a7b8a, 0xcb16c9f7, 0x7fb8255d,
2475 0x6a10f760, 0xbfb8bd3b, 0x2985b22e, 0xdd423fee, 0x0ef38b67, 0x1e89efdd,
2476 0x118d7bf6, 0xc48337fd, 0xf7233dd3, 0xf663bdf0, 0xf3c0e48e, 0xa6c61dd0,
2477 0x4fabe034, 0x53731c63, 0xcb6e20e3, 0xce39416a, 0xf17ceae3, 0xbca06f40,
2478 0x073ef114, 0x20e32da5, 0x54deea1e, 0xa3d40547, 0x067b30d3, 0x9947def9,
2479 0xc5f27b99, 0xa7682dd7, 0xb7f54caf, 0x3bbff3d3, 0x1e2f5ea2, 0x59e3058d,
2480 0x5095bf9c, 0x8d0338af, 0x15f3c60c, 0x8a674ff2, 0xdbf98729, 0x4adefeaa,
2481 0xdfe5576c, 0xf167a95b, 0xad89a50d, 0x59b3af4c, 0xfa6e2cad, 0x959dfde7,
2482 0x9553ddcb, 0xf428b626, 0xe621b255, 0xbea6ec8a, 0xfdae5df9, 0x5a7f6c36,
2483 0x7e0a87d5, 0x98e8b198, 0x3a66cf82, 0xb5f9959b, 0xaf7838d2, 0x1567d28c,
2484 0x35b3c7d0, 0x0b14d469, 0xf01801f8, 0xf7cbbf5d, 0x77f11a7b, 0xcf09baa2,
2485 0x9f5e628b, 0xd8451f55, 0xc651ed53, 0xa979f067, 0x704f8bfd, 0xdc1399bf,
2486 0xf704e66f, 0xfdc1399b, 0xbf704e5a, 0x7c87e116, 0x4c8aa242, 0xe47f5074,
2487 0x828f8137, 0xc23723f8, 0xc8fe90f7, 0x0a71c7e4, 0xb7e7647f, 0xe47f0b08,
2488 0x91e7a95d, 0xec9bbb8f, 0xc43b436f, 0x9ffbd1e6, 0x23f943bb, 0xeeca9fbf,
2489 0xa5503e93, 0x22f3d29f, 0xb4f1a9fa, 0x0bd95e50, 0x37ac59df, 0xcb879010,
2490 0xf1a6d924, 0xb0f18fbf, 0x16ce5377, 0x1dfc28a5, 0x8b7f962a, 0x0f7e17f8,
2491 0xd0196f39, 0xdf7ca04f, 0xd7405ec1, 0xe71d53c7, 0x1dfd9952, 0xab2e87df,
2492 0x5fbfb033, 0xbf21cfc7, 0xebf139e0, 0x718181d4, 0x77e6a114, 0x53d34e76,
2493 0xe55e7499, 0xef153b91, 0x8af18b22, 0xfa718979, 0x5f8cb9da, 0xc50ef2c9,
2494 0xf6db6b3a, 0x63e02f48, 0x9c167ef1, 0xa904275b, 0xe8c69f1f, 0x5287cf42,
2495 0xa4bfed1a, 0x7d0f9d8a, 0xffb9adf4, 0x3ec7a013, 0x509dca13, 0x2cf3d5f5,
2496 0xf10fb1df, 0xd2173ea1, 0x0b4d7679, 0x3b9fcf32, 0x6bf5abbf, 0x4e217437,
2497 0x715097e0, 0x9b250751, 0x2d77c605, 0x4b5e96bd, 0xd2d7a5af, 0xf4b5e96b,
2498 0xbd2d7a5a, 0xaf4b5e96, 0x6bd2d7a5, 0xf4e5ffe9, 0xfffd007f, 0x8000c102,
2499 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x30001131, 0xafb00408,
2500 0x521cae88, 0x11447fea, 0x992c9a42, 0x326ebaf3, 0xb6db6db6, 0x6db6db6d,
2501 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
2502 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0x7f6db6db, 0x98a102fc, 0x80005382,
2503 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x30001131, 0xafb00408,
2504 0x521cae88, 0x11447fea, 0x992c9a42, 0x326ebaf3, 0xb6db6db6, 0x6db6db6d,
2505 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
2506 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0x7f6db6db, 0x98a102fc, 0x80005382,
2507 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x30001131, 0xafb00408,
2508 0x521cae88, 0x11447fea, 0x992c9a42, 0x326ebaf3, 0xb6db6db6, 0x6db6db6d,
2509 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
2510 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0x7f6db6db, 0x98a102fc, 0x80005382,
2511 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x30001131, 0xafb00408,
2512 0x521cae88, 0x11447fea, 0x992c9a42, 0x326ebaf3, 0xb6db6db6, 0x6db6db6d,
2513 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
2514 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0x7f6db6db, 0x98a102fc, 0x80005382,
2515 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x30001131, 0xafb00408,
2516 0x521cae88, 0x11447fea, 0x992c9a42, 0x326ebaf3, 0xb6db6db6, 0x6db6db6d,
2517 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
2518 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0x7f6db6db, 0x98a102fc, 0x80005382,
2519 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x30001131, 0xafb00408,
2520 0x521cae88, 0x11447fea, 0x992c9a42, 0x326ebaf3, 0xb6db6db6, 0x6db6db6d,
2521 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
2522 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0x7f6db6db, 0x98a102fc, 0x80005382,
2523 0x00008000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2524 0xffffffff, 0xffffffff, 0xffffffff, 0x00002000, 0x000040c0, 0x00006180,
2525 0x00008240, 0x0000a300, 0x0000c3c0, 0x0000e480, 0x00010540, 0x00012600,
2526 0x000146c0, 0x00016780, 0x00018840, 0x0001a900, 0x0001c9c0, 0x0001ea80,
2527 0x00020b40, 0x00022c00, 0x00024cc0, 0x00026d80, 0x00028e40, 0x0002af00,
2528 0x0002cfc0, 0x0002f080, 0x00031140, 0x00033200, 0x000352c0, 0x00037380,
2529 0x00039440, 0x0003b500, 0x0003d5c0, 0x0003f680, 0x00041740, 0x00043800,
2530 0x000458c0, 0x00047980, 0x00049a40, 0x00008000, 0x00010300, 0x00018600,
2531 0x00020900, 0x00028c00, 0x00030f00, 0x00039200, 0x00041500, 0x00049800,
2532 0x00051b00, 0x00059e00, 0x00062100, 0x0006a400, 0x00072700, 0x0007aa00,
2533 0x00082d00, 0x0008b000, 0x00093300, 0x0009b600, 0x000a3900, 0x000abc00,
2534 0x000b3f00, 0x000bc200, 0x000c4500, 0x000cc800, 0x000d4b00, 0x000dce00,
2535 0x000e5100, 0x000ed400, 0x000f5700, 0x000fda00, 0x00105d00, 0x00000028,
2536 0x00000000, 0x00100000, 0x00000000, 0x00000000, 0xffffffff, 0x40000000,
2537 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2538 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2539 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2540 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2541 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
2542 0x40000000, 0x00088b1f, 0x00000000, 0x51fbff00, 0x03f0c0cf, 0x65e21f09,
2543 0x63e62860, 0x88237860, 0xcc2b4e2a, 0xfe9942ce, 0x0c0cccf3, 0x32f88117,
2544 0xe2055f10, 0xe9a48cd3, 0xb045e2b7, 0x30327377, 0x7df90358, 0x9b8b5a40,
2545 0xc8014181, 0xb3e201b6, 0x204bfe40, 0xadc40afe, 0xdc0c0c3c, 0x6a0c0c5c,
2546 0xc4042c40, 0xcdf8bcb6, 0xff2023b7, 0xaf951b9f, 0x17ca83cd, 0x3fafc6e6,
2547 0x7cbf0789, 0x6c790106, 0xf928b3f8, 0x4620e1f1, 0x2d43749f, 0xca86aeac,
2548 0x6065522f, 0xe7c40df8, 0x681ae2a1, 0x10aac5f2, 0x03329cfa, 0x7e1ab243,
2549 0xc80853b3, 0x000c060f, 0x4022bae9, 0x00000400, 0x00088b1f, 0x00000000,
2550 0x7dedff00, 0xd554780b, 0x733ef0b5, 0x27bcce66, 0x20212793, 0xf0841e4c,
2551 0x04242074, 0x11093a8c, 0x5076c403, 0xc2ab16fe, 0x25786784, 0x5ae5a911,
2552 0xc0133bff, 0x51b91688, 0x7e2da5a8, 0x68bc104e, 0x01226f69, 0x903a4483,
2553 0xbd08a5c0, 0x168b6ad1, 0xe088786d, 0x7e929205, 0xcfe956de, 0xe7dad6bf,
2554 0x9939cccc, 0x77e8f881, 0xbf41ffbf, 0xdecfb3ba, 0xd7b5ef67, 0xcfb5ef5e,
2555 0x30733d1e, 0xd7632776, 0x73941ff1, 0x4158c645, 0xf81d0ca4, 0x614b3ce2,
2556 0xc18b72ec, 0x6c64cc65, 0xe8431eca, 0x68afa84e, 0xd7588214, 0x3633301d,
2557 0x5b2bb181, 0xec46bd79, 0xb41b78dc, 0xb645d7b3, 0xd3b60a03, 0x8c8563a6,
2558 0xfe31379d, 0xb1d76f4f, 0x9916c634, 0xe3457579, 0x7e3839c1, 0x9991ab55,
2559 0x2df3fde1, 0x2beb07a2, 0x26410877, 0x27befb40, 0x7f180ca5, 0x32685071,
2560 0xe3bea0bb, 0x6765c959, 0x2f81cd6c, 0x0abce0ae, 0x4dfa9f5c, 0x7c2125cc,
2561 0x8d75a5ef, 0xb0696c66, 0x8c066a79, 0xe09774b3, 0x4b3cc1d6, 0x3ba10ab7,
2562 0x2173e027, 0xcbb8c228, 0x2b995a76, 0x9d70c38f, 0x8eb4bcd1, 0xbcc02f95,
2563 0x83670899, 0xe647b5e4, 0xa9f3f053, 0x72b981bf, 0xaf15f523, 0x5ef03cc0,
2564 0x3704aff5, 0xc75ab12e, 0xff304d7c, 0xd9e67d95, 0x7d70d92f, 0x3dae5275,
2565 0x7b951d7a, 0x834b1d71, 0x1b54d28d, 0x2d28d5c2, 0x6f191d1a, 0xcc4dced9,
2566 0x6b828a65, 0x5f00f64b, 0xfcb6bb54, 0xf054cfd4, 0xd3cc652c, 0x83f84364,
2567 0x9131ccd2, 0x22422de7, 0xbe38a963, 0xb19f1aa8, 0x99173d00, 0x6778843b,
2568 0xf477766d, 0xaa755dbe, 0xa2656df7, 0x781c6efc, 0x87de45fe, 0x2a4efd67,
2569 0xa9d3f937, 0x45dfb1fc, 0x9fc4fe70, 0xfd4fe547, 0x73fe7a6e, 0x2f95117f,
2570 0xbe543df8, 0xb2a72fe8, 0x7ea5efd1, 0x5367f92f, 0xa3efc3b9, 0xafeaffe7,
2571 0x7f15f2a2, 0x85ff3d2d, 0xbf95357f, 0xf9e807f4, 0x53d7f9bf, 0x04fb8cd9,
2572 0x16ff6ee5, 0x83f8f72a, 0xff75efd4, 0xf9f72a4e, 0x33f9e89b, 0x13283f88,
2573 0x3d3ace3c, 0x19424fec, 0xb0790273, 0xceb7af64, 0x59e4f500, 0xd7c03ebc,
2574 0x7e012750, 0x3a802c06, 0xdaa0dfec, 0xb4233ace, 0xdbc55a0f, 0x6b9c0687,
2575 0x743ed04c, 0x6ecf6f1d, 0x4331aef0, 0xde66f67b, 0xb0d83c3e, 0xc3ed02c6,
2576 0x51f6f3b7, 0xac6b9d4d, 0x85aa3ed0, 0x721adfb7, 0xfd41b5ae, 0xcf5e0ed6,
2577 0xb5aef4ef, 0x5dff3d43, 0xd5d89f5e, 0xef01d6b0, 0xdfc73c4f, 0xd9bde2d7,
2578 0x60cf9ce0, 0xee0736af, 0x4207e8f2, 0xc23e725d, 0x1cbd8cdc, 0x77d516f8,
2579 0xded4dc1b, 0x47aef81a, 0x92ea093f, 0x058fda9b, 0xc7bed47c, 0x53f6a5e0,
2580 0xbed42581, 0xfb52f247, 0x6a4ac095, 0x4b50dd7f, 0x87eeaced, 0x54bafed4,
2581 0x7549ed4b, 0xcfbea8eb, 0x8c196d00, 0xe33dd4e5, 0xcdfd0009, 0x511b7c11,
2582 0x6aeb747e, 0x12ca18ab, 0xf91d287d, 0xcd8149e9, 0x5d80fe46, 0xf27bba23,
2583 0x7c83c916, 0xc29bfcd7, 0x994cc497, 0xbeb052d6, 0x05a7e5e8, 0xd827e71a,
2584 0x71825baf, 0xce3e6fb2, 0xaa4563b8, 0xab1dc671, 0x1209c652, 0x8dfe963c,
2585 0xb26c7cd3, 0x4b639e1a, 0xa15e7195, 0x5bfd1c71, 0x8ab7b8d7, 0xb5bcf0d5,
2586 0x35e7195c, 0x7fa9271a, 0x1b7eecf0, 0xc64423f0, 0xe036fdd9, 0xd9c69327,
2587 0xf5a4e34f, 0x77fc9e0f, 0xe4e3548a, 0x8ca553bf, 0xce7841d3, 0xbb38dfe8,
2588 0x86ac99df, 0xcaa59de7, 0x9c682738, 0x575bfd21, 0xd58aeffe, 0xb96efcf0,
2589 0x69efce32, 0x8dfeac9c, 0x357de7b3, 0x3f79ecfd, 0xa27f3f4c, 0xb7fb7271,
2590 0xd40f82ae, 0x41f053f4, 0x102e7e98, 0x6ff6479e, 0xa81f3d9c, 0x07cf67e9,
2591 0x33f9fa61, 0x7fb633c1, 0xa3f82aeb, 0xfe0a7e9a, 0xcf9fa618, 0xfdf19e09,
2592 0xd3f5e783, 0x7ebcfc6a, 0x511f8c3a, 0xfb0a7840, 0x33c4cf07, 0x3c4cfc6a,
2593 0x8d8fc613, 0xbfdc99c6, 0xa33f5e71, 0x67ebcfc6, 0x1549f8c2, 0xf4775d70,
2594 0xcf135d6f, 0xf133f1aa, 0x433f186c, 0x19529e08, 0x8ce3061e, 0xbece3f89,
2595 0xecfc6a8b, 0x33f1c8bb, 0x3a27d3be, 0xce90dda0, 0xe4ce08dc, 0x0080de0b,
2596 0xa814faed, 0x30f4b0bb, 0x3d3bc81f, 0xf8d1ddea, 0x84405772, 0xc4aefb76,
2597 0xa2bb4ff1, 0x58e96ff5, 0x8263975c, 0x3877654e, 0x7aaa2d8b, 0x4a925952,
2598 0x6454a73f, 0xb369eaa8, 0xf4f554b2, 0xdeaa4707, 0x5e3058cf, 0x7cbc1f55,
2599 0x643eaab2, 0x7deaa955, 0x55d3e3d7, 0xeeeb59ed, 0x3673d555, 0xcf554f7c,
2600 0x554f3cdd, 0x54badbcf, 0xedc8de35, 0xd1f5552b, 0xd5531ebb, 0x51acb6c7,
2601 0x4f6dddd5, 0x3be3eaab, 0x3f8d539e, 0x54cff8e1, 0xb777c2f5, 0xa745eaa9,
2602 0x3fbd555e, 0x1a6bdcf9, 0x3ce6c6fb, 0x8bae4a3f, 0xc95acf68, 0x910e33ce,
2603 0x192d5ec8, 0xa3faa262, 0x7f546c43, 0x70df0ef4, 0x8fe3ec27, 0x6bd005f0,
2604 0x5bbe4a8f, 0x2fec319d, 0x4b1d39d8, 0x63a7d2c7, 0xd7db7d45, 0x80ce801b,
2605 0x5e874a2e, 0x650d3dcb, 0x3727ae8d, 0xe8dfca11, 0x2e916a4a, 0x4474151f,
2606 0xd591567f, 0x8d58dd22, 0xfd70e88c, 0x0297c2b0, 0x54f87451, 0xcaf39726,
2607 0x6a194fb8, 0x3eef51d3, 0x0066f756, 0x9993f2f5, 0x664cbc60, 0x9bc287ec,
2608 0xbc0e40a1, 0x3a68f99f, 0x09268bda, 0xf9e8d0ec, 0x347f9825, 0xf9c01fcd,
2609 0x6fcce3eb, 0xcd522dca, 0x52aace6f, 0x60966fcd, 0x4f63277e, 0xe7961dd7,
2610 0xffde9137, 0xe6987091, 0xa6ad6537, 0xac4bd7f9, 0x25bf354a, 0xf2037f3c,
2611 0x7f38f3c1, 0xe7f58c41, 0x3faf564e, 0xfd7aa96b, 0xcfff5f12, 0xf3c84eea,
2612 0x3ffd685b, 0xf5f04e17, 0xd7c63d67, 0xa371846f, 0xf18477e7, 0x5ff9c41f,
2613 0x69bf338e, 0xfd7ab178, 0xebd5cbd9, 0x5ff9f237, 0x9e4f7bad, 0xfff346df,
2614 0xaf8f7842, 0x9a71fb3f, 0x75ac68df, 0x38c9a13b, 0x441b52d4, 0x2fe600b9,
2615 0x050c801b, 0xc6444cf3, 0xde0c6248, 0xd164285f, 0x016a3c3e, 0x9ffe83ba,
2616 0xd0de8059, 0x72ed977e, 0xd017ac16, 0x6996af0e, 0x4aaec17a, 0x657819e9,
2617 0x57f72b41, 0xc333f818, 0xad2bbe00, 0x11fd9fbd, 0x7db05de0, 0xa025c91c,
2618 0x2def8674, 0x23529794, 0xe6307c72, 0xe413321d, 0x877bd329, 0x9a863bdc,
2619 0x2fd7683c, 0x1f630466, 0x60d85e3a, 0xc515df38, 0xa8b78b6f, 0xea824beb,
2620 0x097702ba, 0x81940912, 0x0b579652, 0x7f079ef3, 0x7ddd8180, 0x2c6dec06,
2621 0xb9b0313f, 0x0e7e785e, 0x452605fc, 0xed1d55f3, 0xabbd79cb, 0x73d61d3e,
2622 0xc3704abe, 0x0d81ec88, 0x3a196395, 0x7bcf0172, 0x77ef0039, 0x852ff298,
2623 0x7273e9d6, 0x003617f8, 0x7ff1477f, 0xb0bbc88d, 0x0ee08517, 0x7fbfe790,
2624 0xba054573, 0x83d7d0bc, 0x5e577def, 0xc92de2f7, 0xde98f7aa, 0xa9cdef44,
2625 0x1ea20c4c, 0xc36ceef8, 0x3b552eb9, 0xf1c03f30, 0xdd0fec91, 0xf1eebacf,
2626 0xdfb99e82, 0x75d7eea7, 0x8dd1eac0, 0xbb4b7285, 0x3dbec181, 0x8719a550,
2627 0x1f7f6879, 0xa878e192, 0x973edd56, 0x5fd42539, 0x9fab5773, 0xe3b40657,
2628 0xcf00f800, 0xf81c793c, 0xe6f844e7, 0xd7f36dcb, 0x7daa021b, 0x0a947a02,
2629 0xa22cf6e5, 0xbd0f5a02, 0x3fb7dd9f, 0x434041d0, 0xfb588107, 0xf9f7fffe,
2630 0xae7d8dff, 0x3e492d69, 0x8ad70517, 0xe7c969a6, 0xdb2dfaa2, 0x5f555339,
2631 0xd55fbc12, 0x4a96f17f, 0x86c2fb55, 0xf9f6aa25, 0xd5561feb, 0xa4ff032b,
2632 0x75773fea, 0xa1fdaa9d, 0xed54a7da, 0xab3d540f, 0xfbefdfaa, 0x77ffaaa9,
2633 0xdaaa3767, 0x864b0385, 0x46a8dc62, 0x881d0df2, 0x8df7aef1, 0xa1109b6c,
2634 0x2fae855b, 0xfca9d3f8, 0xb2a2efd4, 0xc830e50e, 0x5e3edd75, 0x1cab6cd6,
2635 0xa15bf28a, 0xb50c4ff3, 0x69fe5043, 0x672b55e9, 0x6325d0fb, 0x88bed083,
2636 0x2e596717, 0xf3ca2f30, 0x19db816e, 0xb213f3ca, 0x0d6c675e, 0x8972d7f1,
2637 0xd7f2dff3, 0x3f229606, 0xb942972c, 0xe3f8b6b5, 0xd68126b2, 0x1a36d8c1,
2638 0x10704967, 0xfbd17918, 0xf382ad9a, 0xe69141d2, 0x6e1f46af, 0xdec1da12,
2639 0x3f9c3a0d, 0xbee43ed4, 0xe78f0831, 0xc1c01d19, 0xdf49535a, 0x2797f25d,
2640 0xfe23d39f, 0xf05e54bc, 0xbcf2a6cf, 0x39e547df, 0x6795157f, 0x7654b5fc,
2641 0xf95357f9, 0xe5403f91, 0x2a7aff29, 0x5037f03f, 0x85bfd279, 0x83fbdfca,
2642 0x7bf15e54, 0xf4e854a8, 0xb57d96ff, 0xf2bdb8e8, 0xffafb8df, 0x16afbd1e,
2643 0x23c3939d, 0x0d06ebef, 0x55794abc, 0x61797027, 0xf31676e4, 0x788e2958,
2644 0xc3078955, 0x94571448, 0xf0ddc1e3, 0xd3f62777, 0x1831e537, 0xcfe8eaef,
2645 0x7b8e3173, 0xb191a4f5, 0xd3ebf8cc, 0x3c5c5fee, 0x46ee80b0, 0x3858b7f8,
2646 0x72aa015e, 0xdcec1e36, 0xf3dd7b11, 0x92cf5d78, 0x7726fdf0, 0x3c355c74,
2647 0xc072e22e, 0xd16af1cd, 0xdacf7b71, 0x847c722e, 0xb3efbb76, 0xc6b5e847,
2648 0x718b93d8, 0x2347f662, 0x36c63d43, 0x055871cb, 0x575e015f, 0x3a7ff5f0,
2649 0xfda04e3e, 0x1f1f105b, 0x47e0a5dd, 0x32bff0c4, 0x574aafc5, 0xae90439d,
2650 0x7bf4cab6, 0x027865b5, 0xe7191d1b, 0xd38b9d6e, 0x7ef04df5, 0x0e4be8f5,
2651 0xa657f3b4, 0xf2e79ceb, 0x456fe3e3, 0x16d3a653, 0xaab4a76d, 0x841b57eb,
2652 0x70371e72, 0x831acc25, 0x3ce9d1f2, 0x2c728397, 0x9c654a9d, 0xf392e995,
2653 0x0bf6325c, 0x2576f872, 0xea7e5f12, 0x6fbf5137, 0xe3788e1a, 0x6168e044,
2654 0x247de167, 0xf1d9ebd1, 0x3ba5c7fb, 0x8c245ffd, 0xc336b0c7, 0x985f6867,
2655 0xd1d7ffe0, 0xaa7a63ee, 0x34d6e32b, 0xade30189, 0x6a977cf8, 0xa5cf783e,
2656 0x67ae94e4, 0xf5be88dd, 0x7f42bcec, 0xa0e7ca20, 0x1079489d, 0xbf6d53b3,
2657 0x35eaaa24, 0x2a9d03ad, 0x00ff067b, 0x04cac739, 0x72c1d23d, 0xf5ba2c99,
2658 0xc002f5b6, 0x2e9d0937, 0xf78147a4, 0x92ea615b, 0xafa42e7c, 0xcdb9dfb5,
2659 0x681b3d85, 0x60f85abd, 0xf5ea66ff, 0x265fe1f1, 0x1bd47d5e, 0x22d7fe83,
2660 0xd01ea3fd, 0x999f3f71, 0x43e40e02, 0xdc701e96, 0x6cc3fc4b, 0x9ae0fc61,
2661 0x5513cc19, 0xff01c657, 0x5f6d47ad, 0xa4bbbe72, 0x76bbfee3, 0xbcf2cdde,
2662 0xf55fc337, 0xe2a7b7ae, 0xac78b5ba, 0xe4b3fd6e, 0x5314fca3, 0xefc151e1,
2663 0x59bbd124, 0xee97f984, 0x7f212d3c, 0x7204305d, 0xb903787f, 0x5b7e17df,
2664 0x646b79fa, 0xd8f72b9d, 0xf95fbec9, 0x0bd79cac, 0x779c4eb0, 0xf13c915e,
2665 0x0515e835, 0xa67c6807, 0xd3d88c2b, 0x5e6d7e4a, 0x27f232cb, 0x0901663e,
2666 0xc51792e3, 0x9fb44286, 0x4a353697, 0x32f3801e, 0xbe2395d3, 0x1c77b32e,
2667 0xb5fb51f9, 0x9f08944f, 0x899f6760, 0x6cec1386, 0x6cec1d55, 0xbb117d55,
2668 0x51f30d37, 0xc01b368b, 0xaa75a7c5, 0x9d115fda, 0x5662ee34, 0xc9768f5b,
2669 0xeffc96d9, 0xf0fb86dc, 0x88850bfa, 0x3cd079df, 0xf8f10928, 0xcbf1e136,
2670 0xdf04bfce, 0xde77df1f, 0xf26add08, 0x561e328e, 0xc13c14ec, 0x44737418,
2671 0x7d0ad796, 0x5f8641fd, 0xc59c0f89, 0xdea4417a, 0xa17fa9ad, 0xfe657fa9,
2672 0x4bba014d, 0x24f7ec8b, 0xe91677d1, 0x38f906ad, 0x5fb7c221, 0x3ef4fc79,
2673 0xa37f77e3, 0xf3560fe3, 0xc5ff8c0d, 0x4e7e3a37, 0xfa8df81f, 0x77e3be82,
2674 0x59631d9b, 0xc4a9d902, 0x3a71815f, 0x1fe9bbf2, 0xd2136bda, 0xc0a69fc9,
2675 0x39ddd638, 0xd9a38c41, 0x14e99dcd, 0x54bf07d7, 0x6024f30f, 0x0edf907f,
2676 0xf9f016e6, 0x2cd37ed3, 0xf8ca8794, 0xe55eb776, 0xe914267f, 0x7b28fe35,
2677 0x61f00737, 0x38a6a793, 0xfcedd41b, 0x5b6b666f, 0xe30b7c4c, 0x04e8fca8,
2678 0x2ffe45d6, 0x9e7aa78c, 0xa1d59a38, 0xa8f44a1a, 0x6d154f9f, 0x9c4b6f14,
2679 0x9c4e28c6, 0xfad7ae5c, 0xd2c315f7, 0x4740e0a2, 0x32c9ea1b, 0xcfa6e01c,
2680 0x67fde014, 0xf08cf4cb, 0xc5ff8012, 0xbc593380, 0x01f9c216, 0x39df155e,
2681 0x65f540f2, 0xe7aabc11, 0x4d19e700, 0xe50f207c, 0xb8b31246, 0x53801e71,
2682 0xdbd1eed5, 0x0e1e2853, 0xa3e517f2, 0xc989d4cd, 0xaaef9c7f, 0xf4ebaf0a,
2683 0x190b23e9, 0xfc385085, 0x942fa601, 0x83ef8bf7, 0xd313bfaa, 0x8f04d9d4,
2684 0xd8361c7a, 0x6f8f2d19, 0x8309fd95, 0xe9133bc1, 0xad6870aa, 0xa717f388,
2685 0xaec872bb, 0x3a214b68, 0xca5d5acc, 0x685d42ce, 0x9cf78460, 0x39ef1c0d,
2686 0xf71e3a3d, 0x0e09675c, 0x268cb183, 0x9c833016, 0x301cad02, 0x8259c78c,
2687 0x5ae49fb2, 0xcd3cc3a3, 0x7829a07a, 0x54a7adaf, 0xa73610b7, 0xfc609b09,
2688 0x3e3de96f, 0x67c1c63d, 0xe375d2fa, 0x9ae161f0, 0xa5a0c18e, 0xb8211b19,
2689 0x05080b41, 0xc2de8e87, 0xdf184a43, 0x790f4185, 0xd72ed46c, 0xdaed0859,
2690 0x2faf0b06, 0xae9417d7, 0x988ff787, 0x5d71cbbc, 0x891ce4cc, 0x4a162b79,
2691 0xb7c6f5a2, 0x0724024f, 0xb6f2b815, 0x4cb54d77, 0x2814fe40, 0x1ecc3fcf,
2692 0x24255bb6, 0xa5361dae, 0x6ed0921e, 0x2dbcb6f5, 0xa2bb7fa1, 0xd76a6de9,
2693 0xa1ca1d61, 0x07535dc9, 0xd4f88981, 0xf4d2b2ba, 0x4b5e3011, 0xd60eba65,
2694 0xb2badcf5, 0x4f75ea43, 0x1c51d35b, 0x775eb759, 0x77dd66b7, 0xcfdd70df,
2695 0x5d2eefe9, 0x75ffdc5f, 0x8b3fbec2, 0xa25199f8, 0xeefe510b, 0xf0282da4,
2696 0xec99bb78, 0xc69c7941, 0x1287f638, 0x7e718437, 0xe850eb8a, 0xa14f7947,
2697 0x9174789b, 0x79239ccd, 0x1f4d503e, 0x6d9ef4c7, 0x7a4bd708, 0x4054894f,
2698 0x787b25eb, 0x2ee7cf86, 0x2dd08fcb, 0xd1f2f9b3, 0xe61832be, 0x57e702fd,
2699 0xb2519ae0, 0x7802cc52, 0x21ec6177, 0xd49eb235, 0x2e7301d5, 0x03d533ac,
2700 0x7be177d8, 0xcf7c66be, 0x8427bb31, 0x32262647, 0x4620be5f, 0xaf995ee8,
2701 0xdf1e4dfe, 0x05d4afaf, 0xed5c90d7, 0x08bc7012, 0xe869743d, 0x43d387a1,
2702 0x87a269eb, 0x9cd3b6ea, 0x4aeb5a1e, 0xdbaa9e91, 0x85d1a704, 0x8719eaeb,
2703 0xebeffcfb, 0x61ea97e6, 0x7b5a879f, 0x1d0107ea, 0x69655818, 0x7af09985,
2704 0xb3ebe118, 0xca7c323f, 0x6fede2ba, 0x1facd1c3, 0x707d468d, 0xe61ee75c,
2705 0xe94de08a, 0xd12f4977, 0x7c906c3e, 0x295e90ef, 0xcb823aea, 0x3be8ed7f,
2706 0x1c5bb40e, 0x883defc7, 0xc1663bef, 0xf322b90e, 0x535f1c36, 0x1a67e78a,
2707 0x64381d60, 0xa009eb02, 0x1f1f13dd, 0xf8c25f9c, 0xf84d3968, 0x9e1d61d1,
2708 0xa7e72abf, 0x5ec8cf80, 0x7ee56a19, 0x1e7ac7ee, 0x5e9bfb3f, 0xef6e4b94,
2709 0x2abf1ea6, 0x5c4fd0b9, 0xa9fea3a7, 0x5e8e8e58, 0xf7ea3aff, 0x055e5437,
2710 0xfb287c11, 0x4813d0a9, 0x5fe62b4a, 0x577c5996, 0x6493f4d5, 0x4f1a8acd,
2711 0x9fa36f79, 0x7f8017b9, 0xde63b137, 0x81ff2823, 0xf543fe7e, 0x198318de,
2712 0x47f4a6f1, 0x3fb58cfa, 0x14331ef0, 0xd05c79f0, 0xa563b9bf, 0x7f617688,
2713 0xf650b5f7, 0xacad0b8f, 0xbf7835f6, 0xac4a0130, 0x01f5cb27, 0x2f107d72,
2714 0x75b94fb3, 0x946f3c02, 0x6e9effb8, 0x7a92e390, 0x3bcc48e7, 0x3db81ba5,
2715 0x923e9c58, 0xb7c2bee4, 0x2484be88, 0x58021b32, 0xe964f566, 0x3e14df70,
2716 0x42e8f7d6, 0x594a5076, 0x0dce977a, 0x61f98fcf, 0x9ff037dd, 0xbd108fa6,
2717 0xd1d1ecb1, 0xfcbf5d06, 0x5276b898, 0x6c3b1f57, 0xec9521b4, 0x42f78da3,
2718 0xaf447abd, 0xc6b5fb84, 0x8ddb7d5a, 0xe169efce, 0x13ed763f, 0x577bfa07,
2719 0x8f2c6afe, 0x5078f715, 0xff51dbc6, 0xb14f7a6c, 0x30ab68a3, 0x3ec0cfbe,
2720 0xd70bf0e2, 0x7d92548d, 0x3c890774, 0x3e80c7dc, 0x55a7f509, 0x777e73a0,
2721 0xebb3fa46, 0x8477e7c0, 0xb1b05696, 0xb72bf950, 0x3ff04c6f, 0xe98faff4,
2722 0xed1e747d, 0x9a79e318, 0x3b6d6b42, 0xd33199d6, 0xf985c3bd, 0xa29e753e,
2723 0x2ca1a130, 0x42489509, 0xc533cd26, 0x0e4f69a4, 0xb2fe51e8, 0xe71e4cec,
2724 0x945f3062, 0x44f40e9f, 0x7c3658f9, 0x3395d924, 0x65dd2af2, 0x48bdfbf2,
2725 0x731b7eac, 0xfae44426, 0xeefdd734, 0xd1dd9532, 0xfd3946e0, 0xe245dfd6,
2726 0x7f1e2d6b, 0x7d7ce065, 0x9775efd4, 0x63c5f4e5, 0x67584ba9, 0xa7c5f577,
2727 0xfc5a5f16, 0xc95fc3c6, 0x52597729, 0xf1693c0c, 0x46ff0c72, 0x06368f3c,
2728 0x9de20203, 0x4b98e9e3, 0x78188160, 0x29d2ec52, 0xa4683176, 0x9dd90f76,
2729 0x68f0c977, 0x4f17d6f1, 0xd2bb8a9e, 0x411ff022, 0x4e91e87c, 0x884aefdc,
2730 0xdb0304ff, 0xdd0ceb81, 0x6ab7f949, 0x434c1fb9, 0xf93bb579, 0x8375e150,
2731 0xf087707c, 0x386301bd, 0x6d55fd7d, 0xb83dde7f, 0x14a0dd72, 0xfb9803c4,
2732 0xd4671f1c, 0xf1b8c374, 0x7da4cd61, 0xdba8fc07, 0x587e3993, 0xcbbf6f32,
2733 0xd0d769a9, 0x0abd768d, 0x3e1bfcdd, 0x3f17d498, 0x30ecdd0a, 0x067276c8,
2734 0x1e788c1b, 0x02426fbb, 0x78da2dc5, 0x4f4b5ede, 0xc37a4f13, 0x47f4c8e3,
2735 0x5f3025f4, 0xfb33b9f8, 0x569bc86b, 0xf25166d0, 0x7be8b866, 0x51bc9623,
2736 0x7976fff6, 0x81676e9f, 0x4b03a283, 0x74c25ffd, 0xff591993, 0xda275c21,
2737 0x20d883e7, 0x8318e75c, 0x7969cb8b, 0xcb75e19d, 0xe58a09e7, 0xb64d8bf9,
2738 0x7acb8e10, 0xf8c297f4, 0x5cf8a2cf, 0xc08a4a40, 0xb3fb9061, 0xdb8cb521,
2739 0x79d20f5d, 0xbb0bc01c, 0xf1c08d6e, 0xa7a08307, 0xc70c9578, 0x80a69de5,
2740 0x57ac2b78, 0xf511fdf4, 0xf8e125d6, 0x3e9f5a58, 0x4a7a8b94, 0xdadbdedb,
2741 0xd0ed8d51, 0x93f5116f, 0x71865fe1, 0x9ea7a007, 0x6dc18d37, 0x8a48e231,
2742 0x4a6c093d, 0x83e15cf2, 0x6505513b, 0x92dfa5f7, 0x1c7af1d6, 0xa5b74b5f,
2743 0x1da159e0, 0xbbd7a5aa, 0x7c1ccf58, 0x4553a5ae, 0x7a597eaf, 0x30a9ec50,
2744 0x74d4845d, 0xd003d0a1, 0xfa42ffc7, 0xf1f09ee8, 0x9efe68f3, 0x169bd098,
2745 0xbd810f4b, 0xeca293a7, 0xb3f678e8, 0x48273762, 0xc7da333e, 0x595d797a,
2746 0x9e1d2e79, 0xf25dba8f, 0x62b9f058, 0x0fccdc4f, 0x80e01d60, 0x91cc7d02,
2747 0x83a4ddf1, 0xc0dbe006, 0xf288214a, 0x63d621e6, 0xaa1ef9c0, 0xc9fca835,
2748 0x8f9ee639, 0xe6fd087e, 0x3d270dd4, 0xbf28c3e4, 0x38f3ef48, 0xffcf3d44,
2749 0x5c9ebcb3, 0xaee6bff4, 0xd1fc6836, 0x39e3a224, 0x23ecfe4e, 0x09303be8,
2750 0x4d4aedc7, 0x76f94d1a, 0xfced7f55, 0xe3b43aca, 0x91abdf6a, 0xee78b2e3,
2751 0xf7851dca, 0x83b71251, 0x131ef0c2, 0x6f80bc39, 0x6aebac1d, 0xd3e088db,
2752 0x2954e831, 0x8e5d267d, 0xef52393e, 0x3b38d37a, 0x955f6318, 0x3f7c1479,
2753 0x7c153ac8, 0x0e8b1e7e, 0xffdc7d8b, 0x910e6dd6, 0x2f1dacbd, 0xec8ca7a7,
2754 0x81269cb0, 0x4de5deec, 0x2af9ba25, 0xa3fb9bfb, 0xa6efec7d, 0xf2de3483,
2755 0xfedc8396, 0x3b23aa6e, 0xf70b797e, 0xa43ec047, 0xc80463f3, 0x15cbb268,
2756 0x7983d33f, 0xb79815a2, 0xbd21ede4, 0xf3d5cf0b, 0x78d235fe, 0xf21ca9f1,
2757 0xc0ff7913, 0xa7e8b5c4, 0xa85afd86, 0xbab5fb47, 0x9576c2ba, 0x6c281b5f,
2758 0x5b5f91bf, 0x05385f53, 0x8fe05afd, 0xcdc15245, 0xe4b663f9, 0x797fa1ba,
2759 0x41ade4c4, 0x02e2533e, 0x6abffdda, 0xfd202572, 0xbdfb253d, 0x23cf57d3,
2760 0xfc3cde7b, 0xa37990da, 0x7df2de51, 0x76e24c7f, 0x7be88a4b, 0x3eebc70c,
2761 0xcf172d74, 0x7fb4d4cb, 0xbcf911ba, 0x1ec3ce4d, 0x5d9157f7, 0x13dfeca3,
2762 0xa777b712, 0xa077688f, 0xc14f7ffd, 0xcfe81cef, 0xbcf3d65c, 0x4922a5cf,
2763 0x18f66f65, 0xd7027aee, 0x1e8094ad, 0xf16ee511, 0x82938e84, 0x8ffcbe23,
2764 0x808f77c8, 0x7b5d9df2, 0x5bd70d3b, 0x81d872d3, 0x7e84bef8, 0x5bc9c610,
2765 0x8f30d3da, 0x77f9a2b8, 0x9e7bf40e, 0x7b5db897, 0x40e9df59, 0x1ef96ebf,
2766 0x5fc9dbb0, 0x003da50a, 0x32d4ba78, 0x3e69f0bf, 0xbf5a298d, 0x85f57fe1,
2767 0x76edbb11, 0xeb282053, 0x284e253b, 0xefa1875c, 0x663d116c, 0xedfb5f47,
2768 0x4dacd1f2, 0xcc0fb815, 0x0f861ee0, 0xec83acf5, 0x09962539, 0x21cf0a92,
2769 0xbf2b901d, 0xefbde96e, 0xe7162236, 0xda0251ba, 0x0c14be3d, 0x8db69592,
2770 0x9188375b, 0x73d950be, 0x12ef7b5a, 0x1b77dd73, 0x7aa3b9ca, 0xd6b37686,
2771 0xfdd163fe, 0x9f7fe387, 0xd6bcbc25, 0xfdc56d92, 0x59d320da, 0x54ef4b4d,
2772 0x166a97e4, 0x6f7e0efa, 0x3a22dd55, 0x7246ec43, 0xf85bdd77, 0x9b7753fd,
2773 0xd8f485c1, 0x34d876dd, 0x22adeb16, 0x4e6a99c5, 0x3a428f14, 0x2866d2ba,
2774 0xbcd7bc47, 0xf903b1f9, 0x57cfd15b, 0xde7a44da, 0x9e9676dd, 0x695ee32b,
2775 0x7a851e4d, 0xfdc759a5, 0x9f238ebc, 0x7fdf915b, 0x326aed7d, 0x7eb297f9,
2776 0xaaa7618d, 0xddad4eec, 0x6e19e53a, 0xb5494e47, 0xec579c93, 0xf8fa3ecb,
2777 0x67675b14, 0x6b1f425f, 0x4919f0f4, 0x616ef3b6, 0xd8af31e3, 0x19792d7a,
2778 0x9b7765f2, 0xe286b9d5, 0xe88edc1e, 0xb9f4f8ee, 0xb8fcf819, 0xee9c7148,
2779 0xf1d1226b, 0x86cb03a1, 0xf1a2d976, 0xf5fb4f5c, 0x5f3fc0d9, 0x3ffd0fd9,
2780 0x07716c3b, 0xf77a7d70, 0xd63daf28, 0x78e504be, 0x97432841, 0x4320658e,
2781 0xec35f457, 0xe27d93c4, 0x7f91d7f7, 0xa67a9857, 0xddcd18a2, 0xfe425a7a,
2782 0x057920df, 0x2687e923, 0x8075f22b, 0x73c20e95, 0x561655cc, 0x53d4f48a,
2783 0xa0db9cc7, 0x9d51cf75, 0x30fb04ce, 0x1ba64761, 0xf955edb7, 0xa692f35c,
2784 0x4a332906, 0xbf912c5e, 0x0860bb3b, 0x7a8a490c, 0xcb91a4fe, 0x97870bab,
2785 0xeef248be, 0x161b237d, 0x362dbf43, 0x5bb57d72, 0x85d8cc0a, 0xe8e8cefd,
2786 0x238ec1fb, 0xf3c11c6f, 0xba4e4b10, 0x28bea1c6, 0x6ffa7231, 0x3d6afe3d,
2787 0x3d690b9e, 0x76f478c5, 0x83a8a57b, 0x1733f779, 0xabbd3f8f, 0x1c23ff23,
2788 0x649e63b7, 0x461de75c, 0x1ff6672e, 0xc74795d5, 0xe7cbf605, 0x1a356e1c,
2789 0x4661fc68, 0x8ed7ca91, 0x23cf2696, 0x19e5f3be, 0x75ceef91, 0x915c3bd5,
2790 0xef629578, 0xb5f77a4c, 0xcfe06319, 0x4e749749, 0xbbd76edc, 0xaf5c44db,
2791 0x896302eb, 0x07fb5f42, 0xf88f1bc6, 0x7fdbc657, 0x70078f89, 0x54be421c,
2792 0xf41a0ff0, 0xbea1a347, 0x849f53bf, 0xf82813df, 0xcca1d657, 0x9e626aef,
2793 0x8eb11b46, 0xc41bb5e7, 0x8f52314d, 0x54ef91f4, 0x7449cef8, 0x29e486f9,
2794 0x1810f4e5, 0x870bf582, 0xec57642d, 0x4b11f596, 0xf88a1caf, 0xbe69f653,
2795 0x0513eb91, 0xcff3789e, 0xca54e191, 0xafd74b2f, 0xa2015c1a, 0xc5023d9b,
2796 0x90815c19, 0xfb053b29, 0xe739d365, 0x37d8de48, 0xbd87f707, 0xd6ffa6ab,
2797 0x8ace9d2e, 0x214df1f2, 0xfde0d291, 0x74c34fb4, 0xfa226fa6, 0x88c93d6b,
2798 0x7cee978f, 0x58cdc798, 0x728e9068, 0xc84181c8, 0x9c3fc8b7, 0x0503437f,
2799 0x35b52728, 0xf8441dae, 0xaf90390d, 0xbe027822, 0x41b6b2c1, 0xb25d7a42,
2800 0xe58b978a, 0x6c9647ef, 0x2e7f11f1, 0x15395ada, 0x98d5a7ed, 0x28bd40f4,
2801 0x59d32bd3, 0x4ebcf032, 0x85df6caf, 0xdd3897e1, 0xd4d96c5e, 0x7d02f38e,
2802 0x63e233fd, 0xcfb3eb72, 0xbd0ab823, 0xa06edc5e, 0xde90aa71, 0xad74f8a3,
2803 0xde7bafbc, 0x693ef4e5, 0x7bf4a1bb, 0x0149eeb0, 0xec38c4e6, 0x443bedfe,
2804 0x91fbdf94, 0x9f39339e, 0x70be9ea3, 0x63eb69f8, 0xeb4ecfa8, 0x777bc618,
2805 0x39aaac4b, 0x1a3a2f8a, 0xeff1575f, 0x33759dd2, 0x95dcae28, 0xa66ba024,
2806 0xf782adf0, 0x1a7b92dd, 0x34b7fff1, 0xdfc65ffc, 0x81ff87df, 0xfe649b7e,
2807 0xfc0e54df, 0xb7128f0f, 0xce380a27, 0x79f6296e, 0xfd8d57a1, 0x5710b73b,
2808 0x23ef1eae, 0x72355f57, 0x0d91dbff, 0x73df57f3, 0x30effc95, 0x6cdd327c,
2809 0x26e8532a, 0x7b71f053, 0xf8839753, 0x3d22bc02, 0xf289bd93, 0xb82b24b6,
2810 0x8f45884d, 0x967c946b, 0x72236f8a, 0x5f5fe14d, 0x5853c21b, 0xed16bb56,
2811 0x008ae4e4, 0xc145e9d1, 0xf4093437, 0xe7e445da, 0x67e17218, 0x333e5e32,
2812 0x1be754f8, 0x32c1c2fb, 0xc0abae90, 0x69f3a2e3, 0xee27055b, 0xdaeed28f,
2813 0xf782fdca, 0x9e573e65, 0xf915ffbf, 0x53f78c3e, 0xeface27d, 0x933eb91b,
2814 0xdcceb04c, 0x4c67d720, 0x60be2528, 0xc819e9ba, 0x8f404b6f, 0x8f4a2f7d,
2815 0x1034345d, 0x38782abd, 0x67fbd32b, 0xcfdd7c89, 0xc41e70c9, 0x5be12998,
2816 0x7a0947ce, 0x5af9c0bd, 0x8bbf3814, 0xc3c5fe38, 0xdd11a793, 0xee9b13df,
2817 0x246aed97, 0x772c4cfa, 0xb3b9438e, 0x2736ef49, 0x8f258e8e, 0xec765483,
2818 0x49f909f8, 0xf7c8c748, 0x0aa0f8f1, 0xa0c580f9, 0x7fd020ff, 0x7429fed4,
2819 0x1d717400, 0xd73ca5f1, 0x379285d2, 0x5bb2f053, 0x669b7793, 0x601a78e2,
2820 0x25def2e2, 0xfa78a9cb, 0xf3ef2be5, 0x2bf87dbb, 0xe6a054cd, 0x456fdc2f,
2821 0x13717c4e, 0xe2679b3e, 0xfa644fed, 0x780ede4e, 0xe4a0627a, 0xeb720b5a,
2822 0xe766d809, 0xa63e48f8, 0x595f9e49, 0xa09348c7, 0xf368dbca, 0x6f830629,
2823 0x9f0a2984, 0x8d73f798, 0x334bd08e, 0xd81cfce3, 0x43cf946e, 0x5f765538,
2824 0xc6912981, 0x40c1ea77, 0x967fd405, 0x0361d959, 0x0ceeeeb8, 0xe1718c54,
2825 0x5981db77, 0xbae264f7, 0x853e829c, 0x53ace5d6, 0xdf20ce8e, 0x7c50b71d,
2826 0x3ddb3f24, 0x974cfc8a, 0xf7c71f3b, 0xeca4fbc8, 0x6b75bc67, 0xfdbc5cf5,
2827 0x21e3279c, 0xcad76e55, 0x2e26418f, 0xf9657a37, 0xf83fe5a1, 0x526f9317,
2828 0x3b242fb7, 0x6d8c9d90, 0x326fde07, 0xff5179f0, 0x00d4bf40, 0x23ddfeff,
2829 0xdcec27ef, 0xc343c41c, 0xa39d2376, 0x31d7f850, 0xf18e9bcb, 0xe48a4713,
2830 0xaeb8c176, 0x7e1a6c59, 0xe8f2efbf, 0xd651bfc8, 0x26e1ff5f, 0x7ea26fba,
2831 0x7da19187, 0x57ef209f, 0x0c162cc2, 0xbaf9f109, 0xb1e80763, 0xd3fe2894,
2832 0xee89eb07, 0x5103bf80, 0xd93437fc, 0x2d806e97, 0xdbfac1fe, 0xc0b74cca,
2833 0x8ccc993c, 0xa82aea16, 0x347c006f, 0x96047924, 0xb675f548, 0x0fe3f181,
2834 0x2e4d303f, 0xbf04f3c3, 0x6fbe7a32, 0xc438a54a, 0x1c2cb00f, 0x28b22b50,
2835 0x1d99bdbe, 0xb1f955f3, 0xb0738e46, 0x69469036, 0x9ce2f8aa, 0x2f8a2e9d,
2836 0x507c8d3e, 0x79fe719d, 0x8da6ae1c, 0x078beb9f, 0x678c8a47, 0x17c4e790,
2837 0x115ade29, 0xcf857ffd, 0xc925379e, 0x3011ebfb, 0x1dd0aefe, 0x93da29f2,
2838 0xe31d7e4a, 0x2f8a762e, 0xb0ee8907, 0xc23e309e, 0x742a1b7f, 0x61e2b1e5,
2839 0xafb64cbb, 0xf23487a7, 0xb17db589, 0x4bd031f7, 0x48b7f835, 0x29976af2,
2840 0x54d81eca, 0xc78d2671, 0x439d19cd, 0xe39e447e, 0xffee35c5, 0xe1f28e18,
2841 0x947efcb7, 0x80294671, 0xfdc0aae7, 0xe4d33975, 0xda9d90f1, 0xfc1d9084,
2842 0xd1cf9add, 0xf37f0173, 0x2f951d73, 0x3cb7b3fe, 0x56d9ed13, 0x032c1b9d,
2843 0x5c93ebcc, 0x41650f70, 0x9373d013, 0x2a9b9f85, 0x9079b769, 0x1305bbfe,
2844 0x13e99b9d, 0x19ea2f8f, 0xd7da0bb2, 0x411f01b6, 0xb184bbb5, 0xef57844e,
2845 0x0ad0f3a6, 0xd89ec77e, 0x63df4794, 0x37dc1be9, 0xcbc55b8a, 0xb6af16df,
2846 0x894adc50, 0xf4f71593, 0xb5649d10, 0x61f8ea65, 0x5e8f3e29, 0xd792af5e,
2847 0xbef1926d, 0x226be8fb, 0xb2c2b1ea, 0xef68b586, 0xef7d1867, 0x2e4ddd23,
2848 0x1339db56, 0x3b76da84, 0x4634d7d2, 0x1fc2827e, 0x20ec5dc9, 0x4f12a986,
2849 0xcfd07976, 0x73c17c9a, 0x04a9fd10, 0x77f8132f, 0x24f3e192, 0x58ff70e7,
2850 0x07b8478a, 0x13fc29c6, 0xe328bc23, 0x2a5a3eec, 0xd2919da0, 0x46b82659,
2851 0x2defa5f7, 0xe04e77e8, 0x5f701ee7, 0xe8687f15, 0x6196462f, 0x2fe9487c,
2852 0xbd5cb99a, 0x429be7cd, 0xafa34fa1, 0x349de717, 0xa98ed83b, 0x81558997,
2853 0x84f10c76, 0xd184b3d7, 0x02ba8378, 0x27818eb4, 0x9658257d, 0xf7048948,
2854 0x3a210be4, 0x96a0312f, 0x5b9231d1, 0xfb25df3a, 0x4eda96e1, 0xf771f701,
2855 0xef0443d1, 0x5e0ecee0, 0x9af57cca, 0xb814ffac, 0xa27f644a, 0xd5c38e44,
2856 0x8e9f9e5f, 0xecd181fe, 0xa338c12b, 0x12fa8eb2, 0xbf9e3a5f, 0x3ce782dc,
2857 0xe73fc426, 0x14966691, 0x8cc1373f, 0xaeecee7e, 0x5a7b4823, 0xf8ed39bf,
2858 0xb48fda19, 0xdd1ddcd5, 0x80a57c72, 0xc1e5b5f4, 0x22b37ed8, 0x71c8b62f,
2859 0x14f3a8c4, 0x7ad1cd83, 0x9ac932b9, 0xc28f2515, 0x9e722672, 0x9e7cb762,
2860 0x6f7aa6c2, 0xa46613cc, 0x27834ea7, 0xdf2b9f07, 0xdf2abce1, 0x71f8a01b,
2861 0x961ebe0a, 0x9e68d3f7, 0x1086e749, 0xe3a04e4f, 0xbfb1cd57, 0xd6685987,
2862 0xd3977ac9, 0xf4e4eb0b, 0xb688eb82, 0xb999a633, 0xe3cdbd5e, 0x74e7a29b,
2863 0x9c788452, 0x476c1454, 0x1e589dba, 0xbffa4768, 0x5274c985, 0x4b44e9ce,
2864 0x939bf7ef, 0xa1e93a64, 0xe0260a7b, 0xe43145f7, 0xdb998563, 0xa59d2977,
2865 0x0fc03f44, 0x857ce177, 0x03456a83, 0x339cd0a5, 0xf0f8ef50, 0x9e7822f2,
2866 0x4769e45f, 0xbc7a737a, 0xa8db8e22, 0xc9ba7277, 0xb8c49ef4, 0xe4aa7d77,
2867 0x38d02b5e, 0xe0c736df, 0xa7e416ab, 0x4a7e11d1, 0x5a47e391, 0xc3229cba,
2868 0x1cf193e5, 0x43df1e7f, 0xa74a4f38, 0x33f783ce, 0x4c25b9e0, 0x055c4e46,
2869 0x96f912fa, 0xd2f9d275, 0x09672aa4, 0xe5a0ddf2, 0xf9f7016e, 0x016fbd25,
2870 0x3c76b3ee, 0x350c9f45, 0xbffe8879, 0x6268deb2, 0xf2ff8d26, 0xb5db99b0,
2871 0x7e512b1b, 0x8499f2bf, 0xf0a5d5f2, 0xd6f1d1e5, 0xf3745179, 0xf83a5f74,
2872 0xa07458a7, 0x3a5a7f95, 0xb50bc888, 0xadbc03fc, 0xedc3fbe5, 0x55ce94dc,
2873 0x6a1b9722, 0x7f6f1779, 0x0d0dc8fa, 0x3de98f1e, 0x097ae0cf, 0xf39105e9,
2874 0x74f4f1db, 0xae1ff9a3, 0x31cd1ba7, 0xd4ceb4f4, 0x9f3c1bf3, 0x744da2bb,
2875 0x5f225c61, 0xf6ba8f3e, 0x4f3a24f1, 0xe09362f0, 0xd1439746, 0x502244d3,
2876 0x6127b2bf, 0x4a15bb2c, 0x6ae78078, 0xb2250302, 0x08c759cf, 0x24d633ca,
2877 0x1bac70ca, 0xdbb7fa41, 0x51e600a9, 0x256063eb, 0x91d3fa01, 0x684b181d,
2878 0xf310783a, 0x988b6b2c, 0xb77000cf, 0x80f3f1b7, 0x485bd62f, 0x7e3eef9f,
2879 0x400f37f5, 0x1d71e73d, 0x0e047f1d, 0x4ab673a6, 0x03b145de, 0xe8590e3a,
2880 0xb32f703c, 0x7754d1b8, 0xf8790d8b, 0x21fbec02, 0xe8d983c4, 0xe2281fcb,
2881 0x77aec439, 0xf1eca38a, 0xccbfd6de, 0xe48ae439, 0x7d0e9a97, 0xdf6d185e,
2882 0x14a9f929, 0x3996f7d1, 0x963fdfca, 0x77cb9677, 0x055fb9cd, 0x9c5e309e,
2883 0x5da27f1c, 0x2375f04f, 0x48bf687c, 0x10fb861e, 0xe3d648f8, 0xfb94de32,
2884 0x0adbba0f, 0xbe80fa4e, 0x98393c5e, 0x7b5be1c7, 0xef7768cd, 0x214ef932,
2885 0xf4b7899d, 0xf6a9f9d0, 0xe811deb6, 0xf9fc834f, 0x1ef79f08, 0x9d149b3f,
2886 0xeb12feff, 0x3f5a24fb, 0x729f5bc4, 0x1f4b5e3e, 0xda167dda, 0x184dfe0e,
2887 0x50c07c4b, 0xb086054e, 0xf567fa20, 0x17adc663, 0x31672371, 0x341dc517,
2888 0x999fb479, 0x8e65ffbc, 0x4c679fe2, 0xde21bfde, 0x4efc1e71, 0x05f9d603,
2889 0x989ec7d6, 0xdb478f9f, 0xf53ac2be, 0x18fb9896, 0x215afda2, 0xe60567af,
2890 0x537cf0fd, 0x3852e18b, 0xef231ddf, 0x8091fb07, 0xdd4a05e3, 0x9fb87d27,
2891 0x6bdcd81f, 0x4efa1f11, 0x0091da27, 0xb3b6227f, 0x97ba4aa2, 0x50f060c7,
2892 0x3ad5f47e, 0x5bbd7e7e, 0x1e31b8b0, 0x6491dcd6, 0x33f87941, 0xfb1d2f93,
2893 0x9d5dd48f, 0x09fa7183, 0x3cdd5e9d, 0x41be53d2, 0xe753b216, 0x8e09eaf7,
2894 0xdfda315a, 0xcfeb12fe, 0xe7dcc4b1, 0xc790fb3e, 0xa1f7c5d7, 0xf462e7df,
2895 0x3e9c7bfc, 0x45d651f9, 0xfb83f6f1, 0x3cc5c93e, 0x4f81f552, 0x7ead3fc8,
2896 0x5b9b48c3, 0x0488c6f6, 0x252be3a4, 0x4b89edb1, 0x1eb75afe, 0x967199ec,
2897 0xcb9b922c, 0x23dd2759, 0x61e9a2b0, 0x5e4a3eb7, 0x71d3f62a, 0x8e056743,
2898 0x6440bc7f, 0xbd774075, 0x580389ee, 0x94ac390c, 0x097b45bf, 0xfd1f7f60,
2899 0x9f9bd4d2, 0x9de6d283, 0x338fb4fb, 0x42a11c53, 0xb3cc8763, 0x88f73d70,
2900 0x8fbc325c, 0xbcbce005, 0xe0e74ed7, 0xcf7f8f2e, 0x5c4b1f81, 0x7e5df96e,
2901 0xb0ffcf00, 0xbf3047ce, 0x8d8bf816, 0x718aa8fc, 0xd9d7e5ef, 0x3b76fc23,
2902 0xdbb0418f, 0x70e13f5f, 0xe68aff41, 0x144094f6, 0xa1e7b4fe, 0xc7d7911e,
2903 0x6e745df4, 0x98bfed84, 0x563ef786, 0x829c3bec, 0xec37fdeb, 0xaedfc318,
2904 0xf44d5d58, 0x9f22d533, 0x1960caa3, 0x8bfa0f28, 0x0573ed07, 0x5dc7c70f,
2905 0xf77a821c, 0xd23b1c4a, 0x75ebf72f, 0xf6801a4f, 0xca14854d, 0x55bf1589,
2906 0xbc2d2bfc, 0x3b373b37, 0x58f7e243, 0xb6af9f6a, 0xebdf3d70, 0xf000b336,
2907 0x068d23e9, 0xc4eeaefa, 0xcacc3fb5, 0x64f8fd87, 0x06b9c1ab, 0x85eaadf8,
2908 0x309bc1f6, 0x48ce395e, 0x5c4f97f1, 0xcba41ca1, 0xf3f02fc5, 0x7d6c9fb8,
2909 0xc8f30d24, 0xb5f409ff, 0xdc58e01c, 0x55e7a068, 0xe7a7df8d, 0x5bba6517,
2910 0xe52a42fc, 0x3c744f97, 0xaceb869d, 0xdf93fbfa, 0x966ffe41, 0x41c6a39c,
2911 0xa0977cb9, 0x74b7773a, 0x575559bb, 0xbacad2f2, 0x8f391099, 0x7e7802e7,
2912 0xe79af969, 0x89f57780, 0xc2d2fe5b, 0xdd6f8bed, 0x2eaeeb07, 0xaefb25e8,
2913 0x8c8588fd, 0x44db5fa8, 0x71a1dfd2, 0xadd6f5ff, 0x77f29f50, 0xd31f9bbd,
2914 0xb239274d, 0xece5c4c8, 0x70fa7d94, 0xff719cbe, 0x615776dd, 0x08797cfc,
2915 0xdbd200e4, 0xe18a9f94, 0x79f479bc, 0x5cde6d54, 0xf36b8fc9, 0x029c78e6,
2916 0xf2cdf1e5, 0x1c3f0ae6, 0x49cf84b3, 0x1fb7dd12, 0x45f279e1, 0x2f6e45c7,
2917 0xfc4e44dd, 0xe3d6e116, 0x107b1efe, 0x6427dde3, 0xf6b89c6c, 0xafbc3ac9,
2918 0x012293e1, 0x93ec2033, 0x58f2c66b, 0x2287707c, 0x659cf02f, 0xef5f645e,
2919 0xd7092f71, 0x5dbe0d91, 0x1ceab0f4, 0xd5e5ff68, 0x49f0f98d, 0x419eff0b,
2920 0xfcb4cf2b, 0x67928ff2, 0x0f0ee315, 0x7ca9d809, 0xcd4bcb19, 0xe568ae5c,
2921 0x14a7581b, 0xe4e55a87, 0xa5c0a2f4, 0x5fc57785, 0x3f3058b3, 0xf5177e1a,
2922 0x94efa15b, 0xf8acbe50, 0x260b2e6b, 0x50fea37f, 0x3f8635b2, 0xf095fa04,
2923 0x07d42815, 0xfd408fd1, 0xdb46fd8f, 0x0025c95c, 0x96673ad2, 0x2772e515,
2924 0x416b7fe8, 0x6a313e24, 0xe50e8357, 0x376fd845, 0xc577fda8, 0x72b2c95f,
2925 0x795a31ba, 0xddfc98fd, 0x5df3bc4f, 0x3c4af8ca, 0xf184bea4, 0xb91273ef,
2926 0x839ca6fd, 0x3967eb5c, 0x933e3df8, 0xd26bc3bf, 0xc8f0eff1, 0xfcf5c4a7,
2927 0x83fdc8d8, 0x5c5574bc, 0x29bf09f0, 0x792def07, 0xf7a4efd2, 0x53a7f29f,
2928 0x8bbf23f9, 0x79fc67ca, 0x135efc39, 0xc7c8fe46, 0xd18d2c87, 0xe49b04e7,
2929 0xb093cdbc, 0xd062d7de, 0xe55623e1, 0xf497a03c, 0xd8d2c2db, 0x567bfdf2,
2930 0xe4a5e13d, 0xa087fbf9, 0xc1f1f1dd, 0x097dd1ef, 0x83e26b1f, 0x6e6f250b,
2931 0x13f37d2c, 0xc9379f99, 0x32c7e5fa, 0xfd900d7f, 0x9e729047, 0x4f78d1e6,
2932 0xff773f30, 0xc31dfcac, 0xa9abfd4f, 0xf3cad3bc, 0x8ff76923, 0xf0073b7f,
2933 0x3f036e75, 0xa4ce749f, 0x6cf3bf23, 0x85bcadad, 0xfd8ef0e0, 0xde76511f,
2934 0xf1dc329d, 0xfd6355d6, 0x057e726a, 0xdea072eb, 0x876fd30a, 0x5c3e1e3a,
2935 0xfa432df4, 0x695d66eb, 0xe846afd8, 0x2315ddcc, 0x79209b8f, 0xff84ac6b,
2936 0x5f28219e, 0xed02fd95, 0xfefa2a31, 0xe72b228c, 0x7ce38fcb, 0xa65ab6ff,
2937 0xcf25dbdb, 0xfa9e3e6a, 0x195fc37e, 0xf2b43f3d, 0xb4ffe678, 0x8c02f9ca,
2938 0xce4894df, 0xdb9d7c70, 0xd635dedb, 0x78997118, 0x8e16bf7e, 0x9e9c6c5b,
2939 0xa500f1b4, 0xcf01e254, 0x65044da0, 0x7049d5a6, 0x1803e36b, 0x07158d27,
2940 0x8f2b4ff8, 0x3c7ba61f, 0x9f15d5a2, 0xcef8272f, 0x6c9b7dd0, 0x7bf3a336,
2941 0x0e9b8a03, 0x60643c62, 0xd90eb059, 0xcb513ea5, 0xc63301a7, 0xba7cb249,
2942 0xa4dbcc34, 0xa33f0275, 0x6a9781bd, 0xd69d22a5, 0x4f5d21d6, 0xf168e9f0,
2943 0x412c3a13, 0x54e67141, 0x660266e7, 0x0bfeef39, 0xda82f3c2, 0x1db718b5,
2944 0x797fbcb4, 0x9f7936f7, 0x84d9bc95, 0xc3c206ed, 0xa63fed84, 0xed84d6fc,
2945 0x2885eb77, 0x35693efe, 0x878bff50, 0xff250e97, 0xaa39ce38, 0x26dc794e,
2946 0xfc417bc4, 0xadc710f3, 0x8879f8df, 0xb8a8d6e3, 0xab8af54a, 0x5a77c724,
2947 0x39f8feb9, 0x9f0169e6, 0xe4a05f3f, 0xfe291b69, 0x9a6a5bb6, 0x40887986,
2948 0x43ce8eb5, 0x0bdcf386, 0xf08f79f8, 0x86ef98fb, 0xe2af3fe7, 0xc181eef9,
2949 0xf6df2967, 0x03e79999, 0x6461db3f, 0xf25d2798, 0xefe51376, 0xb1d72cb6,
2950 0xc364f758, 0x9cf9064c, 0xefcf018e, 0x7ca3fee0, 0x081df653, 0x08fdc24b,
2951 0xf9b5c3e7, 0x8bae193f, 0xe9723e72, 0x4869e6ce, 0x93cb1927, 0x563fbc04,
2952 0xeaebeb81, 0xbf506f91, 0xe5f7975e, 0x6f55fa66, 0xb55fa18b, 0xe0d3b57a,
2953 0x6f52da31, 0x641b5fae, 0x2ab5eafa, 0x78e406e7, 0x6247e637, 0xd633cbec,
2954 0x34ce713e, 0x738857db, 0x3149adfa, 0xf7ca9ce3, 0x6c490d9e, 0xfc18ccee,
2955 0x37cc98f0, 0x743dcdba, 0x4da5230e, 0x4a972988, 0x17c94924, 0xc545b08d,
2956 0x35f2b5c7, 0xd8dd7e06, 0xd0aec47f, 0x3e35ec21, 0x668ac731, 0x9c73e000,
2957 0xf2719f0a, 0x9533bf0c, 0xe4a27d90, 0xd49a2e15, 0x6c77dbf6, 0x6dcf3f4a,
2958 0xc4b78fb8, 0x6c53db91, 0x297f0282, 0xc5594bf6, 0x2572f154, 0x1b529e4e,
2959 0xaffbf010, 0x3f230f14, 0xafb26862, 0x7afd00ce, 0x36f73126, 0xe83c27a8,
2960 0x9779412c, 0x883ee554, 0xcbfadda1, 0x0fcaf7f2, 0x395efa33, 0x65f5ef9c,
2961 0x7883bd91, 0x4f0efe8f, 0xfaca0fd1, 0x6bdd6f40, 0xb2cd70e3, 0x7d6f40dd,
2962 0xcf317c83, 0x58be3fd6, 0xf769708c, 0x81ef1b2d, 0x7fd98d4a, 0xb0feac45,
2963 0xd9fdd5cf, 0xbc720de7, 0xa4f9bfbf, 0xf5f0bd46, 0xf17de5e2, 0xbc2c44f2,
2964 0xe5d0a86c, 0x009479e1, 0xe963b8b3, 0x7fb62d9d, 0x8b7edc78, 0x9edc462d,
2965 0xfebf24dd, 0x49773fe2, 0xe2560f18, 0x507b61cf, 0x9e575793, 0xf909b757,
2966 0xb49597e8, 0xb7fb235f, 0x64e7e0fb, 0x8fcdf6ff, 0x025779f3, 0xdc7f2279,
2967 0xbf6f9f25, 0xf7fb95ba, 0xa4fd7322, 0x39a8e018, 0x6841606a, 0x606f8abf,
2968 0x882116fb, 0x3d5f0bf7, 0x8bea853a, 0x192c09f7, 0xe9e02409, 0x160cefc4,
2969 0x425e3e30, 0x8f754e91, 0x7d47a275, 0x7972784f, 0xea9eaa92, 0x3e13df55,
2970 0xaa967660, 0xa46fa07d, 0xd5507daa, 0x96fd5578, 0xe13df55a, 0x457f4143,
2971 0xd30333d7, 0xd7b3fd55, 0x0faaabdf, 0x13df506b, 0xcbadf8ae, 0xdf0cf5e4,
2972 0x2f7d4f32, 0x61084877, 0xbca163be, 0x38e40bdd, 0x52e088c5, 0xc4cb38d5,
2973 0xbbf0470d, 0x57de9b8a, 0x7448dad4, 0x68afbdaa, 0x7d754ed9, 0x46fb89ec,
2974 0x5e0cf3f1, 0xc675373a, 0xdc5f8ea6, 0xc3035f74, 0x1abed6bf, 0x6afbd5d3,
2975 0x886e5976, 0x7a9e6b37, 0x6f7c999f, 0x766f168c, 0xbfff7ab7, 0xed19bc69,
2976 0x0c193c6a, 0xe31d8b3e, 0x44abad80, 0x5cb2defa, 0x4bee4e7d, 0xed93ddc4,
2977 0xcaeee231, 0xcf376abd, 0x0dffb4a7, 0xd04664f3, 0x173c0634, 0x8536e455,
2978 0x48e627f3, 0xaf2b5d9c, 0x75e41294, 0x2af29d8e, 0x5ad3bc91, 0xff21df86,
2979 0x2b708bde, 0xf7588979, 0x05ce6880, 0xbe71c68e, 0x4d0afdea, 0xd240e7f8,
2980 0xae76f983, 0x51ec0b07, 0x8739507a, 0x78c1e8a2, 0x897928e3, 0x4870a578,
2981 0x0f44b8a4, 0xc86257e6, 0xbfdb6ff1, 0x7be93ea6, 0xf6dbf38e, 0xe0bf2882,
2982 0x5047bdfb, 0xefde039e, 0xedd9f5c5, 0x888527a0, 0xd589fc9e, 0xf3d3fc41,
2983 0x3c38311b, 0x48be7233, 0xe1689fc9, 0x0f7cd62d, 0x87b9a6d9, 0xb73c7eb4,
2984 0xb9dae63b, 0xdf2c3d5e, 0xd7235143, 0x7a76346b, 0x8fee7acd, 0x6d15bde2,
2985 0x8d5ff651, 0xe7fd4edd, 0x106a4be8, 0xf70b46ee, 0x8105eaab, 0xa67d78f4,
2986 0x6e3ef340, 0x71f6a52a, 0x5c6a92f6, 0xacb930f7, 0x2a5e58c1, 0xed443bdd,
2987 0x5efb1892, 0x6e765582, 0x7896cf2f, 0xddfd2fff, 0x0ee60ad4, 0x9bbe44a5,
2988 0xd3be7162, 0x3d83c6d7, 0x140ece79, 0x3bf55f8b, 0x9a1fc42a, 0x3f1d0ade,
2989 0x43e70f63, 0xfaf9fbe8, 0x66e7aecc, 0x109ebee0, 0xdb1e78dd, 0x1d602a75,
2990 0x57c7829b, 0xa02256f1, 0x8d6cad93, 0x038bea19, 0x18f78a2e, 0x8fb25fc0,
2991 0xcbddf08f, 0xc7c24cf6, 0xd3219398, 0x789f6858, 0xe3107bca, 0x58b3b9c3,
2992 0x06ed8a12, 0x7f0530d6, 0x55b0291f, 0x5ab31bce, 0x19abfdfa, 0xe8a52b25,
2993 0x5ba94073, 0xe2f3a61f, 0xf87579ca, 0x28fc4167, 0x9e47dff7, 0x4338f3f3,
2994 0xe32f654d, 0x98e5297e, 0xc578ec60, 0xccbbf96c, 0x5ddef587, 0x5a63dfb8,
2995 0xbddee8ba, 0x5b1c8ac5, 0x9defa3a0, 0xe1f793ef, 0x0f3cadbe, 0xbf5daecc,
2996 0xce46162e, 0x0cf8c1fd, 0x2cf173f9, 0xb3bbdd3b, 0xbe932db8, 0x815e668b,
2997 0x6d351be2, 0xbf497b6f, 0x44e0984c, 0x01f3d37f, 0x4b7ef013, 0x039701c4,
2998 0x952efbea, 0x95efd37b, 0xa77ca7d7, 0x8372f20a, 0x78bbf015, 0x81a1dd6b,
2999 0x2f7bde30, 0xa18fba31, 0xf240acf0, 0x37168981, 0xcb85edda, 0x05cfba04,
3000 0xbdd1f40f, 0x6d862314, 0x7e3b8e8b, 0xb78bcb2a, 0xe5a078fe, 0x9c297404,
3001 0x2a48f952, 0xfda768ec, 0x5dfc54c2, 0x95fdc2a8, 0xa338648f, 0x7b2a9bea,
3002 0xde11bb07, 0x80cb530b, 0xe760fe4e, 0x85d74cf0, 0xd9bbfcf4, 0x543fca4e,
3003 0xd20f24d8, 0x9d2d8569, 0x80ae37ee, 0xf400bdad, 0xdfa3fd35, 0x9f2e51eb,
3004 0x05f7cbb2, 0x5c5cb2e4, 0x77c3b267, 0x2accf89e, 0xaf10339f, 0x0fb68d8d,
3005 0xe539f4a3, 0xacdbba47, 0xf9586994, 0x3fe53666, 0xfbb4f795, 0xdf9f9cfa,
3006 0xf0ec9873, 0x57fdc79c, 0xfade81fa, 0x93ddeb1c, 0x1db97f3f, 0xfc52bdc6,
3007 0x17082197, 0x677e8fe0, 0x4ebfb941, 0x296dc719, 0x3f2762b9, 0x3f717986,
3008 0xf9e3936e, 0xbb6d9d93, 0xebb7dd71, 0x0e516b42, 0xa9fef9be, 0x28671c64,
3009 0x3eb8e078, 0xf5d573f8, 0x4570bee4, 0xbf7abee4, 0xf9f0a70b, 0xef2bbf0b,
3010 0x8bc79b9b, 0x500df7bb, 0x0eed8bc5, 0xbfb86fbe, 0xc0937fd4, 0xcfd9f1ef,
3011 0x937c564b, 0x9055fef7, 0x05824f7f, 0xe577e844, 0xc00fde4d, 0x66a87f21,
3012 0x13a270ff, 0xb3cb839f, 0x51e7acc9, 0xb6e4e75c, 0x87efa77f, 0xf2792b27,
3013 0xb93cea0b, 0xe2a59f0f, 0xf43d23b5, 0xb5f7701d, 0x63796fde, 0x43a95bf0,
3014 0xfbf0fbc9, 0x837ec3f0, 0xf87e1f7c, 0xec5342bc, 0x7197f0fb, 0x89f120ca,
3015 0xc52f0fdf, 0xe12fe03a, 0xe907f9ef, 0xc166c1fc, 0xb04c798d, 0xcfef5483,
3016 0x87ded3c8, 0xf17fefcf, 0xe3df93c9, 0xc91f33ee, 0x1e194adf, 0x5dff1b5f,
3017 0xcf3c0e82, 0xdeea7803, 0x51377fc0, 0x777fcf7b, 0x05b7e739, 0x4ba085eb,
3018 0x553bfba0, 0xd6650bed, 0x6776085e, 0x3cec9328, 0x3dc477cd, 0x5c5f6c5e,
3019 0x041befcc, 0xded34fbb, 0x754fe0a0, 0xf961ec4f, 0xfe1671f7, 0xf237d658,
3020 0x64f32fbd, 0x590f31f8, 0xaf591692, 0xf9147fa2, 0xe16050b9, 0x1abee9f7,
3021 0xed463ef9, 0xbb95e7fa, 0x36f3cf09, 0x761c6e08, 0xd067aff1, 0x078053f7,
3022 0x2f995e95, 0x837e73af, 0x6ff3e740, 0xb2a98f76, 0xeeb845ee, 0xaef6becc,
3023 0x50587ef6, 0x5f842e6f, 0xc6b1f990, 0x49afe1c8, 0x885f7466, 0xba25ec90,
3024 0x125dc780, 0xf83b0f94, 0x0de10b39, 0xe627c923, 0xf2937b05, 0xe44e6574,
3025 0x85058143, 0xcffaa3eb, 0x30fbe1af, 0xf842e7c2, 0x12c98efb, 0xc74cdbf9,
3026 0xca3b6dfd, 0xd223d01d, 0x4e10dac9, 0xf2b126b7, 0x67bc0731, 0x20f06aea,
3027 0x342e58cb, 0x2cdcb085, 0x3e7bbbc7, 0xaffc1134, 0x846cbe0b, 0x2a18a27f,
3028 0xe79af927, 0xee93341b, 0xcaf9e3af, 0x167f328d, 0xaefa06b1, 0xa26b3260,
3029 0x527598b2, 0xa1eb0779, 0xac5f83d2, 0xe03da364, 0x798cb2a6, 0x6aca9ca9,
3030 0x0d672ca9, 0x712b7e54, 0xc002625e, 0x51359d35, 0x39e402bd, 0x32890bdd,
3031 0xf74de319, 0xeecec89a, 0xac1cd37e, 0x0e6af800, 0x38bcb918, 0x577d2560,
3032 0x08466073, 0x1fddf9e3, 0x7bf85cd9, 0xa7b176a0, 0xbf48e29a, 0xf7f93ab6,
3033 0xbdd52e34, 0x2bb935dc, 0x78e3f77b, 0x7c7f421f, 0xbaad9e90, 0xafe27ba7,
3034 0x7a8f907f, 0xe1ade260, 0xe81cf27b, 0xcb6d5fcf, 0xcafe3f26, 0x9446dd40,
3035 0x5219d5d3, 0x7ab7e23d, 0x95ee8598, 0x05d3cee9, 0x415b2824, 0xe9fde3fe,
3036 0x05efe06f, 0xff26d940, 0xf901c05e, 0xde10f57e, 0xdab60eaf, 0x951e7f21,
3037 0x95377e1d, 0x5445fc47, 0xa87bf51e, 0x397f31df, 0x5efdc795, 0x9d1eaf2a,
3038 0x77c7df4f, 0x839e9fa7, 0xc87427bf, 0x19a4f951, 0xb28fe1f4, 0x44fc2e7c,
3039 0xfdf4eb08, 0x45aec0c8, 0xd508fdf8, 0xd7d67f41, 0xd19dd2f9, 0x555352ed,
3040 0x92ea1db8, 0x7008fdfc, 0x629e93d2, 0xea4527a8, 0x118dfdf8, 0xbc199ce3,
3041 0x57f3065e, 0xfb5220bf, 0x303f7811, 0xc72bd618, 0x2e094ca3, 0x03461f2e,
3042 0x74e18cbd, 0x7c65df83, 0xea99d5d8, 0x69762310, 0x4e5c13e5, 0xedc0be54,
3043 0xec67cace, 0x9eeef7f2, 0xef0d2132, 0x89cb511d, 0xf94c45f9, 0xbded13fd,
3044 0xea2c45a5, 0x83b9983e, 0xe60f2475, 0xd3f756ae, 0x4ce807ca, 0x95aad3bf,
3045 0x643a1f0b, 0x8d9733fb, 0x97faefc1, 0x1d93b1cf, 0xa76ec976, 0x763f7a73,
3046 0x0164a475, 0x44fbd5bc, 0x0ab413ca, 0xb5b07640, 0xeab8de7f, 0xced0136e,
3047 0xd7a7159d, 0xbeb1b8a6, 0xaefc49fa, 0x4ff352e2, 0x233aa4a7, 0xf4ec59f5,
3048 0xdda007c6, 0xddf56eb9, 0x2ffac0f7, 0xb8c0bd23, 0xfc0d5b97, 0x12939b1e,
3049 0xded32efd, 0x0b21af4c, 0x763f7bea, 0xa6ff3c33, 0x99bbf5e0, 0xbddbfbfc,
3050 0x2b41be99, 0xa7deab47, 0x1afd61df, 0x6bf133ef, 0x00dc2fbe, 0x8a7bed7e,
3051 0x7efbdb5c, 0xa77f0dee, 0x6dead976, 0xcea27243, 0x37d32c15, 0x658279d1,
3052 0x921e5fab, 0xa5cdf603, 0xe88d96e2, 0x7835ef77, 0xf942ef12, 0x71e06cd5,
3053 0xec904366, 0x89af4f80, 0x02466f34, 0x0609fbd7, 0x7c249f6e, 0x3d446a68,
3054 0x1382f603, 0x6bdcafbf, 0xa439f0e6, 0xc112572e, 0xc2c3ebc9, 0x86f1f1ef,
3055 0xf7b97025, 0xb25eb5e9, 0xd76e7ba7, 0x8082efd3, 0xc4faa07c, 0x6884523b,
3056 0x226f67bb, 0x8af3de7f, 0xcc52fd48, 0xf1e8c49e, 0x2f1debb5, 0xdcd7b7cf,
3057 0xc53f1aa3, 0xd653dfc0, 0xe36f9da3, 0x9de51324, 0x496e289e, 0xb2ebfcc3,
3058 0x207bfe12, 0x8abc3245, 0xa3f1357d, 0xe1a3dba9, 0xeeff289b, 0x26e4ceb0,
3059 0x557079fa, 0x7dfa38e2, 0xe297a742, 0xe71e73fb, 0x38f269f5, 0xe08e4520,
3060 0xdcb9e772, 0xf20cd153, 0x28657c39, 0x79e417b7, 0x8afd608f, 0xf510a7a1,
3061 0x24aab886, 0x33de0030, 0x9f495e3c, 0xd5d719f7, 0x6f34b005, 0xe1036468,
3062 0xcdcdc2f9, 0xa13df70c, 0x8a176cf9, 0xefe69499, 0xaf6d7c53, 0xd813a641,
3063 0xfe51998f, 0xa96736d7, 0xd7e60137, 0x391db939, 0x4245ac7d, 0x467a607b,
3064 0xf5f9d906, 0xcc1cc1a5, 0x308cf70f, 0x3a627c53, 0x9f80258c, 0xc5886c72,
3065 0xd412fe83, 0xcf58893d, 0xa7fd4c98, 0x86591d8f, 0xc658f87a, 0xb78c74f7,
3066 0x9e2bc7af, 0x5fc0658e, 0xc21fda0e, 0x8969cf57, 0x963eafbe, 0xf92a74b1,
3067 0xbd382315, 0x6c78cb1f, 0xd22bf62a, 0xc2cbee05, 0xf289a176, 0x70278fae,
3068 0x0c5d3f3d, 0x09efc71d, 0xcef819ef, 0x566ff471, 0xc77ec826, 0x622b9018,
3069 0x5c981fc4, 0x9f8edcd4, 0xde7b15cb, 0xeaea829e, 0xb73ff28e, 0x26f1e963,
3070 0x2f7aa196, 0x03ae3d9d, 0xccdf32cb, 0xe8731032, 0xf88e3caf, 0x70f55a9e,
3071 0x01ffd607, 0x88e3cafe, 0x55c992e7, 0x9f37fbf4, 0xa3e5dfdd, 0x7024e93c,
3072 0x7dc463d4, 0x4b09f622, 0x781af7e2, 0x485f5092, 0xdf7db86b, 0x7b244fb3,
3073 0x39751582, 0xea6e5c74, 0x33aafe90, 0x9e90d2bb, 0x38f207eb, 0x976715cb,
3074 0xfdf2ea83, 0xf322ff02, 0x57624541, 0xc561d21a, 0x9e0261be, 0xe1e2bd3b,
3075 0x56a04a76, 0x3061e7e4, 0xff2694cb, 0xd51678ee, 0x93fceec9, 0xfcf5ebc0,
3076 0xf3d676ee, 0x23ed237d, 0x2f10cf8c, 0xe30f0f3d, 0xeabe0170, 0xb92f5ef1,
3077 0xb983c33f, 0x52abf748, 0x87f21ee9, 0xfc24a72c, 0xe3302469, 0xae3e50d2,
3078 0xe276ca68, 0xef06cdf3, 0x15f71a4c, 0x96e389c1, 0x3c966cef, 0x2a4fd236,
3079 0x90f41e3b, 0x7ba7eed6, 0x3e32e687, 0xd126dcdf, 0x9aba0663, 0x03fcd2db,
3080 0xeecd2e81, 0x8ff7c832, 0x4d6bdea9, 0xfa9f74e0, 0x4fba66cb, 0x87ce1976,
3081 0xee81ab65, 0xab365d95, 0xf1443245, 0x3dd6b2cb, 0x577cafd4, 0xcbc5e533,
3082 0x2f64ecf3, 0xeb0d634f, 0xdf2d5f28, 0x53e3e457, 0xc9add3b0, 0x65003fcf,
3083 0xbe399fc5, 0x3efc53d8, 0x0f83f9b5, 0xbb2f91d9, 0xfc53960a, 0x942143e7,
3084 0xf8bd001a, 0x0ee76650, 0xc92e1ff4, 0x0fd68ef6, 0x0b1dfad1, 0xa2a7335c,
3085 0xdfd7d149, 0x38e8b660, 0xb03f168a, 0xdef11b1d, 0xa24d45a3, 0xd131ef13,
3086 0xfe0a23fa, 0x953f78b4, 0xc7db2290, 0x3f706320, 0x20eca69b, 0xfa71933f,
3087 0xd6017b20, 0x987dc971, 0xd39ab3ee, 0x6279efc4, 0x8a14a13d, 0xb3f06b03,
3088 0x8cda1f41, 0xd60549f7, 0x02fee819, 0x5c02fe1f, 0x8dfdac52, 0xec4a27ba,
3089 0xeb2d3f5b, 0x5bcf3ecb, 0x7a775fb9, 0x1b9f28bd, 0xdbcfb751, 0xb3247f97,
3090 0x26fbe31f, 0xeed27df0, 0xcfd002c7, 0xdf8217e4, 0xafa97287, 0xdfa5e85f,
3091 0xfed9b883, 0xdffff828, 0xc7a90a29, 0x00008000, 0x00088b1f, 0x00000000,
3092 0x7dedff00, 0xc554780b, 0x3d9cf0d9, 0xcd8dcd7b, 0x09c246fd, 0xb8094404,
3093 0x9fb1dc24, 0x4a34021b, 0x414045d0, 0x2dc8d812, 0x088d9242, 0x59b6b696,
3094 0x5a4062e4, 0x7da5aac1, 0x2c142ea8, 0x11a0d05a, 0x86ec5d43, 0xba8b4508,
3095 0x8ad45cb1, 0x14178026, 0xb16d0042, 0xfbdfad1f, 0xbb2733be, 0x6a2364e7,
3096 0xffefefd5, 0x27a3cbff, 0x9cccce73, 0x997ef799, 0x6318c399, 0xb17fc39f,
3097 0x50dff876, 0x261d8ac6, 0xd8c21b27, 0x4fab569c, 0x8a6c61c9, 0xef74676b,
3098 0xa79cc624, 0x18564c0d, 0xedfd2e6b, 0xd543262f, 0x8ad79b24, 0xcb7693f7,
3099 0xcd942f0e, 0x3b58eef1, 0xdaf4b7b4, 0xd5f6c468, 0x512c490f, 0x6724ac62,
3100 0x618b126f, 0x9b0e576c, 0x7783cae5, 0xd0daefe1, 0x950ed135, 0x6cdb1992,
3101 0xfb622577, 0x1b32dee7, 0x1ec60f58, 0x87f5e78c, 0xe3db99bd, 0xfd5098b6,
3102 0x687f5841, 0xd5b23ca8, 0x467f58c0, 0xe8c79c3f, 0xb318a30f, 0xebdfca86,
3103 0xaf94d048, 0xa9a198bd, 0x68fac85f, 0x0759179e, 0xb38f9e68, 0xdfca6817,
3104 0xa9ad1b4f, 0xa4529d7f, 0x3fe84f29, 0xa27f5341, 0xbca6b263, 0xeb8ac8d6,
3105 0x63675e61, 0x8f4b5e8c, 0xd8463cd0, 0xb787040d, 0x478702d3, 0x683b584b,
3106 0x8576c572, 0xa98d5957, 0x7dec35a3, 0x9c38da0f, 0x819c5d58, 0x4eec630d,
3107 0xffa899f5, 0x58df0143, 0x7be0d599, 0xdd46a303, 0xb5bc046f, 0x160d941f,
3108 0x42f32fc0, 0xcec614bb, 0x1a17768b, 0xbe207a0b, 0x7f7e01d8, 0xdfdf8d91,
3109 0xded1f025, 0xc335e0df, 0x816b5bb8, 0xde85fa26, 0x660c56e3, 0xdd7e1843,
3110 0x8259b28d, 0x730370f2, 0x17dd7be3, 0x1059cccd, 0x5163071a, 0xde76bdfc,
3111 0xe64e3abf, 0x8defe68c, 0xaedff7e7, 0xec62e245, 0x5d2b5a9d, 0x82cf0e7f,
3112 0xc0633e38, 0x691fa0cc, 0x34f8cc74, 0x06f6b7a0, 0xfa016ec9, 0x366c6cac,
3113 0xed17f8e3, 0x316549cc, 0x5ea7e15d, 0x31a6d78f, 0x5aabfa05, 0xd52ab2dc,
3114 0x1f6ef401, 0x682bf752, 0xe303555f, 0xb1a91200, 0x965bab0f, 0xbb62d8cb,
3115 0x6716f442, 0x7f43f981, 0xbff4feef, 0xf0073ccf, 0xd4b3fe3b, 0xfd07e47c,
3116 0xffb559f3, 0x17e8f4fc, 0x27f77f3c, 0x83f63f7f, 0xd3ff6a2f, 0x65fbdecf,
3117 0xc6eef3d8, 0x932ebb3f, 0x30746129, 0xace1cccc, 0xe90cb7af, 0x3b3ffa0a,
3118 0x358f1fea, 0xb2497f43, 0xe01d997b, 0x27cd7edc, 0xc51e0cd9, 0xcc34bf0e,
3119 0x37e2131d, 0x095ffb7d, 0xb1bc037e, 0xfb338018, 0x15b7cd81, 0x0ddf06e9,
3120 0x924b63e5, 0x5e906b7d, 0x669ac15d, 0x95b1f718, 0xe06b1c7d, 0x0ec7e53d,
3121 0x86f7338e, 0x2f3cb1f2, 0x24cbfbc3, 0x2cfb8307, 0x3a446acd, 0x5703899d,
3122 0x2b2ef868, 0xd31674e0, 0xf9d02dd2, 0x7c61adfb, 0xb6a96b33, 0x96d5ee5c,
3123 0x61fce387, 0xd899cf1e, 0xbc30fab4, 0xeffcc4fb, 0x047c2f89, 0xce3b8be5,
3124 0x5376e54e, 0xfac85dc7, 0xbfb4f58c, 0x81fa2d1f, 0x32008e39, 0xb7b2f1c5,
3125 0x9fcf34ac, 0xf89183e1, 0xf2266f3f, 0x4f82dbe3, 0xd6c4c4cf, 0x6707c049,
3126 0x6f070e14, 0xd2e1cc8d, 0xed056013, 0x6e2777ab, 0xdfc0b822, 0xb3ee5451,
3127 0xa4c7cb19, 0xde17b240, 0xfb07265b, 0x28cffbe2, 0x1d630fad, 0x4668e2ef,
3128 0x53b491ed, 0x10fa7c04, 0x30f3148c, 0xe7801f01, 0x69d946cc, 0xf1f0441b,
3129 0x29a3e0ea, 0xa8d0fe8f, 0x43af7f29, 0xa2f6be5b, 0xb4c85cb6, 0xdaac8bed,
3130 0x8e02cbf2, 0xfbdaece3, 0x96d34fdf, 0x1e3a55df, 0x1d8bf2e2, 0xf3c30dca,
3131 0x259521cc, 0xcfe00e2c, 0x179c66ec, 0xb864f78c, 0xc11e2b1c, 0x3adb78e1,
3132 0x21cbe7c9, 0x5f9e6afc, 0xecab1cc7, 0xdaf74879, 0x418bf0fb, 0xe82b9a7a,
3133 0xed3aee67, 0x19dfebf3, 0xbc019e35, 0xe325d84e, 0x207f78fb, 0x4e78881b,
3134 0x419f738c, 0xc744f03e, 0xc37d420d, 0x46b9ede4, 0xabd9ff78, 0xe3990e6c,
3135 0x3b21cb81, 0x3938ff1f, 0xe7c011c6, 0x058768fe, 0xd3da2d6e, 0x8fe51527,
3136 0x37cf5eda, 0x52dc800f, 0x9c7be1fa, 0x99af4867, 0x25d20559, 0x28fa021b,
3137 0xe4c2c81d, 0xf6878f8c, 0xceb71dcf, 0x3be04772, 0xef955ce0, 0x77c8259c,
3138 0x35f4e63f, 0x1ec8cda6, 0x352c71c7, 0x9c20b26d, 0x8fc427eb, 0xb999fa03,
3139 0x5b9df38c, 0x3064ac0a, 0x647b99bf, 0x25cce782, 0x44498f92, 0xf435e72f,
3140 0xbea0f022, 0x5e71f00f, 0x329a5fc7, 0xfdd12850, 0xecc62683, 0x678ebef0,
3141 0x1466df25, 0x648d53d9, 0xbb6d542f, 0x337047c2, 0xef1117b2, 0x2a8f816e,
3142 0xa81e2323, 0x0658fe04, 0x4bd4e7f5, 0x178fae34, 0xa8067c5b, 0x261db55f,
3143 0xae3fcf08, 0x2824f931, 0x3328dc7f, 0xbeb10fce, 0x7db550be, 0x7c2f2f3b,
3144 0xf82d96fc, 0xff3c5dbc, 0x2db8fb78, 0xa2b5bef8, 0x9062ef7f, 0x6ddf504b,
3145 0x3e6b5664, 0x0259b75c, 0x63b7a076, 0x4757f651, 0xe8ed3d21, 0x3e0cf0f3,
3146 0xc618c524, 0xab59c74f, 0x85d0e109, 0x9f03b69f, 0x2be575c5, 0xa0f1d237,
3147 0x50b9f4ae, 0x839039aa, 0x9267e372, 0x95d2ab63, 0xa974f54e, 0xc17cedd2,
3148 0xd9b3d01f, 0x1bca1035, 0x1d38f5f4, 0x1fd635ac, 0xb9e715b9, 0x3bfea642,
3149 0xb71009e7, 0xdc2d4902, 0x28c8f7d1, 0xdabe5e78, 0x32efe884, 0x33f3aecf,
3150 0x6ce6fcd1, 0x673274e7, 0xa453e4a9, 0xcfd5f3ae, 0x98bccbb3, 0xa63d956b,
3151 0xcebafceb, 0x218fd383, 0xf1104876, 0xa2d1be75, 0x9dd1fda0, 0xab5d3b7e,
3152 0xff411b64, 0x675adbb6, 0x238c0732, 0x2575bb7e, 0x907688c8, 0x179fa8c1,
3153 0xec5ddfac, 0x2d39be05, 0x4a6f7971, 0xf95874e6, 0x5926ea74, 0x6953f50a,
3154 0x4073f40e, 0x15e3bbbd, 0x81a56382, 0xc1fa09eb, 0x4e0f4e38, 0xc606bcd8,
3155 0x856de601, 0x32679fa6, 0xe361c937, 0x8604b4ab, 0x3b41fa69, 0x7c9fbc26,
3156 0x1c19cfde, 0x9fa85e4f, 0xf1da5daa, 0x9a839954, 0xfb0954f1, 0x0ce7ed48,
3157 0x9fea078e, 0xf784f1c1, 0x3c769cf3, 0x66a09655, 0x769d553c, 0x9f27e895,
3158 0xae55d3f7, 0x73f634f8, 0xb64e7d55, 0x2b4f0c31, 0xfb1631af, 0x0f4dd822,
3159 0xbff973c4, 0x7ecd9b70, 0x557eac32, 0xeca6bc7d, 0x9fb74c69, 0x859fa30c,
3160 0x3bc807f8, 0x032418b6, 0x314ad3c8, 0xfbb291c4, 0xa3d47881, 0x011faf49,
3161 0x5b559a0b, 0xa748cc3b, 0xfcfa5d8c, 0x865861f3, 0xcf1c653f, 0x38450394,
3162 0x1d93469f, 0xf00cfd59, 0x71e017bf, 0xf5f061c6, 0x7fddf986, 0x119b83e9,
3163 0x4dbb313e, 0x7940f709, 0xab45e3ad, 0xdb5fe302, 0xe5f62a68, 0x67dddea1,
3164 0x5f261d9d, 0xfdb93ad7, 0xeb019ccd, 0xfba181e4, 0x8f5f8331, 0x0cf17b43,
3165 0x5e2316b3, 0xd6031ad7, 0x587061c1, 0x3eaa2a0b, 0xc5765c02, 0x5fd744cb,
3166 0xb54b2e1b, 0x01e15170, 0xf085d9f0, 0x535b58f1, 0xffbb4ed0, 0x6871e39a,
3167 0x360d15a7, 0x9ca7a44a, 0x9721e912, 0xabaff39f, 0x0d7f2644, 0x08525626,
3168 0xf441bbf0, 0xfa0ad677, 0xdbf06ae9, 0xd885091c, 0xbc71c6ee, 0xd2f978dd,
3169 0x9e50c9a1, 0xca993dfc, 0x4d99eeaf, 0xe2600d72, 0x27bc0008, 0xbf258d4f,
3170 0x3863fa0e, 0x9fa8a9be, 0xe126d481, 0xa937682d, 0xe005f258, 0x308e377d,
3171 0xf3e70f1d, 0x796d4e49, 0x0cb6b172, 0x335f91fd, 0xafbda5d5, 0xe28759da,
3172 0x07de9363, 0xb1458c17, 0xfed1cf8c, 0x6632fa11, 0x1f6b5ef0, 0x11d9d718,
3173 0xebcd0766, 0xeca9dfd2, 0xb6c0c6bd, 0xa7337b62, 0xb28d9ffb, 0x84e796fa,
3174 0x443dfbd3, 0x030e4db7, 0x37fb6133, 0x9bd43e2c, 0xbb33db7f, 0x77a08b17,
3175 0xd198ed43, 0x35e34690, 0xdcfeb832, 0xfd8c51d4, 0x067bfcff, 0x8ffa0cb6,
3176 0xfb76651b, 0x27bfb422, 0x4231f85e, 0xef072dde, 0x2f2dfd0f, 0x256c728b,
3177 0x3f2148bb, 0x58b7f54d, 0xab2a1f5a, 0x340c967e, 0x34fa4419, 0x9e3d1076,
3178 0x81e9f7f7, 0xe68d8ce3, 0xa07f3c78, 0x2f6e1ed9, 0x047fa234, 0xd01fc676,
3179 0xa36b823f, 0xb5fd7fb0, 0x00bf2a76, 0x035e0e7e, 0x4ff90ab5, 0xd3fb6b7b,
3180 0x075ac5f5, 0x8ed7f75d, 0x5a81eba0, 0xb97bd527, 0x07ae98b6, 0x75745d6b,
3181 0xf9f025c7, 0xec5db918, 0x920afe79, 0xdbafe073, 0x88e28612, 0x3e20066b,
3182 0x793e3bcf, 0x0af0b7f2, 0xafd3a8cf, 0xacf5c116, 0x735771d4, 0x3ff9fc98,
3183 0x3f074fcd, 0x7fc71728, 0xef5d7f39, 0xb73d542f, 0x70179763, 0x87a9e0b4,
3184 0xfbcc18e2, 0x0a5d7194, 0xadcae1ca, 0x709ce32b, 0x0e3bb305, 0x9f29e1f5,
3185 0x3e891c5c, 0xfa54134a, 0x2848c670, 0xabe718e7, 0xefb89e8f, 0xbfabe406,
3186 0x51d9356d, 0x7ec0785f, 0xae7e80b1, 0xf89db86e, 0xbc6dca12, 0x1939ef7c,
3187 0xfe5a8dcb, 0x87bbf059, 0xa2589452, 0xb74e4cbb, 0xdba44c81, 0x8def2dea,
3188 0xb0f23a47, 0xfad3d20e, 0x8bfef876, 0xbd4f7a00, 0xbd7e8e5c, 0xffcab9fe,
3189 0x9eae411e, 0xc9cefb86, 0xab57f871, 0xafaef119, 0x0e34815f, 0x41313c7c,
3190 0x3670f1f0, 0x156ded1c, 0x4c97cc1e, 0xf73f2cfc, 0xa86d419b, 0x39fcb7bf,
3191 0xcaebca4e, 0x67ebe7af, 0xa507fa3f, 0x176cfe7b, 0x6bd7af74, 0x200c234a,
3192 0x7e7e8a15, 0xe20534ad, 0xb9fda346, 0xacf244c9, 0x1f6fc772, 0xd3da35fb,
3193 0x7d1c5a6f, 0xf69bb415, 0xe505191d, 0x494d3b85, 0x311a7c25, 0x2f084a52,
3194 0x696ff81e, 0x0b0f087e, 0x5667d99e, 0x77fbf206, 0xb1f08427, 0x99936770,
3195 0x8f0aec0d, 0x7326faa2, 0xbc044c6b, 0x478db7d4, 0xfb9f96be, 0x7ef119a7,
3196 0xa58905ea, 0xe78044e6, 0x6e717da6, 0xa3c22701, 0xde2753c0, 0x803df574,
3197 0x1553a417, 0x57e7fa4f, 0xc67a7027, 0xa23c94fe, 0x00ff27e7, 0xcb78a9f0,
3198 0x57f9c0e2, 0x1c67793c, 0x6303e3ce, 0xdfeba70d, 0xc2714cac, 0xde4c2b7b,
3199 0xf95d3b14, 0x96478afd, 0x6fcdbd10, 0xc8c29259, 0x1ba670ee, 0xd33cd046,
3200 0x37737e71, 0xcdf9a54e, 0xbba26e63, 0x2ec8df8a, 0x353e2bb4, 0x119de2b2,
3201 0xc175e2f8, 0x066c1f17, 0xfbf3046d, 0xef73c840, 0xcb8fb2eb, 0xca183bcd,
3202 0xdcaa25c9, 0xfca88b64, 0xe9e395a9, 0xe08304f1, 0x70f2e02b, 0x6f72dd7a,
3203 0x51f3f110, 0xfd153396, 0xbf030f47, 0x7d21f797, 0x2dcafd0e, 0x7e3952e3,
3204 0xed4cbdb8, 0xc2290ec0, 0x683f58fb, 0xac3b7f22, 0x273cfb1d, 0xe2c5fef4,
3205 0x28ee30fd, 0x07f3e409, 0xd36edc29, 0x095fefcf, 0xbf028e3c, 0xafa30b20,
3206 0xfce6fe30, 0xe73565be, 0x7ddf956f, 0xf9f18a93, 0xff388727, 0x7cccbb60,
3207 0x9520571a, 0x914d379e, 0x58581e48, 0x6f5f1220, 0xd6be0931, 0x04e9573e,
3208 0x38c46dc6, 0x60bd2746, 0x7f0409ff, 0x3de787b2, 0xe4c2ed08, 0x17df07a1,
3209 0x953fb5d7, 0xfe0be76f, 0x3ff9057f, 0x6cffc43a, 0xeefbe723, 0xf097adf5,
3210 0x3df26957, 0x57e46bf6, 0x82af4fe0, 0xe1726afc, 0xdede3fbc, 0xf456e47c,
3211 0x3e55eb1b, 0x3d4fcad5, 0xbd3c569f, 0xcf53e88f, 0xefd71fa7, 0xa7c8894b,
3212 0xb4a5f73b, 0xd3e245e6, 0xaa7e56ef, 0x2754fbf0, 0xd879553f, 0xf2f51c1d,
3213 0x250481f0, 0xdf843ca2, 0x2bac3621, 0xa774a9fd, 0xdf82dbd2, 0xb942f557,
3214 0x2a9749d3, 0xa5d275dd, 0xf9fa774a, 0x7fa7e16a, 0x158047fe, 0xb90df9e2,
3215 0xf7da1863, 0x45b8c153, 0x03054dbc, 0x6b1f34a3, 0x4d5f11a5, 0xfef3e311,
3216 0xb7184983, 0x79c21241, 0xf4bff54d, 0x0df7be19, 0xdfa2f313, 0x2dcf767b,
3217 0xab57da0a, 0x990ead92, 0xe68f84e4, 0x5eec8efd, 0xb00f7189, 0x8e51aaa3,
3218 0xdb47f74c, 0xddb96ed1, 0x32709eea, 0x7f448411, 0x8dcbe489, 0x07b2656b,
3219 0x2e3c79ad, 0xf2611ae1, 0x9efa5fa1, 0x2be345c1, 0xfd5e1829, 0xf73d1a23,
3220 0xb93dd1cf, 0x2157c606, 0x8c3f87c6, 0xc2ceddd7, 0x0f5faa7e, 0x46bbce5d,
3221 0xa1c5440a, 0xe3b12c3f, 0xddb87061, 0xefe32da7, 0xfd4252bf, 0x777eae5e,
3222 0x5f4df47c, 0x3aba05df, 0x1b787e0e, 0xba7c8d5e, 0xcb3cf4e1, 0xa9e8e1cf,
3223 0x031fc894, 0x615c9bbc, 0x44bad57e, 0xbddef72e, 0xcce280bb, 0xec0ff785,
3224 0x2e6de5c1, 0x423cd7c5, 0x2af79e7e, 0xa8af503d, 0x03f9eef6, 0xe8efe445,
3225 0xe822d3c7, 0xdec22ffc, 0x5a563b3d, 0x9ddf0327, 0x3f641d65, 0xd8dac779,
3226 0x6f7e08d6, 0x7ea7624d, 0xd430f260, 0x86afea4b, 0x4f13b0f8, 0x329e276b,
3227 0x7f0aea0e, 0xe5571dfc, 0xc3effca0, 0xe109f915, 0x1d6b62d9, 0xcf308aef,
3228 0x4adc047b, 0x46667ef6, 0x3f937639, 0xb8f084c7, 0xb1acac69, 0x28947f63,
3229 0x2b0144e4, 0xec9571c0, 0x246e2ebd, 0xec80e3e2, 0x3d5c01b0, 0xf76673fe,
3230 0x11c3cbc0, 0xf5fb47fb, 0x0f31c984, 0x67e278e1, 0x3e05e636, 0x45c44578,
3231 0xf51391e0, 0x44e5741a, 0x225f7dfd, 0x9bbc078f, 0x4eb82768, 0x2534292e,
3232 0x1af37bc3, 0x6f3183ec, 0xbfea2191, 0xf3d0a89b, 0xad4ed14c, 0xebc95197,
3233 0xd5ed99b5, 0x23dfe691, 0x6a5f53b9, 0xdefb35f0, 0x0fe8cd3b, 0xabe16fff,
3234 0xc0d8fef0, 0x8d5f8c18, 0x746e4895, 0xfc4663a5, 0x63fc1e70, 0xfbcf13f4,
3235 0x7cf2bc79, 0x02c38f09, 0x735db93c, 0x8d764493, 0xf87ae74a, 0xabe0273e,
3236 0x28a8ffbe, 0x9db913fb, 0x8557c2a4, 0x6abc7eab, 0xd757907d, 0x1bfbcb86,
3237 0x293f071b, 0x2fc23e61, 0x55d00dd9, 0x8cd5b1b5, 0x5c69e77c, 0x667f426f,
3238 0x65fbc2ba, 0x29a0d746, 0x6ef37461, 0xdbde91a2, 0x267a3f9c, 0xb585c7d2,
3239 0x77f38616, 0x871739ce, 0x8315f37a, 0xc8d1b5e3, 0xe4caaf7f, 0xc707778f,
3240 0xafdad6bf, 0xef0c6b1f, 0x39c68737, 0x84d0b2b9, 0x654669ea, 0x8c352993,
3241 0x4c4dde8e, 0xfdeae7a0, 0xf2854a8c, 0x1a3ef062, 0x16e7f787, 0xd5e49bca,
3242 0xc344c707, 0xf13519f3, 0xc02afe9c, 0x8e72a6f0, 0xbea68f26, 0x5347cf47,
3243 0xe535a24a, 0x3dad45d9, 0x96252e11, 0x044762c0, 0xa926f4fa, 0xf535f9f4,
3244 0x37e81382, 0x5ffedd02, 0xab1617a7, 0x9355a17a, 0xa92ebecf, 0x8d485e8b,
3245 0x2d1617a4, 0x0f115253, 0xd165be6a, 0x2252e34b, 0xb5c385e9, 0x1472df3c,
3246 0xcf5e19e4, 0x70bd014e, 0x985e9875, 0xd13a2362, 0xba482bb7, 0xf1505e8c,
3247 0x99cb1df4, 0x2217a8c3, 0x24f8f5f0, 0xd9b85ead, 0xe17a4e5f, 0x533229e6,
3248 0x497df3c2, 0x56eefec2, 0x4ca6142f, 0x11c9b2a7, 0x106e811d, 0x3a17189e,
3249 0xf8eef22a, 0x3f0fd41e, 0xbc13b24e, 0x3ba27af4, 0x39799e39, 0x04bffe39,
3250 0x2f8e555f, 0xbd912a9a, 0x18ee95d7, 0xe9a2efd1, 0x16ade512, 0x7c72e1ed,
3251 0xf1c81951, 0xae45d61c, 0x0eae50ba, 0xbcab9709, 0xeb9bb57d, 0xce634f01,
3252 0xf9e14b2f, 0x0e4cebad, 0x35bfd42b, 0x85876724, 0x271fd9cb, 0x2b672375,
3253 0xe0bd9cb8, 0x45f1e82f, 0x4263cb71, 0xcafc82be, 0x8ba04475, 0x9ad1a569,
3254 0x06270375, 0x19ef29ff, 0x64578fe4, 0x27bc878a, 0xc1c1fdf4, 0xf6821a7f,
3255 0x0f1c61ff, 0x49b7efe0, 0x9f80ef5c, 0xe058fd71, 0xdc39a2fb, 0x2edaae5e,
3256 0x1baafc13, 0x6f57bf38, 0x3d0e2893, 0x3333ff3e, 0xf0f6ede5, 0x971a86b8,
3257 0xf0bff156, 0x9955d695, 0xc4937cf8, 0xfc0acce3, 0xcd87cb0b, 0xbf242c73,
3258 0xad06fe64, 0xe96250ff, 0x4aed8fd8, 0x3639277e, 0xec8bfc91, 0x7e89556f,
3259 0x3ed36e16, 0x16ac72af, 0xe48057fe, 0xf6bd5576, 0x5fc15ef9, 0xde40e573,
3260 0x7bcf9833, 0xd244764d, 0x4ebd6a67, 0x9bfc5478, 0x780168f0, 0xf0eaf90c,
3261 0x44dfddb8, 0x0baf9379, 0x5ffcfd07, 0x3e46e554, 0xf6fc821b, 0x7249c19e,
3262 0xcf32fbc3, 0xdf59ce3b, 0xfe3c3537, 0x8ba0bafc, 0x55ee0c57, 0x9aaf58e9,
3263 0x6fe73fe7, 0xca1a8704, 0x306cf5a5, 0x37f36efa, 0xa76bf568, 0x48506f3e,
3264 0xecd6975f, 0x43cb6e94, 0x5abcf3b8, 0xf8fd6f85, 0xb65e780c, 0xd437f414,
3265 0x716f9d9f, 0xc5a8fc63, 0x517241d6, 0x05cfcfa5, 0xe053fcbf, 0xc74644e3,
3266 0x8d3bd258, 0x2ef89d92, 0x087ae360, 0x728362f0, 0x8fbfc8f3, 0x5bb07817,
3267 0xde392f88, 0xe427803c, 0x517ef1db, 0xddf6e7ae, 0xee39ff0c, 0x4c9bfbff,
3268 0x91a2aed8, 0xa0236baf, 0x8c3be986, 0x84a61447, 0x1b4f73e1, 0x92adefa7,
3269 0xe0f86e83, 0xe7c197df, 0xdaa8f065, 0x9f165f23, 0x4f3e5c2a, 0xc0827e12,
3270 0x582d8b6b, 0xfc798052, 0x3363923d, 0x53c7f656, 0xbae4e15c, 0xd8df843e,
3271 0x3d578e64, 0x80dfa3dd, 0xf2d4a6eb, 0xfa201c24, 0x7636c5f4, 0x6f6f7d42,
3272 0xcb855f6e, 0xa3be351d, 0xbe6abf5e, 0x1482c3cc, 0x66f352af, 0x83f76523,
3273 0x7257a889, 0xa44f5a25, 0x4660cfe6, 0x40dfd7c4, 0xbe9313ff, 0x66967fa0,
3274 0xecedebe7, 0xe13b7dea, 0x6e5136e9, 0xb4761ace, 0xa17be014, 0xbae0764e,
3275 0xca0c5bb4, 0x9e506b91, 0xe43131ac, 0x4d070b8f, 0xa3df2e4e, 0xbf949f49,
3276 0xfa84c272, 0x82731cb0, 0x09ffc798, 0xc4271bd7, 0x3d02de78, 0x2898c4ec,
3277 0x093a1fab, 0xd1c53fde, 0x9cf30e34, 0xacb48753, 0xe4ee38c4, 0x2391fb22,
3278 0x32d5cf88, 0xaf1e7c43, 0xeb3f222b, 0xe2243bce, 0x6f0037af, 0x94ea7ed8,
3279 0xe047239c, 0xc97565bd, 0x75295314, 0x0d3cdf26, 0x6507a5ca, 0x66f50287,
3280 0x831b18df, 0xfd09d7f1, 0x830ee665, 0xae0b194f, 0x6957f8c4, 0x71531dcd,
3281 0xe7a015dc, 0xe15d1f30, 0x8a97196f, 0xb5128de5, 0xe6dd78f7, 0xe09d2054,
3282 0x21e67386, 0x5079fef0, 0xd9eec10f, 0xb679ebc8, 0x754c0e48, 0x27aff3cd,
3283 0x8b6f3879, 0x598970c4, 0x2b58ec10, 0x8567d7ef, 0xa11b837e, 0x63e7943d,
3284 0x4b77ec7b, 0x90d3cdfc, 0xd49c618f, 0xfdb2c47e, 0x41e72f28, 0x82cc783b,
3285 0xfea0ee5b, 0xb128df6e, 0x62afe834, 0x47cfce44, 0x4d077f60, 0xb47e7c0e,
3286 0x671457e9, 0x4bef099f, 0xcb67fe87, 0x9d68e3ad, 0x3b258fd7, 0xb92abbad,
3287 0x5677f099, 0x9b4b19f0, 0x47baf64a, 0x6f3daa62, 0x3edb8f0c, 0xe89bdc96,
3288 0x65d2de78, 0xad5e70ab, 0x031ce4de, 0x5a39d5d1, 0xe0127897, 0xf43b06ed,
3289 0x83c79984, 0xcc27bd9b, 0xb37261ad, 0xf10fb939, 0x42c69ce5, 0x3aea2f92,
3290 0x6e32f70a, 0xb4adb467, 0x36987ad1, 0xef1b3d93, 0xd0b4af37, 0x5c1df6fd,
3291 0xb567b4bf, 0xdc7e83be, 0xcc4d1b07, 0xbe5c630b, 0x88c3cfb1, 0x9bb60fc7,
3292 0xdfe4de88, 0xcd8e4898, 0x5be3c1df, 0xbf791bcd, 0x72e36c1f, 0x5337e8ad,
3293 0x9ebca3c7, 0x42c9f20f, 0xafcad3f3, 0x1e02ca79, 0x89b75d47, 0x9557cbf4,
3294 0x53e45d53, 0x5f1455cf, 0x7aef4eec, 0x77aa8c58, 0x5ebe31f2, 0x7335955e,
3295 0x196fd203, 0x03068c4f, 0x087d3fbb, 0x2c6569f5, 0x46d53bc3, 0xa712c3fb,
3296 0x96c7ca07, 0x8a7e77fa, 0x6a515ff4, 0xde1e2073, 0xbf23f847, 0x78a44dac,
3297 0x395f3cea, 0xab3e79c1, 0xdfcf3821, 0x356fa5a0, 0x2ddd386e, 0x9eb86733,
3298 0xce6688aa, 0x7f477ab0, 0xef0a7402, 0xf928d599, 0xdb96126c, 0x42192ff6,
3299 0x6b8d3b65, 0x6bfbd0a9, 0x8f8e8963, 0x4adcf0fe, 0x7799d3a4, 0x6eed0c4b,
3300 0x42af75e6, 0x41bd57bd, 0xd6bd7052, 0xfb79bbfc, 0xc71ed0f9, 0x9c57f47d,
3301 0x15ae809e, 0x8deafba4, 0xfd53f7eb, 0xfd82922d, 0x4e54dd1f, 0x57854276,
3302 0x4b7cf466, 0xa001f91b, 0xd30f2897, 0x905395ec, 0x5857abee, 0x57d798ec,
3303 0xc7a547e9, 0x661f9136, 0xc9a0c756, 0xb2516ed0, 0xe50e9112, 0xdea75269,
3304 0x78f17a44, 0xedb57d39, 0x25903930, 0x7c8f4f2e, 0x6f4a825d, 0x90dbd232,
3305 0x6f35bd10, 0xfd23322c, 0xebe3e07d, 0x5e908a11, 0x571f1e91, 0x262c2ae3,
3306 0xe9523edc, 0x07e80ab1, 0xe8e5f4e5, 0xd3fa3bb1, 0x02f81dd3, 0xcee47eb4,
3307 0x771a3695, 0x37ddaad1, 0xc47ce52f, 0xab459c70, 0x8179487e, 0xff1e4679,
3308 0xeb88e156, 0xd24f30da, 0x2e0f1c65, 0x997fa733, 0xf1c6e8f1, 0x10d8e48b,
3309 0x96e803fd, 0x01bac59b, 0xe5039443, 0x5698c4d3, 0x31e304a3, 0x51187525,
3310 0xe14f0f3f, 0xc23979fa, 0x3325eb0a, 0x67281f5a, 0xacee081a, 0xa3d7c297,
3311 0x876476e6, 0xa67b63c7, 0xb06efea8, 0x189fde27, 0x5851e50d, 0xff404db6,
3312 0x5745a26e, 0x60a061ee, 0xbc516313, 0x5eca2a9c, 0x4c9d0328, 0x479f54cc,
3313 0xd12f72f3, 0xebcd1bde, 0xc79f500f, 0xead5f2f0, 0x7f5e18f3, 0x99e7a334,
3314 0x7013b129, 0x14cf573d, 0x237c66bb, 0xfd0d4951, 0x62d957fa, 0x6eb489a8,
3315 0x9a8a6fa7, 0xaf146787, 0xf4fff976, 0x5cb5e606, 0xf90098d6, 0xe9d34e07,
3316 0x867b30d6, 0x13ca7589, 0xa4b23d04, 0xae0bb238, 0x2f01bfc7, 0x26818c13,
3317 0x06b06f6c, 0xb0573f08, 0xfbf7f615, 0xf65222e3, 0xdd05e7e0, 0x56a86bfb,
3318 0x6ff30fde, 0x4b632725, 0xc524ae81, 0xe590f94e, 0x46db994b, 0xed4b94eb,
3319 0xcc49bf68, 0xaf9cf869, 0xfbe17657, 0xefa8f1d5, 0x802e32ef, 0x7c2131b4,
3320 0x1fa91b5c, 0x07675c75, 0xb798bc5b, 0xfd618ef4, 0x74e0c26b, 0xf08ae916,
3321 0xe22264b4, 0x098daced, 0xac728bbc, 0x8447fcfa, 0xeaf1b3d7, 0xd64e5173,
3322 0x95d74f3d, 0xa4febc4d, 0x78272b94, 0x64b3bde1, 0x6814a4e7, 0xd0c73163,
3323 0x28baeaba, 0xbee5debe, 0xed17b764, 0x5a73a023, 0x32cde497, 0x76317f93,
3324 0x5f0ce488, 0xd043315f, 0xb114b1f5, 0xaeb2d94e, 0x0ded05a6, 0x4196c3f0,
3325 0x0ba5cf7d, 0x4c4f8c66, 0x9199b7f4, 0x401baaee, 0xcb15e26e, 0x68dd5798,
3326 0xf75a4676, 0x56452a76, 0xf59a17e3, 0xfab2fbc0, 0xb9424cad, 0xafcb873c,
3327 0xc7e3bb45, 0x39517961, 0xbd6ff7b7, 0x0438e766, 0x69ab9941, 0xb1675e25,
3328 0x8a687dd6, 0x74517ea3, 0x4edc25fa, 0xd449ab2e, 0x03ad6794, 0x75c20e6c,
3329 0xfef5da99, 0xa7b9e44c, 0xe30fd0b3, 0xde04d38d, 0xa5ada7a7, 0xb774f7bc,
3330 0x44e73d76, 0x026332ff, 0x2246bb8e, 0xb8e6093d, 0xf066ed82, 0x6c35c219,
3331 0x7dc0385d, 0x67d0a35c, 0x97ce5c95, 0xb4a97f0a, 0xdd17af82, 0xc2666597,
3332 0x7f71f2df, 0x84d8fd6a, 0xa3f71421, 0x7f1efef5, 0xcfeb098b, 0x137e0258,
3333 0x4ec97bf7, 0xda0ea598, 0x86e60ceb, 0xe3c61b8d, 0xe755fa45, 0x3ee50d35,
3334 0xf5edc3ae, 0x10ed09be, 0x5d668f98, 0x6d0a8ce9, 0x5b46acb9, 0xf733afd6,
3335 0x3b3908a5, 0x7e400d80, 0x19229adb, 0xf944ff89, 0x5791d674, 0xefae0a03,
3336 0x194b6d74, 0x0747eb4a, 0x295ca1a1, 0xf9dca9bb, 0xe6a81cdc, 0xc78c07fb,
3337 0x25cf895b, 0x26e5dfe2, 0xe310bda7, 0x0fdc5529, 0x35cf819e, 0x7d7806eb,
3338 0xcb5dcb2a, 0xfee14d7f, 0x6b9b72da, 0xc12dc531, 0xc13cc54f, 0x98d3a358,
3339 0x307c4790, 0x7b3c922d, 0xabffd05b, 0x8c15b40c, 0x25121fab, 0xe4dfa5e0,
3340 0xcf8c3e1e, 0xb963fbf5, 0xfd53e317, 0x0aef000a, 0x779e05ca, 0xaef2209d,
3341 0xb33e8037, 0x5c9fb5c1, 0xc7f48d3f, 0x176e66d5, 0x2aac7c8b, 0x6b8f9c4f,
3342 0x7a13b1f3, 0xe50cf81e, 0xd61b0dce, 0xdb99ff92, 0x1ebf99c7, 0x8d9f77c6,
3343 0xddbeffbf, 0xcea98fdc, 0x35f24fdb, 0xf4f229d5, 0x36ce4269, 0xe7559c82,
3344 0x454df80f, 0x64fe87b9, 0x37bd1e49, 0x87bd73bd, 0x14a4e493, 0x1cf86318,
3345 0x78aa57e4, 0x0a599def, 0x41652bc1, 0xcef384bd, 0x6865de62, 0x6819ff37,
3346 0xd7abef0a, 0x533ebdaf, 0x56ebf491, 0x541d2067, 0xf58ab5a5, 0xdfcf5faa,
3347 0xe7fe82fc, 0xf7d41ca2, 0xebe7d30f, 0xec4ced04, 0xf144b847, 0xde2e3540,
3348 0xad917e9d, 0x30dc8d06, 0xf234a3d9, 0xad7f4265, 0xd0e899bc, 0x471b99ca,
3349 0x9f3cd1f4, 0x79a01ce4, 0x40b8b93e, 0x1aea9e53, 0xcb7fa9ad, 0xd94d22b4,
3350 0xa6bd7692, 0x49b94dbe, 0x7fee8e53, 0xac7ea6ab, 0x73cd36e3, 0x4ecf4bcb,
3351 0x662e0093, 0x0dd5b7ab, 0xde03a870, 0xd2109118, 0xace2031b, 0xaa287eb4,
3352 0x6c7e46c0, 0x004b60dd, 0x832ea4e9, 0xbcb0d3ef, 0x002d24b4, 0x6c7b58fd,
3353 0xf5c216b7, 0x0c6f92f7, 0x62ac73c6, 0x7755f61d, 0xf95e8d33, 0x2be70665,
3354 0xaa657af5, 0x5c1a687b, 0x9929b6f3, 0xf068048c, 0x358fc42a, 0x6bbb718a,
3355 0x7437df17, 0x91cfea35, 0x64967ea1, 0xc54a0e15, 0xaf3b7776, 0x91b3bf23,
3356 0xbd42fbd9, 0x91bf62cd, 0xda999777, 0x1ab635e5, 0xfdfc619c, 0x0f2e5487,
3357 0xb98d721e, 0x32f8898e, 0x0deac3ea, 0xf7e8cdc7, 0x689bfb57, 0xd720e1dd,
3358 0x16f7da71, 0x9af42fba, 0xd70a23b1, 0x1f553d3d, 0xc2e23d79, 0x6bcd3354,
3359 0x65e390bf, 0x7f61644b, 0x2aa4f8f3, 0x7676cb97, 0x1b8c6404, 0x93e36954,
3360 0xf20d397a, 0xded76359, 0x7140223a, 0x11d3900d, 0x0f5545fd, 0x3cd6dc80,
3361 0x3af6859f, 0x7943275f, 0x9ae39023, 0x4553d3e7, 0xcb006b3c, 0x6fc275c3,
3362 0xe7110cb8, 0x1e0cdbf7, 0x5dc37ebf, 0x087f7044, 0xc21216e3, 0x0e2f0f53,
3363 0x69c1cbc7, 0x15bf9a87, 0x7bd7d2f8, 0x6be3832a, 0x3a723747, 0xceedca90,
3364 0x1f3052cd, 0x15c7a885, 0x033af445, 0x2014a5d7, 0x0ab6fe1e, 0x67b2a8fd,
3365 0xf4fa8625, 0xd12f4daf, 0xae33263a, 0xa438c24f, 0x6954bf58, 0x7fa19652,
3366 0x40e0f400, 0x31baa6fb, 0xaaafe340, 0xfbc2682f, 0xce3c8d55, 0xf1e069e2,
3367 0x4ad66acb, 0x6ee6dd7e, 0x2a6f75c6, 0x5207efa7, 0xc7bf1a15, 0xbd44ef0d,
3368 0xf9f160de, 0x2b7fc424, 0x76ca57c5, 0x941d6c4b, 0x4eb6af37, 0x3d2f648b,
3369 0xe2fde02f, 0xf5c3336a, 0x1ed095e6, 0x6b3fb1e7, 0x3be319bf, 0xca253b65,
3370 0x5bea7867, 0xd6be62a6, 0xd0c4d8b3, 0x77c7508e, 0x7e482b26, 0x84739be4,
3371 0xc787391f, 0xcc5cde2d, 0xee790fed, 0x9d57147b, 0xc8fc255e, 0x0e281739,
3372 0xf08566f4, 0xb8f2e723, 0xd43bf4c7, 0x8e968ebc, 0xd3d53a55, 0xf56e9e9f,
3373 0xe955faf4, 0xa76a4773, 0xf508319d, 0x1c7be03a, 0x1fdef1fa, 0x4c27ca32,
3374 0x426cd4bb, 0x2af7bf3f, 0x281ee3bb, 0x2b7d940f, 0x9ace5e31, 0x95c1f3f9,
3375 0x5f2e249b, 0x3e715b94, 0x86667599, 0x020239fb, 0x53c4014f, 0x43a94e32,
3376 0x357e468a, 0x1ca37b06, 0x0175c1ca, 0xc1a7c700, 0xf949dfcf, 0x065f2e25,
3377 0x69b6973e, 0xd6bd184d, 0xcaa2b908, 0xe66601bd, 0x017189de, 0xc6067d63,
3378 0xf8987717, 0xd16c963e, 0x1d3edf5f, 0xb5c127e3, 0x65ffbc4d, 0x7fcb5571,
3379 0x94fe10c9, 0x75c11673, 0x5da3c8a2, 0x8a5034bf, 0x744ec8f3, 0x6f315307,
3380 0x12a47d99, 0xef5d5af5, 0x1fd0f397, 0xabc3d751, 0x91e6f471, 0x13bc6c1f,
3381 0x32bb6be6, 0xdb69f08a, 0xf48edeb3, 0x243beb6b, 0x57de5235, 0x2a2e7abd,
3382 0x53fc0dcc, 0x5d37b17d, 0xbda4f2d5, 0x6dfd68a7, 0x78dcffb5, 0x698b8fe2,
3383 0xf76d5f74, 0x81ee3127, 0xf32cff62, 0x065e9127, 0x911c6cb9, 0xc2a7aa1f,
3384 0x68e75d41, 0xf085bbeb, 0x3c1de775, 0x7ad8c1bf, 0x654667ea, 0xfd0e548b,
3385 0x9a7262dc, 0x47de0062, 0x709b4c7a, 0xd5d71732, 0xc1c1b8f3, 0xa5c52b5a,
3386 0x53b5ad5e, 0x469b5839, 0x156bd7e5, 0xec915eba, 0x34e104fa, 0xbe9ac5f5,
3387 0xace6b708, 0xa7985d87, 0x44d07b3c, 0xaecc60f0, 0xc17de7d9, 0xea3c532f,
3388 0x5f5f0342, 0xe67f8ea2, 0x4ee60cc5, 0x8a6371e4, 0x0bfd2c57, 0xc54739c9,
3389 0xf7e8f1b9, 0x5b6cae0c, 0xd2cf6585, 0xee9d694f, 0x282fa03b, 0xe3c8d1ef,
3390 0x2d8d55a7, 0xf4b9ceb4, 0xb3f50262, 0x1e31d0c3, 0x82fbccf9, 0xde3beb44,
3391 0x4e673c69, 0xd288fae5, 0x7c451b3a, 0x3c5a4879, 0x1fe3c1c1, 0xe5f8e06c,
3392 0x8245d579, 0xfaae9a1e, 0xc3e21c47, 0xf5a154ba, 0x6407d522, 0x19acb38a,
3393 0x8f6711d3, 0x6e317720, 0xde93eb8d, 0xf494eb12, 0xbd99a7cf, 0xc07d717d,
3394 0xfde44334, 0x50b48ecf, 0x75d71f7e, 0xc7f53297, 0x3f83d7f7, 0xca88eb43,
3395 0x8ca745fc, 0x6ef9ad78, 0x196acff2, 0xfdf0c1fd, 0x320fe806, 0x34bdfbcd,
3396 0xae564b7e, 0x85d6ef26, 0x98335bfe, 0xaeaa7802, 0x20173003, 0xd7455f9d,
3397 0x2af7ddf6, 0xa8d637c8, 0x2f51878e, 0xf2067eb0, 0x5abcaa27, 0xe84b273b,
3398 0xee0cacad, 0x89a7173f, 0x2fc2b2fd, 0x4267ff02, 0xe27ff71a, 0x5f8d32f6,
3399 0x7e4fbfa4, 0xc7ec5591, 0x7978001e, 0xafb8c23a, 0xc2e318cc, 0x1d6cd976,
3400 0xfa0337d1, 0xcfd2ba46, 0x1f1a4673, 0xd3cfca97, 0x28f39f91, 0xacfc4ece,
3401 0x464877ef, 0xcfb40ce1, 0x5fb37756, 0xefc12aeb, 0xc1181b55, 0x8121b3cb,
3402 0x6d8674e0, 0x7a018d70, 0xd8e3033c, 0xd678f40c, 0x878e8ae5, 0xaedd67f6,
3403 0x109884e8, 0x886f57ff, 0x73ab76a2, 0x872c4a6f, 0xf7a08d72, 0x2b22c6f6,
3404 0x06e679c2, 0xfbea77ce, 0x4f4c09de, 0x6a1a3e44, 0xde6330ea, 0x2dbfa7ae,
3405 0xa1bbed0e, 0x222727bb, 0x4e3775ff, 0x779f3a77, 0xb445d2d5, 0xb87f155e,
3406 0xd0a1627e, 0x3a7b9e63, 0xd57ca11e, 0xdbf44652, 0xd5afebb4, 0xfeedbfc8,
3407 0x9e6bca68, 0x7a4d13d9, 0x3cd3ecf0, 0xd4c679af, 0xaa60eb4a, 0xf476cb77,
3408 0x7c2f3d07, 0x9ff230fc, 0xa1459767, 0xdeffbd78, 0xb6aeb873, 0xad1d7fd2,
3409 0xfedca8c3, 0xd541f2dd, 0xfec8bbd2, 0xd71fcb51, 0x37285d5a, 0x2e5c8ddb,
3410 0x867c6c2c, 0x9785d9ec, 0xfcc20c2e, 0xff3d99ef, 0x98e50c3d, 0x86178fe7,
3411 0xe7ec3ed1, 0xe7c30c2f, 0x6ba2e79e, 0xef25d922, 0x8e38f066, 0x0e731faa,
3412 0x9ef13519, 0x73fe8209, 0xc62bac56, 0xb6864d73, 0xaf84714c, 0xd7da1b1b,
3413 0x8617fb40, 0x389b1e1e, 0x8addac37, 0x392fdf20, 0xf46c65a4, 0x747a309c,
3414 0xb8d49866, 0xd38ad7d1, 0xa11fb130, 0x34132e33, 0xd5843ed0, 0x6f3f2341,
3415 0xa1f242a0, 0x8a7600ff, 0x4bd91dbe, 0xe44f6f67, 0x5d1832e7, 0x1d220613,
3416 0xf697dedc, 0x75af3387, 0x3d986e5f, 0xa0683d34, 0xfcd3ddf5, 0xefd90096,
3417 0xefad2341, 0x99a4ed56, 0xcd883ee7, 0x5dc42291, 0x0e3ebffa, 0xfe3eb6e5,
3418 0x6ec6b3d2, 0x2fef0898, 0x08ecc15d, 0x063c7d3f, 0xfb9db17e, 0xf8d75992,
3419 0xd07c128c, 0x5c95ed8a, 0xa7c71d83, 0xb78899da, 0x3efc0886, 0xb3f39d2d,
3420 0x822b47ca, 0x8ac7c206, 0x2e6b18e0, 0xe789275c, 0x7136a00d, 0xff0ae8df,
3421 0x1f18ade4, 0x96e97158, 0x9ef081e8, 0x626e8715, 0xdbbf20f7, 0x62fb58c7,
3422 0xb7df4bbb, 0xd10bcd4e, 0x4a7dfe89, 0x2127d73a, 0x7eb2207b, 0xfbfc178b,
3423 0xd8b9e95d, 0x3d6cfff4, 0x52757e07, 0xabf250fa, 0x07b8f067, 0xfaf5abf7,
3424 0x6abb9541, 0x7e04e3bf, 0x53ddcabb, 0xff80bf64, 0x5c77724b, 0x7af542ba,
3425 0x922527fa, 0x4a687c5f, 0xb5d312a2, 0x87463eff, 0x6baf2121, 0xe69daaff,
3426 0x59f73af1, 0xf2717fd1, 0x8a6796fc, 0x90a493e4, 0x4971e75d, 0xa9649f7c,
3427 0xd4f587c9, 0xf0a70571, 0xa754e9b8, 0xaa86f289, 0x87daa7fd, 0x3c1dcf9d,
3428 0x8bdaa8af, 0x74185daa, 0x94ec38f1, 0x15f9fc21, 0x106beec9, 0xf588ef5e,
3429 0xf247432d, 0xf6b98cfb, 0xcb747fa1, 0x7e2312cd, 0x4aa2f617, 0x527b7a9f,
3430 0x1ddf6f5d, 0xba0a371e, 0x5b2bf954, 0x9eaa17c7, 0xba7a11aa, 0x2274f51a,
3431 0x34cfe9ea, 0x5fbeb776, 0xf4aed3d0, 0x08c76c64, 0x1b0e43be, 0xeefc915d,
3432 0x375fa213, 0x3dae0fe2, 0xe2162f83, 0x7058b378, 0xdd8bfa19, 0xb0974fe9,
3433 0x5e7bba63, 0x5f9fc693, 0x08d78f8e, 0x7c577ffc, 0x9c3feabc, 0xbeed3b8f,
3434 0xba23ce6e, 0x7ef0a332, 0xb928dba4, 0x7c885826, 0xc51367f7, 0x4af5f5c9,
3435 0xff063e85, 0xfbbf4355, 0xf406ccb2, 0xdc153c77, 0x578bafff, 0xe4bf235e,
3436 0xd5d69925, 0x0eff042c, 0x1705b3ed, 0x44ad74ed, 0x33ae183b, 0xfe50b5b6,
3437 0x76854660, 0x831875fc, 0xe477f6c5, 0x32fc7ad0, 0x44e29636, 0x3b78fe65,
3438 0x4baf23ee, 0x86f5a7ae, 0xb2b2adde, 0xedfebc35, 0x8f2b7d6a, 0xf74d2d9b,
3439 0x6b79e72d, 0xab2fbe8d, 0x5af3dbd1, 0xc45a3ffd, 0x03b3ba7d, 0x71b26f9e,
3440 0x26407279, 0x78c6aefe, 0x998cd5d1, 0x4bd5f5d5, 0xdaa39c79, 0x23f68cbf,
3441 0x1fe78957, 0x4714831a, 0x5417fca2, 0x9f5fe53d, 0x9cc87c82, 0xd54f7cda,
3442 0x2724c396, 0x849f79f5, 0x3c8f2e06, 0xf3c8b295, 0x7d68930c, 0xa7d8a363,
3443 0x223728aa, 0xcc5c61dc, 0x863ee0a7, 0xce3fe413, 0xf325fdd8, 0x17f84e3c,
3444 0x7fb3cf31, 0xf972a65f, 0x63754f3c, 0x84fd098b, 0xde7be5cb, 0xc38cef49,
3445 0x97b09c50, 0x7b5fc791, 0xc63b25f9, 0xf5897a97, 0x4757c37e, 0xc77ff5f1,
3446 0xdf2224e6, 0x9f6978ab, 0xfed9e1c4, 0xd88527e6, 0xa331d86e, 0x3e11d71d,
3447 0xbfe2e6ff, 0xad32f264, 0x6c7f18d3, 0x25fa3471, 0x4516c7ed, 0x879f3c23,
3448 0xb9e3e22b, 0xe3118c37, 0x78a1e589, 0x7bd205f2, 0xb2788b77, 0x6c5ef411,
3449 0x6fa32e28, 0xd72153f7, 0x8adf30ea, 0xe79bb974, 0xddd2ebfd, 0x57f953d7,
3450 0x13ff69bd, 0xbcc279c3, 0xc63a019e, 0x9800cfb8, 0x9f95e62c, 0x302b628c,
3451 0xec9753cf, 0xe6f8997e, 0xf9050657, 0x7e53da06, 0x2153bbc8, 0x55a1883d,
3452 0x020cc3cc, 0x7da563dd, 0x8f944979, 0x2fe04ab9, 0xf452fc1d, 0x5334610f,
3453 0x403c8f30, 0x450663e4, 0x7ff62331, 0xe6bdc99f, 0x34ffcc4a, 0x88cb1d19,
3454 0x93891de8, 0x85e6bb62, 0x77cf2724, 0x3521f9ab, 0x7e5dddef, 0x0cf7c248,
3455 0xf945f4e2, 0x3094e620, 0x81e6ae1f, 0x4a2ecdd8, 0x511f2d4e, 0x7967e743,
3456 0x9d37d8b2, 0x8b4a29ff, 0xa5719f90, 0x6bef6131, 0xfa6b81f3, 0xfa744d3f,
3457 0x6b80f355, 0x71e9bfd2, 0xd5efdc2b, 0xfc487b8d, 0xa3f214f9, 0x3a77f9fe,
3458 0xffb560b7, 0xb3bde902, 0x0e71161d, 0x938f2b45, 0x2f144dfb, 0x58fe0b38,
3459 0xdd3e9872, 0xddfbc69e, 0xfa222feb, 0x8d8e086f, 0xc487fac6, 0xa687d5fd,
3460 0xde7b464c, 0xfa3a341b, 0x7fb848d2, 0x0e3410d5, 0x1be4fb45, 0x7a694bc4,
3461 0xa359f984, 0xf3d23eb8, 0xbfe09c51, 0xe70e0cb8, 0x5fb937a2, 0xf3cc59e5,
3462 0x1d75761f, 0x73cf0d70, 0x914acfef, 0x6a77f8d4, 0x6ec8fca4, 0xecbd2ebe,
3463 0x2df68976, 0xc8fcd97f, 0x7fb6c68c, 0x8fa23f2b, 0x219ddf3b, 0x790322f2,
3464 0xdd23b9dc, 0xa84bf34e, 0xfb885c19, 0x7ef9d49e, 0x901f7083, 0x43e6edf9,
3465 0xedf9efaf, 0x352fdff6, 0x837cdd02, 0xcb7d97fd, 0x96fc2ffd, 0xf52fbffb,
3466 0xdb7f85db, 0xcbffdcb7, 0x8fff72df, 0xff07d244, 0xf5ebe6af, 0xfe7d78f9,
3467 0xb7979f5e, 0x8bd734bc, 0xd695eecf, 0x6ae00476, 0x4d35db8d, 0x8c687902,
3468 0xbd4562df, 0xe7923259, 0xb58f56af, 0xa14936fa, 0xaf0abe3c, 0x3fdc5991,
3469 0xf39de7b3, 0x6ce356e2, 0x226c7067, 0x3246bbc6, 0xdacf6ff2, 0x198b1e78,
3470 0xd798e9ed, 0x37e99a82, 0x67521d81, 0x7d079c8b, 0xf7f0a7af, 0x4b1bd1ba,
3471 0xc8af0ab2, 0xfed5a64c, 0x59f648ce, 0xdb2f88ad, 0x17c5191b, 0xbf495199,
3472 0xa4abde89, 0xe3d3fda3, 0x2e3f7e45, 0x689b9cc0, 0x4dce4a5c, 0x928f6e74,
3473 0x407be383, 0xae1367e4, 0xf18397ef, 0x03b004e4, 0x1eb78f31, 0xa7e479f3,
3474 0xfa9ea9da, 0xdc99ddbe, 0xc4c07a4f, 0xef305ce8, 0x11dd7c95, 0xbd9156b3,
3475 0x0ee1e6a6, 0xcb27029a, 0x8dc3ca25, 0x62bff1c1, 0xce6de408, 0x449c4411,
3476 0x3f296dfb, 0xdfc8eaf8, 0x7bd377f5, 0x86fecd14, 0x6187f466, 0x29ee771c,
3477 0xb19dfa20, 0x6fed2477, 0x091ae4f0, 0x46fc5dce, 0x43780711, 0x38d431c4,
3478 0x7a8f9a80, 0xde3fc45b, 0x3f4ab8c1, 0xa1584f3c, 0xc34caceb, 0x5a9e77bf,
3479 0x159cfe57, 0x203d3f49, 0xf78fb8f1, 0x29f71e15, 0x84fa3b30, 0xccac7faf,
3480 0x0f2c78e4, 0x1a83bcf0, 0xcc4279c7, 0x7287e0a7, 0x687602c0, 0x6681aac1,
3481 0xab05ebd4, 0x3af0a2b2, 0xa433e9c8, 0xcfa7bc00, 0xf15069d9, 0xee8e8917,
3482 0x89f114ca, 0x8f941d03, 0x9797467b, 0xd7c99ddf, 0x7165e41b, 0x64ceeefc,
3483 0xafb3be54, 0x8b9a3971, 0xcbb1ae3d, 0x6541f291, 0x38e2f7e0, 0xb8f8ebcb,
3484 0x05977855, 0x4f7c2294, 0x558ebedb, 0xc8afcd78, 0x79b8a229, 0xb455b9e5,
3485 0x85d2e9bf, 0x1c52d7fd, 0xffa0accc, 0x1b55b330, 0xc5909b4f, 0xa0cfe7e3,
3486 0xbb708dc1, 0x6ffe48ce, 0xa24675c1, 0x1b32849f, 0x2609a7f9, 0x7960c726,
3487 0xf283b712, 0xb08a938b, 0x93c4a6cc, 0x407f97fd, 0x179b9f89, 0x5c256f8a,
3488 0xe11938b7, 0xa8bcb974, 0x22bb271a, 0xa44bf9d9, 0x179aafdf, 0x88783aad,
3489 0xf3aa7bd6, 0xe6a2e152, 0x8bcbbb37, 0x3c12ebaa, 0xd6689fc5, 0x1d8c7851,
3490 0x58ae31e3, 0xaccda7b0, 0xcb4b37ee, 0x0b4de509, 0x7ca39f76, 0xf51f9aa9,
3491 0x3b239cd4, 0xb199da1a, 0x3fa0017d, 0x4364e41d, 0xee9bcf2d, 0x1a7bfb12,
3492 0xae78fe61, 0xfe601ff6, 0xfcc3f578, 0xb50bfef1, 0xa81ae9fd, 0x6f75d075,
3493 0x7aba08ed, 0xcf28e7fc, 0x36a642fa, 0x8f99d75f, 0x084d5d93, 0x1d7cb0af,
3494 0x3af9f595, 0x63c78a39, 0xee303f70, 0xb41cf21f, 0xf42efc92, 0x7f42f797,
3495 0xee2d6fe0, 0x6aee385e, 0xd18597cc, 0x61d3bb45, 0xdb6c73c3, 0xe61b0e5d,
3496 0x4e9a0ac9, 0x6a847ed1, 0x15ce9063, 0xa6073ce8, 0x775f1ce1, 0x21b42feb,
3497 0xd79b2f7c, 0x79fffc6a, 0xd7932fad, 0x32f905ba, 0xf23f2439, 0x26e7065d,
3498 0xda701ebc, 0x87c986e6, 0x179e2ed5, 0x9bdb9d59, 0x5741eff8, 0x6139f8ef,
3499 0xe628adfd, 0xeb848a71, 0xf7e16d72, 0x79e2c89f, 0xb98904ac, 0xe4b1c922,
3500 0xbcb8df9e, 0xef648e4e, 0xf402bfb7, 0xc3d03578, 0x5abdf9ee, 0x71b4ae89,
3501 0x73c5d5b6, 0xdbb9e17a, 0xac2c37de, 0x69c38f2f, 0x974c6ce2, 0xde2eeb4f,
3502 0x40d8a336, 0x7bc2e2e7, 0xeb5f51b3, 0xd8cc62e3, 0xb9f5cd91, 0xe4739c53,
3503 0x582364cd, 0x5bdabc97, 0x173877cc, 0x362f4fea, 0xf3509e90, 0x46c5f96b,
3504 0x99f40b56, 0xa3e4d4bf, 0xb1b15abc, 0xff0b9e8d, 0x3f3d8570, 0x3bc9e513,
3505 0x8c76cd07, 0x60e3e9a3, 0x752de28e, 0xa3bda1bd, 0x6d7da252, 0x373fd65d,
3506 0xf8c38d36, 0xaeb660d9, 0x1bd42c6e, 0xe3b06b9c, 0xe5cbe57a, 0x3d85f2e1,
3507 0x219f8fa3, 0xa1fda15d, 0x2f5fa38f, 0xb0bd7ef0, 0xbf43ee97, 0x8fd43932,
3508 0x2f4f4eda, 0xbe94f68f, 0xbf7f2e30, 0x71456fe8, 0xc45ceafe, 0xa1818967,
3509 0x3c5158de, 0xd61b9ac6, 0x234f595f, 0x7986af5f, 0xbcf0a4bd, 0xe9dfcf1e,
3510 0x3caa79f3, 0x8cfa682b, 0x083efff6, 0x95f51972, 0xffc78d27, 0x3c285e0b,
3511 0x34227280, 0x1f9fae4e, 0x37bf534c, 0x7c6788e0, 0xd14fb45e, 0xb8a247bb,
3512 0x27c97e5b, 0xcca1a37b, 0x7fb4f15c, 0x773073de, 0xef939e39, 0xc50e3129,
3513 0x971e3afd, 0xc22799d4, 0xd7e4d07c, 0xf5c7ae2a, 0x075305fc, 0xa67e20b7,
3514 0x9d689a96, 0xa6d7e4de, 0xaae539d1, 0xba982b9e, 0x7c289ee9, 0xf3a25fde,
3515 0x56bf261a, 0x4f9f063c, 0x88c01ed8, 0xb3889b38, 0x3c193907, 0x7c88d278,
3516 0xfbb24572, 0x0537c827, 0xa89e4493, 0xa9e3eb94, 0xc62649fe, 0x7e8d46ed,
3517 0x1bface6c, 0xf3d479c5, 0x7d711204, 0x2f485e42, 0x7d01ec15, 0x57d21b15,
3518 0x7a9eaeff, 0xe09da7b4, 0x2be83579, 0x24c24f1c, 0x62ef4f9e, 0x77fc08bf,
3519 0x93ba7fa7, 0xc467a8bb, 0x529983f9, 0xad7d575a, 0x38673c60, 0x9d12e5da,
3520 0xfd1dd683, 0xcfec26bd, 0xb6ec6ef8, 0x76fd04d7, 0xf1a9aebb, 0xfd13c9bb,
3521 0x787fe7b9, 0x57f8489e, 0xf548be6a, 0x7b09fac7, 0x215ebd57, 0x7b7fbbfc,
3522 0xd12a013f, 0x1209fb88, 0x9827ef22, 0xbda12f59, 0xd827eea4, 0x3b856667,
3523 0xab3d7093, 0x73e44fd8, 0xefb41d91, 0x7aad6fd7, 0x7bce893c, 0xa0cc6dc0,
3524 0x9f485af7, 0x43fd8157, 0x63ff92f6, 0xe7ad3f1e, 0x1aabb1eb, 0xd496fbb5,
3525 0x5f616ceb, 0x50f9858f, 0x77ac459e, 0x91ce2f1d, 0xef21c508, 0x21c78632,
3526 0x59304a3d, 0xe3eb475d, 0x5c4d1779, 0x6438bbb2, 0x75a0eb35, 0x9215d5b3,
3527 0xb7c3f503, 0x91ec971d, 0xddaf5da5, 0x83cb9327, 0x42496e69, 0x706ad5fb,
3528 0xf8bad255, 0x6c7ef817, 0x66fa7c3d, 0x413c7971, 0x331e31e4, 0x6c787a73,
3529 0x5bfb4494, 0xe21c1f70, 0xf817b1f9, 0xf2c7973e, 0x35173ef9, 0x5feea16f,
3530 0xb79432b9, 0xea6ffda0, 0x1f7517be, 0x780fba8b, 0x00a886d2, 0x99f707da,
3531 0x1db8d3ea, 0x3c3a25eb, 0xf3d193dc, 0x6f3f0b28, 0xf8ce3f5d, 0x28c3c2ac,
3532 0xf37f0f87, 0xac88d176, 0x25a67108, 0xaffc2fc2, 0x98fb2eac, 0x30bffb54,
3533 0xfec6a86b, 0xfedeb2a7, 0x16f2a6ff, 0x6f9f0141, 0x32abde70, 0xe6f8ddbf,
3534 0xfc72df67, 0x7b247cfa, 0x4b88b976, 0xd9e7e9e9, 0x68bf552c, 0xbac34bbf,
3535 0xfae43fec, 0x8e524ebb, 0x2f6bb9d2, 0x542573f1, 0xcb175a39, 0xe4215ffb,
3536 0x547d7aa7, 0x914ceb5c, 0x884f5fe3, 0xe764b3e7, 0x0193a472, 0xc8f1b4db,
3537 0x78daf581, 0x098dd5e4, 0x40e0f29a, 0xc17ea686, 0xe79ade81, 0x69578343,
3538 0x237f0f9e, 0xd91e535f, 0x7f534a3a, 0xb46387f4, 0x68755ae7, 0x5ed791e3,
3539 0x2fb749bc, 0x2bf047d2, 0x6f0dca04, 0xad9d6457, 0xa15997a9, 0x8d56579d,
3540 0x96bd5e76, 0x2fcee826, 0x78e6fde1, 0x53ebf3b5, 0x025f9da7, 0xbef2d3e6,
3541 0xd4cd3e7e, 0xecf7a153, 0x61b1f7f5, 0x738a07bb, 0xa99f686d, 0xc1db99fb,
3542 0x6411786e, 0xffb69fdf, 0x9cd7d696, 0x06eda279, 0x79e6cf3a, 0x0379e199,
3543 0x5963dbed, 0xa3e3de80, 0x34162873, 0x661ef4c8, 0x1c9b0c0c, 0x9d1afe76,
3544 0xe9f28f4c, 0x911258a9, 0xf8b69e0b, 0x82fda04a, 0xe106275d, 0x7bf692fe,
3545 0xfbcb3e78, 0x31f14484, 0x841d6de6, 0x60584bdf, 0xa89dfc8c, 0xbcb8b2d7,
3546 0x9a3bbd3b, 0xdb49ebd6, 0xbf52669a, 0x3098b7f5, 0xdbd6a69f, 0xa849fc2f,
3547 0x3d3df7c7, 0x5e77d12e, 0x71e17c70, 0x27bbf54d, 0xfae71fa7, 0x89a3416f,
3548 0xb059efce, 0x9e3b676d, 0x0de0bd57, 0xe65b9d0b, 0xf48e76d9, 0x3b53d16a,
3549 0x469ece08, 0xd5a8bd99, 0x8273da57, 0x5db8f1b7, 0xe9154375, 0xff932841,
3550 0xf91f5d55, 0x9dcbecbc, 0xa9f0bb67, 0x00bcbb3d, 0xfccf85c2, 0x1ee30e2e,
3551 0xc6b7051f, 0xedbedf91, 0xeee9cf8b, 0xfd702e72, 0x173c2fea, 0x03fc23f8,
3552 0x2cc5cbe4, 0xdbcab9dd, 0xa9f7c512, 0xf7c2c302, 0xe8e087f9, 0xf1de78e5,
3553 0x6e7823e9, 0x3fa7e9fd, 0x5bc7047e, 0x8f0baff9, 0xadf498fc, 0xc3728ecd,
3554 0x3a61c4f3, 0x976d5bf7, 0x40e5cd90, 0xa3bfe3fb, 0xdfdbd2f3, 0xb7b038b4,
3555 0x641f3df6, 0xefb77d23, 0xe3052cfc, 0x8cf78b5c, 0xe2f078a3, 0xf0be8b67,
3556 0xb7486b7b, 0xe3e17ebe, 0x3e7375f2, 0xcd5f16b1, 0x38d9cd0d, 0x6f8033ce,
3557 0x9e75f38c, 0xc55f5cf3, 0xc456cdcf, 0x23dbcef9, 0xe5df8b9f, 0xc986e73c,
3558 0xed0f7e37, 0x2e7e069e, 0x75cf65cc, 0xbc78043e, 0x6fe04bfa, 0xbe716afb,
3559 0x9dfc6449, 0x4f003fc1, 0xb9ed6c8e, 0xcc369fce, 0xf8d7f47d, 0xdbb121ac,
3560 0x5f039d73, 0xb9ea6e02, 0x72ccfffb, 0x3e46ce8e, 0x74f7fa7c, 0xade2368e,
3561 0x3a73c144, 0x7f46cd3e, 0x075343ee, 0xb1d72b9d, 0xefc762c7, 0x73d82d37,
3562 0xfda7f894, 0x64b71e59, 0x76fbfce2, 0xe7e3f9d6, 0x8a988b95, 0x3f2c4b67,
3563 0x1fc05a0f, 0xe2568bcf, 0x1738bee8, 0x7ab1d39a, 0xe777745e, 0xeeca2f44,
3564 0xf89cf5cd, 0x96d5401e, 0x9fb99abf, 0x3497c21a, 0x7fe9f682, 0x2adbf9e1,
3565 0xbfc2ec1c, 0x96dbc4eb, 0x7771e7c8, 0xf02f8f9e, 0x73c3f885, 0x35cf3a3c,
3566 0x5435f287, 0x08b28e96, 0x137da0f2, 0xbdbd2f3f, 0xeea9fd1b, 0xd6caaa0f,
3567 0x6798a9f1, 0xf2a1fc77, 0xffc6e5e9, 0x3333e155, 0x8bd0d15b, 0x97d3a70a,
3568 0x75f1cb22, 0xb6bfef82, 0x62ece3fd, 0xf48fdcff, 0x66d0d558, 0x44d9fbe6,
3569 0xf7cc547e, 0xf4dfd834, 0x6427a4fd, 0xd557e3b2, 0xd71c9337, 0x6eea8bcb,
3570 0xb39b6df2, 0x7153bac5, 0xa7e9c14e, 0xefb87d63, 0xdddef4ea, 0xf6effd7c,
3571 0xfa17b336, 0x19edbfdb, 0x721b8f33, 0xe13d41fe, 0xe9ff1b0b, 0x91069b27,
3572 0xdd66eedc, 0x8f78bd77, 0x3df91fc7, 0x34e7ed9e, 0xade859ef, 0x72efff27,
3573 0xe8c8fbef, 0xfbfb05bc, 0x3bf7c828, 0x4ffb847e, 0x17ffbc23, 0x176126d9,
3574 0x22eb13ae, 0x3f03de41, 0x9ee02bbf, 0x3cf5cbd6, 0x9d1999c2, 0xe3be1083,
3575 0x2725917e, 0xaf979f01, 0x7fa8ec95, 0x4c18af67, 0x9ccf9274, 0x89652744,
3576 0xfa937bfc, 0xe6cf1cf7, 0x1ab6fc7a, 0xc3fa4313, 0x280cded3, 0xb624eb7f,
3577 0x3197fb86, 0xe7425313, 0x6ead56d1, 0x0abc2389, 0xef3d533f, 0x3e66a2b6,
3578 0x39fd07c9, 0xdeac9538, 0x2d6fe78c, 0x2dcfcb58, 0xa38b9fd4, 0xcf5dab97,
3579 0x85fb5a89, 0x956df672, 0x81cc1cef, 0x07e7377c, 0xd7e456b1, 0x4a68f0ae,
3580 0xb3ca05be, 0x07a4c80f, 0x2eb0b854, 0xebcbfddf, 0x7f3cf881, 0x973f2fa0,
3581 0xb152515c, 0x3c1e9cde, 0xdd19282e, 0x597ef1c3, 0x19b87ba2, 0xb19beae5,
3582 0xb596c7b8, 0x7c50345d, 0x36595980, 0x59d9938e, 0x537db876, 0x60a7b26e,
3583 0x16cbc4de, 0x58fc51a5, 0xeb0addff, 0x1eff20da, 0x157bf683, 0x5f9c8965,
3584 0xeff3763a, 0x1e46b1ef, 0xeb32b6bf, 0x9c778c32, 0xe0a5d652, 0x95ae5411,
3585 0xc53dfe26, 0x4714f1ed, 0x91456db8, 0xba5fcf19, 0xf69e21ad, 0x93af30b5,
3586 0xe2a8cfbe, 0xc1456db1, 0xf7e834fe, 0x871cfab6, 0x269fc5ac, 0xaea0bc1e,
3587 0xc9dbc54d, 0x64ede0cb, 0xbe01bc24, 0x7a13f734, 0xeec5f169, 0xe94cf6e6,
3588 0x62fafb1d, 0x0d7ceefe, 0x77631eff, 0x340e92f2, 0x35c5094a, 0xe33a338b,
3589 0xef4829b5, 0x250ed617, 0x55f1e9bc, 0xc3d9affc, 0x7b337f71, 0x05ce962b,
3590 0x66c3eb2e, 0x6ff184dd, 0xd953f389, 0xa316262f, 0x8bd01ade, 0xb56bfdf3,
3591 0x82d9fe3c, 0x787ecff1, 0xca9dba6e, 0xf3fc4587, 0xe13fc628, 0x3fc626fa,
3592 0x7c527ae1, 0x33e5433f, 0xd7a20020, 0x7f38bdc1, 0x8925ee0d, 0x34e2ddf8,
3593 0xff8a4bb4, 0x73f38b25, 0x61637d7e, 0xce878d0c, 0xa3fef9cb, 0x7bd1bebf,
3594 0x3a37630d, 0x69b4f1b5, 0xb4f1b453, 0x663915f2, 0x736fd7f4, 0xa3d4d68d,
3595 0x0f5abc88, 0x925e98ba, 0x337e79a8, 0xbfcc34be, 0xf0a5ee2f, 0x1f7147f8,
3596 0x4b5bbd4d, 0x2a5bdfb5, 0xb3c668bf, 0x62dbd985, 0x26b3309f, 0x87bfc219,
3597 0xf1ca4402, 0x3e6de762, 0x416e3a31, 0x60e4fc7a, 0x5e7284b2, 0xaf150f8f,
3598 0x080037b3, 0x1b39dfa0, 0xbd97940c, 0x55e3b66b, 0xaeeccf3c, 0x7bf7f8a7,
3599 0x467bae4e, 0x39805df3, 0xbf84994f, 0xa1fb2763, 0xf232c568, 0x607dca3b,
3600 0xcb88022f, 0xa23ef45f, 0x467e3196, 0x0f91594b, 0x80bec90e, 0xe2727844,
3601 0x4fbd83f7, 0x7e47eff0, 0x0ed86208, 0x2b7677fa, 0x1287c71f, 0x53e5815b,
3602 0xfdfbb7b6, 0x6675e600, 0x0679bae2, 0x307c8dc4, 0xd3e2e499, 0x2cfa4332,
3603 0xe744c3bd, 0x587ede39, 0x31f4efa6, 0xc5533f29, 0xd9cbe62b, 0x1dfe1613,
3604 0x04a00e9b, 0x71f8b7a8, 0x8f9f7d0b, 0xcfcb0328, 0x11adf40e, 0xf2f48874,
3605 0xc6733c61, 0xfe7960d3, 0x6496a3e0, 0x82119f5a, 0xce106f9b, 0xfae09bd7,
3606 0xa3a02f51, 0x06f9e68f, 0x3bbafc91, 0x0f47f899, 0x2e6693df, 0xef48bc9f,
3607 0xea2e4852, 0x26d996ed, 0xc7df7d07, 0xa3a486cb, 0x96b93a5c, 0xf40f477f,
3608 0x3f5f1c4a, 0xabd134f3, 0x46939efa, 0xef8e3c65, 0xe90e5d64, 0x0ad6dbaf,
3609 0x06f4137f, 0xfae3efaf, 0x46ecbd6a, 0x275bc3bb, 0xaf9db9b9, 0x4db78fa5,
3610 0x688b9ede, 0xd68db1fd, 0x6809dcaf, 0x9dca3cc5, 0x2ec9533b, 0x5bec2998,
3611 0x2ddbc696, 0x3b3a73b6, 0x0f4fa07f, 0xea7ad7dc, 0xea01e010, 0x75f3a7b4,
3612 0xacc6a705, 0x3747861b, 0x1dec369d, 0xffb803f6, 0xfbef44f1, 0xc8dbc046,
3613 0x5ee6f76c, 0xac329f18, 0x4473c6cd, 0xfc4fface, 0xf50fbf1c, 0x83930ed1,
3614 0x97e974d8, 0x0c4ed3b3, 0xeb835d8d, 0xf2eb67c2, 0x3f042704, 0x5bf8293c,
3615 0x8b6fcfd5, 0xa7036cf2, 0x2482f63f, 0x34c46bbe, 0x9e217872, 0xe4872a43,
3616 0x2b872aa5, 0xc7fadd85, 0x3e6edc5e, 0x60a5d6c5, 0x4fa005bd, 0x3b3cfef1,
3617 0xb72a4bb7, 0x7ee7eff1, 0x4c9c7c84, 0xf5c31a7d, 0xe4167cf2, 0xea014e7a,
3618 0x77dd0949, 0xc0388b45, 0x409fbe3a, 0xb9e7f72f, 0xe06ffb7d, 0xa3003bfd,
3619 0x7cffe45d, 0x8f1b1ae6, 0x3c6deb71, 0xff97ac9e, 0xb9b7e84c, 0x3d7a7de2,
3620 0xbbe85730, 0x377d3ab9, 0xce8e71cf, 0x0edca91d, 0xb2b945ef, 0xc2efab4e,
3621 0x9a44a9e6, 0x872f3ce7, 0x873f3cf7, 0x769d7bcb, 0x08fda30d, 0x3d59dc2a,
3622 0x77b4d3fc, 0x791c61c5, 0xc33283fe, 0x78aa1cef, 0x823e66a8, 0xb02cc7f7,
3623 0x8f18ed0a, 0x062e31bc, 0xa1f0ba70, 0x2dc7ecbf, 0xa06b944a, 0x7efef3f3,
3624 0x9427b3bf, 0xa4b2f37b, 0x6f7efdfc, 0xd570aecf, 0x829bf1c3, 0x6ef9131b,
3625 0x9863076a, 0x377f85bb, 0xc91eac3a, 0x0901fffb, 0x00d0a8f5, 0x0000d0a8,
3626 0x00088b1f, 0x00000000, 0x3bedff00, 0xe5557469, 0x73dcfbb5, 0xe1dc8487,
3627 0xc2040464, 0xc06e49b9, 0x612f4865, 0x1213d41e, 0xde0d4b22, 0x00c10580,
3628 0x86120137, 0x7c07504c, 0x0040e3e2, 0xaa1a4583, 0xf50af8a5, 0x22d28342,
3629 0xb04a0834, 0xc141170c, 0xd6de8ba7, 0xa44f7d6a, 0x40932861, 0xd2bb6a52,
3630 0xf7b79457, 0x3b939df7, 0xed83a404, 0x58b593af, 0x9ef37efb, 0x77f7bdbf,
3631 0x52015000, 0xaaa8e601, 0xd08eceb5, 0x092bd00c, 0x72c06e60, 0xd80e35b6,
3632 0x37fc0ddf, 0xbb746b7f, 0x01e5e696, 0xf7473754, 0xa41c5fe3, 0xbfe6cc01,
3633 0xff5616a1, 0xd845cc41, 0x766f3d12, 0xe890eadc, 0x556679a4, 0x086e17eb,
3634 0xa1e6ca0c, 0x840cfada, 0x9f12a24d, 0x6e0f351b, 0xca7a01b8, 0x7773948e,
3635 0xde0bc361, 0xc5c2221b, 0x002300c9, 0x5c78174a, 0x439c1cfe, 0x2186f77f,
3636 0xb09e7468, 0x39cd23c0, 0x098a6584, 0x68c79cf0, 0xb1c6994f, 0x477f788d,
3637 0x617c67e2, 0xc1864ef6, 0x15483f08, 0x3a6f3c54, 0xeba236e1, 0x71eb15be,
3638 0xdf8841e7, 0x11f8137a, 0xcbbf5b9e, 0xfe3e47e9, 0x695dc5fe, 0x88772b04,
3639 0x66084410, 0xdcf015bf, 0x2f65f582, 0x56fb833f, 0xdaf78d6c, 0x88e2bbb0,
3640 0x3c7008bf, 0x252b7c0f, 0xe3d7971c, 0xe070c341, 0x71dd8445, 0x8428f23d,
3641 0xdfd982fd, 0x513de68f, 0xd927efe1, 0xd187faa3, 0xf4cc4fbe, 0xee3f7cff,
3642 0x04b6c4fb, 0x9248caaf, 0x44e1a682, 0x84041489, 0x7b7f0bd5, 0x04fc8cd2,
3643 0x9e8f83f1, 0xf2b8014a, 0xb6c408ba, 0x817f24ec, 0xcfdc4a9c, 0x703d05eb,
3644 0x5d29b89e, 0x22f6c4ca, 0xeff9ecec, 0x8d4ce7e7, 0x4fc4e59f, 0xd599e914,
3645 0xf3a50e1f, 0xbe70374f, 0x4d99face, 0xf397a7e3, 0xe7e73573, 0x339f8d4c,
3646 0x7e35788f, 0x4f892bca, 0x9f8d6af2, 0xeace1c0d, 0x3a7537c2, 0x4fc4f5e1,
3647 0xa7155e6c, 0xa60f885c, 0x173f909a, 0x4f508a76, 0x12a80b6d, 0x4485c3da,
3648 0xdf511250, 0x3f8d04ff, 0x7e610a0e, 0xe50ecdce, 0xd29e9106, 0xc49d47b5,
3649 0x453bb9d7, 0x3f2c704e, 0x73eee941, 0xc81f9e44, 0x24d53c25, 0x087942df,
3650 0x408aa5c0, 0xb7fbe12e, 0x825a7df2, 0x79e3e522, 0xde2dfbed, 0x36efc8cd,
3651 0x85c01587, 0x8384f676, 0x227265c1, 0x3a81679b, 0x505f3c00, 0xf8845814,
3652 0xdd3e50db, 0xb2159e90, 0x5905c6cc, 0x87ec5282, 0x7e13200d, 0x24288282,
3653 0x1d2fed75, 0x3e462283, 0x814c3bb5, 0x67ff48cd, 0x3c80d0d6, 0xffaf187b,
3654 0xe913b192, 0x03c835f8, 0xd252bce8, 0xccafc235, 0xfc8cd815, 0x6c4c0879,
3655 0x0cc087df, 0x982708a5, 0xd8713541, 0xba224f60, 0x3fa85990, 0xf1bf35e3,
3656 0x7410e1ed, 0xef82af21, 0x3fae7081, 0x73a55d30, 0xc14d0726, 0x1e0fe87e,
3657 0x090f0732, 0xb2714d08, 0x7c73c245, 0x913c84e3, 0x660cb0e4, 0xf15decf8,
3658 0x21f846db, 0x1326a5bd, 0x8129ebc7, 0x0a28f1d1, 0xdd32f89d, 0x8444470c,
3659 0x4439e28f, 0x5904b4f7, 0x0816f365, 0xa30ccdde, 0x54df8614, 0x2881bf0d,
3660 0x4bc87387, 0x0df76ddc, 0x3547d3d4, 0x069f707c, 0xf1cf5b27, 0x1edf9588,
3661 0xad004f8d, 0xcd6be256, 0x227fef63, 0x71359d20, 0x49f920f6, 0x6e5cb168,
3662 0x39f9afed, 0x48afe1e4, 0xc05f384e, 0xf4f90083, 0x04db06a8, 0xb87b3bb4,
3663 0x1e0d21ff, 0xa5ace8d7, 0xde0bca36, 0xdc5b0212, 0x03e73fb7, 0xd3ad8939,
3664 0x3b0347f7, 0x1026e34d, 0xed6bfc80, 0xb2562dfe, 0xbf5a79bf, 0xb22187ee,
3665 0x5dacde2d, 0x169f912a, 0x41ba6fc0, 0x8b3edad0, 0x13dc2958, 0x7afb25ef,
3666 0xa1ecdad4, 0x5e76277b, 0x5874df2c, 0xef53805c, 0x3e75f9a0, 0x03c03465,
3667 0x0bdbd3df, 0xcbda0a7c, 0xe39de1a4, 0x8e164a8d, 0x8e7f177f, 0x7828e864,
3668 0x452fc133, 0xd7253ede, 0xfce39685, 0x8a728f0a, 0xdcd39ffc, 0xa0fecc0a,
3669 0x58bbf191, 0x28061324, 0x28a37d1c, 0xb858f911, 0x6c9e605b, 0xe636e8ea,
3670 0x50f13a77, 0xd478619f, 0x76f413ec, 0x71bbc148, 0x36ceeeea, 0xb070a3c3,
3671 0xf27c6a2b, 0x9f1a8868, 0x1be91d78, 0x6a71b5a9, 0xd194f488, 0x4a8d9ff1,
3672 0x235b6c6f, 0x42dae3e6, 0x4ba74f3a, 0x65ffef0e, 0x835f19e0, 0x9d75d199,
3673 0xcc5075f9, 0xba6101be, 0x91df665c, 0x5dff223f, 0xe2a48229, 0xfc5f1aba,
3674 0x6117f26a, 0x3d181a7a, 0x8f9d78a1, 0xf1a37cd1, 0x06bfa442, 0x8d55f1f4,
3675 0x67cdf20a, 0xd2af9cea, 0x3f3ab1fc, 0x337f7d70, 0x7d6c4973, 0x4686a6d2,
3676 0x9fa61ed5, 0xbe18b3b5, 0x7c21ee49, 0x295fd339, 0xc42f48ff, 0x4ef906b3,
3677 0x5ca74557, 0x5f8c75d5, 0x6d1131a1, 0xa62337c2, 0xff022ddd, 0x52fc11de,
3678 0x59f949d7, 0x7cd2f811, 0x8b4a67c4, 0x127fbd10, 0xb4ddcf1f, 0x1d1d51ae,
3679 0x90fc036e, 0x5e8227f1, 0x9d299fc6, 0x9be75ef2, 0x6ac7eb85, 0xfee019fc,
3680 0x45e88fa1, 0x7d3972fa, 0xd2fd2881, 0x65bcaef5, 0x14b48aed, 0x2004b38a,
3681 0x68f2c37a, 0xe7fc91f2, 0x9bff3a4b, 0x586f8442, 0xa13dbc1e, 0xa9bf3f59,
3682 0x64abf491, 0x6f2f4eb7, 0xf70bf587, 0xbff216fb, 0xea7c7a21, 0x53f5e8f2,
3683 0x667f73a0, 0xf53a5357, 0xfa43cf17, 0xbcfc69e6, 0x4853537f, 0xbf76fae5,
3684 0x67ac353b, 0xad12b365, 0xed85bf74, 0x6be31b71, 0x93b8de27, 0xbc0fe380,
3685 0x07c7cd1f, 0xb27b79ea, 0xc1af9b7b, 0x4d7ed91e, 0x7764e3e7, 0x7d72bd94,
3686 0xc4fd1df9, 0x4024f37b, 0x161fbd94, 0x4487dba3, 0x437baf9d, 0xa750e58f,
3687 0x1f5efe7e, 0xfc0fb7dd, 0x719f1a30, 0xc7bdbd36, 0x6fe91857, 0x5f1937d4,
3688 0xf9f4fc74, 0xd7a25f45, 0xddaaf3c3, 0x729afa6f, 0x320cdee8, 0xc49a56ff,
3689 0x71c75c21, 0xb56a47bc, 0xbf68a938, 0xbcd00be8, 0xc2cf416e, 0x873d309c,
3690 0xff99169e, 0x8085eb56, 0x196cfd07, 0x04ba56c8, 0xa5628267, 0xcb90f5fb,
3691 0x9c15e8b5, 0x7169f87f, 0x3df70051, 0xc59928b9, 0xadb81f9b, 0x5d87ff8c,
3692 0x6366d37d, 0x0cc250fb, 0x0ef38cab, 0xc1963b3d, 0x7fe93bb7, 0x337a47d7,
3693 0xc9a5ce2b, 0x97e65df9, 0xf6f0250e, 0xbedbf72a, 0xd5af28a5, 0xe7ed996e,
3694 0x5ad2924f, 0x39e13f50, 0x09916c0b, 0x098fef4f, 0x6de7b2bf, 0xfc239f03,
3695 0x4695de96, 0x41ff2ef2, 0x9c4f5149, 0xe2c2be57, 0xab5e7015, 0x7c274a49,
3696 0x658dcffd, 0xb96b30fa, 0x18fbd506, 0x4fd5f83c, 0xcf749dea, 0x1c58146e,
3697 0xcd17f773, 0xbb62e7ef, 0x4bd321b2, 0x30e81ea8, 0x9ce78481, 0x202fdf5e,
3698 0x899dcaa2, 0x3c777baf, 0xbf340f9f, 0x7c7cbaf2, 0x2f9a60fc, 0xfe70cb4a,
3699 0x7017ec39, 0x712adcfc, 0x397840b3, 0x2404dd1d, 0xc097dce9, 0x2b73f0ae,
3700 0xb865816c, 0x7fbb69cf, 0x673a7afa, 0xd29605bd, 0x93d7413a, 0x4e5f198f,
3701 0x3f5cba4b, 0xa1cfcc6e, 0x2dbd3679, 0xca9f2195, 0x157a9d4c, 0x2aefbc04,
3702 0xb5fb7912, 0xb6f91f4d, 0x2f73fae0, 0xaaf163f5, 0x276ca19c, 0xa19d3d7d,
3703 0x3ffb20ec, 0x462ed5f8, 0x3c4bfb5f, 0x51d03b6e, 0x111e569e, 0x315c5427,
3704 0x68387d33, 0x7c231f95, 0x23eb760f, 0x6a2f2ca8, 0xf8a12e4e, 0xe28cf511,
3705 0x45ebd46d, 0x1f126ebb, 0x2645ba36, 0x4ddf43af, 0xea472d1d, 0xf9867ab7,
3706 0xde64e289, 0x6d6eea3e, 0x9cafd154, 0x33822db5, 0xfaf5e159, 0xe8aef9fe,
3707 0x39983938, 0x81d128e1, 0xca30c679, 0xeb7cf453, 0x0733f533, 0xf533f1c9,
3708 0xe3630653, 0x43a74ad4, 0xde7fe725, 0x1c9330e1, 0x9c979a4e, 0x62b938a3,
3709 0xb9f985a3, 0x8ba98d8a, 0x414e29db, 0x5740f17d, 0x2c32927a, 0xda5b9e8c,
3710 0x2beedaa5, 0x07191dec, 0x5dad7fb4, 0xf36a6eb6, 0x6d6fd935, 0x5b129597,
3711 0x2d1b4503, 0xcaabb23e, 0xa0330e21, 0xf1b31cbf, 0xefa42d9d, 0xf3e20b95,
3712 0xe578886c, 0x53931b46, 0x4aa1c3ab, 0x3a77ee38, 0xaf0889cc, 0x6e8c4dba,
3713 0x60cc8657, 0xb8e60881, 0x5397063c, 0xf10d711e, 0xc5f6c649, 0xa3ac2f45,
3714 0x0412e4b4, 0x3d430d26, 0xfd70a6bd, 0x0c5bb6bc, 0x66047e50, 0xf98c5cc5,
3715 0x7ee01cd3, 0x5dbdfaa2, 0x39fc7cd6, 0x41f2aea7, 0xf9f965c8, 0xfcfc98e9,
3716 0x8e1e7474, 0xfe51a61b, 0x30aaffcd, 0xc43b24de, 0x5e6a3d7c, 0xd51e7e44,
3717 0xf2d0c96f, 0xa3c83ceb, 0x9d5aee38, 0xdd829b25, 0x13da3b4a, 0x41b059d2,
3718 0x2e56f860, 0xc4360312, 0xe79920b7, 0xa0976747, 0x5e8caddc, 0x2576c255,
3719 0x37c4b1e5, 0xf8710210, 0x0b0dbef3, 0x1767e4cc, 0x4ca57e6b, 0xdbe91f00,
3720 0xfa6f7899, 0x36c78a02, 0x56be33c6, 0xc7ee78fe, 0xd6bae12f, 0xa229c5a5,
3721 0x5e87d61c, 0xfee03e9a, 0xde149710, 0x67d2fce7, 0x0bdf49d2, 0x4857ee5e,
3722 0x22657871, 0x26e298ec, 0x974cf539, 0x9579e1ed, 0xe6ce9ecb, 0x8083e2f3,
3723 0x2ad970f1, 0x6f01d191, 0x521e02d8, 0x4520fec8, 0xf2d66df2, 0x1cd6acf7,
3724 0xd34a5bfe, 0xfc991ee2, 0x9c5faf37, 0xced171c6, 0xc676a7f8, 0x066ff8bd,
3725 0xf993d5ed, 0x57d13f09, 0x4c66126a, 0x5bb4fb60, 0x328b8ec9, 0xb7701e78,
3726 0xbdd2cb06, 0xea8f09d3, 0x32ef3635, 0x1c47df37, 0xb181e1aa, 0x5429b54d,
3727 0xf3c223f1, 0x0b779b4d, 0xbc796dc9, 0xb924ef12, 0x0e7af282, 0xad98c7ab,
3728 0xa72fb449, 0x76e64ab3, 0x989ffd8c, 0xc1dabfb1, 0x227560fd, 0x15cedbf2,
3729 0xb7fb84c4, 0xbe4cafd1, 0xf0dccf5f, 0x85f3cefa, 0xb99df8f0, 0x49e4afc4,
3730 0xdb1e108f, 0xc8af6645, 0x29c3358c, 0x0e2ed96e, 0xf1a64e7a, 0x57e445c3,
3731 0xc81cefe7, 0x1db2b6e2, 0x617bb21f, 0x56e726be, 0xc7296f2d, 0x33844ef6,
3732 0xf8bdb832, 0x666ba845, 0xe8bf9e6d, 0xabc7d6f2, 0x9c985957, 0x937fd1aa,
3733 0xfa5ea8e3, 0xb56fb65b, 0x79469423, 0x961bf556, 0xcb6fe4a1, 0x97cbfc35,
3734 0x09fd19f6, 0xc5b94fea, 0x543dd125, 0xa95b16a5, 0xb028d55d, 0x6a5d7876,
3735 0xe7e3e93a, 0x4938f7cb, 0x07c4ce4f, 0xb4df743d, 0x52f7882f, 0xc0da887e,
3736 0x97cf93ee, 0x873f367b, 0xc85259ed, 0xacf8e021, 0xc89332c7, 0x82949f2f,
3737 0xd93f1a56, 0x5b5136ec, 0xd4d1a491, 0x62dfcc56, 0x55d1cfed, 0x43fa6b35,
3738 0xe046a5fe, 0xed7aacf2, 0xcf0335b0, 0xffc9a95b, 0xb30ff6ca, 0xa756cfc9,
3739 0x397db287, 0x14d9de4c, 0x04cfc2ff, 0xbcd6df76, 0xba60ebc6, 0xde486bbc,
3740 0x34f35f68, 0xdeecd739, 0x7de924f3, 0xaf3bc90d, 0xdea0beab, 0xaffd611e,
3741 0xbe022a6f, 0xc5e908fe, 0x53cc7899, 0x05b97b79, 0xbcacc7db, 0xbfe6acfd,
3742 0xf790bfb0, 0x4f3c39ab, 0xac6b79e3, 0xbe4adfbe, 0x263f244d, 0xa7f31b0f,
3743 0xadbd1a4d, 0x9270deab, 0x3f6caefc, 0xc1c8eefc, 0x57e61784, 0x5ef44df2,
3744 0xd12d47e3, 0xb3f864ef, 0xe896a1b8, 0xefe98675, 0xdecd73d4, 0xa7d3816a,
3745 0xd66b5bd3, 0xb5c7d7e8, 0x3a345bf5, 0xd7e340ab, 0xbedc7eee, 0x7b227b34,
3746 0xa749fca5, 0xd7c49fcf, 0xbef9faeb, 0x4d6edf46, 0x766a414f, 0xbe487f12,
3747 0x7f5067e4, 0xcd50eb14, 0x2b94e06f, 0xfcb1373b, 0x8e979751, 0xfbe1a7ff,
3748 0x0a4c4942, 0x04d5b1cb, 0x5ded9a73, 0x1a23c5ef, 0xe8ad4f1f, 0xfc82de9e,
3749 0x06f31cfb, 0xbea36e96, 0xd3ce239a, 0xaf3f46f5, 0xfdc95b60, 0x86600eac,
3750 0x9fafed20, 0x304d527b, 0x81273ed3, 0xbf8e87db, 0xf505976e, 0xe81feed3,
3751 0x1c5779a4, 0x37443999, 0x0cd3ff3f, 0x5457ad89, 0x4af3f307, 0x7010108b,
3752 0xebc094e8, 0xec56a782, 0x84e79671, 0x327ffdf5, 0x62ff4e84, 0xa78aeb4e,
3753 0xfa117fae, 0x782cf0cc, 0xd4fdf276, 0x7a16f4fe, 0xd74df3a9, 0xca9c584f,
3754 0x3d5893e2, 0xca7dedad, 0xf6c5e74a, 0x19caf1eb, 0xfec97bca, 0x10faf2f7,
3755 0x5923872c, 0xeeb0f711, 0x0ecff1d7, 0x84f7c343, 0x65e72f7e, 0x2efa3066,
3756 0x1f35b341, 0x85d578fd, 0xa6539150, 0xf5644fb8, 0x08bfbba0, 0xb3d42e8a,
3757 0xbceeddaa, 0xeaad7bc8, 0xa7a611f2, 0x756210d5, 0x1f55b2cb, 0x7d230f16,
3758 0x45c629fc, 0x8c5757e4, 0x3d5c52b5, 0xa1cccb77, 0x0dd3e724, 0xb8badefc,
3759 0x142bc87c, 0x786e9f17, 0x0e666d21, 0x1a282bad, 0x6b65fd89, 0x9e393207,
3760 0x53150f89, 0x1171fdbb, 0x6a358ea8, 0x53c590cb, 0xd1ca3db1, 0x39e89137,
3761 0x8e1624d9, 0x2cfb908c, 0xa54f1690, 0x92eccc78, 0x6a4e0ec8, 0xc2deabfe,
3762 0x933bd2e5, 0x277279eb, 0xa0bafee4, 0x44db3ebe, 0x7e84db7c, 0xc5aee913,
3763 0xd507a018, 0xff1e054d, 0x5c42b1cc, 0x1fd63ccf, 0x4dfb13d7, 0x09aa2709,
3764 0x13c7b6ff, 0x4ddbaa24, 0x883781b3, 0xfb0769ed, 0xa6e851e4, 0xc6287168,
3765 0x9d5cecab, 0xbdf9fa4f, 0xc51eb932, 0xf5e20bee, 0xc76fa4a1, 0x19d63ab4,
3766 0xcb8bef0d, 0xee893a7f, 0x3d5b8ba5, 0xf9f74449, 0x140df1fd, 0x70b79cc7,
3767 0x7fefa57f, 0xd88f77bb, 0x77d88ef7, 0x0c65800d, 0x189901af, 0x6740253f,
3768 0xe3eba4fc, 0x70baeaed, 0xcdd78d22, 0xfaf53db5, 0x5ecd1ffa, 0xd64de257,
3769 0x12f2f0e9, 0xce365864, 0x9e083aa3, 0xe5f0985f, 0xd9c510ae, 0x86c9368d,
3770 0xbd259ef4, 0x86fab6c6, 0x1481eac8, 0x9f9e9313, 0x8050637d, 0x138ab7f2,
3771 0x2cd15dbc, 0x7884a804, 0x22b3ed64, 0x718d9fcd, 0x2221775e, 0xed717d6e,
3772 0x6bff5224, 0x9ecaff5e, 0x56daff38, 0xe037bd81, 0x5e263db0, 0xfca7b77d,
3773 0xf5578bef, 0xe754bffc, 0xa42ef6bb, 0x57cf5bf3, 0x0c5ea20e, 0xedf30bcf,
3774 0x2c3992ea, 0xc4bcbd5e, 0x709b60cf, 0x5628cd6a, 0xbab176e7, 0x5e5a2fef,
3775 0xdc917b10, 0x4ebc0f77, 0xbb48e779, 0xbdbb224b, 0x401164ba, 0x63abad36,
3776 0x5ebb9750, 0xf77bb9df, 0x6aeeb621, 0xa37da0cb, 0xbb01dd70, 0xcee7f98b,
3777 0xf79892f7, 0xbc58ef91, 0x7dd913dd, 0x7451dfc1, 0xd772ebf9, 0xded4abe9,
3778 0x2ffc7445, 0xdee5c53d, 0xd33aded9, 0xfa1ef449, 0x11bef251, 0x9704ef24,
3779 0xb9da7144, 0x5c5fdcf5, 0xf2bd7388, 0xc2fbca20, 0x80698986, 0xa1f6727e,
3780 0x7f512787, 0xa2417ec5, 0xbfbbdcf8, 0xd3f949c4, 0x4eadcdef, 0xbf7ef3ca,
3781 0x0abf7f5e, 0x469fe488, 0x3489838e, 0x0cd0647f, 0xe233ee32, 0x2337ae41,
3782 0x0a039b2e, 0xcfd83bc5, 0xbbd716ea, 0xfe05bab1, 0xfde09725, 0xaf2f7b39,
3783 0xd072e873, 0x1a51adf3, 0x9333079d, 0xfeb4ff38, 0xffbce182, 0xe35d86fc,
3784 0x4d8bbf69, 0xbef08916, 0xfb6164da, 0xc93cc3cf, 0x5b33ef44, 0xed421e79,
3785 0x37d93778, 0x35e637cf, 0x7aa37cf3, 0xbab14581, 0x4167eaba, 0xe7ca3cc4,
3786 0x73a64fb0, 0xa7fa6ae7, 0x853cedeb, 0xef0f37d3, 0x5637a235, 0x99a1138f,
3787 0x4edddbbd, 0x3d56ff9f, 0x37e31dde, 0xa982584e, 0xef9f8993, 0x77565e89,
3788 0xe87e85b9, 0x403f257c, 0xc3ebac7a, 0x0517d43c, 0x079a9287, 0xea3e93e6,
3789 0x9bfba1fa, 0xa5e35bf9, 0x2dfe51b3, 0xdb5daa31, 0x1b3a53d2, 0x7a69e719,
3790 0x99823908, 0xe9d2abe8, 0x535d6b8b, 0xf8a6b082, 0xc421150f, 0xafe88473,
3791 0x9152a4f0, 0xc05e8bef, 0xc69ed964, 0x642091de, 0x061ef601, 0x6a17ff4c,
3792 0xa2b1b075, 0xe519bfbd, 0xf3742a58, 0x96d93e52, 0x2e4d50ef, 0xf9327796,
3793 0x04253e96, 0xc44ffb00, 0x9ea9733b, 0x0e420330, 0xbb3fb637, 0x464d7643,
3794 0xf5ebd5f9, 0x2d63b56a, 0xe65767d5, 0xfffb5a8b, 0x3aa8944a, 0x8afdffc8,
3795 0x530f20ea, 0xffb5943d, 0xf6f5425a, 0x71b477b6, 0xe3425eb8, 0xab402b6d,
3796 0xdbc57d8b, 0x85c7d03f, 0xdb5fb409, 0xe45c7d2a, 0xfdf5e7ed, 0x98daf6b5,
3797 0xe331a5f1, 0x1ff6f12f, 0x504e227e, 0x88f5c273, 0x9ef7b527, 0x7d5a65d2,
3798 0x8336f4c2, 0x93df2cf6, 0x1d17cf54, 0xe7941d67, 0x27947914, 0x7bf0dde9,
3799 0xcd7ffd7d, 0x44af3844, 0x9f78ad50, 0xd9026fc1, 0xda75e7c4, 0xe1ffdd7c,
3800 0xc9bac83c, 0x6f3439bc, 0xcb3cd448, 0xda7de6cd, 0x376ebf75, 0x89e2979b,
3801 0xe77f4fde, 0x9c56e29d, 0x278f5f34, 0x94afef62, 0x8c471e2c, 0x699254ca,
3802 0xb40b239e, 0xe9bc42b8, 0x16615a3b, 0xbb4a038f, 0x99b677f1, 0x32711d43,
3803 0x37e431e2, 0xf9077afe, 0xbe3c0db3, 0x98efb57a, 0xf41fb43e, 0xc757be8e,
3804 0xcc43ef21, 0x3cb3b5af, 0x86fb8ff2, 0xd1bfc8b8, 0xebaf24db, 0xea9f7da5,
3805 0x759dc5ee, 0x67dfbea6, 0xacb74def, 0x409df543, 0x5f71a875, 0x66f3bd71,
3806 0xc93efcf5, 0x01b0da75, 0xb48fc8dd, 0x25effba4, 0xbb0da63c, 0xf9da88bb,
3807 0xaef662b6, 0xefafa3dd, 0x6b3fea1e, 0xa1089e52, 0x6346fb3e, 0x7f611b20,
3808 0xa2130a13, 0x983f0fda, 0x3d844a0c, 0x57b87a4e, 0xd291fb54, 0x53f9a8cc,
3809 0x3515dd67, 0x0d0b6c5e, 0xf69c7966, 0x78ab7cce, 0xc61df3a2, 0x9f3debc1,
3810 0xc7d3fbed, 0x6a1fa28f, 0x5d59126b, 0x2dfeee77, 0x70828f1f, 0xec46805c,
3811 0x74bdfb22, 0x93ca044c, 0x5757eb63, 0xb46eb420, 0x80f135f0, 0xe5c58474,
3812 0x8d1fa8ff, 0xc6a34bc8, 0xfb4567a7, 0x1f756bd3, 0x23180ba5, 0xac7568d5,
3813 0x594f7b2b, 0xbbff5e65, 0xeafd0371, 0xde90b47d, 0xfe903b3b, 0x2d7fa841,
3814 0x38adaca7, 0xe64b23de, 0x05ef4779, 0xe5007966, 0x4acc0b11, 0xa1171e84,
3815 0xbea8b81d, 0xde3f71d2, 0x83474878, 0x74d7d6c2, 0xb8bb5898, 0x5465b4d7,
3816 0xc336aa6f, 0xc754dd80, 0x6e2c1d90, 0x7df9fe2a, 0x67e580e3, 0x63f74282,
3817 0xe7c2a355, 0x4c1ebf8b, 0x1db1b0f5, 0xc53ed8e3, 0x50131c22, 0xe0281f37,
3818 0x31d5d17e, 0x76d7f581, 0x6e0f9b00, 0x54ace2ff, 0x7144aefe, 0x29aefe6f,
3819 0x72888985, 0x86795bb2, 0x2297ebf4, 0xfbbb222c, 0x86f7bde5, 0x5f7a1494,
3820 0x32283418, 0xc59358ff, 0x6a400ddf, 0x5df74ebf, 0x990481ed, 0xc5eac8e4,
3821 0xb7ed0f14, 0xec7c77b1, 0xda90f567, 0x94cdb603, 0xdb3ad5e7, 0x0afec9b3,
3822 0x8907c60e, 0xe307438e, 0xcdbf2ccd, 0x73a1aff4, 0x2bf60e0b, 0xd9537ca4,
3823 0xf3033367, 0x98f7ca63, 0xca589e3d, 0xd25d3ae4, 0xea37fb04, 0xbfbf6c63,
3824 0x4cabf381, 0x872ebbe3, 0x7eef8d72, 0x1a659f8d, 0xdf1067df, 0xc5f2ee91,
3825 0x587b6fc8, 0x29a2c52e, 0xb260fd7b, 0xca5e3e8f, 0x15bf743f, 0x8eaaf7cb,
3826 0xeaf7c638, 0x7c9a1e8e, 0xa1c945bb, 0xb58323bc, 0xdb7dba07, 0x7ae2ce89,
3827 0x5fee2f94, 0x287a0f6e, 0x17519a3f, 0x87f7a5ef, 0x45dd8b6b, 0xab85d7c4,
3828 0xfee6e1b0, 0x8ab5ee8b, 0x74add4df, 0x4a65c844, 0xb8c82e47, 0x2c8ec4df,
3829 0xebed5f06, 0x2e724bdf, 0xcecf18eb, 0x66c8ef29, 0xa95c62e7, 0x23fef8b0,
3830 0xfbffbe3d, 0x20b9c7be, 0x21811b30, 0x75dfca8a, 0x26ef3602, 0xcbfdfc21,
3831 0x54238c4c, 0x1696673c, 0x5b650e7f, 0x6c9b7f22, 0xf8424381, 0x72ff18fb,
3832 0x9da86a91, 0x3be5d7f6, 0x678c7c99, 0x26e5dd70, 0xd543930b, 0x950f5fa1,
3833 0x9092fc70, 0x4eec9ddf, 0xc47ff24d, 0x810995ee, 0xcf6c161d, 0x73977e7f,
3834 0x8fd61c84, 0x43d07366, 0xf919a67e, 0xe6b5f548, 0x00b8e2d5, 0x942667af,
3835 0x9eb5b80c, 0x83b8ebcc, 0xb79febf1, 0x286b4dd3, 0x66cb869f, 0xed879796,
3836 0xb78ef375, 0xb8127f48, 0x6ecadcfe, 0x58912cf7, 0xbf6b167c, 0x959eddba,
3837 0xf9227ffd, 0xcfadbbde, 0xfee11fe0, 0x584a5363, 0x99ef1cbd, 0x87583ca8,
3838 0x7f31eec9, 0xb3b7f9a1, 0xcac7bb6f, 0xcf6b12f8, 0x6db37d7a, 0xb2019dff,
3839 0xf68093f7, 0x2fb47a4f, 0xd9a2de41, 0xdd07f33b, 0xb3af815c, 0x339951f7,
3840 0xddef14ed, 0x9e1ddec4, 0xdece6fd4, 0xf23939bf, 0xf85201bc, 0x1c846afb,
3841 0xa43d50d7, 0xc9852db8, 0x2e9b9751, 0xba7e5d47, 0xfd963ebc, 0x637d1177,
3842 0xd775fdb6, 0xd55762ff, 0x53073deb, 0x793b767c, 0xfee1e3dc, 0x8f285ff6,
3843 0xf7373c7b, 0xfe7af7bf, 0x7e8bff09, 0xe26ec072, 0x5bc3a64f, 0xa3f9872f,
3844 0xb741e3cb, 0x2433d8bf, 0x68241fcc, 0x6f4fd530, 0x9ee98fc7, 0x99fefc6f,
3845 0x67fa0b7e, 0xfff433fc, 0x1292f9c3, 0x78b12f9d, 0x49e50466, 0x5527963e,
3846 0xfc83bd53, 0x4fe818df, 0x15bd59f1, 0x9aa43e58, 0xee4979ba, 0x42d97625,
3847 0xc5259771, 0x3afd216b, 0xbea211ea, 0x48f56bef, 0x2496087d, 0xbd0ddfe8,
3848 0x128cf2cd, 0x43cb4997, 0x30f6f30e, 0x09bdfc7d, 0x0c94d794, 0x18e1c6d2,
3849 0x6c089f1f, 0x472df9fc, 0xcdb25e59, 0xfc20aca3, 0x4c48f05e, 0x74b7173e,
3850 0xfde7e3ef, 0x5747c40d, 0x04bbffb2, 0x5676ad6b, 0xda136b4f, 0xc3b91773,
3851 0xdfb57ff3, 0x8817f271, 0xaca3c877, 0x502f79a1, 0x12352231, 0x16ad79f2,
3852 0x84e6f748, 0x5601cbfb, 0xae58bdd0, 0x6044fd1e, 0x1c3c1df1, 0x1fbe9437,
3853 0x959f7604, 0x35b1dfeb, 0x06c77f44, 0xb3e3175e, 0xfea11dfe, 0xb09de09d,
3854 0xd7bed25c, 0xf92370db, 0x866ce4eb, 0xafdf1173, 0x2e9059b5, 0x22efd757,
3855 0xff477d85, 0xabd6fb42, 0xf2cf1ad0, 0xd7efe8d9, 0x4f3013aa, 0x7b287e45,
3856 0xca3b411c, 0x04f6e171, 0xab986756, 0xa47b8fd7, 0x31f44bb0, 0x3d03d389,
3857 0xfd7dd8d2, 0xe74ba6b8, 0x2cff4097, 0x6fcdc533, 0x1e23355f, 0xeff1f66f,
3858 0x99543925, 0x285f483e, 0xdea45d53, 0x95d0f749, 0x4a97a21d, 0x9d5a5530,
3859 0xb5529a1e, 0xbc188afa, 0xb98fc717, 0xf54cdcef, 0xfe1ec3bd, 0x0dd9714e,
3860 0x5d519dec, 0x10b6936a, 0xa70fd72e, 0x71ed8d3f, 0xe979f719, 0xcef2eefd,
3861 0xa366b367, 0xc05ad01c, 0x00fae2c9, 0x36c1675b, 0xd2b91f7d, 0x96ba42fd,
3862 0x4220fbbf, 0xbb9f3a1e, 0xa28f1ff0, 0x0e29bdfa, 0x09dede98, 0xc78a241b,
3863 0xa58c3975, 0x838a53c7, 0xc8efe0de, 0x6ce8050b, 0x3e725c53, 0x5dfbe78e,
3864 0xb0ef8beb, 0x52cd017c, 0x6cdbaa8d, 0xfcf37998, 0xa5602522, 0xbae9bfad,
3865 0xf68f25e3, 0x06103e4e, 0x791deff2, 0x9b52a35d, 0x952c5633, 0x6a4f44cd,
3866 0xbfe4979c, 0x77666370, 0x7c3043f2, 0x83ce441d, 0x2f4cc90d, 0x1845ba56,
3867 0xb7367a8e, 0xfba4c905, 0x160ee5a8, 0x92d83df7, 0xe313a0c4, 0xf8bfea4e,
3868 0x7983fbca, 0xa7cb871d, 0x63eed5f8, 0x6afb1c58, 0xf563063f, 0x4fb9fcd6,
3869 0xd84b77a1, 0x123ab023, 0x75ca12f9, 0xc7563d75, 0x6eac8378, 0xeec096f7,
3870 0xbf9b293d, 0x75495463, 0xd20e1dec, 0xc22f2c7d, 0x2ec94b25, 0x6cddf45d,
3871 0x8faeff12, 0xf7dacce5, 0x3e4d4eb1, 0x7df9d009, 0x881bef6c, 0xccb67277,
3872 0x3d208bbf, 0x264949c1, 0x5cfc9bb7, 0x393fb66a, 0xe6bde29b, 0x9f54459d,
3873 0x4aea0b9a, 0x13d94770, 0x6ae848dc, 0x77b497a7, 0x2b0f5d31, 0x852173b5,
3874 0xc6855feb, 0x3e8d4ad6, 0x2b5418cb, 0x4772cfa4, 0x377ae6f6, 0x80fe8691,
3875 0x1f0adf7d, 0x40fe3dfc, 0x3f7407bf, 0x2cf535fd, 0xc7d2cfc6, 0x7ce3ddb9,
3876 0x0ffd175e, 0x511f5021, 0x6faceac7, 0x77b0233d, 0x326ebd6d, 0xbd0a0ccd,
3877 0x095422ef, 0xd2f7d296, 0x8598e104, 0x62e38b9d, 0x8cc3ab12, 0x63ebfc62,
3878 0xd39d5952, 0x9830ebce, 0xfd43dc27, 0xbf66ead7, 0x7920f8cb, 0xc51bf7d9,
3879 0x6c4f5e36, 0xdf644f7f, 0xee8add1f, 0x555e5af1, 0x6f62e07b, 0x5f71dbb2,
3880 0xf7e27e89, 0x11e38b71, 0x67c753ca, 0xf197f7f3, 0x9828a6d9, 0xe98bfb2e,
3881 0xea3b3fdc, 0x5f909ba6, 0xc167be7f, 0x8771df2b, 0xae887ae9, 0x40a7ba2c,
3882 0x4d3e90b6, 0x371de504, 0xf06df56e, 0x5064f6b3, 0xf7496c19, 0xa54eca4f,
3883 0xac0310ef, 0x7dc47c7d, 0x8b125eac, 0x655e2c7f, 0x2c5efcd9, 0xc14536cb,
3884 0xcfdfb271, 0x5e1852f1, 0xd1365fb8, 0x24f5e3a5, 0xdfea4ee9, 0x88555f25,
3885 0x7ccaef90, 0x02d7df91, 0xf2c3afbf, 0x25496b1d, 0xbd108ef9, 0x0c17ab4c,
3886 0xe0f48479, 0xa5eadd9a, 0xbe5d3b77, 0x9bde8108, 0x638e72c3, 0x88ba52fa,
3887 0x6c91cbeb, 0x6a0baf37, 0x580e4772, 0xf942ae28, 0x9a7c4d3f, 0x75e44237,
3888 0x3fe50938, 0x4addc980, 0x82995e36, 0x2ae8cf72, 0xde2d5adf, 0x66e2d1ad,
3889 0x66f51fbd, 0xeae9f105, 0x89fd61de, 0x4607b53f, 0x7a9fc4c8, 0xd4dbcf13,
3890 0xd0ead6ff, 0xa38bc99a, 0x47ef62ee, 0x297af660, 0x45be2aff, 0x9355b29e,
3891 0x961ef1cb, 0x5fb60171, 0x4076bbf4, 0xa6809fd3, 0x9c70ff57, 0xe2a21fd5,
3892 0xffa211ac, 0x754fe265, 0xf32b55dc, 0xfe7bda63, 0x19b37a56, 0xd11fd612,
3893 0xb26ff0ea, 0xf5cbe247, 0x55f9f506, 0x44e7ff5a, 0xa64ce7d4, 0xef28e7cf,
3894 0x75e56e3c, 0x156456e7, 0xff107ffd, 0xccbbfccb, 0x3e9a77f0, 0xbc512b06,
3895 0x8042e704, 0xbad0f9c1, 0x9fce1072, 0x469658d8, 0xfc9854f8, 0xa2ad3eec,
3896 0x3be9bc2f, 0xec2f681b, 0x76fcfc81, 0x7a77d2c3, 0x5e538a20, 0x5c285b74,
3897 0xb041b49b, 0x97be40f4, 0x41582d34, 0xb78fb46d, 0xb70f4e48, 0x0ee77a6c,
3898 0xe39d17ec, 0x8f1c7d98, 0x1cac5391, 0x45fc6b0e, 0xd39b787b, 0x70ba30a5,
3899 0xa1ed4dfd, 0xe12bdd06, 0x01ffffa5, 0xd5b93efd, 0xefd023ff, 0xe3781b15,
3900 0x7a6ec8e2, 0x3fbfcc83, 0xf3e7f68f, 0xfa27df80, 0x923afa7e, 0xf397dd20,
3901 0xf4979ba1, 0xfb8592ea, 0x807d4bcd, 0x0125c1d9, 0xf0bcec2f, 0xfee906fd,
3902 0xe199791e, 0xf4d6a37b, 0x39f92e5a, 0xc77e57bc, 0xe699e2fc, 0xe4dd0395,
3903 0x64e903ff, 0xd99f96af, 0x735ff5bc, 0x9510ccbf, 0x80ceb4d3, 0x01a03406,
3904 0x0340680d, 0x0680d01a, 0x0d01a034, 0x1a034068, 0x340680d0, 0x680d01a0,
3905 0xd01a0340, 0xa0340680, 0x40680d01, 0x80d01a03, 0x01a03406, 0x0340680d,
3906 0x0680d01a, 0x0d01a034, 0x1a034068, 0x340680d0, 0x680d01a0, 0xd01a0340,
3907 0xa0340680, 0x40680d01, 0x80d01a03, 0x01a03406, 0x0340680d, 0x055ff01a,
3908 0x328d1fff, 0x800060f6, 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00,
3909 0x30001131, 0xee300408, 0xd80ea5ea, 0xabdef271, 0x964d2104, 0x5dbbcce4,
3910 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3911 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3912 0xee017e3f, 0x0014ab55, 0x000014ab, 0x00088b1f, 0x00000000, 0xc5edff00,
3913 0x30001131, 0xee300408, 0xd80ea5ea, 0xabdef271, 0x964d2104, 0x5dbbcce4,
3914 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3915 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3916 0xee017e3f, 0x0014ab55, 0x000014ab, 0x00088b1f, 0x00000000, 0xc5edff00,
3917 0x30001131, 0xee300408, 0xd80ea5ea, 0xabdef271, 0x964d2104, 0x5dbbcce4,
3918 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3919 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3920 0xee017e3f, 0x0014ab55, 0x000014ab, 0x00088b1f, 0x00000000, 0xc5edff00,
3921 0x30001131, 0xee300408, 0xd80ea5ea, 0xabdef271, 0x964d2104, 0x5dbbcce4,
3922 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3923 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3924 0xee017e3f, 0x0014ab55, 0x000014ab, 0x00088b1f, 0x00000000, 0xc5edff00,
3925 0x30001131, 0xee300408, 0xd80ea5ea, 0xabdef271, 0x964d2104, 0x5dbbcce4,
3926 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3927 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6,
3928 0xee017e3f, 0x0014ab55, 0x000014ab, 0xffffffff, 0xffffffff, 0xffffffff,
3929 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x40000000,
3930 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
3931 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
3932 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
3933 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
3934 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
3935 0x40000000, 0x00088b1f, 0x00000000, 0x62f3ff00, 0x51f86063, 0x408cc10f,
3936 0x7f120cb6, 0x66476028, 0x48107d08, 0xf3e2061f, 0x2fe9a48c, 0xb9b04160,
3937 0x40afec80, 0xa8597833, 0x88a1bee7, 0xcfd2738f, 0x81ae792e, 0x66322ff7,
3938 0xe86067e6, 0x6ff047e4, 0xb3caa3f2, 0x3dd7d3f0, 0xb000c6b4, 0x00eeff4a,
3939 0x0000eeff, 0x00088b1f, 0x00000000, 0x7dd5ff00, 0xc554780b, 0x3d9cf0d9,
3940 0x3764dd97, 0x2485cd9b, 0x200d8410, 0x125c40a2, 0x126e20ee, 0xc3116088,
3941 0x65e28145, 0xb201ae41, 0xdb3f6911, 0x5cbb7ffa, 0xc6d6a444, 0xa0b45b4b,
3942 0x06a2828b, 0x82482459, 0xa5c8ba1b, 0x5835b5b4, 0x0da978aa, 0x24c4dc88,
3943 0x97f4b004, 0x3bef3fca, 0xce7bbb33, 0xf4bc4c6e, 0x7d6f9ffb, 0x7339867c,
3944 0xef3bccce, 0x6779de7d, 0x313b10a2, 0x0ae42775, 0x64246efc, 0x19084c99,
3945 0xbbc32d14, 0x32413cbf, 0x46bcf909, 0x08f39a75, 0x86a1d929, 0xc5f5a46f,
3946 0xd400a41b, 0x0893bb4d, 0xd3484819, 0xcaf7563a, 0xa08e8f0d, 0x4ca764ed,
3947 0x8482d136, 0x4592266d, 0x610b09c8, 0xd60a673f, 0xeab126e7, 0xee7b0de2,
3948 0xd7e7fe82, 0xfd12499a, 0xec8d44fe, 0x4d92fa86, 0xb4488052, 0xad21eebd,
3949 0x5e7fed0b, 0x39260a40, 0x63d37d69, 0x9085339a, 0x6cbfbbe5, 0x5c057182,
3950 0xe2167c67, 0xbfbe00d4, 0x23f63565, 0xadb03ca4, 0xa7ed0bb4, 0x99725abc,
3951 0xebe538e8, 0x038df0a4, 0x9014b9e1, 0x370bbf69, 0x0fb3895b, 0xc10ae183,
3952 0x4b1e7171, 0x6971d3d6, 0xd2a9447f, 0xe3a252ca, 0xf19cfc09, 0x4471c5ad,
3953 0x744bf17d, 0xc55dfa1c, 0xa60b92ab, 0x9e226158, 0xa9bf1d20, 0xf3da692e,
3954 0x32df9836, 0xec4a77ad, 0x0ebe663c, 0x6c0f28f3, 0x006d4ad0, 0x6e6d06d7,
3955 0x0b7f68bf, 0x0f56ff37, 0xd99edad7, 0x6376989e, 0x5147c679, 0x2f5a3bda,
3956 0xb41dc427, 0x6d01fc01, 0xf3e8ff62, 0x908d295a, 0x4cbfd04e, 0xff68969c,
3957 0xb9f1f884, 0xc0615c4c, 0xb8a5093b, 0xead6e962, 0x496dd3d0, 0x0db6ff1a,
3958 0xe9c97e78, 0x81cf98f0, 0x1cbe13e5, 0x73e57f2c, 0xf1bf9c22, 0x29f2c1f5,
3959 0xff9f0b9f, 0xcb1437d6, 0x96373ef5, 0x62c6facf, 0x8657c1b9, 0x9bef3def,
3960 0x9f26e586, 0xe8bf9f07, 0x4be58f9b, 0xfe7c4abe, 0x2c7eef8a, 0xf8fcf8b7,
3961 0x356fab7c, 0x557cdb96, 0xf4e76e58, 0xe00be1da, 0x9b7d3b7b, 0x05f3acb1,
3962 0xbe1bf9f1, 0x017f2c5a, 0xaa65a478, 0xa14cb1db, 0x4d1d4a74, 0x484d941c,
3963 0x32d95946, 0xa633d695, 0xa7b67ab0, 0xf146996a, 0xd69b3d94, 0x2b731d29,
3964 0x6999961b, 0xd652ee7b, 0x58efddde, 0xddeda16e, 0x9ef6b257, 0x93cb6555,
3965 0x27cf7b68, 0x8135fb59, 0xb4c9e5aa, 0xac8d9afd, 0x61b06fbd, 0xf7b695b9,
3966 0xd7ed61ad, 0x6c2b1d87, 0x3efd7eb4, 0x286c2f56, 0xeb42915b, 0x7d598785,
3967 0x0ad56348, 0xc87efd3b, 0x88fdf671, 0x4ceca096, 0x55db1fc0, 0xd2843dd7,
3968 0x52fed7ee, 0xd68c32b7, 0xc47dd735, 0xff66c845, 0x33a56ead, 0x865a87c5,
3969 0xd3fcbbed, 0xc32b5d58, 0x33fcb7f6, 0x6a9dfdf1, 0xec7fb625, 0x9df6c72f,
3970 0xb7b6255a, 0xf6c3eff8, 0xdb0ab53a, 0x601ecb4d, 0xdb0aad75, 0x883d9733,
3971 0x52a1bfef, 0xd2138760, 0x6ea3d97b, 0x966f853f, 0x7d02a9e4, 0x9caa6cd2,
3972 0x28b7404f, 0xaf901ce1, 0x0d322487, 0xc4a7e5e4, 0xa1e6fa89, 0xc83734ab,
3973 0x8343f6e1, 0xc539079f, 0xe7d4265f, 0x0f26b0be, 0xfb0a79fb, 0x3d3f68d1,
3974 0xf0a7efdb, 0x7ebaa19d, 0x2f99df0a, 0xf80e79fa, 0x63b939be, 0x677f6cfd,
3975 0x779e1eb8, 0xaf3f45ca, 0x8ef63f60, 0xaff0abcd, 0xfcf0f523, 0xa7e89175,
3976 0xde95e706, 0xbc767831, 0x1793f14f, 0xfbc767ed, 0xf6123f14, 0x64fd8f53,
3977 0x419e0c75, 0xf5d50c1f, 0xf983e833, 0xd8039fa2, 0xf58e974f, 0xe183e3b3,
3978 0x283e787a, 0x8dbcfd17, 0xd8eb74fd, 0x387d06bc, 0x87cf0f52, 0x473f448b,
3979 0x1d1e9fb0, 0x51e767eb, 0x1e767e3d, 0x28e7e08d, 0x63bbd3f6, 0x4c721af3,
3980 0xc7219f8f, 0x8339f822, 0x63aebf74, 0xa63cecfd, 0x63cecfc7, 0x479cfc11,
3981 0x363bf278, 0xe89f21af, 0x93e433f1, 0x632e7e08, 0x831d053f, 0x1eb4eea7,
3982 0x23a7753f, 0x982551f8, 0xc18ee0d7, 0x1e8cec33, 0x44cec33f, 0x009763f0,
3983 0xeb1de19e, 0x1e8ceea7, 0x2267753f, 0x7846c9f8, 0x5e6c7546, 0xe3d33ec3,
3984 0x1167d867, 0x9e1138fc, 0x08cdcae2, 0xf4fda10f, 0x379fbb6f, 0xcff5e9ce,
3985 0xfe98e71b, 0x8fc47819, 0x21cd57fa, 0x6467002e, 0xa25f994b, 0xd6932575,
3986 0x89ba509d, 0x055fda87, 0xf83f70ec, 0xd32fd1b8, 0xb4ea94f6, 0x58ce3582,
3987 0x02ec5c7b, 0x4d03ec78, 0x18ef7b3a, 0xa7abac99, 0xd9d74e8f, 0x5df1cceb,
3988 0x29acf574, 0x9cf5743d, 0x7dd3ae3b, 0x817665df, 0xd175deae, 0xdbbd5d70,
3989 0xf7dd62d2, 0xd66e07ce, 0x3958f7b5, 0xf5ef5749, 0xf5750fc8, 0xd2ce4fde,
3990 0x2bacfbd5, 0xdd77f5d7, 0x7aba25c6, 0xea9feabf, 0xcb35f9ea, 0x68577575,
3991 0xb05eae8d, 0xff5d71ef, 0x5a7adf03, 0xf87c1f57, 0xe87d5d39, 0xbeeb2f47,
3992 0x35fc7e1f, 0xd9e47d5d, 0xc7ff065d, 0x97d138e6, 0x77f065d7, 0x9a07e8ad,
3993 0xcfe869bb, 0x60b37516, 0x6cddc7fd, 0x28f1ff58, 0x4a0e35cf, 0x07c39fd7,
3994 0x58fdeed4, 0x48ef5cf3, 0x25297f60, 0x4a07244d, 0x8d0c898f, 0x52ad5f6f,
3995 0x527ca3be, 0xef72fddc, 0x9af4b4a3, 0xd1a77a5a, 0xa2a6eff2, 0x3f17c0a5,
3996 0x97e84c95, 0x09526559, 0x1335647c, 0x57d5cbe4, 0x1fde7e0f, 0xe70fdfc3,
3997 0xfd14be31, 0xe656ac3e, 0xeffe1d80, 0x83f3bf65, 0x4f287e1d, 0x93ec3b43,
3998 0xf7f6177e, 0xfde7dfa2, 0x49fc0738, 0xd4fd468b, 0x3a35f1d8, 0x7f1c3f7e,
3999 0xa6bf8c25, 0xbd2df18d, 0x4fc6ea87, 0x375f31ea, 0xc746927e, 0xe8f21077,
4000 0xf1f3dfb2, 0x50bafe29, 0x3dfa50bf, 0x71e96f8e, 0x5abf8e3f, 0xe375f323,
4001 0x7fc64727, 0x69fde412, 0x82507f18, 0xae1ef7f9, 0x728f7f9f, 0x3635fcfd,
4002 0xbd9667ff, 0xc64fc7cd, 0xbd2b3ff9, 0xe3dfe6cd, 0x66fe6ca7, 0xf8ec6fda,
4003 0x37fe08f6, 0xb72ff8c2, 0x9ae5be31, 0xf7f9fa91, 0xbf9fa45c, 0xeaff8d99,
4004 0xf8f8f7b2, 0xab7f1c36, 0x7f9b1ef4, 0x7c7007cf, 0xe5d2b9b3, 0xeee64da0,
4005 0xd00195c9, 0x263dd413, 0x746020d9, 0x2820219c, 0xefd084e9, 0x903d4817,
4006 0xa64e3f0e, 0xffdf477c, 0x1bf29922, 0x6fdcf7f8, 0x12558127, 0x1dd74c19,
4007 0x5767a79c, 0x417ed4cf, 0xcb5d993f, 0xae8433d6, 0xf0a6ae77, 0xff9ed535,
4008 0xef0a43e2, 0x50038dec, 0x274e514f, 0x3e1cddf0, 0xf0ccaf15, 0xb7594841,
4009 0x12bf5489, 0xa4dbaca5, 0x06e4d8fe, 0x411e7fbf, 0x78f8e318, 0xa27a954e,
4010 0xe6fe4631, 0x17d7d5ad, 0x0175f404, 0x09301177, 0xa4c5fd2d, 0xf71d254f,
4011 0x10275d18, 0x447f97ea, 0x594270fd, 0xdc9513f6, 0xf2f1465d, 0x404f5d31,
4012 0x27ae91bd, 0x4cae9da0, 0x14c72e91, 0xb63bf382, 0x7a001ada, 0x0193f17c,
4013 0xbb87d81a, 0x1bf2a7ef, 0x727edf2b, 0x5fc28738, 0xd339e7c6, 0x076fa19f,
4014 0x4c3c53bc, 0x0b2bf3e4, 0x974f1e2d, 0xd59ee4c4, 0x459954b9, 0xf24a6bdf,
4015 0x54ffd0a8, 0xe9b356e2, 0x9d2e7778, 0x5f107aa8, 0xca135cee, 0x5135c939,
4016 0x56e89f39, 0xf4c6358f, 0x8066a93f, 0x93227b4a, 0xdf9feac7, 0x37afa656,
4017 0x44d56ea9, 0x5134d3e9, 0xdda81b22, 0xdf4d3a99, 0x2339c62e, 0xc5fce3a5,
4018 0x6e746578, 0x9e61d39d, 0xeffa63f4, 0x3cd83a1f, 0x34bc3ae8, 0x3f73d617,
4019 0x689b5c90, 0x57bc2a7d, 0xa83d7400, 0xb769f3c1, 0x90d6b9a4, 0x92897878,
4020 0xe11cfd83, 0xca23bceb, 0xcd0c5fa6, 0x83ff878b, 0x29b756dd, 0x461e7e3f,
4021 0xa093a7b8, 0xba76f60a, 0xc67cff47, 0x18fce37c, 0x74e09c5f, 0x407c063e,
4022 0x07c093cb, 0x39c7cf14, 0x2bf5441f, 0xc01383e3, 0x4eb09907, 0xa7307c66,
4023 0x6ffd312a, 0x479ff4e7, 0x29676afc, 0x9ca9f74a, 0xba73b7ee, 0xe7ab5bcf,
4024 0x3cf9b88f, 0x1cc1e1b9, 0x3cf98267, 0xa62547b2, 0x657979f8, 0x2ff91f06,
4025 0x8e89b029, 0xbea5677b, 0xfd0376fd, 0x777e9c3c, 0x7165e846, 0xbf3e5197,
4026 0x011927eb, 0x7c7133d0, 0x31f5e9c1, 0xb5b4d7a7, 0x4cefed8f, 0xe46be1e2,
4027 0xf6b13af4, 0xfb44d579, 0x112f9c6b, 0xf08c6ff0, 0x9bbbe11a, 0xdfa03438,
4028 0x9febf7dd, 0xa627f4cf, 0x28b6b79f, 0xf3cc78e3, 0x1971c1c5, 0x68e463c7,
4029 0xba89e6e1, 0x74c082fa, 0xd6f3fbdd, 0xcfb5d4ce, 0x6ba05aa9, 0xbdf567bf,
4030 0xff4cfaba, 0xdfef744f, 0x5d32ff7d, 0x0f959dfb, 0xcc67daeb, 0x9f574c7f,
4031 0xf74a79ee, 0x1b69d4fe, 0x95b7ed74, 0x9f6ba4bd, 0xae9b763c, 0xa75dd13e,
4032 0xbdda5f7b, 0x9fc43ba0, 0xd9e79abc, 0xbd9b886c, 0x49cf266f, 0xe84c7af1,
4033 0x273ee3bb, 0xebe13f3e, 0x9f29e583, 0xf19f9f0b, 0x1972c50d, 0x176a71e8,
4034 0xf4ac754c, 0x3bb33e3e, 0x07217fe8, 0x6eaea89f, 0x7a8d3fa0, 0xc4e7a8cf,
4035 0x46bd46fb, 0xa7e0b97f, 0x59cf15b4, 0xb0329124, 0xf312cd0b, 0x43f3c457,
4036 0xb2123edc, 0x1a45cb1c, 0xaf45d393, 0x39062e75, 0x7b85a45a, 0xeedada57,
4037 0x9c250497, 0x9eaa9ccf, 0xade7383a, 0xef806bed, 0x05abe439, 0xf3dd4281,
4038 0xe8479b85, 0x47bb3bbe, 0x402af846, 0xff8187b6, 0x04deb65d, 0xb7bc31f6,
4039 0x00fee4db, 0x1319fbaf, 0x09db5bc0, 0xdf59eaed, 0x0ae38cd8, 0xcb0cb9e0,
4040 0x5869be53, 0xb079f09e, 0x8f9bee3c, 0x255f31e5, 0xfbbe8d96, 0xe7d8fcb1,
4041 0xdf23f2c7, 0xf03f2c6a, 0xc4796155, 0x77cb16b7, 0x0f2c017d, 0xf96336fb,
4042 0x65882f8e, 0xcb16af83, 0x4b1b9f26, 0xfc312f21, 0x0c73bdd2, 0x277d08bf,
4043 0xce29e1f4, 0x5f80672f, 0x73c5f112, 0xa938be7a, 0x185f2256, 0x0e91a1f5,
4044 0x6df77d46, 0xf4dd21f9, 0x9443f0fd, 0x7a06b9de, 0xde8f6cf7, 0x397d221f,
4045 0x0e4dd3bd, 0xf7a70f06, 0x45780623, 0x041281a9, 0x7e6665bd, 0x595b711e,
4046 0xabc453dc, 0x7b8b3249, 0x337578f2, 0xbc0377fd, 0x10fb04a7, 0xbf6b5fda,
4047 0xe21bdbff, 0xcc47adcc, 0x3db5e484, 0xdafd233f, 0x9bf103c4, 0xc9ff0ebe,
4048 0x14af0cc9, 0xda84b1aa, 0xbed73587, 0xeac59aee, 0x423b010a, 0xb8d8ae82,
4049 0xc05fa46f, 0x78fb7665, 0x7f31374d, 0x6657bad3, 0x776f08f8, 0xf2894e4d,
4050 0xd2dcd7ab, 0x95f833bb, 0xd8099a1f, 0xe9b01233, 0xf5a7e5f1, 0xb57c51c1,
4051 0xf4f68f35, 0xfc2fffde, 0xda8fa7b4, 0xa48743d3, 0x735fc7af, 0x24f75d31,
4052 0x008e2f58, 0x6df41c3e, 0x1ba1b0f8, 0xf81061f0, 0x5adff69d, 0xe92a4d73,
4053 0x66e7ed17, 0x13af9393, 0xde4e9ebe, 0xd37e0854, 0x1334537e, 0xcbae9eb9,
4054 0xf24dcf65, 0x5dcff020, 0x6f4a7e8d, 0x6bab6eff, 0x49d61385, 0x7612fe67,
4055 0x75fa17c2, 0xe7c1eb73, 0x59aeb0ed, 0x1c726392, 0x3e9b6c2f, 0x0e79838b,
4056 0x547fac5b, 0x56b7afab, 0xdc596349, 0xa53a99c4, 0x8769e83f, 0xd02f78e3,
4057 0x8a58399b, 0x68e4967e, 0xf019e38e, 0x79c9805e, 0x81ea1a75, 0xbe0b3e33,
4058 0xd1c37df7, 0x38513f56, 0xf427c86a, 0x2b89107b, 0xbf7edb3d, 0x2e56be4d,
4059 0x228f1068, 0x580bf521, 0xffd1252f, 0x7e80f4af, 0x7e8bac15, 0x6fd941bd,
4060 0x579e1ebe, 0xdfa3c6eb, 0x1b1ec539, 0xfcb6d77c, 0xe084e428, 0x3f374a5f,
4061 0x2fb8a7f8, 0xfbd0e494, 0xbaba696d, 0x43b3b6b7, 0x3fc1c7e7, 0x2d1cd1c0,
4062 0x8b47c029, 0x2b355b38, 0x8512d5b6, 0x322c066f, 0xf6259f81, 0xa34b62de,
4063 0x968fa1e6, 0x7f4148ec, 0x7c63c978, 0x1a4fcd9f, 0x4359fbe0, 0x29970779,
4064 0x51fd3154, 0xb44c470b, 0x89af0f7e, 0x3559aefd, 0xff5fd10b, 0xdd71f894,
4065 0x1aae5a77, 0x796a7e0c, 0xa6e68370, 0x989cfb74, 0xffbe82c6, 0x2f63bc9c,
4066 0x57b7918c, 0x7be70d64, 0xffbd6acf, 0xbab1d74a, 0xeac75d3a, 0xa4c973ea,
4067 0x9a17d82c, 0x974aa4fb, 0xd5aeb8d4, 0x7656ffb5, 0x91e77ce0, 0x876055ca,
4068 0xbc29a93f, 0x71e0047d, 0xb0c1fae7, 0x9b459c4e, 0x29fea973, 0x03487cdf,
4069 0xe3a6f939, 0x0bef802f, 0xf315c7e2, 0xe407db8a, 0x59bc5878, 0xd8120772,
4070 0xf76e5abd, 0x3bfa5e84, 0x1eb31fc0, 0x23e7cd3f, 0x3f9adfea, 0x65c32932,
4071 0x4339e945, 0xc1921cf6, 0xa49f008e, 0x5be2f946, 0xd7139ff7, 0xd7bfdfff,
4072 0x1d12bbfe, 0x4ffed37f, 0xdefc5e83, 0x0715effa, 0xf044c5ff, 0xb22c3a0b,
4073 0x17c01c34, 0xbe096e1d, 0x14dcb853, 0x7c60714d, 0x725ab9aa, 0xc4fbe999,
4074 0x2c8e9c4d, 0x3d601fa6, 0x6a5afcd9, 0xe1bd413e, 0x1f3a6e20, 0x552e7f2b,
4075 0xd123d9ef, 0x3b4ae175, 0xfe51a771, 0x9953e954, 0x692ad1ca, 0xe5a24580,
4076 0x7f739ae2, 0x9bf68379, 0x88099214, 0xa1853374, 0xdd97f701, 0xac776069,
4077 0x03b411e4, 0x257ec7b0, 0xd1a70a23, 0x0578103e, 0x8d8397ec, 0x61b6463b,
4078 0x9d75a6fc, 0x9955718c, 0x919bf75c, 0x0f782f54, 0xeda2f952, 0xb405f0ad,
4079 0x5d7095af, 0x04b07adf, 0x24eaf3eb, 0x6beb4192, 0x60f9ec93, 0x26dcd2af,
4080 0x63373c5d, 0x4e7e3eac, 0x5806eefc, 0xf3e6cfff, 0x1c00c405, 0x53bd790b,
4081 0x7de1ba59, 0x5c4c5ffa, 0xee67b66c, 0x93f14278, 0x771f4d3d, 0x723f285f,
4082 0xed3ae200, 0x06ed6dca, 0x9463900d, 0xf59b85db, 0x21b78175, 0x09e64a4a,
4083 0x6236c9b0, 0xadb5bc03, 0x67c1dbc7, 0x8cdfef63, 0x7c71d81c, 0xce64f11a,
4084 0xc935e3d1, 0xb5abc7a9, 0x066f018f, 0xf4b8a6bc, 0x3a66a2f8, 0xa9af0890,
4085 0xfae87b43, 0x7af1bef9, 0x6fb3e017, 0x57f49f14, 0xa262c966, 0x56767007,
4086 0x46ffc8c2, 0x85b5c979, 0x55f7f825, 0xf8658199, 0xf5052b95, 0x5f870e40,
4087 0xb3becd9a, 0x60c8bc82, 0x2f285d55, 0x3b046910, 0x391f256e, 0xf2268e80,
4088 0xb7d2b909, 0x37de3a6d, 0x59d1df71, 0xc075abf4, 0x1f23d7cf, 0xe9fc5d20,
4089 0x0f22b024, 0x00e5d1e4, 0x59f416bb, 0xbae9b39c, 0x711f55f1, 0xcdfea6ce,
4090 0x96073e6b, 0xf7b0168f, 0x0091fb9b, 0xe1831bac, 0x884e590b, 0xeba1cf67,
4091 0x1fffaa34, 0x80265ad5, 0x9517fc3f, 0x55eecfad, 0xab772c35, 0x47ffae26,
4092 0x79f201ff, 0x00ffa99a, 0xd0e6a5f1, 0x50d5cb26, 0xbf3195af, 0x75569bc0,
4093 0x14df8c2d, 0xb35c1952, 0xf64f182d, 0xc768abd6, 0xc48f669b, 0x9f311a7c,
4094 0x163c90a6, 0xa1cdd9e2, 0xc4f7ec4f, 0xdaa69dd8, 0xbb05ae27, 0xb12994f7,
4095 0x628cfbff, 0xc87e6efa, 0xfa3d38ba, 0xf509d28c, 0xe83da3e7, 0xb6262a3c,
4096 0x9becbf22, 0x77ce337b, 0x9a724847, 0xf2a5dc29, 0x0fe83f1d, 0x537f86fb,
4097 0xee24de98, 0x58b333f1, 0x5f563ce8, 0xabd4888c, 0x7ec32afe, 0xc3c45d25,
4098 0xcac0e2be, 0x8c87e8b9, 0x0292490e, 0xc108ebfa, 0x0fc8467e, 0x7f32c094,
4099 0xe3a28350, 0x0921c1c7, 0x91b836f1, 0x90d37e60, 0x61f6fa23, 0xae218a8d,
4100 0x9f819016, 0x3fd29c46, 0x6d7c13af, 0xd7c05927, 0x25965e4f, 0x5b9a4ff0,
4101 0x1d396b88, 0x977679bf, 0xf9a78022, 0xd046ec02, 0x363cb2f2, 0x8ff7fad1,
4102 0x9e87f30a, 0xc6fed8d2, 0x816d7353, 0x6fbe9465, 0xb8c72dce, 0xf13f17c4,
4103 0xbfb44f74, 0x5287a315, 0xdc83684d, 0x75cfb0a9, 0x1295c4df, 0xd552031a,
4104 0xfe252cb9, 0x82bfc17d, 0x771f059f, 0x09ec9b9e, 0xb2671824, 0xe294fcca,
4105 0x8d247db9, 0x5bb4d7c2, 0x4da57422, 0x747b969a, 0xe9630ef1, 0x0173cb27,
4106 0x79ed6f1e, 0x2594ec0d, 0xfa0fd894, 0x3ca3b14c, 0x2ff72d34, 0x1fb5bc83,
4107 0x3bf46153, 0x27dfaebf, 0x48723e31, 0x2cefb271, 0x9e813355, 0xe42c732d,
4108 0xd6379639, 0xf00a5279, 0x55b8c97b, 0xcba7de14, 0x9f37684c, 0xbf085d52,
4109 0x7961317f, 0xa2ff7c71, 0x61b204eb, 0x5cfc8c4d, 0x95248a54, 0x0ea92bf6,
4110 0xe3c33fec, 0xd77e0092, 0x8769ffbf, 0x4be690fd, 0x1763a466, 0xdf10f71e,
4111 0xfad95575, 0xfeea8371, 0xd0f58152, 0x0b944cfc, 0x9ceec797, 0xf5f2ed4d,
4112 0x09ef14b5, 0xffe146fc, 0x98e87ba5, 0x9b749e14, 0xb892f909, 0xd5074edd,
4113 0x7e225e77, 0x8883947e, 0xa225845c, 0x51ea8e0c, 0x53852429, 0x681c3ea8,
4114 0x5a6585b1, 0xf3a7cfa6, 0x6231fd86, 0x2835fd61, 0x40fb2367, 0x7ca1aeb8,
4115 0x4d821839, 0xaef587f4, 0xafd0bfd8, 0x84af2f42, 0x67ed36b8, 0x604a63e5,
4116 0x9d67ed05, 0x357498d2, 0xcedcf32d, 0xba412062, 0x5003f4e2, 0x2e27cd57,
4117 0xf6b1210a, 0xf1169f5c, 0x0ed0a847, 0x78c64af8, 0xd38e9180, 0xf4f2f822,
4118 0xf3fce952, 0x09bcb60f, 0x892b8b6e, 0x6fdae78d, 0xca593b41, 0x4fb0eaed,
4119 0x17d0014d, 0xee237c24, 0x112d799b, 0x17d3a0fd, 0xc4686ec3, 0xef61ae7c,
4120 0x54a87833, 0x41fde1b9, 0x7d723c11, 0xa136fdc2, 0x8284863f, 0x2eaeb085,
4121 0xb5ee1508, 0x3e0bf1d1, 0xa71b7262, 0x15d20e3f, 0xaf6f8f5b, 0x307c8c37,
4122 0x90e54c20, 0x1d1fa5d3, 0x23a0f0bf, 0x52f68752, 0x7019ea95, 0xc99eb916,
4123 0x1b30389c, 0x7f38bdf7, 0xe42af119, 0x05e728d9, 0x9af6bbf7, 0x0c885c19,
4124 0x8a4438e3, 0x09ece1c2, 0x392de87a, 0x1157f415, 0xeb8503c5, 0x696f2e73,
4125 0x60e30217, 0x6e864ffe, 0x65df224a, 0x7e99b25d, 0xc62f631d, 0x20d99ec9,
4126 0xd85ed477, 0x7b150f01, 0x8f4c682e, 0x11de9185, 0x0172a7be, 0x10b909df,
4127 0x6fe46efc, 0xe82b0f21, 0x189ea657, 0x4760249f, 0xce082965, 0xeb61d52e,
4128 0xe157801c, 0x1a7f1337, 0x3a9663c6, 0x78eb38d8, 0x24d2ca5e, 0xd7fa7677,
4129 0x25ef5fe8, 0xc4c40913, 0x8b4abc39, 0x7bd17a06, 0x8c812349, 0x8d9f80ef,
4130 0xad59f871, 0xcfc78a76, 0xebf3c86c, 0xfe02bff4, 0x87fe1180, 0x5ff8519c,
4131 0x421456b7, 0xe70efe9d, 0xef9bd2c4, 0x15f90a13, 0xb6b43af2, 0x9cb52f72,
4132 0x2719f271, 0x0c80a197, 0x4f978a78, 0xccf41932, 0x23f33088, 0x817a728c,
4133 0xf6f9a3cf, 0xefc0de96, 0x0ea7b2f9, 0xf7def7e0, 0x2fe83745, 0xc63249df,
4134 0x6bf32053, 0x2bd81765, 0xb3a190d2, 0xda76f107, 0xf5c4e8cf, 0x9f9f057a,
4135 0xd4f94b54, 0x9e05fb0e, 0x0affd07d, 0x41ff5b07, 0xc7f41e40, 0x7bf3c545,
4136 0x852b0b90, 0xa7e2192d, 0x1879c27d, 0x45c832a7, 0x3560725b, 0xce9079f0,
4137 0x9f8cec17, 0xa5ab99da, 0x5879e1b6, 0x52f0634d, 0xa23f07e9, 0x06c260eb,
4138 0x8fb820ab, 0xe59f35da, 0x602d74af, 0x729fd6f9, 0x50c27e7d, 0x3eca545e,
4139 0x0aa97986, 0xbe0b9bf1, 0x2a00dc3d, 0xaa4e5fc4, 0x1f008fee, 0x9c6eb196,
4140 0xb883ae47, 0x72276a24, 0xa2e4a095, 0x722fa470, 0x9fc6bda2, 0xbfb49fb0,
4141 0x22cef1dc, 0xd52e77a0, 0xcaf71089, 0x91247f05, 0xc22aa85c, 0x3ef9adfd,
4142 0x5f07e710, 0x407f7ce1, 0x18cdf3a3, 0xbcb1a2df, 0xd4ce2a85, 0xdbf0092e,
4143 0x4e3b7294, 0xc4a2e9b6, 0x8634fcfc, 0x08bae367, 0x52f30608, 0x8d41fd78,
4144 0xb8e94928, 0xbec3f16e, 0xc164dfb2, 0xb8958b75, 0xbae7a082, 0xbe1e2c68,
4145 0x86ad724a, 0x16952ffa, 0x78f9e40b, 0xfefd6cad, 0x2e49c8e8, 0xbf62be85,
4146 0xd61f35a1, 0x3bcf949e, 0xa6fdf469, 0x57bdad91, 0xba5a0ce2, 0xcb737e31,
4147 0x27c12f30, 0xb56e8215, 0x496e8eaa, 0xa1888f10, 0xad148adb, 0x4dc5f80f,
4148 0xd60bb252, 0x240b4d29, 0xe164a706, 0xff9053f3, 0x1e127122, 0xf2d42857,
4149 0x6f423f10, 0x86acf9d3, 0xfb0dc052, 0xf92fd0fa, 0x89b0359d, 0x8f1bfabe,
4150 0x81c433a5, 0xed8e67b3, 0xaf67710c, 0x491ba5bd, 0xf3a60710, 0xcbf3001b,
4151 0x40d32b56, 0x79df65cf, 0x30f40edc, 0xd7f62dc2, 0x4bfb07f0, 0x586c656f,
4152 0x7125fe83, 0xe7cf7ab3, 0x05094eb0, 0x60e39978, 0x2a49cff0, 0xb7d58acb,
4153 0x132cfa4f, 0xef5a2515, 0xec4bc914, 0xffe7cba3, 0x89daefb5, 0xbd7be9a3,
4154 0x59372635, 0x9fe3f5a4, 0xd6e671d1, 0x3f105d58, 0x8cf65478, 0x773fb803,
4155 0x70975f3b, 0x01295d1d, 0x959f8b1c, 0xf079d3c8, 0x43fb611d, 0x1f943f1c,
4156 0xd98ecf3a, 0x2ef3a037, 0xd3c506d3, 0xb52559b5, 0x7212e710, 0x2ca7c999,
4157 0x4ba082f4, 0xea9bd026, 0xe5465205, 0x8dce2634, 0xdc6166af, 0xe8527f0a,
4158 0xbf02fff7, 0x31437ed1, 0x1ba09dca, 0x48f4c3e9, 0x4c75c812, 0xfeb9aabc,
4159 0x14fcabbd, 0x9fffbf8e, 0xb68429f3, 0x496943ff, 0xf53e3901, 0xdc535fc0,
4160 0x00f60f90, 0x977acf5b, 0xeebce2a4, 0x8ff77ee2, 0xb46a9e38, 0xd79872b2,
4161 0x637fbedd, 0x6fa2379c, 0x8efb67ef, 0x8ffaa80b, 0x4b6a2fdd, 0x1479c32f,
4162 0xfd7793a2, 0x8562ecbe, 0x7e30eb9d, 0xeb6349bf, 0x1bd505e6, 0xc0275cb4,
4163 0x806ff9e3, 0x5f5f14e7, 0xf161aa9c, 0xacdf011e, 0xf81a01ea, 0x9908ffdc,
4164 0x1fed9849, 0xb95f4ca9, 0xb7c5126d, 0x08d1e387, 0x179e01f7, 0x3257e739,
4165 0xe933c1fa, 0xb953f758, 0x601684f7, 0xff08c71c, 0x52bcba9c, 0xf3987fc8,
4166 0x29eb84b0, 0xaa01ff78, 0x3ff73d3f, 0x68e80e74, 0x9f319f9c, 0x171f18c4,
4167 0x43c8b37e, 0x983c4d9b, 0x27171297, 0xfb1cfd0a, 0x9e8bc637, 0x797af8d5,
4168 0xfb021930, 0xbef96725, 0x621b9c3a, 0xcb04ebfb, 0x14925072, 0x1e968b9f,
4169 0xb926052a, 0xc61b72a3, 0x33f8c5eb, 0xf833f8f8, 0xaae15438, 0xe633c7c0,
4170 0xf36217ab, 0xdc68b6dc, 0xc7421e6f, 0x89e3a393, 0x39731671, 0x7a0be314,
4171 0xe72abe0a, 0x7f515d74, 0xd3235bb2, 0x0c498703, 0x9ff88c7d, 0xca2b3bf7,
4172 0xa1cf0447, 0xfd039c5f, 0x51736738, 0xec271769, 0xc28e545f, 0xcfe269fc,
4173 0xe16af961, 0x1bb7581c, 0x36a4def1, 0xd8257376, 0xfee2689f, 0xb9717b5c,
4174 0x03c89a1d, 0x94f2c2a8, 0x67e07552, 0x191b87c0, 0xb9de2c1f, 0xb79075e5,
4175 0xb2bfadf2, 0x569dbc83, 0xbc60b2aa, 0xb41e9b45, 0x29c57ec3, 0xbd076fc5,
4176 0xe4c03a78, 0x8aefc8ce, 0x305bec59, 0xe0f6157e, 0x9f3fcbcc, 0xc5f9fc00,
4177 0x7a01d526, 0x1cd9bbde, 0x547c5336, 0xd0fc30d4, 0x7f5651fa, 0xade2f108,
4178 0xfe5dc3d5, 0x9cb2afe2, 0xe7969f6c, 0x9d7185f3, 0xd3f1b15f, 0x2f0f9052,
4179 0x1d7dc169, 0xfe3077e3, 0x97dc74a5, 0xc6a5a99b, 0x11be0bb7, 0x8d6f05eb,
4180 0x3c469be0, 0x7f7c665f, 0x172fd73e, 0xfe72bf05, 0x0120f811, 0x9de457a6,
4181 0xd28ff3eb, 0x7f8dd9fa, 0x62fd4bb2, 0xbfcb09f5, 0xf3de0d68, 0xdb672eec,
4182 0xe71360fe, 0x0177e8c3, 0xcb59cefc, 0xac4230f3, 0xed86a45c, 0xb4591710,
4183 0xecf5c541, 0xbfcf2da2, 0xbdd834f0, 0xabaecdf7, 0xb70bff69, 0x38777fec,
4184 0xa6dc2fad, 0xd3678e66, 0x763149b0, 0x5a7c0bda, 0xf943a510, 0xb39afdf6,
4185 0x40fe7b3f, 0x0b1e947a, 0x48d1edb7, 0x947c78ff, 0x8c68f704, 0x09740dff,
4186 0x7d852d1e, 0xbfe7796e, 0xe9fba035, 0xbc8112dd, 0x6e7c38cc, 0xd2fb8fd8,
4187 0x23a42780, 0x6e8453a7, 0x94bdf786, 0x39e7682e, 0xefed8c9d, 0x3fe40e69,
4188 0x5dce0fe8, 0x757e7e51, 0xfccfc517, 0x982ecc0f, 0xef57fcff, 0x4e3cc3b3,
4189 0xaf8c952a, 0x05983fd7, 0xeabe6476, 0xc96072cf, 0xe67fcf9e, 0xf36fc847,
4190 0x8b28fd0e, 0x99d2fd30, 0x9dfcd1c5, 0xd6737e61, 0x9bf386dd, 0x77c83c4b,
4191 0x65cbd7f3, 0xa8babf10, 0x12dbb190, 0xb94fc5c8, 0xce7c9c5c, 0x27f8fb8c,
4192 0xb8531ec1, 0xccc8effc, 0xa2f721cf, 0x9f11fd7d, 0x58fcb50b, 0x18e3c8bf,
4193 0x1e22cd13, 0x2c72b54c, 0xa87c6ebf, 0xe673e801, 0xc436772a, 0xf144bd01,
4194 0x57487c73, 0xa1f2bf68, 0x3f5cd931, 0x7f189539, 0xc39e04b7, 0x3baa0dfb,
4195 0x1df75f29, 0x1d1792b9, 0x9f1f297f, 0xfb0c9dc2, 0x12b327c6, 0x305f87c7,
4196 0xd611624b, 0xa303f3a0, 0x7de4cdf2, 0xbe4cc3e3, 0x2607bc85, 0x0bf6858e,
4197 0xc0fc9987, 0x53c7e077, 0xd8d9c2b8, 0x848a67be, 0xc3da80fa, 0x51bd7244,
4198 0x6fad72e5, 0xe1427c17, 0x897fc056, 0xfb610bf0, 0x7e7927bc, 0xe927dcfb,
4199 0xc1763177, 0xe3d9e30b, 0x3b7213fb, 0x6617f84f, 0x7593fcbd, 0x5bc6129d,
4200 0x22c47e8c, 0xd3c2f035, 0x3e54af20, 0xda2edf41, 0xbcc196a2, 0xfbdeab3f,
4201 0x9ca90fee, 0x7214167c, 0x469fd7aa, 0xdaff9d39, 0xa34fe47e, 0xdc167e9c,
4202 0x4e50959f, 0x73c7edb7, 0xfa72f1b7, 0x053fab3f, 0xf01bd6fe, 0x5b61f427,
4203 0xc3ea3478, 0x4fc410e1, 0xb7090fa0, 0x13fe46c3, 0xadf8277c, 0xddc595fc,
4204 0xf844ef41, 0x845df052, 0xc5df052f, 0xf0ead1e5, 0x083f3717, 0x589f01a2,
4205 0x75828ed6, 0xf6c5c586, 0xcb39ae13, 0x819693e2, 0x67d6fd6c, 0x43f582ad,
4206 0xb020c726, 0xec4613fb, 0xa427ecfc, 0xbef9fe6d, 0x963e9dcb, 0x65075fa3,
4207 0x895f042f, 0x1090e3a5, 0x16fbd383, 0x7d40f409, 0xf76396e0, 0x930b640b,
4208 0xbd1f9df7, 0x2c780856, 0xca97ee6a, 0xae1babf8, 0xb5fc445b, 0x054cefd5,
4209 0xea1ada7d, 0xad4f7989, 0x4494e507, 0xe25fa5e7, 0xfb857df4, 0x491bcd5b,
4210 0xadf94c95, 0xdfa0b499, 0xc168dfe0, 0xbe38b67c, 0xe67f3330, 0xe803e2bb,
4211 0x2978f80f, 0x5134b1a9, 0xf9f09a3c, 0x5ff3784e, 0x0baf1f68, 0xbf81306d,
4212 0x9346dd7e, 0x24be4fce, 0x1480baf8, 0x784f5f00, 0x20652933, 0x2ecaf3ee,
4213 0x0dee5738, 0x093cd39d, 0xf38c95f2, 0xdfc1fe87, 0xe0716fea, 0xc1a86fb8,
4214 0xdbdcf07b, 0xeb0216e7, 0x6aad3a85, 0x3b382261, 0xeb383125, 0x7cba338e,
4215 0x6a29785f, 0x618b85b6, 0x61237a7f, 0x3a38f671, 0xde0eb613, 0xaa7f704c,
4216 0x7ab32435, 0xa347db35, 0x2462fca0, 0xf699777c, 0xd79f231a, 0x057b6ed4,
4217 0x8455e7ce, 0xb6898724, 0x1a8d2857, 0x36b78bf0, 0x363d064d, 0xcbce29c0,
4218 0x894ffa3b, 0x16febfe1, 0x77b9e705, 0x00331bf8, 0x6acfe72f, 0xddd5f604,
4219 0x60ec5afb, 0x0a87ceef, 0x9adadf91, 0x191f76d7, 0xfee9eb05, 0x78a77f00,
4220 0x4eabf63a, 0x9447d5d6, 0x5c00ba78, 0x4b8dcc13, 0xfef0095d, 0xf7d9858a,
4221 0xdb3e4bef, 0xbf2c3b2b, 0x7afc8587, 0x7c41bf70, 0x378700ff, 0x13b37e46,
4222 0x6592efc9, 0xf7986cce, 0xd99efa92, 0x7f25cf80, 0xe2253b50, 0x963e2dab,
4223 0xee15b4df, 0xadf90017, 0x7d7bf2a1, 0x50d6fc8c, 0xff8bcdf9, 0xfbe5ae6e,
4224 0x202ddf95, 0xfbe009bf, 0x90af9f09, 0x51d0fcdf, 0x1afcdf94, 0x4acef9fd,
4225 0x2bf27b4b, 0xf2c29a75, 0x04d65c60, 0x00f01afa, 0x795bb2f9, 0x038c387e,
4226 0x37c2fc72, 0x24bce394, 0x4a7fef06, 0x20ec978e, 0x4f128798, 0x4bc7266f,
4227 0x4b1ca8ea, 0xc7267740, 0xcb09ea4b, 0x6fc83407, 0x65f9389f, 0xd98457df,
4228 0xbcdadef7, 0xc741dcdf, 0x2eab702b, 0x20bf7d0b, 0x6283cf2a, 0xb685f9e5,
4229 0xc760f9e4, 0x970779e4, 0x3da72a67, 0xeae8095c, 0x63f3e90a, 0xb27618de,
4230 0xe5f03b7a, 0x275c659f, 0x0f79e21d, 0x7276197f, 0x3fc5f020, 0xff8a1e00,
4231 0x9a6f9c3d, 0xbfec7e7c, 0xe853f874, 0xabec9547, 0x03ec35fa, 0x12a8de2e,
4232 0x351587d0, 0x328fd147, 0x5f85bfae, 0x0b875c65, 0x7e5ed23d, 0x776e61cc,
4233 0x088dca26, 0xc65b792f, 0xf38c3ffb, 0xc1c5ef17, 0x5deab079, 0xc042afb8,
4234 0x407c5ed9, 0xb83da3cc, 0x15debcc4, 0x148032f2, 0xe286dc42, 0xffc5e511,
4235 0xb5cf1947, 0xad5d1595, 0x23e51fbb, 0xaac2cf8e, 0x870812a2, 0x37e7e44f,
4236 0xf7bdaee7, 0x18af9c00, 0x0059c474, 0xe188f4ee, 0xa7ac0f66, 0x416a4a5e,
4237 0x49741679, 0xb974624d, 0xa379fbc4, 0xf031654b, 0x7256b79b, 0x86f1dd80,
4238 0xc1f785ff, 0x8bea7dec, 0x05a3e052, 0x8cc392f5, 0x834e787c, 0xb5295e75,
4239 0x854fc0bf, 0x7eb873a1, 0x245f505b, 0xea0bf7c3, 0xa3c0bc24, 0x9474fc3d,
4240 0x0edc296e, 0x6df8016f, 0xb30b6700, 0xd13e1c6b, 0x3afc55ee, 0xbe9e4bf8,
4241 0xc1972ab4, 0x571704ed, 0x02283bc0, 0xe7194cef, 0x057841d5, 0x3783dbde,
4242 0xc74f4935, 0x679e47b7, 0xb4a110fb, 0xbe6bad0e, 0x97887ee9, 0x4cfae034,
4243 0x90cc8bec, 0xac0b663d, 0xf3e97b6f, 0xc1690995, 0xa1efebbc, 0xf5d7ff7f,
4244 0x0037d91f, 0xece41dff, 0xcbae2a4f, 0xb338a497, 0x1df1dce1, 0xb75d2af0,
4245 0xfb336d34, 0xff313de1, 0xabb73e13, 0xc3710297, 0xf19e58b1, 0xf57ab995,
4246 0x4f6fb18a, 0xbe43b79d, 0x821f7357, 0x294d2179, 0xda274e2c, 0x0b3249dd,
4247 0x587e73fa, 0xf57c34a4, 0x1b49f821, 0x5c03061b, 0xbcf32e27, 0xb1e6cb92,
4248 0xd3ddd689, 0xe7109db9, 0x3802ef28, 0x2fb2249d, 0xe59f377a, 0x927e705d,
4249 0xad6667ae, 0xf8852b4b, 0xa0bcf1b2, 0x83403827, 0xde31a438, 0x11b88738,
4250 0xd0f9718f, 0xbf1611e4, 0xeedff034, 0x273b0724, 0x706a54aa, 0x3ac4f65e,
4251 0x8829f889, 0x8f88db0b, 0xf1e24c6f, 0x1fc20ec8, 0x46b1ce77, 0x11b978c2,
4252 0x971b79ee, 0x6042eaad, 0xf15e6cbe, 0xb579b3f0, 0x78d20f35, 0x8bb58923,
4253 0xbcec420b, 0x3223c576, 0xaf3c83b3, 0xe02bc044, 0x2a5dc233, 0xa7ff422f,
4254 0xfa8cad79, 0x607f2ef7, 0xba479c15, 0xfb84a56b, 0x54f9c62e, 0x009cced4,
4255 0xdf43c0fa, 0xf3693887, 0x69ed0447, 0x00296af3, 0xd73f8c78, 0x4bfb66e9,
4256 0x427bbc7c, 0x7e7351f2, 0x1ea2f4db, 0x3665d20e, 0x849acba5, 0xd5c8a3fa,
4257 0x168e462b, 0x7ab9c604, 0xe20bc6e9, 0xe6e17eba, 0xbfe7ba89, 0x74f1e249,
4258 0x4f6fbf1e, 0x6265489e, 0x47e422bd, 0xaf9093c8, 0x817ce0dd, 0x0702519e,
4259 0x4f00f372, 0x1a7ea18f, 0x4c5e7b27, 0x8f217962, 0x54afa74e, 0xe79e753c,
4260 0x0cbc7085, 0x2399f465, 0x6de7c78f, 0x078a31e9, 0xb6c0fedd, 0xe27c7d24,
4261 0xcc47cebb, 0x9881c843, 0x8c0e519f, 0x21e91bdf, 0xba46c0e2, 0x6721e918,
4262 0x7e40fa9b, 0x5d939121, 0xb9cb77e0, 0xe8d7caa6, 0x5a7772b8, 0xcbf703f6,
4263 0x65a4cf25, 0x7928c955, 0xa8572d16, 0x30ad2f4c, 0x1898b8b1, 0x970e5dff,
4264 0xcb923328, 0x3ec1270e, 0x830ddbe3, 0x0c2f2cad, 0x5c7145f7, 0x9215a78a,
4265 0xe83f809b, 0xfed04fdf, 0xbd926417, 0x712b7f80, 0xd6fdc50f, 0x9e3e7124,
4266 0x5fd2e1e5, 0x582e942e, 0x35a70fc7, 0x83473fff, 0x8ab2ecbf, 0x4f5625fa,
4267 0x153de135, 0xab25ffc4, 0xb93af367, 0xa2b9eacc, 0xfc29d69d, 0x7bfceeae,
4268 0xef566ff2, 0xcdffda2b, 0xb45ebfde, 0x21dac57f, 0x7fb69481, 0xa357f0f5,
4269 0xae7f30fd, 0xbbb548c7, 0x62bbf02f, 0xe529eb62, 0xdcf30d4d, 0x15fe3e44,
4270 0x96ab97ce, 0x8562bf15, 0xb762a23c, 0x67c4f213, 0xdf3b73f0, 0x90f414b6,
4271 0xf7bc26ad, 0x9ba04a01, 0xc0e2cc96, 0xc6a49e82, 0xcbce17dd, 0x2fbba091,
4272 0x246635e4, 0xc192927b, 0x61ab7abf, 0xcd47c814, 0x060c1f3b, 0x0ee80bff,
4273 0x05be14fd, 0xfa50da77, 0x436abced, 0x46705e6c, 0x193d9172, 0x6cdd1af2,
4274 0x3a724adf, 0x14051dc8, 0xadf6b80e, 0xf4d68427, 0x8035b2fb, 0xfb0f6a3a,
4275 0xc1659527, 0x986ba478, 0x9cb8fbc5, 0x2e9ecbe4, 0xb8b9bcf0, 0xe061d1f1,
4276 0x7ed89997, 0xef48693b, 0xe5a13f90, 0x74798fdf, 0x47b5b9e9, 0x3e3ee166,
4277 0xdc90cfdb, 0x6e838c6e, 0x24179c8d, 0x25603f98, 0x6fdc2ec9, 0x7f1c9177,
4278 0x307fcf16, 0x1cccbe31, 0xccffb31c, 0x1fbf45e7, 0x870fe70d, 0x375e5958,
4279 0x710ca79d, 0x89c401b8, 0x33e42165, 0xf55604f4, 0x09177d60, 0xed19f91e,
4280 0x7624f1ff, 0x336585ef, 0x4c87e5d1, 0xd876664f, 0x21f9656f, 0x12706ac9,
4281 0x73e4ede8, 0xbb7a01c4, 0xe0a6bd79, 0xf1c50ef9, 0x3c5fcc03, 0xef002260,
4282 0x01c06a8b, 0xd72d7479, 0x48e7ce2a, 0x4e66bfb4, 0xe3efd17f, 0xc85af39a,
4283 0xcad078cb, 0xb1162fea, 0xd396833c, 0x5af2005a, 0x952d73d3, 0x93b3f9b1,
4284 0xf13f9992, 0x78f14a62, 0x3eb043a0, 0x43f8c099, 0xa2065376, 0xbaa579f4,
4285 0x63f80920, 0xe288e02b, 0xb8ecdd21, 0x3f4bfa17, 0xc3cde14f, 0xafc46ee7,
4286 0x4a901ce2, 0x66fc3bf1, 0x47ee139b, 0x7829317a, 0xcb41c833, 0x839e1316,
4287 0x26b9aade, 0xab6b7d42, 0x257901d3, 0x9305e62f, 0x4c5b3e71, 0xc9ad9f38,
4288 0xa12dd72d, 0xa3e9af70, 0x14f8058c, 0xe92c512b, 0xcec54f20, 0x99f3e97b,
4289 0xacaf4cc9, 0x7a793134, 0xf589d93c, 0x7e3a25c7, 0x8457bc01, 0x4fce24f2,
4290 0x75b0b734, 0x0d29a76b, 0xf275f032, 0x25de7144, 0x3c7f832c, 0xbda08cb2,
4291 0x0353691c, 0xb9538c4e, 0xfd29336d, 0x07661147, 0x08b47d46, 0x0528c3f3,
4292 0xfda08f0e, 0x04a9b5ed, 0x1e7845e6, 0x4f9c8de8, 0xb28d206e, 0x70dfb685,
4293 0x74c2b889, 0xe92f1bbc, 0x2ddcbff3, 0x8d14d18e, 0xb62488a4, 0x78f863c7,
4294 0x00adc4c5, 0xf45894ff, 0x7b018def, 0xe318e14c, 0x49339c30, 0x1bb476e6,
4295 0x2e7b16e9, 0x8dede447, 0x853dfb91, 0xcd58c0fe, 0x66d87805, 0xfb07bf73,
4296 0x9506fe7f, 0x46175a24, 0x6a3ed7d6, 0x61537a39, 0x798c94b9, 0x6d1f947b,
4297 0xadd707c0, 0xfdc3f2ad, 0x62f5d787, 0x81df03fd, 0x7d66b95e, 0x87d80666,
4298 0x511f4e02, 0x7e033e0a, 0x7e32a472, 0x951f5c72, 0x79c9f5c7, 0xbe429fc8,
4299 0x9fa0cf80, 0x46606a5d, 0xe50738a2, 0x9fc0f5cf, 0xfd046cdb, 0xb6779fdb,
4300 0x12b9034c, 0xfce31ce3, 0x2d572c6f, 0x8547b25b, 0x76645f79, 0x4b977466,
4301 0x3c8c635a, 0xc1852bfe, 0x4d5675eb, 0x1bf1009e, 0x2dfb8a9b, 0x162e3c59,
4302 0x639d1fcb, 0x59f043f8, 0x51e58d93, 0xa9297e08, 0xbbae2bfb, 0xe2122e4a,
4303 0x3f1123c8, 0x28cbf04f, 0x61f3187f, 0xd7e61147, 0xe8a5f919, 0x7d015382,
4304 0xb4bf1ed4, 0x089027c5, 0xc8d27605, 0xb992072f, 0xbf26d29f, 0x5e03b65c,
4305 0x6497d696, 0xa4fc5d7f, 0x5b47f396, 0x4cacc3ed, 0x5f9f19ef, 0xa8f66148,
4306 0x41faab4e, 0x5b85e83e, 0x7b902e4c, 0x70b90dca, 0x325d513f, 0x95288efb,
4307 0x4dbea13d, 0x5b667a61, 0x667a8cc8, 0xc1e3cd9b, 0x161cd07d, 0xa78a241f,
4308 0x5c9af211, 0x35ce2c5d, 0x0cfcfc31, 0x1aa0bfe7, 0xe212761e, 0x74607f0b,
4309 0x014b7a1f, 0x9d25189c, 0x1fb93367, 0x00db4a78, 0x6c3dcbf7, 0x7c0d3a2d,
4310 0x04b20c95, 0x35c74f79, 0x38ad77dc, 0xdbfea1ae, 0x2950fbb9, 0x9e0afdd8,
4311 0xd76431e7, 0xd062d2a1, 0x37a65627, 0x29fd71cf, 0x4e60c3ea, 0xf70d0fa0,
4312 0x4c230d15, 0x53ddc54f, 0x1f937c04, 0x77bb8f6d, 0x0635d1a8, 0xef771ac8,
4313 0x98f711d0, 0x7bdc2714, 0x797bc1e3, 0xe1efeee2, 0x67bc60fc, 0xc7927fa6,
4314 0xf83f0562, 0x36dd8695, 0xb3276be0, 0xb2ad41c7, 0xa92bcb2f, 0x23fc09ec,
4315 0x147f0ce4, 0xf7bfc15f, 0x7cf62e79, 0xbe7c2dc3, 0xb614b88f, 0x61a8dd3f,
4316 0x082fe81e, 0xedc82efb, 0x1e6b6f52, 0x5f4b0bd3, 0x5d7c019d, 0xf98ddf38,
4317 0xc8a58fb6, 0x2497fcf8, 0x7409e96c, 0xaf182972, 0x92ceaa0a, 0x3df45293,
4318 0x81f594a2, 0x4eaed4b8, 0xfe3085c9, 0xb5cf56c3, 0x5a513f00, 0x4377c20e,
4319 0x82141786, 0x580db65e, 0x4a760199, 0x1ae14dc0, 0x8516c9bb, 0x6595c043,
4320 0xb0f87c65, 0xd6b5e675, 0xd03bec4e, 0x4f47b53b, 0x417be058, 0x39fd60ff,
4321 0x3e18f746, 0xf947ba00, 0xea1bba40, 0xdc050f02, 0xbff2dede, 0x25c60f87,
4322 0x87e103e2, 0x76ecbf51, 0x1ff78fc0, 0x73b37b97, 0x6fcf2c1d, 0x24778c88,
4323 0x9b25f246, 0xb05d8a72, 0xf9d1597f, 0x3e525887, 0xa067ff3a, 0xff766ee7,
4324 0x04e7f0b0, 0x45cbe4df, 0x234bafd8, 0x2e83de78, 0xe21fb0d8, 0x823cc349,
4325 0x63060eed, 0x744fdff3, 0x59282ea3, 0x72674d60, 0x1bb5efc9, 0xefd09610,
4326 0xc715401c, 0x75d7e81d, 0xe2e8bd45, 0x242725f8, 0x03c5ce09, 0x05c95f2b,
4327 0x019c33ff, 0x8f300fe3, 0xed3ec30f, 0xb951d66b, 0xeb029f30, 0x8fc09ec8,
4328 0xfa59f7af, 0xaf693027, 0x7dbf9977, 0x4fea33a3, 0x97b8fd09, 0xbfc62b77,
4329 0xcbf4cadf, 0xcfb66e8d, 0x163d7a0e, 0x801f610e, 0x1487008c, 0x62ba6a9e,
4330 0x6a1dbd45, 0x11be78a4, 0xd8f4a0e0, 0xf01a9123, 0xee4c8a17, 0xfbf012cc,
4331 0x8015853a, 0x5ffeb9b3, 0x340e20dd, 0x23fbf43e, 0x9178ef00, 0xe7d2eb1f,
4332 0x6cfd1ac7, 0xf588ffe1, 0x148ff086, 0x47e1088a, 0x7874fb41, 0xe0e9f14e,
4333 0x0c8de0f7, 0xfefe305b, 0x5af3ab78, 0x85779737, 0x98bc63ce, 0x572be5c7,
4334 0x4cba5246, 0x5a3f3120, 0x0a4a05bf, 0x2483f8ff, 0x82f18c9c, 0xe7f80516,
4335 0x8e449716, 0xadd9f0c5, 0xf875f543, 0xf68aca8d, 0x46fbded7, 0x2242323b,
4336 0xff1f9b5f, 0x3e83cb4d, 0x47f62fb6, 0x18f7db1f, 0x2bf643de, 0xed0db0e0,
4337 0x1c3bf6cc, 0xb5070f0c, 0x73ed76c4, 0x4dc3ef2e, 0xef10f98d, 0x4bebb3dd,
4338 0xee6fa3b4, 0xf05df2fa, 0x569d871b, 0x8767c408, 0x8a981e9f, 0x39a1d271,
4339 0xf442be78, 0xc6b4fdeb, 0xe473d84a, 0xdfff711f, 0x5b8f0a01, 0x582cf803,
4340 0xf1f671be, 0x0bbfa027, 0xdbc615c7, 0xcd52fc7c, 0xebe20bd3, 0xc81efca5,
4341 0xa7f31203, 0x7e01fb44, 0xd6bbdaef, 0x31105e48, 0x3497d2c7, 0xe820bfa0,
4342 0xb1a9cb78, 0x78fc95a7, 0x98efc0ba, 0x39afbfe0, 0x295edccf, 0x714e97f6,
4343 0xefbd91bc, 0x4ddb3ee3, 0xe02af735, 0x2394dfa7, 0xb8cc7713, 0xe2569ce3,
4344 0xfc6b898e, 0x63f06ac3, 0xc4f4bef6, 0xbf8b8804, 0x2f91e325, 0x9fdb686f,
4345 0x20dea1f2, 0x3377dc27, 0xd0a6f5e2, 0xfdf00abd, 0x97931b38, 0x7e1fc6f6,
4346 0xeb8fe51d, 0xf984de81, 0x9425837f, 0xdf5d231f, 0x8cdbf5dc, 0xf8f17ec6,
4347 0x02de8b6e, 0x6f0e82ef, 0x054e2d9c, 0x0747b47c, 0xa6ee9f23, 0x79d3f3f3,
4348 0xfcfce985, 0xd37b4fd4, 0x3efac0e7, 0x05d60e5f, 0x9feb7a7f, 0x4f3f00cf,
4349 0x0c98e5f0, 0xeac327c6, 0xb620c89e, 0xf88c9d28, 0x74636eea, 0xc0e9fc9b,
4350 0x7e3e5414, 0x6ce700d2, 0x536c38ca, 0x57ef1389, 0xbdfcfc24, 0x954dbed1,
4351 0xea0318ef, 0x8cdf68d2, 0x738a6d76, 0xd7c3de26, 0x6384bdde, 0x2052aadf,
4352 0x5954b3dd, 0x80fbb0aa, 0xe02e9f99, 0x6ff3d231, 0x09b6eca4, 0x19f0db52,
4353 0x67071de9, 0x3d353caf, 0x3fc2bc01, 0x4e10f717, 0x78f686f9, 0xd7cf4db8,
4354 0x7e8d4fe7, 0x5b6ad41b, 0x8ba46472, 0x83e85db1, 0x00a01852, 0x23f83f4b,
4355 0x48596ce3, 0x1a4bd2bf, 0xb579c371, 0x93e449ae, 0xc642bb18, 0xba7e4777,
4356 0xb59ec1cf, 0x97154fc5, 0x1193c44c, 0xf6b52be5, 0x55f02b31, 0x8565529d,
4357 0x6c1babfd, 0x52a45713, 0xb4fe8c3c, 0x5bee0a78, 0x84089a35, 0xce84c6c6,
4358 0x813885ed, 0x1c5d5f38, 0x7c0253da, 0xc0694fb8, 0x05f35375, 0xf8c61bea,
4359 0x15a1b599, 0x6ac3f056, 0x0b8c6533, 0xba23481c, 0x6dc7a073, 0x3daaefcc,
4360 0x9dc13ade, 0x0a73bda0, 0xdc4c9f6b, 0x6768f999, 0x51be3053, 0xf384daba,
4361 0xf6b92d1f, 0x321f8267, 0xd9afdd9d, 0x7f643f5c, 0xe9b78526, 0x1fd434ce,
4362 0xba1f6a63, 0x110941d7, 0x3e2177fc, 0xb929996f, 0x95efa39e, 0x2f585d3a,
4363 0xeb879d9d, 0x655f21b8, 0xed0f1e4c, 0xd75c54e3, 0x2917918c, 0x3cfa6f10,
4364 0xf5802a47, 0x71a92ee1, 0xe4fc1999, 0xe21c6c89, 0x7ac067f0, 0x19f19df3,
4365 0xcf20d603, 0x05d5fa88, 0x75ea186b, 0x3ba5b3eb, 0xbf81efce, 0x36f4b04f,
4366 0x8e51cf09, 0x7f12e471, 0xae94ff0c, 0xfea4f4a6, 0x7650a4d7, 0xe4f1f031,
4367 0xc40932b1, 0x656df1f0, 0x5d881256, 0xb1f3f20f, 0xde2af52d, 0xf8e42037,
4368 0x53bfce66, 0xdee865a7, 0x0ede6fa7, 0x886267f6, 0xfcb841c7, 0xd9cb80fc,
4369 0x3bfd7ccd, 0x1bab93dd, 0xbf308cb7, 0x65a4cfe6, 0x671d2a74, 0x960f4a76,
4370 0x70d2d51f, 0xe5f07318, 0xcf4083ae, 0x618fa0fd, 0x5a2f2b3d, 0x2390fc89,
4371 0xb77f00b9, 0xb7edf4b8, 0xe3d7d50e, 0xe8353fee, 0x74e0db81, 0x0faf1c94,
4372 0x56dfdc84, 0xc710ab2f, 0xe288adb9, 0xbd61fd17, 0x5eaede7f, 0x107cecb8,
4373 0x5bef86dc, 0xb2a4ec2f, 0xefca9436, 0xae1fa16e, 0x7e815722, 0x3f572318,
4374 0x4cd2fc01, 0x01399eed, 0x21fb08bf, 0x54a5f3d6, 0xc83f815e, 0xab8c4cd9,
4375 0xe544b98e, 0x9eba2336, 0xea0be88f, 0xf812b84f, 0x7ad81f39, 0x221df6ea,
4376 0xd4fe83fa, 0x9fdddfc1, 0xb550a318, 0x75700052, 0xd442fe25, 0x2c571857,
4377 0x10450385, 0x8739cbdf, 0x42af1b71, 0x5768a7d7, 0x8c7a679f, 0xd2ae0bfe,
4378 0xf46ffc15, 0x789c4433, 0x7ff08a52, 0x89117cf4, 0x31514e17, 0xa1f8238e,
4379 0xf208f014, 0x38c6453d, 0x21fc7b7e, 0xe29fffc6, 0xe3c2920b, 0xaf48bd7f,
4380 0xe083f08e, 0x4617c103, 0x4347f1fb, 0xfb2da75c, 0xf5f29691, 0x1f7f63f6,
4381 0x7b74f515, 0x6764887e, 0x7363d97a, 0xb5f37960, 0x0fc0d9b7, 0x83f5c499,
4382 0xf89143b0, 0x17c65ad4, 0x29671bfb, 0x05e46fb0, 0xc51790bd, 0x0adf88bb,
4383 0x4d58ac3e, 0x9e397e30, 0x7aa6a5eb, 0x8ef3cf16, 0x12900396, 0xec7a1252,
4384 0xf9675609, 0xb79e822e, 0x5228be70, 0xf7f028f6, 0x49756e5f, 0xb913882e,
4385 0x82703c79, 0x6078c25b, 0x7f823e9c, 0xc75bf6d0, 0xd758014a, 0xa093f519,
4386 0x7fde64f7, 0x7df09f1c, 0xdc9f2357, 0xbee5c290, 0x9ffee93b, 0x03c60bf4,
4387 0x4db53b5d, 0x7b7df157, 0xbe0d9d74, 0x5ed9c82d, 0xfe02bf96, 0xa6f5d035,
4388 0x3bf60a4b, 0xe7ef4535, 0xf05b385c, 0xf20b5c4b, 0xaf798df7, 0x37b4f9c6,
4389 0xc7e124fe, 0x8c5ebf73, 0xf2c2b37b, 0xa6768df9, 0xbfc2bb5d, 0x32abd233,
4390 0x26bfb125, 0xde1c6bf4, 0x8b6dfeb9, 0x5fe9ed6e, 0x53feefa1, 0x2bf457fa,
4391 0xcf1882ec, 0x5adb97a8, 0xbb3d09cf, 0xe309836a, 0xf5f03727, 0xae3c0df2,
4392 0xc3f70cfb, 0xdede3c02, 0xf782d17c, 0xb6550653, 0x63dfe53f, 0xd6d038c3,
4393 0xe97fccdd, 0xfbe2756d, 0xc6324a0f, 0x641c1e29, 0xd74c3d42, 0x3f308526,
4394 0x3e9098a5, 0x85dacfb0, 0x2b56b3ed, 0xe3d432e1, 0x7e40852e, 0xf1959e54,
4395 0xfa6f83c1, 0x0fff4067, 0x5a6deb1e, 0x70e37181, 0x4331f803, 0xa7dc140a,
4396 0x313b334a, 0x6f54dcce, 0xe6aabcc6, 0x03daffba, 0xf9aa277f, 0xf2c17122,
4397 0x39bd5f66, 0x7a044fb2, 0x96fc8c62, 0xcd11790c, 0x0ef3042d, 0x970b4e47,
4398 0x06e97ac0, 0xd602b0d2, 0x7635c3e1, 0xa788dd8e, 0xc6de7ca3, 0xbec8847d,
4399 0x1bcb3d41, 0x79e14929, 0x06fb7123, 0x6fb8250d, 0x15ae48a0, 0xd33ed124,
4400 0x60df667f, 0xf29ce038, 0x7a0c5ff3, 0x7fb1b488, 0xfb6355b0, 0x54872d4c,
4401 0x39327e02, 0x5e309995, 0x423eded3, 0xb764eedd, 0x82fb0ed3, 0xdbaf9fcc,
4402 0xccedc5dd, 0xfcfdfb6f, 0x986296c6, 0xd36ad6c6, 0x47632b4a, 0xe246bb8c,
4403 0x727c4671, 0xbfedc7bc, 0x61a35c84, 0x63c462dd, 0xe2194b71, 0x4fe29bf7,
4404 0x13d6c5c8, 0xebe06ec9, 0xb8ba27ad, 0x3c63dc61, 0x3b32e70e, 0xbf7604fe,
4405 0x326b78ee, 0x6e6ab3ee, 0x5a1bac27, 0x762e2cd2, 0xf3e3110f, 0x78dee760,
4406 0x3c07fc6f, 0xb935b7ae, 0x337d8fe5, 0xd851f763, 0xc51349be, 0x0faa3eeb,
4407 0x3cfd5f7f, 0xfe7e03e6, 0x13cc51f2, 0x4c86f85a, 0xadaf102c, 0x85e7e14e,
4408 0x03f81a03, 0xee3235e5, 0x18b9534f, 0x5625393c, 0x7960acdf, 0x3dd95b34,
4409 0x99afe59f, 0xf7e9e303, 0x927fafe5, 0x4df6f90f, 0xc00e5bcb, 0xbff01fdf,
4410 0x33bfb12c, 0x87cc6fe7, 0x95cb9afb, 0x2eb271c4, 0x9d7fe676, 0x034eb3ad,
4411 0xccda40ff, 0x79605efe, 0x8e6aaa70, 0xd9a5ef59, 0xd31ef155, 0xec492f0b,
4412 0x5f0a097e, 0xe2bf7dec, 0x7d9c06ef, 0xd5f06249, 0xbbf801aa, 0xb79be583,
4413 0xbe39c135, 0x5c6623f2, 0x9f3779bf, 0x4b33fbc3, 0xfcc16eb6, 0x4cad6f60,
4414 0x09d619f6, 0x9b53f3ba, 0x45e430e5, 0xbfb0d455, 0x98eb4023, 0x4c115527,
4415 0xbdb08e7c, 0xb70b3e73, 0x87eebfd6, 0x2feda83c, 0x9dbec1da, 0x0764d869,
4416 0xbf7ed3bc, 0xdc62fcf6, 0xc3e0a979, 0xea5e7b5f, 0x5a72610c, 0x379c3762,
4417 0x37c19cdb, 0x6383c223, 0x78a3faf3, 0x70b9fc64, 0xe067c5cb, 0xd7d9ef3c,
4418 0xe0067b3e, 0xf9d5f45d, 0x0d7f6067, 0xbd60f512, 0x6ff97dea, 0x7c521e78,
4419 0xdff72777, 0x117a5e9a, 0xbd3691cf, 0x6f41766f, 0xbb27f54d, 0xa6ca79c1,
4420 0x82caff6d, 0xfad2deb8, 0x2e77e831, 0xcffd41dd, 0xa2bafb04, 0x83e8326c,
4421 0x1ab1ceb6, 0x66b7b5e9, 0xf380376f, 0xf06f4a73, 0xdfe7237b, 0x2ecf2c82,
4422 0x3aadee72, 0xb8e179f1, 0x93356e73, 0x2061bd6f, 0xd40baa94, 0xdde7bb46,
4423 0x5e3a530e, 0x55fa01df, 0xeaf3cc3f, 0x73efd312, 0xd3a507f8, 0xf3faeccf,
4424 0xe66b17e6, 0xb434fb3c, 0x79b464d5, 0x01dc2dde, 0xc8f389bc, 0x55eeed63,
4425 0xd79b9076, 0x85f3c15e, 0x74f1b740, 0x2e5b4da2, 0xdc738376, 0xbb96d4a7,
4426 0xda836f30, 0x940b8843, 0xf287bfd7, 0x10e3b4d3, 0x3f0969c6, 0x2244dc17,
4427 0x538e763f, 0x98dcf3e2, 0x71c9cec2, 0x3a39c3fc, 0x39f4e3d0, 0xf8c72f3f,
4428 0x6ba39c58, 0xbd5cfceb, 0xefbf07bd, 0x77bb13ba, 0x1a87e378, 0x4a20dfbb,
4429 0x3468692f, 0x3a2dbd0f, 0x00383c09, 0xcf62430f, 0xa73e2683, 0xcc373918,
4430 0x03f405e9, 0xde722fff, 0x6247d693, 0x248f7a5d, 0x1b4d07d0, 0x26d239d8,
4431 0xf53df135, 0xad687ce2, 0x9e62ce81, 0x9087c96d, 0xffe0f6d3, 0xc979f8a6,
4432 0x8bf1d4ee, 0xcbd9d3c0, 0x87f8f589, 0xddbbe976, 0x8c96e36b, 0x607cdaf7,
4433 0xd3f704ef, 0x98f9e51e, 0xcc5acf2c, 0x96f82cf7, 0xbecf4f94, 0x17fde32c,
4434 0x517b82ab, 0x85f51b8f, 0xc23597d8, 0xb78739fb, 0x89d996a2, 0x04a5afb3,
4435 0xb39fb46c, 0x3f21d66f, 0xd51f5457, 0xc0ef8f20, 0x8b1aede6, 0x01f933d7,
4436 0xc71b113b, 0x9eeafb3a, 0x24dbd47c, 0x97f27e71, 0x437a1f5c, 0x56f1c789,
4437 0xb38dd39f, 0xfbc41fd0, 0xef1bdab1, 0x0a9ee28c, 0x50699dfd, 0x4cfa3f31,
4438 0x8d41c590, 0xedcc7fe3, 0x203ee466, 0xcf412f6a, 0x5768fb88, 0x3cf30468,
4439 0xe79626fd, 0x6a7efc69, 0x00d3c32a, 0xee04b387, 0x82d9750b, 0x52b8b9b8,
4440 0xd4cdc32e, 0x6c7b9115, 0xf6f7f85c, 0xe4977922, 0x2f309b91, 0x925de452,
4441 0x50bd5927, 0x613703d4, 0xfe10e51e, 0xdac03fbe, 0xeb4c2161, 0xecf97eb3,
4442 0x2c7efe4d, 0x3320b26f, 0x9cffcfea, 0x829630fa, 0xd5a67ee8, 0xa049fc4c,
4443 0x3ebdf82f, 0x22b27f22, 0x3575e449, 0x9ef7f3b2, 0xfa5f9d6c, 0x77a7bb47,
4444 0x5b73ec2a, 0x552776c2, 0xc6eb4b29, 0x4e2a1da0, 0xfabe2075, 0x03911f6e,
4445 0xc1ffc1fb, 0x76a707f1, 0xa57f1f8a, 0x6ab7faca, 0xe074dfb4, 0x4025be97,
4446 0x09ddbee7, 0x831773e6, 0xa3bf4a13, 0x9e7c14cb, 0xfec1c944, 0x073b995e,
4447 0xd22b1fe2, 0x2c63cc34, 0xdd00b0a6, 0x5e5c658c, 0x72a9aa68, 0xa5c72d1b,
4448 0xcdc875b2, 0x1ebe4ea9, 0x277f6169, 0xffc2d1cc, 0xe7db184e, 0x9682e597,
4449 0xe981d830, 0xecbfcc29, 0xdc31f2da, 0xb4eef1ff, 0x37582ebe, 0x7a4c0d4d,
4450 0x21b7e610, 0xf00933d5, 0xeeb4befb, 0x9b5f946a, 0x34fc0527, 0xfcb1ddc9,
4451 0x8871f8d0, 0xdbf4fc05, 0x61057187, 0xbc18f763, 0xe955943b, 0xa7c01e78,
4452 0xae323f18, 0x03d8bf21, 0x13883d71, 0xf11efbf1, 0xce3a7afe, 0xcc26e3f6,
4453 0xb64a6f8f, 0x59b47bf3, 0x00b608dc, 0x3fc7def0, 0xbef9972f, 0x5f775f96,
4454 0xa7bb2d5c, 0xb89eee3e, 0x08129e83, 0x8bef1839, 0x3b37de33, 0x4f300494,
4455 0xdc7f78d4, 0x307ebe08, 0x40f71bde, 0x5d0fb72a, 0xbddd1748, 0x5fd616db,
4456 0xf03d5beb, 0x09dc1b9c, 0x6b3c5325, 0x4d0c994e, 0x0d73ca8f, 0x3e708fd5,
4457 0x4e7e75f8, 0xc761ffb8, 0x2d7f003d, 0x79435fdc, 0x1dfc177b, 0x072a2d13,
4458 0xbb930ffd, 0xb9a75ec1, 0xacd4ff99, 0xd3cb7bb2, 0xbf4058e8, 0xc98fb834,
4459 0x89c4fa0e, 0x9bfe1b79, 0x3c7bee09, 0xa0499729, 0x92e9721f, 0x5c47ee1b,
4460 0x3dc7cfc9, 0xf6e9326a, 0xca9d7e61, 0xf96fe3f4, 0xefb1633d, 0xb7a04a4d,
4461 0xeb654d9f, 0x552cdb85, 0x9f198557, 0x9f740b3d, 0x70a8f26e, 0x599a9b4f,
4462 0x331c42a9, 0xce4fca35, 0x13e2092b, 0xeecedfef, 0xab5f7f4b, 0x81ebf39a,
4463 0xef66f3d1, 0xc7814600, 0x6fb8e92c, 0xbee38d3b, 0x4d4ce9d5, 0xd5a7818b,
4464 0x99dbe426, 0xeadb720a, 0x91e589e9, 0x1f719a1f, 0xcfa688e9, 0x02f71783,
4465 0xc480fb89, 0x7da2417d, 0x291586fe, 0xe91f1fe0, 0x74e77443, 0xd2ff5c42,
4466 0xf9039ef5, 0xf3a3047f, 0xa67f73fb, 0xff15dfc2, 0x82f48fab, 0xc5f187bf,
4467 0x4cdd73f4, 0x73cddf14, 0xd7f8b9ff, 0x79a3ddb4, 0xdcbc04de, 0x1578db9d,
4468 0x531dd7c8, 0x4dfa41ce, 0xf9bf7cdc, 0x9e3f653c, 0x61250ecb, 0xef3bc23c,
4469 0x4f180acb, 0xe6f687e8, 0x1d972f9b, 0x2a70bd06, 0x8bde09f0, 0xf626c646,
4470 0x8dfe8d5f, 0xe71773e0, 0x0db231f3, 0x493356ed, 0x5cac7966, 0x73ee636e,
4471 0xb37ee273, 0xe209fc9b, 0x98f62b3a, 0xd99fec08, 0xe1778941, 0x87754882,
4472 0x8af6165d, 0xf5942db8, 0xda1fcd21, 0xb95ea54f, 0x17c42569, 0xc8682fe0,
4473 0xfa80faf1, 0x56296e2b, 0x4f2bec0f, 0x79d607ac, 0x5a96c056, 0x58607a7b,
4474 0xdb7e84d8, 0x5f07d537, 0xe281f419, 0x82be2270, 0x605033e0, 0xc43e1fff,
4475 0x8000938b, 0x00008000, 0x00088b1f, 0x00000000, 0x59edff00, 0xe554707b,
4476 0xef773f15, 0xc3cdddde, 0x210366e4, 0x804d8404, 0x85701020, 0x5c7c0188,
4477 0x94422101, 0xd6da0300, 0x02101ba9, 0x16a52d79, 0x9b8cea9d, 0x8e233480,
4478 0xd29dad13, 0x542cce96, 0x2ec4952a, 0x4dd0689a, 0xd15c04ba, 0x63e02711,
4479 0xb46d63a0, 0xec083a2d, 0x98f8a71a, 0xe739ec76, 0x647dd7bb, 0xeffa7471,
4480 0xe5f98617, 0x7cebdfbb, 0xe3cefce7, 0x648a12fb, 0x40a50307, 0x676a733f,
4481 0xf1d31c02, 0xee016bb7, 0x0d1c442a, 0x00f250e0, 0x007f73e6, 0xd63c03c6,
4482 0xe9b6dc06, 0xdb007b5a, 0x2ed8c9ae, 0x95d6c801, 0xfc76edf6, 0x06dbb8fd,
4483 0xbab60173, 0xc00f77f0, 0xf9e9b1f0, 0xffbf8150, 0xbe956be7, 0x16bcea57,
4484 0x373f4d7c, 0xb772b025, 0xecf7000d, 0xb5ddc372, 0x9d701e34, 0x913ac4a2,
4485 0x46383668, 0x9dbac401, 0xef289d7b, 0xb1b0b870, 0xddc3db13, 0x5a64d759,
4486 0x1e17c2cf, 0x40074ec2, 0xf3e36e8d, 0x91bdb05c, 0x35eb8157, 0x87973cf5,
4487 0x33c685c7, 0xd752e6a7, 0x64df0e9b, 0x4e7dcf1d, 0x9aee5bd9, 0xc1ed1d84,
4488 0x508fa459, 0x87df2ca4, 0x43b4ccf2, 0xe47b3ec0, 0xf8ddfefa, 0xcb400e71,
4489 0xcce3376e, 0x987a9cf0, 0xe223df85, 0x8687b43c, 0x817ad35d, 0xb77b17db,
4490 0xff3d69bb, 0x7c4afa5f, 0x470700b9, 0xc4219dc3, 0x2e98be67, 0x4ec1dbe6,
4491 0x05e9e7e3, 0xd0402f2c, 0x39170ab6, 0x9c38e1a8, 0x1b0bf177, 0x9ff6b38f,
4492 0xaab37bd9, 0x222a89a3, 0xfa80031d, 0x3d3b0ac8, 0xa7accf64, 0x676e1400,
4493 0xfdc14105, 0x528297fa, 0x002bfa89, 0x5dfd82af, 0x01f7f1d9, 0xa73ef1db,
4494 0x67f61f67, 0xc6e01de9, 0x421cbbf5, 0x8c00d3ff, 0xdf1372e7, 0xc2b2fdad,
4495 0x65c806bf, 0xea411bbb, 0x0dc077b7, 0x9b7e89b9, 0xfdcb057e, 0xa7f05d43,
4496 0xcb623b2b, 0x53e23945, 0x5cb1f600, 0xf7813909, 0x169ce4b5, 0x7fb4280c,
4497 0xa303ecfc, 0x9f7d2e58, 0x7210e487, 0x67aa7842, 0x0dd7cd3f, 0xee96473e,
4498 0x74f8d2f1, 0x20b3fcb9, 0x9e09f908, 0x55018fe2, 0xd13b3df8, 0xfb855d76,
4499 0x42de0994, 0xe2fb7660, 0xc4da93eb, 0x7cc4aaf3, 0xfb6d7ebf, 0x1db9e40e,
4500 0xa9a2afed, 0x70af1073, 0x7c3d39d3, 0x31bca43e, 0x83d0b67a, 0xe394f517,
4501 0x8cdffd12, 0x52e6fe47, 0xf38c573b, 0x659cf53a, 0x400feca5, 0x8202d0fe,
4502 0x912af7df, 0x00a937b3, 0xcdaf1fe7, 0x9d73c0af, 0xeb6c0db7, 0xd49f71c4,
4503 0xd823ca85, 0xfdf3ceae, 0x5efdc75c, 0xaedd6f7c, 0x739fa899, 0x06b79a5d,
4504 0xe050c1e7, 0x8fa87189, 0xcf346786, 0x007e4923, 0xc445e3e3, 0xfc7df4df,
4505 0x189eda67, 0x58747e47, 0x1db0b8f1, 0x4813e2d3, 0x47f096ee, 0x7978830e,
4506 0x078703f8, 0xf81715e7, 0x543f9276, 0x222eb6f5, 0x8e83cebd, 0x0ce23aed,
4507 0xaf88f81b, 0x0f5c62a1, 0xbb7e1df7, 0x926b5f7c, 0x85753a1d, 0x7dc407e3,
4508 0x0a916b13, 0xfaffd361, 0xf631721f, 0x24c1f91c, 0x1347bf5a, 0xb5e6b33c,
4509 0xd238c0c2, 0x631c1b7b, 0x82c7beb4, 0xd9e26af6, 0x775d778c, 0x9fe3491b,
4510 0x69f9fd36, 0x41710fda, 0xc90f6f81, 0x43e478db, 0xf39d1e47, 0x8009a19f,
4511 0x4f764243, 0xf97b9ebe, 0xf34fe0f8, 0xee3dbf27, 0x8ffef1a0, 0x7415df91,
4512 0x079f0f1e, 0x1f23beed, 0xddf078ed, 0xd875e9de, 0xfc2a53df, 0x1dab47b1,
4513 0xdf5be347, 0x086b34b9, 0x123231f1, 0xd7d4bf8e, 0x86f49138, 0x4d985ffc,
4514 0xf908767e, 0x69f849ef, 0x8a29f905, 0xaffc415e, 0x8e34f6a4, 0xc18e5dc3,
4515 0x3d97ec65, 0x44bf2036, 0x203fb3fe, 0x40fdf5ff, 0x781fd1e3, 0xf3f654fe,
4516 0x419b41ae, 0xf1c600ed, 0xb85edc29, 0x835dda9a, 0x73f6758b, 0x3679f21b,
4517 0x80646bf9, 0x4c0109d7, 0x5029d321, 0xf648aa1b, 0xa3d63cdb, 0xdba7d4cd,
4518 0x55d0dff4, 0x9e2f7c9e, 0x53554723, 0xb54f23fc, 0xb502f225, 0x3fdc2bb7,
4519 0xed0df1e6, 0xc13fa24f, 0x740799a0, 0x2d383bc1, 0x5d4ff9e2, 0x7d6ffe22,
4520 0x4e8afe65, 0x13d6e73c, 0x13f7f72a, 0xce31ca4f, 0x78193c9b, 0xe536e748,
4521 0xe7da0f05, 0xfcc543d8, 0x1b6c5afd, 0x1ae74718, 0xba51165b, 0x38eeaaa9,
4522 0x36bf384a, 0xbc4348b4, 0xa3c1cefe, 0x19f3709a, 0x81eebfc4, 0x29d8675b,
4523 0x42719dee, 0xfdd88a16, 0x67fdfc55, 0xfadb0f50, 0xf219ff51, 0xf9871e06,
4524 0x0e3b5007, 0xc7f6478a, 0xdc8e2b14, 0xbc7c4d5f, 0xda26add8, 0x120b4828,
4525 0xf417da9b, 0x6c01ed6d, 0xc46057df, 0x71bf9789, 0x8d44e2fb, 0x8aafc9d8,
4526 0xde7b2dc8, 0xe28f30fe, 0x98c3b77f, 0x2ee9fc41, 0x0ca14d83, 0xd74f7d3c,
4527 0x4e954f98, 0xdfa992d8, 0xa0fc205d, 0x88bb003c, 0xaadd2d47, 0x5fbb441e,
4528 0xc70d56e8, 0x431f00d5, 0x8a02ed60, 0xb0630137, 0x01bff518, 0xc8031fac,
4529 0xa6894d1e, 0x68daf641, 0x6b1c3736, 0xd63ca1a8, 0x20e83ea4, 0xa4f8da3f,
4530 0x55d0e1f6, 0xffc6ee66, 0x27686153, 0x53ff11c5, 0xed82378a, 0xfb527b4d,
4531 0x7887c21b, 0xa953c35e, 0xb13a9bdf, 0xddb44aed, 0x3a8c5705, 0x997f033b,
4532 0x42b09304, 0x5c711e20, 0xdc70ecd0, 0xd97dbc89, 0x6f4953ed, 0x3f426d07,
4533 0x0fd94f18, 0x2cbf2b55, 0x7e287114, 0x2fec8201, 0xf3474207, 0x9df9ae50,
4534 0x63da5ea5, 0xcff45dbe, 0xfce52def, 0xbaa0f602, 0x65500d12, 0xde9096f8,
4535 0x176f2f51, 0x9937b9e3, 0xfc7411f1, 0xa6cded87, 0x1e91361e, 0x073635d0,
4536 0x079ee553, 0x4fb4edc1, 0x3f3c01fd, 0x903c6bce, 0xd7e96fda, 0xb4d3ae6f,
4537 0x2c7464fb, 0x75287362, 0xfd1e1f9c, 0xa17aa554, 0x73fbf537, 0x5cc09bc0,
4538 0x60133f4b, 0xeb07e902, 0x97b1802b, 0x8ee4678f, 0x344f97a4, 0x329c5751,
4539 0xd7fab1d7, 0x41697c9a, 0x344e28f1, 0xf120d505, 0xc8129365, 0xcfb79503,
4540 0xd7b943ad, 0xe0f0bc5b, 0x3dc7d43f, 0x9bd67ea6, 0xe173e0bc, 0x4a3de6fc,
4541 0xeff38230, 0xfe553479, 0x25baa10d, 0x79233ce3, 0xab53a9b3, 0x6e7e6073,
4542 0xb40e2d80, 0x98de48f9, 0x70e800fa, 0xe74afe50, 0xb94f8b4f, 0x6e46dc8c,
4543 0x5fffdcdd, 0xe22d46ee, 0xf8da7ca0, 0x201bc52b, 0xe27fbbf9, 0xe791b280,
4544 0x60dbecb0, 0xd73cc4f1, 0x56cf3df7, 0x61d3becb, 0xbab7db3a, 0x37d93bf0,
4545 0x6f463ebd, 0xc618ff63, 0x9150577c, 0xfcfa4fe0, 0xbd9d6625, 0x5e303774,
4546 0xcf2cfde8, 0x8362f383, 0x68c079c3, 0x47bca6ab, 0xf149c9ed, 0xcec0ada6,
4547 0xfe2ceefb, 0x500b63c7, 0x690f4b3f, 0xa0e0ac5e, 0x96ad4ae9, 0x95d373f2,
4548 0x4e4d14af, 0xe6ed27ca, 0x3687a5f8, 0x9c5165b4, 0x25e293f8, 0x7f858bf7,
4549 0x40ed4036, 0x829de2a7, 0xc383a3f3, 0x7b202e6f, 0xa5cce714, 0xb77dfcf5,
4550 0x76c2e8cc, 0xaf1cdf74, 0x17ac49ea, 0x2df38b75, 0x7ce352bd, 0xe724be79,
4551 0xbf68350f, 0xfb2f6306, 0x9e97f9f1, 0xc79f9077, 0xc62814ba, 0x47c5a28d,
4552 0xbea00d9f, 0xd270bfcf, 0xa2f84541, 0xa18e93ee, 0x2e03a96f, 0x50885504,
4553 0x3877b03c, 0xdb52bee8, 0x10c72ff3, 0x7d4f45d5, 0x34bd20e0, 0x471c2af4,
4554 0x41a8f61a, 0xb47afe0f, 0xf10745ef, 0x8153a5a8, 0xfdc9a531, 0xe663f71a,
4555 0xc23e7964, 0x092adffe, 0xf933ae7e, 0xe2d3f168, 0xce333aeb, 0xe54f6fac,
4556 0x763046e3, 0x0dfce096, 0x4f1c759d, 0x8e647437, 0xaabc5633, 0x28ead88f,
4557 0x4eefd7ee, 0x1bf9b71d, 0x941c061e, 0xd9e3d317, 0xd3878b51, 0x70f11a60,
4558 0xa26eb238, 0xe97f791d, 0xa844c364, 0x37afa918, 0xe56d7ccc, 0xf5e9cbcb,
4559 0x0e67ef62, 0xf1fe73ca, 0xfc17df1a, 0x48edffe3, 0xe209c9e6, 0x25b7e609,
4560 0x3ed94fe1, 0x8b23e135, 0xc0dbbf69, 0xbdfa44d7, 0x53a39c2d, 0x24335bfd,
4561 0xd85976fc, 0x242a0c19, 0xdbf38d9f, 0x41da106d, 0x3bf58ff6, 0x92f03fb9,
4562 0x981075c2, 0xd4deac71, 0xdfa9bd77, 0x8d5fbc7a, 0x30f54d9b, 0xfae283ea,
4563 0x6ea37b55, 0xbf316fec, 0x3476bd37, 0x0cbcf48f, 0x16599c44, 0xb2c67112,
4564 0xd2279597, 0xd0331cfd, 0x8ddec98f, 0x823c2761, 0x719b97e3, 0xc6277966,
4565 0xdfa46519, 0x30e6c6c7, 0x423d025f, 0xd8bcf4de, 0xfe3a9dd2, 0x2ba8814c,
4566 0xf67acd87, 0xd57b34cb, 0x02a721c4, 0x51e65bd7, 0x359e41bd, 0x8ffda768,
4567 0xe1fe42cf, 0x933dc7fa, 0x397b1ef8, 0xd669bd3b, 0x057b56e9, 0xc3ea8b12,
4568 0x5b91de90, 0xf737e490, 0x3921d860, 0x01a9e61a, 0xbdd27fd2, 0xd2ecc565,
4569 0xdd16f78c, 0x1d5fe38d, 0x6bd1febf, 0xc62def92, 0xe1e272de, 0x597f8a2f,
4570 0x43e29b33, 0x172788a7, 0x7cdd70ab, 0xeb81c3aa, 0x33a77f5a, 0x3f0bf748,
4571 0xadea88f2, 0xf213c4a5, 0x0b72b0cf, 0xfeeb04f1, 0x4afeb4f1, 0xe146192c,
4572 0x8af657f9, 0xe2e5647a, 0xaf77994f, 0x46e7164d, 0x74c98dbd, 0xffeab00f,
4573 0x9d442f96, 0xb16f7d69, 0xa03df10f, 0x6f30ac25, 0x9cbe07bb, 0xc6f28a50,
4574 0x509f3efa, 0x16eb5887, 0x54f5b479, 0x797d5036, 0xa0ceaff1, 0x74bce513,
4575 0x1f0fe5f8, 0x2ea5f6c0, 0xf2e63117, 0xc1d95c71, 0x0da2d37e, 0x721d7115,
4576 0xebbceb18, 0x7c73bd68, 0xc81ee88f, 0xbc40dbba, 0x5137ceb8, 0xb5bb16ff,
4577 0xa9d71b42, 0x9183b06d, 0x3ae499ea, 0xcac75eae, 0x8d864b14, 0x566bfe66,
4578 0x7bc42373, 0x57346e2b, 0x883dc625, 0x6b88dffc, 0x533b38dc, 0x5cec08fc,
4579 0x1b8c8ca0, 0x777b158d, 0xfd5321ba, 0x977ce113, 0xe3dcef5e, 0x24e6de46,
4580 0x1e2a1b78, 0xde84b67a, 0xa13b4e71, 0xffce94b5, 0xafb204d5, 0x9ceb7e75,
4581 0x9e7e4ce7, 0xc601fba7, 0x952ad69d, 0x279b65f5, 0x708baad0, 0x7626f31e,
4582 0xf5483732, 0x17fe8cfe, 0x8d0788cb, 0xb25c7007, 0x7d1da1ff, 0x90438854,
4583 0x421cdcf9, 0x3ce492a1, 0x74e2ffd8, 0x97d91be2, 0xa6fc9dde, 0xb2e5d37d,
4584 0xfdc45150, 0xfb88a6d5, 0x287d8f6b, 0xfe4dee8f, 0x306d6ac3, 0xfcd67ec9,
4585 0x80fe4d7b, 0xefd3dc5d, 0x7c4420a7, 0xd81e0b0a, 0xef2204fa, 0x1a778ad6,
4586 0x334aca0d, 0x7e442ff4, 0x035e4b7c, 0xea6d0b92, 0x33cce2d7, 0xcb1b49ff,
4587 0x5c393fe3, 0x03df9c94, 0x8a18eeb4, 0xc04dad7b, 0x28072471, 0x0b1c62ce,
4588 0xf97b63e4, 0x97ae2ce9, 0x6abb65a2, 0xa9956e38, 0x5b6b7140, 0xc9a9e6ff,
4589 0x05bfe1f9, 0xe91738aa, 0x95aa98a1, 0xa6fec527, 0x9560da1e, 0xbc17cf79,
4590 0x7888140d, 0x27a3f782, 0x47ee19dd, 0x6ddeb5df, 0x3d8273ed, 0xfa974ec9,
4591 0x0dfef9ea, 0x52a6f85f, 0xef9f019c, 0xfd6dc26a, 0xfbe953f5, 0x57cdfea5,
4592 0xd2a4bbf3, 0x02bf9296, 0xd5315f24, 0x7914ef45, 0xefb9bfb0, 0xd460229d,
4593 0x276a7e58, 0x6efdafe7, 0x8ec4e751, 0x84fbf164, 0x07826502, 0xdd653930,
4594 0xb857eea6, 0x55ea688e, 0x583e648d, 0x22dc7af3, 0x1e261e0f, 0x1486b620,
4595 0x487ced83, 0xf3ef5360, 0x16a34f2c, 0x76b63b62, 0x4bbfa26a, 0x3c97d620,
4596 0x00ee002f, 0x39feafc9, 0x52754c3c, 0x87964f73, 0x3eb14bde, 0xc4b1f914,
4597 0xfa8fdc19, 0x99c2f459, 0xcd5b8a22, 0xf50a682f, 0xbbea50c3, 0x679b736d,
4598 0xbde88fc5, 0xe81575e0, 0xda55e1dd, 0xc4b0ed02, 0x4d54d181, 0x1d66efca,
4599 0x5f9bb560, 0xc8d4abaa, 0xcb06dbef, 0xe6ce512b, 0x3b4abafe, 0x78b4f419,
4600 0xb634ba0f, 0x3009eb91, 0x95b65d84, 0x27f0a634, 0xf7290300, 0xb14e506e,
4601 0x8d61631e, 0x03a281df, 0xfde9ca67, 0x6fe4b9a8, 0x7347e4e5, 0x537bc50a,
4602 0x554bbd33, 0x7de27c90, 0x4d7f9aca, 0xafb3f0a1, 0x0b7b7f4d, 0x7bcda3bc,
4603 0x9e1b2ece, 0x4d1aadff, 0x05eb847f, 0x6edd9f51, 0xb7d5cdc6, 0xbc5f5c69,
4604 0xc78d1e05, 0xcca18a1b, 0xfac8bce5, 0xa78cddb9, 0xe352aa2b, 0xf03dcadb,
4605 0x91a11670, 0x635b4eb9, 0x0c0abfae, 0x7575775e, 0x6635b8ea, 0x36a6b69d,
4606 0x56e7fbf5, 0x930c9cdc, 0xc2ea6e39, 0x66c75b9e, 0xb90c7e71, 0x0cdef93c,
4607 0xb475e279, 0xf541c78f, 0x683c0b9a, 0x1c66e3a7, 0x01c92b6d, 0x177e28f7,
4608 0xa3fd9209, 0x53bfbed9, 0x719f8ade, 0x34553bf2, 0x1565ce2d, 0x29cd3f0a,
4609 0x514a7114, 0x9b276ca2, 0xa3ed9c72, 0xed9baf28, 0xe7ec5237, 0x533bc4d7,
4610 0xfc937914, 0xacc27c8e, 0x788aa223, 0x7b974b47, 0x8778a17c, 0x34dfa11a,
4611 0x5fd08ebd, 0x36a2de9a, 0x6ec5c751, 0x5ffef856, 0xc519f58e, 0x958bb5af,
4612 0x14f141a0, 0x2bfdc0f5, 0x54c3d615, 0x62704f88, 0x8f981dff, 0x4d8beea8,
4613 0xb6fd7513, 0xefe2f9b5, 0x9b780124, 0x64f168ec, 0x57e45d85, 0x286b0f8b,
4614 0xdf12cebf, 0x6ede9f29, 0x7755d3e6, 0x850af35e, 0xadaf4b45, 0x2f9ca7e4,
4615 0xb1463146, 0x475e20be, 0x53c7eafb, 0x917d23dc, 0xf32f479f, 0xadc2742e,
4616 0xa72e7eb1, 0x2fd36abf, 0xa839476e, 0x7adefdae, 0xeba5e734, 0x9530bab3,
4617 0x2b581887, 0xf2138fc8, 0xc7e6333b, 0x943ca6d5, 0x47e80363, 0xedfd4d6b,
4618 0x2eadf7cd, 0x0477efc4, 0x7e4c3d57, 0xb3d94675, 0xce2410ff, 0x9d187a4d,
4619 0x85addeb4, 0x090c3de2, 0x9b7ef192, 0x16f0179e, 0xd7b8e016, 0x54af718f,
4620 0x241777bc, 0x933eebe9, 0xb161d7d7, 0x079c764a, 0x25de9501, 0xdc3b03ae,
4621 0x443b6d45, 0x200b88ec, 0xfe81dfc2, 0x4fc45608, 0x9d73fcea, 0x9944723d,
4622 0xeff8e3c5, 0x9061f343, 0x7108ddc7, 0x3b740346, 0x32f042e1, 0xcb22b956,
4623 0x08af6ca9, 0x4baa5485, 0x82f64523, 0x5213a8b3, 0x2473a665, 0xb38763ce,
4624 0xd2a2fd56, 0x0b6011df, 0x3cfd3dd9, 0x0c79d61d, 0x0d4a4bc1, 0x555ca177,
4625 0x93695210, 0x1548601b, 0x39f32ff1, 0x4ddd6016, 0x01b8b77f, 0xfacd9fed,
4626 0xebf8f208, 0xa66a3ce9, 0xaf2d0cf3, 0xeb1615e0, 0x29129f24, 0xf39d7db2,
4627 0x2b11cfdd, 0x6f375e02, 0x03e2fc7d, 0xfbbf8995, 0x9eafc378, 0x2a3d3fa6,
4628 0xd3f70186, 0x665c4ddf, 0x9fb11add, 0x788f86ff, 0xe17dfd3f, 0x5215dfba,
4629 0x7ce8f23c, 0x8781f04e, 0xf60638f8, 0xb23f74e8, 0x7142b8d1, 0x128b8fdc,
4630 0x5c103bbc, 0x2f21b1e5, 0xf2e518ee, 0x43cca5aa, 0xab8d675e, 0xcf7a4ae3,
4631 0xe14e4d43, 0x91e4c1ba, 0x6aab7f25, 0x2af891fc, 0x8944a251, 0x944a2512,
4632 0x44a25128, 0x4a251289, 0xa2512894, 0x25128944, 0x5128944a, 0x128944a2,
4633 0x28944a25, 0x8944a251, 0x944a2512, 0x44a25128, 0x4a251289, 0xa2512894,
4634 0x25128944, 0x5128944a, 0x128944a2, 0x28944a25, 0x8944a251, 0x944a2512,
4635 0x44a25128, 0x4a251289, 0xa2512894, 0x25128944, 0x5128944a, 0x128944a2,
4636 0x28944a25, 0xffe12251, 0x72255300, 0x008000ab, 0x00000000, 0x00088b1f,
4637 0x00000000, 0xc5edff00, 0x30001131, 0xee300408, 0xd85aa12a, 0xaa66f6b1,
4638 0x964d2113, 0x5dbbcce4, 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4639 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4640 0xdb6db6db, 0xb6db6db6, 0x3d017e3f, 0x009b1baa, 0x00009b1b, 0x00088b1f,
4641 0x00000000, 0xc5edff00, 0x30001131, 0xee300408, 0xd85aa12a, 0xaa66f6b1,
4642 0x964d2113, 0x5dbbcce4, 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4643 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4644 0xdb6db6db, 0xb6db6db6, 0x3d017e3f, 0x009b1baa, 0x00009b1b, 0x00088b1f,
4645 0x00000000, 0xc5edff00, 0x30001131, 0xee300408, 0xd85aa12a, 0xaa66f6b1,
4646 0x964d2113, 0x5dbbcce4, 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4647 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4648 0xdb6db6db, 0xb6db6db6, 0x3d017e3f, 0x009b1baa, 0x00009b1b, 0x00088b1f,
4649 0x00000000, 0xc5edff00, 0x30001131, 0xee300408, 0xd85aa12a, 0xaa66f6b1,
4650 0x964d2113, 0x5dbbcce4, 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4651 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4652 0xdb6db6db, 0xb6db6db6, 0x3d017e3f, 0x009b1baa, 0x00009b1b, 0x00088b1f,
4653 0x00000000, 0xc5edff00, 0x30001131, 0xee300408, 0xd85aa12a, 0xaa66f6b1,
4654 0x964d2113, 0x5dbbcce4, 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4655 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4656 0xdb6db6db, 0xb6db6db6, 0x3d017e3f, 0x009b1baa, 0x00009b1b, 0x00088b1f,
4657 0x00000000, 0xc5edff00, 0x30001131, 0xee300408, 0xd85aa12a, 0xaa66f6b1,
4658 0x964d2113, 0x5dbbcce4, 0x6db6db15, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4659 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
4660 0xdb6db6db, 0xb6db6db6, 0x3d017e3f, 0x009b1baa, 0x00009b1b, 0xffffffff,
4661 0xffffffff, 0xffffffff, 0xffffffff, 0x00001000, 0x00002080, 0x00003100,
4662 0x00004180, 0x00005200, 0x00006280, 0x00007300, 0x00008380, 0x00009400,
4663 0x0000a480, 0x0000b500, 0x0000c580, 0x0000d600, 0x0000e680, 0x0000f700,
4664 0x00010780, 0x00011800, 0x00012880, 0x00013900, 0x00014980, 0x00015a00,
4665 0x00016a80, 0x00017b00, 0x00018b80, 0x00019c00, 0x0001ac80, 0x0001bd00,
4666 0x0001cd80, 0x0001de00, 0x0001ee80, 0x0001ff00, 0x00000000, 0x00010001,
4667 0x000e0004, 0xcccccccd, 0xffffffff, 0xffffffff, 0xcccc0201, 0xcccccccc,
4668 0x00100000, 0x00000000, 0x00000000, 0xffffffff, 0x40000000, 0x40000000,
4669 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
4670 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
4671 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
4672 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
4673 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
4674 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
4675 0x40000000, 0x40000000, 0x00088b1f, 0x00000000, 0x1113ff00, 0x51f86066,
4676 0x423ec08f, 0xac9d0c0c, 0xc4b462a8, 0x1818990b, 0x12b102fe, 0x3c430333,
4677 0x203aded0, 0x2388107d, 0x16181858, 0x2fd610b0, 0x022bd404, 0x2c4062c4,
4678 0x19b7c401, 0x9cdfb348, 0x1f0f680b, 0xc8037f82, 0x3f4024be, 0x1c360fff,
4679 0xfb5f40ad, 0x1819d502, 0x8aa06bfe, 0xf2a26831, 0x9bf13519, 0xcf2684c1,
4680 0x2167c68c, 0x63247fa0, 0x0d75b600, 0x000400f1, 0x00000000, 0x00088b1f,
4681 0x00000000, 0x7dd5ff00, 0xd554780b, 0x673ef0b5, 0xf3399cce, 0x00fde4cc,
4682 0x108f0992, 0x2104e034, 0x0432b445, 0x3b69488c, 0xc514543c, 0xf791e109,
4683 0xb14a3e44, 0x44033bd2, 0x350af808, 0x0380a050, 0xed168d02, 0x06823ca0,
4684 0xfda2901c, 0x5a1bdedb, 0xcb6ab7bd, 0x880b851f, 0x52d11921, 0xf77ac5ea,
4685 0xcc9f7b5a, 0xd0049339, 0x9fdffed6, 0xcfb3767e, 0xd6bdaf7e, 0xf7b5ebda,
4686 0xa441c448, 0x84be421c, 0xfc8471bf, 0xa484205e, 0x83bf52c6, 0xa908a3a6,
4687 0x2d0867d9, 0xc26425cf, 0x5c64633e, 0x136fcd0a, 0x179a2642, 0xbcb19b0f,
4688 0xfbcb3373, 0xdd4f6d0d, 0x01c9cb4a, 0x1349d903, 0x49116f92, 0x1467211a,
4689 0xd146fec2, 0xf321117c, 0xb35b2ccd, 0x426cc8ed, 0x98b797eb, 0x3fb69988,
4690 0x81e0d7b3, 0x429dc2fc, 0xd439d088, 0x67255c1c, 0x8417fed1, 0x45d9b084,
4691 0x47e93bf3, 0xd7b15e5a, 0x5dfa8210, 0xaf34b68e, 0x01f3908d, 0x9864b885,
4692 0xed693bdf, 0x86548405, 0xd16494f6, 0x05bb957a, 0xa9c748b7, 0xc6442cdc,
4693 0x42ef828d, 0xa8bb40c8, 0x5712b66a, 0x97c39b3e, 0x75c5c704, 0xc742dc2c,
4694 0xa912fda5, 0x61daf651, 0xcbb2b5bc, 0xf9cf831e, 0x51c71380, 0xd3cf35f3,
4695 0xdabb6871, 0x2c370497, 0xbe2456b1, 0xf3bf1d30, 0x73e679a0, 0x32df5836,
4696 0x5daecf39, 0x587ee947, 0x9b686547, 0x7983625c, 0x17e7936d, 0x6aabfac4,
4697 0x6bcfd64e, 0x9f74a0c3, 0x3d3e3ca6, 0x95c4201f, 0x1257cb17, 0x60db09e2,
4698 0xea7921fe, 0x63f7d8f0, 0xb3f71124, 0x5c40d9aa, 0x427fac4a, 0x40ddf882,
4699 0x2b8011dc, 0xb5bbb569, 0xa9d176fb, 0x8985b7df, 0xf31f6dbc, 0xc3ef9a79,
4700 0x27a70e5a, 0x4d347e61, 0x499738f0, 0x1309fd74, 0x4ab85389, 0x3246b5fb,
4701 0x7acbdc33, 0x186405ef, 0x888f884d, 0xe25adf38, 0x2ed21fbb, 0x4e9caeb1,
4702 0x3245fe9e, 0xabbd74bc, 0xfbfed604, 0x57f585c4, 0xb03d900d, 0x2aef6baf,
4703 0xcb90ce7a, 0xf90292d7, 0xd0d6bbf9, 0x7926932e, 0x0257c008, 0x614015b8,
4704 0xcb40d07b, 0x4713bbed, 0xe16971ae, 0xc61f3c57, 0x75128c73, 0xcdbce3fb,
4705 0x4d27cba2, 0xaf838a4c, 0x46e679cd, 0x34f3a79e, 0xd211d189, 0x67c64220,
4706 0x8b6f882b, 0x9ba465b3, 0x79b3b7c5, 0x85b6ce2d, 0x38ff3482, 0xe685b834,
4707 0xce4ddf65, 0x4741e05e, 0xa4064916, 0xe98c913e, 0x7000de59, 0x9c5078a4,
4708 0x03ef2573, 0x68c5fa9a, 0x1f4d225e, 0x0107c616, 0x8e012b2e, 0x481ab534,
4709 0x6adbac1d, 0x86a70822, 0x05cf4521, 0x9d5a7035, 0x1b94e14b, 0xb1b577eb,
4710 0x09b8832e, 0x23bc1359, 0xf8526528, 0x1dcdd2e6, 0x23bdf30b, 0xdb4c1c12,
4711 0x00ce2ee7, 0xa5322a78, 0x32f8ed03, 0xc700bf1d, 0xae38046f, 0x3f18fbe7,
4712 0x463792be, 0x6079be37, 0xb37c6eb9, 0x38a7c74c, 0x5df829b9, 0x63853e3e,
4713 0x233f2116, 0x95f1c5df, 0xfc704b81, 0xeb949906, 0x8f74b7c6, 0x7771821f,
4714 0x437e31f5, 0xfafd58de, 0xd7ea5607, 0xbff5b32f, 0x8f9bbc10, 0xfff5c16f,
4715 0xd6cddc82, 0x6c47f03f, 0xafda26fd, 0x37477c76, 0xf700c3fc, 0x5fc07dfd,
4716 0x7e9b7a19, 0xf5aa83fd, 0xf1b137eb, 0xc83e0d5f, 0xf8e1b7c7, 0xd90791af,
4717 0xc52d07fa, 0x3aa64df1, 0x991693b7, 0x21752c72, 0xfd176bc0, 0x074d3a5f,
4718 0x45be71d3, 0x422482d3, 0x901ffb68, 0xc5870881, 0xa850df16, 0xf142c97f,
4719 0x0be316cd, 0x0052b424, 0x38e5afba, 0xa977773d, 0x326d24fc, 0x4bf185b7,
4720 0x10e9f942, 0x96cebf3a, 0x4fbd2f4f, 0x47773be7, 0x42e0dba1, 0x6ed0247a,
4721 0xdf8a5f1e, 0x8841e0c0, 0x1daa7b37, 0x7b3793f8, 0xf22c70da, 0x40599f00,
4722 0xf03d8e70, 0xf1a35e78, 0xbe86bb4c, 0xe7d06c16, 0xbcfa422b, 0x80f1ef3a,
4723 0x160d3424, 0x3a3afc93, 0x8fca19ee, 0x1f93e508, 0xe9047e52, 0x08792359,
4724 0x94d38dce, 0x4b59115f, 0x5f70cb57, 0xfe0c48ce, 0x91583667, 0x7dad2f1e,
4725 0x60832658, 0x640a563e, 0xf24178cd, 0xff9d3e76, 0x089d7c3d, 0x57e022e7,
4726 0xb4f73d6c, 0x47a14cd6, 0xb2779d2c, 0x31a75dae, 0xf5be0462, 0x963d0920,
4727 0x7b2ffb41, 0x87d18f62, 0x4fd3c7fc, 0xfd26ba44, 0xf7d74a44, 0xd87e34ce,
4728 0x733769ae, 0x3f635aef, 0xd3e7de9a, 0xae559f7f, 0x431a77cf, 0xe5ce1146,
4729 0xa36c810a, 0xa7583ffd, 0xf9c7572f, 0x7db1248c, 0x43dde3e6, 0x049992d7,
4730 0xfe91fa59, 0xeb64e7db, 0x497ae7a0, 0xca1f383f, 0x9a4ef704, 0x8dea107f,
4731 0x4b7c7d84, 0xe7b3ef86, 0x90d7ba25, 0x5225f39e, 0x9273f606, 0x25271b9f,
4732 0x08b753e3, 0x7edfe73d, 0x4711ead8, 0xfc475cf4, 0x4e221fbc, 0x968787dc,
4733 0x0697bfe8, 0xf0c7d7e3, 0x3e32dfc0, 0x7be6b4f9, 0xe4aef84d, 0xa97c1ad3,
4734 0xcbaa9e6a, 0xd3ee8457, 0xa1b05fd5, 0xaf3e5754, 0x5e5742b1, 0x2eb0f0d6,
4735 0x447c1a5f, 0x25a1ff57, 0x0fe574cb, 0x95d6add6, 0xab5f2acf, 0xdbe7dfcb,
4736 0xef7faba8, 0x72ba6dcc, 0x0e4570e1, 0xd97e37c8, 0xe1499397, 0x135de17e,
4737 0xf0c42ed9, 0x73f3c558, 0xcf4c0c81, 0x2e985c07, 0xf4a57a03, 0xa9641e2f,
4738 0x0e697b7f, 0xf78ab9d0, 0xd9758d67, 0xf8f12740, 0xf18f4f1d, 0x03780c78,
4739 0xe75f50e7, 0xbc40b579, 0x025df740, 0xefd48f3b, 0x97fce67f, 0x6f48e590,
4740 0xc7a332d5, 0x8b3397ea, 0xe5aa5e81, 0xad9d5e48, 0x58497eef, 0xb21075c0,
4741 0x08a9fb1d, 0xedd0aa51, 0x3cdd20eb, 0x70188e3b, 0x3e105afc, 0xdef3816e,
4742 0xf8c02a5b, 0xa7b23791, 0x78f9870f, 0x25be60e6, 0x4762f915, 0x69f25260,
4743 0xc5e7e009, 0x26605cf4, 0x3e0267a6, 0xca074f4c, 0x5030fd31, 0x607b6987,
4744 0x0327a609, 0x14ff4c41, 0xbdf4c068, 0x7fa62340, 0xf4c06c0c, 0x4c21033f,
4745 0x4c1e033b, 0x14d4f1bb, 0x90f903cd, 0x20226fbc, 0x2e1492e2, 0x3372a97f,
4746 0x5c85f961, 0x2e0bee6e, 0x27defbf1, 0xbc5048fc, 0x2c59beda, 0xa8e83f6c,
4747 0xf3a50893, 0xbbf6c335, 0x44bcb0e7, 0xdd843f90, 0xbbb2f95a, 0xf483d85f,
4748 0x9fc7ef6b, 0xf381dce1, 0x9e030def, 0x8af2247f, 0x0b5dba7b, 0xc047ba0f,
4749 0x86b75e6f, 0xd5fe5276, 0x7c31705f, 0x2e5c06b9, 0x039cf5be, 0x0cc2e8f8,
4750 0xe6fa79d1, 0x1357d7be, 0x34da75ce, 0xe8b7f1f3, 0x851b17f3, 0x741e4c49,
4751 0x0e18cc25, 0x9e74e0f8, 0x96fb0c1e, 0xcfdaa981, 0x79d90cc2, 0x85ea193a,
4752 0x77643d70, 0xd517e222, 0x3fdeb047, 0xf57d1e7b, 0x5ec79b13, 0x47b68a72,
4753 0xdf507b19, 0x0bc4fbf5, 0xe41933e9, 0xbc6ad268, 0x85aae704, 0x40e5f7fe,
4754 0xbcc257e8, 0x6c3fafda, 0x826e9a08, 0xe375bbef, 0x552e76d1, 0x7d7683d7,
4755 0xce449fe3, 0x5941f8a8, 0x6fae09d2, 0x9d9b3556, 0xa89d7e7a, 0x325bfbcb,
4756 0x0dfe3a9d, 0x4af4a0ff, 0x9c120a26, 0x2b1cd5bb, 0x835b24ba, 0x1bb7e740,
4757 0x8bee86f0, 0x6af5605f, 0x47d97694, 0x67dc2d3f, 0xe17df3c7, 0x05efae5a,
4758 0x9fb41b49, 0x70778633, 0xd34ace85, 0x449ce51f, 0x9e32f9a4, 0x39aef553,
4759 0x7cf0ab7b, 0x94126fff, 0xc8ff3ce1, 0xe70458d0, 0x9b786553, 0x76fba1ec,
4760 0x80938881, 0xbf205cef, 0x91acdc77, 0x3208afe3, 0x41acb7ae, 0x79516e7f,
4761 0xf2a79747, 0x9f3f2e8e, 0x3d034b4c, 0x91937e6a, 0xff285e8a, 0x043bcae8,
4762 0x80bbf627, 0xfe04add4, 0xcdef6a7e, 0x700adcf7, 0xc8a5b03c, 0x6873f347,
4763 0xbf4a3f71, 0x6427cd95, 0x3aaf93a0, 0x1fb4057e, 0x755c73d9, 0x51f43d5d,
4764 0x669a870e, 0x85ea13c1, 0xa6459b9f, 0x9f74a9d7, 0x72753a25, 0x7e5c5e5b,
4765 0xf6fe5c64, 0xc6d7fcb8, 0x908a149f, 0xdefdb169, 0x44f2f82d, 0x478043e0,
4766 0xf9bc3109, 0xf467fdda, 0x3fe47fe8, 0x44feffb5, 0xffb4ff87, 0xfda9ffdb,
4767 0xff31ee0f, 0x5ff5bdc9, 0x149e8a6b, 0xdd7b1ce0, 0xe198e78c, 0x7a0839b0,
4768 0x19ab7f82, 0xf637dcf5, 0xd01775fd, 0x26b3e75d, 0x8e7a6262, 0x93bff280,
4769 0xdf767bf5, 0x0ffeb75f, 0x8d0b3f2d, 0xb60b7f69, 0xef80fad2, 0x64c8adbb,
4770 0x184e5eba, 0x2f5d2841, 0xefd1fd78, 0x2e2f2a11, 0x91dee2b0, 0x0f4cbf05,
4771 0x51fb00ad, 0x799fcb2a, 0x08284071, 0xed979e76, 0x1808c311, 0xa3ed40f7,
4772 0xad2fee30, 0xa42d1e84, 0xd61375f3, 0xa305fceb, 0x2ee78a7f, 0x24415e9d,
4773 0xe77e3757, 0xb5241c02, 0xe052f85c, 0xf0e22840, 0xd55ef4a1, 0x8f31e092,
4774 0xfbeaf800, 0x2e8c60b9, 0x0eff2376, 0x5bc88966, 0x77205922, 0xcb53d7c7,
4775 0x5540e2fd, 0xb6ec581e, 0xfd53eac5, 0x37cb3e79, 0xa0fd3166, 0x052feb0d,
4776 0x958d49fa, 0xd597ecf7, 0xcec891ff, 0xac3f58db, 0x53d72d7d, 0x1572e9e3,
4777 0xe6aacba7, 0xa6f6862f, 0x7f32f55f, 0xa65fbefc, 0xafdd0582, 0x10e6cbe0,
4778 0x23b5616c, 0x6bef7a82, 0x6d511edc, 0x9e1ea089, 0x3905c7c5, 0x6944f20f,
4779 0x8ced097f, 0xf404cc07, 0xedd79add, 0x9adfd81e, 0xf33d7ffd, 0x63bdfa33,
4780 0xf80dd59f, 0x0ffaf350, 0x4c6bdf71, 0xdd02d991, 0x2a1ee8bf, 0x1dfad2ff,
4781 0x4d9d7e7b, 0xc61d3f68, 0x55d27648, 0x613565ec, 0xcafc9c53, 0xe03e7de6,
4782 0x98f2019e, 0x3b5447ca, 0x53fb7c5a, 0x45cff162, 0x4417970a, 0x7c88b34f,
4783 0xa9df6f4b, 0x5d39525c, 0xfdabde7b, 0xbecc4a54, 0xc43f7ea4, 0x1ba87be1,
4784 0x2e935fce, 0xf2e83d6d, 0x02ebcc10, 0xf3834b69, 0x13f9b6a8, 0x4aed4419,
4785 0x2e813590, 0xbee032df, 0xa12b9b10, 0x4d4df937, 0x4cc605cf, 0x75de5097,
4786 0xfedfea63, 0xc28b2381, 0x4f86fe7f, 0xe91ce1b2, 0x199e643a, 0x7f39fd42,
4787 0xbf1834ba, 0xa0f5dca3, 0x51eb8ac1, 0xe3a4abc7, 0xf5b10bd5, 0x755c6b5f,
4788 0xaefc753c, 0xcfac9f8d, 0x69f8e174, 0xb8fc7e30, 0x5c753b6a, 0xde7c572a,
4789 0xd886978d, 0x414b96fe, 0x72c3ce19, 0x947ee122, 0x14797a93, 0xcd8841d2,
4790 0x74ed4977, 0x97ca9f90, 0x4a5d3edc, 0xf900f366, 0x6901e60d, 0x5ef1c6d7,
4791 0xfb7fa380, 0x3a520554, 0x305f5c0f, 0x221a16d3, 0x3ca0f9b0, 0x7d414c1f,
4792 0x777be257, 0xe9fdf026, 0x17b87f4c, 0xb81d39fb, 0xf1c6f313, 0x1437c875,
4793 0x85a988d2, 0x1ffd3184, 0x8f9c46f1, 0x90238a8d, 0x98f81aa7, 0x0e11c359,
4794 0xb6245979, 0xe913f87e, 0xcdbf2b38, 0x572ddad7, 0x30e1c53d, 0x580679c5,
4795 0xbe47d066, 0x08ae5da4, 0xa3f364cc, 0xbe5128f8, 0x517f84e5, 0xc79d3a78,
4796 0x103826ff, 0x4a7ad9ef, 0x5d056848, 0x7c73248f, 0xbe184c99, 0x5e265c34,
4797 0xdd3c1d8d, 0x090ef8c0, 0xe83e411e, 0x5fc1fde0, 0x9451e694, 0x245655a7,
4798 0x7802df64, 0x089270e1, 0x91b7638c, 0xd8047588, 0x5af3a551, 0x1b79c1f9,
4799 0xa8ecebcd, 0x3a78f2fa, 0xb14bed53, 0x7e70db71, 0xe2cfdfb4, 0xae2cfdfa,
4800 0xd6aecfdf, 0xbf270aaf, 0x740bddb2, 0x87c058fc, 0xa78ea6fb, 0x7c28f1f0,
4801 0x113f51f2, 0x429dee2d, 0xd616ae0c, 0x22633d15, 0xc0337fb8, 0xf4e14ce8,
4802 0xe8e1c278, 0xb29050a3, 0xd7fe0081, 0xfd353b73, 0xed34daf3, 0x7a415388,
4803 0x99c7cd5e, 0xa1fc6061, 0x9ecff39e, 0xee78cdf5, 0xee6fa8f7, 0xf7a5beab,
4804 0xe6bef6fa, 0x3e75ed63, 0xd55f955f, 0xff5ffebe, 0xf869711e, 0x52829396,
4805 0x30ccaf2f, 0x126b7ed0, 0x1dbdfccf, 0x0f5144bf, 0xf7ebfa51, 0x4af802cb,
4806 0x5832c7f1, 0xa056ddff, 0xf05ee7df, 0xd74996c5, 0x63af9331, 0x14e97366,
4807 0x86264738, 0x526496a6, 0x5abfbf3c, 0x17709b70, 0xbce8ffe9, 0xbaf3e3ee,
4808 0x3a4051bf, 0x21917fb8, 0x6ec5eae4, 0x41fe0b35, 0x09d567cb, 0xd3d088a1,
4809 0x1b4b057e, 0x3e760696, 0x3b4f6e36, 0xeaf1045c, 0x6cde3e21, 0x0c1a4a42,
4810 0x845bed3d, 0xef2957e3, 0x35dede27, 0x2ed1b887, 0xffcf2f16, 0xe463e419,
4811 0x91b921c7, 0x46c1afee, 0x31e416f1, 0xfe8dc583, 0x3037fe90, 0xdc2159fd,
4812 0x2e5047ce, 0xa4040722, 0x573e8bfb, 0xec55d242, 0x33025b30, 0x62f0ced1,
4813 0xd9a60360, 0xce043c8b, 0x412f6961, 0xa05b7f79, 0xdf0fbf1c, 0xd1942edb,
4814 0x176ce4bc, 0x6774d3e6, 0x1f7e0960, 0x3fafaf58, 0x644baf7c, 0xd4225cf5,
4815 0xc3e0367b, 0xea05cf7a, 0x7cf5bed0, 0x3ff301a0, 0xcd31040f, 0x95f3626b,
4816 0x2fe82a96, 0x11a045fc, 0x18fed1eb, 0x41427aff, 0x2f7c3cfe, 0x79b797ab,
4817 0x2dd6084c, 0x777e7939, 0x197fe639, 0x377f6108, 0xb5fde0ec, 0xb30b9412,
4818 0xb3afdd17, 0xce96b863, 0x030fc9d1, 0xe5752beb, 0x3f063aea, 0x6f5750b1,
4819 0x5890def8, 0xfdf30056, 0xe4bbee91, 0xffe0890c, 0x5cbcdfcb, 0x3b0dcfd7,
4820 0x15eae8d6, 0xae89feec, 0x4ddec47c, 0x75bbbcba, 0xeeaf2ebb, 0xca65f54f,
4821 0x5679e9d8, 0x4205f975, 0x2fdb3f28, 0xf4375e79, 0x075cb722, 0x76bca05e,
4822 0x69f87c2d, 0x5c7083c0, 0x4840f545, 0xb3fcb833, 0x3493ec1a, 0x27d838ff,
4823 0xecc82fd1, 0x3b734f54, 0x3e40dad5, 0xe0267f7e, 0xc0bafcc6, 0x0c6fcc18,
4824 0xcffcc24c, 0xdfcc5e02, 0x09bf3123, 0xf00da9e0, 0xda3359f4, 0xe9671087,
4825 0x525b5d7f, 0x923f2043, 0x32f1c68c, 0xa2e637e4, 0x3f709a5d, 0xb3a70543,
4826 0x955687b3, 0x7122a6ac, 0x288beb55, 0x9939511f, 0x4e9adc80, 0xefd6bd79,
4827 0x037f2d77, 0xfef58395, 0x0721b987, 0x258aadf0, 0x0a29c993, 0xcfcda3ef,
4828 0xfae9da39, 0x432c762b, 0x3abcbb7d, 0x6d20bb28, 0xd3fd067e, 0x0dc4d5e5,
4829 0xb6e547c7, 0x4b9eff6d, 0x99f55dc7, 0x0f80da40, 0x0107214b, 0x91b376bf,
4830 0xde58ae72, 0x009cfcdc, 0xd93b34f3, 0xee9d98be, 0x0a79e208, 0xc5710f71,
4831 0x519cdaf0, 0x7f6e7e87, 0xe825f47a, 0x3c87dcdf, 0x2ee92bfb, 0xe50d1a41,
4832 0x8a30c46d, 0xf7d80cd1, 0x78582f1f, 0xe791ec04, 0x80b7201f, 0x6bf1e73f,
4833 0xe74ecbcc, 0x4eeded05, 0x93bb0b06, 0xf36393fb, 0x1d96ff42, 0x9b1b95e6,
4834 0xe5e89d97, 0x52bccd62, 0x772854a4, 0x4ece780a, 0xf04f1824, 0x79fa6df4,
4835 0xb2f30d3d, 0x44af3df5, 0xebc02f3a, 0xc4af0e44, 0xfd42f09e, 0x5e0e3134,
4836 0x6bc37d89, 0x912bcc28, 0xf4230578, 0xebc18333, 0x79fa2999, 0x780d733d,
4837 0x4179d2a5, 0xaf0e54fb, 0xc2f09ed4, 0xbc1c6a7c, 0xd786fb52, 0xd2979858,
4838 0x0df1d45f, 0x8e8b60cb, 0xefc0d82f, 0xfb5729a7, 0xd2ca8c73, 0xfddf4f7d,
4839 0x005150b0, 0xdd40d3f2, 0x3789a4f7, 0x5329f2e8, 0x4ffaea46, 0x9756319b,
4840 0x58a078cf, 0x3b9acf97, 0x7fbed759, 0x795d34f5, 0x191103fa, 0xcb9a8bf4,
4841 0xd6f9e3db, 0x7c2f523d, 0x0728cbab, 0x35d7cec1, 0x4163c99c, 0xbd63ca81,
4842 0x3e8baff0, 0x5b17db86, 0xff436f87, 0x39789fea, 0x1fb40bc7, 0xe0f03d83,
4843 0x55f7f450, 0x13ddfa73, 0xf3be4668, 0x7c8c204a, 0x6fb71f68, 0x8738801d,
4844 0x0381823c, 0xd378df68, 0x82788215, 0x19e6dfea, 0xfceb3ce0, 0xfc13329d,
4845 0x8be69dae, 0xefc8230e, 0x3771d452, 0xa94107cd, 0x8905b881, 0x1f6dea4c,
4846 0xb7f38dff, 0x9ecf07e5, 0x1d2f7e84, 0xb44cbb34, 0x56af09df, 0xf9a7643c,
4847 0xdd98f7da, 0xfbfe2fa4, 0x63f7c92b, 0x97e62706, 0x93f97da9, 0x5f8e8411,
4848 0x00d13bb8, 0x180aa7fc, 0x07f82a44, 0x1f41b3db, 0x05ec791a, 0xfd47fc1d,
4849 0xfedd65f6, 0x230b1e14, 0x43f752df, 0x7ee84f3d, 0x8538c034, 0x56e3e07d,
4850 0xe225db89, 0x067f74f9, 0xa7c0b3af, 0xbfe59569, 0x9697eca3, 0xda6cdfcf,
4851 0xbf9ceb0e, 0xe071d961, 0x1cb767cb, 0x0bbefe38, 0xdbe3a1a7, 0xb9435f54,
4852 0xe7f36bf0, 0x53dcf07f, 0xbd7e22f1, 0x119b9755, 0x70f9dd2e, 0xbdcef6ef,
4853 0x7b53d312, 0x57b7d3c2, 0x18587f42, 0x2eaa8ee3, 0x7bdf84bf, 0xd42eb1ca,
4854 0xd539172f, 0xfdc9b5f9, 0x601d0f80, 0x8545d97e, 0x2fc812e1, 0xbdd1317a,
4855 0xf95faa02, 0x46834bf2, 0xda345ece, 0x2af0be93, 0xddea91f6, 0xc5ea1226,
4856 0x4625d23e, 0x48d2996b, 0x578a50e5, 0x2768965d, 0xf5477fe4, 0x986349fa,
4857 0x12e20abd, 0x62daa59a, 0xbf36ac69, 0xfaca58b0, 0x4d42faea, 0xdfc7c7eb,
4858 0x817d3127, 0x427f07ea, 0xf5e814f8, 0xe84f5506, 0xae703d6b, 0x0cec3ea3,
4859 0xbbaf5af7, 0x728d75dc, 0xd2e51ae5, 0x45ffca35, 0xcf29f7e3, 0x55ea66bf,
4860 0xe058bf9e, 0xd03e074a, 0x76098f45, 0xe064468e, 0x2d0d555f, 0x1adf3f0c,
4861 0x8ff9009d, 0x7d5abeb9, 0x72f8c439, 0x5cd79588, 0x788108a6, 0xd426e2ca,
4862 0x49163f7e, 0xe17c6f79, 0x1fd32356, 0x20ff5a6b, 0x73cf80bb, 0x7ce1a93a,
4863 0x4532e6a4, 0x695f4a28, 0x1bd61346, 0xfe233466, 0xef491915, 0xad8d9f72,
4864 0x8027e54f, 0xce4fc093, 0x3cc5cc6e, 0xf5f227e5, 0x8e1a93f0, 0x9f955f67,
4865 0x02f30adc, 0xf3da54bc, 0xf7905e30, 0xdaeebf13, 0xa9c20746, 0xfe80ce9b,
4866 0xed7e066f, 0x02a63429, 0xf71809dd, 0x4262dd58, 0xa356e439, 0x5eebed8b,
4867 0xbeac4fe6, 0x03f18bbc, 0x17d38d89, 0x538fc7be, 0xe3a2d8d5, 0x16f83d4b,
4868 0xff8c578f, 0xf1919f7e, 0xe2848bef, 0xfc4f4147, 0xafa2f150, 0x5b2e6b7e,
4869 0xdee8f374, 0x767deeef, 0xc6c73ee0, 0x953c7053, 0xa470aa1f, 0x38dbb9f0,
4870 0x627c27ba, 0x38412970, 0x48fb7276, 0xc98d5f3c, 0xc55edc0f, 0x81e3d9f9,
4871 0xb5adde3f, 0x38fb5af7, 0x387156c7, 0xd1040eac, 0xf51d242e, 0x5aaec138,
4872 0x6f07766f, 0x49f0c437, 0xa164d8e6, 0x9d035e62, 0x849525a7, 0x16a6d196,
4873 0xe7f02b98, 0x2af8825c, 0xfe1d24d9, 0xaf3429c8, 0x288db7e3, 0x13069b27,
4874 0xe957f001, 0x615f2faf, 0x6b3af164, 0x4b3bb7f2, 0x927fbce9, 0xb820fbff,
4875 0x6d601dd2, 0xebfda033, 0x63bfaea2, 0xca64dcd2, 0xfcf8132f, 0x72d1b79c,
4876 0xc1e6f8cd, 0xade4014e, 0x76fa89a4, 0x0cb070f1, 0x8abfeba6, 0x1c524cdd,
4877 0x20a197e8, 0xc2317662, 0x612230e5, 0x272ae8dc, 0xadcb47e3, 0x95d7a40e,
4878 0x63ee2239, 0xadb7b713, 0xc81b3b07, 0xfc848a52, 0xeac894cb, 0xb44109cb,
4879 0x4ec199a3, 0x8a7d806b, 0xda4ede60, 0xeb009f31, 0xb8f2041e, 0x4c9fd70b,
4880 0x6f412b22, 0xbedf1aef, 0x164fbe18, 0xfe02cf7d, 0x3b6cca5c, 0xd53d8029,
4881 0xf40a1beb, 0x2c10c1be, 0xcffad174, 0x5085a21a, 0xfd169b2f, 0x39a58931,
4882 0xd3e4d710, 0xff987ff8, 0xf437963b, 0x912ce7cc, 0x5721fce2, 0x5fcb6a86,
4883 0x012f3d10, 0x129ca79d, 0xba909e50, 0x09bd4de3, 0x2bf70f10, 0xb1878f23,
4884 0x2fe93d31, 0x8f4cb9ad, 0xeac721ed, 0xf70537f9, 0x79ba63f4, 0x63f2e3b9,
4885 0xd8d31fa6, 0x2797fdc3, 0x0ec1f8ea, 0x1d8d03a0, 0x11e4b07d, 0xa4355fc1,
4886 0xcabf7e91, 0x6dd6bf7e, 0x601a0cbf, 0xf8f1f77e, 0xb3d5220b, 0x22f78f3c,
4887 0xff744bb0, 0x6cd455df, 0x593bcb3d, 0xf9873fce, 0xc0f9baf3, 0xec045361,
4888 0xce1eef7b, 0xdcfb062c, 0x51e8c66b, 0x3ff5c82b, 0xfdcdf260, 0x5a331cef,
4889 0xedefba69, 0x4b9076ed, 0x9cfa724f, 0xd846a24d, 0x0f8f1f47, 0xaafaed53,
4890 0x55ca8c5d, 0x0f9be046, 0x7f774244, 0x3c1ee697, 0x1c2efa16, 0x8adfb397,
4891 0x9ad80afe, 0xb12cec2f, 0x16bb4d12, 0x679671f7, 0x45eb34ed, 0x57ad8e7c,
4892 0xd668f5c1, 0x5b15fb8b, 0x50f082af, 0xfc19fbd7, 0x787ce69f, 0x14fbe8db,
4893 0xdd7e33f0, 0x5b344ad5, 0xfbf8881a, 0x5a9bc057, 0x8d272f83, 0x00c2e3ae,
4894 0x5854d0df, 0xf2325b4f, 0x6ff8bebf, 0xf466fc77, 0xcdb71606, 0xf386a7f1,
4895 0x86fb15fb, 0xe11d8026, 0x220daffc, 0x21e7ddc8, 0xbf7e921e, 0x81343cd8,
4896 0x73bec55c, 0x2e75db8e, 0xe8095d3a, 0x911d094f, 0xbec00b4b, 0x539e4471,
4897 0x9a9eb3d0, 0x91ed0f2f, 0xb20ed14b, 0xa2388647, 0x1af71e1a, 0x993f7fdf,
4898 0x6379c1d1, 0x20e804b8, 0x04e0a2fa, 0xeed55eff, 0x5ed1c73d, 0x247123b2,
4899 0x710d2f8b, 0x08db473f, 0x908a9fd8, 0x146f1f41, 0x91057266, 0xb0cc46da,
4900 0x8f52e16b, 0x63fd34ed, 0xed57dcfc, 0x31496cbf, 0xbb720539, 0xfa0f1cec,
4901 0xc32b7043, 0x1e89b2cf, 0x33f69d83, 0x7f4041b6, 0xdba72de5, 0xaca98e31,
4902 0xbf409129, 0x472c8f65, 0x9b6d533f, 0xf81da5ab, 0x0f704864, 0x794fe021,
4903 0x14c7f0b8, 0xb28eeb1e, 0xc3fc807d, 0xb8f32fe8, 0x6fbb1a6c, 0xd0aeb187,
4904 0xa0f0f409, 0x5cf203cd, 0xbbcf0ce9, 0x205957e0, 0xfe008e45, 0x7d2ceba8,
4905 0x0e0635c0, 0xd9b0d285, 0x2442a983, 0xa56be50b, 0x4d205112, 0x86648997,
4906 0xffcfeb7c, 0x6c289cc2, 0xa216e9bd, 0xfebfefb0, 0x8de1e01b, 0x8edeb2cd,
4907 0x6fe7d619, 0x0be7d16a, 0xcdfcfa23, 0x4ff3e96f, 0xf74941c0, 0x0c2fb5f7,
4908 0x37f088c4, 0x47fe0085, 0x8588990f, 0x97eaabae, 0x2703d466, 0x9cf0d954,
4909 0x7305f8f8, 0xde47f208, 0xec08b57b, 0xb4bf954b, 0x6f01b8b3, 0xaf2825f8,
4910 0x811fa97a, 0x0dff7273, 0x8cb7b544, 0xff64b900, 0x3ed80ddf, 0x9fed3cfa,
4911 0xe0f8ffd6, 0x947a5fcf, 0xf9f8ffb6, 0x1210497e, 0xdf87d594, 0xef59aabb,
4912 0x41ba1e1f, 0x2161ff3f, 0x664abe7d, 0x2f0bfafa, 0x187e2ac8, 0xdba5df18,
4913 0x17f5c695, 0x907f9697, 0x6e20fd45, 0x8182e400, 0x4455efb1, 0xbf46afd3,
4914 0xe1e9c89f, 0x019dc05c, 0xc88a63e7, 0x85cfeae2, 0x7a0348de, 0x1bc768fa,
4915 0xe74f4069, 0x4fd04b03, 0x6767bd55, 0xd5e79c12, 0xf0e1bfcf, 0xaedf7a40,
4916 0xdc82c6a7, 0x0c21bcf4, 0xd3dfa0f3, 0xf8477be0, 0xf4598e57, 0xc91db9fb,
4917 0xd17def88, 0x30a8457b, 0x7c0e7b43, 0x8ee87c55, 0x383272a3, 0x9de3181c,
4918 0x0fba5dfe, 0x780d9b55, 0x7c2aa65f, 0x038677f7, 0xa2366c1d, 0x8f7aabdd,
4919 0xbe3ea091, 0x7bb456ed, 0x813eed55, 0x8dfec771, 0x5e5718a5, 0x61af1124,
4920 0x664cba24, 0x75ae7a40, 0xb7ec039f, 0x926e7f55, 0xefc81725, 0x78a3fdfa,
4921 0x548c7180, 0x069a28f2, 0xb2cf494e, 0xa9bff022, 0x57ae7bdf, 0x5f7e3edf,
4922 0x78d5915e, 0xddaf9225, 0xc97af8df, 0x37688253, 0x5cb25ea9, 0x7d500f17,
4923 0xfe0651ba, 0x4a0e3f1a, 0xfa739a90, 0x017f0835, 0xeb917f3a, 0x51ce5439,
4924 0xc3cfa2e8, 0x3cb106bf, 0x80952b9c, 0x1bfeb047, 0x851744c8, 0x3234d547,
4925 0x032cd209, 0xe42c7bc1, 0xefefe615, 0x7a0473a0, 0x237dd8e8, 0x84bab7da,
4926 0xc33f5df6, 0xb7c8edfe, 0x07119c3a, 0xb6544dc4, 0xe2ee319a, 0xf2320be3,
4927 0x37e1658d, 0xdc6f101c, 0x145992f1, 0xf1f5b0a9, 0x8362e49e, 0x37e7f003,
4928 0x4e19aecc, 0x571d962e, 0x7b9a2fd1, 0x00f8b78f, 0xafcf49fe, 0x273d94ff,
4929 0x7d678064, 0xe98b9e32, 0xbd8575c9, 0xedaafdc5, 0x42bae452, 0xb3d3c817,
4930 0x5aefdc6d, 0x72f80b9f, 0x06e197d1, 0x6054a979, 0xf4480efd, 0xed7e849e,
4931 0x924bd6cc, 0x076c32de, 0x70653a7c, 0xf852762f, 0x945e25cd, 0xf28ee60b,
4932 0xa48740c9, 0x96fdc59e, 0x51222449, 0xf80cb039, 0xa3cc08ea, 0x59b65efc,
4933 0xb9a2f8c0, 0xe775184f, 0x69e1c400, 0x1a4e57d7, 0x124adfb1, 0xb37cb4c6,
4934 0xf802bcbe, 0xa5578534, 0x95e0fcc2, 0xf0718c3b, 0x5a3ea089, 0x930bfbbd,
4935 0xfd751c76, 0xfaea217f, 0xd1e5973c, 0xfd45fd4c, 0xf70129be, 0xd8c8ffd9,
4936 0xe65f380c, 0xf8e0f699, 0x985cfc55, 0x7e58ea4f, 0xa00c8922, 0xeba3cfe3,
4937 0x9e607382, 0x918e8242, 0x92309f2c, 0xdf93c7ad, 0x0eb03d73, 0x36f277ed,
4938 0x56aaafdb, 0xd61c3221, 0xf20de743, 0x5b47ac37, 0xb3af9aaf, 0xaefd377a,
4939 0x7690ffb5, 0xf7bb5fac, 0x5fae930b, 0xe7a0cf6e, 0x7dd33110, 0x37cdd758,
4940 0x71b4c343, 0xe1bdaa23, 0xbac78724, 0x0267e7bb, 0x720d3dbd, 0xd8071658,
4941 0x8127aa18, 0x032c676f, 0xb7c742ac, 0xc79ddcdc, 0x2ce5a2f2, 0x76b4c83f,
4942 0x54fe86c2, 0x32fa310f, 0x3329ae41, 0x68438f78, 0x37c54ece, 0x29c744d4,
4943 0x12d93d93, 0x1e4f75f2, 0xb09659da, 0x6474fff5, 0x5ebab0dd, 0xbf7518e4,
4944 0x08e10bd6, 0x641d43c6, 0xbd7c41f2, 0x4fc62671, 0x1fb68e12, 0xdd173e07,
4945 0x5a11e547, 0xc1f0a36f, 0x6de3b071, 0x5645cbbc, 0xdd067cd0, 0x1b77e01f,
4946 0x502f5205, 0x4bda8cb8, 0xa3d01be5, 0xd4378ef7, 0x4cdd70d8, 0x6dd6b06e,
4947 0xfa47fb03, 0x0123f943, 0xb930ef5f, 0xdd741e70, 0xe5a34d0f, 0xb983cb19,
4948 0x384bff60, 0x0ede6a1a, 0x8b70efe7, 0xa74bc61b, 0x6127b1b0, 0x7fe700da,
4949 0x023c2906, 0xc5319574, 0x88ec1235, 0xffac1ceb, 0xd0f0d154, 0x46539054,
4950 0x28d27cb2, 0xfb8ed9e2, 0x49c716b3, 0x30499137, 0xf20ef83f, 0xb3d6ed17,
4951 0xc4349107, 0x5d4275f6, 0x3e9f8c21, 0x7064a588, 0x8bcbca06, 0x9eaa7cb8,
4952 0xf7f59f6f, 0xea3f0024, 0x3f01f7e2, 0x201279b3, 0x1b1c8c8e, 0x9fed6a26,
4953 0x0345fd6a, 0xdf50e93c, 0xc124597f, 0x287fe464, 0x5e67fa5f, 0xff857b42,
4954 0x1a824cb2, 0x9cbfec3e, 0xd777cfa4, 0xb1f6c34b, 0x4a12167a, 0x839eadee,
4955 0x11fd7484, 0x7f2d7f7d, 0xec24f5e5, 0x77698c8f, 0xe9d91c80, 0xdb3e476a,
4956 0x46831215, 0x1174f7aa, 0x9dc1f182, 0x6d5df64e, 0x265339df, 0xa2679411,
4957 0x40474fd8, 0xb2630881, 0xf413f5a9, 0x1eb7561f, 0x35ef8129, 0x7ce30da4,
4958 0x1256c26b, 0xdbffc5ec, 0x970b0011, 0x3f29fce6, 0xfdd4ed8a, 0x9037b588,
4959 0xb38fd690, 0x52222da2, 0xeab75a5a, 0xc00a2bd7, 0xd3947704, 0x2b37f04d,
4960 0x72d1b73c, 0x23a3a883, 0xba6ea8eb, 0x275f3242, 0x061d181a, 0xe262bb7f,
4961 0xaf3c9a6d, 0xf83edddf, 0x291309bb, 0x602a8ddd, 0xf55d9fed, 0x972c6fef,
4962 0xae807c62, 0xd76bdb3f, 0xbcb895e4, 0x6b87e68d, 0xf2b8cef2, 0x8cf2b894,
4963 0x567f7cb8, 0xc91ec3bf, 0x1ca9b836, 0x13f7eab7, 0x3a4fca24, 0xa9b32332,
4964 0x309e4f04, 0x226133bc, 0x6a8f8dc4, 0x5a79c0f3, 0x59b82adb, 0x5f830fb8,
4965 0xb9e19bad, 0x832eddcd, 0xaa3adf7f, 0x7688b8ed, 0x7209c12a, 0x27bc2da6,
4966 0xe7687982, 0x330bb4d2, 0xfc3aa4fd, 0xb3ebb601, 0xe9117cff, 0x87fe4d7c,
4967 0x765aef58, 0x8faf9274, 0x6e2bef83, 0x3be0b770, 0x92bd026a, 0x77bf9144,
4968 0x992ff9ec, 0x7c633fdd, 0xf3d333ab, 0x43adf206, 0xb7cb5382, 0xa41f30fc,
4969 0x0e5c65e7, 0x935c7062, 0xb886517f, 0xb787f78d, 0xa9c703be, 0xcb27d175,
4970 0x73fb1e40, 0x20d1d9cd, 0x1f2d809f, 0x217af4f8, 0xd6f18664, 0x7861a18b,
4971 0xc866adff, 0x7a05d111, 0xf016fb7c, 0x75574417, 0xda4ffc22, 0x284007db,
4972 0x9755c5fb, 0x7db53e59, 0x5dc7ec0b, 0x009b7f0d, 0x0e4f1ef7, 0xd2201f68,
4973 0x8355a5fc, 0x487e6227, 0xf7c816fb, 0x3f2c1c53, 0x81807dbc, 0x0921cfb6,
4974 0x76ff6113, 0x8abf193a, 0x3967bfe7, 0xf7e755ff, 0x29cf7f4e, 0x66a90b80,
4975 0x1c0b7dfc, 0xed9f94cf, 0x73b538ec, 0x9d9fdd17, 0x9fc8cc4b, 0x10bc6429,
4976 0xe1ce938f, 0xf20ee78c, 0x8df50953, 0x926b384c, 0xcf68fb62, 0x7f21736e,
4977 0x0f6ea1be, 0xb3e9d79c, 0xff3f900b, 0xac99ec87, 0xfdd2c6a4, 0xfad29a36,
4978 0xe3271593, 0xed1106a7, 0xda8fe99e, 0xda78fe51, 0x0561d6cc, 0x1b534afe,
4979 0x7c2b8fdf, 0x4c4c571d, 0xdf24b91f, 0xdacdfd81, 0x950cf946, 0x240966db,
4980 0x309c80a8, 0x81394655, 0x3341a3aa, 0xdc5537cd, 0xddd27180, 0x335ad2fa,
4981 0xd0a9bfce, 0x26760993, 0x9a693f55, 0xd44cc9ea, 0xdb4d65c8, 0x67cab958,
4982 0x5e69729b, 0x12102e73, 0xad9779c6, 0xbb424dcf, 0xf3eec4bc, 0x743b5fac,
4983 0x573c1afb, 0x9b3ae1a7, 0x68664312, 0x2fffc2a7, 0xf0c93dfd, 0xbef57efd,
4984 0x7507df28, 0xd30ac9dc, 0xec0cca87, 0xf1527e3c, 0x44cb3ae1, 0x39a208cf,
4985 0x4d03279f, 0xa448e068, 0xfdf0d1f6, 0x8c7843ff, 0xa3fdf586, 0xf1daf8f0,
4986 0x84fc71c5, 0xa0bb8df2, 0x67259aff, 0xf30cdc79, 0x5df0a9bf, 0xe98c442f,
4987 0x77b06f8c, 0xd077e804, 0x3e4c0abb, 0xe753b42f, 0x1ad1fb3d, 0xf5d4d794,
4988 0x60787f58, 0x9d99dc12, 0xc5fe795d, 0xecfdb49d, 0xf775591f, 0xa4be5581,
4989 0xae46bde2, 0x11eec618, 0x4fbb29ab, 0xe80a7208, 0x3aeaed77, 0xc4264f24,
4990 0x18afaf8b, 0x609e8228, 0x828ff805, 0xb7432efb, 0x9c18132f, 0x9caa9e60,
4991 0x08bb8843, 0x2953b3d6, 0xf97d86ae, 0xa05e2952, 0xf071b2a4, 0xa75e097c,
4992 0x03d78dfd, 0x7aeae779, 0xfc72610d, 0xefa604a6, 0xd0f10249, 0x8dffcdf9,
4993 0x811adb71, 0x13e21f03, 0xb0bb30b6, 0xc357972a, 0x79f74ee9, 0xe7e3973e,
4994 0xc17e3973, 0x1deea306, 0x3e908a82, 0xbcd89a4f, 0x523eb9aa, 0x9fb0da45,
4995 0xbd7d66aa, 0xd82faa6a, 0x83bf701d, 0x8690f1ca, 0xf9eae5f5, 0xc2f96fe1,
4996 0xa0f77fa4, 0xa361f711, 0x09f1c999, 0x8fb93d23, 0xb5fc7f01, 0xffcde511,
4997 0xc2a2fbe6, 0xf1624061, 0x8b5f00c3, 0x9ff84441, 0xec394916, 0x95c0676f,
4998 0x93307831, 0x02f5a76f, 0x9aaf35bf, 0x361f01cb, 0xffcea22b, 0x64628f78,
4999 0xcce5c37e, 0x4fbd1e9e, 0xc8133b46, 0xffbd5ac1, 0xe7d54539, 0x10ff72d7,
5000 0x129a33d3, 0xa9bedc99, 0xe9077049, 0x2b4d277c, 0x5ff800af, 0xc021699c,
5001 0x3d72e76a, 0x746a42f3, 0xfaadc031, 0x76bb4bbe, 0x7c37d011, 0x74be022f,
5002 0xc7ecd18a, 0x967fd172, 0x0fb3fe00, 0x7cef8c43, 0xfdc0eb48, 0x9dab6098,
5003 0x4f1355c5, 0xefda3ce6, 0x6ee9d5a9, 0xe3533b88, 0x641d4e49, 0x46f5cbfe,
5004 0xf3dc096f, 0xfa63ee0d, 0x574687c3, 0xeb23dc36, 0xd011caf2, 0xd744cbbb,
5005 0x7b2025d6, 0xaaf6b61d, 0x5a9ff85f, 0xfeae7180, 0x23dfa5ca, 0xfdd3d157,
5006 0xbd3d7a2d, 0x61b34493, 0x07ca9b5d, 0xfc742386, 0x6e61d6ce, 0x40cad666,
5007 0x93ad4be3, 0xd54d3dd5, 0x7187bc3a, 0xbdf088c8, 0xff91fede, 0xf0fc7ed1,
5008 0x684bf06f, 0xef681fed, 0x7a43dbd0, 0xfabed9e6, 0x7e674d5f, 0xeff2b892,
5009 0xb093becb, 0xf93fb50f, 0x0825c9eb, 0x37d228d7, 0x3e7a6469, 0xa144779d,
5010 0xb46f4fed, 0xdda77f23, 0xf9fdbde1, 0xbe053654, 0xd194b393, 0xf486f55b,
5011 0x4837606d, 0x57eac89c, 0x768a186f, 0xfedcb184, 0xea40df3b, 0x133ba015,
5012 0xa1390069, 0x696ae4cc, 0x9c63c4d7, 0x5bd267b9, 0xbcb45f40, 0x0dabca1e,
5013 0x82fcdeec, 0x8da2b6b6, 0xecc22f30, 0x02cde5c3, 0x78c53881, 0xdad115fb,
5014 0x3560a889, 0x80cdbc36, 0x55d83f4a, 0x55df63f2, 0xbf79ee3a, 0x3d26efe5,
5015 0xbf2a82dc, 0x7abd31f1, 0x9ff83a70, 0x901c7a54, 0x48cc95e8, 0xe074ae07,
5016 0x3e0c67a7, 0xe02c97b4, 0xb82b1bf7, 0x478eaf9e, 0x3be30df9, 0x281fb70a,
5017 0x2d70aecc, 0x47daa3fe, 0x0f403b54, 0xf294b3be, 0xf37d119d, 0x0aea421d,
5018 0x80f84ed1, 0xd2740dcd, 0xfe70ff83, 0xba53eea6, 0xd8d0f8cc, 0xd10321a5,
5019 0x6497b9c8, 0xcd3697cf, 0xa3ffe2b9, 0x826eb8a2, 0xb40c97bc, 0xbe365c81,
5020 0xf70a91d2, 0xcebf98dc, 0xdb3c46da, 0x662df7e8, 0xfed02f2a, 0x90b871ee,
5021 0x0cc8647f, 0x97928c0f, 0xa2f2d214, 0xfb9436e2, 0x09c4a9a3, 0xc6decefc,
5022 0xa762dffa, 0x3b4246ed, 0xdbba77c6, 0xa2dea42b, 0x2afc5f69, 0xe9725fbb,
5023 0xdfed1da0, 0x734b1297, 0xbe748f80, 0xa77e476a, 0xba53bbfa, 0x8958d5df,
5024 0x1e1db9eb, 0xd5854a45, 0x3d03f715, 0xfb93088b, 0xd86277b1, 0xf46358b9,
5025 0xe9ff00e5, 0x9644d778, 0xe08b7ed3, 0xbc54a231, 0xef0257b7, 0x2ebed536,
5026 0xca486400, 0x8216772b, 0x5864d91d, 0xf7428f74, 0x34b0c4a7, 0x576d08fa,
5027 0x04e6c033, 0x9cc4c293, 0x7de7fd3f, 0x5ed1ff34, 0xaba7de23, 0x266139d8,
5028 0xa2fad1d8, 0xa2fbf8ff, 0x7975bf74, 0xbcbabfba, 0xbf9f45bf, 0x814f6cd7,
5029 0x36942cfb, 0xd8cf70dd, 0xb73baa64, 0xf4d7ce8d, 0x354dc99a, 0xd9b37211,
5030 0xe81980f7, 0x071e8c5d, 0x3a729978, 0xe17c8046, 0xc044fd6f, 0x559250f7,
5031 0x072f80ff, 0x9992e7e8, 0xf3efb3c1, 0x9eec289b, 0x6967551d, 0xc36d94da,
5032 0x597a68fd, 0x6f8c0908, 0x045d194f, 0xf7e130e7, 0x97183c4f, 0x265367e5,
5033 0x4cfefc4d, 0x68437ed3, 0xded79c19, 0x5c27bc72, 0x856bcf4b, 0xb87177e6,
5034 0x8b47d557, 0x53445ee0, 0x3061a4d2, 0xc90be92f, 0x0abbfb0b, 0x17c8d13a,
5035 0x3fe2cdcb, 0x115a3f76, 0x2d89efe2, 0x7b873a07, 0xf8e9e39b, 0x0cf8bee3,
5036 0xe8532ee3, 0xc9cfc030, 0xee376656, 0xfda21652, 0x43ae6fda, 0x44b8d5bf,
5037 0x60b5d709, 0xa0242d80, 0x9f20991d, 0x3932260c, 0xcb41611a, 0xffb986cf,
5038 0x0b4e0e3a, 0x9ab930b6, 0xbbe033ec, 0xc1400b31, 0xd5fbb902, 0x700f18a9,
5039 0xc9a7f376, 0x5b6e01e3, 0xbb0270ef, 0xccbdf5a2, 0x8369e78f, 0xada4bbf7,
5040 0xbd0172df, 0x6262db1f, 0x765448f3, 0xfb8f7ec1, 0x837280c2, 0xc81f1224,
5041 0x67b24d0d, 0x6b91d018, 0x8012cef3, 0x59a9d9eb, 0x517fd622, 0x37184e20,
5042 0x7c1a4971, 0x5e48205f, 0xfdfa3f46, 0xa26bf753, 0x05c99939, 0x7f782b86,
5043 0x4db4d8fa, 0x3e3dcf18, 0xc6f7f367, 0x8d3b7f42, 0xd2846f78, 0x3e703dc7,
5044 0xc0f5d0d4, 0xbcb66a7c, 0xb38cc693, 0x628a4484, 0xa3fcdbef, 0xaab26074,
5045 0x07975c78, 0xf2c16c7c, 0x3bed3cba, 0x78f03d1e, 0x1b9ba533, 0x166078a9,
5046 0xaf2097c8, 0x35ea4ff7, 0x1e5e293e, 0xc54af555, 0x6d3b3c4d, 0x08f3d768,
5047 0x329d3f94, 0x4e47c84b, 0x27ac6599, 0xf3616dfd, 0x3f105cef, 0xd02dfbeb,
5048 0x60f10e5f, 0xea2b853c, 0x0ee2a62c, 0x69cf0080, 0x9fc599b2, 0xf51f73d1,
5049 0x44a9f5a0, 0xffd1aef7, 0x3a51fde5, 0xb2f0077e, 0xc72bddf3, 0xd9b5ae01,
5050 0x8f40231d, 0x0cfe5ff0, 0x56b65eed, 0xb9b4f766, 0x0d9e64bd, 0x992a7be8,
5051 0x83e3105b, 0xcfe3377e, 0xd1baebf1, 0x63f16462, 0xc7ec5129, 0xd7f4656a,
5052 0x4df6f5c4, 0xf7a82c4b, 0x99094a6d, 0x955fd261, 0x573f54ce, 0x2a63b705,
5053 0x7b415e3b, 0x4e09090e, 0x2e296bf0, 0xe55d2746, 0x3fcf11b3, 0x882831da,
5054 0xd1e3bdf9, 0xf1db65af, 0x8040c35c, 0x83f30b53, 0x0eeddcd9, 0x3b47df58,
5055 0x7d60394e, 0xb80c3be5, 0x27d0f2ee, 0x620af369, 0xf049bd74, 0xfaf3c15d,
5056 0x46b59d0a, 0xc768fb4f, 0x6d7369a7, 0x730a4f4c, 0x706f417b, 0x2f1952f9,
5057 0xc65c2858, 0x751d9839, 0xf7c453dc, 0x386de232, 0x4f6f6b5b, 0x6af3b0b5,
5058 0x0dc9859c, 0x7ad0d6e3, 0x7c618788, 0x1ebe29cf, 0x57a32079, 0xf8fc6d3b,
5059 0xb4441be7, 0x26ac56a3, 0xff3d6768, 0xf46c81fc, 0x903cee6b, 0x5f53473d,
5060 0x6f8c3f8d, 0xf1616d9f, 0xa7f1a41f, 0xe20d251e, 0x7378d83d, 0x2007cabc,
5061 0x3b86909f, 0x1e38fa3c, 0xbd4d130a, 0xa7c40dae, 0xefd58a0c, 0x01dcff2a,
5062 0x5a736a71, 0xb413110d, 0xa70678f7, 0xebcbbc80, 0x2f77f7c7, 0x45a123c7,
5063 0x5ac93d40, 0xfa3e4510, 0x1134f9b5, 0x4d3e5a6c, 0xe324f7f7, 0xf0e3d1d3,
5064 0x19d813ee, 0x6b933ce1, 0xf5c8126d, 0x5e182b69, 0xa2207f45, 0xc435ddfc,
5065 0xf9522f52, 0xb0cace45, 0xb14aff01, 0x01acb8b0, 0xbf58f959, 0x1a679efb,
5066 0x4999e7bb, 0x8a7e30ea, 0x1f51db38, 0x38863fee, 0x580d0e41, 0x41911c98,
5067 0x830c1bdc, 0x7a3c9820, 0xf10151ea, 0x8e7c03c4, 0xa9ea0a88, 0x3f185f14,
5068 0xfa33e477, 0xf952f0e6, 0xa02ad0a8, 0x92db371c, 0x862bf5c8, 0xa3c2d757,
5069 0x3c62ffd9, 0x778ea05a, 0x12e478bd, 0x5be1f5c8, 0x1fc2761f, 0x845fb828,
5070 0xf0a771fb, 0x3628a67e, 0xb880af7c, 0xf1dd1d8d, 0xcd9fb464, 0xfd04de54,
5071 0xf62bb541, 0x62ea515b, 0x76b6e07e, 0xdface790, 0x7c5cf052, 0x05cb6c5c,
5072 0xcede3a79, 0x11367748, 0x533801ce, 0x1f94bd61, 0x5797fb30, 0x9d71fbc6,
5073 0xe21b8f01, 0x44880607, 0xcfdf3e02, 0x35ef8b90, 0xdd380bf6, 0x59dc182b,
5074 0xbb1e631c, 0xb12b5c0f, 0x075942fb, 0x1772c912, 0x5f4cc7c8, 0xcb8eface,
5075 0x78b52e0d, 0x225346ff, 0x7ea987b3, 0x69ecbef7, 0x9f4f41a4, 0xcbad5daa,
5076 0x537e174e, 0x0659ce0c, 0x85049f3e, 0x41ee4fdf, 0x35c00ae7, 0xff510c6d,
5077 0x4b3e4036, 0x14fe37cd, 0xae957bcf, 0xbd9d7b55, 0x736b9bc0, 0x7abb9213,
5078 0x8be031dd, 0xb8e7efd7, 0xfdd5e57f, 0x025dff1c, 0x9e7a0e7e, 0xb4c39776,
5079 0xe6ab39e9, 0xae12203d, 0x21cac7b2, 0x11695ece, 0x2575fb78, 0xde5c4877,
5080 0x3ee7f1c2, 0x3caaef06, 0xf1ba266d, 0xe293f3b4, 0x629087fa, 0xdfad4b9b,
5081 0x5bfa1138, 0x83e79237, 0x5f83d41f, 0xbea369e7, 0x6f29043f, 0x029a990f,
5082 0xc9f07fd6, 0x1a9fc741, 0xe1ef3b1c, 0xa97807fc, 0xf7aafee7, 0x44de34a6,
5083 0x3f3ab2c7, 0xf50778c5, 0xf4a7f6fc, 0x24e22f7e, 0xff5fe3e7, 0x761e841d,
5084 0x261693ca, 0xc90096df, 0xf9003d51, 0x17a97fb2, 0x9ca825e3, 0xb7cc21f1,
5085 0x338eddf3, 0xe7796847, 0xf78fcfb4, 0x7d6e3c03, 0x31e83678, 0xfa03b7e0,
5086 0x501b37f1, 0x055a55ce, 0x462d6f86, 0x7f1517a4, 0x7f1c9d2a, 0x7f788312,
5087 0x3090e9b0, 0x5445ec1a, 0x9bbecd3f, 0xd5b165ee, 0x31c70173, 0x533fdfea,
5088 0xeccad953, 0xe2fcfe56, 0xffd0798d, 0xf9c0810e, 0xc3ff26bf, 0xbfa8b9b4,
5089 0x4f36907c, 0x65a2aed3, 0x691f8b1d, 0x470af636, 0xfa606ad9, 0x1e7dc1dc,
5090 0x43e70be0, 0xca4b1618, 0x906ad0a5, 0x45cbcb57, 0x8546efd4, 0xbe43ef4a,
5091 0x2026533d, 0x5c587787, 0xd3cd1e6c, 0xe42f1083, 0xbf81ffa7, 0x7e77936a,
5092 0x3347ca29, 0xd5c41b15, 0xce2fcf9e, 0x5795fb44, 0x061c0276, 0x926537bc,
5093 0x149ef80b, 0xadb4b8c6, 0x2091b6b5, 0x83efadd7, 0x63693ecf, 0x782f5cfb,
5094 0x7e67df83, 0x5bb5a271, 0xf930b4e5, 0xe4cac32e, 0x867bf541, 0xb79dc995,
5095 0x0026db05, 0xda961c3a, 0xfaf720ad, 0xd013e789, 0xe6d7894b, 0x0f7089da,
5096 0x129ddea3, 0x4d3da170, 0xfc7f6949, 0x4dbf2826, 0x223b38c2, 0xe3033fb5,
5097 0x894eae76, 0xfc850bdd, 0x6f680523, 0x1beacc7b, 0x14e3a562, 0xf3b27971,
5098 0x10859de0, 0xe1ce38d7, 0xe824c9fa, 0xed0973e7, 0x8a9ee33a, 0xf8004db6,
5099 0xd9903e7d, 0x08e895b9, 0x9376b9ed, 0x9e93ad95, 0x92ef286f, 0xfbf237c3,
5100 0x1d9eb40a, 0x5a16f1ba, 0xb8de4153, 0xfd18f458, 0x24694c6c, 0x7d549f80,
5101 0x9282bb40, 0x872025e2, 0x4a96084c, 0x271cb718, 0x71e04c87, 0xf4a4881d,
5102 0xfbc7317b, 0xe1777421, 0x558a2dfd, 0xc7265ff5, 0xaeb792e4, 0xa3e090cc,
5103 0x8a88af2a, 0x1399ed0f, 0xc6085a67, 0x1e8cafd3, 0x9e2ec117, 0x0a7af942,
5104 0xf160cbde, 0xb32ff9a2, 0x466120fb, 0x3ffeddb7, 0xa8fd1da9, 0x7e56ad93,
5105 0xfc33d7ae, 0xb7186d21, 0xb0900940, 0xd6cf68fd, 0xfd5057de, 0xf27f6a86,
5106 0xad8f6672, 0x7c17f6e1, 0xdf9696f9, 0xb2ed556d, 0x467e75cb, 0xf0bedc75,
5107 0xc6aac2ab, 0x804b4453, 0xd507a31e, 0x4a4f8a78, 0x8cfa2f00, 0x5778e0a7,
5108 0x78f572db, 0xd195bf0a, 0x4f1d37c9, 0x913588f1, 0x11f44bc5, 0x471f114f,
5109 0x911999d1, 0xda4b5ed0, 0x7d04eeb7, 0x7e84c5bc, 0x6f2d29db, 0xcbce11fe,
5110 0x43090a29, 0x5cbc56dc, 0x5f4d35e1, 0x75def80e, 0xc056cce1, 0xef7775c3,
5111 0xb03f3377, 0xd7885e5e, 0x7cabb60f, 0x1b73cb97, 0x1fa7d7ad, 0x29bef5a8,
5112 0xcbe54eb9, 0x5187ae7e, 0xb9c072fa, 0x23d383b3, 0xd1c41250, 0xdd6dcbc5,
5113 0x1c9c7ef2, 0xd19eff11, 0x9d6f69a4, 0x61a47bc1, 0xa87100b3, 0xde0919af,
5114 0x63ee0dd3, 0x85b56dfa, 0xc3ea93f1, 0x2ca9fdec, 0xe3ed1793, 0xf22315e4,
5115 0xf9e57f0d, 0xfd114497, 0xdc00af04, 0x27e5a653, 0x5faefd40, 0xd50e901b,
5116 0x85b690f7, 0x2a74fc98, 0x94c88c5f, 0x79c1b7ce, 0xa13ce30c, 0x3d741bf7,
5117 0x31f18fd9, 0x5ae837ee, 0x9706fccd, 0x6033e3cc, 0x330ecaf3, 0xb7197ffb,
5118 0xf14aafff, 0xae8332fd, 0xc64ff16b, 0x1e75dda3, 0xd65a61f1, 0xc71bb7a0,
5119 0xbfccbdec, 0x78af0554, 0xcc05fbb3, 0x8fb1a7df, 0xae523bc1, 0xce18a906,
5120 0x5ce25ca5, 0x15d97c0e, 0x16fdd0a4, 0xbbf9eb4d, 0x802882c3, 0x4ead213c,
5121 0xac7ec0b1, 0x012717aa, 0x45eb05bd, 0x5bb88f7c, 0xd7e7e00e, 0x29ffce25,
5122 0x8e3042c8, 0x77f3d69a, 0x96fed57b, 0xa9023111, 0x9574b028, 0xdbd49a53,
5123 0x57f6a8b9, 0xc653ac6f, 0x4034be83, 0x25ecbb44, 0xe01333d9, 0x8f29297a,
5124 0xbd645c40, 0x1261aebd, 0xbf1c472b, 0xb17a8e64, 0x1312dbfc, 0x092b88d8,
5125 0xfcdbd9f8, 0xdb878edc, 0x3838c6bc, 0xe3f3d9c6, 0x88cb3ee3, 0xa0e6686f,
5126 0x6f92719e, 0x69733e73, 0xbfbf2e4d, 0xaeaee0c0, 0x067f597f, 0x4b007137,
5127 0x9e280e07, 0x303ffb09, 0xa04d8651, 0xd223b329, 0x07fce095, 0xef053b7e,
5128 0xb7cfc513, 0xc023841e, 0xbdecd5ab, 0xff3aaf8f, 0xddff79f8, 0xcce9c69a,
5129 0x5f780193, 0x3df194e6, 0x17d96baf, 0x705cb972, 0xd6a1fe2d, 0x07f806fb,
5130 0x1b578bd3, 0x13adbc78, 0x97bc08f9, 0x04a77f08, 0x9e08aef7, 0x79d5a1df,
5131 0x06d5aeb0, 0xc27e1f7c, 0xef9e1b74, 0xfbd987b5, 0xdb4b3576, 0xad9ce1b3,
5132 0xf7c76e2d, 0x0de1e36b, 0xfe5495b3, 0x49cdeb43, 0x1c6ef821, 0x79fbd069,
5133 0x3cb3fa7a, 0xd3e03645, 0x37aec8c6, 0x654338e9, 0xd7c858df, 0x02ee8d2e,
5134 0x91e3b579, 0x5e404af7, 0xd26f539b, 0x2792a7c5, 0xd2227ef4, 0x65768490,
5135 0x5effa4d2, 0x5dae39be, 0x2351bf0f, 0xd97ae3e2, 0x7be80c37, 0xd3f9839c,
5136 0xef88a549, 0x01db75fc, 0xe1ce1a9e, 0xeed3cee7, 0xee7d03ef, 0xef67ad2f,
5137 0xf77aef59, 0x2fec02f7, 0xbe6ad7dd, 0x7df617bf, 0xb7f60f2b, 0xf2b7cf63,
5138 0x1bd77f60, 0x3f403d1b, 0x0f9f153b, 0xefa73cfc, 0xa39ca2f0, 0x0b5c45c6,
5139 0x275d172f, 0xe6fa2e5e, 0xe7aaf2f0, 0xcaa6c05a, 0x5ced5f49, 0x9ead3f83,
5140 0x218af87d, 0x34bf4668, 0x3d98ffc3, 0xf077fcec, 0x0a2cb95c, 0xabe8f7e0,
5141 0xae5c51bf, 0x104850cc, 0xc54513ec, 0xe8aed8ed, 0xdc809173, 0xf179caa4,
5142 0x9f09f870, 0x4f36f3ff, 0x5f879c02, 0xce5aeed7, 0x4fa128eb, 0x43b9fc99,
5143 0x6bbb3370, 0x1dd5c598, 0x9d82752a, 0xd9885cf5, 0xb1f76b5d, 0x422bea77,
5144 0x5df0446f, 0x09c156f3, 0x8ec541fa, 0xeef01c0f, 0xae4e2690, 0x448ce819,
5145 0x9deceff5, 0x40729d0b, 0xb79d1bbc, 0x6b78e415, 0x7a06544a, 0xf1172da8,
5146 0x295ab3dd, 0xb5bcf18a, 0x241dc429, 0xf5ea5f20, 0x6c2e352d, 0xba465793,
5147 0xdecad4d9, 0x7d934ca1, 0x0f11fdb9, 0x6dfbe3fb, 0xb7edfd2a, 0xf800fe79,
5148 0x7ad3f31b, 0x8b576c5a, 0xc32ff91b, 0x617fe636, 0xccd97fe5, 0x6e3502e4,
5149 0xce8ff544, 0xf3eef1e7, 0xf83bbc79, 0xf81a236d, 0x9b56df82, 0xd5b6fd57,
5150 0x88322f10, 0xe5b56df9, 0x8d687edd, 0xae5b56df, 0xe889178d, 0x93234df8,
5151 0x310b0d77, 0x25d2864e, 0x579163c6, 0x88ced505, 0x74a7e9f4, 0x0c6464b0,
5152 0xf0fdd57f, 0x12b87f97, 0x3cfcf3e2, 0xf01ab2ee, 0x61c60477, 0x5fc04c46,
5153 0x355f14c3, 0x4b6a2efc, 0x7d7374e4, 0x37e8c8f6, 0xedf1df4c, 0xe3c7573f,
5154 0xb3aead74, 0x02ad5d7b, 0x75b8c3a3, 0xf189ebc5, 0xcf5569f6, 0x4bdf16bb,
5155 0xdf1f5fb6, 0xabfdeb53, 0xfdb65ef9, 0xbef7c39f, 0x47fffb29, 0x3034c6ae,
5156 0xe87b3e05, 0xd083df87, 0xad8312a4, 0x4c9477fb, 0xae3fe1d7, 0x437062d9,
5157 0x21cd4ddc, 0xaaf21bbb, 0x7fde323f, 0x94f64958, 0xfde3c800, 0x5710d588,
5158 0xfedae831, 0xb77b62c4, 0xfb573d5f, 0xb151785e, 0x61bf5f9e, 0xa7d934fb,
5159 0x02e2d3c1, 0x82f7e02a, 0x24148ab7, 0xa9f638da, 0x7eb7e676, 0x9fefbf83,
5160 0x88069321, 0x6eda7893, 0x14467bc5, 0xa62e306b, 0x6e9dead8, 0x9afc0d1f,
5161 0x83d9efc1, 0x0b8812f7, 0xc618d67e, 0x1ac13efb, 0x5727de1b, 0xff6a23ed,
5162 0xa97ea96f, 0xcd73e06b, 0xcd73e275, 0xf1cf8c37, 0xe3ab17ed, 0x61dfaf5d,
5163 0x06918503, 0xb3f1e3df, 0xf17d76af, 0xef765581, 0x91d23b72, 0x5eb9ef07,
5164 0x11e8ff2f, 0xf1b92987, 0x4dc41d5e, 0xfc559c42, 0x74f7a87e, 0x6b70b954,
5165 0x97a1fb9f, 0xc57eb707, 0x3c96b8fd, 0x0de2a4f8, 0x8f4f7ac1, 0x3e81e4f7,
5166 0xeccecabb, 0x0ccd9b2e, 0x0c0b372f, 0x13e07b1f, 0xe2a3efbf, 0xf5fb01d5,
5167 0x7ad43bd9, 0x78fe6aff, 0x2d7c2ed4, 0x69fc077b, 0x886c90f1, 0x7d767be2,
5168 0xfe9ec7f2, 0x5977162e, 0x517a86dc, 0xef8090f4, 0xf6f3ab33, 0xd63b31b7,
5169 0xd45c39ef, 0x1cb8fbef, 0xfcf0e398, 0xf10a9ec1, 0x8f028a49, 0x59028c3b,
5170 0x2f28e40e, 0x0da9378b, 0xda8fb8b3, 0x70e304a5, 0xb511fbd4, 0xc809532d,
5171 0xbecd0b6d, 0x55fb433f, 0x8682d9ef, 0x4fa3b004, 0x75a72023, 0x37f2cbbe,
5172 0x401f7d9b, 0x3b697fb9, 0xa69bfdda, 0xa138c79d, 0x5d3f2fa2, 0x3a5df609,
5173 0xa40bb45f, 0xd3f7f498, 0xc7c60e1d, 0x50ead4d4, 0x7b41ebe1, 0xfb950778,
5174 0xa7f2de40, 0x5f609c78, 0x56cded50, 0xe1da1b57, 0x6732f76b, 0xad81915f,
5175 0x9fda3c87, 0x8ef6d1f9, 0xe415fc2f, 0x9042e6c3, 0xb7de8b57, 0xe3a8fda1,
5176 0x138c2c91, 0xbbeacc78, 0x1f6af80c, 0xe40bba15, 0x0e3a1ccb, 0x7b1dadc8,
5177 0x79842aee, 0xe0a17d77, 0xccecbaba, 0x24f5d0bf, 0xcaf88999, 0x665dd1ed,
5178 0x9f022786, 0x666ad76f, 0xba1e0a9f, 0xdd03bf91, 0x38368f6d, 0xd1ecc746,
5179 0xa5407cf1, 0x08fbeeff, 0x1ff414b3, 0xbd61fcab, 0xeaa39d91, 0xeece77f9,
5180 0x3c16f1e2, 0x2a75aeae, 0x79e0d78b, 0xf8554f1b, 0xe3bb6f3e, 0x9cf3ac1c,
5181 0xdec7fa5d, 0xe24cbec3, 0x2fd8e7fd, 0xe36939c4, 0xdfe0add5, 0x53897b01,
5182 0x37b2bc46, 0xa1dfe610, 0xf9f20578, 0x09b6d16d, 0x839d7409, 0x01b7229b,
5183 0x165f0fbc, 0x53a0bbd9, 0x92f78b7f, 0xde360413, 0x57da27a0, 0x8afb050f,
5184 0xc36fedf3, 0x9d1abad6, 0x5b92e0c5, 0x870ef668, 0xd52241b8, 0xc578c3e5,
5185 0x3c5918ef, 0xda2b21df, 0xabb29a09, 0xbb691273, 0x684cf7ce, 0x03e789af,
5186 0xcb241a6a, 0x606f8e31, 0x0ed01fcb, 0xe82bdf6f, 0x93a6a6e0, 0xf7e6361c,
5187 0x6095b609, 0x296dc9ac, 0x0e6e77ec, 0x7f041fbd, 0x5f1ab4bd, 0x46f52486,
5188 0x7572088f, 0x7b411970, 0xa72690e4, 0xc395fb08, 0x0eba44e3, 0x1f08cfff,
5189 0xddaa9f9e, 0x64a9843d, 0x7a095f6c, 0xfdacb495, 0xc7ec20f6, 0xb6b144de,
5190 0xd68bfa00, 0x12b27c32, 0x5a739f38, 0x95bf2d06, 0x9c1a73e6, 0x7aea3fe8,
5191 0x0de30ab5, 0x439d7483, 0xa167597a, 0xdce5c583, 0xa520e3c8, 0xfc115643,
5192 0xb85ad2d2, 0x5341440d, 0xd29671ef, 0x129c43f6, 0xc38e7de2, 0xd4f00b37,
5193 0x5902f9ca, 0x9c7f4162, 0x6d78625d, 0x8bdef25f, 0x55bfcf10, 0x1d4fef66,
5194 0x34e37c3d, 0x96addfb4, 0xc6ab5ed0, 0x74e02e51, 0x47de13dc, 0xe0725e31,
5195 0xbf303fa1, 0xfa0b1d0d, 0x3f0c8c97, 0xf829d5a4, 0xc87fe07e, 0xfd0b8c3e,
5196 0x80c47d76, 0xe9e728fe, 0xaeb92667, 0xebc4b7ad, 0x891ccb29, 0x622e295f,
5197 0x3d9be399, 0x3fdbe24f, 0x55f78eae, 0xd7a210f5, 0x63e87acf, 0x5c7572f1,
5198 0x0ee4befb, 0xf542ee35, 0x504f1177, 0xcc526f17, 0xbe8a21c7, 0xef0b6abf,
5199 0x50a3c78f, 0xf205c439, 0xd70ada4e, 0x8ebf8832, 0xdfa098fe, 0x09978d46,
5200 0x9738b316, 0xbde0a8a0, 0x88d20cab, 0x48fd3271, 0x1ed01044, 0xd3b6e2c6,
5201 0xb6865e21, 0x8818ef5b, 0xee216ffd, 0x41f20306, 0xa4abbe17, 0xfdd055c6,
5202 0xd3243a41, 0xc13f1e64, 0x566b37f0, 0x70e2085a, 0x9f7edcfd, 0x7f1f2b35,
5203 0x3f135567, 0x33feecc1, 0x7d4f882d, 0x10aa53de, 0xd6253df9, 0x1710d36f,
5204 0x4d7ff3de, 0x693e6bb5, 0xe2e3ed67, 0xaa38542c, 0xfc2a1671, 0xf14c7bd4,
5205 0x79314c70, 0x57bc02df, 0x7dd425e3, 0x0d8fdeee, 0x55d82ecc, 0x1cbbe221,
5206 0x155d7f6a, 0xdc83679f, 0x626adc50, 0xefd712f8, 0xaefbeea6, 0x67c63321,
5207 0x96bd7df3, 0xdfbeaa1c, 0x23bf9475, 0xd7bf8c75, 0xc21665de, 0x399f8006,
5208 0xc9381b3a, 0xee4784f6, 0x5d817b84, 0xdc3668f6, 0x78dcdc2b, 0xa7cc24ff,
5209 0xfe424f46, 0xc3ff84b5, 0x5ba243f2, 0x89e19ee1, 0x1e58b3a7, 0x908b2e70,
5210 0x49848e33, 0xe07f82c1, 0xe3d73a5c, 0x022e1a77, 0xfb486b1c, 0xd3b436ca,
5211 0x146973f0, 0xa26463e3, 0x44ecc429, 0x13ffdc2e, 0x631dec99, 0xbdc0fe5b,
5212 0xdfde506d, 0x5a2df684, 0x627bf88e, 0xee5678c8, 0xfa4dfb62, 0x029c59db,
5213 0x13d33dff, 0x1fd1e3b9, 0x4df8035e, 0x462b85e5, 0xc740989f, 0xe1b420bf,
5214 0xee27593b, 0xe00161f8, 0x8ffd85eb, 0xe2b9060e, 0x77f7b94e, 0x72731ee1,
5215 0x7ec8c239, 0xa34de5f7, 0xf9409acf, 0xb3ad1fc3, 0xff69124b, 0xcbc79333,
5216 0xe0ef3089, 0x51eef8f3, 0xc4bfdf2a, 0x4bee4c19, 0x2015e89c, 0x3363f17e,
5217 0x1f54b3a3, 0xe2063dfb, 0x3ddc219b, 0x12d7235c, 0xc4113bf6, 0x7b804ae7,
5218 0x68eff108, 0x6b5e12dc, 0xf7f73900, 0x780ce881, 0xfefd5552, 0x38f7a107,
5219 0xc604828b, 0x5c19a6c7, 0x141f01c3, 0x29cdf1b1, 0x2bc6c4b7, 0xfbf17048,
5220 0x70a375c5, 0x51ba86dc, 0x28f4c7a0, 0xd072d1b7, 0xe5a09e93, 0x97297bc3,
5221 0xd67afb78, 0x938ef35e, 0xa974e01b, 0x2fbc03f4, 0x04eb38b4, 0xc27647be,
5222 0x0ef03c48, 0xfb93304e, 0x0739e8f5, 0x273c7dfb, 0x3b4fc591, 0x40704c37,
5223 0xffdb107e, 0xfd0848bb, 0xb06653bc, 0x21df597b, 0xb4edf56d, 0xfa199dde,
5224 0xcbb963df, 0x277fcfa5, 0xc29f9f5f, 0xebbe07e3, 0x1eff7fd6, 0x0f804a89,
5225 0xffa31fdf, 0x441797dd, 0x0be0094f, 0x2f8c27e5, 0x2aee3c0a, 0xf9c20845,
5226 0x2c81e37e, 0xc61a9ef5, 0xf5c0bdb3, 0x7fbf3f11, 0x91aa6701, 0x8586e3ae,
5227 0x1bdc9dec, 0x93928833, 0xf92bfc04, 0xf07bbe08, 0xa729f711, 0xf4789bc0,
5228 0xd713a97b, 0xf419e2af, 0x1f7c3b75, 0xe2e0cf9d, 0xd2538321, 0x418eefd8,
5229 0x6b2309d9, 0x84b1fc1b, 0x7d684e7c, 0x3e2c6ff3, 0xf184bc62, 0xd7ab0277,
5230 0x4ff86665, 0xfefc524f, 0xe21ede53, 0x27c89caa, 0x4abfdc2d, 0x8be85df0,
5231 0x78d8d2a3, 0xfa8b0f1c, 0x5bc01629, 0x7cbb5df5, 0x1bf6e127, 0x7069a64a,
5232 0xe794103e, 0xfd54bc54, 0x3c380348, 0x7f327e28, 0x1f872671, 0x06f7f091,
5233 0xcfda8932, 0xadc61374, 0x04bafcf1, 0xde2a6f46, 0xb5ec7fae, 0x5f00a737,
5234 0xc03f5c12, 0x3bb2ee7e, 0x74f9bd61, 0x804999ac, 0x78d829bf, 0xf449e707,
5235 0x247927bb, 0x8c5d8798, 0xb09a1b18, 0xbf7f307c, 0x4fa4fa6c, 0xfe1a4866,
5236 0x61adfb45, 0xfdf55afd, 0x459ba3c2, 0x68337e9a, 0x7e9a49bf, 0xf2c2689f,
5237 0xbfe5fbbe, 0xe7e92147, 0xaf8fb6a7, 0xf3f5ea4f, 0x7c7dabec, 0x14f7f53d,
5238 0x4df87326, 0xf329e356, 0x640f71f5, 0x7e615b8c, 0xc39c7d6c, 0x8edf1c9b,
5239 0x306dff5b, 0x09250be8, 0x2844a70f, 0x1a524c3d, 0xf408dbeb, 0xd0fa461b,
5240 0x802ff5d0, 0x7e652e2e, 0xb6fbbf80, 0xd989e078, 0x97a519d0, 0x7ba309dd,
5241 0xe7c547ce, 0x3c5179ee, 0xf1543c06, 0xdd9e7e38, 0x30bdfc78, 0xa16d7206,
5242 0xaaa407f2, 0x9d48423c, 0x0d70eb80, 0x2283ad88, 0x87528961, 0x22b37ff3,
5243 0x33bdf388, 0xff8c19f1, 0x3be49319, 0x799af302, 0x3dec27d3, 0xa1d28c93,
5244 0xf9d10720, 0xfd484d1e, 0x355f377f, 0xe1dc796e, 0xbd82373b, 0xe3ee9bb4,
5245 0x5fed5ce8, 0xf234d395, 0x2af73b15, 0xf2be5545, 0x19642900, 0xe57cb832,
5246 0xacd678c2, 0xf10dcb80, 0x8af91aaa, 0x44d547c9, 0xeece07bd, 0xa060fced,
5247 0x987abe5e, 0xb76ebc60, 0x271a557c, 0xede3cd5f, 0xc42092a7, 0x93d936c5,
5248 0x805e2c42, 0x162d39ce, 0x8db4dbff, 0xb74d8dc9, 0x82419cb8, 0x33d31672,
5249 0xe87bf166, 0x6bde4cb9, 0x77c98fba, 0xbaea1ce3, 0x6b78fa2c, 0x133567ee,
5250 0xb8b12f2a, 0x99abb40c, 0xa5d97d9d, 0xb53576f4, 0xf202ffde, 0x007f0832,
5251 0x00007f08, 0x00088b1f, 0x00000000, 0x7de5ff00, 0xd5547c09, 0x73b9f8b9,
5252 0x64cacb67, 0x109848df, 0x424e3b08, 0x875b3612, 0xe22948b0, 0x3cb888b0,
5253 0x4240b21c, 0x3eb44196, 0xc33fedad, 0x0d220222, 0xc168d46d, 0x2a14180e,
5254 0x0431a0d8, 0xa4587049, 0x141a87d0, 0x2f1f682d, 0x48145840, 0xad88a0c6,
5255 0xbefbffcb, 0xef726e73, 0xf6b42264, 0xfa7fb6ff, 0xef7397b3, 0x6df3be59,
5256 0x39ce5be7, 0xd78deec3, 0x1ec658b1, 0xacc630b4, 0x98eb458c, 0xb19436b3,
5257 0x96eff0ef, 0x95e5e7ae, 0x6289e63a, 0xa31574ac, 0x47d7e5e7, 0x7a83cfa6,
5258 0x4c8c7697, 0x66e783cf, 0x92d433b3, 0x50e158cd, 0x2fa18a7b, 0x7b46f963,
5259 0x9b19933a, 0xbeb45e64, 0xcc9eba19, 0xd393f516, 0x5b09fb18, 0xcf074c74,
5260 0x48ce9151, 0xc8673fac, 0x287a2967, 0x0379f8b3, 0xfd8c611c, 0xc28f675e,
5261 0x19b98cf7, 0x718535c2, 0x4398a6b8, 0xf870f2bd, 0xa5c340f7, 0xfe8c8196,
5262 0x1c7183be, 0x4b6f6726, 0x1155630c, 0x67971fb5, 0xa35cf631, 0xe2b6e6c9,
5263 0xec1496d7, 0x11deb18f, 0x043086e7, 0x543ce185, 0x39e814f0, 0x4cb2d13c,
5264 0x040bf4f0, 0xc65e630f, 0x68e0ba72, 0x94ae8437, 0xb1e0a97a, 0x00d17eb3,
5265 0xc7be24a7, 0x06895ab1, 0x6a5383f3, 0x1257e3fc, 0x33d38fd4, 0x63265877,
5266 0xea97981b, 0x1ce75efd, 0xb3c6e381, 0xb8e1894a, 0x112b6c2b, 0x96e0dd4f,
5267 0xbf30c901, 0x1ec977d9, 0x0ae60c13, 0x7ace1f09, 0xd4fb3d61, 0xba7f1804,
5268 0x2af67f18, 0xac0884c7, 0x78e25d37, 0x00ffc2f0, 0xfbe219fe, 0xa9b2c6f4,
5269 0x3198e00c, 0x13ba70c1, 0xa66ff83e, 0x0181ba65, 0xc2a6b39c, 0x7bd7737b,
5270 0x61d2209c, 0x2cffd28e, 0x6c39bb6d, 0x387267cd, 0x10191696, 0xd5ee735f,
5271 0x09669f7e, 0x42173e8b, 0x077c076d, 0x60603af3, 0x79f68f34, 0xe609b3cc,
5272 0x82cc56f1, 0x3347f7f5, 0x43b7e036, 0x7fe86533, 0xcd716c62, 0xf4bf283a,
5273 0xbf2a60dc, 0x83cf7b15, 0xf3fbf147, 0xa09e54e9, 0x6e504683, 0xb3ce99ff,
5274 0x9cd01529, 0x5494d773, 0x9040ff18, 0x467ef7e8, 0x9d83e3ef, 0x5ea1d355,
5275 0x99bef0fc, 0x04d3e0cb, 0x0aede323, 0xde9ff7f9, 0x9ce54614, 0x191eacfb,
5276 0x6c109cba, 0x30f7d375, 0xaa09b6c9, 0xd130c91e, 0x53e361f7, 0xccbef7f9,
5277 0xe7df851e, 0x23fb5185, 0x0b5e2199, 0x47f2f78c, 0x01fbe883, 0x0eb9b3e9,
5278 0x595b5120, 0x52e91ea8, 0xe336689e, 0xc940c873, 0x3df0083b, 0x5f8c5221,
5279 0x353de7c6, 0xca226b73, 0xdf5c84cd, 0x6850c75c, 0x670e6897, 0xfe1f1137,
5280 0x8879f90c, 0x34aadc6d, 0x5f16afe4, 0x150f9a8a, 0xf8574f3a, 0xcf96826f,
5281 0xc51e7e40, 0xfa9f0af6, 0x87c2a7f3, 0xea0b3e1a, 0xb97f33e2, 0xd7009e57,
5282 0xb18f924a, 0x97721f20, 0xe38e747c, 0xe3fe2727, 0xf8bf24f6, 0xdca2c527,
5283 0xc2777f88, 0xd0f24b57, 0xb9e9b99b, 0xcb83e501, 0x8708b3cb, 0xc56cd751,
5284 0xdb247df7, 0x33c20b60, 0x0c7666ca, 0x0a372eeb, 0x783ac97c, 0x2e1dd991,
5285 0x3943d3fc, 0x45fe7589, 0xb8e0e747, 0xb3b43bfc, 0xb82ec8b3, 0xa4adfc60,
5286 0x7870569f, 0xb88b4836, 0xd09763bc, 0x5768b94f, 0x41b7ccae, 0x0678df3b,
5287 0x2ffa8778, 0xc4967ec4, 0xfe18dddb, 0x82b87995, 0x4f81ee41, 0x611d9966,
5288 0x1dd39846, 0xb724f911, 0xebf73277, 0xb38f8011, 0xc2136706, 0xae643c77,
5289 0xed7e1191, 0xf757a146, 0x74285f20, 0xc7f4e052, 0x7a0f794f, 0xfe1e7fcd,
5290 0x57a2e978, 0x133e0273, 0x2b2a22d8, 0x79e1bdf3, 0xae5e0ff6, 0x69bdf983,
5291 0x147c9df0, 0x6fcdebe4, 0xeb3736cc, 0x20cdf382, 0xbc3d12eb, 0xd992ff77,
5292 0xb3e00736, 0x051f8168, 0xb32e772e, 0xcebeb19b, 0x8a9659ec, 0xe06af674,
5293 0xcfe88fca, 0x7f174c58, 0x5eeb31c5, 0x2afb3154, 0x3d56b6ec, 0x57a487ad,
5294 0xcf50c2d8, 0xab9f6866, 0x99c4e5e7, 0x50a59eb1, 0xdce8f76e, 0x3c6f1806,
5295 0x347375e8, 0xefe74fbe, 0x38230b59, 0xc20b3147, 0x90011559, 0xbbaaf7c2,
5296 0xd1c03dd2, 0xd95bfeac, 0x7ddf041d, 0x0fa4c1c5, 0xc16032aa, 0x83efc2cb,
5297 0x896efbe9, 0xd62ee38f, 0xd355b8d1, 0xeaa8feb9, 0x53b8f16f, 0x54ceb271,
5298 0x8daaf7e4, 0xd04884f6, 0x5b328923, 0xa47a0b54, 0xf0ca152a, 0xeec65d8c,
5299 0xf4c47d43, 0xc3d3e1f6, 0x78fbf0ba, 0x11deb8d8, 0x84b71fc0, 0x96fe75f3,
5300 0x2af9ccb5, 0x29b563d6, 0xd57587d3, 0x00008a8b, 0xd4305eb0, 0x596efe83,
5301 0x6286f50d, 0xac2f507f, 0x83763d7b, 0x68a7c476, 0xac608c47, 0x9f11d858,
5302 0x8299dd6e, 0x9b27c476, 0xa9e4a677, 0xd8945fea, 0xbfd71c1c, 0xbc656f7d,
5303 0x66ec67ca, 0xa0926f18, 0xf98724fb, 0x50eb8494, 0xe77b44fc, 0x1a7c85fa,
5304 0x0235bf61, 0xef9061f5, 0xb47ba445, 0xf90e77d1, 0x6261bd8a, 0xa3ae199b,
5305 0x1a5d72be, 0xf7876faf, 0x1bc8efe5, 0xdb7e0357, 0xdbfe3862, 0xbe041976,
5306 0x2dff9e5b, 0x0c34af94, 0x3c61ab60, 0x0231bc17, 0xd71cbbff, 0x853d702a,
5307 0xbfce333f, 0x57112854, 0x55d98983, 0xfc1b60eb, 0xc5d99457, 0xd04ced2f,
5308 0xe88421b7, 0x1b372e5b, 0x75caff91, 0x70875d92, 0x59ec1c2c, 0xa7e97526,
5309 0xe8af4512, 0x132972d8, 0x262cede9, 0x9827bcbe, 0xfdf0966d, 0x80c5f4e9,
5310 0x9af352af, 0xa18f5c66, 0xd70901de, 0xb407a41c, 0x53ed885f, 0xbcb3e3bb,
5311 0xad54e00e, 0xb4dba5f7, 0xc6642f70, 0x0784efae, 0xd7cbc937, 0xc414e706,
5312 0xb730596b, 0xcd4b2e43, 0xf03f0839, 0xf017b79d, 0x2649afa9, 0xc0c426be,
5313 0xbe8a79f8, 0xdc7ce6a9, 0xb3c7d55e, 0x09e7be04, 0xca35e5ba, 0x0b3c135e,
5314 0x5a7bbce3, 0x2d4addb0, 0xfbc74b1d, 0x3952ea0e, 0x1ea38e1e, 0x4dc152af,
5315 0xa7054e7a, 0xa25cbddc, 0x7d45eef7, 0xc63f3fe0, 0xeba935be, 0x4ab689dd,
5316 0xe709f236, 0xf495667b, 0x0797d066, 0x4ca15d05, 0xe62499f3, 0xf5f23466,
5317 0x14ef9fdb, 0xd08eaefc, 0x8eba3971, 0xbe412dbc, 0xbcbeb98e, 0xb3fef529,
5318 0xdff56de4, 0x06ec6f29, 0x8267c1d7, 0xf8083b98, 0xd8ca5ab3, 0xfab27a8b,
5319 0x465b6636, 0x37ebb55f, 0x088673ac, 0xc035fd7c, 0x85987403, 0x9d7906ff,
5320 0xad3f7d1d, 0xfc97607b, 0x9cd9f516, 0x776ec201, 0x2424bb70, 0x9b19f38b,
5321 0x61fd3cc0, 0x1ca2610a, 0x23d9b932, 0x1eb91f03, 0x006765ce, 0xf8fb311f,
5322 0x32f5f2fb, 0xe51375d9, 0xa865d8bf, 0x659431db, 0x5cc80582, 0xd53f4417,
5323 0xa633f512, 0x24fee371, 0x6e4c4728, 0x7016464e, 0x6674bc3d, 0x9c0208eb,
5324 0xd058b1e8, 0xdfe1f163, 0x67c5bd50, 0x7d827979, 0x57942f60, 0x799921d7,
5325 0xa1c761a0, 0x2f2c7a99, 0x28b125d8, 0x104cf718, 0xd501a397, 0xc955663a,
5326 0x304f20e3, 0x75f8aab3, 0x4d4896c8, 0xa26d5879, 0x0d4dfea6, 0x33df357d,
5327 0xdf3583bc, 0xd4ca1c47, 0xc79bb394, 0x3c8fea68, 0x8f29ab9e, 0xa9a2996e,
5328 0x0cc2f63f, 0xbe47f94d, 0x99f535bb, 0x103cdedb, 0xe82050f0, 0x8a0ff8af,
5329 0x5ae5bafe, 0x2c3da69e, 0xe8095ec7, 0xb15fc85a, 0xc80b3582, 0x2d07193f,
5330 0xc896fdd4, 0x8da20e6b, 0xf5a95856, 0x6b54164f, 0x1b0dc5cb, 0x5609408d,
5331 0x2fbed1ec, 0x0f2da2d9, 0x43a79e88, 0x011b3abe, 0xf820c9fe, 0x428b1447,
5332 0x2ec9eff9, 0x44efa7f1, 0x00758fe1, 0x7e8098df, 0x33dface9, 0x7d234737,
5333 0xdf03cc0d, 0x7e05b03b, 0xf5c1be07, 0x03d0e3a3, 0x8523e43a, 0x3278fede,
5334 0x1ee96bc5, 0x3dd2d564, 0xee96a064, 0xdd2d3661, 0xd2d28d7b, 0xa5aec23d,
5335 0x2d64d47b, 0x5a1c63dd, 0xd1cdc7ba, 0xa9c13dd2, 0x91527ba5, 0x8bc9ee96,
5336 0xf3ef74b4, 0xa9ae96b0, 0xbe5a85ee, 0xc503e3f0, 0xb95b4b4e, 0x8e9eafd8,
5337 0xe0fcd4e9, 0x40ca9a28, 0xfcaff4cf, 0x7fffa6b9, 0x45a43f36, 0x92353f0a,
5338 0x7e477e45, 0x645fbd86, 0x46ff7776, 0x7f6a6bd1, 0x65d39f42, 0xefa4f67f,
5339 0xd3cbd9ba, 0x47a09c78, 0xdc9ad97b, 0xf5272f65, 0x982797cc, 0x4bd689bb,
5340 0xf08746b6, 0x70e165dd, 0xa357c15c, 0xd59bbb19, 0x13dfb01a, 0xc0146750,
5341 0x03e7027b, 0x9acbdfe3, 0xe65cfde9, 0x5993a7a3, 0x63ccf88c, 0x30167a36,
5342 0xe8a73d07, 0x1e22b79c, 0x392dcd4a, 0xceaf6fa8, 0x42527a3b, 0x21448ea0,
5343 0x2f23dfd0, 0x4ea75a6e, 0xd999cc57, 0xd6b18fda, 0xb44ce70a, 0x16e33ba7,
5344 0x568d6676, 0xbc6f2de1, 0x7a8f5034, 0xa1b60e56, 0xa777943d, 0xde6cf644,
5345 0x3739fc97, 0xfe43af92, 0x2b0f65cf, 0xfe14ab78, 0x1e43f707, 0xbb0ab48e,
5346 0xc943399e, 0x7059b3be, 0xb8fe805d, 0x9182ff3d, 0x82582eec, 0x2e80d7f5,
5347 0x4f4e24db, 0x4dda2ba4, 0x7cccf4c3, 0x9843ca0d, 0x27ccfc93, 0x7892a0f4,
5348 0x1fb1833f, 0xa0dbda17, 0x75234a02, 0x8e394e34, 0x3cd4f007, 0xaa20cccb,
5349 0xe98126ac, 0x9afb4207, 0xf12ca225, 0xbce1fe32, 0x454cdfc9, 0x4d2b6d78,
5350 0x4858af64, 0x4ccd923e, 0xe3dc91c4, 0x493ef0dc, 0xed090d06, 0xbfc01bd6,
5351 0x6b942488, 0x2198c3e6, 0xfaf99ce2, 0x934c157e, 0x51f8539d, 0x0a2f7c26,
5352 0x1dbfdeb4, 0x9595edc9, 0x40efc715, 0xcdef297a, 0x84b3377a, 0xf7825ea2,
5353 0xeb31b92a, 0xb0f11d99, 0x533dc2a2, 0xc8d9ff5d, 0xf1e7ea48, 0x4e2d8bde,
5354 0xdf723ef8, 0x720428a2, 0xd9739067, 0x10a1658f, 0xe9458962, 0x069ad46f,
5355 0x1ec3fb99, 0x919afd19, 0xd4e7f5c7, 0x2dd1a471, 0x0bd8f2da, 0x0f42b2da,
5356 0xc177f376, 0x82650728, 0x00f14caf, 0x195eaa97, 0x67c0f63a, 0x0fdcf165,
5357 0x84c1be63, 0x1b90a377, 0x0de49d53, 0xc130f902, 0x0a61925c, 0x9ccc0c2b,
5358 0xedeb7480, 0x6e5da0b4, 0xd0ebd44c, 0x2ff2603f, 0xf800ce6c, 0x78a69e53,
5359 0x7eb555fd, 0x17ea03f9, 0x48d86bb0, 0xdff11236, 0x41e02f09, 0x1a3a7802,
5360 0x46ae36e2, 0xcdcc9c78, 0x613603cb, 0xb3fea7b9, 0x7a59becd, 0x0b6cc110,
5361 0xbc3fc67f, 0x447e9674, 0xa3af7af7, 0x64e3075d, 0xd93db8eb, 0x8e5cde9d,
5362 0x6bb3e93a, 0x01646c81, 0xb0d553e8, 0x7fd4e3ff, 0x25793e9c, 0x51e22ba9,
5363 0x6fc092ee, 0xcd698787, 0xf8009612, 0xc75aac2e, 0x092e3f90, 0x8f325c38,
5364 0x24d7b1c3, 0xb5e8a7aa, 0x10022c97, 0x875a1af3, 0x62f04407, 0x0eb72f7a,
5365 0x6bd2f2e5, 0x2fae88bd, 0xf1474efe, 0xa3cc41b8, 0x610cf9c3, 0x8c3efa5e,
5366 0x26f950b5, 0x67281514, 0xdbf12b30, 0xbb23e608, 0x2b5cf411, 0xd972b9ea,
5367 0x2820bbf9, 0xbe764e5f, 0xe84e7a44, 0x4fc174fd, 0xaf7e8ae9, 0xddc7fbd6,
5368 0xf8a48d3e, 0xad0b6f4a, 0x54ce4223, 0x3af82674, 0x7f91448e, 0xe768e209,
5369 0x544db4e5, 0xc688303e, 0x587c1429, 0x8d88ec98, 0xc5ebd154, 0xf5336b8a,
5370 0x7802f92a, 0x5bbf28ec, 0x4d66822a, 0xa397bd50, 0x32071e38, 0xa18fd5df,
5371 0x2175f9ff, 0xe047b436, 0xf97ec68d, 0x4729c90f, 0x5b97bc01, 0x9a3af5ac,
5372 0xf50ea567, 0x24efd962, 0x33c01cf6, 0x66b97180, 0x7035e2fd, 0x9848a96d,
5373 0xf9f40135, 0x0fdc917b, 0x1c7cc971, 0xe28433b6, 0x8cc98531, 0x853f4385,
5374 0x7c91a7af, 0x0bd0c40d, 0xcc32b1c2, 0x8c2f7683, 0xdd95151b, 0xf1ff1e1d,
5375 0x35df43df, 0xb733f49b, 0x1ef543bf, 0xdd9973f4, 0x7bc7556e, 0x19bb0b56,
5376 0xe39213fc, 0x3b9fd160, 0x7aff7197, 0x84fb8f30, 0x296ae6b2, 0x62f5e7ad,
5377 0x9a651a20, 0x014c02f5, 0x36ce5718, 0x16ae5c93, 0x47acc472, 0xe18fe8ad,
5378 0x3a184673, 0x8f0e9cfd, 0x1cfbb187, 0x24fd7a2a, 0x3f0baf8a, 0x6a78e289,
5379 0x077b7337, 0x2a19f5e3, 0x31af387f, 0x251bec9f, 0xec2edfbe, 0x9503f6c9,
5380 0x27e8c1b9, 0xbe388a57, 0x058a9fb0, 0xfa682d2b, 0x4ad78e4d, 0x3e91587d,
5381 0xfe7de2f9, 0x535dad4a, 0xf649c5b8, 0x24ecf5cf, 0x09c514c0, 0x49a4edfd,
5382 0xd96f4251, 0xefc60658, 0x3b49accf, 0x307a8c18, 0x1e305995, 0x9abf249f,
5383 0xf11428b1, 0x871cace0, 0x4f543df2, 0x67afeb72, 0x1a87041e, 0xe245b9e9,
5384 0xe7f774f4, 0xd92db4f1, 0xb2dcefdc, 0x7f5a63b7, 0x58cbe7e8, 0xdda52f8e,
5385 0x6a06b197, 0x38e828f7, 0xd8cb5f7c, 0x6e7e40e4, 0xc977c091, 0x7a8b2096,
5386 0x8dab2a7d, 0x0d5d94d0, 0x7af51609, 0x2c28f640, 0x4c146caa, 0x7e2ba721,
5387 0x72d0d653, 0x768ac430, 0xca017381, 0xbfc1fb49, 0x3a250f86, 0xff5072f8,
5388 0xf9c7183d, 0x02b6e113, 0x9f743b3c, 0xffd355cd, 0x80bd28d1, 0xffa7af9b,
5389 0x2d765c30, 0x1e87975c, 0xe1c29d8b, 0xd5c239fa, 0x8b1d3de6, 0x8cb805f4,
5390 0xe476b86a, 0x3f9ff8f2, 0xa1fc9e9e, 0x88f564f0, 0x87df35a7, 0xc0c61da7,
5391 0x74126cf0, 0x6e80f97b, 0xfac027b2, 0xcfc849b4, 0x1aef0c3f, 0x6b6dfc3f,
5392 0x15618d9e, 0xe1137780, 0x9635be2f, 0x7f021672, 0xe04e22b5, 0xc6fa12ce,
5393 0xfd03ba06, 0x7a468fba, 0xead40f50, 0x2c54d459, 0x96d814e7, 0x46af3cc0,
5394 0x5da0fb38, 0xfe21eae4, 0x7f8091f2, 0x7014a247, 0xef881ffe, 0xf5e48f7b,
5395 0x89ff75c1, 0xf28626e3, 0x09ebe0af, 0x1339ad4b, 0xe6fa37fb, 0xf59cb0db,
5396 0x1a1ad9b9, 0xef1d7fa0, 0xf27e57ff, 0x3caff4a1, 0xc81a8ddf, 0x01d247e3,
5397 0xfb209419, 0x9ac7cdd5, 0x7f9cc3c7, 0x9d27a595, 0x79e30ffa, 0x79fe36b9,
5398 0x762c7bd9, 0x778be71a, 0x4b97df51, 0x876fc367, 0xbdf24bb2, 0x97f31433,
5399 0xd7cd2746, 0x6d8991f5, 0xbce7600c, 0x9942f821, 0x057f329f, 0x151fb0ee,
5400 0xee0091f4, 0x5a2613b0, 0xf5103e0c, 0x97a07595, 0x5e71a3b0, 0xacdc0eb4,
5401 0x6ca071e7, 0x57f7d13d, 0x1c50c6a3, 0x27c88768, 0x291b46fa, 0x870fe95e,
5402 0xff8f9a21, 0x9bf7b5c4, 0x8d3f62fb, 0x33e78a06, 0x4cfc4b7d, 0xdbd717e0,
5403 0x9427877a, 0x8ef266f8, 0x4763a450, 0x753c0b78, 0xa76a06d1, 0x7287bd43,
5404 0x8c9e4d71, 0xc8fdae7a, 0xc55916e7, 0xccb472e7, 0xb9ac6be3, 0xbff42c79,
5405 0x30599336, 0xd62a1cbe, 0xad23d0df, 0xe87f0845, 0x249b9fa8, 0x4af6fc55,
5406 0xadda8994, 0x6d62fa35, 0x09ab9fd0, 0xf78a051c, 0xb1b118b7, 0x85970782,
5407 0xeb3ca1e3, 0xe866e800, 0x4760d1a7, 0x2b68e578, 0x7700a7d7, 0x1e0fbc3d,
5408 0x1f25b9f4, 0x78c167bf, 0x87dabb7d, 0x833d3859, 0x439e61b3, 0xb3de5f91,
5409 0x97b3c014, 0xdf081cc4, 0x3f5cd183, 0xc455702b, 0xfc02fd71, 0xf114321e,
5410 0x7ca3ac9a, 0x66fae3ea, 0x96e3dfc2, 0x8c25967e, 0x79c76ef0, 0x299b46f9,
5411 0xed1d56ee, 0xf9c6898c, 0x1e1cd818, 0x8c766cf7, 0x32587c27, 0x07002356,
5412 0xf0bd9106, 0xc38bc133, 0xb21cf358, 0x168cb20b, 0xf594475c, 0x8ede8bf9,
5413 0xcd37685e, 0xd076e68d, 0xd742b7f9, 0xc0abbae0, 0x2c02b677, 0xb957633a,
5414 0x8498e6d0, 0x9ccf9978, 0xe78e502b, 0x551e0157, 0xc0de7efc, 0x16bc2dfb,
5415 0xaa51bccc, 0x36eea376, 0x6bc2bb62, 0x760bcce1, 0x5e20f9f7, 0x5f187cef,
5416 0xf18ac6cf, 0x33fc156f, 0xea07fa33, 0x7c9f9b31, 0x8bf3f86d, 0x8d8f5c79,
5417 0x4995bc45, 0x7bb4462d, 0xabf98ed7, 0xb3e9ed11, 0x4de61615, 0x4679beff,
5418 0x9c6aaf31, 0xccd77ace, 0x3ca51f34, 0x5b24f917, 0xc250df3d, 0xf88ad9c3,
5419 0x4931e0eb, 0xfeaec783, 0xd8f06afb, 0x1a74ffbd, 0xc0c56cff, 0xa43ff4eb,
5420 0x1aadfe87, 0xedfabbf8, 0xedb6e347, 0x04297bcb, 0x779f7bf8, 0x31bb73e9,
5421 0x64c7bb1e, 0x373ca131, 0x3f22e6d4, 0xbc0edd5e, 0xd0f4fc04, 0xff28af9e,
5422 0xa326d0f8, 0x3768c70d, 0x02dae6f8, 0xcc7eefe8, 0xea8dd6e2, 0xa746167a,
5423 0xdffd9d11, 0x0b1ef59b, 0x03cd95c6, 0x375c16f5, 0xb3d9accc, 0x4cd7f894,
5424 0x3f8944fa, 0x8b4efd28, 0xccfa3592, 0x5fd9f425, 0x9047cef5, 0x5f3aedde,
5425 0x89da1e7d, 0xb70f3f03, 0x41117f92, 0x3f12ba76, 0x892383d0, 0x3989ad76,
5426 0xde4de618, 0xa3ba758e, 0x82dfbfa1, 0x411c62b8, 0xc4e3561e, 0x2293fb78,
5427 0x5064ffee, 0xa54dbc73, 0xeb45d697, 0xb09d987f, 0xb35f8fd2, 0xcbd17c3f,
5428 0xc47583d7, 0x2bf372af, 0xb58bbf08, 0xc55c7918, 0x5e67f64a, 0x94e3c1d6,
5429 0xacfc520f, 0x05fbfe95, 0xbfd02392, 0xe11de252, 0x9ae2ace8, 0xd68c36bd,
5430 0x5e10fceb, 0x28b7ffce, 0x8a819fca, 0x6ac43d26, 0x162f9e65, 0x310e9671,
5431 0xdaf37687, 0xda1ff414, 0xa3ab1e45, 0x46e83f71, 0x4fecae78, 0xf37fcf74,
5432 0x9f6869d1, 0x79e33e83, 0x5a30a6ab, 0x624df227, 0x9106279c, 0x9123b17f,
5433 0x7ab57fdb, 0xcaa6786f, 0x77bc7c1e, 0x685f736e, 0x7f656977, 0x5dcbda1d,
5434 0x0efbcdfa, 0x39dae7f6, 0x574df888, 0x39e9e83f, 0xd7489718, 0xdcebb0d9,
5435 0x31eaaffa, 0x16b650de, 0xef1801ec, 0xa469e812, 0xc4feae93, 0x705f5c70,
5436 0xcb3f5c6c, 0x9fc893ea, 0xd1f10fcc, 0x60b293fe, 0xea05ba5b, 0x4d8fd7e5,
5437 0xf33fbe47, 0x5c14a0e4, 0x58c74e0f, 0xdc4f3053, 0x192024fe, 0x69ba79e6,
5438 0x6abf7f00, 0x17d470e4, 0x9c436b61, 0xadfc009e, 0x95fcf7e8, 0x14767226,
5439 0xcc48ef3a, 0x7c406b68, 0x7e93320c, 0xf6450507, 0xdf21fe53, 0x17786b0c,
5440 0x473f159e, 0xa15ac7c1, 0x3ffe954f, 0x79517a16, 0xd299fac2, 0x31ef7082,
5441 0x1ccffd11, 0xc38d7bd1, 0xf1b21ed1, 0xd08556f1, 0x0730f978, 0x29cbc80b,
5442 0x8e9d8eb1, 0xbc470eb4, 0x2832ebe7, 0xe443ba0f, 0x7c5956e5, 0xe41eb8e1,
5443 0x194ad9eb, 0xbe62afea, 0xf8d508f0, 0xd7b28df9, 0xfbddf448, 0x4d5ff90e,
5444 0xabe90c61, 0xfc8c337b, 0xa69bd773, 0x018f684d, 0x6821ddfe, 0x91371e17,
5445 0xc9afb2df, 0xfb617644, 0xd7f21089, 0x42c3f1fc, 0x3f48297d, 0x44499bd7,
5446 0xdf64f6df, 0x0c8edcf3, 0x680f9862, 0x891cea3f, 0xd1694274, 0x9ec3e3c5,
5447 0xd5cd7680, 0xda2f20a6, 0x60f4f035, 0x6acdd07c, 0x9efde9e2, 0x347e8610,
5448 0xa8643d3c, 0xe0f17549, 0x1082a0b3, 0xfda99bed, 0x01ce2943, 0x4a1f1fa8,
5449 0xb143fe83, 0xbbd52b7d, 0x9379d7da, 0x1221c785, 0xd48978c5, 0x5fb7326f,
5450 0x8d39f499, 0xef89fd03, 0x65ddf4cd, 0x79a48e72, 0x36c61c7c, 0x61679806,
5451 0xa0bcb6a5, 0xf62e5b5a, 0x5b25cb68, 0x745f65b4, 0x814fd114, 0x7f73e15b,
5452 0x70c4a4bc, 0x87c142bb, 0xd2769f3f, 0x61f03af3, 0xcbf1013c, 0x571d391a,
5453 0x929aba0f, 0x0f2de387, 0x9753e4d6, 0x3e279d34, 0x9fd8376c, 0x77c075c1,
5454 0x9136c0d4, 0xd50360fe, 0xf8ffb6fe, 0xe7adf3dd, 0xbcf5be45, 0x26dadf26,
5455 0x160c2ef4, 0x5084f18e, 0xe11c359b, 0xad4ba1d8, 0x3d5f22f5, 0xbe7c4419,
5456 0x21cbf716, 0x401baddf, 0x054452f0, 0xf0b3cfc6, 0xfd08cff1, 0x54c5e677,
5457 0x642d33ca, 0x4b4fa4b5, 0x44bef399, 0x5887e78c, 0x57ff9073, 0xcdfb02d9,
5458 0x27baf8fe, 0x34e3d386, 0x7d8ac6b3, 0x6fcc564d, 0x80bfe114, 0x74fd4504,
5459 0xdfbe20f6, 0xd175f48f, 0xd481137a, 0xd8ccf7c9, 0xf3ff9655, 0x0d0077cb,
5460 0x3655fe11, 0x67ae3877, 0xde7c2c17, 0x91593f60, 0x9f3245be, 0x8875fa07,
5461 0x2f120bc7, 0xd942fa2b, 0xdf00b12f, 0x989e7ccb, 0x518f2fa7, 0xc7ae38fc,
5462 0xf75e925c, 0xd693e830, 0xf2386b08, 0xb4aaeb53, 0xb79825c8, 0x66c6b088,
5463 0x3aecf0aa, 0xd026bcc0, 0x0946d65f, 0xf0ddbf63, 0xf39223b5, 0x085d6fa3,
5464 0x8eaf2bad, 0xf6ab996b, 0x8635ff13, 0xc58f91db, 0x16a6ff70, 0x40ec826d,
5465 0x5a74e078, 0xcab4e820, 0xf931fce6, 0x16f57e4b, 0xf412f754, 0xb95f7bf3,
5466 0x2f295ffb, 0x0fc55eb5, 0x8a4edeb0, 0x385de3e5, 0x374b7464, 0xfb4a5f91,
5467 0x82eb7c9a, 0x70bf6ec8, 0xae3a4a68, 0x82eb4543, 0x155f5122, 0x8b135e1d,
5468 0x8db8c8f6, 0x3ae2c58f, 0x6269b055, 0x9fe2533a, 0x482a3e2a, 0x3da3a7b1,
5469 0xb6567be4, 0xd5453f60, 0x4ab5c132, 0x167e695f, 0x36ab9fde, 0x24549d90,
5470 0xdbd73ae0, 0x2f788e19, 0x11bd33d2, 0xef4e7ef0, 0xf03b270c, 0x2ffc9959,
5471 0xbd40f9ff, 0x00ccfa63, 0xfa0b3278, 0x00b48be2, 0x47547bfc, 0x66082a74,
5472 0x36e75724, 0xb9edfcf2, 0x587de764, 0x157f056e, 0xaaad77f7, 0x0eb70e2c,
5473 0x73f78eed, 0xddf12766, 0x051f3102, 0x28e3feaf, 0xbc476d78, 0xe871fda2,
5474 0x2768c9b9, 0x91929eb8, 0xc6ded933, 0x8e47e42b, 0x72789a6b, 0x075fbe2c,
5475 0xd7158076, 0xdcefbec7, 0x4ad4eb83, 0x909da199, 0xcb1694d7, 0x57d76a86,
5476 0xdef22fb4, 0xa3ae159e, 0x90d31df7, 0x6d5b4e9f, 0xfb2a99b1, 0xcfc11dee,
5477 0x5fc974fe, 0xec70b7f7, 0x818d68af, 0xdff057e0, 0xfd93630e, 0x41e21953,
5478 0xedef6f3e, 0x7a157ea3, 0x2116fd28, 0x81fe15be, 0x2c63577a, 0x7c795f82,
5479 0x99d535b1, 0x0fc00b63, 0xe3037ff3, 0x61d57f62, 0xdcbfcc76, 0xbccab8e8,
5480 0xc8aae93b, 0xafd399ad, 0x8a54f9f5, 0xea8eeadf, 0xe9e99369, 0x50535bca,
5481 0xfd61f2de, 0x5f3a7f46, 0xfe449df2, 0xe315b285, 0x4aebf9d5, 0xf2f1c3ee,
5482 0xf874984f, 0xadcf75bd, 0x3f2e09c3, 0x529e01fa, 0x7b75f102, 0xa6c52faa,
5483 0xfbac1fc2, 0x7ccacf24, 0x1c137054, 0xe4307fe0, 0xa054f6ff, 0xbfee4a9b,
5484 0xf50f7210, 0x63e2462d, 0x5fc470fb, 0x7e2d7ce7, 0xcdf8b5f3, 0x3e2318f7,
5485 0xcd273666, 0x9323e0a7, 0xfc17df0e, 0x28e9a7fa, 0xc7abad9f, 0x235abcd3,
5486 0x8e51c3ed, 0xffa0535a, 0x59e7dda1, 0xe7986bf0, 0x6799efd0, 0xabd11065,
5487 0xfa4679c7, 0x33df679e, 0xed58c8cf, 0xadeacf3c, 0x5c5fa8e1, 0xfb8664bb,
5488 0x8ec95cc3, 0xd97963b5, 0x768614b2, 0x05d0f589, 0xd5e912fa, 0xb8a068d6,
5489 0x30ef22a1, 0x83f20dde, 0x35a1f88e, 0x28f4fad7, 0x0b656f5a, 0x575bd9c6,
5490 0x51e7788f, 0x95aeb728, 0xb407682d, 0x81fc72e6, 0x0f50ebdc, 0xa638a6b4,
5491 0xc18f7951, 0x39fa14b2, 0x0fb7f953, 0x0c0bf225, 0x73f34656, 0xbe3b45ac,
5492 0xfd45e01d, 0xcd997805, 0xcd034aed, 0xa7cad57f, 0x7777e256, 0xfe964df5,
5493 0xa7eb40d6, 0x6b45cf16, 0x321c8d64, 0x73c695bd, 0x8ac93afd, 0x0cf050f3,
5494 0xc67d349a, 0x607c2eb0, 0x2eb0d679, 0xfd94b8bc, 0xeb3d626c, 0x9f885bd4,
5495 0xc05d7cbe, 0xafa8ea7d, 0xa77d3f70, 0x57affb3c, 0xdfc67a7e, 0xd04db89e,
5496 0x16ef5fd3, 0x7ca9cbab, 0x5cbaa15f, 0x4a37a7e2, 0xbac3befd, 0xfc502d3b,
5497 0x78e77774, 0x02796f1c, 0xaf5c4a6f, 0xd68949fd, 0xd5bd3cd5, 0xabc17e88,
5498 0x155c78e3, 0x8ff301fc, 0x683b0e49, 0xb67a793e, 0xef8994dc, 0x994f546d,
5499 0xdcb7f427, 0x8ef46b04, 0xa077ae60, 0xaaa364de, 0x0557e8ac, 0xfe44479e,
5500 0xc3fe7942, 0xad64f3fe, 0xb38aacff, 0x201b123f, 0xf7299ece, 0xc608ed7d,
5501 0x64c976db, 0xf30eba37, 0x7d7d8575, 0xf06de9e5, 0x1a4f7cbe, 0xe6555bed,
5502 0xf6c78fef, 0x7de12b86, 0x21db7de1, 0xcbc63063, 0x72a31af2, 0xf48a2fc9,
5503 0xaffbc405, 0xfe94fcc4, 0xe12df4da, 0x2df6d5d3, 0xa19f096b, 0x86bc8fe2,
5504 0x164fb42b, 0x5596e7f0, 0x534cfb7a, 0x79fa2e4c, 0xcc4a7ff9, 0x55f3c1d5,
5505 0x06b5cf41, 0x506b0beb, 0xc899764e, 0x3c3b6f6f, 0xdbed8747, 0xe789170e,
5506 0x9e7a7643, 0xe382933d, 0x7f38eb87, 0x14bde32b, 0x7ca5edcb, 0x7fe7a9dd,
5507 0x8dfefa84, 0xaa65d4b8, 0x2ebe69f8, 0x6dc4fc93, 0x845cdf06, 0x95f1ec1b,
5508 0xe943efb8, 0x2b58d5e7, 0xebb6d1c1, 0x0fa8f3fc, 0xce4dacce, 0xb6d23544,
5509 0xcc70c06b, 0x189db7fb, 0x3fe78e91, 0xb04c9eda, 0x66d81ea1, 0xfc443eb0,
5510 0x86cc2ab6, 0x87f4ae72, 0xac7e60e3, 0x1cc8d76d, 0x4edbb3f4, 0x4ca17870,
5511 0x73d4377e, 0xa50efee3, 0xf59d70df, 0x8c8fb857, 0x7940c9fd, 0xa4dfc5b4,
5512 0x1abfa1c5, 0x5f9c0c6e, 0xbb5dfb40, 0xc1296a7f, 0xf1e3ecad, 0x7d95efb7,
5513 0xd17efe3d, 0xf80bd07c, 0x2b7fdfde, 0x702b9562, 0x1fbf917f, 0xdc7e40c7,
5514 0xfa62beca, 0xbdf5a5ab, 0x2677cb64, 0x0fb13d4d, 0xbe031a88, 0x571e40f2,
5515 0xc3c65c53, 0xe52b5fe3, 0x5f42f980, 0x3ec7cf2c, 0xdcedf213, 0x4f5d1516,
5516 0x1e3e98eb, 0xc8da7af0, 0x7f99f1cc, 0xaf973fbf, 0xbacc57de, 0x73a777fb,
5517 0x00b9953d, 0x32d5e9d7, 0xa1fd47ed, 0x7b7f9dfe, 0xf3e88480, 0x4effb099,
5518 0x3e705cc3, 0x5ab3fb3d, 0x067c1578, 0xfe057d89, 0xfe22cdf5, 0x991bf03e,
5519 0x9bee51d9, 0xcfe41e0c, 0x3f9f8d90, 0x67f20f7d, 0x6a92c1a3, 0xed017ca5,
5520 0x64bb6573, 0xb75c7f4f, 0x2f84cf1a, 0xd76575c4, 0xd34e3a08, 0x92ecbfe9,
5521 0xd6dfee29, 0xf3162570, 0xe50fd003, 0x4f4d5d3b, 0x7b7f90d9, 0x4e312382,
5522 0xeffa61fe, 0xa1f8bf66, 0x6db67bc8, 0xfa8e973c, 0x6260f41d, 0xfa67ca1c,
5523 0xff9e46d7, 0x7da1c96c, 0x273f1bbf, 0x73ddbcbb, 0x7349ec95, 0x940f6ca3,
5524 0x671a1c57, 0x4df061fc, 0xf007c2d0, 0x1478450c, 0x3eadcb38, 0xbd737f3a,
5525 0x5d84ffbc, 0x1cf14b85, 0xd1f9e608, 0x94682fbe, 0x582add69, 0x40ac7b2f,
5526 0x7e030997, 0xed082fb1, 0x8a24a7d1, 0x6f924e0b, 0xd40e70fe, 0x4ca4f05f,
5527 0x1f1bbde5, 0x7480d0fa, 0xbca06f5d, 0x99a682e1, 0xfc57da46, 0x122cc494,
5528 0x37d9ab8d, 0x12972c50, 0x09f6dd5c, 0x680fedf8, 0x7d0b76cb, 0xe37ef7e0,
5529 0xa2fb198a, 0x9267a9f1, 0x017efbb5, 0xcb103bfc, 0xdfe047cf, 0x126bfe96,
5530 0x416d0e91, 0x5ca3358c, 0x5fc85bea, 0x3e7e5e61, 0xd9d76db3, 0xeb97a414,
5531 0x5e292f8d, 0xb01c93d9, 0xf33fbe46, 0xfc8938ce, 0x5cdf81d2, 0x5008e699,
5532 0x6fc8b67f, 0x13b8316f, 0xb7dd3ed1, 0xe38f2af1, 0xae71e2ec, 0xee67fb1e,
5533 0xf26f1e20, 0x2c1c5106, 0x0532d6ab, 0x3cec01e5, 0x36b93fcc, 0x09b198ad,
5534 0x0dbb41ca, 0xabab4456, 0x05c9287f, 0xaaa141ca, 0xb61e455f, 0xb2947c88,
5535 0xd8b661bf, 0x6feca397, 0xf83bf650, 0x77eca1c3, 0x3bf62d98, 0x78eb1dbc,
5536 0xc19e0e28, 0xd9385f3a, 0x5ffb7eb1, 0xe2cfda7a, 0x3fd1efbf, 0x4f9fee6e,
5537 0xcbecad5b, 0x47146088, 0x8dfac237, 0xcd86c395, 0xabf51778, 0xfe4c98e1,
5538 0xef23ded0, 0xf1f5aac5, 0x38737d0a, 0xd72f31c6, 0xd1fe4419, 0xc316f947,
5539 0xa98dcf91, 0x862597a4, 0xca0bae76, 0xb375def8, 0x338eaede, 0xe7c71d3f,
5540 0x9d2e22bb, 0xfb7ab7af, 0xb7afcc21, 0x688cf259, 0x148e1b8f, 0x367e464c,
5541 0xf919e7c4, 0x54e6b9f8, 0x9e844ba4, 0xa3457ff8, 0x05b36e32, 0x7bf257fb,
5542 0x2cc71161, 0x598577c8, 0xbf3fbeb3, 0x4a83f227, 0xdf33af7e, 0x7be33f17,
5543 0xe33b7bf3, 0x8bf71d38, 0xff71bbe7, 0x3b7bf2cf, 0x5265fe91, 0x30f1a4cb,
5544 0x8ef88ac4, 0x6ebdf9c0, 0xfcb1bcf3, 0x567147de, 0x9ceb7f9e, 0xbdf90f6f,
5545 0x58dffd6e, 0xff7baf7e, 0xbaf7e43d, 0xf9837ff5, 0x797ecebd, 0x50f96f7e,
5546 0x5b3fed1d, 0xe3c4dc7e, 0xffbe66e4, 0x65e424c3, 0x668277b9, 0x74f284ff,
5547 0x184909b3, 0x275e5f27, 0xbcfe464f, 0xa0b3c96c, 0x78221a7c, 0xb064c83c,
5548 0xd43f464f, 0x85191114, 0x711ff97c, 0xabaf3469, 0x3f888b11, 0xc87982af,
5549 0x722d89cf, 0xef797960, 0xca649902, 0xd6177f2f, 0xd57cf324, 0x7758b368,
5550 0x87e4b7df, 0xf3fbfe52, 0x3d1e5538, 0xed00fb2c, 0xce0d648b, 0x8fbf283e,
5551 0x127f405b, 0x7c50b79f, 0x7f3928c6, 0x76217187, 0xbb639f82, 0x601ce41a,
5552 0x3ea5c951, 0x2eec28de, 0x33ea126f, 0xa7a2ab37, 0xe10ae1ab, 0x2a478959,
5553 0x47cc5ddf, 0xa5794778, 0x7a09b8c3, 0x706f7d2b, 0xb573a00e, 0xbb4e8e02,
5554 0x6ea18fe0, 0x6a69a73c, 0x8ff286fa, 0x34df7aed, 0x36d4eb8c, 0xfc6a21ca,
5555 0xb973c526, 0x9cfe4dc8, 0xd8e556f2, 0x57e617ae, 0x7ca0064b, 0xc37c9b96,
5556 0x7b7dee11, 0xf51c36fe, 0x92a6d5ca, 0x0b7ef83e, 0xdc75a7d4, 0xe7572be8,
5557 0xaaf3fd5d, 0xf381f1d1, 0x969a5bad, 0xdb1c2225, 0xf6005e30, 0x3fc3f955,
5558 0x663a73a7, 0xea0dff66, 0x837a060f, 0x99868afc, 0x93b438f2, 0x01db003e,
5559 0xf8bb59ca, 0xcc959bfa, 0x2d37983c, 0x0e60fa6f, 0xdb3cabd2, 0x32974168,
5560 0x6de78338, 0x16cdb383, 0x45a6ff5c, 0xe2303e71, 0xed869b3a, 0xdd214627,
5561 0x3031c41e, 0x7b73b9cf, 0xb7f01bbd, 0x854f0ff0, 0x27dfc033, 0xafda4afa,
5562 0xb1f9ba51, 0x2f3c3b70, 0xc714dde8, 0x0723c4fc, 0x1794ffdc, 0xf6b7f8af,
5563 0xfe754950, 0x3fdfd3e0, 0x6ef88d31, 0x7982c1b3, 0x1316d77f, 0xaf2b9f9d,
5564 0x33f3a62b, 0xcbc53e50, 0xfe867f8f, 0xbb41ab95, 0xe97c2f4e, 0xad2b58a9,
5565 0xb124ee0b, 0x941f11ee, 0x849d9cd7, 0xc1f857f8, 0x8f8e1dbf, 0xb55de5fb,
5566 0xaf633cf2, 0x7b15dfee, 0x5dff5943, 0xfb884f75, 0x3fc85a01, 0x845faff0,
5567 0xb19a3232, 0xfddaf199, 0x983e0ad1, 0xa3f48627, 0xf0c373bc, 0x54be5053,
5568 0x92e16ff3, 0xbf8a4f0a, 0xff9b51d3, 0x3dac37bb, 0xb06defaf, 0x7574b02e,
5569 0xb3b50f3b, 0x177e0836, 0xf06a5f7c, 0x955ca386, 0xdcd8346e, 0xfb74baf0,
5570 0x973e2f0b, 0xc3667245, 0xfb64ac75, 0x818e1f5b, 0x430ec972, 0x8d3e54f4,
5571 0xde754950, 0x61ff05cd, 0xc3a1405e, 0x32ded7c2, 0xf7f1875a, 0xa2ec88bf,
5572 0xbd8ec947, 0xfc5e7446, 0x76be31f1, 0xbbf291af, 0x3da974fe, 0xef2b7245,
5573 0xbbec86fc, 0x2c48f64f, 0x3e00352e, 0xee15be37, 0x3a227814, 0xd2753a0a,
5574 0x92beafcd, 0xe4e8577f, 0xde3b3dff, 0xfd85f242, 0x3f023ca1, 0xc606f2bf,
5575 0xd9323ffb, 0xaf45fe70, 0xf38e103c, 0xc45faf38, 0x63c37af9, 0xb71876b1,
5576 0xb58ee0c8, 0x2fbf93d0, 0xc467fe7a, 0xfe8e0b6f, 0xcc7fdb8c, 0xfca3a09e,
5577 0x7bf29ba5, 0xd0efeb85, 0x0da2ffe8, 0x85ffae3c, 0x11de4d9e, 0x0b8e2e40,
5578 0x937e72bd, 0xe7d9f289, 0xf6860f31, 0xdf327bcb, 0xa7eec7b7, 0xdf629078,
5579 0xe54d2780, 0xfe1e842f, 0x894ebc43, 0xfc359b7f, 0x3378f35a, 0x64d3e7d2,
5580 0x25ea1c7b, 0x05bbd317, 0xa0efa43e, 0xc4e8f95f, 0x1e1f4e38, 0x6076a33f,
5581 0xf7c78e8f, 0x40d9bf58, 0x3b5550f1, 0x8f966e71, 0x1f18a0ff, 0x7cc60ee0,
5582 0x5658f9ca, 0xd44fc814, 0xe7c67427, 0x29e7359b, 0xcb9be4bb, 0x2e2acd7b,
5583 0x7bbc8adf, 0xefc64fa6, 0xf2e31f9f, 0x3292ed83, 0x1c6f2e09, 0x4b3bdf7d,
5584 0x27cfce1a, 0x75c9037b, 0xb5c8418d, 0x27c2bbf6, 0xee9eb700, 0x05f85021,
5585 0xfc248ffb, 0xbad2d517, 0x1dd8d26d, 0xbc2f1c2e, 0xdc8a7f7b, 0xfff2102e,
5586 0x7f38bc7e, 0xad9fe425, 0xf3a1b98f, 0xcf06a545, 0xbca1cf8b, 0xbef7e09e,
5587 0x90376e94, 0xdb717e5d, 0x06ef0ffe, 0xab58b939, 0x7f56a9c8, 0xd169cbfa,
5588 0x7f116fab, 0xc5e9cbfa, 0x0362b7da, 0xb78ee9ca, 0x2eee0ec8, 0xfab9ffa7,
5589 0xdfdfc153, 0xe8a7f0fc, 0xe8f09ec3, 0xe3ab0faf, 0x21f501ad, 0x9f531dfc,
5590 0xa5f0537b, 0x6fc29df0, 0xeb2e5f0b, 0x93a77a83, 0xebbe152f, 0xef854be4,
5591 0xd73bedba, 0xfbffcfe0, 0xe00df85b, 0x60faec72, 0xb3d01252, 0xc9fb91b4,
5592 0x9620eed0, 0x5a764f01, 0x41e558c6, 0x55db6f3c, 0x6b95f8f6, 0xfddbeafd,
5593 0xfabf0eca, 0x22f2bf4e, 0x821efabf, 0x3f61b4ab, 0xbcc96fdf, 0xa586fa9a,
5594 0xdd161dcc, 0xf31e0e75, 0xcfd02b58, 0xf4f3c6df, 0xb8f0258f, 0xb8c62fa9,
5595 0x891ff682, 0xe13e2a7d, 0xb43bb467, 0x354e54fb, 0x5b7fa4ca, 0xf8f3813c,
5596 0x3c9209e0, 0x3fb0f4b4, 0x4d3b895e, 0x1e534394, 0x2a3a3806, 0x60a0fc79,
5597 0x94e19dc9, 0xbb4c69cf, 0x850ae31d, 0x2c31f987, 0x73143f65, 0xaa09f5db,
5598 0x98170efd, 0x319be9fb, 0x4258d64f, 0x35828bf1, 0x0fcd7a5a, 0x0be2907d,
5599 0xf7b4abf3, 0xad7c2900, 0xd68b0bc4, 0xc42fbf6b, 0x1ee8847b, 0x47da4a85,
5600 0xfb46b0b4, 0x0e7c89dd, 0x41273c7c, 0x2c1909d8, 0xf9bde443, 0x57a11239,
5601 0x6f43ca27, 0x21cbfca7, 0x1da5f299, 0xbde1328d, 0xfb449b63, 0x863b9869,
5602 0xf99ca5e4, 0xf8299f48, 0x60f284b9, 0x5cdf59ec, 0x73dffd7a, 0xa52a851e,
5603 0xff0f1ff5, 0xd52f3c2d, 0x8ddf489f, 0x4e7f9de5, 0xaf7598f9, 0x104f7e3f,
5604 0xdf6a1fed, 0x35f74613, 0x9dbd37b5, 0x85e528f2, 0x07ba364c, 0x9497cf61,
5605 0x6a5f6b7f, 0xd57d422a, 0xcafdcc9e, 0x0e5f4d65, 0x39657ae7, 0xc098df3f,
5606 0x34744dcf, 0x94f28dfe, 0xca268d1d, 0x84f6b933, 0x7ae11f90, 0x9cfc8823,
5607 0x292fa6f6, 0x9acffcbe, 0x3788b94f, 0x3cf187b7, 0xbfb8bb4f, 0xf47bb5c4,
5608 0x2d87980b, 0x446bdbab, 0x9bfc65bf, 0xdf5d90df, 0x67b72afe, 0x1eded0da,
5609 0x5bae7883, 0x7dc44e33, 0x4d0ecca8, 0x0db77b45, 0xb1912385, 0x9d5dcfa1,
5610 0x081a1eea, 0x5e50df4f, 0xf3f146f5, 0xfc18ffd2, 0xb9dfb448, 0x63cc31b4,
5611 0x5fde7096, 0xf518fc9d, 0xd79e1ec1, 0xb17be657, 0x1fd90976, 0xc1f79bd7,
5612 0xfddfee04, 0xe4b799ef, 0x9f7991bd, 0xef4e6ffd, 0x98d43c62, 0xba2e5ddd,
5613 0xcf1379f3, 0xb30f6d17, 0xc837bc11, 0xffc486ef, 0x157f7465, 0xfd7e1ee8,
5614 0x6ffbf779, 0xe99eef3e, 0xa0ae787e, 0xf3e305bb, 0x21bf37ae, 0x3d5efef8,
5615 0xe87fe137, 0xfd3b15fc, 0x6fd7c67d, 0x91c3a257, 0xee9efb88, 0x5f02bc38,
5616 0x274e74b9, 0xcd12c3c5, 0x4d9fee74, 0x8e87e28d, 0x33618ef5, 0x57877586,
5617 0x25fe1bf1, 0x31273ed1, 0x07feaba6, 0xa619efb3, 0x7d57779e, 0x58d1be3e,
5618 0x379d3f7b, 0xfca50b29, 0xc18f6e2c, 0x36cc2f76, 0xf713fe71, 0x990f1c3c,
5619 0xa606307b, 0x738347f2, 0xe739c23e, 0xc0ac9fce, 0xca2fb4b2, 0x35e718ba,
5620 0xdc4725af, 0xc710b08b, 0xfb3b352f, 0x72f9aa60, 0x2f4073b2, 0x511c47b4,
5621 0x1ccb9e3c, 0xe1011cc3, 0x37ce6b77, 0x994bf62a, 0xea3aa1b0, 0xbe517ad2,
5622 0x645ed5e4, 0xb8e9b57f, 0xe026d87f, 0xb767e0bd, 0x1a8e7917, 0x5c58ff31,
5623 0xcea8d473, 0x7389963f, 0x3fe3fea9, 0x23f3c891, 0x87f6be9f, 0x8bf748ab,
5624 0xa3a7d45f, 0x5d2256bd, 0xdd5d79a2, 0x98ae747a, 0xff9c0adf, 0x14be1d43,
5625 0xb4abcc23, 0xc791af76, 0xf4fcc523, 0x9beff4be, 0x79ae9b5f, 0xaabb9d12,
5626 0x8e7ce897, 0xeeacaed2, 0x93b424e8, 0xe8226a8b, 0xa7dc473e, 0xca9dcfc2,
5627 0x7860fb7e, 0x8eb2493f, 0x4bf7dbf8, 0xd21bf689, 0xe9dfb41f, 0xbee0f08e,
5628 0xcaee936a, 0x676899b1, 0x8ce7e30f, 0x438307d6, 0xbbc77e0f, 0xc41b5f02,
5629 0xbf780779, 0x07c7df12, 0x4ff1f6f3, 0xfedf68eb, 0x9409b90b, 0x7bdd543f,
5630 0x72075291, 0x36b26494, 0x49b8c0b4, 0x0f28bd15, 0xb9d13dbc, 0x5f71f105,
5631 0x18e52e94, 0x421ce1c1, 0x8e6f80e7, 0x753f21ba, 0xf818b306, 0x9e7e527e,
5632 0x4f85867d, 0xb5d850a5, 0xee9d9933, 0x3983b8e1, 0x6d7bdea9, 0xd7da3b46,
5633 0x336e61ef, 0xa3f7ee93, 0x0f3177f7, 0x5e61ef3d, 0xac2fffaa, 0x5f0aca85,
5634 0x17de3f02, 0x3cf1f9cd, 0x8e8160a6, 0x47dc226f, 0x3f278643, 0xfe9ef80c,
5635 0x94fe80cc, 0x76e2ad2f, 0x9ee0f5f0, 0x574bfc2e, 0xf210f3a2, 0x2fe4c77b,
5636 0x7e82af9e, 0xf12f6674, 0x91ee7283, 0x7c11884d, 0xdb72fdf1, 0x0f99d1dc,
5637 0xe2bf450d, 0x5bd24156, 0x509fdced, 0x2edc0dce, 0xd9ef01e4, 0x343a0489,
5638 0xa7bdf95b, 0x3dbd2acc, 0xc793ca02, 0xe59fb4c9, 0x20d6e08f, 0x4331fc7f,
5639 0xd9a5f716, 0xd134fda9, 0x3371d4ef, 0x7a82f797, 0xc96ebe93, 0x9327f3c2,
5640 0x8afd6b7b, 0x5c6f449f, 0x29cf011e, 0x7fefb4fd, 0x88f59aca, 0xb543a9d7,
5641 0x2cb4cdfe, 0x38bdbd6d, 0x2a962466, 0x4b845ee9, 0x193fc289, 0xfdab06cc,
5642 0x1d3e6513, 0xd118af53, 0xe493ec17, 0x597482bc, 0xb9d9db7c, 0xcf4ede74,
5643 0x4d111ede, 0xbcd1cff7, 0xe6f02b5a, 0x55cec646, 0xa179e998, 0x20ecc2c2,
5644 0xc4569ff7, 0x8552f3d3, 0x55b7de95, 0xf8e7a40c, 0x90dfc724, 0x9f95053e,
5645 0x670fd1e9, 0xee34e955, 0x9acf8203, 0x9d1d5e75, 0xd124d85f, 0x82079a7e,
5646 0x8ef1739a, 0xa73607ac, 0x61739c52, 0x0c41ed43, 0x1d78141f, 0xf39c9093,
5647 0x883a2d0f, 0xc06bb2cf, 0x158023e9, 0x24a61c12, 0xa763eb94, 0x7ac6df67,
5648 0xe37b1be6, 0xd05183a9, 0x1b0af9ff, 0xc549f5c1, 0xac5e7a28, 0xb3dc13b0,
5649 0xa4961c92, 0x67d2a46c, 0x6db73fc4, 0x824fa53b, 0x12ad13fa, 0xb63f2bad,
5650 0xe4078f33, 0xd7c0daab, 0xb304ea85, 0xdc74e50d, 0x1e1b19b0, 0x9df7a864,
5651 0x1dc70889, 0xe2278a53, 0xcd46d338, 0xeeb47ba3, 0x7bf19afc, 0x58dc2695,
5652 0xe9f988dc, 0x247bcbdd, 0x3acbcbe2, 0xff18edeb, 0xa649ff75, 0xde0740fc,
5653 0xe3fe80d3, 0xe32f7e71, 0xe2d3d7e2, 0x362f3f50, 0x5fd0e358, 0x79f62ddf,
5654 0xe97a045c, 0xc5eceb55, 0x9cce7fed, 0x25bfd2a7, 0xfabaecaf, 0xf2fbf411,
5655 0xea1b48c9, 0xe2918bbd, 0x28b6467e, 0x9b48f504, 0x19623bc8, 0xd65015ef,
5656 0x5833d45d, 0xebcc18be, 0x9492bce7, 0xe382728b, 0x7a5d8d59, 0x6795fd28,
5657 0xed6a3efa, 0x6d4b6f1a, 0x41cf47e1, 0xe747b2f9, 0x723ac036, 0x61b6d599,
5658 0x135dd6dc, 0x066dfb4a, 0x87e0fa4a, 0x7c3d6f89, 0xd56488bf, 0xeb6c3c63,
5659 0xd1121b2b, 0x392dd80e, 0xfa823ee6, 0xffaf037b, 0xe48fd3d2, 0x53e7c2ed,
5660 0x823eaf65, 0xa08a4f78, 0x2b9ff376, 0x36fc8c1e, 0x5d5efd6c, 0xa9bfbc22,
5661 0x7c52d4e6, 0xc2a240ce, 0x926d8cf7, 0x8cdd778c, 0x865d4ba8, 0x1fb898af,
5662 0xfbc0b06e, 0xed9ff5d0, 0xf4107703, 0x08e2ed6b, 0x525757ca, 0x671bd7bb,
5663 0xc10f7fbe, 0x7bc04ee1, 0x8cf3dd35, 0xb8f03edc, 0x5c9f2237, 0x51b40e76,
5664 0x7ee1cd7e, 0xd973e916, 0xf5c36b19, 0x0ee75ea0, 0x4ff5831f, 0x76087bf2,
5665 0xc70d1cd6, 0xeabd11fd, 0xed082c0c, 0xad1f0c95, 0x56c9654b, 0x259659bc,
5666 0x64eb7f3f, 0xd7927946, 0xa53f5237, 0x99e61b66, 0x42bf5e8b, 0x13f61cf1,
5667 0xfc8feb66, 0x4fcbc751, 0xfd13b04c, 0xc17e368a, 0x2a0ecdcb, 0x2a77643b,
5668 0x0f945fdd, 0xfbf40c76, 0x5877588c, 0x47d270cb, 0x2ed672c4, 0x9f013f7c,
5669 0x3abdf02d, 0xfb809dd5, 0x0af594c3, 0x219f99d6, 0x839ba37f, 0xef739bed,
5670 0xf775a149, 0xa519d706, 0xfc8c679f, 0x46f5bd7e, 0xb66e1ebe, 0xf42778f0,
5671 0x4fe514bf, 0x64931759, 0xae1d5869, 0x6c98cf73, 0x3e37accb, 0xfee2ddce,
5672 0x2af813ae, 0x430d6c41, 0xf8ffba42, 0xe9ffc636, 0xfbf23dfe, 0x15675799,
5673 0xf941ecf7, 0x4fc3a4e9, 0xe619bf2e, 0xe003f82d, 0x83013820, 0xf2a7f50c,
5674 0xe38b2c3e, 0xb669d233, 0x2e2b7e61, 0x33dd116a, 0xd307f0a1, 0xdda0477b,
5675 0x995bfab0, 0xffb94bce, 0x7f714a1a, 0x4ddf787f, 0x7af471e2, 0x639e07c0,
5676 0x7bf07772, 0x5ac31a9f, 0xf403fe5e, 0x9bdc58df, 0x0dbbc6e2, 0xf756fefc,
5677 0xdc5df174, 0x5778dd27, 0xa27dc92c, 0x7601eb89, 0xd38d304f, 0x7e6cf068,
5678 0x8f4fbf1a, 0x85c7f6a7, 0xde671d9c, 0x955f707b, 0x7ba467db, 0x1822ab39,
5679 0xb55367dd, 0xfdc50064, 0xe07dbfea, 0xbda186df, 0x639f84b2, 0xacf0caab,
5680 0x55ff7dc4, 0x70e34cbf, 0x1724de48, 0x260e2fb6, 0xdd355d3d, 0x4071809e,
5681 0xba10b4e7, 0xfba7ba57, 0x28323f5e, 0x09ec89e7, 0x0ae78f88, 0xfdf533fa,
5682 0xca4e7f41, 0x57748c3d, 0x3a73d1f2, 0x8ecc22f3, 0x21de5bf7, 0x6e15770a,
5683 0xbb7e420e, 0x14e828a3, 0x178f6bc6, 0xb8c30d2d, 0x7e4e1de3, 0x359b273f,
5684 0x8f3eaed1, 0xfb24e7f9, 0x5657e461, 0xdeedd8a0, 0x1ed3c47c, 0xbdce999f,
5685 0xa847f901, 0x7f8544ed, 0xbe77aafe, 0x8ddaed87, 0x92e35ee2, 0xb6cda6af,
5686 0x6bf1faaa, 0xf27edfe7, 0x37bf330c, 0x7644cea9, 0x8ec27dc1, 0xb3bc9972,
5687 0xad5a0ed1, 0xf607fe73, 0xe9f85aef, 0xa277b470, 0x17fbf067, 0x09be31db,
5688 0x7a0a4f75, 0xff7c649d, 0x98517ba0, 0xb2f11bc8, 0x0f28d1f3, 0x9ec7a7bf,
5689 0x07e58850, 0x1f70d886, 0x99e45390, 0x7c44b958, 0xf9c2d272, 0x146364e4,
5690 0xe33e8fdf, 0x30e9d3da, 0xab8e938f, 0x7a848f6f, 0x79f81b27, 0xcc3cbf8e,
5691 0x2f9619cf, 0x60d2913b, 0x7baf3eed, 0xd97bf297, 0x0bf85def, 0x93da6f3a,
5692 0xaa5bddfc, 0xd21987dd, 0xce15fedb, 0xb5c67a33, 0x1287a849, 0x2d9f4a4b,
5693 0xdbdabd44, 0x2fbe2df9, 0x2394b637, 0xff77ca3e, 0x7fda0a7b, 0xda5ebbed,
5694 0xaf9e1071, 0xdeba9d19, 0xade97df8, 0x67618fa9, 0xd72f9ec2, 0xae403d03,
5695 0x34edea9f, 0x717e06f6, 0x63a6f04d, 0xe6864bbb, 0xf6378849, 0x1bb31b8b,
5696 0x5cdc6d3f, 0x115fa12f, 0x4f4e58dc, 0xe11c33d9, 0xc37928b8, 0xa71e1ef1,
5697 0xc97e8fd8, 0x188f0de2, 0x72c7f78a, 0x1f3ff5fe, 0x8ac5a048, 0xaed0327d,
5698 0xe71656a4, 0x27143c97, 0x025faff6, 0x0ddea9ef, 0xcbce57be, 0xac344495,
5699 0x66f44b1d, 0xee166f5e, 0xf74feceb, 0xfd7e5d32, 0x5fb574a5, 0x0eecffe5,
5700 0x9d3f9f2f, 0xa9bcc6e7, 0x7bf7df87, 0xe4068a09, 0x71266db3, 0x51f38f8e,
5701 0xc104d6db, 0xda8f9c67, 0xa8f00eb6, 0x9cf3b6e5, 0x8736ada0, 0x6bdbedf6,
5702 0x501ed073, 0x6b999fe4, 0x36677ee9, 0xda3876b0, 0xc23d8add, 0xf4e9b51c,
5703 0x8e9b53de, 0x3c75ebf5, 0xbb8ca73f, 0x7e24e5f0, 0xeb9998df, 0x0f2f85c5,
5704 0x94c6fba1, 0xcf37af7e, 0x4d46d501, 0x5b479079, 0xef9bd69e, 0xeffdf85b,
5705 0xcbf1f73b, 0x93c61ec2, 0x40f79d85, 0xbd73de76, 0xf2f05255, 0xfa0e5260,
5706 0xaaf28ca3, 0x0be07bbb, 0xbd21ae05, 0xf30b3fb9, 0xbbceb863, 0xbbfae23f,
5707 0xf331c33e, 0x6fd72836, 0xb6fb2348, 0xe9f8e74d, 0x79e71c30, 0x3ebaafbe,
5708 0x9cf947c2, 0xfdb967fa, 0x5de62e5b, 0x424ce11f, 0xc2a17a7d, 0xffee2f16,
5709 0xe96c3b26, 0x98e11589, 0x61dfaff7, 0xd5f8c0c8, 0x63fb3527, 0xad3e2f91,
5710 0x37ee9878, 0x75e3bc1c, 0x6e94a3ca, 0x1c7de07d, 0x8336d2f7, 0xd2acdd0d,
5711 0x8b5c5ebb, 0x56e948f6, 0x5be716b9, 0xe53f75ba, 0xbed52fc7, 0x71fb8e15,
5712 0x9144d42f, 0x53f08c1f, 0x1cf7fafe, 0x2ff8fe0f, 0xabc464f6, 0xc91591f7,
5713 0x7f78b5ee, 0x5a2d90c9, 0x3c7d17bc, 0xedea10e9, 0x18cff50b, 0x1fbc56f5,
5714 0xa6fdfb56, 0xeff96d06, 0xe4abaf3d, 0xd4e39091, 0xdcc85c74, 0xdda9f507,
5715 0xb5645feb, 0x3f18edb3, 0x9727bce8, 0xdae8edcb, 0xbb379475, 0x6e6e78fe,
5716 0xe9da853c, 0xa379ab9e, 0xe231b7f8, 0xe6b65efe, 0xdbc424e8, 0x5a2427bc,
5717 0x36bde6ef, 0xcfea00e0, 0x9aee3b53, 0x93d9cf42, 0xe8f91f09, 0xd67ee085,
5718 0x061bc946, 0x8e28cb65, 0x9e6ac2ef, 0xee5bca17, 0x8d69ee77, 0x2af8fedf,
5719 0x0d05f7ed, 0xbcc2bf7b, 0x79f99176, 0x3f741f8a, 0xfba1e3c7, 0x605e177f,
5720 0xac2dcfe4, 0x2814cef9, 0xcca851be, 0xda63fdc3, 0x264dc01f, 0xfff0fff0,
5721 0x4daee346, 0xe1ea3d47, 0x651b5531, 0x731957c4, 0x2349643e, 0x021bc5bf,
5722 0x8137cfe3, 0xeb4992dd, 0x4ae7cd21, 0x8f3a2f75, 0x5059ef0e, 0xda03de26,
5723 0xe4eb839c, 0x1b30ba95, 0x9cd69fdf, 0x02d57683, 0x21f9d328, 0x0bce2956,
5724 0xf1fee87b, 0xcd06d505, 0x1ec5e07d, 0x7255996d, 0xef14b0fb, 0xfa470ed3,
5725 0x92bb50b7, 0xa57ada2d, 0x91e39f30, 0xfb51ffb8, 0x5b7cc5de, 0x2b7da45f,
5726 0xefd498df, 0xb1547b15, 0x0e38958f, 0xe460b228, 0x7237bb97, 0x04b77a3d,
5727 0x0c3b45f3, 0xafb234ed, 0x420e3b3c, 0x2878aab9, 0xdff54fd9, 0xca5bfdf2,
5728 0x0caad4f9, 0x279e3a7b, 0x88375aab, 0xb25bbfe6, 0x7a863ea7, 0xd859ba60,
5729 0xe1ee8c57, 0xa44e2aaf, 0x1c23fbf5, 0x2ced0132, 0xf729ef6e, 0xeea227f5,
5730 0x18e371c2, 0xb53f8fbf, 0xb37a8bd6, 0x3fae29ea, 0x81563b14, 0x4f675f3b,
5731 0xb36e75c1, 0xcdebe9d9, 0x23a56ff7, 0x09bff9dc, 0x4557bc22, 0xfce8c2f8,
5732 0x0dd4517f, 0xc59ba7ad, 0xabcca0fa, 0x7dd07255, 0x293d4ae8, 0x9cdbeb99,
5733 0xa28bfb5c, 0x0b39c51e, 0x6fab1d72, 0x3c147c01, 0x1fa2b3ad, 0xbb6789dd,
5734 0x13ef1d3d, 0x94175d68, 0xcc9cf089, 0x47367ae0, 0xf6061bdc, 0x3c137dbb,
5735 0x9a759383, 0x32706578, 0xc163a7b7, 0x5af1c27f, 0x5438f227, 0xfc839658,
5736 0xe6a9c079, 0x19e53c1e, 0x302be02b, 0xa3f4fe3a, 0xd274f000, 0x7bc7027b,
5737 0xad12fdeb, 0xa21f3047, 0x83afce5f, 0x2ad00e28, 0x4e8503d6, 0xb4d92fc0,
5738 0x54bd09ce, 0x21f80ab5, 0x2da1ed15, 0x6afa835b, 0x0be286f8, 0x3ebe2eec,
5739 0x7c704554, 0x4c393d56, 0x6f82e5d8, 0xbf120c9e, 0x6cedc0c7, 0xec51fd65,
5740 0x3d3e6570, 0xef40e1d9, 0x7c2ac961, 0xe999d3f9, 0x7dead93d, 0x5e74fe94,
5741 0xd2986e60, 0x0bc1550a, 0x5c067825, 0x6b7d91d2, 0xde0892ce, 0x2a7ad581,
5742 0xb259d51f, 0x8da6ee51, 0x11f179dd, 0x7e7857d4, 0xebf47907, 0x39bbbeef,
5743 0xa951f707, 0x7dc472fe, 0xeb0fc8ca, 0xef183799, 0xd894afd9, 0xa03acd69,
5744 0x8fdfe32d, 0xb9fabb63, 0xf89efd5e, 0xdcfd9ff7, 0x69d8c159, 0xf85d8590,
5745 0xebc347ec, 0x4665fbd5, 0xb93c7236, 0x5f4f308e, 0x597677d2, 0x0467ef8d,
5746 0xcbfcee1f, 0x6e3023ab, 0x687dae31, 0xe9679e2f, 0xd3ef53a7, 0x5ed660ed,
5747 0xa3b4efb8, 0xee17ad31, 0x2438eb4b, 0xf0033987, 0x038056f5, 0x572ff1e3,
5748 0x5ed9e998, 0xf0652ac3, 0x8f99da2b, 0x6bba67f6, 0x5f902ccc, 0x73b934ba,
5749 0x739319ff, 0x3ba5f7d4, 0xa4ec7d68, 0x9fa9a5d3, 0xc77787e8, 0x569dfe3f,
5750 0x87f913d6, 0xebf715e3, 0x06b75e20, 0x740a4cb5, 0xe04aafde, 0xafbeda6d,
5751 0xe0e33f68, 0x943a8dc6, 0x3a35c1f7, 0x26b93acd, 0xca43ec59, 0xd7089964,
5752 0x61417db4, 0x438f4859, 0xe6082db2, 0xccfc6ae7, 0xd7e00ce8, 0xfb11e3f9,
5753 0x8702fdc7, 0xa7842d93, 0xf25a86dd, 0x365f772b, 0xbb29fdd3, 0x8125958c,
5754 0x23eccce0, 0xd8ebc405, 0x5f6833f3, 0x5e157fca, 0x7a87b5c7, 0x588e3173,
5755 0xbb1c78c3, 0x7d71bf1b, 0xd185b1d4, 0x710ef739, 0x1b63a80e, 0xa01ebca3,
5756 0x77dc49e2, 0x8b7df203, 0x80d63f7a, 0xe32f1d86, 0x28de5efa, 0x72e4fed1,
5757 0xf7118b7d, 0x221aba5b, 0x65bfcc64, 0xae3dc558, 0x59b0cb7a, 0x9c38392a,
5758 0x17e7e7ac, 0x07beecc6, 0xc972bdc7, 0xec87e748, 0xef747c07, 0x11c695c0,
5759 0x3cefbebd, 0x6c156bce, 0x7b3bde0a, 0x5f119938, 0xd0c1f3f8, 0xf29ac16d,
5760 0x8899d958, 0xd4cd34f2, 0x002da0f2, 0xc4528add, 0x7aa370fa, 0x89fff3cc,
5761 0xe8a63b1e, 0x8eaca731, 0x74a46487, 0x817163d3, 0xc962d8f4, 0x5ef8871a,
5762 0x871694dc, 0xd87c5cf4, 0x8f481310, 0xac38076d, 0x007f7720, 0x7b67c3f9,
5763 0x9bb1e81d, 0x0eac7a54, 0xbf0058f4, 0x3ae52924, 0x5ff3cc7a, 0x51db6f23,
5764 0xe798058f, 0x1fae14f0, 0xbc363d14, 0xb1e914f1, 0xcd3a75e1, 0x29feda39,
5765 0x5263d3d7, 0x2c68accc, 0x01216c1b, 0x89f106f8, 0x27c47779, 0xd41c713e,
5766 0x9629f967, 0xfd9f4bbf, 0xecfa7af8, 0x8abf08bf, 0x3afc5b3e, 0x3ba37f23,
5767 0xdfe231df, 0xfd18bbc5, 0x26e2cfce, 0x3716cfae, 0xcf0fbe31, 0xec0d8f4f,
5768 0xff18c7a6, 0x6f2f165d, 0x7d486aef, 0x2fe85ee6, 0x99b06ed3, 0x97667ea1,
5769 0xeb56cb5e, 0x1e94fcb5, 0x1ba1daf4, 0x0baf6bd3, 0xaafa06bd, 0x7f51ea2f,
5770 0x6a35b0be, 0xf763977f, 0x5edbf3e8, 0x5b78f943, 0x4701f3a6, 0x9dfebe45,
5771 0x90b3e7d1, 0x1e11eaaf, 0x4235d390, 0xdc2adb5e, 0x03f8ffd4, 0xdb657e7c,
5772 0xca0f5a24, 0x57bdb8eb, 0xf07b235e, 0x31a4e180, 0xff3ed15f, 0xe18926e2,
5773 0xa6e9b2d1, 0xfef1a7ca, 0x8192f630, 0xd4e53889, 0x143f150c, 0xf8a12a8c,
5774 0x999e8161, 0xc96ddf71, 0xb73fbe28, 0x7b959444, 0xf53b0ba2, 0xcdbedfa0,
5775 0xf7e9fb86, 0x7bcffc34, 0xdcf7134e, 0xf2417b4d, 0xdd5ffde0, 0x712a7bcf,
5776 0x97fbed38, 0xcba77cc5, 0xf61f842d, 0xde73e06e, 0xe5e3fb2f, 0x8d4bc090,
5777 0x478bc5ac, 0xe517880a, 0x8782ad5c, 0x565bb7e2, 0xf8a75c60, 0x32fc8959,
5778 0x782b79ff, 0x761f76ea, 0x909dff23, 0xdb62f7ee, 0xd25bbf35, 0x144477ed,
5779 0x7fcdfb3c, 0x323fa2bb, 0x37bc08d8, 0xf482f81b, 0xfc4ffb87, 0xb8c7421e,
5780 0x3d6a71fe, 0xc3c09afc, 0xe371ca88, 0x2e99add1, 0xd5f98afc, 0x804c1ff7,
5781 0xb71f67f9, 0x6303fdd2, 0x9ee898c7, 0x3e41adbe, 0x9f0a6fd2, 0x3e70fa19,
5782 0xecfd116b, 0x4b945c4e, 0x241a74fb, 0x2e13da0b, 0x37bf106f, 0x082df805,
5783 0xf67fecaa, 0x478124ea, 0x689efd0b, 0x006f5883, 0x4e57e8ef, 0xc01fd652,
5784 0x88cfca3b, 0xd7074e46, 0x2c874e16, 0xe567e3c6, 0xf30d92d5, 0xf70de5ea,
5785 0x8a3e711b, 0x50bf85de, 0xfc545d35, 0x27f357a9, 0x7bad547d, 0x34fbe225,
5786 0x1887e553, 0xfc06993f, 0x0cd891be, 0xfc3df7fe, 0x5f77eddb, 0x2f7bf3ae,
5787 0xa78e1f72, 0xf44788ed, 0xdc7d12f3, 0xbac2f26e, 0xddf5d610, 0xf06b77a5,
5788 0x6bb9fe38, 0x249abf9c, 0x3b01c62b, 0xefc354f1, 0xf056cf6d, 0x788afc84,
5789 0x63279c6f, 0xf8837e79, 0xf9bf1fdd, 0xb5083ee2, 0x9d37171c, 0x906ffde2,
5790 0xbcc02c6c, 0x7fdfe47b, 0x927b6f90, 0x2d1f435f, 0xe413beff, 0x2efb823b,
5791 0x77e24ddc, 0x34231a19, 0x7dfec279, 0x35b01db8, 0xfd1cf808, 0x1b06c3e8,
5792 0x2fe0a7de, 0x3d62b1ef, 0xaadf7b43, 0x420f97ca, 0xb12e3180, 0x28ceccc5,
5793 0x76e5f470, 0x6edf5aa5, 0xb331620f, 0xbfee7ab2, 0x4f5ba09f, 0x1e528df6,
5794 0x5ea1e386, 0x54f1806c, 0x7d7f2cf9, 0xd7e5f8af, 0x0fc6579b, 0xce32979c,
5795 0xd87e7bdf, 0xfe799ac5, 0xd0245f02, 0x26dfe179, 0x9fa9bc63, 0x7bdf57a4,
5796 0xfe6fdcae, 0x3b3fe84f, 0xfee7a625, 0xf685bc59, 0x4efb2937, 0x0e3cfd94,
5797 0xf3fb130b, 0xae33fe6f, 0xfcec57e3, 0x8e9641fc, 0xae33707d, 0x3a06b90f,
5798 0x88e57ac7, 0x573fe281, 0x2e7bf026, 0xbf7b7f6f, 0xedf2f51e, 0xff0114a8,
5799 0xe44b67b7, 0xaec51d1f, 0x6d1da347, 0x80257da6, 0x1f9811bf, 0x1ca9a8c9,
5800 0x333ee78f, 0xe19678b7, 0x17de36d3, 0x6dd20efd, 0x7bf74c9c, 0xc6a3db34,
5801 0xc0fa3ae3, 0x71819659, 0xa9ef5877, 0x1621e67d, 0xd8c6f583, 0x18fdc863,
5802 0xb1f9f75d, 0xe8c70099, 0x0acdb223, 0x0fefa6f5, 0xf77cc50d, 0xe63af5c0,
5803 0x0c6be154, 0x73c32cf3, 0xed5ba33e, 0x22ee1133, 0x2e305fb0, 0x71b8d45f,
5804 0x2e439e19, 0x7b512f5a, 0x2939db97, 0xbdb3e61c, 0x4349b3fa, 0x3d401f50,
5805 0x9eb5c6ec, 0x48d573d7, 0xcf394c36, 0x24675c6f, 0xefc3517d, 0x91eed86f,
5806 0xebf79998, 0xdbbf4331, 0x2cfb43d7, 0xd05b638a, 0x7cd5720e, 0x5cdffb46,
5807 0xdfb52700, 0xccc5cfc6, 0x94567687, 0xa9fb9a97, 0x12f5e2bf, 0x457323c3,
5808 0x543af8db, 0xc360c474, 0x9f7b75ef, 0x2a74f5a5, 0x8a90978c, 0x02778eeb,
5809 0x884739c5, 0xffc77b7d, 0xed5df90f, 0xd58fd38c, 0x2feb92fc, 0x9fbf2989,
5810 0x4f9f57ab, 0x97d3e8eb, 0x2db10bef, 0x3f414631, 0x498a8cef, 0x7d5f11d5,
5811 0x71b4e746, 0xf013935f, 0x179c547d, 0x8cea3fdb, 0x409f7d51, 0x4f3f2b2f,
5812 0x8e30d05b, 0x321551ce, 0x9aa39d07, 0x8fdb9a36, 0xc828feef, 0xde33fb83,
5813 0xe37af835, 0xe23ffdfb, 0xb6dcd3bf, 0xb6dfeb9d, 0x1fda16e4, 0x307f1e7b,
5814 0xb65c6009, 0x717d265e, 0xce819b7e, 0x7018c90d, 0xe76dfc44, 0xf5fec5f6,
5815 0x5bf3dfbc, 0x7e361db8, 0x70931dc3, 0x59b05dbd, 0xf5c46739, 0xce3fe2b3,
5816 0x62f388b7, 0xfc8d1b95, 0x5fefacde, 0xac3d1477, 0xbf911efc, 0xfceb2d9e,
5817 0xc92f6cfd, 0xffad594f, 0x2ed0ccf9, 0xefe9043f, 0xb9f88afd, 0xa18188fc,
5818 0xb99d221f, 0x4f8ff944, 0xef871d70, 0x3b251ba3, 0x3a2a3b9e, 0x1d90f26e,
5819 0xdf7799ed, 0x393d71cf, 0x3afba261, 0x1cf055ce, 0xef9328f6, 0xf781bf2f,
5820 0xe3351c9f, 0x97e03cce, 0x05ef8479, 0x3be1116c, 0x473f336b, 0x2ab47597,
5821 0xe7ae3e76, 0x7fdc7813, 0x9cccb541, 0x89f0fd2a, 0x37799f64, 0x1ee8175f,
5822 0x598e856b, 0xb8f9cac6, 0xe562de9e, 0xd9bad8fa, 0x2fcde740, 0x760cfd08,
5823 0x5103dd3e, 0xac5d6bbc, 0xe2ff4551, 0xf8b175a6, 0xc42b2853, 0xe265b439,
5824 0x91b17a9c, 0x47bc538f, 0x8d546cb2, 0xf4a3f4a3, 0xdbc5dc6b, 0x67f135a5,
5825 0x2317fd4f, 0x2fcf347c, 0xfc27a88c, 0x7e36e9fb, 0x7a8cfd0f, 0xee155aff,
5826 0xaef51817, 0x8c72974c, 0x2d35333a, 0x0f643ef0, 0xd31fcf8f, 0x747f7e69,
5827 0x35825fd4, 0x6cba91f9, 0xdfa07790, 0x4edc0d6d, 0x653ecbab, 0xb2a2cb2c,
5828 0x5cbbe505, 0x27cb85c4, 0x75f57df0, 0xa3974719, 0x92cd4fbc, 0xdb981f88,
5829 0x29dfc469, 0x8accbb07, 0x5905a779, 0x6802fdbc, 0xf758728f, 0xd04b972c,
5830 0x1fd4560f, 0x830017ff, 0x8000007b, 0x00008000, 0x00088b1f, 0x00000000,
5831 0x7cedff00, 0x55537c7b, 0x393ef0b6, 0x526d3479, 0xa0fa5b42, 0xb4db4e50,
5832 0x9494b14d, 0x27457897, 0x880b5a3c, 0x46107006, 0xf4228206, 0xbd185499,
5833 0x35fde338, 0x9c414415, 0x0e7c570b, 0x42d2d37a, 0x1429a2c1, 0x20d5b16c,
5834 0xb47441d2, 0x3bd15ef6, 0x0f8afea3, 0x52d25a04, 0x8ef4f987, 0x6b5adfa3,
5835 0xa126d39f, 0xdf7ef515, 0x37f5375f, 0xef6758b3, 0xbdeb1fb3, 0xce275ef6,
5836 0x620a3b5d, 0xd67318e3, 0x319e920a, 0x6abd54d6, 0xc614f273, 0x2c8ba68a,
5837 0x67e7c242, 0xf01192b4, 0x2c7133e6, 0xd3e3b187, 0x1939db3f, 0x74339dda,
5838 0x7ff41d26, 0xc637d357, 0xf3ec6064, 0x991cc64a, 0x5ea5b388, 0x698459c0,
5839 0x8c09e2c2, 0x060e313d, 0xead8ca99, 0x0c0599e6, 0xeccddf9e, 0xf8bfb19b,
5840 0x7981f436, 0x47a20d5d, 0x2e9c0027, 0xc60dba8e, 0xc680f77d, 0x7e3b280a,
5841 0xfdda8e83, 0x153da007, 0x4faed8e0, 0xdcbfc004, 0xe86e61a5, 0xc89771b0,
5842 0xb2fff418, 0xc5f7a05e, 0x90597ee7, 0x3adaf804, 0x2983aac1, 0xad9aef8f,
5843 0x1efec24d, 0xd9bc61c0, 0xbc6869cf, 0x7f78fbb5, 0xc5e433f8, 0xf186b633,
5844 0xe2a635bf, 0x632e599b, 0x65a7cce5, 0x69efd0e9, 0x115da7cd, 0xf87bedbc,
5845 0x1827b15f, 0xc60fad2f, 0x4bb6d9cb, 0x6f403462, 0x750ef3f0, 0xef386dd7,
5846 0xb4f41bfa, 0xb637d9ee, 0xeb8f5e9c, 0x5c30d06e, 0xef1bece7, 0xba02ef8f,
5847 0x963351ae, 0x8e90693c, 0x0cc788e5, 0x559d8eb1, 0xb31fa4da, 0x1c75909e,
5848 0x3b8c6719, 0x63fc0d7b, 0x3df49b12, 0xb8dcee90, 0x628d8c91, 0x740b5dcc,
5849 0xb67e0049, 0xf00f360a, 0x4765b8a5, 0xf3d616bc, 0x02fdfe3d, 0xf11db6f0,
5850 0xb6d73c22, 0xbd2fd408, 0xad62c38d, 0x60aff16d, 0x0aafc51f, 0xb0696aa6,
5851 0xb9ce32bf, 0x7df10271, 0xbfef3373, 0xb5e015b1, 0xac5f8fc3, 0x0ac6bedd,
5852 0x65dd4a70, 0x72b864ad, 0xb17e651c, 0x739c782d, 0x8e857cb2, 0x2c1a2f97,
5853 0x10bba46a, 0xaf7e4569, 0xadbcb817, 0xdc799bbf, 0xacc94f20, 0x87406042,
5854 0x9013e644, 0xbd29c0df, 0x86fce41d, 0xcb55903e, 0xf17edd20, 0x1d5b0475,
5855 0x6c99c740, 0x3b3e1064, 0x7fa82922, 0xa83529be, 0xecc4a6fd, 0x52b9f6a0,
5856 0xdf3e105e, 0xff505d72, 0x4199d605, 0xe7d3adf8, 0x685ff506, 0xdb84185b,
5857 0xeb8d4998, 0xba5cad6f, 0x999073f8, 0x041d2b57, 0x70287a15, 0xd8c54e86,
5858 0xee0bc13f, 0xa036ec9b, 0x19288ccf, 0x3e397367, 0xd8d1f002, 0x06ddb37e,
5859 0x20919d74, 0xc7016ce3, 0x05f69593, 0xe538ffbc, 0xfb785bfd, 0x2dfb4a35,
5860 0xd2a27dbc, 0xafc72b7e, 0xf1eed467, 0x03776adc, 0x8ed1ebfe, 0xb6f8096a,
5861 0x138aebe4, 0xfde9a023, 0xa77745aa, 0x45583f02, 0x18d36306, 0x0034875b,
5862 0xed182ed6, 0x351a4a78, 0x7ff4aed8, 0xe357b255, 0xd14bdef3, 0x63226cb9,
5863 0x51dfc80d, 0xe6321f3f, 0x716779a3, 0x1159b2d2, 0x33ea1f06, 0x0cf4d08b,
5864 0x631a51e8, 0x0db18d82, 0x906f4831, 0x0477a213, 0x89a55f41, 0x8995ebe0,
5865 0x94a8df04, 0x63336ad8, 0x821695ed, 0xf4ad2b27, 0x74e554fc, 0xda576f82,
5866 0x5953be08, 0xd2a3b048, 0xe290504e, 0x9f1872d8, 0xa23eb1ed, 0xd5b87a41,
5867 0xfcc2cf23, 0x7e40cff8, 0xd4c64286, 0x1722acec, 0xcabf79d0, 0x65f48ad6,
5868 0x6ce98c6c, 0x5ef3e0d4, 0x815243a1, 0x46a7bade, 0x0f40eb58, 0xf37a0f8c,
5869 0x4617a04c, 0x11bac1a7, 0xe59c6168, 0xbb43524b, 0xbad69d71, 0x029fda11,
5870 0xf587ab73, 0xda991ad4, 0x1cc9f602, 0x34f1100f, 0xf7aa8d0e, 0x7fec0552,
5871 0x1ff5045f, 0x0236c603, 0x196825fa, 0x7de0f7c3, 0x1ffd8116, 0xdfd81163,
5872 0x684024fc, 0x10e1adaf, 0x37f48224, 0x43cde741, 0xe2e09efb, 0xd555d8eb,
5873 0xee304921, 0x5c7ca9ae, 0x29f13158, 0x8119cc5f, 0x499fb2f6, 0xb8394c23,
5874 0x005abd1f, 0x83d5e881, 0x2bb009df, 0x45034f59, 0xdb24f402, 0x01d4c113,
5875 0xbd4d757a, 0xe09f0829, 0x3fea0c4d, 0x6a0a59b1, 0x8259f3cf, 0xb49f27da,
5876 0x3b53e106, 0xbff507a6, 0x105b43f6, 0x61575d7e, 0xcfebff50, 0xfef083d9,
5877 0x618fd81c, 0x94defe78, 0x9ff50428, 0x703ade0b, 0x89aac67c, 0x232df33e,
5878 0x1bf79e83, 0x1b869d38, 0x78358177, 0xb71f855c, 0x7f1e0f4e, 0xdc782da1,
5879 0x3d87cb1f, 0x906a27a0, 0x13d07aff, 0x4f41fb84, 0x0de720d4, 0xbf8827a0,
5880 0xd0827a08, 0xcf827a0b, 0x209e820f, 0x827a04de, 0x13d011f8, 0x4f419bc4,
5881 0x3d051e10, 0xa357e7c1, 0xef3cbb57, 0x53de7949, 0xed8cbcf2, 0x8d5d3a20,
5882 0xefcb6f2e, 0xdfbf23bf, 0x079bef81, 0x30bcb0e5, 0xc835f543, 0xf398ccf3,
5883 0x87582eda, 0x01575d6d, 0x6f7d4dc6, 0x8246ac8a, 0xc9cf0e6e, 0x5aab8c4a,
5884 0x9456d962, 0x5bdf7b5f, 0xa70fc42a, 0xfb42b69b, 0x78ffe696, 0x4dfddb07,
5885 0xcdf184a2, 0x459fcdeb, 0x5f3d38e3, 0x2c753247, 0x3459f7be, 0xdf654bc6,
5886 0x42b7c230, 0xb9c5fa3b, 0xe5f3228d, 0xb57bbaa0, 0x5663ded8, 0xe3168f70,
5887 0xa3437b33, 0x5a52f916, 0x6fed48df, 0xedc1357a, 0xed41d5f5, 0xb00fec26,
5888 0x4689ed54, 0x56685e7a, 0xff51f3c6, 0xc3f73332, 0x6f8fea17, 0x5bd61ebe,
5889 0x562ab8de, 0x3697f584, 0xd77f17bc, 0xe2ffd00f, 0x1c721791, 0x0b797ef0,
5890 0x1c18678c, 0x2345bcaf, 0x65fd7ce3, 0x1882c6e6, 0x621a1ba0, 0x87acfcb0,
5891 0xc01b676d, 0xd736942e, 0x577c6195, 0xc343b96a, 0x5ebd3e80, 0x01d710b1,
5892 0x71062a7f, 0x9189995b, 0x7ef1e87f, 0x8c177d15, 0xc4f79afb, 0x7a87e82d,
5893 0xe3478f5b, 0xd04dbdbc, 0xabbf803f, 0xb11c7953, 0xfc4b553a, 0x1e3a69eb,
5894 0x16fb412d, 0x774e71ef, 0xfff68fb5, 0x02f78cba, 0x8b377a24, 0x5afa2e3c,
5895 0xc6507c45, 0x9a33a173, 0x4619ed8a, 0x97a757dc, 0xaa7f77cf, 0x579b9fc4,
5896 0x9ff5c6ad, 0x55365c4a, 0xae05fb24, 0xf1def01a, 0xc2b6ebf3, 0x30bd4a52,
5897 0xf7f210ee, 0xbb6e3ca8, 0x69bf471c, 0x1a3ed43e, 0x30aa7ee8, 0x807c8f36,
5898 0xaa636fdc, 0x6815fa8a, 0xe80ae61d, 0x8c9069d7, 0x160fcf28, 0xbf911ba6,
5899 0xe7c423af, 0x0eb5bb85, 0x7c4d2580, 0x47534ebe, 0x675dca34, 0xe31164d3,
5900 0x7fbc6551, 0x901de791, 0xb9be01ef, 0x9e454f89, 0x338e036a, 0xfcfe3fc8,
5901 0xbd1354fe, 0xdef3ca77, 0x7f603b92, 0x2b28969d, 0xcb5da5f2, 0xa5fd708a,
5902 0xbe7160e8, 0xa46ae4d6, 0xfddf3283, 0x2d7a3f32, 0xbfabe22a, 0xbbf72359,
5903 0xf5058ea3, 0xd57e70d3, 0xe4c7af06, 0x3bfbf339, 0x73d97fa0, 0xbef8c322,
5904 0x8f11534c, 0x20fcc7fb, 0x9d32dd68, 0xf8be34cb, 0x2d7900f8, 0x1bd0196b,
5905 0x8b79c903, 0xf11227a2, 0xa763e153, 0x4aebe445, 0x2c1879d4, 0x8eb1acb9,
5906 0xced41ae4, 0x4d3907ad, 0xff20ea8e, 0xdccffc97, 0xfc0ad54f, 0xfb2559b9,
5907 0xb5c7154d, 0x3e2fd100, 0x7853fb27, 0x1f00999f, 0x00146c0b, 0x4fa614d7,
5908 0x917c4155, 0x21e6362c, 0xb6a9753f, 0xff9854a6, 0xc87ec97d, 0x6489f142,
5909 0x553e43b4, 0x66e0d97e, 0x7efed023, 0xdbce24f4, 0x047904df, 0xd11e5bcc,
5910 0x9073ef3c, 0x282b7ecf, 0x7fb7ac08, 0x5ce28697, 0x00833b10, 0xe99acd71,
5911 0x94be5f5c, 0x8844d31c, 0x54abcb17, 0xc832afb4, 0x5f98f4bf, 0x62eef6c9,
5912 0x28adea63, 0x452765a7, 0x2be60453, 0x9d7fd4de, 0x86837881, 0x57a72af2,
5913 0xff30fab0, 0x255a326b, 0x9deacfc0, 0x9d379869, 0xe2d3eaad, 0x3e21677b,
5914 0xcbcf9c7f, 0xa7cb4f50, 0xd4519f73, 0x193da3bc, 0x57e60960, 0xafc8cfe2,
5915 0x3a99f242, 0x8c75c7fc, 0xf21539fd, 0xb26f8c1a, 0x37c63659, 0x048ce2f9,
5916 0x7f995fd2, 0x1710276c, 0x13f5a612, 0xdfa809ac, 0x3cd2d45b, 0xab6f77dc,
5917 0x71f484c6, 0xc62a1db5, 0x22ca7b75, 0xafd82aad, 0xa251c373, 0x815fef63,
5918 0xf65710ce, 0x33ca3226, 0x67a7197b, 0x6797336f, 0x44f04697, 0x9e20fbe0,
5919 0xe0845e34, 0x5ea682a9, 0xd9347f77, 0x510ac621, 0xcb2dd7fe, 0x68bc6150,
5920 0x80337203, 0x57b91447, 0xf5c0a5fc, 0x977546fc, 0x7bde1238, 0xe7fdc343,
5921 0x48d353df, 0x9968e7ee, 0x46f5f103, 0xc62bf92b, 0x887de8aa, 0x52fe28a7,
5922 0x67c435fc, 0xc7254f14, 0x147e497a, 0x6d50bc3f, 0xab8e04d2, 0x821bdfbc,
5923 0x0580f32b, 0xe0ede3e1, 0xf8c0def1, 0xa6fc7923, 0x1e740f8c, 0x6afe7481,
5924 0x70fc958a, 0x91f042ca, 0xa41577a4, 0xf59e8a77, 0x01cd5c80, 0x3810cab9,
5925 0x1d76cabf, 0x728073a3, 0x00e741d6, 0xde7cd105, 0xf11f9c02, 0xd2130e48,
5926 0xedffda04, 0xdb5e9c69, 0xa7d8a864, 0xc4b66913, 0x698d8034, 0xa469318e,
5927 0xb792261f, 0x408cb2f5, 0x35d0927c, 0xf75d7d84, 0xf06e7e27, 0xda3dc815,
5928 0x08575f99, 0xfe203992, 0x6ed3fd29, 0x69c34b2d, 0x18161d6c, 0xbd7188af,
5929 0xc5d9e451, 0x1b95b2bb, 0x303992f4, 0x7fc3b2fe, 0x72c567a0, 0x279e117b,
5930 0xd8e0fe40, 0x27992f10, 0x8f627bc3, 0x4fd73c16, 0x73577396, 0x73d3ee30,
5931 0x0519f379, 0xffc9c60f, 0xf5e72694, 0xc8a7fcb2, 0x10ed58f2, 0xabdf683c,
5932 0xee1355bf, 0x90782e5e, 0x8784bf07, 0x45e4621b, 0x99a2bf62, 0xbf47f41e,
5933 0x8ef29404, 0x2fa4719d, 0xb9fb08d4, 0x2fffde4d, 0x0263bed5, 0xc684e7ec,
5934 0xc2f98a9b, 0x2b08f289, 0x418cbf8e, 0x64f60180, 0x7820eb39, 0xd879ca3a,
5935 0xc7bb8347, 0x81ff3c62, 0xf8c56743, 0x8d537aa7, 0x2e66ed11, 0x3cc264db,
5936 0xff514805, 0x9f1fe4fd, 0x0b8830cf, 0x5f0aff90, 0xcbecd31b, 0x073f00d2,
5937 0x749c493c, 0xefa5fbe5, 0x3e468e1f, 0xd0e6ff76, 0xda19db92, 0x3bb23e9d,
5938 0x1a551525, 0xa8c41c9c, 0x906d32c3, 0xe0bf0abf, 0x1f1052df, 0x90630f61,
5939 0x42cf622e, 0x177ffbd2, 0xabb1fa19, 0xf3a151f1, 0xac7e642f, 0x21f6e16d,
5940 0xdd0abf94, 0xa21e676f, 0x5daff81f, 0x23a617c4, 0xffca147b, 0x0407f1ab,
5941 0xcd363971, 0xe431d38e, 0xdb8ab26b, 0x2035e4ab, 0x3beeb02f, 0x0bada398,
5942 0x8fa892e0, 0x32e72434, 0x7ccb969f, 0x167980fa, 0xdfff5258, 0x9a44e9f1,
5943 0xe91a7b63, 0xfd4869ad, 0x32c7d50c, 0xe2aefac9, 0x67a43c6f, 0x3579fac1,
5944 0xf85664bd, 0x8e7f802f, 0x7fa4d10d, 0x625d7f0a, 0xd5f7e903, 0xad18f3cf,
5945 0xf059bcab, 0x847f52f8, 0x10b00a5e, 0x884363e0, 0x1afc2a3e, 0xf6291ece,
5946 0xfb96b4ec, 0xa27df763, 0x8ff2f307, 0x1309df05, 0xceeca7da, 0xd282640c,
5947 0x8eaae3ff, 0x38c0f7b1, 0xf0e4cf1f, 0x0159c634, 0xad922db8, 0xa49e23b4,
5948 0x3f7ee373, 0xa167b216, 0xf858fe7f, 0x9e385be7, 0x5f1095a0, 0x04cb3096,
5949 0xef0d69f8, 0xc57dd8af, 0xecbc7fde, 0x4fd439da, 0xbee06f60, 0x47a25c60,
5950 0xa782fddf, 0x256a4406, 0x5f5c6a98, 0x0aa7acea, 0x27f9e0d3, 0x43cf4dbf,
5951 0x05d6d87e, 0x2e7e878f, 0x3ce22275, 0xebf1baef, 0x9caacd3e, 0xfc0679c1,
5952 0xf44b9cd4, 0xfd53f15c, 0xb25a1965, 0x2833ab53, 0x69922fde, 0x1ec98b6d,
5953 0x87f829f1, 0x08fa4f7e, 0x5fa0ce55, 0xc8793fe9, 0xefa008e0, 0x4c3bf079,
5954 0x3f67801b, 0x97e81296, 0x3479ed8e, 0xa451f913, 0xb9e2e775, 0x3feab9e3,
5955 0x2edfa0a4, 0x2670f3da, 0xb67b8dc5, 0x5ffc6264, 0xa668f354, 0x0728f08d,
5956 0x4e6a1fe5, 0xd703ee87, 0x101adeed, 0xf26526a7, 0xc47979f8, 0x1f8c7cb1,
5957 0xf1735de7, 0xcbf41321, 0x4260adf8, 0xeb35f831, 0xddfd0878, 0x77970b0a,
5958 0xec8233b6, 0x43678c31, 0x2f65d7be, 0x3d7d45a8, 0xb34cf965, 0x74bfe31a,
5959 0x056bd135, 0x804b6cf3, 0x6088f676, 0xfd8163aa, 0xff6356c7, 0x6d049b55,
5960 0xb1fa1c62, 0x97987991, 0xd247d2e9, 0x247cee3a, 0xaf9f1daf, 0x9f3f8078,
5961 0x7534f3a7, 0x694f38e2, 0x37a475ad, 0x278c34f6, 0xd2ebf595, 0xcadef4b5,
5962 0xcbc5026d, 0x4f193cca, 0xee0757c6, 0xfdce9753, 0x8db29b32, 0x32adcfec,
5963 0xe07e6e5f, 0x611237bd, 0x1d6349dc, 0x7f6874c6, 0x66b389e7, 0x139f3c1f,
5964 0xf3073e73, 0xe3ad0c86, 0x77dc62d9, 0xfb8ace8d, 0x2c9b9298, 0xdfff6026,
5965 0xe11c7ccc, 0x3d5607ca, 0xf2768c5b, 0x73ca08e9, 0x13adf594, 0x83e61524,
5966 0xbf6fabc7, 0xee76e913, 0x778a0889, 0x256755d7, 0xdfc81fb0, 0xa5ff02f7,
5967 0x41f6c64c, 0x05f08efe, 0xd825dfc8, 0x44ca81e2, 0x94aa5fc2, 0x5ca5b208,
5968 0xb899d6be, 0xbc6e193d, 0x4b9790c9, 0x3ca64760, 0x7c41e302, 0xcd9c6f38,
5969 0xcaf40e92, 0xb35e5f18, 0x0657de45, 0x4ee79fbc, 0x98748d9d, 0x769ee5b2,
5970 0xd2e31d0c, 0x56f2fe79, 0xa82923e7, 0x381f6bc7, 0xb4317cf3, 0xe7b74aaf,
5971 0xbb11fbe1, 0x7e3e512e, 0x15e1e5bc, 0x1aa2ef48, 0xbc9fdf1d, 0x644f73ef,
5972 0xe78b3c26, 0x286a6f75, 0x3aed763f, 0x8016fcf3, 0x47bb6d77, 0x3fef281b,
5973 0x7113bf76, 0xba7f533d, 0x97470d9e, 0x8f67ae9f, 0xd53e90a6, 0xfce59e80,
5974 0x3d733d7c, 0xdcf44550, 0x15ff6e9c, 0x8d39dbca, 0xebf5053b, 0x240df65c,
5975 0x8136eef7, 0x5fd8a1f8, 0xf2a5fde5, 0xde554bfe, 0xce02336d, 0xc6432f15,
5976 0xd63ef486, 0xc62665f2, 0x979b97b5, 0x47dc088d, 0xfb023c28, 0x35864c86,
5977 0xda7dbd03, 0x69a7db2b, 0xd856e91d, 0x8f1534df, 0xabdb4367, 0xbdb255d2,
5978 0xcf0ffc85, 0xc5ff1433, 0x0f78b43a, 0xf82ad651, 0xaa3ef122, 0x6af3a6f9,
5979 0xd81257ba, 0x7de741a7, 0xe01a7d8c, 0xe75b8777, 0xc713a0d5, 0xe3da0f51,
5980 0x31543f6b, 0xbdbf805f, 0xf9922bae, 0xc81de602, 0x114f6023, 0x4b7f1fc0,
5981 0xd87d9052, 0xe7042e9e, 0x36aef013, 0x15f21fa0, 0x2dfc65ef, 0x9f8835d9,
5982 0xfb3e72d7, 0xc47c408f, 0x389849cf, 0xe71e906d, 0xd173ba5b, 0x70f42b2e,
5983 0xb926ed1e, 0xf87e6b29, 0x99f44092, 0x7b9d5e7b, 0xdb1cfa75, 0x7c8b9dd3,
5984 0x9ae9af3d, 0x5f947986, 0xfc8b95db, 0xedc2be71, 0x93a54ffe, 0x11f8bcf2,
5985 0x05d800d8, 0x3ca260a7, 0xa1ec5f2f, 0x927fdcbc, 0x96cee5e7, 0xfb7764dd,
5986 0x88b9f95b, 0x9051d54b, 0x1508e780, 0xeed1da67, 0xfcf227f5, 0x21b7c609,
5987 0xcba466bd, 0x97dd53fe, 0xdfec10b2, 0xe1390189, 0xd439da79, 0xe38e2d73,
5988 0xc17b432d, 0x1d58a372, 0xf501778c, 0xd8af9e1e, 0xe519ba90, 0xd4679cff,
5989 0x6fa3b424, 0x49ddfee5, 0x45af68e7, 0x638a4499, 0x7f0069e0, 0x11e1f607,
5990 0x1e282d99, 0x80b6628a, 0x74ad2e7e, 0xa7bfc52b, 0x74c7ba44, 0xc67ae78d,
5991 0x2b3d728e, 0x9b4c74df, 0xa35e3018, 0x7894f76c, 0x7f6bde70, 0x345d7d27,
5992 0xf023b991, 0x14f597bd, 0x2031b0e7, 0x7a2f80ff, 0xf283c139, 0xdca8f7e0,
5993 0x178bc81a, 0x87fee64d, 0x7ef1d21d, 0xa454d289, 0x6af31f87, 0x4c794fa0,
5994 0xc00c6647, 0x2b89df23, 0x4e4f98ed, 0x2be01c02, 0xf2cf9702, 0x23991d45,
5995 0xd0495cf1, 0xa4bcf0ab, 0x77b786bc, 0x54bc78aa, 0xf7dfc69e, 0x7b57dc0f,
5996 0xde821653, 0x9cbdb6f5, 0x5be02772, 0x9c35be0d, 0x7c4cbe0f, 0xb99eda0e,
5997 0x46efe608, 0x5cf74d9f, 0x5ed08be5, 0xdc151b75, 0xf78c71c9, 0xb5cd9ee9,
5998 0x5baae508, 0xbc15e0af, 0x5c64105d, 0xe5c15f79, 0x8c8547f7, 0xb4859237,
5999 0x0a4ff487, 0x3dca35c1, 0x58ff3c9c, 0xb517fefe, 0x7bc22cf7, 0xcf3af9b7,
6000 0x57f44ac9, 0xd218692f, 0xf0e07f55, 0x697fa459, 0xb33bf70b, 0x39ee1c0e,
6001 0xd872f288, 0xb1e6f748, 0xe3e254e6, 0xdbbd96c6, 0x375ca126, 0xada073f2,
6002 0xff3fef0d, 0xc3a7ea3b, 0x57183163, 0xe69eb759, 0xebca2f9d, 0x1e39eb66,
6003 0xdfb3b725, 0xb2847c72, 0x3c71dfaf, 0x6b7fb796, 0xa75a17fe, 0xfb81f0ff,
6004 0x9fa05e50, 0x17a5e29b, 0xa2605e40, 0x73d94392, 0x1bf59e30, 0xfce0563b,
6005 0xab3afdce, 0x09e7c25b, 0x95be30b3, 0xa4dcfccc, 0x14f6fc78, 0x4754a7cc,
6006 0x1df9edf7, 0xd7efbb9e, 0x2ba139d3, 0x12a5db86, 0x3dda7ab1, 0xf7bb3f24,
6007 0xb5f701fc, 0xf6e74f4f, 0x1edcd1c5, 0xa0c9ef15, 0xfe579ef3, 0x940ad9f1,
6008 0xd7717c83, 0xd7fe7c1e, 0xe90abd5a, 0x8db5a9d4, 0x4cfd01b8, 0xa9e286a7,
6009 0x3e2f1962, 0x13d7cb1d, 0xf24055d5, 0x653db713, 0x4948c811, 0xe0b7fdec,
6010 0xdb8be7ba, 0xce7f479f, 0x0ce8eaf6, 0xa03efceb, 0xbe77bc2b, 0x2da7434e,
6011 0x35467dfe, 0xb0b76bca, 0x38b3c57d, 0xd7ef1d7e, 0xf44edfad, 0x3165d776,
6012 0x31fa0f9c, 0x16ea9f3c, 0x3f3d0476, 0x1737b75f, 0xfb0bade3, 0xa5dc53e7,
6013 0x97a293e8, 0x20bab525, 0x293fc7fd, 0xf963f31e, 0x8666e4cf, 0xc2e9fc80,
6014 0xcffc6791, 0x85f5e806, 0x0b4f8d06, 0xb1d62a34, 0xa7af784d, 0xf24963e8,
6015 0xbfb8854d, 0xe6755512, 0x278bc03a, 0xbd40ad77, 0x1167af3c, 0x2defd089,
6016 0x2e0f3f15, 0x885aaa69, 0xf5b87b76, 0x7c799b14, 0x9f913979, 0xd66e5f97,
6017 0xa9cf027b, 0x9547e143, 0x3d5b7a4c, 0x42baff88, 0x19473e47, 0xb7ad2def,
6018 0x670ee30c, 0x9fc3f70c, 0x3306ff40, 0xee6661c4, 0x086e56a7, 0x1cdcbfee,
6019 0xda9dcf43, 0xcbb44cae, 0xcccbf8ca, 0xd4cf6e26, 0x9fe8995d, 0x7923df43,
6020 0x82f57b47, 0xa4aaf640, 0xf7433849, 0xf8d248c7, 0x44967a41, 0xee623db8,
6021 0x9c487cd0, 0xc601f326, 0x77ac87fa, 0x9b7a0d25, 0x8d29c61e, 0x7f468aec,
6022 0x8aec6655, 0xff6f73c6, 0xc8d59151, 0xc6538bec, 0x4f9c1b4f, 0xbd8b8fc9,
6023 0xa87e9b1a, 0x183b60f9, 0x7fc5adef, 0x32622903, 0x3514deb8, 0xcc7cd147,
6024 0xe50d35d4, 0xf05768b6, 0x534fb87b, 0x9bfa3e80, 0xc607c777, 0x75c7bfa1,
6025 0x8677de53, 0x1ff7a6f4, 0x1ca0a69f, 0x26d8a894, 0x20bee73c, 0xc0617bf0,
6026 0x82f85ee9, 0xf25e5e7c, 0xca244337, 0x65cb85cf, 0x01fec7a4, 0xd928fb3b,
6027 0x6762bf07, 0x15c70d59, 0x7076cb3b, 0xeecec07c, 0x3762b8e2, 0x42a3fe95,
6028 0x1d0a4fde, 0x9077a94f, 0xe6ed93c7, 0x6e7abaa2, 0x7f7e4537, 0x4c6b76c7,
6029 0xfce27f3c, 0x19d32b5a, 0x95d3b412, 0x123577e4, 0x19c5b1fa, 0x76a579ca,
6030 0xa0e27e90, 0x7499fa3e, 0xbbf509a0, 0x10f940c8, 0x070d15c4, 0x59791cf1,
6031 0x07ef15bc, 0x9caee943, 0x7cc5c777, 0x7cf906b3, 0x8af1d6ab, 0x7269ef19,
6032 0x82afc8ba, 0x74bf90b6, 0xb8a3aabe, 0xb7d357aa, 0x965fed07, 0xf61af1d6,
6033 0x6c76d32b, 0xea4b029e, 0xe3b574d1, 0x943cd091, 0x5c43b257, 0xbb39fd5e,
6034 0x39527ce9, 0xe6577f2f, 0x5ea70323, 0x7025f28d, 0x7cde3939, 0x57b46de8,
6035 0xf2748efe, 0x03e45703, 0xa3478fcd, 0xe210f9dd, 0x5c407714, 0xbdaae1fc,
6036 0x14b50f74, 0xde011fef, 0x7f7829b9, 0xa62edffd, 0x0b6d8838, 0xbcf28e78,
6037 0xa50f1833, 0x2fb5ca0b, 0x24dc8f48, 0x9ba5dfc7, 0xeace9608, 0x061d2270,
6038 0x8b8045f0, 0x21ebf801, 0x667f4878, 0x1e6266f7, 0x08d61dfa, 0xc6ca3d01,
6039 0xbc534efa, 0xd0c3407a, 0xbf046c3f, 0x28e1f849, 0x1d532baa, 0xc718bf00,
6040 0x9bfa22fd, 0xca0ee8d2, 0x7587fceb, 0x60f0df74, 0xb82997cb, 0x8ba6bf7f,
6041 0x96d295f2, 0x9e31e397, 0x344b358d, 0x78dff83e, 0xdc3d8fba, 0xb6318f12,
6042 0xe54cbcf2, 0x94eb94cd, 0x28fed172, 0x5f45cbcf, 0x54bfae26, 0xf6c5c8e8,
6043 0xd453b458, 0x7111701f, 0x1328fb46, 0x2d60ddb8, 0x5089f922, 0x706745be,
6044 0x25f60bbb, 0x8f11ee97, 0xb15978f2, 0x605f6427, 0x79f1d7bc, 0x261fb70e,
6045 0x5e14fce5, 0x31bb462d, 0xa4d99d84, 0x41564dd8, 0x06644d79, 0x3ef2b75f,
6046 0x30f3cb8d, 0xd2be776a, 0x83969b9d, 0x7bf249ef, 0x7d2cf601, 0x1da13ed0,
6047 0xf23b2449, 0xf61e26a0, 0x60bcf255, 0x14af08dd, 0x802aaf2f, 0xfaad6cee,
6048 0x2fca029e, 0x19ee9b99, 0x8575d742, 0x7f39997e, 0xd2f3e44b, 0xbcfc3d92,
6049 0x9f8682f4, 0xf2bd832f, 0x3b5afda1, 0xf500aaa7, 0x72b8eeef, 0xdcb9e06d,
6050 0xb35fc6d5, 0x5b5f1833, 0x30905551, 0x6c979e84, 0x8a3ed1d8, 0x1d17e10d,
6051 0xd2f105d5, 0x7595cf95, 0xeb2bd05f, 0x1519a59c, 0x55a58f48, 0xae00a305,
6052 0xf4b9f88d, 0xd0befbe0, 0xdfa1f3a2, 0xf9d2fa06, 0x575f8de9, 0x5c3f9d04,
6053 0xe662bc6d, 0xe1c2f3a1, 0xcb0a1fd6, 0xcc69df04, 0x57e818a3, 0xe819e91d,
6054 0x2f7cc04d, 0xb4fbfeca, 0x9e78a04a, 0x871aad15, 0xac7301f9, 0x6b7e871a,
6055 0x0c0178b8, 0xdd1568e5, 0x8209ba49, 0x0eb0ae1e, 0xffa50f41, 0xbcfc191d,
6056 0xaf5945e1, 0x7d2fcf46, 0x9fb420e6, 0x19456c96, 0x5c28a8c0, 0x8945e623,
6057 0xda183c23, 0x7203be53, 0x036394ed, 0x5f7cab43, 0xbb522858, 0x586459ab,
6058 0x8d12caa7, 0x57d80c9e, 0xf54edb21, 0x7798f37b, 0xa9791506, 0x3d7f7ebb,
6059 0x4d7fcfb4, 0xd195bc9c, 0x37e50f7d, 0x330e9105, 0x5fb055c6, 0x4ef43f39,
6060 0x7e701859, 0x37f647b7, 0xfc814433, 0x14525f40, 0x5dced39d, 0x503cbe5a,
6061 0x10853b4e, 0x72fa79ba, 0xf5f1bf29, 0x6dd206e5, 0x15516bc9, 0xbcc80e74,
6062 0xcc049653, 0xaf0672f3, 0x696af89f, 0xb8979d06, 0xd27bf32e, 0x27dbf17c,
6063 0xd7588f31, 0x80af7906, 0x407ea7e3, 0x2f906675, 0x0dd09c62, 0xcc1ce9f9,
6064 0x66cc1df5, 0x61387b43, 0xae7be514, 0x7ac30203, 0xae8b6733, 0x9d9bef06,
6065 0x8c78ae9a, 0xbf34b673, 0xec3f45af, 0x569efc3a, 0x92abbcc2, 0x2637f5c9,
6066 0x05d7d215, 0x5bbf40ec, 0x01f59cde, 0x93f2b5da, 0x5cb0d4fc, 0x3fdd1efd,
6067 0xce14b9e2, 0x48d4da57, 0xcc658df7, 0xd65f7247, 0xf6ff9c10, 0x075d0e27,
6068 0xa76cb2f4, 0xd3ee7c14, 0x225fcf3c, 0xb72f0ab2, 0xce9f148b, 0x73a04c4d,
6069 0x38f7c1d8, 0xf7626d7d, 0xdb6e7843, 0x0558269b, 0xd237aa18, 0x26e309bd,
6070 0xc73f2677, 0x85f57ded, 0x7ce86b29, 0xeb0533c4, 0x73e57ba4, 0xec8fb9fc,
6071 0xeb018b50, 0xebcadb99, 0x59237a17, 0xbbe211d1, 0x23f20c63, 0x92ded52b,
6072 0xb6967181, 0xf1eb9def, 0xaf8e59de, 0x57b1f743, 0x253e6fbe, 0xbacae9c7,
6073 0xf32727e7, 0x21e618f3, 0xf3976a39, 0xda0a9b62, 0x4cd3ee03, 0x77528299,
6074 0x046befc7, 0x9c3e8f7e, 0x17bd617e, 0xbd623bd6, 0x72fdc217, 0x7bd6245d,
6075 0x5ca2fe21, 0x5ef58917, 0xbdeb1cf8, 0xeb926f10, 0x0bdeb122, 0x42f7ac71,
6076 0x8bae5478, 0xa54b853c, 0xbfd2eef8, 0x3edb9e61, 0xfc721f10, 0x3e084c74,
6077 0xe9ffb83a, 0x1f182118, 0x33ff502d, 0xcdfe9775, 0x1675839d, 0xf0dfd926,
6078 0x9ce50b3a, 0xb670b3ab, 0xb1f20779, 0x3c24c275, 0x69266747, 0xb74bea04,
6079 0x56ffe7cc, 0x1da02fdb, 0xe47d1160, 0x64c4e797, 0x78bb408f, 0xba62e4f2,
6080 0xd38feb87, 0x93bc3e91, 0x7ec3e8ee, 0x9e6f98ae, 0xeb06cc3f, 0x265a66e6,
6081 0xfc029a6f, 0xe4106998, 0x44fb7238, 0x059f72bb, 0xbadd99fc, 0xdb9a8a6a,
6082 0x994e130b, 0xc6ad962f, 0xe925d771, 0xaa1e6327, 0x1dfc734b, 0x5fe855c7,
6083 0x19ad7a30, 0x48d76fe7, 0xeabc601f, 0xf3cf13fe, 0xa501fa95, 0x33a927df,
6084 0xdef099f5, 0x26fa4b5c, 0x2819ebcc, 0x4dbc8a1f, 0x3e501acb, 0x6128aa6c,
6085 0x4933d923, 0x67d5fb8d, 0x92cefdf2, 0x4f80fdf8, 0x6063a92b, 0xcce45f7c,
6086 0xdb77cc38, 0x949fbe65, 0xe64a7ef9, 0xcdd1d63b, 0x3a3af351, 0x87475884,
6087 0x20ea10f0, 0xdd2fbfcc, 0x7149931e, 0xd20a5f72, 0x984ba95d, 0xedc67a87,
6088 0xf5d20a4f, 0x27c72c90, 0x99d3fb64, 0xefe24f66, 0x54acf8f1, 0x96e81fae,
6089 0x7d9473cf, 0xbe0def2a, 0xfb05e7cf, 0x6ffee12d, 0x5f645510, 0x5b38e543,
6090 0x788efb96, 0xbd4abde3, 0x3739c608, 0x261fdc88, 0x41dffaab, 0x6f1c93bb,
6091 0x90c23694, 0x78a3b3f9, 0x09bd36bf, 0xdb6f6c4d, 0xddce7437, 0x296190fb,
6092 0x30314fbf, 0x3da11efc, 0xe04d4271, 0xe51fe979, 0x908fc079, 0x9a2cba5e,
6093 0x3923f61f, 0x423f01c6, 0x144e66f9, 0x9bf923dd, 0xa4fca2bf, 0x09aa75b7,
6094 0xe1dfd4e5, 0x715fa031, 0xc4ffe3fd, 0xb7f0bfa3, 0x6cf5417e, 0xa4bf6ffe,
6095 0x722db73a, 0xcdebe1bd, 0x87589d72, 0xbde7c464, 0x60159f85, 0x1c32adbf,
6096 0x3cfc23b4, 0x686f814f, 0x681de66c, 0x51509ecf, 0x8dd8a2fe, 0x98597d50,
6097 0xf78e5239, 0x676831ec, 0xc4ec5f40, 0x597d01b7, 0xc1798316, 0x12917da0,
6098 0x132ea87e, 0xcd598bed, 0xb4420bed, 0xb733662f, 0x7da3882f, 0x05f68841,
6099 0x417da39f, 0xe20bed1c, 0x47105f68, 0xed1082fb, 0xebff3e0b, 0xd3a75e52,
6100 0x3f29810b, 0x5c5035c7, 0x7f8ebebf, 0x8dbeb27f, 0xafaddbdf, 0xac0ea816,
6101 0x94dfe607, 0x509d4439, 0xe4275c93, 0xa2f741dd, 0x15a2c3ae, 0xd6017859,
6102 0x6dcf09bd, 0xd0277d35, 0x051ab82f, 0xcf84956b, 0xb63ad297, 0x60fd4eb4,
6103 0xd3af3e39, 0x2fe85558, 0xa3c72f5a, 0xad692bdf, 0x2735ff23, 0xbfcb4da1,
6104 0x9e181197, 0x71d12f1f, 0xe11728fd, 0x3fba24e9, 0xae5ffb26, 0xad73a0eb,
6105 0x0a417ad2, 0x35c08efc, 0x7fc512fd, 0xf2b9fdca, 0x57b94bdd, 0xca0ead2f,
6106 0x6ebc6c9f, 0x4aff718b, 0x9e406579, 0xc3277cab, 0x74d56fc4, 0xc08afe3f,
6107 0xd7ab8562, 0x36b49573, 0xaffac66e, 0xb4767bd0, 0x16d75424, 0x44febf72,
6108 0x95d75ca6, 0x6f30f2c7, 0xf5627c2e, 0x5f30c381, 0xe51d76ff, 0x774f609d,
6109 0x409efea1, 0x9cba0439, 0xb9d3d368, 0xb23be7db, 0xde1f1046, 0xf6489914,
6110 0xb7d90c72, 0xf2811a75, 0x3597b031, 0xc2ecdef8, 0xceaec8bb, 0xfc8abb06,
6111 0x93eee454, 0xca2d7b54, 0x1209bae7, 0x1d7cb9f9, 0x93c697bb, 0x9200c5eb,
6112 0x146fe5de, 0x57c02a3c, 0x2f7d2b31, 0x86c812b4, 0xc6af50f1, 0x75d608f0,
6113 0xaebc64ad, 0x75a39143, 0x8eef943b, 0x577d10c6, 0xd95cf4c8, 0xb06fc7fa,
6114 0x1d2ee36e, 0x56490f3f, 0xe4803af1, 0xe7bebcad, 0xf5e0e66e, 0x8b4d9872,
6115 0xdabd2f94, 0x511dcf05, 0x79f85263, 0xe380948f, 0xa1a53aaf, 0x84fce33a,
6116 0x8a0e9905, 0xfd50e64f, 0x43bbe086, 0x1f9afefc, 0xeb83878a, 0xec684e37,
6117 0x3b573df4, 0x73d925ca, 0x9553c107, 0xbb150445, 0xf63fd4ad, 0x88dcbdb6,
6118 0x0cbbe7f3, 0x62b7a456, 0x83a8ae07, 0xa950e48c, 0x100b1c83, 0xc0cc0aeb,
6119 0xda0c5363, 0x44ec8967, 0xb273aab2, 0x1bfffb84, 0x3f200eff, 0xe30f2da1,
6120 0xfc7974a6, 0x43fd92d3, 0x9a2d9fe4, 0xbc3df1b9, 0xf40eda4f, 0x080dc02c,
6121 0x6d7b2f18, 0x6dbfc622, 0x1a46a982, 0x78ee8eca, 0x5c97eb08, 0x7184c166,
6122 0xf6e44159, 0xbf1878fc, 0x8ad52d20, 0xccd5dc76, 0x403f2de3, 0x3debf7ce,
6123 0x55dfc0a2, 0xce9c63c7, 0xea9596f9, 0x351ccee8, 0xacbe7cf8, 0x5fadbd4f,
6124 0xabe3faf1, 0x38b563c7, 0xade99bbe, 0xc8f8f275, 0x8cd7f9f7, 0x914cb8a5,
6125 0x8486fe9b, 0xef9b941a, 0x7cbbff65, 0xcc1a7bf9, 0x1cd33b03, 0xaff38dff,
6126 0xa1e97d58, 0xd0e7da78, 0xd3a9507e, 0x4a83f50f, 0xabfff37c, 0xcaedff3e,
6127 0x54ef820a, 0x51d8206e, 0x51f6a6e9, 0x735cfc59, 0xfc0ab8b8, 0x10d65c43,
6128 0xbf4294f1, 0xe4aae221, 0xae3ca9ac, 0x89473cc2, 0xa388aeab, 0x0155df40,
6129 0x75bb3efa, 0x608f9de4, 0x6b53b3dc, 0xeb0090c5, 0xc81bd7a8, 0x4d64643e,
6130 0x529e2a1d, 0xf8a069e8, 0x27e99fab, 0x2cb3fce1, 0x1fbc6ae9, 0x0425989f,
6131 0x3fa80be5, 0x1fd46fb8, 0xea3fa884, 0x39e7b880, 0x14f6a82d, 0x29b82f1e,
6132 0xbf13d05e, 0x5d815737, 0x662efc01, 0x3d2bb20a, 0x31857621, 0x1d70affb,
6133 0x9d795a6b, 0x3a5f5297, 0x93d7c00b, 0x5e33b086, 0x46c6676e, 0x3ce1f77a,
6134 0x54919d63, 0xc3427caf, 0x16c4eee5, 0x9ab82f5e, 0x8ff7f9d9, 0x689bda57,
6135 0xb15defa4, 0x01fc9f7d, 0xa8f5dffa, 0xcd9ee281, 0xfda66b49, 0xf8cdec4f,
6136 0x7f0f4e2c, 0xe7de6fa5, 0x22731f20, 0x905cf7f9, 0xee2859bb, 0x7e924555,
6137 0x8ed97e40, 0x6bac57df, 0x8ed0f211, 0x77d9d1cf, 0x6a9d3ae1, 0x27167ebe,
6138 0x3baa27df, 0xbf42f78a, 0x2b64f8ce, 0x1263cfe6, 0xffac308f, 0xe61577ca,
6139 0x64ecbda0, 0xbf7be9db, 0x5dc73a8d, 0x39c5e7c8, 0x7b9d0215, 0x5897faca,
6140 0x95b35518, 0x153591f8, 0x2708bef9, 0xe6e473a3, 0x2e8f98c5, 0xf1c10a8a,
6141 0x8dce8b1e, 0x6c78e55f, 0xd2827b48, 0x1cc9e32e, 0x2f356777, 0xd2e573c6,
6142 0xf3e9bd7a, 0x91cffaa0, 0x39abb841, 0x6079f4c9, 0x03fe2a7d, 0x822daecf,
6143 0x93dc059a, 0x078e0837, 0x85e53f70, 0x2e39f917, 0x5abf23eb, 0x7d112595,
6144 0x7ccebd47, 0x737dff28, 0x902e748d, 0x87915b10, 0x472c09e7, 0x52fd8a9a,
6145 0x17147d34, 0x96ab7ef6, 0x8be8b3bf, 0xef202dbe, 0x7f95be7f, 0xcfca117f,
6146 0x7b970b3c, 0x0db0d997, 0x8c4ce6f9, 0x7ad82088, 0xa616e289, 0xdef19bb6,
6147 0x3a0af214, 0x3f7d08b7, 0xb7efc2dd, 0x656b3753, 0x90ff813a, 0x8e337ae4,
6148 0xc674d9bb, 0x948befaa, 0x266ccae9, 0x866d3ff8, 0xfcffc64a, 0x0113e638,
6149 0x7fd86dfd, 0x6b5f9db0, 0xf77bef2b, 0x26f8fbbe, 0xca1f3cb3, 0xf1461ad7,
6150 0xa0f7e873, 0x06625a9f, 0x2e5033ea, 0x53d38b9e, 0xf7583f9e, 0x6ba0ebcf,
6151 0x7f3d72f5, 0xf83fbd68, 0x8ae7f43b, 0x725f7b9f, 0x52bf1d50, 0xf9d4aff7,
6152 0xcd2f3127, 0xe027b4a7, 0xda88baed, 0x3847a1db, 0x2193f303, 0x659376e8,
6153 0x91647fe6, 0x17d9b8de, 0xfee7c1ea, 0x810de8a8, 0xe486727c, 0x66593737,
6154 0xfbca7bd1, 0xb1661be5, 0x26e3262f, 0xaccc38e5, 0x14e7ff22, 0xd9021bd9,
6155 0xa28f5e11, 0xec1a77bc, 0x9ff7ce3c, 0x7e11f760, 0x0bfef608, 0xc19fe7a0,
6156 0x08fc21de, 0xff3e1dec, 0xc21dec04, 0xf803f02e, 0x03f053fc, 0x61dc9708,
6157 0xe57a829c, 0x5f62ae6a, 0x3b3dd704, 0xd3bfe302, 0x97968733, 0x9e2a598b,
6158 0xdd0ea5bf, 0xe9e596ae, 0x6f9c8df4, 0x4f3377bd, 0xdfc92a4d, 0x86178c26,
6159 0xd7b7eefb, 0x5afbedc8, 0x37bc1cf9, 0xb2e7e389, 0x473cfc34, 0xf7c69ec5,
6160 0x3af066d7, 0x2b8ec539, 0x1fc82af9, 0x63acaf8d, 0x29d79c9c, 0x55663cfd,
6161 0x0a48f7d0, 0xfde1639c, 0x5f313e48, 0x0d4c7947, 0x44a74f90, 0x172a19f2,
6162 0x1d385a9f, 0x772e3acc, 0xa09768c9, 0x9e82727f, 0xe361c6e2, 0x51ef90b0,
6163 0x394f90ae, 0x32c64b1e, 0xf3e1988f, 0xf7aca363, 0x7e3f3a3f, 0x943150d8,
6164 0x3ff998fd, 0x3e80ffdd, 0x8affef06, 0x8e876b7d, 0xf7db873f, 0xca2bbd40,
6165 0xc1f610cf, 0xb81f603a, 0xb164dcfc, 0x1d4cb78d, 0x05483bfe, 0xebe0cdae,
6166 0x6a83e456, 0xc5ee3094, 0xee0fa57d, 0x91fd6067, 0xcb5bfb21, 0x94225ee8,
6167 0x13df018f, 0x05fafb29, 0x1ba147ae, 0xa38a3e58, 0xa81994c7, 0xc590fbce,
6168 0x4769efc4, 0x0762b97d, 0xf645feb4, 0xf1507f13, 0x6ec51a7a, 0xc4173c0f,
6169 0x82730b95, 0x513339ec, 0xfd23ad9c, 0x7bbc41f2, 0x4f7830d0, 0xb7f7eca9,
6170 0xcbf63eb2, 0x6fffb5f9, 0x8ff65f3c, 0x73dfa3ee, 0xefcd3ff0, 0x9bc460d1,
6171 0x6eee0eb1, 0xcc253bf9, 0x9e5ad5af, 0xcf21ab37, 0x7d2f7bf6, 0xae01f782,
6172 0xaa3c4467, 0x9733e262, 0xd3fc5097, 0x7e6131a6, 0xc7e9f1be, 0x9dbca24f,
6173 0x7424126d, 0xd826fed9, 0x3ba7e636, 0xf43d1e8d, 0xe7e2682f, 0x45eb6b27,
6174 0xfcff048f, 0x696efe42, 0xfa1a33f6, 0x234d699e, 0xfe3977af, 0x6bca7af4,
6175 0xcf207acf, 0xc40b7186, 0xbcf1da07, 0xfe39e4be, 0xfb2512bb, 0x1efc5adc,
6176 0xa05aa4af, 0x97c9537c, 0xaf75e4cb, 0x6c7909d9, 0x30483dd0, 0x14bccc5e,
6177 0x06d4955f, 0x086b2f3f, 0xb5ef7fce, 0x94d77c0c, 0xf9c8ebc7, 0x3f62acbd,
6178 0xdcab8caf, 0xfac1a7c4, 0xe3c6bfeb, 0x76d8be79, 0x0353e539, 0xf8ca17c7,
6179 0xca2fc019, 0xfacaf6e7, 0x62e8fc95, 0x85e29b12, 0x2e313afd, 0x50efe495,
6180 0xc8aedf81, 0x1f485bae, 0x8c268a8f, 0x8b34b6b3, 0x7967a46e, 0x7d377eab,
6181 0xf4e78537, 0x3df3a446, 0xc26ff7e4, 0x273c267b, 0x83b67c84, 0xce83a6e4,
6182 0x6fad99e5, 0xb697dd0d, 0x4fe84de8, 0x683f479d, 0xfd06efc7, 0x57860587,
6183 0x7cefcaf8, 0xd78679ac, 0xcddfc199, 0x229afdf8, 0x5f006217, 0x436bef91,
6184 0xc33e2af8, 0x8d35f3f3, 0xdedf2823, 0xf568b4f8, 0x39785ca1, 0x17be157f,
6185 0x3ce8db88, 0x7c48f805, 0xdd4cfd9e, 0x07289193, 0x05fdf8fb, 0xfdf101c8,
6186 0x77ce2eec, 0xc443db6d, 0x2cb57f77, 0xf7fc2d07, 0xf8ea4a49, 0x17e81079,
6187 0xf1abc9f9, 0x5f7c6aff, 0x7c83db20, 0x3889c671, 0xe5ef778c, 0xe988adf3,
6188 0x9a07bf2e, 0x20bb993e, 0x7975f515, 0x26c6eee1, 0x07891980, 0xce621999,
6189 0x51db3a53, 0x5cb9e04b, 0x79d79e9b, 0xca045103, 0x4bfae433, 0x53dd4ce9,
6190 0x5e47af68, 0xfe31f143, 0xf79c0445, 0x60cf3f00, 0xb23bd09e, 0xd8cbc0fb,
6191 0x7e8e946f, 0x55bca58f, 0xa2e5d3e7, 0x9bf2e45f, 0x715bedaf, 0xafddc60f,
6192 0x433ee8ea, 0x45dff1b0, 0xe3fd6d28, 0xc84f7887, 0x416df29a, 0xff209bbf,
6193 0xfe2941ae, 0x37b602ae, 0xe8067a68, 0x3fa6ed80, 0x165d7bd1, 0x9e92875e,
6194 0x71848370, 0xcc65c6ec, 0x943e9911, 0xe764679d, 0x8729ef95, 0x3986c38d,
6195 0x2fe2506f, 0x12331ee6, 0x7df94cf5, 0xad0ec505, 0x3c5bbf95, 0x7529df71,
6196 0x96afd22c, 0x714c8eff, 0x389fd82b, 0x7922df3a, 0x38aee73b, 0xbf9782a2,
6197 0x468ab944, 0x0e68fab9, 0xc7db2ff6, 0x3c0683fb, 0xdf871919, 0x4f286b29,
6198 0x7937d01b, 0xa3df867c, 0x05f3bb40, 0x0ea6c581, 0xab6a2f61, 0x421e8f37,
6199 0x2e214a6e, 0xca8745c3, 0xb829b38f, 0x768377df, 0xf8f7c264, 0x9726567d,
6200 0x662cf72f, 0x0d5ffdc1, 0x40d8f92a, 0x947e067e, 0x19e660ea, 0xc972df29,
6201 0xd5ced2e7, 0x51273a26, 0xed538dfc, 0xf299b33d, 0x43972332, 0x63dfa335,
6202 0xb68d54e9, 0xef380d6e, 0x4e979ce8, 0x6fc59fdf, 0xdc70faf4, 0xb58205be,
6203 0x44e69a06, 0x5f2efcf1, 0x0bdb2f65, 0xb8a86fed, 0xf30e7ddf, 0x17fd1137,
6204 0xff419397, 0x93cfcfc6, 0x7f3c8d0b, 0x9adca8f3, 0xa61df489, 0xdd94eb1b,
6205 0x2bd52d76, 0x1d291ced, 0x677c0268, 0xefd90e71, 0x73f1df23, 0x5a65bef4,
6206 0xf33bf3f2, 0xae51cbec, 0x4f1b2e77, 0xd208afed, 0xe33f7863, 0x7da48e2e,
6207 0xcfc85cec, 0x4c2e771b, 0x5967f6a4, 0xdf1a955f, 0xd9fbe6ab, 0x3a04d8f9,
6208 0x39d38dff, 0xbef1b372, 0xd8c7be58, 0xc24b6a99, 0x0527d37a, 0x71bbb2fb,
6209 0x1a0609bc, 0xe24590ef, 0xc6cb12f7, 0xe907b63f, 0x8a9a4634, 0x7e0fdb76,
6210 0x7ff00def, 0x4dd86c7f, 0xf71732f5, 0xc705b99f, 0xe4057d2f, 0x37f7c60f,
6211 0xebbe8318, 0x66efbe57, 0xc5b4df6a, 0xb0bf40c6, 0xbcb5d791, 0xeaf6e464,
6212 0x3373cea0, 0xe4725fbc, 0xebb45cb3, 0xdafb07fe, 0xdaee3193, 0x243af02f,
6213 0xde2e5777, 0x87a89647, 0xce6faf8e, 0x4f4bf1e6, 0x8c52d44b, 0x63fa84e7,
6214 0xe252df54, 0xe7435dbd, 0xd9bf7254, 0x866e3cd9, 0xed1f747e, 0xdfc827de,
6215 0x05a6f8bb, 0x752b5bde, 0xb8fb3dcd, 0x6b34951c, 0x92e47be8, 0x51ff46fa,
6216 0x59d43fc4, 0xf55d7c51, 0x783ee897, 0xe8074bf6, 0x3fef02de, 0x473a08de,
6217 0x3b39dfe6, 0xaae63b65, 0x395ec917, 0x77f9ca9b, 0x19e2f55f, 0xd28fbdc2,
6218 0xf15d34ef, 0x27731d5d, 0x5f4912ab, 0x29e6b193, 0xa5f4bdb4, 0x206e23b6,
6219 0xbda1e961, 0x2ee7e8d1, 0x2345d474, 0x55dc61dd, 0x5e7c11da, 0x2b883dfc,
6220 0x7d05b5c7, 0x6ef2e69f, 0x02ebc4b9, 0x845fc8bb, 0xff80bff6, 0x6f7f3f00,
6221 0xd91dfcb6, 0xf25aecb5, 0x14b1f5ff, 0xa6fac157, 0x13b77e05, 0x0f4bffea,
6222 0x0dde7e5c, 0xbb073ded, 0x96f5c79f, 0xd515f77d, 0xf557b123, 0xdae6b754,
6223 0x73f93eff, 0xcd7fbde5, 0x7fa871e6, 0x583ddedf, 0x2fffea97, 0xf347159d,
6224 0x22997db7, 0xe36839e1, 0xf10f7437, 0xfa7cb69b, 0x8737e6de, 0xd0fc2767,
6225 0xb7281177, 0x75c0cc9e, 0x92bf8879, 0xac503bfc, 0xfc218655, 0x3c74de3a,
6226 0x1179d705, 0xba754df8, 0x72f73f12, 0xbee9cb7a, 0x8007f101, 0x8786cebe,
6227 0xb8ffa12f, 0x4d9cff1a, 0x61bd6f8b, 0x2b43d90a, 0xf58b95aa, 0xe87ffdd1,
6228 0xfb7c037b, 0xc4e3e04f, 0x86bfc11f, 0x70ff342d, 0xff88bbfc, 0x081d3e00,
6229 0xa6e5dfe1, 0xeb1dffbb, 0x6c535968, 0x8128f7d0, 0x08fdf374, 0x7c0915ba,
6230 0xdb66dffc, 0xf4bed19a, 0x0f617c1c, 0xdf2309d6, 0x2eb0966e, 0x330a72ed,
6231 0x7d30f7e2, 0x697f282b, 0xaed099d3, 0x407db495, 0xeb97e3fa, 0x80cfe029,
6232 0x06cfce7e, 0x2fc83afe, 0x55d9b6c9, 0xa2e9f46b, 0xf4efe907, 0xa2942c2c,
6233 0x7a19f9e9, 0x8c72e1ee, 0x2ddfc3f4, 0xdd8e7a73, 0x97c10c26, 0x9e34ecde,
6234 0xd1467927, 0xff6bcbbe, 0x00c0e3c2, 0x91d3097e, 0x6e28674f, 0x0a4f8e1c,
6235 0xeff24c1d, 0xadf00d88, 0x685feb96, 0x87f0177f, 0x7e653fee, 0xf7f0ff21,
6236 0xceb85cd4, 0x20cf8e68, 0x0d80f85c, 0xd5fc0f61, 0xfce3ca3a, 0x83c9f721,
6237 0xd79079fc, 0xa9ea855d, 0xf4e1cfbc, 0xabd3d143, 0xd2a7ffad, 0x52d92fe7,
6238 0x7428bc90, 0x6876f9ea, 0xcf1c6e3b, 0x9f67fef5, 0x3504da3f, 0x7f3a0f8b,
6239 0xf3c78c34, 0x4133a6c7, 0x7eca8fe7, 0xda73e47b, 0xf922fd9e, 0xeff2cdc7,
6240 0x0bda84ac, 0xd0983be5, 0xd7938ef5, 0x7f7f94eb, 0xd1a0e7a1, 0x7a718063,
6241 0x79216f5e, 0xd19c3676, 0x7b6a79e2, 0x9efa21fd, 0xf41fd14e, 0xf5809e13,
6242 0x2c78bcf7, 0xce36ec97, 0x275f0433, 0x33cf978c, 0xc79e875b, 0x682970d5,
6243 0x57b7529e, 0x57ab754b, 0xda82ef99, 0x778e3b76, 0x7eff83a1, 0xd0ef05e1,
6244 0xf1a6a9e7, 0x615cf91a, 0x2fe0873b, 0xbcfe01ed, 0x1b4db053, 0xc30c2a3f,
6245 0x30c30c30, 0x0c30c30c, 0xc30c30c3, 0x30c30c30, 0x0c30c30c, 0xc30c30c3,
6246 0x30c30c30, 0x0c30c30c, 0xc30c30c3, 0x30c30c30, 0x0c30c30c, 0xc30c30c3,
6247 0x30c30c30, 0x0c30c30c, 0xc30c30c3, 0x30c30c30, 0xc1b7ff0c, 0x8dca0bff,
6248 0x8000e737, 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x20000131,
6249 0x22b0030c, 0xb0131302, 0x14e7ff1b, 0x93c9084d, 0x26ebaf39, 0x6db6db63,
6250 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
6251 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xf6db6db6, 0x10192fc7,
6252 0x8000dcb1, 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x20000131,
6253 0x22b0030c, 0xb0131302, 0x14e7ff1b, 0x93c9084d, 0x26ebaf39, 0x6db6db63,
6254 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
6255 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xf6db6db6, 0x10192fc7,
6256 0x8000dcb1, 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x20000131,
6257 0x22b0030c, 0xb0131302, 0x14e7ff1b, 0x93c9084d, 0x26ebaf39, 0x6db6db63,
6258 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
6259 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xf6db6db6, 0x10192fc7,
6260 0x8000dcb1, 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x20000131,
6261 0x22b0030c, 0xb0131302, 0x14e7ff1b, 0x93c9084d, 0x26ebaf39, 0x6db6db63,
6262 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
6263 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xf6db6db6, 0x10192fc7,
6264 0x8000dcb1, 0x00008000, 0x00088b1f, 0x00000000, 0xc5edff00, 0x20000131,
6265 0x22b0030c, 0xb0131302, 0x14e7ff1b, 0x93c9084d, 0x26ebaf39, 0x6db6db63,
6266 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
6267 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xf6db6db6, 0x10192fc7,
6268 0x8000dcb1, 0x00008000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
6269 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
6270 0xffffffff, 0x00100000, 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff,
6271 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
6272 0xffffffff, 0xffffffff, 0x00100000, 0x00000000, 0xfffffff3, 0x314fffff,
6273 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd,
6274 0xfffffff1, 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
6275 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3,
6276 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff,
6277 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd,
6278 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
6279 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3,
6280 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x31efffff,
6281 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd,
6282 0xfffffff5, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
6283 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x310fffff, 0x0c30c30c, 0xc30c30c3,
6284 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff,
6285 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd,
6286 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
6287 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3,
6288 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff,
6289 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd,
6290 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
6291 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x30efffff, 0x0c30c30c, 0xc30c30c3,
6292 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x304fffff,
6293 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd,
6294 0xfffffff3, 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
6295 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3,
6296 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff,
6297 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd,
6298 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3,
6299 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3,
6300 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff,
6301 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd,
6302 0xffffff97, 0x056fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3,
6303 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3,
6304 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x320fffff,
6305 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd,
6306 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
6307 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3,
6308 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff,
6309 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd,
6310 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
6311 0x0008cf3c, 0xcdcdcdcd, 0xffffff8a, 0x042fffff, 0x0c30c30c, 0xc30c30c3,
6312 0xcf3cc000, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x05cfffff,
6313 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd,
6314 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
6315 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
6316 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
6317 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd,
6318 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
6319 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
6320 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
6321 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd,
6322 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
6323 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
6324 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
6325 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd,
6326 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
6327 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
6328 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
6329 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd,
6330 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
6331 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
6332 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
6333 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd,
6334 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
6335 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
6336 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
6337 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd,
6338 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
6339 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
6340 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
6341 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd,
6342 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
6343 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
6344 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
6345 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd,
6346 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
6347 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
6348 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
6349 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd,
6350 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
6351 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
6352 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
6353 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd,
6354 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
6355 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3,
6356 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff,
6357 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd,
6358 0x000a0000, 0x000700a0, 0x00028110, 0x000b8138, 0x000201f0, 0x00010210,
6359 0x000f0220, 0x00010310, 0x00080000, 0x00080080, 0x00028100, 0x000b8128,
6360 0x000201e0, 0x00010200, 0x00070210, 0x00020280, 0x000f0000, 0x000800f0,
6361 0x00028170, 0x000b8198, 0x00020250, 0x00010270, 0x000b8280, 0x00080338,
6362 0x00100000, 0x00080100, 0x00028180, 0x000b81a8, 0x00020260, 0x00018280,
6363 0x000e8298, 0x00080380, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc,
6364 0x00002000, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000,
6365 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000
6366};
6367
6368#endif /*__BNX2X_INIT_VALUES_H__*/
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
new file mode 100644
index 000000000000..86055297ab02
--- /dev/null
+++ b/drivers/net/bnx2x_reg.h
@@ -0,0 +1,4394 @@
1/* bnx2x_reg.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * The registers description starts with the regsister Access type followed
10 * by size in bits. For example [RW 32]. The access types are:
11 * R - Read only
12 * RC - Clear on read
13 * RW - Read/Write
14 * ST - Statistics register (clear on read)
15 * W - Write only
16 * WB - Wide bus register - the size is over 32 bits and it should be
17 * read/write in consecutive 32 bits accesses
18 * WR - Write Clear (write 1 to clear the bit)
19 *
20 */
21
22
23/* [R 19] Interrupt register #0 read */
24#define BRB1_REG_BRB1_INT_STS 0x6011c
25/* [RW 4] Parity mask register #0 read/write */
26#define BRB1_REG_BRB1_PRTY_MASK 0x60138
27/* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
28 address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
29 BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. */
30#define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
31/* [RW 23] LL RAM data. */
32#define BRB1_REG_LL_RAM 0x61000
33/* [R 24] The number of full blocks. */
34#define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
35/* [ST 32] The number of cycles that the write_full signal towards MAC #0
36 was asserted. */
37#define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
38#define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
39#define BRB1_REG_NUM_OF_FULL_CYCLES_2 0x600d0
40#define BRB1_REG_NUM_OF_FULL_CYCLES_3 0x600d4
41#define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
42/* [ST 32] The number of cycles that the pause signal towards MAC #0 was
43 asserted. */
44#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
45#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
46#define BRB1_REG_NUM_OF_PAUSE_CYCLES_2 0x600c0
47#define BRB1_REG_NUM_OF_PAUSE_CYCLES_3 0x600c4
48/* [RW 10] Write client 0: De-assert pause threshold. */
49#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
50#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
51/* [RW 10] Write client 0: Assert pause threshold. */
52#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
53#define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
54/* [RW 1] Reset the design by software. */
55#define BRB1_REG_SOFT_RESET 0x600dc
56/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
57#define CCM_REG_CAM_OCCUP 0xd0188
58/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
59 acknowledge output is deasserted; all other signals are treated as usual;
60 if 1 - normal activity. */
61#define CCM_REG_CCM_CFC_IFEN 0xd003c
62/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
63 disregarded; valid is deasserted; all other signals are treated as usual;
64 if 1 - normal activity. */
65#define CCM_REG_CCM_CQM_IFEN 0xd000c
66/* [RW 1] If set the Q index; received from the QM is inserted to event ID.
67 Otherwise 0 is inserted. */
68#define CCM_REG_CCM_CQM_USE_Q 0xd00c0
69/* [RW 11] Interrupt mask register #0 read/write */
70#define CCM_REG_CCM_INT_MASK 0xd01e4
71/* [R 11] Interrupt register #0 read */
72#define CCM_REG_CCM_INT_STS 0xd01d8
73/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
74 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
75 Is used to determine the number of the AG context REG-pairs written back;
76 when the input message Reg1WbFlg isn't set. */
77#define CCM_REG_CCM_REG0_SZ 0xd00c4
78/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
79 disregarded; valid is deasserted; all other signals are treated as usual;
80 if 1 - normal activity. */
81#define CCM_REG_CCM_STORM0_IFEN 0xd0004
82/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
83 disregarded; valid is deasserted; all other signals are treated as usual;
84 if 1 - normal activity. */
85#define CCM_REG_CCM_STORM1_IFEN 0xd0008
86/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
87 disregarded; valid output is deasserted; all other signals are treated as
88 usual; if 1 - normal activity. */
89#define CCM_REG_CDU_AG_RD_IFEN 0xd0030
90/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
91 are disregarded; all other signals are treated as usual; if 1 - normal
92 activity. */
93#define CCM_REG_CDU_AG_WR_IFEN 0xd002c
94/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
95 disregarded; valid output is deasserted; all other signals are treated as
96 usual; if 1 - normal activity. */
97#define CCM_REG_CDU_SM_RD_IFEN 0xd0038
98/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
99 input is disregarded; all other signals are treated as usual; if 1 -
100 normal activity. */
101#define CCM_REG_CDU_SM_WR_IFEN 0xd0034
102/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
103 the initial credit value; read returns the current value of the credit
104 counter. Must be initialized to 1 at start-up. */
105#define CCM_REG_CFC_INIT_CRD 0xd0204
106/* [RW 2] Auxillary counter flag Q number 1. */
107#define CCM_REG_CNT_AUX1_Q 0xd00c8
108/* [RW 2] Auxillary counter flag Q number 2. */
109#define CCM_REG_CNT_AUX2_Q 0xd00cc
110/* [RW 28] The CM header value for QM request (primary). */
111#define CCM_REG_CQM_CCM_HDR_P 0xd008c
112/* [RW 28] The CM header value for QM request (secondary). */
113#define CCM_REG_CQM_CCM_HDR_S 0xd0090
114/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
115 acknowledge output is deasserted; all other signals are treated as usual;
116 if 1 - normal activity. */
117#define CCM_REG_CQM_CCM_IFEN 0xd0014
118/* [RW 6] QM output initial credit. Max credit available - 32. Write writes
119 the initial credit value; read returns the current value of the credit
120 counter. Must be initialized to 32 at start-up. */
121#define CCM_REG_CQM_INIT_CRD 0xd020c
122/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
123 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
124 prioritised); 2 stands for weight 2; tc. */
125#define CCM_REG_CQM_P_WEIGHT 0xd00b8
126/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
127 acknowledge output is deasserted; all other signals are treated as usual;
128 if 1 - normal activity. */
129#define CCM_REG_CSDM_IFEN 0xd0018
130/* [RC 1] Set when the message length mismatch (relative to last indication)
131 at the SDM interface is detected. */
132#define CCM_REG_CSDM_LENGTH_MIS 0xd0170
133/* [RW 28] The CM header for QM formatting in case of an error in the QM
134 inputs. */
135#define CCM_REG_ERR_CCM_HDR 0xd0094
136/* [RW 8] The Event ID in case the input message ErrorFlg is set. */
137#define CCM_REG_ERR_EVNT_ID 0xd0098
138/* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
139 writes the initial credit value; read returns the current value of the
140 credit counter. Must be initialized to 64 at start-up. */
141#define CCM_REG_FIC0_INIT_CRD 0xd0210
142/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
143 writes the initial credit value; read returns the current value of the
144 credit counter. Must be initialized to 64 at start-up. */
145#define CCM_REG_FIC1_INIT_CRD 0xd0214
146/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
147 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
148 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
149 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
150 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
151#define CCM_REG_GR_ARB_TYPE 0xd015c
152/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
153 highest priority is 3. It is supposed; that the Store channel priority is
154 the compliment to 4 of the rest priorities - Aggregation channel; Load
155 (FIC0) channel and Load (FIC1). */
156#define CCM_REG_GR_LD0_PR 0xd0164
157/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
158 highest priority is 3. It is supposed; that the Store channel priority is
159 the compliment to 4 of the rest priorities - Aggregation channel; Load
160 (FIC0) channel and Load (FIC1). */
161#define CCM_REG_GR_LD1_PR 0xd0168
162/* [RW 2] General flags index. */
163#define CCM_REG_INV_DONE_Q 0xd0108
164/* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
165 context and sent to STORM; for a specific connection type. The double
166 REG-pairs are used in order to align to STORM context row size of 128
167 bits. The offset of these data in the STORM context is always 0. Index
168 _(0..15) stands for the connection type (one of 16). */
169#define CCM_REG_N_SM_CTX_LD_0 0xd004c
170#define CCM_REG_N_SM_CTX_LD_1 0xd0050
171#define CCM_REG_N_SM_CTX_LD_10 0xd0074
172#define CCM_REG_N_SM_CTX_LD_11 0xd0078
173#define CCM_REG_N_SM_CTX_LD_12 0xd007c
174#define CCM_REG_N_SM_CTX_LD_13 0xd0080
175#define CCM_REG_N_SM_CTX_LD_14 0xd0084
176#define CCM_REG_N_SM_CTX_LD_15 0xd0088
177#define CCM_REG_N_SM_CTX_LD_2 0xd0054
178#define CCM_REG_N_SM_CTX_LD_3 0xd0058
179#define CCM_REG_N_SM_CTX_LD_4 0xd005c
180/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
181 acknowledge output is deasserted; all other signals are treated as usual;
182 if 1 - normal activity. */
183#define CCM_REG_PBF_IFEN 0xd0028
184/* [RC 1] Set when the message length mismatch (relative to last indication)
185 at the pbf interface is detected. */
186#define CCM_REG_PBF_LENGTH_MIS 0xd0180
187/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
188 weight 8 (the most prioritised); 1 stands for weight 1(least
189 prioritised); 2 stands for weight 2; tc. */
190#define CCM_REG_PBF_WEIGHT 0xd00ac
191/* [RW 6] The physical queue number of queue number 1 per port index. */
192#define CCM_REG_PHYS_QNUM1_0 0xd0134
193#define CCM_REG_PHYS_QNUM1_1 0xd0138
194/* [RW 6] The physical queue number of queue number 2 per port index. */
195#define CCM_REG_PHYS_QNUM2_0 0xd013c
196#define CCM_REG_PHYS_QNUM2_1 0xd0140
197/* [RW 6] The physical queue number of queue number 3 per port index. */
198#define CCM_REG_PHYS_QNUM3_0 0xd0144
199/* [RW 6] The physical queue number of queue number 0 with QOS equal 0 port
200 index 0. */
201#define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
202#define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
203/* [RW 6] The physical queue number of queue number 0 with QOS equal 1 port
204 index 0. */
205#define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
206#define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
207/* [RW 6] The physical queue number of queue number 0 with QOS equal 2 port
208 index 0. */
209#define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
210/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
211 disregarded; acknowledge output is deasserted; all other signals are
212 treated as usual; if 1 - normal activity. */
213#define CCM_REG_STORM_CCM_IFEN 0xd0010
214/* [RC 1] Set when the message length mismatch (relative to last indication)
215 at the STORM interface is detected. */
216#define CCM_REG_STORM_LENGTH_MIS 0xd016c
217/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
218 disregarded; acknowledge output is deasserted; all other signals are
219 treated as usual; if 1 - normal activity. */
220#define CCM_REG_TSEM_IFEN 0xd001c
221/* [RC 1] Set when the message length mismatch (relative to last indication)
222 at the tsem interface is detected. */
223#define CCM_REG_TSEM_LENGTH_MIS 0xd0174
224/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
225 weight 8 (the most prioritised); 1 stands for weight 1(least
226 prioritised); 2 stands for weight 2; tc. */
227#define CCM_REG_TSEM_WEIGHT 0xd00a0
228/* [RW 1] Input usem Interface enable. If 0 - the valid input is
229 disregarded; acknowledge output is deasserted; all other signals are
230 treated as usual; if 1 - normal activity. */
231#define CCM_REG_USEM_IFEN 0xd0024
232/* [RC 1] Set when message length mismatch (relative to last indication) at
233 the usem interface is detected. */
234#define CCM_REG_USEM_LENGTH_MIS 0xd017c
235/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
236 weight 8 (the most prioritised); 1 stands for weight 1(least
237 prioritised); 2 stands for weight 2; tc. */
238#define CCM_REG_USEM_WEIGHT 0xd00a8
239/* [RW 1] Input xsem Interface enable. If 0 - the valid input is
240 disregarded; acknowledge output is deasserted; all other signals are
241 treated as usual; if 1 - normal activity. */
242#define CCM_REG_XSEM_IFEN 0xd0020
243/* [RC 1] Set when the message length mismatch (relative to last indication)
244 at the xsem interface is detected. */
245#define CCM_REG_XSEM_LENGTH_MIS 0xd0178
246/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
247 weight 8 (the most prioritised); 1 stands for weight 1(least
248 prioritised); 2 stands for weight 2; tc. */
249#define CCM_REG_XSEM_WEIGHT 0xd00a4
250/* [RW 19] Indirect access to the descriptor table of the XX protection
251 mechanism. The fields are: [5:0] - message length; [12:6] - message
252 pointer; 18:13] - next pointer. */
253#define CCM_REG_XX_DESCR_TABLE 0xd0300
254/* [R 7] Used to read the value of XX protection Free counter. */
255#define CCM_REG_XX_FREE 0xd0184
256/* [RW 6] Initial value for the credit counter; responsible for fulfilling
257 of the Input Stage XX protection buffer by the XX protection pending
258 messages. Max credit available - 127. Write writes the initial credit
259 value; read returns the current value of the credit counter. Must be
260 initialized to maximum XX protected message size - 2 at start-up. */
261#define CCM_REG_XX_INIT_CRD 0xd0220
262/* [RW 7] The maximum number of pending messages; which may be stored in XX
263 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
264 At write comprises the start value of the ~ccm_registers_xx_free.xx_free
265 counter. */
266#define CCM_REG_XX_MSG_NUM 0xd0224
267/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
268#define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
269/* [RW 18] Indirect access to the XX table of the XX protection mechanism.
270 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
271 header pointer. */
272#define CCM_REG_XX_TABLE 0xd0280
273#define CDU_REG_CDU_CHK_MASK0 0x101000
274#define CDU_REG_CDU_CHK_MASK1 0x101004
275#define CDU_REG_CDU_CONTROL0 0x101008
276#define CDU_REG_CDU_DEBUG 0x101010
277#define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
278/* [RW 7] Interrupt mask register #0 read/write */
279#define CDU_REG_CDU_INT_MASK 0x10103c
280/* [R 7] Interrupt register #0 read */
281#define CDU_REG_CDU_INT_STS 0x101030
282/* [RW 5] Parity mask register #0 read/write */
283#define CDU_REG_CDU_PRTY_MASK 0x10104c
284/* [RC 32] logging of error data in case of a CDU load error:
285 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
286 ype_error; ctual_active; ctual_compressed_context}; */
287#define CDU_REG_ERROR_DATA 0x101014
288/* [WB 216] L1TT ram access. each entry has the following format :
289 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
290 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
291#define CDU_REG_L1TT 0x101800
292/* [WB 24] MATT ram access. each entry has the following
293 format:{RegionLength[11:0]; egionOffset[11:0]} */
294#define CDU_REG_MATT 0x101100
295/* [R 1] indication the initializing the activity counter by the hardware
296 was done. */
297#define CFC_REG_AC_INIT_DONE 0x104078
298/* [RW 13] activity counter ram access */
299#define CFC_REG_ACTIVITY_COUNTER 0x104400
300#define CFC_REG_ACTIVITY_COUNTER_SIZE 256
301/* [R 1] indication the initializing the cams by the hardware was done. */
302#define CFC_REG_CAM_INIT_DONE 0x10407c
303/* [RW 2] Interrupt mask register #0 read/write */
304#define CFC_REG_CFC_INT_MASK 0x104108
305/* [R 2] Interrupt register #0 read */
306#define CFC_REG_CFC_INT_STS 0x1040fc
307/* [RC 2] Interrupt register #0 read clear */
308#define CFC_REG_CFC_INT_STS_CLR 0x104100
309/* [RW 4] Parity mask register #0 read/write */
310#define CFC_REG_CFC_PRTY_MASK 0x104118
311/* [RW 21] CID cam access (21:1 - Data; alid - 0) */
312#define CFC_REG_CID_CAM 0x104800
313#define CFC_REG_CONTROL0 0x104028
314#define CFC_REG_DEBUG0 0x104050
315/* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
316 vector) whether the cfc should be disabled upon it */
317#define CFC_REG_DISABLE_ON_ERROR 0x104044
318/* [RC 14] CFC error vector. when the CFC detects an internal error it will
319 set one of these bits. the bit description can be found in CFC
320 specifications */
321#define CFC_REG_ERROR_VECTOR 0x10403c
322#define CFC_REG_INIT_REG 0x10404c
323/* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
324 field allows changing the priorities of the weighted-round-robin arbiter
325 which selects which CFC load client should be served next */
326#define CFC_REG_LCREQ_WEIGHTS 0x104084
327/* [R 1] indication the initializing the link list by the hardware was done. */
328#define CFC_REG_LL_INIT_DONE 0x104074
329/* [R 9] Number of allocated LCIDs which are at empty state */
330#define CFC_REG_NUM_LCIDS_ALLOC 0x104020
331/* [R 9] Number of Arriving LCIDs in Link List Block */
332#define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
333/* [R 9] Number of Inside LCIDs in Link List Block */
334#define CFC_REG_NUM_LCIDS_INSIDE 0x104008
335/* [R 9] Number of Leaving LCIDs in Link List Block */
336#define CFC_REG_NUM_LCIDS_LEAVING 0x104018
337/* [RW 8] The event id for aggregated interrupt 0 */
338#define CSDM_REG_AGG_INT_EVENT_0 0xc2038
339/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
340#define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
341/* [RW 16] The maximum value of the competion counter #0 */
342#define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
343/* [RW 16] The maximum value of the competion counter #1 */
344#define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
345/* [RW 16] The maximum value of the competion counter #2 */
346#define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
347/* [RW 16] The maximum value of the competion counter #3 */
348#define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
349/* [RW 13] The start address in the internal RAM for the completion
350 counters. */
351#define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
352/* [RW 32] Interrupt mask register #0 read/write */
353#define CSDM_REG_CSDM_INT_MASK_0 0xc229c
354#define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
355/* [RW 11] Parity mask register #0 read/write */
356#define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
357#define CSDM_REG_ENABLE_IN1 0xc2238
358#define CSDM_REG_ENABLE_IN2 0xc223c
359#define CSDM_REG_ENABLE_OUT1 0xc2240
360#define CSDM_REG_ENABLE_OUT2 0xc2244
361/* [RW 4] The initial number of messages that can be sent to the pxp control
362 interface without receiving any ACK. */
363#define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
364/* [ST 32] The number of ACK after placement messages received */
365#define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
366/* [ST 32] The number of packet end messages received from the parser */
367#define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
368/* [ST 32] The number of requests received from the pxp async if */
369#define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
370/* [ST 32] The number of commands received in queue 0 */
371#define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
372/* [ST 32] The number of commands received in queue 10 */
373#define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
374/* [ST 32] The number of commands received in queue 11 */
375#define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
376/* [ST 32] The number of commands received in queue 1 */
377#define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
378/* [ST 32] The number of commands received in queue 3 */
379#define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
380/* [ST 32] The number of commands received in queue 4 */
381#define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
382/* [ST 32] The number of commands received in queue 5 */
383#define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
384/* [ST 32] The number of commands received in queue 6 */
385#define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
386/* [ST 32] The number of commands received in queue 7 */
387#define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
388/* [ST 32] The number of commands received in queue 8 */
389#define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
390/* [ST 32] The number of commands received in queue 9 */
391#define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
392/* [RW 13] The start address in the internal RAM for queue counters */
393#define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
394/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
395#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
396/* [R 1] parser fifo empty in sdm_sync block */
397#define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
398/* [R 1] parser serial fifo empty in sdm_sync block */
399#define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
400/* [RW 32] Tick for timer counter. Applicable only when
401 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
402#define CSDM_REG_TIMER_TICK 0xc2000
403/* [RW 5] The number of time_slots in the arbitration cycle */
404#define CSEM_REG_ARB_CYCLE_SIZE 0x200034
405/* [RW 3] The source that is associated with arbitration element 0. Source
406 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
407 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
408#define CSEM_REG_ARB_ELEMENT0 0x200020
409/* [RW 3] The source that is associated with arbitration element 1. Source
410 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
411 sleeping thread with priority 1; 4- sleeping thread with priority 2.
412 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
413#define CSEM_REG_ARB_ELEMENT1 0x200024
414/* [RW 3] The source that is associated with arbitration element 2. Source
415 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
416 sleeping thread with priority 1; 4- sleeping thread with priority 2.
417 Could not be equal to register ~csem_registers_arb_element0.arb_element0
418 and ~csem_registers_arb_element1.arb_element1 */
419#define CSEM_REG_ARB_ELEMENT2 0x200028
420/* [RW 3] The source that is associated with arbitration element 3. Source
421 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
422 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
423 not be equal to register ~csem_registers_arb_element0.arb_element0 and
424 ~csem_registers_arb_element1.arb_element1 and
425 ~csem_registers_arb_element2.arb_element2 */
426#define CSEM_REG_ARB_ELEMENT3 0x20002c
427/* [RW 3] The source that is associated with arbitration element 4. Source
428 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
429 sleeping thread with priority 1; 4- sleeping thread with priority 2.
430 Could not be equal to register ~csem_registers_arb_element0.arb_element0
431 and ~csem_registers_arb_element1.arb_element1 and
432 ~csem_registers_arb_element2.arb_element2 and
433 ~csem_registers_arb_element3.arb_element3 */
434#define CSEM_REG_ARB_ELEMENT4 0x200030
435/* [RW 32] Interrupt mask register #0 read/write */
436#define CSEM_REG_CSEM_INT_MASK_0 0x200110
437#define CSEM_REG_CSEM_INT_MASK_1 0x200120
438/* [RW 32] Parity mask register #0 read/write */
439#define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
440#define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
441#define CSEM_REG_ENABLE_IN 0x2000a4
442#define CSEM_REG_ENABLE_OUT 0x2000a8
443/* [RW 32] This address space contains all registers and memories that are
444 placed in SEM_FAST block. The SEM_FAST registers are described in
445 appendix B. In order to access the SEM_FAST registers the base address
446 CSEM_REGISTERS_FAST_MEMORY (Offset: 0x220000) should be added to each
447 SEM_FAST register offset. */
448#define CSEM_REG_FAST_MEMORY 0x220000
449/* [RW 1] Disables input messages from FIC0 May be updated during run_time
450 by the microcode */
451#define CSEM_REG_FIC0_DISABLE 0x200224
452/* [RW 1] Disables input messages from FIC1 May be updated during run_time
453 by the microcode */
454#define CSEM_REG_FIC1_DISABLE 0x200234
455/* [RW 15] Interrupt table Read and write access to it is not possible in
456 the middle of the work */
457#define CSEM_REG_INT_TABLE 0x200400
458/* [ST 24] Statistics register. The number of messages that entered through
459 FIC0 */
460#define CSEM_REG_MSG_NUM_FIC0 0x200000
461/* [ST 24] Statistics register. The number of messages that entered through
462 FIC1 */
463#define CSEM_REG_MSG_NUM_FIC1 0x200004
464/* [ST 24] Statistics register. The number of messages that were sent to
465 FOC0 */
466#define CSEM_REG_MSG_NUM_FOC0 0x200008
467/* [ST 24] Statistics register. The number of messages that were sent to
468 FOC1 */
469#define CSEM_REG_MSG_NUM_FOC1 0x20000c
470/* [ST 24] Statistics register. The number of messages that were sent to
471 FOC2 */
472#define CSEM_REG_MSG_NUM_FOC2 0x200010
473/* [ST 24] Statistics register. The number of messages that were sent to
474 FOC3 */
475#define CSEM_REG_MSG_NUM_FOC3 0x200014
476/* [RW 1] Disables input messages from the passive buffer May be updated
477 during run_time by the microcode */
478#define CSEM_REG_PAS_DISABLE 0x20024c
479/* [WB 128] Debug only. Passive buffer memory */
480#define CSEM_REG_PASSIVE_BUFFER 0x202000
481/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
482#define CSEM_REG_PRAM 0x240000
483/* [R 16] Valid sleeping threads indication have bit per thread */
484#define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
485/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
486#define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
487/* [RW 16] List of free threads . There is a bit per thread. */
488#define CSEM_REG_THREADS_LIST 0x2002e4
489/* [RW 3] The arbitration scheme of time_slot 0 */
490#define CSEM_REG_TS_0_AS 0x200038
491/* [RW 3] The arbitration scheme of time_slot 10 */
492#define CSEM_REG_TS_10_AS 0x200060
493/* [RW 3] The arbitration scheme of time_slot 11 */
494#define CSEM_REG_TS_11_AS 0x200064
495/* [RW 3] The arbitration scheme of time_slot 12 */
496#define CSEM_REG_TS_12_AS 0x200068
497/* [RW 3] The arbitration scheme of time_slot 13 */
498#define CSEM_REG_TS_13_AS 0x20006c
499/* [RW 3] The arbitration scheme of time_slot 14 */
500#define CSEM_REG_TS_14_AS 0x200070
501/* [RW 3] The arbitration scheme of time_slot 15 */
502#define CSEM_REG_TS_15_AS 0x200074
503/* [RW 3] The arbitration scheme of time_slot 16 */
504#define CSEM_REG_TS_16_AS 0x200078
505/* [RW 3] The arbitration scheme of time_slot 17 */
506#define CSEM_REG_TS_17_AS 0x20007c
507/* [RW 3] The arbitration scheme of time_slot 18 */
508#define CSEM_REG_TS_18_AS 0x200080
509/* [RW 3] The arbitration scheme of time_slot 1 */
510#define CSEM_REG_TS_1_AS 0x20003c
511/* [RW 3] The arbitration scheme of time_slot 2 */
512#define CSEM_REG_TS_2_AS 0x200040
513/* [RW 3] The arbitration scheme of time_slot 3 */
514#define CSEM_REG_TS_3_AS 0x200044
515/* [RW 3] The arbitration scheme of time_slot 4 */
516#define CSEM_REG_TS_4_AS 0x200048
517/* [RW 3] The arbitration scheme of time_slot 5 */
518#define CSEM_REG_TS_5_AS 0x20004c
519/* [RW 3] The arbitration scheme of time_slot 6 */
520#define CSEM_REG_TS_6_AS 0x200050
521/* [RW 3] The arbitration scheme of time_slot 7 */
522#define CSEM_REG_TS_7_AS 0x200054
523/* [RW 3] The arbitration scheme of time_slot 8 */
524#define CSEM_REG_TS_8_AS 0x200058
525/* [RW 3] The arbitration scheme of time_slot 9 */
526#define CSEM_REG_TS_9_AS 0x20005c
527/* [RW 1] Parity mask register #0 read/write */
528#define DBG_REG_DBG_PRTY_MASK 0xc0a8
529/* [RW 2] debug only: These bits indicate the credit for PCI request type 4
530 interface; MUST be configured AFTER pci_ext_buffer_strt_addr_lsb/msb are
531 configured */
532#define DBG_REG_PCI_REQ_CREDIT 0xc120
533/* [RW 32] Commands memory. The address to command X; row Y is to calculated
534 as 14*X+Y. */
535#define DMAE_REG_CMD_MEM 0x102400
536/* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
537 initial value is all ones. */
538#define DMAE_REG_CRC16C_INIT 0x10201c
539/* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
540 CRC-16 T10 initial value is all ones. */
541#define DMAE_REG_CRC16T10_INIT 0x102020
542/* [RW 2] Interrupt mask register #0 read/write */
543#define DMAE_REG_DMAE_INT_MASK 0x102054
544/* [RW 4] Parity mask register #0 read/write */
545#define DMAE_REG_DMAE_PRTY_MASK 0x102064
546/* [RW 1] Command 0 go. */
547#define DMAE_REG_GO_C0 0x102080
548/* [RW 1] Command 1 go. */
549#define DMAE_REG_GO_C1 0x102084
550/* [RW 1] Command 10 go. */
551#define DMAE_REG_GO_C10 0x102088
552#define DMAE_REG_GO_C10_SIZE 1
553/* [RW 1] Command 11 go. */
554#define DMAE_REG_GO_C11 0x10208c
555#define DMAE_REG_GO_C11_SIZE 1
556/* [RW 1] Command 12 go. */
557#define DMAE_REG_GO_C12 0x102090
558#define DMAE_REG_GO_C12_SIZE 1
559/* [RW 1] Command 13 go. */
560#define DMAE_REG_GO_C13 0x102094
561#define DMAE_REG_GO_C13_SIZE 1
562/* [RW 1] Command 14 go. */
563#define DMAE_REG_GO_C14 0x102098
564#define DMAE_REG_GO_C14_SIZE 1
565/* [RW 1] Command 15 go. */
566#define DMAE_REG_GO_C15 0x10209c
567#define DMAE_REG_GO_C15_SIZE 1
568/* [RW 1] Command 10 go. */
569#define DMAE_REG_GO_C10 0x102088
570/* [RW 1] Command 11 go. */
571#define DMAE_REG_GO_C11 0x10208c
572/* [RW 1] Command 12 go. */
573#define DMAE_REG_GO_C12 0x102090
574/* [RW 1] Command 13 go. */
575#define DMAE_REG_GO_C13 0x102094
576/* [RW 1] Command 14 go. */
577#define DMAE_REG_GO_C14 0x102098
578/* [RW 1] Command 15 go. */
579#define DMAE_REG_GO_C15 0x10209c
580/* [RW 1] Command 2 go. */
581#define DMAE_REG_GO_C2 0x1020a0
582/* [RW 1] Command 3 go. */
583#define DMAE_REG_GO_C3 0x1020a4
584/* [RW 1] Command 4 go. */
585#define DMAE_REG_GO_C4 0x1020a8
586/* [RW 1] Command 5 go. */
587#define DMAE_REG_GO_C5 0x1020ac
588/* [RW 1] Command 6 go. */
589#define DMAE_REG_GO_C6 0x1020b0
590/* [RW 1] Command 7 go. */
591#define DMAE_REG_GO_C7 0x1020b4
592/* [RW 1] Command 8 go. */
593#define DMAE_REG_GO_C8 0x1020b8
594/* [RW 1] Command 9 go. */
595#define DMAE_REG_GO_C9 0x1020bc
596/* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
597 input is disregarded; valid is deasserted; all other signals are treated
598 as usual; if 1 - normal activity. */
599#define DMAE_REG_GRC_IFEN 0x102008
600/* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
601 acknowledge input is disregarded; valid is deasserted; full is asserted;
602 all other signals are treated as usual; if 1 - normal activity. */
603#define DMAE_REG_PCI_IFEN 0x102004
604/* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
605 initial value to the credit counter; related to the address. Read returns
606 the current value of the counter. */
607#define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
608/* [RW 8] Aggregation command. */
609#define DORQ_REG_AGG_CMD0 0x170060
610/* [RW 8] Aggregation command. */
611#define DORQ_REG_AGG_CMD1 0x170064
612/* [RW 8] Aggregation command. */
613#define DORQ_REG_AGG_CMD2 0x170068
614/* [RW 8] Aggregation command. */
615#define DORQ_REG_AGG_CMD3 0x17006c
616/* [RW 28] UCM Header. */
617#define DORQ_REG_CMHEAD_RX 0x170050
618/* [RW 5] Interrupt mask register #0 read/write */
619#define DORQ_REG_DORQ_INT_MASK 0x170180
620/* [R 5] Interrupt register #0 read */
621#define DORQ_REG_DORQ_INT_STS 0x170174
622/* [RC 5] Interrupt register #0 read clear */
623#define DORQ_REG_DORQ_INT_STS_CLR 0x170178
624/* [RW 2] Parity mask register #0 read/write */
625#define DORQ_REG_DORQ_PRTY_MASK 0x170190
626/* [RW 8] The address to write the DPM CID to STORM. */
627#define DORQ_REG_DPM_CID_ADDR 0x170044
628/* [RW 5] The DPM mode CID extraction offset. */
629#define DORQ_REG_DPM_CID_OFST 0x170030
630/* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
631#define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
632/* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
633#define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
634/* [R 13] Current value of the DQ FIFO fill level according to following
635 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
636 doorbell. */
637#define DORQ_REG_DQ_FILL_LVLF 0x1700a4
638/* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
639 equal to full threshold; reset on full clear. */
640#define DORQ_REG_DQ_FULL_ST 0x1700c0
641/* [RW 28] The value sent to CM header in the case of CFC load error. */
642#define DORQ_REG_ERR_CMHEAD 0x170058
643#define DORQ_REG_IF_EN 0x170004
644#define DORQ_REG_MODE_ACT 0x170008
645/* [RW 5] The normal mode CID extraction offset. */
646#define DORQ_REG_NORM_CID_OFST 0x17002c
647/* [RW 28] TCM Header when only TCP context is loaded. */
648#define DORQ_REG_NORM_CMHEAD_TX 0x17004c
649/* [RW 3] The number of simultaneous outstanding requests to Context Fetch
650 Interface. */
651#define DORQ_REG_OUTST_REQ 0x17003c
652#define DORQ_REG_REGN 0x170038
653/* [R 4] Current value of response A counter credit. Initial credit is
654 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
655 register. */
656#define DORQ_REG_RSPA_CRD_CNT 0x1700ac
657/* [R 4] Current value of response B counter credit. Initial credit is
658 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
659 register. */
660#define DORQ_REG_RSPB_CRD_CNT 0x1700b0
661/* [RW 4] The initial credit at the Doorbell Response Interface. The write
662 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
663 read reads this written value. */
664#define DORQ_REG_RSP_INIT_CRD 0x170048
665/* [RW 4] Initial activity counter value on the load request; when the
666 shortcut is done. */
667#define DORQ_REG_SHRT_ACT_CNT 0x170070
668/* [RW 28] TCM Header when both ULP and TCP context is loaded. */
669#define DORQ_REG_SHRT_CMHEAD 0x170054
670#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
671#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
672#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
673#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
674#define HC_REG_AGG_INT_0 0x108050
675#define HC_REG_AGG_INT_1 0x108054
676/* [RW 16] attention bit and attention acknowledge bits status for port 0
677 and 1 according to the following address map: addr 0 - attn_bit_0; addr 1
678 - attn_ack_bit_0; addr 2 - attn_bit_1; addr 3 - attn_ack_bit_1; */
679#define HC_REG_ATTN_BIT 0x108120
680/* [RW 16] attn bits status index for attn bit msg; addr 0 - function 0;
681 addr 1 - functin 1 */
682#define HC_REG_ATTN_IDX 0x108100
683/* [RW 32] port 0 lower 32 bits address field for attn messag. */
684#define HC_REG_ATTN_MSG0_ADDR_L 0x108018
685/* [RW 32] port 1 lower 32 bits address field for attn messag. */
686#define HC_REG_ATTN_MSG1_ADDR_L 0x108020
687/* [RW 8] status block number for attn bit msg - function 0; */
688#define HC_REG_ATTN_NUM_P0 0x108038
689/* [RW 8] status block number for attn bit msg - function 1 */
690#define HC_REG_ATTN_NUM_P1 0x10803c
691#define HC_REG_CONFIG_0 0x108000
692#define HC_REG_CONFIG_1 0x108004
693/* [RW 3] Parity mask register #0 read/write */
694#define HC_REG_HC_PRTY_MASK 0x1080a0
695/* [RW 17] status block interrupt mask; one in each bit means unmask; zerow
696 in each bit means mask; bit 0 - default SB; bit 1 - SB_0; bit 2 - SB_1...
697 bit 16- SB_15; addr 0 - port 0; addr 1 - port 1 */
698#define HC_REG_INT_MASK 0x108108
699/* [RW 16] port 0 attn bit condition monitoring; each bit that is set will
700 lock a change fron 0 to 1 in the corresponding attention signals that
701 comes from the AEU */
702#define HC_REG_LEADING_EDGE_0 0x108040
703#define HC_REG_LEADING_EDGE_1 0x108048
704/* [RW 16] all producer and consumer of port 0 according to the following
705 addresses; U_prod: 0-15; C_prod: 16-31; U_cons: 32-47; C_cons:48-63;
706 Defoult_prod: U/C/X/T/Attn-64/65/66/67/68; Defoult_cons:
707 U/C/X/T/Attn-69/70/71/72/73 */
708#define HC_REG_P0_PROD_CONS 0x108200
709/* [RW 16] all producer and consumer of port 1according to the following
710 addresses; U_prod: 0-15; C_prod: 16-31; U_cons: 32-47; C_cons:48-63;
711 Defoult_prod: U/C/X/T/Attn-64/65/66/67/68; Defoult_cons:
712 U/C/X/T/Attn-69/70/71/72/73 */
713#define HC_REG_P1_PROD_CONS 0x108400
714/* [W 1] This register is write only and has 4 addresses as follow: 0 =
715 clear all PBA bits port 0; 1 = clear all pending interrupts request
716 port0; 2 = clear all PBA bits port 1; 3 = clear all pending interrupts
717 request port1; here is no meaning for the data in this register */
718#define HC_REG_PBA_COMMAND 0x108140
719#define HC_REG_PCI_CONFIG_0 0x108010
720#define HC_REG_PCI_CONFIG_1 0x108014
721/* [RW 24] all counters acording to the following address: LSB: 0=read; 1=
722 read_clear; 0-71 = HW counters (the inside order is the same as the
723 interrupt table in the spec); 72-219 = SW counters 1 (stops after first
724 consumer upd) the inside order is: 72-103 - U_non_default_p0; 104-135
725 C_non_defaul_p0; 36-145 U/C/X/T/Attn_default_p0; 146-177
726 U_non_default_p1; 178-209 C_non_defaul_p1; 10-219 U/C/X/T/Attn_default_p1
727 ; 220-367 = SW counters 2 (stops when prod=cons) the inside order is:
728 220-251 - U_non_default_p0; 252-283 C_non_defaul_p0; 84-293
729 U/C/X/T/Attn_default_p0; 294-325 U_non_default_p1; 326-357
730 C_non_defaul_p1; 58-367 U/C/X/T/Attn_default_p1 ; 368-515 = mailbox
731 counters; (the inside order of the mailbox counter is 368-431 U and C
732 non_default_p0; 432-441 U/C/X/T/Attn_default_p0; 442-505 U and C
733 non_default_p1; 506-515 U/C/X/T/Attn_default_p1) */
734#define HC_REG_STATISTIC_COUNTERS 0x109000
735/* [RW 16] port 0 attn bit condition monitoring; each bit that is set will
736 lock a change fron 1 to 0 in the corresponding attention signals that
737 comes from the AEU */
738#define HC_REG_TRAILING_EDGE_0 0x108044
739#define HC_REG_TRAILING_EDGE_1 0x10804c
740#define HC_REG_UC_RAM_ADDR_0 0x108028
741#define HC_REG_UC_RAM_ADDR_1 0x108030
742/* [RW 16] ustorm address for coalesc now message */
743#define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
744#define HC_REG_VQID_0 0x108008
745#define HC_REG_VQID_1 0x10800c
746#define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
747#define MCP_REG_MCPR_NVM_ADDR 0x8640c
748#define MCP_REG_MCPR_NVM_CFG4 0x8642c
749#define MCP_REG_MCPR_NVM_COMMAND 0x86400
750#define MCP_REG_MCPR_NVM_READ 0x86410
751#define MCP_REG_MCPR_NVM_SW_ARB 0x86420
752#define MCP_REG_MCPR_NVM_WRITE 0x86408
753#define MCP_REG_MCPR_NVM_WRITE1 0x86428
754#define MCP_REG_MCPR_SCRATCH 0xa0000
755/* [R 32] read first 32 bit after inversion of function 0. mapped as
756 follows: [0] NIG attention for function0; [1] NIG attention for
757 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
758 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
759 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
760 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
761 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
762 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
763 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
764 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
765 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
766 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
767 Parity error; [31] PBF Hw interrupt; */
768#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
769#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
770/* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
771 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
772 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
773 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
774 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
775 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
776 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
777 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
778 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
779 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
780 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
781 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
782 interrupt; */
783#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
784/* [R 32] read second 32 bit after inversion of function 0. mapped as
785 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
786 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
787 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
788 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
789 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
790 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
791 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
792 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
793 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
794 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
795 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
796 interrupt; */
797#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
798#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
799/* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
800 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
801 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
802 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
803 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
804 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
805 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
806 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
807 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
808 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
809 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
810 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
811#define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
812/* [R 32] read third 32 bit after inversion of function 0. mapped as
813 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
814 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
815 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
816 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
817 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
818 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
819 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
820 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
821 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
822 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
823 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
824 attn1; */
825#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
826#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
827/* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
828 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
829 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
830 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
831 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
832 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
833 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
834 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
835 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
836 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
837 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
838 timers attn_4 func1; [30] General attn0; [31] General attn1; */
839#define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
840/* [R 32] read fourth 32 bit after inversion of function 0. mapped as
841 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
842 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
843 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
844 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
845 [14] General attn16; [15] General attn17; [16] General attn18; [17]
846 General attn19; [18] General attn20; [19] General attn21; [20] Main power
847 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
848 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
849 Latched timeout attention; [27] GRC Latched reserved access attention;
850 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
851 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
852#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
853#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
854/* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
855 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
856 [4] General attn6; [5] General attn7; [6] General attn8; [7] General
857 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
858 General attn13; [12] General attn14; [13] General attn15; [14] General
859 attn16; [15] General attn17; [16] General attn18; [17] General attn19;
860 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
861 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
862 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
863 attention; [27] GRC Latched reserved access attention; [28] MCP Latched
864 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
865 ump_tx_parity; [31] MCP Latched scpad_parity; */
866#define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
867/* [W 11] write to this register results with the clear of the latched
868 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
869 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
870 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
871 GRC Latched reserved access attention; one in d7 clears Latched
872 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
873 Latched ump_tx_parity; one in d10 clears Latched scpad_parity; read from
874 this register return zero */
875#define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
876/* [RW 32] first 32b for enabling the output for function 0 output0. mapped
877 as follows: [0] NIG attention for function0; [1] NIG attention for
878 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
879 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
880 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
881 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
882 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
883 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
884 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
885 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
886 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
887 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
888 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
889#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
890#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
891#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
892/* [RW 32] first 32b for enabling the output for function 1 output0. mapped
893 as follows: [0] NIG attention for function0; [1] NIG attention for
894 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
895 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
896 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
897 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
898 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
899 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
900 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
901 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
902 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
903 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
904 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
905#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
906#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
907#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
908/* [RW 32] first 32b for enabling the output for close the gate nig 0.
909 mapped as follows: [0] NIG attention for function0; [1] NIG attention for
910 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
911 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
912 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
913 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
914 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
915 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
916 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
917 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
918 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
919 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
920 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
921#define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
922#define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
923/* [RW 32] first 32b for enabling the output for close the gate pxp 0.
924 mapped as follows: [0] NIG attention for function0; [1] NIG attention for
925 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
926 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
927 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
928 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
929 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
930 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
931 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
932 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
933 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
934 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
935 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
936#define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
937#define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
938/* [RW 32] second 32b for enabling the output for function 0 output0. mapped
939 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
940 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
941 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
942 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
943 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
944 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
945 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
946 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
947 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
948 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
949 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
950 interrupt; */
951#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
952#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
953/* [RW 32] second 32b for enabling the output for function 1 output0. mapped
954 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
955 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
956 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
957 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
958 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
959 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
960 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
961 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
962 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
963 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
964 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
965 interrupt; */
966#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
967#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
968/* [RW 32] second 32b for enabling the output for close the gate nig 0.
969 mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt;
970 [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5]
971 Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8]
972 XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11]
973 XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw
974 interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI
975 core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity
976 error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw
977 interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI
978 Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw
979 interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM
980 Parity error; [31] CCM Hw interrupt; */
981#define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
982#define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
983/* [RW 32] second 32b for enabling the output for close the gate pxp 0.
984 mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt;
985 [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5]
986 Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8]
987 XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11]
988 XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw
989 interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI
990 core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity
991 error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw
992 interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI
993 Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw
994 interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM
995 Parity error; [31] CCM Hw interrupt; */
996#define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
997#define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
998/* [RW 32] third 32b for enabling the output for function 0 output0. mapped
999 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1000 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1001 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1002 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1003 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1004 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1005 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1006 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1007 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1008 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1009 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1010 attn1; */
1011#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1012#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1013/* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1014 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1015 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1016 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1017 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1018 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1019 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1020 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1021 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1022 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1023 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1024 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1025 attn1; */
1026#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1027#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
1028/* [RW 32] third 32b for enabling the output for close the gate nig 0.
1029 mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2]
1030 PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity
1031 error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC
1032 Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE
1033 Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13]
1034 IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt;
1035 [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0;
1036 [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0;
1037 [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST;
1038 [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers
1039 attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31]
1040 General attn1; */
1041#define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1042#define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
1043/* [RW 32] third 32b for enabling the output for close the gate pxp 0.
1044 mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2]
1045 PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity
1046 error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC
1047 Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE
1048 Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13]
1049 IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt;
1050 [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0;
1051 [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0;
1052 [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST;
1053 [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers
1054 attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31]
1055 General attn1; */
1056#define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1057#define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1058/* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1059 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1060 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1061 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1062 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1063 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1064 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1065 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1066 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1067 Latched timeout attention; [27] GRC Latched reserved access attention;
1068 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1069 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1070#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1071#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
1072/* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1073 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1074 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1075 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1076 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1077 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1078 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1079 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1080 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1081 Latched timeout attention; [27] GRC Latched reserved access attention;
1082 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1083 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1084#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1085#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
1086/* [RW 32] fourth 32b for enabling the output for close the gate nig
1087 0.mapped as follows: [0] General attn2; [1] General attn3; [2] General
1088 attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6]
1089 General attn8; [7] General attn9; [8] General attn10; [9] General attn11;
1090 [10] General attn12; [11] General attn13; [12] General attn14; [13]
1091 General attn15; [14] General attn16; [15] General attn17; [16] General
1092 attn18; [17] General attn19; [18] General attn20; [19] General attn21;
1093 [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched
1094 attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched
1095 attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved
1096 access attention; [28] MCP Latched rom_parity; [29] MCP Latched
1097 ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched
1098 scpad_parity; */
1099#define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1100#define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
1101/* [RW 32] fourth 32b for enabling the output for close the gate pxp
1102 0.mapped as follows: [0] General attn2; [1] General attn3; [2] General
1103 attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6]
1104 General attn8; [7] General attn9; [8] General attn10; [9] General attn11;
1105 [10] General attn12; [11] General attn13; [12] General attn14; [13]
1106 General attn15; [14] General attn16; [15] General attn17; [16] General
1107 attn18; [17] General attn19; [18] General attn20; [19] General attn21;
1108 [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched
1109 attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched
1110 attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved
1111 access attention; [28] MCP Latched rom_parity; [29] MCP Latched
1112 ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched
1113 scpad_parity; */
1114#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1115#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1116/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1117 128 bit vector */
1118#define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1119#define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1120#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1121#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1122#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1123#define MISC_REG_AEU_GENERAL_ATTN_13 0xa034
1124#define MISC_REG_AEU_GENERAL_ATTN_14 0xa038
1125#define MISC_REG_AEU_GENERAL_ATTN_15 0xa03c
1126#define MISC_REG_AEU_GENERAL_ATTN_16 0xa040
1127#define MISC_REG_AEU_GENERAL_ATTN_17 0xa044
1128#define MISC_REG_AEU_GENERAL_ATTN_18 0xa048
1129#define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c
1130#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1131#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1132#define MISC_REG_AEU_GENERAL_ATTN_20 0xa050
1133#define MISC_REG_AEU_GENERAL_ATTN_21 0xa054
1134#define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1135#define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1136#define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1137#define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
1138/* [RW 32] first 32b for inverting the input for function 0; for each bit:
1139 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1140 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1141 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1142 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1143 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1144 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1145 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1146 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1147 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1148 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1149 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1150 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1151#define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1152#define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1153/* [RW 32] second 32b for inverting the input for function 0; for each bit:
1154 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1155 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1156 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1157 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1158 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1159 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1160 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1161 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1162 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1163 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1164 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1165 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1166#define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1167#define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1168/* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1169 [9:8] = mask close the gates signals of function 0 toward PXP [8] and NIG
1170 [9]. Zero = mask; one = unmask */
1171#define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1172#define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
1173/* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1174 Port. */
1175#define MISC_REG_BOND_ID 0xa400
1176/* [R 8] These bits indicate the metal revision of the chip. This value
1177 starts at 0x00 for each all-layer tape-out and increments by one for each
1178 tape-out. */
1179#define MISC_REG_CHIP_METAL 0xa404
1180/* [R 16] These bits indicate the part number for the chip. */
1181#define MISC_REG_CHIP_NUM 0xa408
1182/* [R 4] These bits indicate the base revision of the chip. This value
1183 starts at 0x0 for the A0 tape-out and increments by one for each
1184 all-layer tape-out. */
1185#define MISC_REG_CHIP_REV 0xa40c
1186/* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1187 access that does not finish within
1188 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1189 cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1190 assert it attention output. */
1191#define MISC_REG_GRC_TIMEOUT_EN 0xa280
1192/* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1193 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1194 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1195 (reset value 001) Charge pump current control; 111 for 720u; 011 for
1196 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1197 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1198 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1199 Pll_observe (reset value 010) Bits to control observability. bit 10 is
1200 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1201 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1202 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1203 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1204 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1205 connected to RESET input directly. [15] capRetry_en (reset value 0)
1206 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1207 value 0) bit to continuously monitor vco freq (inverted). [17]
1208 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1209 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1210 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1211 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1212 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1213 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1214 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1215 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1216 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1217 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1218 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1219 register bits. */
1220#define MISC_REG_LCPLL_CTRL_1 0xa2a4
1221#define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1222/* [RW 4] Interrupt mask register #0 read/write */
1223#define MISC_REG_MISC_INT_MASK 0xa388
1224/* [RW 1] Parity mask register #0 read/write */
1225#define MISC_REG_MISC_PRTY_MASK 0xa398
1226/* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1227 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1228 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1229 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1230 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1231 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1232 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1233 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1234 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1235 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1236 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1237 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1238 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1239 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1240 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1241 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1242 testa_en (reset value 0); */
1243#define MISC_REG_PLL_STORM_CTRL_1 0xa294
1244#define MISC_REG_PLL_STORM_CTRL_2 0xa298
1245#define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1246#define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
1247/* [RW 32] reset reg#1; rite/read one = the specific block is out of reset;
1248 write/read zero = the specific block is in reset; addr 0-wr- the write
1249 value will be written to the register; addr 1-set - one will be written
1250 to all the bits that have the value of one in the data written (bits that
1251 have the value of zero will not be change) ; addr 2-clear - zero will be
1252 written to all the bits that have the value of one in the data written
1253 (bits that have the value of zero will not be change); addr 3-ignore;
1254 read ignore from all addr except addr 00; inside order of the bits is:
1255 [0] rst_brb1; [1] rst_prs; [2] rst_src; [3] rst_tsdm; [4] rst_tsem; [5]
1256 rst_tcm; [6] rst_rbcr; [7] rst_nig; [8] rst_usdm; [9] rst_ucm; [10]
1257 rst_usem; [11] rst_upb; [12] rst_ccm; [13] rst_csem; [14] rst_csdm; [15]
1258 rst_rbcu; [16] rst_pbf; [17] rst_qm; [18] rst_tm; [19] rst_dorq; [20]
1259 rst_xcm; [21] rst_xsdm; [22] rst_xsem; [23] rst_rbct; [24] rst_cdu; [25]
1260 rst_cfc; [26] rst_pxp; [27] rst_pxpv; [28] rst_rbcp; [29] rst_hc; [30]
1261 rst_dmae; [31] rst_semi_rtc; */
1262#define MISC_REG_RESET_REG_1 0xa580
1263#define MISC_REG_RESET_REG_2 0xa590
1264/* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1265 shared with the driver resides */
1266#define MISC_REG_SHARED_MEM_ADDR 0xa2b4
1267#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1268#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1269#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1270#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1271/* [RW 1] Input enable for RX_BMAC0 IF */
1272#define NIG_REG_BMAC0_IN_EN 0x100ac
1273/* [RW 1] output enable for TX_BMAC0 IF */
1274#define NIG_REG_BMAC0_OUT_EN 0x100e0
1275/* [RW 1] output enable for TX BMAC pause port 0 IF */
1276#define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1277/* [RW 1] output enable for RX_BMAC0_REGS IF */
1278#define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1279/* [RW 1] output enable for RX BRB1 port0 IF */
1280#define NIG_REG_BRB0_OUT_EN 0x100f8
1281/* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1282#define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1283/* [RW 1] output enable for RX BRB1 port1 IF */
1284#define NIG_REG_BRB1_OUT_EN 0x100fc
1285/* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1286#define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1287/* [RW 1] output enable for RX BRB1 LP IF */
1288#define NIG_REG_BRB_LB_OUT_EN 0x10100
1289/* [WB_W 72] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1290 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush */
1291#define NIG_REG_DEBUG_PACKET_LB 0x10800
1292/* [RW 1] Input enable for TX Debug packet */
1293#define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1294/* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1295 packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1296 First packet may be deleted from the middle. And last packet will be
1297 always deleted till the end. */
1298#define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1299/* [RW 1] Output enable to EMAC0 */
1300#define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1301/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1302 to emac for port0; other way to bmac for port0 */
1303#define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1304/* [RW 1] Input enable for TX PBF user packet port0 IF */
1305#define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1306/* [RW 1] Input enable for TX PBF user packet port1 IF */
1307#define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
1308/* [RW 1] Input enable for RX_EMAC0 IF */
1309#define NIG_REG_EMAC0_IN_EN 0x100a4
1310/* [RW 1] output enable for TX EMAC pause port 0 IF */
1311#define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1312/* [R 1] status from emac0. This bit is set when MDINT from either the
1313 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1314 be cleared in the attached PHY device that is driving the MINT pin. */
1315#define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1316/* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1317 are described in appendix A. In order to access the BMAC0 registers; the
1318 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1319 added to each BMAC register offset */
1320#define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1321/* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1322 are described in appendix A. In order to access the BMAC0 registers; the
1323 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1324 added to each BMAC register offset */
1325#define NIG_REG_INGRESS_BMAC1_MEM 0x11000
1326/* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1327#define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
1328/* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
1329 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
1330#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
1331/* [RW 1] led 10g for port 0 */
1332#define NIG_REG_LED_10G_P0 0x10320
1333/* [RW 1] Port0: This bit is set to enable the use of the
1334 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1335 defined below. If this bit is cleared; then the blink rate will be about
1336 8Hz. */
1337#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
1338/* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
1339 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
1340 is reset to 0x080; giving a default blink period of approximately 8Hz. */
1341#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
1342/* [RW 1] Port0: If set along with the
1343 nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
1344 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1345 bit; the Traffic LED will blink with the blink rate specified in
1346 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1347 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1348 fields. */
1349#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
1350/* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
1351 Traffic LED will then be controlled via bit ~nig_registers_
1352 led_control_traffic_p0.led_control_traffic_p0 and bit
1353 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
1354#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
1355/* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
1356 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
1357 set; the LED will blink with blink rate specified in
1358 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1359 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1360 fields. */
1361#define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
1362/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1363 9-11PHY7; 12 MAC4; 13-15 PHY10; */
1364#define NIG_REG_LED_MODE_P0 0x102f0
1365#define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
1366/* [RW 1] send to BRB1 if no match on any of RMP rules. */
1367#define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
1368/* [RW 32] cm header for llh0 */
1369#define NIG_REG_LLH0_CM_HEADER 0x1007c
1370#define NIG_REG_LLH0_ERROR_MASK 0x1008c
1371/* [RW 8] event id for llh0 */
1372#define NIG_REG_LLH0_EVENT_ID 0x10084
1373/* [RW 8] init credit counter for port0 in LLH */
1374#define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1375#define NIG_REG_LLH0_XCM_MASK 0x10130
1376/* [RW 1] send to BRB1 if no match on any of RMP rules. */
1377#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
1378/* [RW 32] cm header for llh1 */
1379#define NIG_REG_LLH1_CM_HEADER 0x10080
1380#define NIG_REG_LLH1_ERROR_MASK 0x10090
1381/* [RW 8] event id for llh1 */
1382#define NIG_REG_LLH1_EVENT_ID 0x10088
1383/* [RW 8] init credit counter for port1 in LLH */
1384#define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1385#define NIG_REG_LLH1_XCM_MASK 0x10134
1386#define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
1387#define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
1388/* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
1389#define NIG_REG_NIG_EMAC0_EN 0x1003c
1390/* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
1391 EMAC0 to strip the CRC from the ingress packets. */
1392#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
1393/* [RW 1] Input enable for RX PBF LP IF */
1394#define NIG_REG_PBF_LB_IN_EN 0x100b4
1395/* [RW 1] output enable for RX parser descriptor IF */
1396#define NIG_REG_PRS_EOP_OUT_EN 0x10104
1397/* [RW 1] Input enable for RX parser request IF */
1398#define NIG_REG_PRS_REQ_IN_EN 0x100b8
1399/* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
1400#define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
1401/* [R 1] status from serdes0 that inputs to interrupt logic of link status */
1402#define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
1403/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1404 for port0 */
1405#define NIG_REG_STAT0_BRB_DISCARD 0x105f0
1406/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1407 for port1 */
1408#define NIG_REG_STAT1_BRB_DISCARD 0x10628
1409/* [WB_R 64] Rx statistics : User octets received for LP */
1410#define NIG_REG_STAT2_BRB_OCTET 0x107e0
1411#define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
1412#define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
1413/* [RW 1] output enable for RX_XCM0 IF */
1414#define NIG_REG_XCM0_OUT_EN 0x100f0
1415/* [RW 1] output enable for RX_XCM1 IF */
1416#define NIG_REG_XCM1_OUT_EN 0x100f4
1417/* [RW 5] control to xgxs - CL45 DEVAD */
1418#define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
1419/* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
1420#define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
1421/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
1422#define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
1423/* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
1424#define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
1425/* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
1426#define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
1427/* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
1428#define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
1429#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
1430#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
1431#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
1432#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
1433/* [RW 1] Disable processing further tasks from port 0 (after ending the
1434 current task in process). */
1435#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
1436/* [RW 1] Disable processing further tasks from port 1 (after ending the
1437 current task in process). */
1438#define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
1439/* [RW 1] Disable processing further tasks from port 4 (after ending the
1440 current task in process). */
1441#define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
1442#define PBF_REG_IF_ENABLE_REG 0x140044
1443/* [RW 1] Init bit. When set the initial credits are copied to the credit
1444 registers (except the port credits). Should be set and then reset after
1445 the configuration of the block has ended. */
1446#define PBF_REG_INIT 0x140000
1447/* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
1448 copied to the credit register. Should be set and then reset after the
1449 configuration of the port has ended. */
1450#define PBF_REG_INIT_P0 0x140004
1451/* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
1452 copied to the credit register. Should be set and then reset after the
1453 configuration of the port has ended. */
1454#define PBF_REG_INIT_P1 0x140008
1455/* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
1456 copied to the credit register. Should be set and then reset after the
1457 configuration of the port has ended. */
1458#define PBF_REG_INIT_P4 0x14000c
1459/* [RW 1] Enable for mac interface 0. */
1460#define PBF_REG_MAC_IF0_ENABLE 0x140030
1461/* [RW 1] Enable for mac interface 1. */
1462#define PBF_REG_MAC_IF1_ENABLE 0x140034
1463/* [RW 1] Enable for the loopback interface. */
1464#define PBF_REG_MAC_LB_ENABLE 0x140040
1465/* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
1466 not suppoterd. */
1467#define PBF_REG_P0_ARB_THRSH 0x1400e4
1468/* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
1469#define PBF_REG_P0_CREDIT 0x140200
1470/* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
1471 lines. */
1472#define PBF_REG_P0_INIT_CRD 0x1400d0
1473/* [RW 1] Indication that pause is enabled for port 0. */
1474#define PBF_REG_P0_PAUSE_ENABLE 0x140014
1475/* [R 8] Number of tasks in port 0 task queue. */
1476#define PBF_REG_P0_TASK_CNT 0x140204
1477/* [R 11] Current credit for port 1 in the tx port buffers in 16 byte lines. */
1478#define PBF_REG_P1_CREDIT 0x140208
1479/* [RW 11] Initial credit for port 1 in the tx port buffers in 16 byte
1480 lines. */
1481#define PBF_REG_P1_INIT_CRD 0x1400d4
1482/* [R 8] Number of tasks in port 1 task queue. */
1483#define PBF_REG_P1_TASK_CNT 0x14020c
1484/* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
1485#define PBF_REG_P4_CREDIT 0x140210
1486/* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
1487 lines. */
1488#define PBF_REG_P4_INIT_CRD 0x1400e0
1489/* [R 8] Number of tasks in port 4 task queue. */
1490#define PBF_REG_P4_TASK_CNT 0x140214
1491/* [RW 5] Interrupt mask register #0 read/write */
1492#define PBF_REG_PBF_INT_MASK 0x1401d4
1493/* [R 5] Interrupt register #0 read */
1494#define PBF_REG_PBF_INT_STS 0x1401c8
1495#define PB_REG_CONTROL 0
1496/* [RW 2] Interrupt mask register #0 read/write */
1497#define PB_REG_PB_INT_MASK 0x28
1498/* [R 2] Interrupt register #0 read */
1499#define PB_REG_PB_INT_STS 0x1c
1500/* [RW 4] Parity mask register #0 read/write */
1501#define PB_REG_PB_PRTY_MASK 0x38
1502#define PRS_REG_A_PRSU_20 0x40134
1503/* [R 8] debug only: CFC load request current credit. Transaction based. */
1504#define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
1505/* [R 8] debug only: CFC search request current credit. Transaction based. */
1506#define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
1507/* [RW 6] The initial credit for the search message to the CFC interface.
1508 Credit is transaction based. */
1509#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
1510/* [RW 24] CID for port 0 if no match */
1511#define PRS_REG_CID_PORT_0 0x400fc
1512#define PRS_REG_CID_PORT_1 0x40100
1513/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1514 load response is reset and packet type is 0. Used in packet start message
1515 to TCM. */
1516#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
1517#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
1518#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
1519#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
1520#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
1521/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1522 load response is set and packet type is 0. Used in packet start message
1523 to TCM. */
1524#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
1525#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
1526#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
1527#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
1528#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
1529/* [RW 32] The CM header for a match and packet type 1 for loopback port.
1530 Used in packet start message to TCM. */
1531#define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
1532#define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
1533#define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
1534#define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
1535/* [RW 32] The CM header for a match and packet type 0. Used in packet start
1536 message to TCM. */
1537#define PRS_REG_CM_HDR_TYPE_0 0x40078
1538#define PRS_REG_CM_HDR_TYPE_1 0x4007c
1539#define PRS_REG_CM_HDR_TYPE_2 0x40080
1540#define PRS_REG_CM_HDR_TYPE_3 0x40084
1541#define PRS_REG_CM_HDR_TYPE_4 0x40088
1542/* [RW 32] The CM header in case there was not a match on the connection */
1543#define PRS_REG_CM_NO_MATCH_HDR 0x400b8
1544/* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
1545 start message to TCM. */
1546#define PRS_REG_EVENT_ID_1 0x40054
1547#define PRS_REG_EVENT_ID_2 0x40058
1548#define PRS_REG_EVENT_ID_3 0x4005c
1549/* [RW 8] Context region for flush packet with packet type 0. Used in CFC
1550 load request message. */
1551#define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
1552#define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
1553#define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
1554#define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
1555#define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
1556#define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
1557#define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
1558#define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
1559/* [RW 4] The increment value to send in the CFC load request message */
1560#define PRS_REG_INC_VALUE 0x40048
1561/* [RW 1] If set indicates not to send messages to CFC on received packets */
1562#define PRS_REG_NIC_MODE 0x40138
1563/* [RW 8] The 8-bit event ID for cases where there is no match on the
1564 connection. Used in packet start message to TCM. */
1565#define PRS_REG_NO_MATCH_EVENT_ID 0x40070
1566/* [ST 24] The number of input CFC flush packets */
1567#define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
1568/* [ST 32] The number of cycles the Parser halted its operation since it
1569 could not allocate the next serial number */
1570#define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
1571/* [ST 24] The number of input packets */
1572#define PRS_REG_NUM_OF_PACKETS 0x40124
1573/* [ST 24] The number of input transparent flush packets */
1574#define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
1575/* [RW 8] Context region for received Ethernet packet with a match and
1576 packet type 0. Used in CFC load request message */
1577#define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
1578#define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
1579#define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
1580#define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
1581#define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
1582#define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
1583#define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
1584#define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
1585/* [R 2] debug only: Number of pending requests for CAC on port 0. */
1586#define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
1587/* [R 2] debug only: Number of pending requests for header parsing. */
1588#define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
1589/* [R 1] Interrupt register #0 read */
1590#define PRS_REG_PRS_INT_STS 0x40188
1591/* [RW 8] Parity mask register #0 read/write */
1592#define PRS_REG_PRS_PRTY_MASK 0x401a4
1593/* [RW 8] Context region for pure acknowledge packets. Used in CFC load
1594 request message */
1595#define PRS_REG_PURE_REGIONS 0x40024
1596/* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
1597 serail number was released by SDM but cannot be used because a previous
1598 serial number was not released. */
1599#define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
1600/* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
1601 serail number was released by SDM but cannot be used because a previous
1602 serial number was not released. */
1603#define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
1604/* [R 4] debug only: SRC current credit. Transaction based. */
1605#define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
1606/* [R 8] debug only: TCM current credit. Cycle based. */
1607#define PRS_REG_TCM_CURRENT_CREDIT 0x40160
1608/* [R 8] debug only: TSDM current credit. Transaction based. */
1609#define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
1610/* [R 6] Debug only: Number of used entries in the data FIFO */
1611#define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
1612/* [R 7] Debug only: Number of used entries in the header FIFO */
1613#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
1614#define PXP2_REG_PGL_CONTROL0 0x120490
1615#define PXP2_REG_PGL_CONTROL1 0x120514
1616/* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
1617 its[15:0]-address */
1618#define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
1619#define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
1620#define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
1621#define PXP2_REG_PGL_INT_CSDM_3 0x120500
1622#define PXP2_REG_PGL_INT_CSDM_4 0x120504
1623#define PXP2_REG_PGL_INT_CSDM_5 0x120508
1624#define PXP2_REG_PGL_INT_CSDM_6 0x12050c
1625#define PXP2_REG_PGL_INT_CSDM_7 0x120510
1626/* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
1627 its[15:0]-address */
1628#define PXP2_REG_PGL_INT_TSDM_0 0x120494
1629#define PXP2_REG_PGL_INT_TSDM_1 0x120498
1630#define PXP2_REG_PGL_INT_TSDM_2 0x12049c
1631#define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
1632#define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
1633#define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
1634#define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
1635#define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
1636/* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
1637 its[15:0]-address */
1638#define PXP2_REG_PGL_INT_USDM_0 0x1204b4
1639#define PXP2_REG_PGL_INT_USDM_1 0x1204b8
1640#define PXP2_REG_PGL_INT_USDM_2 0x1204bc
1641#define PXP2_REG_PGL_INT_USDM_3 0x1204c0
1642#define PXP2_REG_PGL_INT_USDM_4 0x1204c4
1643#define PXP2_REG_PGL_INT_USDM_5 0x1204c8
1644#define PXP2_REG_PGL_INT_USDM_6 0x1204cc
1645#define PXP2_REG_PGL_INT_USDM_7 0x1204d0
1646/* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
1647 its[15:0]-address */
1648#define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
1649#define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
1650#define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
1651#define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
1652#define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
1653#define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
1654#define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
1655#define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
1656/* [R 1] this bit indicates that a read request was blocked because of
1657 bus_master_en was deasserted */
1658#define PXP2_REG_PGL_READ_BLOCKED 0x120568
1659/* [R 6] debug only */
1660#define PXP2_REG_PGL_TXR_CDTS 0x120528
1661/* [R 18] debug only */
1662#define PXP2_REG_PGL_TXW_CDTS 0x12052c
1663/* [R 1] this bit indicates that a write request was blocked because of
1664 bus_master_en was deasserted */
1665#define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
1666#define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
1667#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
1668#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
1669#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
1670#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
1671#define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
1672#define PXP2_REG_PSWRQ_BW_ADD28 0x120228
1673#define PXP2_REG_PSWRQ_BW_ADD28 0x120228
1674#define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
1675#define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
1676#define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
1677#define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
1678#define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
1679#define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
1680#define PXP2_REG_PSWRQ_BW_L1 0x1202b0
1681#define PXP2_REG_PSWRQ_BW_L10 0x1202d4
1682#define PXP2_REG_PSWRQ_BW_L11 0x1202d8
1683#define PXP2_REG_PSWRQ_BW_L10 0x1202d4
1684#define PXP2_REG_PSWRQ_BW_L11 0x1202d8
1685#define PXP2_REG_PSWRQ_BW_L2 0x1202b4
1686#define PXP2_REG_PSWRQ_BW_L28 0x120318
1687#define PXP2_REG_PSWRQ_BW_L28 0x120318
1688#define PXP2_REG_PSWRQ_BW_L3 0x1202b8
1689#define PXP2_REG_PSWRQ_BW_L6 0x1202c4
1690#define PXP2_REG_PSWRQ_BW_L7 0x1202c8
1691#define PXP2_REG_PSWRQ_BW_L8 0x1202cc
1692#define PXP2_REG_PSWRQ_BW_L9 0x1202d0
1693#define PXP2_REG_PSWRQ_BW_RD 0x120324
1694#define PXP2_REG_PSWRQ_BW_UB1 0x120238
1695#define PXP2_REG_PSWRQ_BW_UB10 0x12025c
1696#define PXP2_REG_PSWRQ_BW_UB11 0x120260
1697#define PXP2_REG_PSWRQ_BW_UB10 0x12025c
1698#define PXP2_REG_PSWRQ_BW_UB11 0x120260
1699#define PXP2_REG_PSWRQ_BW_UB2 0x12023c
1700#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
1701#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
1702#define PXP2_REG_PSWRQ_BW_UB3 0x120240
1703#define PXP2_REG_PSWRQ_BW_UB6 0x12024c
1704#define PXP2_REG_PSWRQ_BW_UB7 0x120250
1705#define PXP2_REG_PSWRQ_BW_UB8 0x120254
1706#define PXP2_REG_PSWRQ_BW_UB9 0x120258
1707#define PXP2_REG_PSWRQ_BW_WR 0x120328
1708#define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
1709#define PXP2_REG_PSWRQ_QM0_L2P 0x120038
1710#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
1711#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
1712/* [RW 25] Interrupt mask register #0 read/write */
1713#define PXP2_REG_PXP2_INT_MASK 0x120578
1714/* [R 25] Interrupt register #0 read */
1715#define PXP2_REG_PXP2_INT_STS 0x12056c
1716/* [RC 25] Interrupt register #0 read clear */
1717#define PXP2_REG_PXP2_INT_STS_CLR 0x120570
1718/* [RW 32] Parity mask register #0 read/write */
1719#define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
1720#define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
1721/* [R 1] Debug only: The 'almost full' indication from each fifo (gives
1722 indication about backpressure) */
1723#define PXP2_REG_RD_ALMOST_FULL_0 0x120424
1724/* [R 8] Debug only: The blocks counter - number of unused block ids */
1725#define PXP2_REG_RD_BLK_CNT 0x120418
1726/* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
1727 Must be bigger than 6. Normally should not be changed. */
1728#define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
1729/* [RW 2] CDU byte swapping mode configuration for master read requests */
1730#define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
1731/* [RW 1] When '1'; inputs to the PSWRD block are ignored */
1732#define PXP2_REG_RD_DISABLE_INPUTS 0x120374
1733/* [R 1] PSWRD internal memories initialization is done */
1734#define PXP2_REG_RD_INIT_DONE 0x120370
1735/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1736 allocated for vq10 */
1737#define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
1738/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1739 allocated for vq11 */
1740#define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
1741/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1742 allocated for vq17 */
1743#define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
1744/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1745 allocated for vq18 */
1746#define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
1747/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1748 allocated for vq19 */
1749#define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
1750/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1751 allocated for vq22 */
1752#define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
1753/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1754 allocated for vq6 */
1755#define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
1756/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1757 allocated for vq9 */
1758#define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
1759/* [RW 2] PBF byte swapping mode configuration for master read requests */
1760#define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
1761/* [R 1] Debug only: Indication if delivery ports are idle */
1762#define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
1763#define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
1764/* [RW 2] QM byte swapping mode configuration for master read requests */
1765#define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
1766/* [R 7] Debug only: The SR counter - number of unused sub request ids */
1767#define PXP2_REG_RD_SR_CNT 0x120414
1768/* [RW 2] SRC byte swapping mode configuration for master read requests */
1769#define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
1770/* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
1771 be bigger than 1. Normally should not be changed. */
1772#define PXP2_REG_RD_SR_NUM_CFG 0x120408
1773/* [RW 1] Signals the PSWRD block to start initializing internal memories */
1774#define PXP2_REG_RD_START_INIT 0x12036c
1775/* [RW 2] TM byte swapping mode configuration for master read requests */
1776#define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
1777/* [RW 10] Bandwidth addition to VQ0 write requests */
1778#define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
1779/* [RW 10] Bandwidth addition to VQ12 read requests */
1780#define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
1781/* [RW 10] Bandwidth addition to VQ13 read requests */
1782#define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
1783/* [RW 10] Bandwidth addition to VQ14 read requests */
1784#define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
1785/* [RW 10] Bandwidth addition to VQ15 read requests */
1786#define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
1787/* [RW 10] Bandwidth addition to VQ16 read requests */
1788#define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
1789/* [RW 10] Bandwidth addition to VQ17 read requests */
1790#define PXP2_REG_RQ_BW_RD_ADD17 0x120200
1791/* [RW 10] Bandwidth addition to VQ18 read requests */
1792#define PXP2_REG_RQ_BW_RD_ADD18 0x120204
1793/* [RW 10] Bandwidth addition to VQ19 read requests */
1794#define PXP2_REG_RQ_BW_RD_ADD19 0x120208
1795/* [RW 10] Bandwidth addition to VQ20 read requests */
1796#define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
1797/* [RW 10] Bandwidth addition to VQ22 read requests */
1798#define PXP2_REG_RQ_BW_RD_ADD22 0x120210
1799/* [RW 10] Bandwidth addition to VQ23 read requests */
1800#define PXP2_REG_RQ_BW_RD_ADD23 0x120214
1801/* [RW 10] Bandwidth addition to VQ24 read requests */
1802#define PXP2_REG_RQ_BW_RD_ADD24 0x120218
1803/* [RW 10] Bandwidth addition to VQ25 read requests */
1804#define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
1805/* [RW 10] Bandwidth addition to VQ26 read requests */
1806#define PXP2_REG_RQ_BW_RD_ADD26 0x120220
1807/* [RW 10] Bandwidth addition to VQ27 read requests */
1808#define PXP2_REG_RQ_BW_RD_ADD27 0x120224
1809/* [RW 10] Bandwidth addition to VQ4 read requests */
1810#define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
1811/* [RW 10] Bandwidth addition to VQ5 read requests */
1812#define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
1813/* [RW 10] Bandwidth Typical L for VQ0 Read requests */
1814#define PXP2_REG_RQ_BW_RD_L0 0x1202ac
1815/* [RW 10] Bandwidth Typical L for VQ12 Read requests */
1816#define PXP2_REG_RQ_BW_RD_L12 0x1202dc
1817/* [RW 10] Bandwidth Typical L for VQ13 Read requests */
1818#define PXP2_REG_RQ_BW_RD_L13 0x1202e0
1819/* [RW 10] Bandwidth Typical L for VQ14 Read requests */
1820#define PXP2_REG_RQ_BW_RD_L14 0x1202e4
1821/* [RW 10] Bandwidth Typical L for VQ15 Read requests */
1822#define PXP2_REG_RQ_BW_RD_L15 0x1202e8
1823/* [RW 10] Bandwidth Typical L for VQ16 Read requests */
1824#define PXP2_REG_RQ_BW_RD_L16 0x1202ec
1825/* [RW 10] Bandwidth Typical L for VQ17 Read requests */
1826#define PXP2_REG_RQ_BW_RD_L17 0x1202f0
1827/* [RW 10] Bandwidth Typical L for VQ18 Read requests */
1828#define PXP2_REG_RQ_BW_RD_L18 0x1202f4
1829/* [RW 10] Bandwidth Typical L for VQ19 Read requests */
1830#define PXP2_REG_RQ_BW_RD_L19 0x1202f8
1831/* [RW 10] Bandwidth Typical L for VQ20 Read requests */
1832#define PXP2_REG_RQ_BW_RD_L20 0x1202fc
1833/* [RW 10] Bandwidth Typical L for VQ22 Read requests */
1834#define PXP2_REG_RQ_BW_RD_L22 0x120300
1835/* [RW 10] Bandwidth Typical L for VQ23 Read requests */
1836#define PXP2_REG_RQ_BW_RD_L23 0x120304
1837/* [RW 10] Bandwidth Typical L for VQ24 Read requests */
1838#define PXP2_REG_RQ_BW_RD_L24 0x120308
1839/* [RW 10] Bandwidth Typical L for VQ25 Read requests */
1840#define PXP2_REG_RQ_BW_RD_L25 0x12030c
1841/* [RW 10] Bandwidth Typical L for VQ26 Read requests */
1842#define PXP2_REG_RQ_BW_RD_L26 0x120310
1843/* [RW 10] Bandwidth Typical L for VQ27 Read requests */
1844#define PXP2_REG_RQ_BW_RD_L27 0x120314
1845/* [RW 10] Bandwidth Typical L for VQ4 Read requests */
1846#define PXP2_REG_RQ_BW_RD_L4 0x1202bc
1847/* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
1848#define PXP2_REG_RQ_BW_RD_L5 0x1202c0
1849/* [RW 7] Bandwidth upper bound for VQ0 read requests */
1850#define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
1851/* [RW 7] Bandwidth upper bound for VQ12 read requests */
1852#define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
1853/* [RW 7] Bandwidth upper bound for VQ13 read requests */
1854#define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
1855/* [RW 7] Bandwidth upper bound for VQ14 read requests */
1856#define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
1857/* [RW 7] Bandwidth upper bound for VQ15 read requests */
1858#define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
1859/* [RW 7] Bandwidth upper bound for VQ16 read requests */
1860#define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
1861/* [RW 7] Bandwidth upper bound for VQ17 read requests */
1862#define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
1863/* [RW 7] Bandwidth upper bound for VQ18 read requests */
1864#define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
1865/* [RW 7] Bandwidth upper bound for VQ19 read requests */
1866#define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
1867/* [RW 7] Bandwidth upper bound for VQ20 read requests */
1868#define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
1869/* [RW 7] Bandwidth upper bound for VQ22 read requests */
1870#define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
1871/* [RW 7] Bandwidth upper bound for VQ23 read requests */
1872#define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
1873/* [RW 7] Bandwidth upper bound for VQ24 read requests */
1874#define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
1875/* [RW 7] Bandwidth upper bound for VQ25 read requests */
1876#define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
1877/* [RW 7] Bandwidth upper bound for VQ26 read requests */
1878#define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
1879/* [RW 7] Bandwidth upper bound for VQ27 read requests */
1880#define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
1881/* [RW 7] Bandwidth upper bound for VQ4 read requests */
1882#define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
1883/* [RW 7] Bandwidth upper bound for VQ5 read requests */
1884#define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
1885/* [RW 10] Bandwidth addition to VQ29 write requests */
1886#define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
1887/* [RW 10] Bandwidth addition to VQ30 write requests */
1888#define PXP2_REG_RQ_BW_WR_ADD30 0x120230
1889/* [RW 10] Bandwidth Typical L for VQ29 Write requests */
1890#define PXP2_REG_RQ_BW_WR_L29 0x12031c
1891/* [RW 10] Bandwidth Typical L for VQ30 Write requests */
1892#define PXP2_REG_RQ_BW_WR_L30 0x120320
1893/* [RW 7] Bandwidth upper bound for VQ29 */
1894#define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
1895/* [RW 7] Bandwidth upper bound for VQ30 */
1896#define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
1897/* [RW 2] Endian mode for cdu */
1898#define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
1899/* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
1900 -128k */
1901#define PXP2_REG_RQ_CDU_P_SIZE 0x120018
1902/* [R 1] 1' indicates that the requester has finished its internal
1903 configuration */
1904#define PXP2_REG_RQ_CFG_DONE 0x1201b4
1905/* [RW 2] Endian mode for debug */
1906#define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
1907/* [RW 1] When '1'; requests will enter input buffers but wont get out
1908 towards the glue */
1909#define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
1910/* [RW 2] Endian mode for hc */
1911#define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
1912/* [WB 53] Onchip address table */
1913#define PXP2_REG_RQ_ONCHIP_AT 0x122000
1914/* [RW 2] Endian mode for qm */
1915#define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
1916/* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
1917 -128k */
1918#define PXP2_REG_RQ_QM_P_SIZE 0x120050
1919/* [RW 1] 1' indicates that the RBC has finished configurating the PSWRQ */
1920#define PXP2_REG_RQ_RBC_DONE 0x1201b0
1921/* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
1922 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
1923#define PXP2_REG_RQ_RD_MBS0 0x120160
1924/* [RW 2] Endian mode for src */
1925#define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
1926/* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
1927 -128k */
1928#define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
1929/* [RW 2] Endian mode for tm */
1930#define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
1931/* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
1932 -128k */
1933#define PXP2_REG_RQ_TM_P_SIZE 0x120034
1934/* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
1935#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
1936/* [R 8] Number of entries occupied by vq 0 in pswrq memory */
1937#define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
1938/* [R 8] Number of entries occupied by vq 10 in pswrq memory */
1939#define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
1940/* [R 8] Number of entries occupied by vq 11 in pswrq memory */
1941#define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
1942/* [R 8] Number of entries occupied by vq 12 in pswrq memory */
1943#define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
1944/* [R 8] Number of entries occupied by vq 13 in pswrq memory */
1945#define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
1946/* [R 8] Number of entries occupied by vq 14 in pswrq memory */
1947#define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
1948/* [R 8] Number of entries occupied by vq 15 in pswrq memory */
1949#define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
1950/* [R 8] Number of entries occupied by vq 16 in pswrq memory */
1951#define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
1952/* [R 8] Number of entries occupied by vq 17 in pswrq memory */
1953#define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
1954/* [R 8] Number of entries occupied by vq 18 in pswrq memory */
1955#define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
1956/* [R 8] Number of entries occupied by vq 19 in pswrq memory */
1957#define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
1958/* [R 8] Number of entries occupied by vq 1 in pswrq memory */
1959#define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
1960/* [R 8] Number of entries occupied by vq 20 in pswrq memory */
1961#define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
1962/* [R 8] Number of entries occupied by vq 21 in pswrq memory */
1963#define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
1964/* [R 8] Number of entries occupied by vq 22 in pswrq memory */
1965#define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
1966/* [R 8] Number of entries occupied by vq 23 in pswrq memory */
1967#define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
1968/* [R 8] Number of entries occupied by vq 24 in pswrq memory */
1969#define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
1970/* [R 8] Number of entries occupied by vq 25 in pswrq memory */
1971#define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
1972/* [R 8] Number of entries occupied by vq 26 in pswrq memory */
1973#define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
1974/* [R 8] Number of entries occupied by vq 27 in pswrq memory */
1975#define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
1976/* [R 8] Number of entries occupied by vq 28 in pswrq memory */
1977#define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
1978/* [R 8] Number of entries occupied by vq 29 in pswrq memory */
1979#define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
1980/* [R 8] Number of entries occupied by vq 2 in pswrq memory */
1981#define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
1982/* [R 8] Number of entries occupied by vq 30 in pswrq memory */
1983#define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
1984/* [R 8] Number of entries occupied by vq 31 in pswrq memory */
1985#define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
1986/* [R 8] Number of entries occupied by vq 3 in pswrq memory */
1987#define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
1988/* [R 8] Number of entries occupied by vq 4 in pswrq memory */
1989#define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
1990/* [R 8] Number of entries occupied by vq 5 in pswrq memory */
1991#define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
1992/* [R 8] Number of entries occupied by vq 6 in pswrq memory */
1993#define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
1994/* [R 8] Number of entries occupied by vq 7 in pswrq memory */
1995#define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
1996/* [R 8] Number of entries occupied by vq 8 in pswrq memory */
1997#define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
1998/* [R 8] Number of entries occupied by vq 9 in pswrq memory */
1999#define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
2000/* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
2001 001:256B; 010: 512B; */
2002#define PXP2_REG_RQ_WR_MBS0 0x12015c
2003/* [RW 10] if Number of entries in dmae fifo will be higer than this
2004 threshold then has_payload indication will be asserted; the default value
2005 should be equal to &gt; write MBS size! */
2006#define PXP2_REG_WR_DMAE_TH 0x120368
2007/* [R 1] debug only: Indication if PSWHST arbiter is idle */
2008#define PXP_REG_HST_ARB_IS_IDLE 0x103004
2009/* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
2010 this client is waiting for the arbiter. */
2011#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
2012/* [WB 160] Used for initialization of the inbound interrupts memory */
2013#define PXP_REG_HST_INBOUND_INT 0x103800
2014/* [RW 32] Interrupt mask register #0 read/write */
2015#define PXP_REG_PXP_INT_MASK_0 0x103074
2016#define PXP_REG_PXP_INT_MASK_1 0x103084
2017/* [R 32] Interrupt register #0 read */
2018#define PXP_REG_PXP_INT_STS_0 0x103068
2019#define PXP_REG_PXP_INT_STS_1 0x103078
2020/* [RC 32] Interrupt register #0 read clear */
2021#define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
2022/* [RW 26] Parity mask register #0 read/write */
2023#define PXP_REG_PXP_PRTY_MASK 0x103094
2024/* [RW 4] The activity counter initial increment value sent in the load
2025 request */
2026#define QM_REG_ACTCTRINITVAL_0 0x168040
2027#define QM_REG_ACTCTRINITVAL_1 0x168044
2028#define QM_REG_ACTCTRINITVAL_2 0x168048
2029#define QM_REG_ACTCTRINITVAL_3 0x16804c
2030/* [RW 32] The base logical address (in bytes) of each physical queue. The
2031 index I represents the physical queue number. The 12 lsbs are ignore and
2032 considered zero so practically there are only 20 bits in this register. */
2033#define QM_REG_BASEADDR 0x168900
2034/* [RW 16] The byte credit cost for each task. This value is for both ports */
2035#define QM_REG_BYTECRDCOST 0x168234
2036/* [RW 16] The initial byte credit value for both ports. */
2037#define QM_REG_BYTECRDINITVAL 0x168238
2038/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2039 queue uses port 0 else it uses port 1. */
2040#define QM_REG_BYTECRDPORT_LSB 0x168228
2041/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2042 queue uses port 0 else it uses port 1. */
2043#define QM_REG_BYTECRDPORT_MSB 0x168224
2044/* [RW 16] The byte credit value that if above the QM is considered almost
2045 full */
2046#define QM_REG_BYTECREDITAFULLTHR 0x168094
2047/* [RW 4] The initial credit for interface */
2048#define QM_REG_CMINITCRD_0 0x1680cc
2049#define QM_REG_CMINITCRD_1 0x1680d0
2050#define QM_REG_CMINITCRD_2 0x1680d4
2051#define QM_REG_CMINITCRD_3 0x1680d8
2052#define QM_REG_CMINITCRD_4 0x1680dc
2053#define QM_REG_CMINITCRD_5 0x1680e0
2054#define QM_REG_CMINITCRD_6 0x1680e4
2055#define QM_REG_CMINITCRD_7 0x1680e8
2056/* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
2057 is masked */
2058#define QM_REG_CMINTEN 0x1680ec
2059/* [RW 12] A bit vector which indicates which one of the queues are tied to
2060 interface 0 */
2061#define QM_REG_CMINTVOQMASK_0 0x1681f4
2062#define QM_REG_CMINTVOQMASK_1 0x1681f8
2063#define QM_REG_CMINTVOQMASK_2 0x1681fc
2064#define QM_REG_CMINTVOQMASK_3 0x168200
2065#define QM_REG_CMINTVOQMASK_4 0x168204
2066#define QM_REG_CMINTVOQMASK_5 0x168208
2067#define QM_REG_CMINTVOQMASK_6 0x16820c
2068#define QM_REG_CMINTVOQMASK_7 0x168210
2069/* [RW 20] The number of connections divided by 16 which dictates the size
2070 of each queue per port 0 */
2071#define QM_REG_CONNNUM_0 0x168020
2072/* [R 6] Keep the fill level of the fifo from write client 4 */
2073#define QM_REG_CQM_WRC_FIFOLVL 0x168018
2074/* [RW 8] The context regions sent in the CFC load request */
2075#define QM_REG_CTXREG_0 0x168030
2076#define QM_REG_CTXREG_1 0x168034
2077#define QM_REG_CTXREG_2 0x168038
2078#define QM_REG_CTXREG_3 0x16803c
2079/* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
2080 bypass enable */
2081#define QM_REG_ENBYPVOQMASK 0x16823c
2082/* [RW 32] A bit mask per each physical queue. If a bit is set then the
2083 physical queue uses the byte credit */
2084#define QM_REG_ENBYTECRD_LSB 0x168220
2085/* [RW 32] A bit mask per each physical queue. If a bit is set then the
2086 physical queue uses the byte credit */
2087#define QM_REG_ENBYTECRD_MSB 0x16821c
2088/* [RW 4] If cleared then the secondary interface will not be served by the
2089 RR arbiter */
2090#define QM_REG_ENSEC 0x1680f0
2091/* [RW 32] A bit vector per each physical queue which selects which function
2092 number to use on PCI access for that queue. */
2093#define QM_REG_FUNCNUMSEL_LSB 0x168230
2094/* [RW 32] A bit vector per each physical queue which selects which function
2095 number to use on PCI access for that queue. */
2096#define QM_REG_FUNCNUMSEL_MSB 0x16822c
2097/* [RW 32] A mask register to mask the Almost empty signals which will not
2098 be use for the almost empty indication to the HW block */
2099#define QM_REG_HWAEMPTYMASK_LSB 0x168218
2100/* [RW 32] A mask register to mask the Almost empty signals which will not
2101 be use for the almost empty indication to the HW block */
2102#define QM_REG_HWAEMPTYMASK_MSB 0x168214
2103/* [RW 4] The number of outstanding request to CFC */
2104#define QM_REG_OUTLDREQ 0x168804
2105/* [RC 1] A flag to indicate that overflow error occurred in one of the
2106 queues. */
2107#define QM_REG_OVFERROR 0x16805c
2108/* [RC 6] the Q were the qverflow occurs */
2109#define QM_REG_OVFQNUM 0x168058
2110/* [R 32] Pause state for physical queues 31-0 */
2111#define QM_REG_PAUSESTATE0 0x168410
2112/* [R 32] Pause state for physical queues 64-32 */
2113#define QM_REG_PAUSESTATE1 0x168414
2114/* [RW 2] The PCI attributes field used in the PCI request. */
2115#define QM_REG_PCIREQAT 0x168054
2116/* [R 16] The byte credit of port 0 */
2117#define QM_REG_PORT0BYTECRD 0x168300
2118/* [R 16] The byte credit of port 1 */
2119#define QM_REG_PORT1BYTECRD 0x168304
2120/* [WB 54] Pointer Table Memory; The mapping is as follow: ptrtbl[53:30]
2121 read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read bank0;
2122 ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
2123#define QM_REG_PTRTBL 0x168a00
2124/* [RW 2] Interrupt mask register #0 read/write */
2125#define QM_REG_QM_INT_MASK 0x168444
2126/* [R 2] Interrupt register #0 read */
2127#define QM_REG_QM_INT_STS 0x168438
2128/* [RW 9] Parity mask register #0 read/write */
2129#define QM_REG_QM_PRTY_MASK 0x168454
2130/* [R 32] Current queues in pipeline: Queues from 32 to 63 */
2131#define QM_REG_QSTATUS_HIGH 0x16802c
2132/* [R 32] Current queues in pipeline: Queues from 0 to 31 */
2133#define QM_REG_QSTATUS_LOW 0x168028
2134/* [R 24] The number of tasks queued for each queue */
2135#define QM_REG_QTASKCTR_0 0x168308
2136/* [RW 4] Queue tied to VOQ */
2137#define QM_REG_QVOQIDX_0 0x1680f4
2138#define QM_REG_QVOQIDX_10 0x16811c
2139#define QM_REG_QVOQIDX_11 0x168120
2140#define QM_REG_QVOQIDX_12 0x168124
2141#define QM_REG_QVOQIDX_13 0x168128
2142#define QM_REG_QVOQIDX_14 0x16812c
2143#define QM_REG_QVOQIDX_15 0x168130
2144#define QM_REG_QVOQIDX_16 0x168134
2145#define QM_REG_QVOQIDX_17 0x168138
2146#define QM_REG_QVOQIDX_21 0x168148
2147#define QM_REG_QVOQIDX_25 0x168158
2148#define QM_REG_QVOQIDX_29 0x168168
2149#define QM_REG_QVOQIDX_32 0x168174
2150#define QM_REG_QVOQIDX_33 0x168178
2151#define QM_REG_QVOQIDX_34 0x16817c
2152#define QM_REG_QVOQIDX_35 0x168180
2153#define QM_REG_QVOQIDX_36 0x168184
2154#define QM_REG_QVOQIDX_37 0x168188
2155#define QM_REG_QVOQIDX_38 0x16818c
2156#define QM_REG_QVOQIDX_39 0x168190
2157#define QM_REG_QVOQIDX_40 0x168194
2158#define QM_REG_QVOQIDX_41 0x168198
2159#define QM_REG_QVOQIDX_42 0x16819c
2160#define QM_REG_QVOQIDX_43 0x1681a0
2161#define QM_REG_QVOQIDX_44 0x1681a4
2162#define QM_REG_QVOQIDX_45 0x1681a8
2163#define QM_REG_QVOQIDX_46 0x1681ac
2164#define QM_REG_QVOQIDX_47 0x1681b0
2165#define QM_REG_QVOQIDX_48 0x1681b4
2166#define QM_REG_QVOQIDX_49 0x1681b8
2167#define QM_REG_QVOQIDX_5 0x168108
2168#define QM_REG_QVOQIDX_50 0x1681bc
2169#define QM_REG_QVOQIDX_51 0x1681c0
2170#define QM_REG_QVOQIDX_52 0x1681c4
2171#define QM_REG_QVOQIDX_53 0x1681c8
2172#define QM_REG_QVOQIDX_54 0x1681cc
2173#define QM_REG_QVOQIDX_55 0x1681d0
2174#define QM_REG_QVOQIDX_56 0x1681d4
2175#define QM_REG_QVOQIDX_57 0x1681d8
2176#define QM_REG_QVOQIDX_58 0x1681dc
2177#define QM_REG_QVOQIDX_59 0x1681e0
2178#define QM_REG_QVOQIDX_50 0x1681bc
2179#define QM_REG_QVOQIDX_51 0x1681c0
2180#define QM_REG_QVOQIDX_52 0x1681c4
2181#define QM_REG_QVOQIDX_53 0x1681c8
2182#define QM_REG_QVOQIDX_54 0x1681cc
2183#define QM_REG_QVOQIDX_55 0x1681d0
2184#define QM_REG_QVOQIDX_56 0x1681d4
2185#define QM_REG_QVOQIDX_57 0x1681d8
2186#define QM_REG_QVOQIDX_58 0x1681dc
2187#define QM_REG_QVOQIDX_59 0x1681e0
2188#define QM_REG_QVOQIDX_6 0x16810c
2189#define QM_REG_QVOQIDX_60 0x1681e4
2190#define QM_REG_QVOQIDX_61 0x1681e8
2191#define QM_REG_QVOQIDX_62 0x1681ec
2192#define QM_REG_QVOQIDX_63 0x1681f0
2193#define QM_REG_QVOQIDX_60 0x1681e4
2194#define QM_REG_QVOQIDX_61 0x1681e8
2195#define QM_REG_QVOQIDX_62 0x1681ec
2196#define QM_REG_QVOQIDX_63 0x1681f0
2197#define QM_REG_QVOQIDX_7 0x168110
2198#define QM_REG_QVOQIDX_8 0x168114
2199#define QM_REG_QVOQIDX_9 0x168118
2200/* [R 24] Remaining pause timeout for port 0 */
2201#define QM_REG_REMAINPAUSETM0 0x168418
2202/* [R 24] Remaining pause timeout for port 1 */
2203#define QM_REG_REMAINPAUSETM1 0x16841c
2204/* [RW 1] Initialization bit command */
2205#define QM_REG_SOFT_RESET 0x168428
2206/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
2207#define QM_REG_TASKCRDCOST_0 0x16809c
2208#define QM_REG_TASKCRDCOST_1 0x1680a0
2209#define QM_REG_TASKCRDCOST_10 0x1680c4
2210#define QM_REG_TASKCRDCOST_11 0x1680c8
2211#define QM_REG_TASKCRDCOST_2 0x1680a4
2212#define QM_REG_TASKCRDCOST_4 0x1680ac
2213#define QM_REG_TASKCRDCOST_5 0x1680b0
2214/* [R 6] Keep the fill level of the fifo from write client 3 */
2215#define QM_REG_TQM_WRC_FIFOLVL 0x168010
2216/* [R 6] Keep the fill level of the fifo from write client 2 */
2217#define QM_REG_UQM_WRC_FIFOLVL 0x168008
2218/* [RC 32] Credit update error register */
2219#define QM_REG_VOQCRDERRREG 0x168408
2220/* [R 16] The credit value for each VOQ */
2221#define QM_REG_VOQCREDIT_0 0x1682d0
2222#define QM_REG_VOQCREDIT_1 0x1682d4
2223#define QM_REG_VOQCREDIT_10 0x1682f8
2224#define QM_REG_VOQCREDIT_11 0x1682fc
2225#define QM_REG_VOQCREDIT_4 0x1682e0
2226/* [RW 16] The credit value that if above the QM is considered almost full */
2227#define QM_REG_VOQCREDITAFULLTHR 0x168090
2228/* [RW 16] The init and maximum credit for each VoQ */
2229#define QM_REG_VOQINITCREDIT_0 0x168060
2230#define QM_REG_VOQINITCREDIT_1 0x168064
2231#define QM_REG_VOQINITCREDIT_10 0x168088
2232#define QM_REG_VOQINITCREDIT_11 0x16808c
2233#define QM_REG_VOQINITCREDIT_2 0x168068
2234#define QM_REG_VOQINITCREDIT_4 0x168070
2235#define QM_REG_VOQINITCREDIT_5 0x168074
2236/* [RW 1] The port of which VOQ belongs */
2237#define QM_REG_VOQPORT_1 0x1682a4
2238#define QM_REG_VOQPORT_10 0x1682c8
2239#define QM_REG_VOQPORT_11 0x1682cc
2240#define QM_REG_VOQPORT_2 0x1682a8
2241/* [RW 32] The physical queue number associated with each VOQ */
2242#define QM_REG_VOQQMASK_0_LSB 0x168240
2243/* [RW 32] The physical queue number associated with each VOQ */
2244#define QM_REG_VOQQMASK_0_MSB 0x168244
2245/* [RW 32] The physical queue number associated with each VOQ */
2246#define QM_REG_VOQQMASK_1_MSB 0x16824c
2247/* [RW 32] The physical queue number associated with each VOQ */
2248#define QM_REG_VOQQMASK_2_LSB 0x168250
2249/* [RW 32] The physical queue number associated with each VOQ */
2250#define QM_REG_VOQQMASK_2_MSB 0x168254
2251/* [RW 32] The physical queue number associated with each VOQ */
2252#define QM_REG_VOQQMASK_3_LSB 0x168258
2253/* [RW 32] The physical queue number associated with each VOQ */
2254#define QM_REG_VOQQMASK_4_LSB 0x168260
2255/* [RW 32] The physical queue number associated with each VOQ */
2256#define QM_REG_VOQQMASK_4_MSB 0x168264
2257/* [RW 32] The physical queue number associated with each VOQ */
2258#define QM_REG_VOQQMASK_5_LSB 0x168268
2259/* [RW 32] The physical queue number associated with each VOQ */
2260#define QM_REG_VOQQMASK_5_MSB 0x16826c
2261/* [RW 32] The physical queue number associated with each VOQ */
2262#define QM_REG_VOQQMASK_6_LSB 0x168270
2263/* [RW 32] The physical queue number associated with each VOQ */
2264#define QM_REG_VOQQMASK_6_MSB 0x168274
2265/* [RW 32] The physical queue number associated with each VOQ */
2266#define QM_REG_VOQQMASK_7_LSB 0x168278
2267/* [RW 32] The physical queue number associated with each VOQ */
2268#define QM_REG_VOQQMASK_7_MSB 0x16827c
2269/* [RW 32] The physical queue number associated with each VOQ */
2270#define QM_REG_VOQQMASK_8_LSB 0x168280
2271/* [RW 32] The physical queue number associated with each VOQ */
2272#define QM_REG_VOQQMASK_8_MSB 0x168284
2273/* [RW 32] The physical queue number associated with each VOQ */
2274#define QM_REG_VOQQMASK_9_LSB 0x168288
2275/* [RW 32] Wrr weights */
2276#define QM_REG_WRRWEIGHTS_0 0x16880c
2277#define QM_REG_WRRWEIGHTS_1 0x168810
2278#define QM_REG_WRRWEIGHTS_10 0x168814
2279#define QM_REG_WRRWEIGHTS_10_SIZE 1
2280/* [RW 32] Wrr weights */
2281#define QM_REG_WRRWEIGHTS_11 0x168818
2282#define QM_REG_WRRWEIGHTS_11_SIZE 1
2283/* [RW 32] Wrr weights */
2284#define QM_REG_WRRWEIGHTS_12 0x16881c
2285#define QM_REG_WRRWEIGHTS_12_SIZE 1
2286/* [RW 32] Wrr weights */
2287#define QM_REG_WRRWEIGHTS_13 0x168820
2288#define QM_REG_WRRWEIGHTS_13_SIZE 1
2289/* [RW 32] Wrr weights */
2290#define QM_REG_WRRWEIGHTS_14 0x168824
2291#define QM_REG_WRRWEIGHTS_14_SIZE 1
2292/* [RW 32] Wrr weights */
2293#define QM_REG_WRRWEIGHTS_15 0x168828
2294#define QM_REG_WRRWEIGHTS_15_SIZE 1
2295/* [RW 32] Wrr weights */
2296#define QM_REG_WRRWEIGHTS_10 0x168814
2297#define QM_REG_WRRWEIGHTS_11 0x168818
2298#define QM_REG_WRRWEIGHTS_12 0x16881c
2299#define QM_REG_WRRWEIGHTS_13 0x168820
2300#define QM_REG_WRRWEIGHTS_14 0x168824
2301#define QM_REG_WRRWEIGHTS_15 0x168828
2302#define QM_REG_WRRWEIGHTS_2 0x16882c
2303#define QM_REG_WRRWEIGHTS_3 0x168830
2304#define QM_REG_WRRWEIGHTS_4 0x168834
2305#define QM_REG_WRRWEIGHTS_5 0x168838
2306#define QM_REG_WRRWEIGHTS_6 0x16883c
2307#define QM_REG_WRRWEIGHTS_7 0x168840
2308#define QM_REG_WRRWEIGHTS_8 0x168844
2309#define QM_REG_WRRWEIGHTS_9 0x168848
2310/* [R 6] Keep the fill level of the fifo from write client 1 */
2311#define QM_REG_XQM_WRC_FIFOLVL 0x168000
2312#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2313#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0
2314#define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
2315#define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
2316#define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
2317#define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
2318#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
2319#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
2320#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
2321#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
2322#define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
2323#define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
2324#define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
2325#define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
2326#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
2327#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
2328#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2329#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
2330#define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
2331#define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
2332#define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
2333#define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
2334#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
2335#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
2336#define CFC_DEBUG1_REG_WRITE_AC (0x1<<4)
2337#define CFC_DEBUG1_REG_WRITE_AC_SIZE 4
2338/* [R 1] debug only: This bit indicates wheter indicates that external
2339 buffer was wrapped (oldest data was thrown); Relevant only when
2340 ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap); */
2341#define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124
2342#define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1
2343/* [R 1] debug only: This bit indicates wheter the internal buffer was
2344 wrapped (oldest data was thrown) Relevant only when
2345 ~dbg_registers_debug_target=0 (internal buffer) */
2346#define DBG_REG_WRAP_ON_INT_BUFFER 0xc128
2347#define DBG_REG_WRAP_ON_INT_BUFFER_SIZE 1
2348/* [RW 32] Wrr weights */
2349#define QM_REG_WRRWEIGHTS_0 0x16880c
2350#define QM_REG_WRRWEIGHTS_0_SIZE 1
2351/* [RW 32] Wrr weights */
2352#define QM_REG_WRRWEIGHTS_1 0x168810
2353#define QM_REG_WRRWEIGHTS_1_SIZE 1
2354/* [RW 32] Wrr weights */
2355#define QM_REG_WRRWEIGHTS_10 0x168814
2356#define QM_REG_WRRWEIGHTS_10_SIZE 1
2357/* [RW 32] Wrr weights */
2358#define QM_REG_WRRWEIGHTS_11 0x168818
2359#define QM_REG_WRRWEIGHTS_11_SIZE 1
2360/* [RW 32] Wrr weights */
2361#define QM_REG_WRRWEIGHTS_12 0x16881c
2362#define QM_REG_WRRWEIGHTS_12_SIZE 1
2363/* [RW 32] Wrr weights */
2364#define QM_REG_WRRWEIGHTS_13 0x168820
2365#define QM_REG_WRRWEIGHTS_13_SIZE 1
2366/* [RW 32] Wrr weights */
2367#define QM_REG_WRRWEIGHTS_14 0x168824
2368#define QM_REG_WRRWEIGHTS_14_SIZE 1
2369/* [RW 32] Wrr weights */
2370#define QM_REG_WRRWEIGHTS_15 0x168828
2371#define QM_REG_WRRWEIGHTS_15_SIZE 1
2372/* [RW 32] Wrr weights */
2373#define QM_REG_WRRWEIGHTS_2 0x16882c
2374#define QM_REG_WRRWEIGHTS_2_SIZE 1
2375/* [RW 32] Wrr weights */
2376#define QM_REG_WRRWEIGHTS_3 0x168830
2377#define QM_REG_WRRWEIGHTS_3_SIZE 1
2378/* [RW 32] Wrr weights */
2379#define QM_REG_WRRWEIGHTS_4 0x168834
2380#define QM_REG_WRRWEIGHTS_4_SIZE 1
2381/* [RW 32] Wrr weights */
2382#define QM_REG_WRRWEIGHTS_5 0x168838
2383#define QM_REG_WRRWEIGHTS_5_SIZE 1
2384/* [RW 32] Wrr weights */
2385#define QM_REG_WRRWEIGHTS_6 0x16883c
2386#define QM_REG_WRRWEIGHTS_6_SIZE 1
2387/* [RW 32] Wrr weights */
2388#define QM_REG_WRRWEIGHTS_7 0x168840
2389#define QM_REG_WRRWEIGHTS_7_SIZE 1
2390/* [RW 32] Wrr weights */
2391#define QM_REG_WRRWEIGHTS_8 0x168844
2392#define QM_REG_WRRWEIGHTS_8_SIZE 1
2393/* [RW 32] Wrr weights */
2394#define QM_REG_WRRWEIGHTS_9 0x168848
2395#define QM_REG_WRRWEIGHTS_9_SIZE 1
2396/* [RW 22] Number of free element in the free list of T2 entries - port 0. */
2397#define SRC_REG_COUNTFREE0 0x40500
2398/* [WB 64] First free element in the free list of T2 entries - port 0. */
2399#define SRC_REG_FIRSTFREE0 0x40510
2400#define SRC_REG_KEYRSS0_0 0x40408
2401#define SRC_REG_KEYRSS1_9 0x40454
2402/* [WB 64] Last free element in the free list of T2 entries - port 0. */
2403#define SRC_REG_LASTFREE0 0x40530
2404/* [RW 5] The number of hash bits used for the search (h); Values can be 8
2405 to 24. */
2406#define SRC_REG_NUMBER_HASH_BITS0 0x40400
2407/* [RW 1] Reset internal state machines. */
2408#define SRC_REG_SOFT_RST 0x4049c
2409/* [R 1] Interrupt register #0 read */
2410#define SRC_REG_SRC_INT_STS 0x404ac
2411/* [RW 3] Parity mask register #0 read/write */
2412#define SRC_REG_SRC_PRTY_MASK 0x404c8
2413/* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
2414#define TCM_REG_CAM_OCCUP 0x5017c
2415/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
2416 disregarded; valid output is deasserted; all other signals are treated as
2417 usual; if 1 - normal activity. */
2418#define TCM_REG_CDU_AG_RD_IFEN 0x50034
2419/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
2420 are disregarded; all other signals are treated as usual; if 1 - normal
2421 activity. */
2422#define TCM_REG_CDU_AG_WR_IFEN 0x50030
2423/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
2424 disregarded; valid output is deasserted; all other signals are treated as
2425 usual; if 1 - normal activity. */
2426#define TCM_REG_CDU_SM_RD_IFEN 0x5003c
2427/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
2428 input is disregarded; all other signals are treated as usual; if 1 -
2429 normal activity. */
2430#define TCM_REG_CDU_SM_WR_IFEN 0x50038
2431/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
2432 the initial credit value; read returns the current value of the credit
2433 counter. Must be initialized to 1 at start-up. */
2434#define TCM_REG_CFC_INIT_CRD 0x50204
2435/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
2436 weight 8 (the most prioritised); 1 stands for weight 1(least
2437 prioritised); 2 stands for weight 2; tc. */
2438#define TCM_REG_CP_WEIGHT 0x500c0
2439/* [RW 1] Input csem Interface enable. If 0 - the valid input is
2440 disregarded; acknowledge output is deasserted; all other signals are
2441 treated as usual; if 1 - normal activity. */
2442#define TCM_REG_CSEM_IFEN 0x5002c
2443/* [RC 1] Message length mismatch (relative to last indication) at the In#9
2444 interface. */
2445#define TCM_REG_CSEM_LENGTH_MIS 0x50174
2446/* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
2447#define TCM_REG_ERR_EVNT_ID 0x500a0
2448/* [RW 28] The CM erroneous header for QM and Timers formatting. */
2449#define TCM_REG_ERR_TCM_HDR 0x5009c
2450/* [RW 8] The Event ID for Timers expiration. */
2451#define TCM_REG_EXPR_EVNT_ID 0x500a4
2452/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
2453 writes the initial credit value; read returns the current value of the
2454 credit counter. Must be initialized to 64 at start-up. */
2455#define TCM_REG_FIC0_INIT_CRD 0x5020c
2456/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
2457 writes the initial credit value; read returns the current value of the
2458 credit counter. Must be initialized to 64 at start-up. */
2459#define TCM_REG_FIC1_INIT_CRD 0x50210
2460/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
2461 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
2462 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
2463 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
2464#define TCM_REG_GR_ARB_TYPE 0x50114
2465/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
2466 highest priority is 3. It is supposed that the Store channel is the
2467 compliment of the other 3 groups. */
2468#define TCM_REG_GR_LD0_PR 0x5011c
2469/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
2470 highest priority is 3. It is supposed that the Store channel is the
2471 compliment of the other 3 groups. */
2472#define TCM_REG_GR_LD1_PR 0x50120
2473/* [RW 4] The number of double REG-pairs; loaded from the STORM context and
2474 sent to STORM; for a specific connection type. The double REG-pairs are
2475 used to align to STORM context row size of 128 bits. The offset of these
2476 data in the STORM context is always 0. Index _i stands for the connection
2477 type (one of 16). */
2478#define TCM_REG_N_SM_CTX_LD_0 0x50050
2479#define TCM_REG_N_SM_CTX_LD_1 0x50054
2480#define TCM_REG_N_SM_CTX_LD_10 0x50078
2481#define TCM_REG_N_SM_CTX_LD_11 0x5007c
2482#define TCM_REG_N_SM_CTX_LD_12 0x50080
2483#define TCM_REG_N_SM_CTX_LD_13 0x50084
2484#define TCM_REG_N_SM_CTX_LD_14 0x50088
2485#define TCM_REG_N_SM_CTX_LD_15 0x5008c
2486#define TCM_REG_N_SM_CTX_LD_2 0x50058
2487#define TCM_REG_N_SM_CTX_LD_3 0x5005c
2488#define TCM_REG_N_SM_CTX_LD_4 0x50060
2489/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
2490 acknowledge output is deasserted; all other signals are treated as usual;
2491 if 1 - normal activity. */
2492#define TCM_REG_PBF_IFEN 0x50024
2493/* [RC 1] Message length mismatch (relative to last indication) at the In#7
2494 interface. */
2495#define TCM_REG_PBF_LENGTH_MIS 0x5016c
2496/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
2497 weight 8 (the most prioritised); 1 stands for weight 1(least
2498 prioritised); 2 stands for weight 2; tc. */
2499#define TCM_REG_PBF_WEIGHT 0x500b4
2500/* [RW 6] The physical queue number 0 per port index. */
2501#define TCM_REG_PHYS_QNUM0_0 0x500e0
2502#define TCM_REG_PHYS_QNUM0_1 0x500e4
2503/* [RW 6] The physical queue number 1 per port index. */
2504#define TCM_REG_PHYS_QNUM1_0 0x500e8
2505/* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
2506 acknowledge output is deasserted; all other signals are treated as usual;
2507 if 1 - normal activity. */
2508#define TCM_REG_PRS_IFEN 0x50020
2509/* [RC 1] Message length mismatch (relative to last indication) at the In#6
2510 interface. */
2511#define TCM_REG_PRS_LENGTH_MIS 0x50168
2512/* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
2513 weight 8 (the most prioritised); 1 stands for weight 1(least
2514 prioritised); 2 stands for weight 2; tc. */
2515#define TCM_REG_PRS_WEIGHT 0x500b0
2516/* [RW 8] The Event ID for Timers formatting in case of stop done. */
2517#define TCM_REG_STOP_EVNT_ID 0x500a8
2518/* [RC 1] Message length mismatch (relative to last indication) at the STORM
2519 interface. */
2520#define TCM_REG_STORM_LENGTH_MIS 0x50160
2521/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
2522 disregarded; acknowledge output is deasserted; all other signals are
2523 treated as usual; if 1 - normal activity. */
2524#define TCM_REG_STORM_TCM_IFEN 0x50010
2525/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
2526 acknowledge output is deasserted; all other signals are treated as usual;
2527 if 1 - normal activity. */
2528#define TCM_REG_TCM_CFC_IFEN 0x50040
2529/* [RW 11] Interrupt mask register #0 read/write */
2530#define TCM_REG_TCM_INT_MASK 0x501dc
2531/* [R 11] Interrupt register #0 read */
2532#define TCM_REG_TCM_INT_STS 0x501d0
2533/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
2534 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
2535 Is used to determine the number of the AG context REG-pairs written back;
2536 when the input message Reg1WbFlg isn't set. */
2537#define TCM_REG_TCM_REG0_SZ 0x500d8
2538/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
2539 disregarded; valid is deasserted; all other signals are treated as usual;
2540 if 1 - normal activity. */
2541#define TCM_REG_TCM_STORM0_IFEN 0x50004
2542/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
2543 disregarded; valid is deasserted; all other signals are treated as usual;
2544 if 1 - normal activity. */
2545#define TCM_REG_TCM_STORM1_IFEN 0x50008
2546/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
2547 disregarded; valid is deasserted; all other signals are treated as usual;
2548 if 1 - normal activity. */
2549#define TCM_REG_TCM_TQM_IFEN 0x5000c
2550/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
2551#define TCM_REG_TCM_TQM_USE_Q 0x500d4
2552/* [RW 28] The CM header for Timers expiration command. */
2553#define TCM_REG_TM_TCM_HDR 0x50098
2554/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
2555 disregarded; acknowledge output is deasserted; all other signals are
2556 treated as usual; if 1 - normal activity. */
2557#define TCM_REG_TM_TCM_IFEN 0x5001c
2558/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
2559 the initial credit value; read returns the current value of the credit
2560 counter. Must be initialized to 32 at start-up. */
2561#define TCM_REG_TQM_INIT_CRD 0x5021c
2562/* [RW 28] The CM header value for QM request (primary). */
2563#define TCM_REG_TQM_TCM_HDR_P 0x50090
2564/* [RW 28] The CM header value for QM request (secondary). */
2565#define TCM_REG_TQM_TCM_HDR_S 0x50094
2566/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
2567 acknowledge output is deasserted; all other signals are treated as usual;
2568 if 1 - normal activity. */
2569#define TCM_REG_TQM_TCM_IFEN 0x50014
2570/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
2571 acknowledge output is deasserted; all other signals are treated as usual;
2572 if 1 - normal activity. */
2573#define TCM_REG_TSDM_IFEN 0x50018
2574/* [RC 1] Message length mismatch (relative to last indication) at the SDM
2575 interface. */
2576#define TCM_REG_TSDM_LENGTH_MIS 0x50164
2577/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
2578 weight 8 (the most prioritised); 1 stands for weight 1(least
2579 prioritised); 2 stands for weight 2; tc. */
2580#define TCM_REG_TSDM_WEIGHT 0x500c4
2581/* [RW 1] Input usem Interface enable. If 0 - the valid input is
2582 disregarded; acknowledge output is deasserted; all other signals are
2583 treated as usual; if 1 - normal activity. */
2584#define TCM_REG_USEM_IFEN 0x50028
2585/* [RC 1] Message length mismatch (relative to last indication) at the In#8
2586 interface. */
2587#define TCM_REG_USEM_LENGTH_MIS 0x50170
2588/* [RW 21] Indirect access to the descriptor table of the XX protection
2589 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
2590 pointer; 20:16] - next pointer. */
2591#define TCM_REG_XX_DESCR_TABLE 0x50280
2592/* [R 6] Use to read the value of XX protection Free counter. */
2593#define TCM_REG_XX_FREE 0x50178
2594/* [RW 6] Initial value for the credit counter; responsible for fulfilling
2595 of the Input Stage XX protection buffer by the XX protection pending
2596 messages. Max credit available - 127.Write writes the initial credit
2597 value; read returns the current value of the credit counter. Must be
2598 initialized to 19 at start-up. */
2599#define TCM_REG_XX_INIT_CRD 0x50220
2600/* [RW 6] Maximum link list size (messages locked) per connection in the XX
2601 protection. */
2602#define TCM_REG_XX_MAX_LL_SZ 0x50044
2603/* [RW 6] The maximum number of pending messages; which may be stored in XX
2604 protection. ~tcm_registers_xx_free.xx_free is read on read. */
2605#define TCM_REG_XX_MSG_NUM 0x50224
2606/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
2607#define TCM_REG_XX_OVFL_EVNT_ID 0x50048
2608/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
2609 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
2610 header pointer. */
2611#define TCM_REG_XX_TABLE 0x50240
2612/* [RW 4] Load value for for cfc ac credit cnt. */
2613#define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
2614/* [RW 4] Load value for cfc cld credit cnt. */
2615#define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
2616/* [RW 8] Client0 context region. */
2617#define TM_REG_CL0_CONT_REGION 0x164030
2618/* [RW 8] Client1 context region. */
2619#define TM_REG_CL1_CONT_REGION 0x164034
2620/* [RW 8] Client2 context region. */
2621#define TM_REG_CL2_CONT_REGION 0x164038
2622/* [RW 2] Client in High priority client number. */
2623#define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
2624/* [RW 4] Load value for clout0 cred cnt. */
2625#define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
2626/* [RW 4] Load value for clout1 cred cnt. */
2627#define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
2628/* [RW 4] Load value for clout2 cred cnt. */
2629#define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
2630/* [RW 1] Enable client0 input. */
2631#define TM_REG_EN_CL0_INPUT 0x164008
2632/* [RW 1] Enable client1 input. */
2633#define TM_REG_EN_CL1_INPUT 0x16400c
2634/* [RW 1] Enable client2 input. */
2635#define TM_REG_EN_CL2_INPUT 0x164010
2636/* [RW 1] Enable real time counter. */
2637#define TM_REG_EN_REAL_TIME_CNT 0x1640d8
2638/* [RW 1] Enable for Timers state machines. */
2639#define TM_REG_EN_TIMERS 0x164000
2640/* [RW 4] Load value for expiration credit cnt. CFC max number of
2641 outstanding load requests for timers (expiration) context loading. */
2642#define TM_REG_EXP_CRDCNT_VAL 0x164238
2643/* [RW 18] Linear0 Max active cid. */
2644#define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
2645/* [WB 64] Linear0 phy address. */
2646#define TM_REG_LIN0_PHY_ADDR 0x164270
2647/* [RW 24] Linear0 array scan timeout. */
2648#define TM_REG_LIN0_SCAN_TIME 0x16403c
2649/* [WB 64] Linear1 phy address. */
2650#define TM_REG_LIN1_PHY_ADDR 0x164280
2651/* [RW 6] Linear timer set_clear fifo threshold. */
2652#define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
2653/* [RW 2] Load value for pci arbiter credit cnt. */
2654#define TM_REG_PCIARB_CRDCNT_VAL 0x164260
2655/* [RW 1] Timer software reset - active high. */
2656#define TM_REG_TIMER_SOFT_RST 0x164004
2657/* [RW 20] The amount of hardware cycles for each timer tick. */
2658#define TM_REG_TIMER_TICK_SIZE 0x16401c
2659/* [RW 8] Timers Context region. */
2660#define TM_REG_TM_CONTEXT_REGION 0x164044
2661/* [RW 1] Interrupt mask register #0 read/write */
2662#define TM_REG_TM_INT_MASK 0x1640fc
2663/* [R 1] Interrupt register #0 read */
2664#define TM_REG_TM_INT_STS 0x1640f0
2665/* [RW 8] The event id for aggregated interrupt 0 */
2666#define TSDM_REG_AGG_INT_EVENT_0 0x42038
2667/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
2668#define TSDM_REG_CFC_RSP_START_ADDR 0x42008
2669/* [RW 16] The maximum value of the competion counter #0 */
2670#define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
2671/* [RW 16] The maximum value of the competion counter #1 */
2672#define TSDM_REG_CMP_COUNTER_MAX1 0x42020
2673/* [RW 16] The maximum value of the competion counter #2 */
2674#define TSDM_REG_CMP_COUNTER_MAX2 0x42024
2675/* [RW 16] The maximum value of the competion counter #3 */
2676#define TSDM_REG_CMP_COUNTER_MAX3 0x42028
2677/* [RW 13] The start address in the internal RAM for the completion
2678 counters. */
2679#define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
2680#define TSDM_REG_ENABLE_IN1 0x42238
2681#define TSDM_REG_ENABLE_IN2 0x4223c
2682#define TSDM_REG_ENABLE_OUT1 0x42240
2683#define TSDM_REG_ENABLE_OUT2 0x42244
2684/* [RW 4] The initial number of messages that can be sent to the pxp control
2685 interface without receiving any ACK. */
2686#define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
2687/* [ST 32] The number of ACK after placement messages received */
2688#define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
2689/* [ST 32] The number of packet end messages received from the parser */
2690#define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
2691/* [ST 32] The number of requests received from the pxp async if */
2692#define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
2693/* [ST 32] The number of commands received in queue 0 */
2694#define TSDM_REG_NUM_OF_Q0_CMD 0x42248
2695/* [ST 32] The number of commands received in queue 10 */
2696#define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
2697/* [ST 32] The number of commands received in queue 11 */
2698#define TSDM_REG_NUM_OF_Q11_CMD 0x42270
2699/* [ST 32] The number of commands received in queue 1 */
2700#define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
2701/* [ST 32] The number of commands received in queue 3 */
2702#define TSDM_REG_NUM_OF_Q3_CMD 0x42250
2703/* [ST 32] The number of commands received in queue 4 */
2704#define TSDM_REG_NUM_OF_Q4_CMD 0x42254
2705/* [ST 32] The number of commands received in queue 5 */
2706#define TSDM_REG_NUM_OF_Q5_CMD 0x42258
2707/* [ST 32] The number of commands received in queue 6 */
2708#define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
2709/* [ST 32] The number of commands received in queue 7 */
2710#define TSDM_REG_NUM_OF_Q7_CMD 0x42260
2711/* [ST 32] The number of commands received in queue 8 */
2712#define TSDM_REG_NUM_OF_Q8_CMD 0x42264
2713/* [ST 32] The number of commands received in queue 9 */
2714#define TSDM_REG_NUM_OF_Q9_CMD 0x42268
2715/* [RW 13] The start address in the internal RAM for the packet end message */
2716#define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
2717/* [RW 13] The start address in the internal RAM for queue counters */
2718#define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
2719/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
2720#define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
2721/* [R 1] parser fifo empty in sdm_sync block */
2722#define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
2723/* [R 1] parser serial fifo empty in sdm_sync block */
2724#define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
2725/* [RW 32] Tick for timer counter. Applicable only when
2726 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
2727#define TSDM_REG_TIMER_TICK 0x42000
2728/* [RW 32] Interrupt mask register #0 read/write */
2729#define TSDM_REG_TSDM_INT_MASK_0 0x4229c
2730#define TSDM_REG_TSDM_INT_MASK_1 0x422ac
2731/* [RW 11] Parity mask register #0 read/write */
2732#define TSDM_REG_TSDM_PRTY_MASK 0x422bc
2733/* [RW 5] The number of time_slots in the arbitration cycle */
2734#define TSEM_REG_ARB_CYCLE_SIZE 0x180034
2735/* [RW 3] The source that is associated with arbitration element 0. Source
2736 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2737 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
2738#define TSEM_REG_ARB_ELEMENT0 0x180020
2739/* [RW 3] The source that is associated with arbitration element 1. Source
2740 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2741 sleeping thread with priority 1; 4- sleeping thread with priority 2.
2742 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
2743#define TSEM_REG_ARB_ELEMENT1 0x180024
2744/* [RW 3] The source that is associated with arbitration element 2. Source
2745 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2746 sleeping thread with priority 1; 4- sleeping thread with priority 2.
2747 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
2748 and ~tsem_registers_arb_element1.arb_element1 */
2749#define TSEM_REG_ARB_ELEMENT2 0x180028
2750/* [RW 3] The source that is associated with arbitration element 3. Source
2751 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2752 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
2753 not be equal to register ~tsem_registers_arb_element0.arb_element0 and
2754 ~tsem_registers_arb_element1.arb_element1 and
2755 ~tsem_registers_arb_element2.arb_element2 */
2756#define TSEM_REG_ARB_ELEMENT3 0x18002c
2757/* [RW 3] The source that is associated with arbitration element 4. Source
2758 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2759 sleeping thread with priority 1; 4- sleeping thread with priority 2.
2760 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
2761 and ~tsem_registers_arb_element1.arb_element1 and
2762 ~tsem_registers_arb_element2.arb_element2 and
2763 ~tsem_registers_arb_element3.arb_element3 */
2764#define TSEM_REG_ARB_ELEMENT4 0x180030
2765#define TSEM_REG_ENABLE_IN 0x1800a4
2766#define TSEM_REG_ENABLE_OUT 0x1800a8
2767/* [RW 32] This address space contains all registers and memories that are
2768 placed in SEM_FAST block. The SEM_FAST registers are described in
2769 appendix B. In order to access the SEM_FAST registers the base address
2770 TSEM_REGISTERS_FAST_MEMORY (Offset: 0x1a0000) should be added to each
2771 SEM_FAST register offset. */
2772#define TSEM_REG_FAST_MEMORY 0x1a0000
2773/* [RW 1] Disables input messages from FIC0 May be updated during run_time
2774 by the microcode */
2775#define TSEM_REG_FIC0_DISABLE 0x180224
2776/* [RW 1] Disables input messages from FIC1 May be updated during run_time
2777 by the microcode */
2778#define TSEM_REG_FIC1_DISABLE 0x180234
2779/* [RW 15] Interrupt table Read and write access to it is not possible in
2780 the middle of the work */
2781#define TSEM_REG_INT_TABLE 0x180400
2782/* [ST 24] Statistics register. The number of messages that entered through
2783 FIC0 */
2784#define TSEM_REG_MSG_NUM_FIC0 0x180000
2785/* [ST 24] Statistics register. The number of messages that entered through
2786 FIC1 */
2787#define TSEM_REG_MSG_NUM_FIC1 0x180004
2788/* [ST 24] Statistics register. The number of messages that were sent to
2789 FOC0 */
2790#define TSEM_REG_MSG_NUM_FOC0 0x180008
2791/* [ST 24] Statistics register. The number of messages that were sent to
2792 FOC1 */
2793#define TSEM_REG_MSG_NUM_FOC1 0x18000c
2794/* [ST 24] Statistics register. The number of messages that were sent to
2795 FOC2 */
2796#define TSEM_REG_MSG_NUM_FOC2 0x180010
2797/* [ST 24] Statistics register. The number of messages that were sent to
2798 FOC3 */
2799#define TSEM_REG_MSG_NUM_FOC3 0x180014
2800/* [RW 1] Disables input messages from the passive buffer May be updated
2801 during run_time by the microcode */
2802#define TSEM_REG_PAS_DISABLE 0x18024c
2803/* [WB 128] Debug only. Passive buffer memory */
2804#define TSEM_REG_PASSIVE_BUFFER 0x181000
2805/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
2806#define TSEM_REG_PRAM 0x1c0000
2807/* [R 8] Valid sleeping threads indication have bit per thread */
2808#define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
2809/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
2810#define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
2811/* [RW 8] List of free threads . There is a bit per thread. */
2812#define TSEM_REG_THREADS_LIST 0x1802e4
2813/* [RW 3] The arbitration scheme of time_slot 0 */
2814#define TSEM_REG_TS_0_AS 0x180038
2815/* [RW 3] The arbitration scheme of time_slot 10 */
2816#define TSEM_REG_TS_10_AS 0x180060
2817/* [RW 3] The arbitration scheme of time_slot 11 */
2818#define TSEM_REG_TS_11_AS 0x180064
2819/* [RW 3] The arbitration scheme of time_slot 12 */
2820#define TSEM_REG_TS_12_AS 0x180068
2821/* [RW 3] The arbitration scheme of time_slot 13 */
2822#define TSEM_REG_TS_13_AS 0x18006c
2823/* [RW 3] The arbitration scheme of time_slot 14 */
2824#define TSEM_REG_TS_14_AS 0x180070
2825/* [RW 3] The arbitration scheme of time_slot 15 */
2826#define TSEM_REG_TS_15_AS 0x180074
2827/* [RW 3] The arbitration scheme of time_slot 16 */
2828#define TSEM_REG_TS_16_AS 0x180078
2829/* [RW 3] The arbitration scheme of time_slot 17 */
2830#define TSEM_REG_TS_17_AS 0x18007c
2831/* [RW 3] The arbitration scheme of time_slot 18 */
2832#define TSEM_REG_TS_18_AS 0x180080
2833/* [RW 3] The arbitration scheme of time_slot 1 */
2834#define TSEM_REG_TS_1_AS 0x18003c
2835/* [RW 3] The arbitration scheme of time_slot 2 */
2836#define TSEM_REG_TS_2_AS 0x180040
2837/* [RW 3] The arbitration scheme of time_slot 3 */
2838#define TSEM_REG_TS_3_AS 0x180044
2839/* [RW 3] The arbitration scheme of time_slot 4 */
2840#define TSEM_REG_TS_4_AS 0x180048
2841/* [RW 3] The arbitration scheme of time_slot 5 */
2842#define TSEM_REG_TS_5_AS 0x18004c
2843/* [RW 3] The arbitration scheme of time_slot 6 */
2844#define TSEM_REG_TS_6_AS 0x180050
2845/* [RW 3] The arbitration scheme of time_slot 7 */
2846#define TSEM_REG_TS_7_AS 0x180054
2847/* [RW 3] The arbitration scheme of time_slot 8 */
2848#define TSEM_REG_TS_8_AS 0x180058
2849/* [RW 3] The arbitration scheme of time_slot 9 */
2850#define TSEM_REG_TS_9_AS 0x18005c
2851/* [RW 32] Interrupt mask register #0 read/write */
2852#define TSEM_REG_TSEM_INT_MASK_0 0x180100
2853#define TSEM_REG_TSEM_INT_MASK_1 0x180110
2854/* [RW 32] Parity mask register #0 read/write */
2855#define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
2856#define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
2857/* [R 5] Used to read the XX protection CAM occupancy counter. */
2858#define UCM_REG_CAM_OCCUP 0xe0170
2859/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
2860 disregarded; valid output is deasserted; all other signals are treated as
2861 usual; if 1 - normal activity. */
2862#define UCM_REG_CDU_AG_RD_IFEN 0xe0038
2863/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
2864 are disregarded; all other signals are treated as usual; if 1 - normal
2865 activity. */
2866#define UCM_REG_CDU_AG_WR_IFEN 0xe0034
2867/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
2868 disregarded; valid output is deasserted; all other signals are treated as
2869 usual; if 1 - normal activity. */
2870#define UCM_REG_CDU_SM_RD_IFEN 0xe0040
2871/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
2872 input is disregarded; all other signals are treated as usual; if 1 -
2873 normal activity. */
2874#define UCM_REG_CDU_SM_WR_IFEN 0xe003c
2875/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
2876 the initial credit value; read returns the current value of the credit
2877 counter. Must be initialized to 1 at start-up. */
2878#define UCM_REG_CFC_INIT_CRD 0xe0204
2879/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
2880 weight 8 (the most prioritised); 1 stands for weight 1(least
2881 prioritised); 2 stands for weight 2; tc. */
2882#define UCM_REG_CP_WEIGHT 0xe00c4
2883/* [RW 1] Input csem Interface enable. If 0 - the valid input is
2884 disregarded; acknowledge output is deasserted; all other signals are
2885 treated as usual; if 1 - normal activity. */
2886#define UCM_REG_CSEM_IFEN 0xe0028
2887/* [RC 1] Set when the message length mismatch (relative to last indication)
2888 at the csem interface is detected. */
2889#define UCM_REG_CSEM_LENGTH_MIS 0xe0160
2890/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
2891 weight 8 (the most prioritised); 1 stands for weight 1(least
2892 prioritised); 2 stands for weight 2; tc. */
2893#define UCM_REG_CSEM_WEIGHT 0xe00b8
2894/* [RW 1] Input dorq Interface enable. If 0 - the valid input is
2895 disregarded; acknowledge output is deasserted; all other signals are
2896 treated as usual; if 1 - normal activity. */
2897#define UCM_REG_DORQ_IFEN 0xe0030
2898/* [RC 1] Set when the message length mismatch (relative to last indication)
2899 at the dorq interface is detected. */
2900#define UCM_REG_DORQ_LENGTH_MIS 0xe0168
2901/* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
2902#define UCM_REG_ERR_EVNT_ID 0xe00a4
2903/* [RW 28] The CM erroneous header for QM and Timers formatting. */
2904#define UCM_REG_ERR_UCM_HDR 0xe00a0
2905/* [RW 8] The Event ID for Timers expiration. */
2906#define UCM_REG_EXPR_EVNT_ID 0xe00a8
2907/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
2908 writes the initial credit value; read returns the current value of the
2909 credit counter. Must be initialized to 64 at start-up. */
2910#define UCM_REG_FIC0_INIT_CRD 0xe020c
2911/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
2912 writes the initial credit value; read returns the current value of the
2913 credit counter. Must be initialized to 64 at start-up. */
2914#define UCM_REG_FIC1_INIT_CRD 0xe0210
2915/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
2916 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
2917 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
2918 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
2919#define UCM_REG_GR_ARB_TYPE 0xe0144
2920/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
2921 highest priority is 3. It is supposed that the Store channel group is
2922 compliment to the others. */
2923#define UCM_REG_GR_LD0_PR 0xe014c
2924/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
2925 highest priority is 3. It is supposed that the Store channel group is
2926 compliment to the others. */
2927#define UCM_REG_GR_LD1_PR 0xe0150
2928/* [RW 2] The queue index for invalidate counter flag decision. */
2929#define UCM_REG_INV_CFLG_Q 0xe00e4
2930/* [RW 5] The number of double REG-pairs; loaded from the STORM context and
2931 sent to STORM; for a specific connection type. the double REG-pairs are
2932 used in order to align to STORM context row size of 128 bits. The offset
2933 of these data in the STORM context is always 0. Index _i stands for the
2934 connection type (one of 16). */
2935#define UCM_REG_N_SM_CTX_LD_0 0xe0054
2936#define UCM_REG_N_SM_CTX_LD_1 0xe0058
2937#define UCM_REG_N_SM_CTX_LD_10 0xe007c
2938#define UCM_REG_N_SM_CTX_LD_11 0xe0080
2939#define UCM_REG_N_SM_CTX_LD_12 0xe0084
2940#define UCM_REG_N_SM_CTX_LD_13 0xe0088
2941#define UCM_REG_N_SM_CTX_LD_14 0xe008c
2942#define UCM_REG_N_SM_CTX_LD_15 0xe0090
2943#define UCM_REG_N_SM_CTX_LD_2 0xe005c
2944#define UCM_REG_N_SM_CTX_LD_3 0xe0060
2945#define UCM_REG_N_SM_CTX_LD_4 0xe0064
2946/* [RW 6] The physical queue number 0 per port index (CID[23]) */
2947#define UCM_REG_PHYS_QNUM0_0 0xe0110
2948#define UCM_REG_PHYS_QNUM0_1 0xe0114
2949/* [RW 6] The physical queue number 1 per port index (CID[23]) */
2950#define UCM_REG_PHYS_QNUM1_0 0xe0118
2951#define UCM_REG_PHYS_QNUM1_1 0xe011c
2952/* [RW 8] The Event ID for Timers formatting in case of stop done. */
2953#define UCM_REG_STOP_EVNT_ID 0xe00ac
2954/* [RC 1] Set when the message length mismatch (relative to last indication)
2955 at the STORM interface is detected. */
2956#define UCM_REG_STORM_LENGTH_MIS 0xe0154
2957/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
2958 disregarded; acknowledge output is deasserted; all other signals are
2959 treated as usual; if 1 - normal activity. */
2960#define UCM_REG_STORM_UCM_IFEN 0xe0010
2961/* [RW 4] Timers output initial credit. Max credit available - 15.Write
2962 writes the initial credit value; read returns the current value of the
2963 credit counter. Must be initialized to 4 at start-up. */
2964#define UCM_REG_TM_INIT_CRD 0xe021c
2965/* [RW 28] The CM header for Timers expiration command. */
2966#define UCM_REG_TM_UCM_HDR 0xe009c
2967/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
2968 disregarded; acknowledge output is deasserted; all other signals are
2969 treated as usual; if 1 - normal activity. */
2970#define UCM_REG_TM_UCM_IFEN 0xe001c
2971/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
2972 disregarded; acknowledge output is deasserted; all other signals are
2973 treated as usual; if 1 - normal activity. */
2974#define UCM_REG_TSEM_IFEN 0xe0024
2975/* [RC 1] Set when the message length mismatch (relative to last indication)
2976 at the tsem interface is detected. */
2977#define UCM_REG_TSEM_LENGTH_MIS 0xe015c
2978/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
2979 weight 8 (the most prioritised); 1 stands for weight 1(least
2980 prioritised); 2 stands for weight 2; tc. */
2981#define UCM_REG_TSEM_WEIGHT 0xe00b4
2982/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
2983 acknowledge output is deasserted; all other signals are treated as usual;
2984 if 1 - normal activity. */
2985#define UCM_REG_UCM_CFC_IFEN 0xe0044
2986/* [RW 11] Interrupt mask register #0 read/write */
2987#define UCM_REG_UCM_INT_MASK 0xe01d4
2988/* [R 11] Interrupt register #0 read */
2989#define UCM_REG_UCM_INT_STS 0xe01c8
2990/* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
2991 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
2992 Is used to determine the number of the AG context REG-pairs written back;
2993 when the Reg1WbFlg isn't set. */
2994#define UCM_REG_UCM_REG0_SZ 0xe00dc
2995/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
2996 disregarded; valid is deasserted; all other signals are treated as usual;
2997 if 1 - normal activity. */
2998#define UCM_REG_UCM_STORM0_IFEN 0xe0004
2999/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
3000 disregarded; valid is deasserted; all other signals are treated as usual;
3001 if 1 - normal activity. */
3002#define UCM_REG_UCM_STORM1_IFEN 0xe0008
3003/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
3004 disregarded; acknowledge output is deasserted; all other signals are
3005 treated as usual; if 1 - normal activity. */
3006#define UCM_REG_UCM_TM_IFEN 0xe0020
3007/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
3008 disregarded; valid is deasserted; all other signals are treated as usual;
3009 if 1 - normal activity. */
3010#define UCM_REG_UCM_UQM_IFEN 0xe000c
3011/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
3012#define UCM_REG_UCM_UQM_USE_Q 0xe00d8
3013/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
3014 the initial credit value; read returns the current value of the credit
3015 counter. Must be initialized to 32 at start-up. */
3016#define UCM_REG_UQM_INIT_CRD 0xe0220
3017/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
3018 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3019 prioritised); 2 stands for weight 2; tc. */
3020#define UCM_REG_UQM_P_WEIGHT 0xe00cc
3021/* [RW 28] The CM header value for QM request (primary). */
3022#define UCM_REG_UQM_UCM_HDR_P 0xe0094
3023/* [RW 28] The CM header value for QM request (secondary). */
3024#define UCM_REG_UQM_UCM_HDR_S 0xe0098
3025/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
3026 acknowledge output is deasserted; all other signals are treated as usual;
3027 if 1 - normal activity. */
3028#define UCM_REG_UQM_UCM_IFEN 0xe0014
3029/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
3030 acknowledge output is deasserted; all other signals are treated as usual;
3031 if 1 - normal activity. */
3032#define UCM_REG_USDM_IFEN 0xe0018
3033/* [RC 1] Set when the message length mismatch (relative to last indication)
3034 at the SDM interface is detected. */
3035#define UCM_REG_USDM_LENGTH_MIS 0xe0158
3036/* [RW 1] Input xsem Interface enable. If 0 - the valid input is
3037 disregarded; acknowledge output is deasserted; all other signals are
3038 treated as usual; if 1 - normal activity. */
3039#define UCM_REG_XSEM_IFEN 0xe002c
3040/* [RC 1] Set when the message length mismatch (relative to last indication)
3041 at the xsem interface isdetected. */
3042#define UCM_REG_XSEM_LENGTH_MIS 0xe0164
3043/* [RW 20] Indirect access to the descriptor table of the XX protection
3044 mechanism. The fields are:[5:0] - message length; 14:6] - message
3045 pointer; 19:15] - next pointer. */
3046#define UCM_REG_XX_DESCR_TABLE 0xe0280
3047/* [R 6] Use to read the XX protection Free counter. */
3048#define UCM_REG_XX_FREE 0xe016c
3049/* [RW 6] Initial value for the credit counter; responsible for fulfilling
3050 of the Input Stage XX protection buffer by the XX protection pending
3051 messages. Write writes the initial credit value; read returns the current
3052 value of the credit counter. Must be initialized to 12 at start-up. */
3053#define UCM_REG_XX_INIT_CRD 0xe0224
3054/* [RW 6] The maximum number of pending messages; which may be stored in XX
3055 protection. ~ucm_registers_xx_free.xx_free read on read. */
3056#define UCM_REG_XX_MSG_NUM 0xe0228
3057/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3058#define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
3059/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
3060 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
3061 header pointer. */
3062#define UCM_REG_XX_TABLE 0xe0300
3063/* [RW 8] The event id for aggregated interrupt 0 */
3064#define USDM_REG_AGG_INT_EVENT_0 0xc4038
3065#define USDM_REG_AGG_INT_EVENT_1 0xc403c
3066#define USDM_REG_AGG_INT_EVENT_10 0xc4060
3067#define USDM_REG_AGG_INT_EVENT_11 0xc4064
3068#define USDM_REG_AGG_INT_EVENT_12 0xc4068
3069#define USDM_REG_AGG_INT_EVENT_13 0xc406c
3070#define USDM_REG_AGG_INT_EVENT_14 0xc4070
3071#define USDM_REG_AGG_INT_EVENT_15 0xc4074
3072#define USDM_REG_AGG_INT_EVENT_16 0xc4078
3073#define USDM_REG_AGG_INT_EVENT_17 0xc407c
3074#define USDM_REG_AGG_INT_EVENT_18 0xc4080
3075#define USDM_REG_AGG_INT_EVENT_19 0xc4084
3076/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
3077 or auto-mask-mode (1) */
3078#define USDM_REG_AGG_INT_MODE_0 0xc41b8
3079#define USDM_REG_AGG_INT_MODE_1 0xc41bc
3080#define USDM_REG_AGG_INT_MODE_10 0xc41e0
3081#define USDM_REG_AGG_INT_MODE_11 0xc41e4
3082#define USDM_REG_AGG_INT_MODE_12 0xc41e8
3083#define USDM_REG_AGG_INT_MODE_13 0xc41ec
3084#define USDM_REG_AGG_INT_MODE_14 0xc41f0
3085#define USDM_REG_AGG_INT_MODE_15 0xc41f4
3086#define USDM_REG_AGG_INT_MODE_16 0xc41f8
3087#define USDM_REG_AGG_INT_MODE_17 0xc41fc
3088#define USDM_REG_AGG_INT_MODE_18 0xc4200
3089#define USDM_REG_AGG_INT_MODE_19 0xc4204
3090/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
3091#define USDM_REG_CFC_RSP_START_ADDR 0xc4008
3092/* [RW 16] The maximum value of the competion counter #0 */
3093#define USDM_REG_CMP_COUNTER_MAX0 0xc401c
3094/* [RW 16] The maximum value of the competion counter #1 */
3095#define USDM_REG_CMP_COUNTER_MAX1 0xc4020
3096/* [RW 16] The maximum value of the competion counter #2 */
3097#define USDM_REG_CMP_COUNTER_MAX2 0xc4024
3098/* [RW 16] The maximum value of the competion counter #3 */
3099#define USDM_REG_CMP_COUNTER_MAX3 0xc4028
3100/* [RW 13] The start address in the internal RAM for the completion
3101 counters. */
3102#define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
3103#define USDM_REG_ENABLE_IN1 0xc4238
3104#define USDM_REG_ENABLE_IN2 0xc423c
3105#define USDM_REG_ENABLE_OUT1 0xc4240
3106#define USDM_REG_ENABLE_OUT2 0xc4244
3107/* [RW 4] The initial number of messages that can be sent to the pxp control
3108 interface without receiving any ACK. */
3109#define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
3110/* [ST 32] The number of ACK after placement messages received */
3111#define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
3112/* [ST 32] The number of packet end messages received from the parser */
3113#define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
3114/* [ST 32] The number of requests received from the pxp async if */
3115#define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
3116/* [ST 32] The number of commands received in queue 0 */
3117#define USDM_REG_NUM_OF_Q0_CMD 0xc4248
3118/* [ST 32] The number of commands received in queue 10 */
3119#define USDM_REG_NUM_OF_Q10_CMD 0xc4270
3120/* [ST 32] The number of commands received in queue 11 */
3121#define USDM_REG_NUM_OF_Q11_CMD 0xc4274
3122/* [ST 32] The number of commands received in queue 1 */
3123#define USDM_REG_NUM_OF_Q1_CMD 0xc424c
3124/* [ST 32] The number of commands received in queue 2 */
3125#define USDM_REG_NUM_OF_Q2_CMD 0xc4250
3126/* [ST 32] The number of commands received in queue 3 */
3127#define USDM_REG_NUM_OF_Q3_CMD 0xc4254
3128/* [ST 32] The number of commands received in queue 4 */
3129#define USDM_REG_NUM_OF_Q4_CMD 0xc4258
3130/* [ST 32] The number of commands received in queue 5 */
3131#define USDM_REG_NUM_OF_Q5_CMD 0xc425c
3132/* [ST 32] The number of commands received in queue 6 */
3133#define USDM_REG_NUM_OF_Q6_CMD 0xc4260
3134/* [ST 32] The number of commands received in queue 7 */
3135#define USDM_REG_NUM_OF_Q7_CMD 0xc4264
3136/* [ST 32] The number of commands received in queue 8 */
3137#define USDM_REG_NUM_OF_Q8_CMD 0xc4268
3138/* [ST 32] The number of commands received in queue 9 */
3139#define USDM_REG_NUM_OF_Q9_CMD 0xc426c
3140/* [RW 13] The start address in the internal RAM for the packet end message */
3141#define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
3142/* [RW 13] The start address in the internal RAM for queue counters */
3143#define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
3144/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
3145#define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
3146/* [R 1] parser fifo empty in sdm_sync block */
3147#define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
3148/* [R 1] parser serial fifo empty in sdm_sync block */
3149#define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
3150/* [RW 32] Tick for timer counter. Applicable only when
3151 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
3152#define USDM_REG_TIMER_TICK 0xc4000
3153/* [RW 32] Interrupt mask register #0 read/write */
3154#define USDM_REG_USDM_INT_MASK_0 0xc42a0
3155#define USDM_REG_USDM_INT_MASK_1 0xc42b0
3156/* [RW 11] Parity mask register #0 read/write */
3157#define USDM_REG_USDM_PRTY_MASK 0xc42c0
3158/* [RW 5] The number of time_slots in the arbitration cycle */
3159#define USEM_REG_ARB_CYCLE_SIZE 0x300034
3160/* [RW 3] The source that is associated with arbitration element 0. Source
3161 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3162 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
3163#define USEM_REG_ARB_ELEMENT0 0x300020
3164/* [RW 3] The source that is associated with arbitration element 1. Source
3165 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3166 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3167 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
3168#define USEM_REG_ARB_ELEMENT1 0x300024
3169/* [RW 3] The source that is associated with arbitration element 2. Source
3170 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3171 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3172 Could not be equal to register ~usem_registers_arb_element0.arb_element0
3173 and ~usem_registers_arb_element1.arb_element1 */
3174#define USEM_REG_ARB_ELEMENT2 0x300028
3175/* [RW 3] The source that is associated with arbitration element 3. Source
3176 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3177 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
3178 not be equal to register ~usem_registers_arb_element0.arb_element0 and
3179 ~usem_registers_arb_element1.arb_element1 and
3180 ~usem_registers_arb_element2.arb_element2 */
3181#define USEM_REG_ARB_ELEMENT3 0x30002c
3182/* [RW 3] The source that is associated with arbitration element 4. Source
3183 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3184 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3185 Could not be equal to register ~usem_registers_arb_element0.arb_element0
3186 and ~usem_registers_arb_element1.arb_element1 and
3187 ~usem_registers_arb_element2.arb_element2 and
3188 ~usem_registers_arb_element3.arb_element3 */
3189#define USEM_REG_ARB_ELEMENT4 0x300030
3190#define USEM_REG_ENABLE_IN 0x3000a4
3191#define USEM_REG_ENABLE_OUT 0x3000a8
3192/* [RW 32] This address space contains all registers and memories that are
3193 placed in SEM_FAST block. The SEM_FAST registers are described in
3194 appendix B. In order to access the SEM_FAST registers... the base address
3195 USEM_REGISTERS_FAST_MEMORY (Offset: 0x320000) should be added to each
3196 SEM_FAST register offset. */
3197#define USEM_REG_FAST_MEMORY 0x320000
3198/* [RW 1] Disables input messages from FIC0 May be updated during run_time
3199 by the microcode */
3200#define USEM_REG_FIC0_DISABLE 0x300224
3201/* [RW 1] Disables input messages from FIC1 May be updated during run_time
3202 by the microcode */
3203#define USEM_REG_FIC1_DISABLE 0x300234
3204/* [RW 15] Interrupt table Read and write access to it is not possible in
3205 the middle of the work */
3206#define USEM_REG_INT_TABLE 0x300400
3207/* [ST 24] Statistics register. The number of messages that entered through
3208 FIC0 */
3209#define USEM_REG_MSG_NUM_FIC0 0x300000
3210/* [ST 24] Statistics register. The number of messages that entered through
3211 FIC1 */
3212#define USEM_REG_MSG_NUM_FIC1 0x300004
3213/* [ST 24] Statistics register. The number of messages that were sent to
3214 FOC0 */
3215#define USEM_REG_MSG_NUM_FOC0 0x300008
3216/* [ST 24] Statistics register. The number of messages that were sent to
3217 FOC1 */
3218#define USEM_REG_MSG_NUM_FOC1 0x30000c
3219/* [ST 24] Statistics register. The number of messages that were sent to
3220 FOC2 */
3221#define USEM_REG_MSG_NUM_FOC2 0x300010
3222/* [ST 24] Statistics register. The number of messages that were sent to
3223 FOC3 */
3224#define USEM_REG_MSG_NUM_FOC3 0x300014
3225/* [RW 1] Disables input messages from the passive buffer May be updated
3226 during run_time by the microcode */
3227#define USEM_REG_PAS_DISABLE 0x30024c
3228/* [WB 128] Debug only. Passive buffer memory */
3229#define USEM_REG_PASSIVE_BUFFER 0x302000
3230/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
3231#define USEM_REG_PRAM 0x340000
3232/* [R 16] Valid sleeping threads indication have bit per thread */
3233#define USEM_REG_SLEEP_THREADS_VALID 0x30026c
3234/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
3235#define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
3236/* [RW 16] List of free threads . There is a bit per thread. */
3237#define USEM_REG_THREADS_LIST 0x3002e4
3238/* [RW 3] The arbitration scheme of time_slot 0 */
3239#define USEM_REG_TS_0_AS 0x300038
3240/* [RW 3] The arbitration scheme of time_slot 10 */
3241#define USEM_REG_TS_10_AS 0x300060
3242/* [RW 3] The arbitration scheme of time_slot 11 */
3243#define USEM_REG_TS_11_AS 0x300064
3244/* [RW 3] The arbitration scheme of time_slot 12 */
3245#define USEM_REG_TS_12_AS 0x300068
3246/* [RW 3] The arbitration scheme of time_slot 13 */
3247#define USEM_REG_TS_13_AS 0x30006c
3248/* [RW 3] The arbitration scheme of time_slot 14 */
3249#define USEM_REG_TS_14_AS 0x300070
3250/* [RW 3] The arbitration scheme of time_slot 15 */
3251#define USEM_REG_TS_15_AS 0x300074
3252/* [RW 3] The arbitration scheme of time_slot 16 */
3253#define USEM_REG_TS_16_AS 0x300078
3254/* [RW 3] The arbitration scheme of time_slot 17 */
3255#define USEM_REG_TS_17_AS 0x30007c
3256/* [RW 3] The arbitration scheme of time_slot 18 */
3257#define USEM_REG_TS_18_AS 0x300080
3258/* [RW 3] The arbitration scheme of time_slot 1 */
3259#define USEM_REG_TS_1_AS 0x30003c
3260/* [RW 3] The arbitration scheme of time_slot 2 */
3261#define USEM_REG_TS_2_AS 0x300040
3262/* [RW 3] The arbitration scheme of time_slot 3 */
3263#define USEM_REG_TS_3_AS 0x300044
3264/* [RW 3] The arbitration scheme of time_slot 4 */
3265#define USEM_REG_TS_4_AS 0x300048
3266/* [RW 3] The arbitration scheme of time_slot 5 */
3267#define USEM_REG_TS_5_AS 0x30004c
3268/* [RW 3] The arbitration scheme of time_slot 6 */
3269#define USEM_REG_TS_6_AS 0x300050
3270/* [RW 3] The arbitration scheme of time_slot 7 */
3271#define USEM_REG_TS_7_AS 0x300054
3272/* [RW 3] The arbitration scheme of time_slot 8 */
3273#define USEM_REG_TS_8_AS 0x300058
3274/* [RW 3] The arbitration scheme of time_slot 9 */
3275#define USEM_REG_TS_9_AS 0x30005c
3276/* [RW 32] Interrupt mask register #0 read/write */
3277#define USEM_REG_USEM_INT_MASK_0 0x300110
3278#define USEM_REG_USEM_INT_MASK_1 0x300120
3279/* [RW 32] Parity mask register #0 read/write */
3280#define USEM_REG_USEM_PRTY_MASK_0 0x300130
3281#define USEM_REG_USEM_PRTY_MASK_1 0x300140
3282/* [RW 2] The queue index for registration on Aux1 counter flag. */
3283#define XCM_REG_AUX1_Q 0x20134
3284/* [RW 2] Per each decision rule the queue index to register to. */
3285#define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
3286/* [R 5] Used to read the XX protection CAM occupancy counter. */
3287#define XCM_REG_CAM_OCCUP 0x20244
3288/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
3289 disregarded; valid output is deasserted; all other signals are treated as
3290 usual; if 1 - normal activity. */
3291#define XCM_REG_CDU_AG_RD_IFEN 0x20044
3292/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
3293 are disregarded; all other signals are treated as usual; if 1 - normal
3294 activity. */
3295#define XCM_REG_CDU_AG_WR_IFEN 0x20040
3296/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
3297 disregarded; valid output is deasserted; all other signals are treated as
3298 usual; if 1 - normal activity. */
3299#define XCM_REG_CDU_SM_RD_IFEN 0x2004c
3300/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
3301 input is disregarded; all other signals are treated as usual; if 1 -
3302 normal activity. */
3303#define XCM_REG_CDU_SM_WR_IFEN 0x20048
3304/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
3305 the initial credit value; read returns the current value of the credit
3306 counter. Must be initialized to 1 at start-up. */
3307#define XCM_REG_CFC_INIT_CRD 0x20404
3308/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
3309 weight 8 (the most prioritised); 1 stands for weight 1(least
3310 prioritised); 2 stands for weight 2; tc. */
3311#define XCM_REG_CP_WEIGHT 0x200dc
3312/* [RW 1] Input csem Interface enable. If 0 - the valid input is
3313 disregarded; acknowledge output is deasserted; all other signals are
3314 treated as usual; if 1 - normal activity. */
3315#define XCM_REG_CSEM_IFEN 0x20028
3316/* [RC 1] Set at message length mismatch (relative to last indication) at
3317 the csem interface. */
3318#define XCM_REG_CSEM_LENGTH_MIS 0x20228
3319/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
3320 weight 8 (the most prioritised); 1 stands for weight 1(least
3321 prioritised); 2 stands for weight 2; tc. */
3322#define XCM_REG_CSEM_WEIGHT 0x200c4
3323/* [RW 1] Input dorq Interface enable. If 0 - the valid input is
3324 disregarded; acknowledge output is deasserted; all other signals are
3325 treated as usual; if 1 - normal activity. */
3326#define XCM_REG_DORQ_IFEN 0x20030
3327/* [RC 1] Set at message length mismatch (relative to last indication) at
3328 the dorq interface. */
3329#define XCM_REG_DORQ_LENGTH_MIS 0x20230
3330/* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
3331#define XCM_REG_ERR_EVNT_ID 0x200b0
3332/* [RW 28] The CM erroneous header for QM and Timers formatting. */
3333#define XCM_REG_ERR_XCM_HDR 0x200ac
3334/* [RW 8] The Event ID for Timers expiration. */
3335#define XCM_REG_EXPR_EVNT_ID 0x200b4
3336/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
3337 writes the initial credit value; read returns the current value of the
3338 credit counter. Must be initialized to 64 at start-up. */
3339#define XCM_REG_FIC0_INIT_CRD 0x2040c
3340/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
3341 writes the initial credit value; read returns the current value of the
3342 credit counter. Must be initialized to 64 at start-up. */
3343#define XCM_REG_FIC1_INIT_CRD 0x20410
3344/* [RW 8] The maximum delayed ACK counter value.Must be at least 2. Per port
3345 value. */
3346#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
3347#define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
3348/* [RW 28] The delayed ACK timeout in ticks. Per port value. */
3349#define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
3350#define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
3351/* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
3352 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
3353 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
3354 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
3355#define XCM_REG_GR_ARB_TYPE 0x2020c
3356/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
3357 highest priority is 3. It is supposed that the Channel group is the
3358 compliment of the other 3 groups. */
3359#define XCM_REG_GR_LD0_PR 0x20214
3360/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
3361 highest priority is 3. It is supposed that the Channel group is the
3362 compliment of the other 3 groups. */
3363#define XCM_REG_GR_LD1_PR 0x20218
3364/* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
3365 disregarded; acknowledge output is deasserted; all other signals are
3366 treated as usual; if 1 - normal activity. */
3367#define XCM_REG_NIG0_IFEN 0x20038
3368/* [RC 1] Set at message length mismatch (relative to last indication) at
3369 the nig0 interface. */
3370#define XCM_REG_NIG0_LENGTH_MIS 0x20238
3371/* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
3372 disregarded; acknowledge output is deasserted; all other signals are
3373 treated as usual; if 1 - normal activity. */
3374#define XCM_REG_NIG1_IFEN 0x2003c
3375/* [RC 1] Set at message length mismatch (relative to last indication) at
3376 the nig1 interface. */
3377#define XCM_REG_NIG1_LENGTH_MIS 0x2023c
3378/* [RW 3] The weight of the input nig1 in the WRR mechanism. 0 stands for
3379 weight 8 (the most prioritised); 1 stands for weight 1(least
3380 prioritised); 2 stands for weight 2; tc. */
3381#define XCM_REG_NIG1_WEIGHT 0x200d8
3382/* [RW 5] The number of double REG-pairs; loaded from the STORM context and
3383 sent to STORM; for a specific connection type. The double REG-pairs are
3384 used in order to align to STORM context row size of 128 bits. The offset
3385 of these data in the STORM context is always 0. Index _i stands for the
3386 connection type (one of 16). */
3387#define XCM_REG_N_SM_CTX_LD_0 0x20060
3388#define XCM_REG_N_SM_CTX_LD_1 0x20064
3389#define XCM_REG_N_SM_CTX_LD_10 0x20088
3390#define XCM_REG_N_SM_CTX_LD_11 0x2008c
3391#define XCM_REG_N_SM_CTX_LD_12 0x20090
3392#define XCM_REG_N_SM_CTX_LD_13 0x20094
3393#define XCM_REG_N_SM_CTX_LD_14 0x20098
3394#define XCM_REG_N_SM_CTX_LD_15 0x2009c
3395#define XCM_REG_N_SM_CTX_LD_2 0x20068
3396#define XCM_REG_N_SM_CTX_LD_3 0x2006c
3397#define XCM_REG_N_SM_CTX_LD_4 0x20070
3398/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
3399 acknowledge output is deasserted; all other signals are treated as usual;
3400 if 1 - normal activity. */
3401#define XCM_REG_PBF_IFEN 0x20034
3402/* [RC 1] Set at message length mismatch (relative to last indication) at
3403 the pbf interface. */
3404#define XCM_REG_PBF_LENGTH_MIS 0x20234
3405/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
3406 weight 8 (the most prioritised); 1 stands for weight 1(least
3407 prioritised); 2 stands for weight 2; tc. */
3408#define XCM_REG_PBF_WEIGHT 0x200d0
3409/* [RW 8] The Event ID for Timers formatting in case of stop done. */
3410#define XCM_REG_STOP_EVNT_ID 0x200b8
3411/* [RC 1] Set at message length mismatch (relative to last indication) at
3412 the STORM interface. */
3413#define XCM_REG_STORM_LENGTH_MIS 0x2021c
3414/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
3415 weight 8 (the most prioritised); 1 stands for weight 1(least
3416 prioritised); 2 stands for weight 2; tc. */
3417#define XCM_REG_STORM_WEIGHT 0x200bc
3418/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
3419 disregarded; acknowledge output is deasserted; all other signals are
3420 treated as usual; if 1 - normal activity. */
3421#define XCM_REG_STORM_XCM_IFEN 0x20010
3422/* [RW 4] Timers output initial credit. Max credit available - 15.Write
3423 writes the initial credit value; read returns the current value of the
3424 credit counter. Must be initialized to 4 at start-up. */
3425#define XCM_REG_TM_INIT_CRD 0x2041c
3426/* [RW 28] The CM header for Timers expiration command. */
3427#define XCM_REG_TM_XCM_HDR 0x200a8
3428/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
3429 disregarded; acknowledge output is deasserted; all other signals are
3430 treated as usual; if 1 - normal activity. */
3431#define XCM_REG_TM_XCM_IFEN 0x2001c
3432/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
3433 disregarded; acknowledge output is deasserted; all other signals are
3434 treated as usual; if 1 - normal activity. */
3435#define XCM_REG_TSEM_IFEN 0x20024
3436/* [RC 1] Set at message length mismatch (relative to last indication) at
3437 the tsem interface. */
3438#define XCM_REG_TSEM_LENGTH_MIS 0x20224
3439/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
3440 weight 8 (the most prioritised); 1 stands for weight 1(least
3441 prioritised); 2 stands for weight 2; tc. */
3442#define XCM_REG_TSEM_WEIGHT 0x200c0
3443/* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
3444#define XCM_REG_UNA_GT_NXT_Q 0x20120
3445/* [RW 1] Input usem Interface enable. If 0 - the valid input is
3446 disregarded; acknowledge output is deasserted; all other signals are
3447 treated as usual; if 1 - normal activity. */
3448#define XCM_REG_USEM_IFEN 0x2002c
3449/* [RC 1] Message length mismatch (relative to last indication) at the usem
3450 interface. */
3451#define XCM_REG_USEM_LENGTH_MIS 0x2022c
3452/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
3453 weight 8 (the most prioritised); 1 stands for weight 1(least
3454 prioritised); 2 stands for weight 2; tc. */
3455#define XCM_REG_USEM_WEIGHT 0x200c8
3456/* [RW 2] DA counter command; used in case of window update doorbell.The
3457 first index stands for the value DaEnable of that connection. The second
3458 index stands for port number. */
3459#define XCM_REG_WU_DA_CNT_CMD00 0x201d4
3460/* [RW 2] DA counter command; used in case of window update doorbell.The
3461 first index stands for the value DaEnable of that connection. The second
3462 index stands for port number. */
3463#define XCM_REG_WU_DA_CNT_CMD01 0x201d8
3464/* [RW 2] DA counter command; used in case of window update doorbell.The
3465 first index stands for the value DaEnable of that connection. The second
3466 index stands for port number. */
3467#define XCM_REG_WU_DA_CNT_CMD10 0x201dc
3468/* [RW 2] DA counter command; used in case of window update doorbell.The
3469 first index stands for the value DaEnable of that connection. The second
3470 index stands for port number. */
3471#define XCM_REG_WU_DA_CNT_CMD11 0x201e0
3472/* [RW 8] DA counter update value used in case of window update doorbell.The
3473 first index stands for the value DaEnable of that connection. The second
3474 index stands for port number. */
3475#define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
3476/* [RW 8] DA counter update value; used in case of window update
3477 doorbell.The first index stands for the value DaEnable of that
3478 connection. The second index stands for port number. */
3479#define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
3480/* [RW 8] DA counter update value; used in case of window update
3481 doorbell.The first index stands for the value DaEnable of that
3482 connection. The second index stands for port number. */
3483#define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
3484/* [RW 8] DA counter update value; used in case of window update
3485 doorbell.The first index stands for the value DaEnable of that
3486 connection. The second index stands for port number. */
3487#define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
3488/* [RW 1] DA timer command; used in case of window update doorbell.The first
3489 index stands for the value DaEnable of that connection. The second index
3490 stands for port number. */
3491#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
3492/* [RW 1] DA timer command; used in case of window update doorbell.The first
3493 index stands for the value DaEnable of that connection. The second index
3494 stands for port number. */
3495#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
3496/* [RW 1] DA timer command; used in case of window update doorbell.The first
3497 index stands for the value DaEnable of that connection. The second index
3498 stands for port number. */
3499#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
3500/* [RW 1] DA timer command; used in case of window update doorbell.The first
3501 index stands for the value DaEnable of that connection. The second index
3502 stands for port number. */
3503#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
3504/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
3505 acknowledge output is deasserted; all other signals are treated as usual;
3506 if 1 - normal activity. */
3507#define XCM_REG_XCM_CFC_IFEN 0x20050
3508/* [RW 14] Interrupt mask register #0 read/write */
3509#define XCM_REG_XCM_INT_MASK 0x202b4
3510/* [R 14] Interrupt register #0 read */
3511#define XCM_REG_XCM_INT_STS 0x202a8
3512/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
3513 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3514 Is used to determine the number of the AG context REG-pairs written back;
3515 when the Reg1WbFlg isn't set. */
3516#define XCM_REG_XCM_REG0_SZ 0x200f4
3517/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
3518 disregarded; valid is deasserted; all other signals are treated as usual;
3519 if 1 - normal activity. */
3520#define XCM_REG_XCM_STORM0_IFEN 0x20004
3521/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
3522 disregarded; valid is deasserted; all other signals are treated as usual;
3523 if 1 - normal activity. */
3524#define XCM_REG_XCM_STORM1_IFEN 0x20008
3525/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
3526 disregarded; acknowledge output is deasserted; all other signals are
3527 treated as usual; if 1 - normal activity. */
3528#define XCM_REG_XCM_TM_IFEN 0x20020
3529/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
3530 disregarded; valid is deasserted; all other signals are treated as usual;
3531 if 1 - normal activity. */
3532#define XCM_REG_XCM_XQM_IFEN 0x2000c
3533/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
3534#define XCM_REG_XCM_XQM_USE_Q 0x200f0
3535/* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
3536#define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
3537/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
3538 the initial credit value; read returns the current value of the credit
3539 counter. Must be initialized to 32 at start-up. */
3540#define XCM_REG_XQM_INIT_CRD 0x20420
3541/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
3542 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3543 prioritised); 2 stands for weight 2; tc. */
3544#define XCM_REG_XQM_P_WEIGHT 0x200e4
3545/* [RW 28] The CM header value for QM request (primary). */
3546#define XCM_REG_XQM_XCM_HDR_P 0x200a0
3547/* [RW 28] The CM header value for QM request (secondary). */
3548#define XCM_REG_XQM_XCM_HDR_S 0x200a4
3549/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
3550 acknowledge output is deasserted; all other signals are treated as usual;
3551 if 1 - normal activity. */
3552#define XCM_REG_XQM_XCM_IFEN 0x20014
3553/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
3554 acknowledge output is deasserted; all other signals are treated as usual;
3555 if 1 - normal activity. */
3556#define XCM_REG_XSDM_IFEN 0x20018
3557/* [RC 1] Set at message length mismatch (relative to last indication) at
3558 the SDM interface. */
3559#define XCM_REG_XSDM_LENGTH_MIS 0x20220
3560/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
3561 weight 8 (the most prioritised); 1 stands for weight 1(least
3562 prioritised); 2 stands for weight 2; tc. */
3563#define XCM_REG_XSDM_WEIGHT 0x200e0
3564/* [RW 17] Indirect access to the descriptor table of the XX protection
3565 mechanism. The fields are: [5:0] - message length; 11:6] - message
3566 pointer; 16:12] - next pointer. */
3567#define XCM_REG_XX_DESCR_TABLE 0x20480
3568/* [R 6] Used to read the XX protection Free counter. */
3569#define XCM_REG_XX_FREE 0x20240
3570/* [RW 6] Initial value for the credit counter; responsible for fulfilling
3571 of the Input Stage XX protection buffer by the XX protection pending
3572 messages. Max credit available - 3.Write writes the initial credit value;
3573 read returns the current value of the credit counter. Must be initialized
3574 to 2 at start-up. */
3575#define XCM_REG_XX_INIT_CRD 0x20424
3576/* [RW 6] The maximum number of pending messages; which may be stored in XX
3577 protection. ~xcm_registers_xx_free.xx_free read on read. */
3578#define XCM_REG_XX_MSG_NUM 0x20428
3579/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3580#define XCM_REG_XX_OVFL_EVNT_ID 0x20058
3581/* [RW 15] Indirect access to the XX table of the XX protection mechanism.
3582 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
3583 header pointer. */
3584#define XCM_REG_XX_TABLE 0x20500
3585/* [RW 8] The event id for aggregated interrupt 0 */
3586#define XSDM_REG_AGG_INT_EVENT_0 0x166038
3587#define XSDM_REG_AGG_INT_EVENT_1 0x16603c
3588#define XSDM_REG_AGG_INT_EVENT_10 0x166060
3589#define XSDM_REG_AGG_INT_EVENT_11 0x166064
3590#define XSDM_REG_AGG_INT_EVENT_12 0x166068
3591#define XSDM_REG_AGG_INT_EVENT_13 0x16606c
3592#define XSDM_REG_AGG_INT_EVENT_14 0x166070
3593#define XSDM_REG_AGG_INT_EVENT_15 0x166074
3594#define XSDM_REG_AGG_INT_EVENT_16 0x166078
3595#define XSDM_REG_AGG_INT_EVENT_17 0x16607c
3596#define XSDM_REG_AGG_INT_EVENT_18 0x166080
3597#define XSDM_REG_AGG_INT_EVENT_19 0x166084
3598#define XSDM_REG_AGG_INT_EVENT_2 0x166040
3599#define XSDM_REG_AGG_INT_EVENT_20 0x166088
3600#define XSDM_REG_AGG_INT_EVENT_21 0x16608c
3601#define XSDM_REG_AGG_INT_EVENT_22 0x166090
3602#define XSDM_REG_AGG_INT_EVENT_23 0x166094
3603#define XSDM_REG_AGG_INT_EVENT_24 0x166098
3604#define XSDM_REG_AGG_INT_EVENT_25 0x16609c
3605#define XSDM_REG_AGG_INT_EVENT_26 0x1660a0
3606#define XSDM_REG_AGG_INT_EVENT_27 0x1660a4
3607#define XSDM_REG_AGG_INT_EVENT_28 0x1660a8
3608#define XSDM_REG_AGG_INT_EVENT_29 0x1660ac
3609/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
3610 or auto-mask-mode (1) */
3611#define XSDM_REG_AGG_INT_MODE_0 0x1661b8
3612#define XSDM_REG_AGG_INT_MODE_1 0x1661bc
3613#define XSDM_REG_AGG_INT_MODE_10 0x1661e0
3614#define XSDM_REG_AGG_INT_MODE_11 0x1661e4
3615#define XSDM_REG_AGG_INT_MODE_12 0x1661e8
3616#define XSDM_REG_AGG_INT_MODE_13 0x1661ec
3617#define XSDM_REG_AGG_INT_MODE_14 0x1661f0
3618#define XSDM_REG_AGG_INT_MODE_15 0x1661f4
3619#define XSDM_REG_AGG_INT_MODE_16 0x1661f8
3620#define XSDM_REG_AGG_INT_MODE_17 0x1661fc
3621#define XSDM_REG_AGG_INT_MODE_18 0x166200
3622#define XSDM_REG_AGG_INT_MODE_19 0x166204
3623/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
3624#define XSDM_REG_CFC_RSP_START_ADDR 0x166008
3625/* [RW 16] The maximum value of the competion counter #0 */
3626#define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
3627/* [RW 16] The maximum value of the competion counter #1 */
3628#define XSDM_REG_CMP_COUNTER_MAX1 0x166020
3629/* [RW 16] The maximum value of the competion counter #2 */
3630#define XSDM_REG_CMP_COUNTER_MAX2 0x166024
3631/* [RW 16] The maximum value of the competion counter #3 */
3632#define XSDM_REG_CMP_COUNTER_MAX3 0x166028
3633/* [RW 13] The start address in the internal RAM for the completion
3634 counters. */
3635#define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
3636#define XSDM_REG_ENABLE_IN1 0x166238
3637#define XSDM_REG_ENABLE_IN2 0x16623c
3638#define XSDM_REG_ENABLE_OUT1 0x166240
3639#define XSDM_REG_ENABLE_OUT2 0x166244
3640/* [RW 4] The initial number of messages that can be sent to the pxp control
3641 interface without receiving any ACK. */
3642#define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
3643/* [ST 32] The number of ACK after placement messages received */
3644#define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
3645/* [ST 32] The number of packet end messages received from the parser */
3646#define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
3647/* [ST 32] The number of requests received from the pxp async if */
3648#define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
3649/* [ST 32] The number of commands received in queue 0 */
3650#define XSDM_REG_NUM_OF_Q0_CMD 0x166248
3651/* [ST 32] The number of commands received in queue 10 */
3652#define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
3653/* [ST 32] The number of commands received in queue 11 */
3654#define XSDM_REG_NUM_OF_Q11_CMD 0x166270
3655/* [ST 32] The number of commands received in queue 1 */
3656#define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
3657/* [ST 32] The number of commands received in queue 3 */
3658#define XSDM_REG_NUM_OF_Q3_CMD 0x166250
3659/* [ST 32] The number of commands received in queue 4 */
3660#define XSDM_REG_NUM_OF_Q4_CMD 0x166254
3661/* [ST 32] The number of commands received in queue 5 */
3662#define XSDM_REG_NUM_OF_Q5_CMD 0x166258
3663/* [ST 32] The number of commands received in queue 6 */
3664#define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
3665/* [ST 32] The number of commands received in queue 7 */
3666#define XSDM_REG_NUM_OF_Q7_CMD 0x166260
3667/* [ST 32] The number of commands received in queue 8 */
3668#define XSDM_REG_NUM_OF_Q8_CMD 0x166264
3669/* [ST 32] The number of commands received in queue 9 */
3670#define XSDM_REG_NUM_OF_Q9_CMD 0x166268
3671/* [RW 13] The start address in the internal RAM for queue counters */
3672#define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
3673/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
3674#define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
3675/* [R 1] parser fifo empty in sdm_sync block */
3676#define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
3677/* [R 1] parser serial fifo empty in sdm_sync block */
3678#define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
3679/* [RW 32] Tick for timer counter. Applicable only when
3680 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
3681#define XSDM_REG_TIMER_TICK 0x166000
3682/* [RW 32] Interrupt mask register #0 read/write */
3683#define XSDM_REG_XSDM_INT_MASK_0 0x16629c
3684#define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
3685/* [RW 11] Parity mask register #0 read/write */
3686#define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
3687/* [RW 5] The number of time_slots in the arbitration cycle */
3688#define XSEM_REG_ARB_CYCLE_SIZE 0x280034
3689/* [RW 3] The source that is associated with arbitration element 0. Source
3690 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3691 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
3692#define XSEM_REG_ARB_ELEMENT0 0x280020
3693/* [RW 3] The source that is associated with arbitration element 1. Source
3694 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3695 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3696 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
3697#define XSEM_REG_ARB_ELEMENT1 0x280024
3698/* [RW 3] The source that is associated with arbitration element 2. Source
3699 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3700 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3701 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
3702 and ~xsem_registers_arb_element1.arb_element1 */
3703#define XSEM_REG_ARB_ELEMENT2 0x280028
3704/* [RW 3] The source that is associated with arbitration element 3. Source
3705 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3706 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
3707 not be equal to register ~xsem_registers_arb_element0.arb_element0 and
3708 ~xsem_registers_arb_element1.arb_element1 and
3709 ~xsem_registers_arb_element2.arb_element2 */
3710#define XSEM_REG_ARB_ELEMENT3 0x28002c
3711/* [RW 3] The source that is associated with arbitration element 4. Source
3712 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3713 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3714 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
3715 and ~xsem_registers_arb_element1.arb_element1 and
3716 ~xsem_registers_arb_element2.arb_element2 and
3717 ~xsem_registers_arb_element3.arb_element3 */
3718#define XSEM_REG_ARB_ELEMENT4 0x280030
3719#define XSEM_REG_ENABLE_IN 0x2800a4
3720#define XSEM_REG_ENABLE_OUT 0x2800a8
3721/* [RW 32] This address space contains all registers and memories that are
3722 placed in SEM_FAST block. The SEM_FAST registers are described in
3723 appendix B. In order to access the SEM_FAST registers the base address
3724 XSEM_REGISTERS_FAST_MEMORY (Offset: 0x2a0000) should be added to each
3725 SEM_FAST register offset. */
3726#define XSEM_REG_FAST_MEMORY 0x2a0000
3727/* [RW 1] Disables input messages from FIC0 May be updated during run_time
3728 by the microcode */
3729#define XSEM_REG_FIC0_DISABLE 0x280224
3730/* [RW 1] Disables input messages from FIC1 May be updated during run_time
3731 by the microcode */
3732#define XSEM_REG_FIC1_DISABLE 0x280234
3733/* [RW 15] Interrupt table Read and write access to it is not possible in
3734 the middle of the work */
3735#define XSEM_REG_INT_TABLE 0x280400
3736/* [ST 24] Statistics register. The number of messages that entered through
3737 FIC0 */
3738#define XSEM_REG_MSG_NUM_FIC0 0x280000
3739/* [ST 24] Statistics register. The number of messages that entered through
3740 FIC1 */
3741#define XSEM_REG_MSG_NUM_FIC1 0x280004
3742/* [ST 24] Statistics register. The number of messages that were sent to
3743 FOC0 */
3744#define XSEM_REG_MSG_NUM_FOC0 0x280008
3745/* [ST 24] Statistics register. The number of messages that were sent to
3746 FOC1 */
3747#define XSEM_REG_MSG_NUM_FOC1 0x28000c
3748/* [ST 24] Statistics register. The number of messages that were sent to
3749 FOC2 */
3750#define XSEM_REG_MSG_NUM_FOC2 0x280010
3751/* [ST 24] Statistics register. The number of messages that were sent to
3752 FOC3 */
3753#define XSEM_REG_MSG_NUM_FOC3 0x280014
3754/* [RW 1] Disables input messages from the passive buffer May be updated
3755 during run_time by the microcode */
3756#define XSEM_REG_PAS_DISABLE 0x28024c
3757/* [WB 128] Debug only. Passive buffer memory */
3758#define XSEM_REG_PASSIVE_BUFFER 0x282000
3759/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
3760#define XSEM_REG_PRAM 0x2c0000
3761/* [R 16] Valid sleeping threads indication have bit per thread */
3762#define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
3763/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
3764#define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
3765/* [RW 16] List of free threads . There is a bit per thread. */
3766#define XSEM_REG_THREADS_LIST 0x2802e4
3767/* [RW 3] The arbitration scheme of time_slot 0 */
3768#define XSEM_REG_TS_0_AS 0x280038
3769/* [RW 3] The arbitration scheme of time_slot 10 */
3770#define XSEM_REG_TS_10_AS 0x280060
3771/* [RW 3] The arbitration scheme of time_slot 11 */
3772#define XSEM_REG_TS_11_AS 0x280064
3773/* [RW 3] The arbitration scheme of time_slot 12 */
3774#define XSEM_REG_TS_12_AS 0x280068
3775/* [RW 3] The arbitration scheme of time_slot 13 */
3776#define XSEM_REG_TS_13_AS 0x28006c
3777/* [RW 3] The arbitration scheme of time_slot 14 */
3778#define XSEM_REG_TS_14_AS 0x280070
3779/* [RW 3] The arbitration scheme of time_slot 15 */
3780#define XSEM_REG_TS_15_AS 0x280074
3781/* [RW 3] The arbitration scheme of time_slot 16 */
3782#define XSEM_REG_TS_16_AS 0x280078
3783/* [RW 3] The arbitration scheme of time_slot 17 */
3784#define XSEM_REG_TS_17_AS 0x28007c
3785/* [RW 3] The arbitration scheme of time_slot 18 */
3786#define XSEM_REG_TS_18_AS 0x280080
3787/* [RW 3] The arbitration scheme of time_slot 1 */
3788#define XSEM_REG_TS_1_AS 0x28003c
3789/* [RW 3] The arbitration scheme of time_slot 2 */
3790#define XSEM_REG_TS_2_AS 0x280040
3791/* [RW 3] The arbitration scheme of time_slot 3 */
3792#define XSEM_REG_TS_3_AS 0x280044
3793/* [RW 3] The arbitration scheme of time_slot 4 */
3794#define XSEM_REG_TS_4_AS 0x280048
3795/* [RW 3] The arbitration scheme of time_slot 5 */
3796#define XSEM_REG_TS_5_AS 0x28004c
3797/* [RW 3] The arbitration scheme of time_slot 6 */
3798#define XSEM_REG_TS_6_AS 0x280050
3799/* [RW 3] The arbitration scheme of time_slot 7 */
3800#define XSEM_REG_TS_7_AS 0x280054
3801/* [RW 3] The arbitration scheme of time_slot 8 */
3802#define XSEM_REG_TS_8_AS 0x280058
3803/* [RW 3] The arbitration scheme of time_slot 9 */
3804#define XSEM_REG_TS_9_AS 0x28005c
3805/* [RW 32] Interrupt mask register #0 read/write */
3806#define XSEM_REG_XSEM_INT_MASK_0 0x280110
3807#define XSEM_REG_XSEM_INT_MASK_1 0x280120
3808/* [RW 32] Parity mask register #0 read/write */
3809#define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
3810#define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
3811#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
3812#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
3813#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
3814#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
3815#define MCPR_NVM_COMMAND_DOIT (1L<<4)
3816#define MCPR_NVM_COMMAND_DONE (1L<<3)
3817#define MCPR_NVM_COMMAND_FIRST (1L<<7)
3818#define MCPR_NVM_COMMAND_LAST (1L<<8)
3819#define MCPR_NVM_COMMAND_WR (1L<<5)
3820#define MCPR_NVM_COMMAND_WREN (1L<<16)
3821#define MCPR_NVM_COMMAND_WREN_BITSHIFT 16
3822#define MCPR_NVM_COMMAND_WRDI (1L<<17)
3823#define MCPR_NVM_COMMAND_WRDI_BITSHIFT 17
3824#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
3825#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
3826#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
3827#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
3828#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
3829#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
3830#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
3831#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
3832#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
3833#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
3834#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
3835#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
3836#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
3837#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
3838#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
3839#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
3840#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
3841#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
3842#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
3843#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
3844#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
3845#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
3846#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
3847#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
3848#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
3849#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
3850#define EMAC_MODE_25G_MODE (1L<<5)
3851#define EMAC_MODE_ACPI_RCVD (1L<<20)
3852#define EMAC_MODE_HALF_DUPLEX (1L<<1)
3853#define EMAC_MODE_MPKT (1L<<18)
3854#define EMAC_MODE_MPKT_RCVD (1L<<19)
3855#define EMAC_MODE_PORT_GMII (2L<<2)
3856#define EMAC_MODE_PORT_MII (1L<<2)
3857#define EMAC_MODE_PORT_MII_10M (3L<<2)
3858#define EMAC_MODE_RESET (1L<<0)
3859#define EMAC_REG_EMAC_MAC_MATCH 0x10
3860#define EMAC_REG_EMAC_MDIO_COMM 0xac
3861#define EMAC_REG_EMAC_MDIO_MODE 0xb4
3862#define EMAC_REG_EMAC_MODE 0x0
3863#define EMAC_REG_EMAC_RX_MODE 0xc8
3864#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
3865#define EMAC_REG_EMAC_RX_STAT_AC 0x180
3866#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
3867#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
3868#define EMAC_REG_EMAC_TX_MODE 0xbc
3869#define EMAC_REG_EMAC_TX_STAT_AC 0x280
3870#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
3871#define EMAC_RX_MODE_FLOW_EN (1L<<2)
3872#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
3873#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
3874#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
3875#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
3876#define EMAC_TX_MODE_RESET (1L<<0)
3877#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
3878#define MISC_REGISTERS_RESET_REG_1_SET 0x584
3879#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
3880#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
3881#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
3882#define MISC_REGISTERS_RESET_REG_2_SET 0x594
3883#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
3884#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
3885#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
3886#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
3887#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
3888#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
3889#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
3890#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
3891#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
3892#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
3893#define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
3894#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18)
3895#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31)
3896#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9)
3897#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1<<8)
3898#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1<<7)
3899#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1<<6)
3900#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1<<29)
3901#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1<<28)
3902#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1<<1)
3903#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1<<0)
3904#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1<<18)
3905#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11)
3906#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13)
3907#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12)
3908#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12)
3909#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15)
3910#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14)
3911#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1<<20)
3912#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1<<0)
3913#define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1<<31)
3914#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3)
3915#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1<<2)
3916#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1<<5)
3917#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1<<4)
3918#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3)
3919#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2)
3920#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22)
3921#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27)
3922#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5)
3923#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25)
3924#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1<<24)
3925#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1<<29)
3926#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1<<28)
3927#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1<<23)
3928#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1<<27)
3929#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1<<26)
3930#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1<<21)
3931#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1<<20)
3932#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1<<25)
3933#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1<<24)
3934#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1<<16)
3935#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1<<9)
3936#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1<<7)
3937#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1<<6)
3938#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1<<11)
3939#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10)
3940#define RESERVED_GENERAL_ATTENTION_BIT_0 0
3941
3942#define EVEREST_GEN_ATTN_IN_USE_MASK 0x3e0
3943#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
3944
3945#define RESERVED_GENERAL_ATTENTION_BIT_6 6
3946#define RESERVED_GENERAL_ATTENTION_BIT_7 7
3947#define RESERVED_GENERAL_ATTENTION_BIT_8 8
3948#define RESERVED_GENERAL_ATTENTION_BIT_9 9
3949#define RESERVED_GENERAL_ATTENTION_BIT_10 10
3950#define RESERVED_GENERAL_ATTENTION_BIT_11 11
3951#define RESERVED_GENERAL_ATTENTION_BIT_12 12
3952#define RESERVED_GENERAL_ATTENTION_BIT_13 13
3953#define RESERVED_GENERAL_ATTENTION_BIT_14 14
3954#define RESERVED_GENERAL_ATTENTION_BIT_15 15
3955#define RESERVED_GENERAL_ATTENTION_BIT_16 16
3956#define RESERVED_GENERAL_ATTENTION_BIT_17 17
3957#define RESERVED_GENERAL_ATTENTION_BIT_18 18
3958#define RESERVED_GENERAL_ATTENTION_BIT_19 19
3959#define RESERVED_GENERAL_ATTENTION_BIT_20 20
3960#define RESERVED_GENERAL_ATTENTION_BIT_21 21
3961
3962/* storm asserts attention bits */
3963#define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
3964#define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
3965#define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
3966#define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
3967
3968/* mcp error attention bit */
3969#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
3970
3971#define LATCHED_ATTN_RBCR 23
3972#define LATCHED_ATTN_RBCT 24
3973#define LATCHED_ATTN_RBCN 25
3974#define LATCHED_ATTN_RBCU 26
3975#define LATCHED_ATTN_RBCP 27
3976#define LATCHED_ATTN_TIMEOUT_GRC 28
3977#define LATCHED_ATTN_RSVD_GRC 29
3978#define LATCHED_ATTN_ROM_PARITY_MCP 30
3979#define LATCHED_ATTN_UM_RX_PARITY_MCP 31
3980#define LATCHED_ATTN_UM_TX_PARITY_MCP 32
3981#define LATCHED_ATTN_SCPAD_PARITY_MCP 33
3982
3983#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
3984#define GENERAL_ATTEN_OFFSET(atten_name) (1 << ((94 + atten_name) % 32))
3985/*
3986 * This file defines GRC base address for every block.
3987 * This file is included by chipsim, asm microcode and cpp microcode.
3988 * These values are used in Design.xml on regBase attribute
3989 * Use the base with the generated offsets of specific registers.
3990 */
3991
3992#define GRCBASE_PXPCS 0x000000
3993#define GRCBASE_PCICONFIG 0x002000
3994#define GRCBASE_PCIREG 0x002400
3995#define GRCBASE_EMAC0 0x008000
3996#define GRCBASE_EMAC1 0x008400
3997#define GRCBASE_DBU 0x008800
3998#define GRCBASE_MISC 0x00A000
3999#define GRCBASE_DBG 0x00C000
4000#define GRCBASE_NIG 0x010000
4001#define GRCBASE_XCM 0x020000
4002#define GRCBASE_PRS 0x040000
4003#define GRCBASE_SRCH 0x040400
4004#define GRCBASE_TSDM 0x042000
4005#define GRCBASE_TCM 0x050000
4006#define GRCBASE_BRB1 0x060000
4007#define GRCBASE_MCP 0x080000
4008#define GRCBASE_UPB 0x0C1000
4009#define GRCBASE_CSDM 0x0C2000
4010#define GRCBASE_USDM 0x0C4000
4011#define GRCBASE_CCM 0x0D0000
4012#define GRCBASE_UCM 0x0E0000
4013#define GRCBASE_CDU 0x101000
4014#define GRCBASE_DMAE 0x102000
4015#define GRCBASE_PXP 0x103000
4016#define GRCBASE_CFC 0x104000
4017#define GRCBASE_HC 0x108000
4018#define GRCBASE_PXP2 0x120000
4019#define GRCBASE_PBF 0x140000
4020#define GRCBASE_XPB 0x161000
4021#define GRCBASE_TIMERS 0x164000
4022#define GRCBASE_XSDM 0x166000
4023#define GRCBASE_QM 0x168000
4024#define GRCBASE_DQ 0x170000
4025#define GRCBASE_TSEM 0x180000
4026#define GRCBASE_CSEM 0x200000
4027#define GRCBASE_XSEM 0x280000
4028#define GRCBASE_USEM 0x300000
4029#define GRCBASE_MISC_AEU GRCBASE_MISC
4030
4031
4032/*the offset of the configuration space in the pci core register*/
4033#define PCICFG_OFFSET 0x2000
4034#define PCICFG_VENDOR_ID_OFFSET 0x00
4035#define PCICFG_DEVICE_ID_OFFSET 0x02
4036#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
4037#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
4038#define PCICFG_INT_LINE 0x3c
4039#define PCICFG_INT_PIN 0x3d
4040#define PCICFG_CACHE_LINE_SIZE 0x0c
4041#define PCICFG_LATENCY_TIMER 0x0d
4042#define PCICFG_REVESION_ID 0x08
4043#define PCICFG_BAR_1_LOW 0x10
4044#define PCICFG_BAR_1_HIGH 0x14
4045#define PCICFG_BAR_2_LOW 0x18
4046#define PCICFG_BAR_2_HIGH 0x1c
4047#define PCICFG_GRC_ADDRESS 0x78
4048#define PCICFG_GRC_DATA 0x80
4049#define PCICFG_DEVICE_CONTROL 0xb4
4050#define PCICFG_LINK_CONTROL 0xbc
4051
4052#define BAR_USTRORM_INTMEM 0x400000
4053#define BAR_CSTRORM_INTMEM 0x410000
4054#define BAR_XSTRORM_INTMEM 0x420000
4055#define BAR_TSTRORM_INTMEM 0x430000
4056
4057#define BAR_IGU_INTMEM 0x440000
4058
4059#define BAR_DOORBELL_OFFSET 0x800000
4060
4061#define BAR_ME_REGISTER 0x450000
4062
4063
4064#define GRC_CONFIG_2_SIZE_REG 0x408 /* config_2 offset */
4065#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
4066#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
4067#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
4068#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
4069#define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
4070#define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
4071#define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
4072#define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
4073#define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
4074#define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
4075#define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
4076#define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
4077#define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
4078#define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
4079#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
4080#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
4081#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
4082#define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
4083#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
4084#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
4085#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
4086#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
4087#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
4088#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
4089#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
4090#define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
4091#define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
4092#define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
4093#define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
4094#define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
4095#define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
4096#define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
4097#define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
4098#define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
4099#define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
4100#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
4101#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
4102#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
4103#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
4104#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
4105
4106/* config_3 offset */
4107#define GRC_CONFIG_3_SIZE_REG (0x40c)
4108#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
4109#define PCI_CONFIG_3_FORCE_PME (1L<<24)
4110#define PCI_CONFIG_3_PME_STATUS (1L<<25)
4111#define PCI_CONFIG_3_PME_ENABLE (1L<<26)
4112#define PCI_CONFIG_3_PM_STATE (0x3L<<27)
4113#define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
4114#define PCI_CONFIG_3_PCI_POWER (1L<<31)
4115
4116/* config_2 offset */
4117#define GRC_CONFIG_2_SIZE_REG 0x408
4118
4119#define GRC_BAR2_CONFIG 0x4e0
4120#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
4121#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
4122#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
4123#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
4124#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
4125#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
4126#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
4127#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
4128#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
4129#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
4130#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
4131#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
4132#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
4133#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
4134#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
4135#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
4136#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
4137#define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
4138
4139#define PCI_PM_DATA_A (0x410)
4140#define PCI_PM_DATA_B (0x414)
4141#define PCI_ID_VAL1 (0x434)
4142#define PCI_ID_VAL2 (0x438)
4143
4144#define MDIO_REG_BANK_CL73_IEEEB0 0x0
4145#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
4146#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
4147#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
4148#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
4149
4150#define MDIO_REG_BANK_CL73_IEEEB1 0x10
4151#define MDIO_CL73_IEEEB1_AN_ADV2 0x01
4152#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
4153#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
4154#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
4155#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
4156
4157#define MDIO_REG_BANK_RX0 0x80b0
4158#define MDIO_RX0_RX_EQ_BOOST 0x1c
4159#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4160#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
4161
4162#define MDIO_REG_BANK_RX1 0x80c0
4163#define MDIO_RX1_RX_EQ_BOOST 0x1c
4164#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4165#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
4166
4167#define MDIO_REG_BANK_RX2 0x80d0
4168#define MDIO_RX2_RX_EQ_BOOST 0x1c
4169#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4170#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
4171
4172#define MDIO_REG_BANK_RX3 0x80e0
4173#define MDIO_RX3_RX_EQ_BOOST 0x1c
4174#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4175#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
4176
4177#define MDIO_REG_BANK_RX_ALL 0x80f0
4178#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
4179#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4180#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
4181
4182#define MDIO_REG_BANK_TX0 0x8060
4183#define MDIO_TX0_TX_DRIVER 0x17
4184#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
4185#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
4186#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
4187#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
4188#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
4189#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
4190#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
4191#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
4192#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
4193
4194#define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
4195#define MDIO_BLOCK0_XGXS_CONTROL 0x10
4196
4197#define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
4198#define MDIO_BLOCK1_LANE_CTRL0 0x15
4199#define MDIO_BLOCK1_LANE_CTRL1 0x16
4200#define MDIO_BLOCK1_LANE_CTRL2 0x17
4201#define MDIO_BLOCK1_LANE_PRBS 0x19
4202
4203#define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
4204#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
4205#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
4206#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
4207#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
4208#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
4209#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
4210
4211#define MDIO_REG_BANK_GP_STATUS 0x8120
4212#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
4213#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
4214#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
4215#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
4216#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
4217#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
4218#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
4219
4220#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
4221#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
4222#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
4223#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
4224#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
4225#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
4226#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
4227#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
4228#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
4229#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
4230#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
4231#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
4232#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
4233#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
4234#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
4235#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
4236#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
4237#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
4238
4239
4240#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
4241#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
4242#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
4243#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
4244#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
4245
4246#define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
4247#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
4248#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
4249#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
4250#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
4251#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
4252#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
4253#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
4254#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
4255#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
4256#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
4257#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
4258#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
4259#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
4260#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
4261#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
4262#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
4263#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
4264#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
4265#define MDIO_SERDES_DIGITAL_MISC1 0x18
4266#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
4267#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
4268#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
4269#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
4270#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
4271#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
4272#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
4273#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
4274#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
4275#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
4276#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
4277#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
4278#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
4279#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
4280#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
4281#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
4282#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
4283#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
4284
4285#define MDIO_REG_BANK_OVER_1G 0x8320
4286#define MDIO_OVER_1G_DIGCTL_3_4 0x14
4287#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
4288#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
4289#define MDIO_OVER_1G_UP1 0x19
4290#define MDIO_OVER_1G_UP1_2_5G 0x0001
4291#define MDIO_OVER_1G_UP1_5G 0x0002
4292#define MDIO_OVER_1G_UP1_6G 0x0004
4293#define MDIO_OVER_1G_UP1_10G 0x0010
4294#define MDIO_OVER_1G_UP1_10GH 0x0008
4295#define MDIO_OVER_1G_UP1_12G 0x0020
4296#define MDIO_OVER_1G_UP1_12_5G 0x0040
4297#define MDIO_OVER_1G_UP1_13G 0x0080
4298#define MDIO_OVER_1G_UP1_15G 0x0100
4299#define MDIO_OVER_1G_UP1_16G 0x0200
4300#define MDIO_OVER_1G_UP2 0x1A
4301#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
4302#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
4303#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
4304#define MDIO_OVER_1G_UP3 0x1B
4305#define MDIO_OVER_1G_UP3_HIGIG2 0x0001
4306#define MDIO_OVER_1G_LP_UP1 0x1C
4307#define MDIO_OVER_1G_LP_UP2 0x1D
4308#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
4309#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
4310#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
4311#define MDIO_OVER_1G_LP_UP3 0x1E
4312
4313#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
4314#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
4315#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
4316#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
4317
4318#define MDIO_REG_BANK_CL73_USERB0 0x8370
4319#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
4320#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
4321#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
4322#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
4323#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
4324#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
4325
4326#define MDIO_REG_BANK_AER_BLOCK 0xFFD0
4327#define MDIO_AER_BLOCK_AER_REG 0x1E
4328
4329#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
4330#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
4331#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
4332#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
4333#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
4334#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
4335#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
4336#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
4337#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
4338#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
4339#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
4340#define MDIO_COMBO_IEEE0_MII_STATUS 0x11
4341#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
4342#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
4343#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
4344#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
4345#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
4346#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
4347#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
4348#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
4349#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
4350#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
4351#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
4352#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
4353#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
4354#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
4355#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
4356#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE\
4357 0x0000
4358#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH\
4359 0x0180
4360#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
4361#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
4362#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
4363
4364
4365#define EXT_PHY_OPT_PMA_PMD_DEVAD 0x1
4366#define EXT_PHY_OPT_WIS_DEVAD 0x2
4367#define EXT_PHY_OPT_PCS_DEVAD 0x3
4368#define EXT_PHY_OPT_PHY_XS_DEVAD 0x4
4369#define EXT_PHY_OPT_CNTL 0x0
4370#define EXT_PHY_OPT_PMD_RX_SD 0xa
4371#define EXT_PHY_OPT_PMD_MISC_CNTL 0xca0a
4372#define EXT_PHY_OPT_PHY_IDENTIFIER 0xc800
4373#define EXT_PHY_OPT_PMD_DIGITAL_CNT 0xc808
4374#define EXT_PHY_OPT_PMD_DIGITAL_SATUS 0xc809
4375#define EXT_PHY_OPT_CMU_PLL_BYPASS 0xca09
4376#define EXT_PHY_OPT_LASI_CNTL 0x9002
4377#define EXT_PHY_OPT_RX_ALARM 0x9003
4378#define EXT_PHY_OPT_LASI_STATUS 0x9005
4379#define EXT_PHY_OPT_PCS_STATUS 0x0020
4380#define EXT_PHY_OPT_XGXS_LANE_STATUS 0x0018
4381
4382#define EXT_PHY_KR_PMA_PMD_DEVAD 0x1
4383#define EXT_PHY_KR_PCS_DEVAD 0x3
4384#define EXT_PHY_KR_AUTO_NEG_DEVAD 0x7
4385#define EXT_PHY_KR_CTRL 0x0000
4386#define EXT_PHY_KR_CTRL2 0x0007
4387#define EXT_PHY_KR_PCS_STATUS 0x0020
4388#define EXT_PHY_KR_PMD_CTRL 0x0096
4389#define EXT_PHY_KR_LASI_CNTL 0x9002
4390#define EXT_PHY_KR_LASI_STATUS 0x9005
4391#define EXT_PHY_KR_MISC_CTRL1 0xca85
4392#define EXT_PHY_KR_GEN_CTRL 0xca10
4393#define EXT_PHY_KR_ROM_CODE 0xca19
4394
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 1fbd0256e86b..f162d9c1226c 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1943,6 +1943,7 @@
1943#define PCI_DEVICE_ID_NX2_5706 0x164a 1943#define PCI_DEVICE_ID_NX2_5706 0x164a
1944#define PCI_DEVICE_ID_NX2_5708 0x164c 1944#define PCI_DEVICE_ID_NX2_5708 0x164c
1945#define PCI_DEVICE_ID_TIGON3_5702FE 0x164d 1945#define PCI_DEVICE_ID_TIGON3_5702FE 0x164d
1946#define PCI_DEVICE_ID_NX2_57710 0x164e
1946#define PCI_DEVICE_ID_TIGON3_5705 0x1653 1947#define PCI_DEVICE_ID_TIGON3_5705 0x1653
1947#define PCI_DEVICE_ID_TIGON3_5705_2 0x1654 1948#define PCI_DEVICE_ID_TIGON3_5705_2 0x1654
1948#define PCI_DEVICE_ID_TIGON3_5720 0x1658 1949#define PCI_DEVICE_ID_TIGON3_5720 0x1658
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 09:53:21 -0500