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authorMatt Porter <mporter@kernel.crashing.org>2005-08-01 01:34:52 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-08-01 22:14:01 -0400
commitc9cf73aee140baa425429902aaed2c758401343f (patch)
tree7e28361e87950e7e66a453e4218745a4b0912119
parente8be1c8e065691c332fd8e9bae70c7096a69c31d (diff)
[PATCH] ppc32: add 440ep support
Add PPC440EP core support. PPC440EP is a PPC440-based SoC with a classic PPC FPU and another set of peripherals. Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com> Signed-off-by: Matt Porter <mporter@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat
-rw-r--r--arch/ppc/boot/simple/Makefile6
-rw-r--r--arch/ppc/boot/simple/pibs.c4
-rw-r--r--arch/ppc/kernel/cputable.c20
-rw-r--r--arch/ppc/kernel/entry.S1
-rw-r--r--arch/ppc/kernel/head_44x.S12
-rw-r--r--arch/ppc/kernel/misc.S1
-rw-r--r--arch/ppc/platforms/4xx/Kconfig20
-rw-r--r--arch/ppc/platforms/4xx/Makefile2
-rw-r--r--arch/ppc/platforms/4xx/ibm440ep.c220
-rw-r--r--arch/ppc/platforms/4xx/ibm440ep.h76
-rw-r--r--arch/ppc/syslib/Makefile2
-rw-r--r--arch/ppc/syslib/ibm440gx_common.c15
-rw-r--r--arch/ppc/syslib/ibm44x_common.h4
-rw-r--r--include/asm-ppc/ibm44x.h34
-rw-r--r--include/asm-ppc/ibm4xx.h4
-rw-r--r--include/asm-ppc/ppc_asm.h6
16 files changed, 421 insertions, 6 deletions
diff --git a/arch/ppc/boot/simple/Makefile b/arch/ppc/boot/simple/Makefile
index 991b4cbb83c8..d4dc4fa79647 100644
--- a/arch/ppc/boot/simple/Makefile
+++ b/arch/ppc/boot/simple/Makefile
@@ -61,6 +61,12 @@ zimageinitrd-$(CONFIG_IBM_OPENBIOS) := zImage.initrd-TREE
61 end-$(CONFIG_EMBEDDEDBOOT) := embedded 61 end-$(CONFIG_EMBEDDEDBOOT) := embedded
62 misc-$(CONFIG_EMBEDDEDBOOT) := misc-embedded.o 62 misc-$(CONFIG_EMBEDDEDBOOT) := misc-embedded.o
63 63
64 zimage-$(CONFIG_BAMBOO) := zImage-TREE
65zimageinitrd-$(CONFIG_BAMBOO) := zImage.initrd-TREE
66 end-$(CONFIG_BAMBOO) := bamboo
67 entrypoint-$(CONFIG_BAMBOO) := 0x01000000
68 extra.o-$(CONFIG_BAMBOO) := pibs.o
69
64 zimage-$(CONFIG_EBONY) := zImage-TREE 70 zimage-$(CONFIG_EBONY) := zImage-TREE
65zimageinitrd-$(CONFIG_EBONY) := zImage.initrd-TREE 71zimageinitrd-$(CONFIG_EBONY) := zImage.initrd-TREE
66 end-$(CONFIG_EBONY) := ebony 72 end-$(CONFIG_EBONY) := ebony
diff --git a/arch/ppc/boot/simple/pibs.c b/arch/ppc/boot/simple/pibs.c
index 1348740e503f..67222d57c345 100644
--- a/arch/ppc/boot/simple/pibs.c
+++ b/arch/ppc/boot/simple/pibs.c
@@ -91,9 +91,11 @@ load_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
91 91
92 mac64 = simple_strtoull((char *)PIBS_MAC_BASE, 0, 16); 92 mac64 = simple_strtoull((char *)PIBS_MAC_BASE, 0, 16);
93 memcpy(hold_residual->bi_enetaddr, (char *)&mac64+2, 6); 93 memcpy(hold_residual->bi_enetaddr, (char *)&mac64+2, 6);
94#ifdef CONFIG_440GX 94#if defined(CONFIG_440GX) || defined(CONFIG_440EP)
95 mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET), 0, 16); 95 mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET), 0, 16);
96 memcpy(hold_residual->bi_enet1addr, (char *)&mac64+2, 6); 96 memcpy(hold_residual->bi_enet1addr, (char *)&mac64+2, 6);
97#endif
98#ifdef CONFIG_440GX
97 mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*2), 0, 16); 99 mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*2), 0, 16);
98 memcpy(hold_residual->bi_enet2addr, (char *)&mac64+2, 6); 100 memcpy(hold_residual->bi_enet2addr, (char *)&mac64+2, 6);
99 mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*3), 0, 16); 101 mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*3), 0, 16);
diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c
index 50936cda0af9..8a3d74f2531e 100644
--- a/arch/ppc/kernel/cputable.c
+++ b/arch/ppc/kernel/cputable.c
@@ -852,6 +852,26 @@ struct cpu_spec cpu_specs[] = {
852 852
853#endif /* CONFIG_40x */ 853#endif /* CONFIG_40x */
854#ifdef CONFIG_44x 854#ifdef CONFIG_44x
855 {
856 .pvr_mask = 0xf0000fff,
857 .pvr_value = 0x40000850,
858 .cpu_name = "440EP Rev. A",
859 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
860 CPU_FTR_USE_TB,
861 .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
862 .icache_bsize = 32,
863 .dcache_bsize = 32,
864 },
865 {
866 .pvr_mask = 0xf0000fff,
867 .pvr_value = 0x400008d3,
868 .cpu_name = "440EP Rev. B",
869 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
870 CPU_FTR_USE_TB,
871 .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
872 .icache_bsize = 32,
873 .dcache_bsize = 32,
874 },
855 { /* 440GP Rev. B */ 875 { /* 440GP Rev. B */
856 .pvr_mask = 0xf0000fff, 876 .pvr_mask = 0xf0000fff,
857 .pvr_value = 0x40000440, 877 .pvr_value = 0x40000440,
diff --git a/arch/ppc/kernel/entry.S b/arch/ppc/kernel/entry.S
index d4df68629cc6..cb83045e2edf 100644
--- a/arch/ppc/kernel/entry.S
+++ b/arch/ppc/kernel/entry.S
@@ -215,6 +215,7 @@ syscall_dotrace_cont:
215 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */ 215 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
216 mtlr r10 216 mtlr r10
217 addi r9,r1,STACK_FRAME_OVERHEAD 217 addi r9,r1,STACK_FRAME_OVERHEAD
218 PPC440EP_ERR42
218 blrl /* Call handler */ 219 blrl /* Call handler */
219 .globl ret_from_syscall 220 .globl ret_from_syscall
220ret_from_syscall: 221ret_from_syscall:
diff --git a/arch/ppc/kernel/head_44x.S b/arch/ppc/kernel/head_44x.S
index 72ee8f33bde4..69ff3a9961e8 100644
--- a/arch/ppc/kernel/head_44x.S
+++ b/arch/ppc/kernel/head_44x.S
@@ -190,7 +190,9 @@ skpinv: addi r4,r4,1 /* Increment */
190 190
191 /* xlat fields */ 191 /* xlat fields */
192 lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */ 192 lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */
193#ifndef CONFIG_440EP
193 ori r4,r4,0x0001 /* ERPN is 1 for second 4GB page */ 194 ori r4,r4,0x0001 /* ERPN is 1 for second 4GB page */
195#endif
194 196
195 /* attrib fields */ 197 /* attrib fields */
196 li r5,0 198 li r5,0
@@ -228,6 +230,16 @@ skpinv: addi r4,r4,1 /* Increment */
228 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ 230 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
229 mtspr SPRN_IVPR,r4 231 mtspr SPRN_IVPR,r4
230 232
233#ifdef CONFIG_440EP
234 /* Clear DAPUIB flag in CCR0 (enable APU between CPU and FPU) */
235 mfspr r2,SPRN_CCR0
236 lis r3,0xffef
237 ori r3,r3,0xffff
238 and r2,r2,r3
239 mtspr SPRN_CCR0,r2
240 isync
241#endif
242
231 /* 243 /*
232 * This is where the main kernel code starts. 244 * This is where the main kernel code starts.
233 */ 245 */
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index c2fb85b49a11..ce71b4a01585 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -1145,6 +1145,7 @@ _GLOBAL(kernel_thread)
1145 stwu r0,-16(r1) 1145 stwu r0,-16(r1)
1146 mtlr r30 /* fn addr in lr */ 1146 mtlr r30 /* fn addr in lr */
1147 mr r3,r31 /* load arg and call fn */ 1147 mr r3,r31 /* load arg and call fn */
1148 PPC440EP_ERR42
1148 blrl 1149 blrl
1149 li r0,__NR_exit /* exit if function returns */ 1150 li r0,__NR_exit /* exit if function returns */
1150 li r3,0 1151 li r3,0
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
index a0612a86455a..f7c045764e04 100644
--- a/arch/ppc/platforms/4xx/Kconfig
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -68,6 +68,11 @@ choice
68 depends on 44x 68 depends on 44x
69 default EBONY 69 default EBONY
70 70
71config BAMBOO
72 bool "Bamboo"
73 help
74 This option enables support for the IBM PPC440EP evaluation board.
75
71config EBONY 76config EBONY
72 bool "Ebony" 77 bool "Ebony"
73 help 78 help
@@ -98,6 +103,12 @@ config NP405H
98 depends on ASH 103 depends on ASH
99 default y 104 default y
100 105
106config 440EP
107 bool
108 depends on BAMBOO
109 select PPC_FPU
110 default y
111
101config 440GP 112config 440GP
102 bool 113 bool
103 depends on EBONY 114 depends on EBONY
@@ -115,7 +126,7 @@ config 440SP
115 126
116config 440 127config 440
117 bool 128 bool
118 depends on 440GP || 440SP 129 depends on 440GP || 440SP || 440EP
119 default y 130 default y
120 131
121config 440A 132config 440A
@@ -123,6 +134,11 @@ config 440A
123 depends on 440GX 134 depends on 440GX
124 default y 135 default y
125 136
137config IBM440EP_ERR42
138 bool
139 depends on 440EP
140 default y
141
126# All 405-based cores up until the 405GPR and 405EP have this errata. 142# All 405-based cores up until the 405GPR and 405EP have this errata.
127config IBM405_ERR77 143config IBM405_ERR77
128 bool 144 bool
@@ -142,7 +158,7 @@ config BOOKE
142 158
143config IBM_OCP 159config IBM_OCP
144 bool 160 bool
145 depends on ASH || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT 161 depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
146 default y 162 default y
147 163
148config XILINX_OCP 164config XILINX_OCP
diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile
index ea470c6adbb6..844c3b5066e8 100644
--- a/arch/ppc/platforms/4xx/Makefile
+++ b/arch/ppc/platforms/4xx/Makefile
@@ -2,6 +2,7 @@
2# Makefile for the PowerPC 4xx linux kernel. 2# Makefile for the PowerPC 4xx linux kernel.
3 3
4obj-$(CONFIG_ASH) += ash.o 4obj-$(CONFIG_ASH) += ash.o
5obj-$(CONFIG_BAMBOO) += bamboo.o
5obj-$(CONFIG_CPCI405) += cpci405.o 6obj-$(CONFIG_CPCI405) += cpci405.o
6obj-$(CONFIG_EBONY) += ebony.o 7obj-$(CONFIG_EBONY) += ebony.o
7obj-$(CONFIG_EP405) += ep405.o 8obj-$(CONFIG_EP405) += ep405.o
@@ -19,6 +20,7 @@ obj-$(CONFIG_405GP) += ibm405gp.o
19obj-$(CONFIG_REDWOOD_5) += ibmstb4.o 20obj-$(CONFIG_REDWOOD_5) += ibmstb4.o
20obj-$(CONFIG_NP405H) += ibmnp405h.o 21obj-$(CONFIG_NP405H) += ibmnp405h.o
21obj-$(CONFIG_REDWOOD_6) += ibmstbx25.o 22obj-$(CONFIG_REDWOOD_6) += ibmstbx25.o
23obj-$(CONFIG_440EP) += ibm440ep.o
22obj-$(CONFIG_440GP) += ibm440gp.o 24obj-$(CONFIG_440GP) += ibm440gp.o
23obj-$(CONFIG_440GX) += ibm440gx.o 25obj-$(CONFIG_440GX) += ibm440gx.o
24obj-$(CONFIG_440SP) += ibm440sp.o 26obj-$(CONFIG_440SP) += ibm440sp.o
diff --git a/arch/ppc/platforms/4xx/ibm440ep.c b/arch/ppc/platforms/4xx/ibm440ep.c
new file mode 100644
index 000000000000..284da01f1ffd
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm440ep.c
@@ -0,0 +1,220 @@
1/*
2 * arch/ppc/platforms/4xx/ibm440ep.c
3 *
4 * PPC440EP I/O descriptions
5 *
6 * Wade Farnsworth <wfarnsworth@mvista.com>
7 * Copyright 2004 MontaVista Software Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15#include <linux/init.h>
16#include <linux/module.h>
17#include <platforms/4xx/ibm440ep.h>
18#include <asm/ocp.h>
19#include <asm/ppc4xx_pic.h>
20
21static struct ocp_func_emac_data ibm440ep_emac0_def = {
22 .rgmii_idx = -1, /* No RGMII */
23 .rgmii_mux = -1, /* No RGMII */
24 .zmii_idx = 0, /* ZMII device index */
25 .zmii_mux = 0, /* ZMII input of this EMAC */
26 .mal_idx = 0, /* MAL device index */
27 .mal_rx_chan = 0, /* MAL rx channel number */
28 .mal_tx_chan = 0, /* MAL tx channel number */
29 .wol_irq = 61, /* WOL interrupt number */
30 .mdio_idx = -1, /* No shared MDIO */
31 .tah_idx = -1, /* No TAH */
32};
33
34static struct ocp_func_emac_data ibm440ep_emac1_def = {
35 .rgmii_idx = -1, /* No RGMII */
36 .rgmii_mux = -1, /* No RGMII */
37 .zmii_idx = 0, /* ZMII device index */
38 .zmii_mux = 1, /* ZMII input of this EMAC */
39 .mal_idx = 0, /* MAL device index */
40 .mal_rx_chan = 1, /* MAL rx channel number */
41 .mal_tx_chan = 2, /* MAL tx channel number */
42 .wol_irq = 63, /* WOL interrupt number */
43 .mdio_idx = -1, /* No shared MDIO */
44 .tah_idx = -1, /* No TAH */
45};
46OCP_SYSFS_EMAC_DATA()
47
48static struct ocp_func_mal_data ibm440ep_mal0_def = {
49 .num_tx_chans = 4, /* Number of TX channels */
50 .num_rx_chans = 2, /* Number of RX channels */
51 .txeob_irq = 10, /* TX End Of Buffer IRQ */
52 .rxeob_irq = 11, /* RX End Of Buffer IRQ */
53 .txde_irq = 33, /* TX Descriptor Error IRQ */
54 .rxde_irq = 34, /* RX Descriptor Error IRQ */
55 .serr_irq = 32, /* MAL System Error IRQ */
56};
57OCP_SYSFS_MAL_DATA()
58
59static struct ocp_func_iic_data ibm440ep_iic0_def = {
60 .fast_mode = 0, /* Use standad mode (100Khz) */
61};
62
63static struct ocp_func_iic_data ibm440ep_iic1_def = {
64 .fast_mode = 0, /* Use standad mode (100Khz) */
65};
66OCP_SYSFS_IIC_DATA()
67
68struct ocp_def core_ocp[] = {
69 { .vendor = OCP_VENDOR_IBM,
70 .function = OCP_FUNC_OPB,
71 .index = 0,
72 .paddr = 0x0EF600000ULL,
73 .irq = OCP_IRQ_NA,
74 .pm = OCP_CPM_NA,
75 },
76 { .vendor = OCP_VENDOR_IBM,
77 .function = OCP_FUNC_16550,
78 .index = 0,
79 .paddr = PPC440EP_UART0_ADDR,
80 .irq = UART0_INT,
81 .pm = IBM_CPM_UART0,
82 },
83 { .vendor = OCP_VENDOR_IBM,
84 .function = OCP_FUNC_16550,
85 .index = 1,
86 .paddr = PPC440EP_UART1_ADDR,
87 .irq = UART1_INT,
88 .pm = IBM_CPM_UART1,
89 },
90 { .vendor = OCP_VENDOR_IBM,
91 .function = OCP_FUNC_16550,
92 .index = 2,
93 .paddr = PPC440EP_UART2_ADDR,
94 .irq = UART2_INT,
95 .pm = IBM_CPM_UART2,
96 },
97 { .vendor = OCP_VENDOR_IBM,
98 .function = OCP_FUNC_16550,
99 .index = 3,
100 .paddr = PPC440EP_UART3_ADDR,
101 .irq = UART3_INT,
102 .pm = IBM_CPM_UART3,
103 },
104 { .vendor = OCP_VENDOR_IBM,
105 .function = OCP_FUNC_IIC,
106 .index = 0,
107 .paddr = 0x0EF600700ULL,
108 .irq = 2,
109 .pm = IBM_CPM_IIC0,
110 .additions = &ibm440ep_iic0_def,
111 .show = &ocp_show_iic_data
112 },
113 { .vendor = OCP_VENDOR_IBM,
114 .function = OCP_FUNC_IIC,
115 .index = 1,
116 .paddr = 0x0EF600800ULL,
117 .irq = 7,
118 .pm = IBM_CPM_IIC1,
119 .additions = &ibm440ep_iic1_def,
120 .show = &ocp_show_iic_data
121 },
122 { .vendor = OCP_VENDOR_IBM,
123 .function = OCP_FUNC_GPIO,
124 .index = 0,
125 .paddr = 0x0EF600B00ULL,
126 .irq = OCP_IRQ_NA,
127 .pm = IBM_CPM_GPIO0,
128 },
129 { .vendor = OCP_VENDOR_IBM,
130 .function = OCP_FUNC_GPIO,
131 .index = 1,
132 .paddr = 0x0EF600C00ULL,
133 .irq = OCP_IRQ_NA,
134 .pm = OCP_CPM_NA,
135 },
136 { .vendor = OCP_VENDOR_IBM,
137 .function = OCP_FUNC_MAL,
138 .paddr = OCP_PADDR_NA,
139 .irq = OCP_IRQ_NA,
140 .pm = OCP_CPM_NA,
141 .additions = &ibm440ep_mal0_def,
142 .show = &ocp_show_mal_data,
143 },
144 { .vendor = OCP_VENDOR_IBM,
145 .function = OCP_FUNC_EMAC,
146 .index = 0,
147 .paddr = 0x0EF600E00ULL,
148 .irq = 60,
149 .pm = OCP_CPM_NA,
150 .additions = &ibm440ep_emac0_def,
151 .show = &ocp_show_emac_data,
152 },
153 { .vendor = OCP_VENDOR_IBM,
154 .function = OCP_FUNC_EMAC,
155 .index = 1,
156 .paddr = 0x0EF600F00ULL,
157 .irq = 62,
158 .pm = OCP_CPM_NA,
159 .additions = &ibm440ep_emac1_def,
160 .show = &ocp_show_emac_data,
161 },
162 { .vendor = OCP_VENDOR_IBM,
163 .function = OCP_FUNC_ZMII,
164 .paddr = 0x0EF600D00ULL,
165 .irq = OCP_IRQ_NA,
166 .pm = OCP_CPM_NA,
167 },
168 { .vendor = OCP_VENDOR_INVALID
169 }
170};
171
172/* Polarity and triggering settings for internal interrupt sources */
173struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
174 { .polarity = 0xffbffe03,
175 .triggering = 0xfffffe00,
176 .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
177 },
178 { .polarity = 0xffffc6ef,
179 .triggering = 0xffffc7ff,
180 .ext_irq_mask = 0x00003800, /* IRQ7 - IRQ9 */
181 },
182};
183
184static struct resource usb_gadget_resources[] = {
185 [0] = {
186 .start = 0x050000100ULL,
187 .end = 0x05000017FULL,
188 .flags = IORESOURCE_MEM,
189 },
190 [1] = {
191 .start = 55,
192 .end = 55,
193 .flags = IORESOURCE_IRQ,
194 },
195};
196
197static u64 dma_mask = 0xffffffffULL;
198
199static struct platform_device usb_gadget_device = {
200 .name = "musbhsfc",
201 .id = 0,
202 .num_resources = ARRAY_SIZE(usb_gadget_resources),
203 .resource = usb_gadget_resources,
204 .dev = {
205 .dma_mask = &dma_mask,
206 .coherent_dma_mask = 0xffffffffULL,
207 }
208};
209
210static struct platform_device *ibm440ep_devs[] __initdata = {
211 &usb_gadget_device,
212};
213
214static int __init
215ibm440ep_platform_add_devices(void)
216{
217 return platform_add_devices(ibm440ep_devs, ARRAY_SIZE(ibm440ep_devs));
218}
219arch_initcall(ibm440ep_platform_add_devices);
220
diff --git a/arch/ppc/platforms/4xx/ibm440ep.h b/arch/ppc/platforms/4xx/ibm440ep.h
new file mode 100644
index 000000000000..97c80b8e3e10
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm440ep.h
@@ -0,0 +1,76 @@
1/*
2 * arch/ppc/platforms/4xx/ibm440ep.h
3 *
4 * PPC440EP definitions
5 *
6 * Wade Farnsworth <wfarnsworth@mvista.com>
7 *
8 * Copyright 2002 Roland Dreier
9 * Copyright 2004 MontaVista Software, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#ifdef __KERNEL__
19#ifndef __PPC_PLATFORMS_IBM440EP_H
20#define __PPC_PLATFORMS_IBM440EP_H
21
22#include <linux/config.h>
23#include <asm/ibm44x.h>
24
25/* UART */
26#define PPC440EP_UART0_ADDR 0x0EF600300
27#define PPC440EP_UART1_ADDR 0x0EF600400
28#define PPC440EP_UART2_ADDR 0x0EF600500
29#define PPC440EP_UART3_ADDR 0x0EF600600
30#define UART0_INT 0
31#define UART1_INT 1
32#define UART2_INT 3
33#define UART3_INT 4
34
35/* Clock and Power Management */
36#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
37#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
38#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
39#define IBM_CPM_USB1H 0x08000000 /* USB 1.1 Host */
40#define IBM_CPM_FPU 0x04000000 /* floating point unit */
41#define IBM_CPM_CPU 0x02000000 /* processor core */
42#define IBM_CPM_DMA 0x01000000 /* DMA controller */
43#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
44#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
45#define IBM_CPM_EBC 0x00200000 /* External Bus Controller */
46#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
47#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
48#define IBM_CPM_PLB4 0x00040000 /* PLB4 bus arbiter */
49#define IBM_CPM_PLB4x3 0x00020000 /* PLB4 to PLB3 bridge controller */
50#define IBM_CPM_PLB3x4 0x00010000 /* PLB3 to PLB4 bridge controller */
51#define IBM_CPM_PLB3 0x00008000 /* PLB3 bus arbiter */
52#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
53#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
54#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
55#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
56#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
57#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
58#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
59#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
60#define IBM_CPM_EMAC0 0x00000020 /* ethernet port 0 */
61#define IBM_CPM_EMAC1 0x00000010 /* ethernet port 1 */
62#define IBM_CPM_UART2 0x00000008 /* serial port 2 */
63#define IBM_CPM_UART3 0x00000004 /* serial port 3 */
64#define IBM_CPM_USB2D 0x00000002 /* USB 2.0 Device */
65#define IBM_CPM_USB2H 0x00000001 /* USB 2.0 Host */
66
67#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
68 | IBM_CPM_EBC | IBM_CPM_BGO | IBM_CPM_FPU \
69 | IBM_CPM_EBM | IBM_CPM_PLB4 | IBM_CPM_3x4 \
70 | IBM_CPM_PLB3 | IBM_CPM_PLB4x3 \
71 | IBM_CPM_EMAC0 | IBM_CPM_TMRCLK \
72 | IBM_CPM_DMA | IBM_CPM_PCI | IBM_CPM_EMAC1)
73
74
75#endif /* __PPC_PLATFORMS_IBM440EP_H */
76#endif /* __KERNEL__ */
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
index dec5bf4f6879..220a65ab0a51 100644
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_PPCBUG_NVRAM) += prep_nvram.o
11obj-$(CONFIG_PPC_OCP) += ocp.o 11obj-$(CONFIG_PPC_OCP) += ocp.o
12obj-$(CONFIG_IBM_OCP) += ibm_ocp.o 12obj-$(CONFIG_IBM_OCP) += ibm_ocp.o
13obj-$(CONFIG_44x) += ibm44x_common.o 13obj-$(CONFIG_44x) += ibm44x_common.o
14obj-$(CONFIG_440EP) += ibm440gx_common.o
14obj-$(CONFIG_440GP) += ibm440gp_common.o 15obj-$(CONFIG_440GP) += ibm440gp_common.o
15obj-$(CONFIG_440GX) += ibm440gx_common.o 16obj-$(CONFIG_440GX) += ibm440gx_common.o
16obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o 17obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o
@@ -44,6 +45,7 @@ obj-$(CONFIG_PPC_CHRP) += open_pic.o indirect_pci.o i8259.o
44obj-$(CONFIG_PPC_PREP) += open_pic.o indirect_pci.o i8259.o todc_time.o 45obj-$(CONFIG_PPC_PREP) += open_pic.o indirect_pci.o i8259.o todc_time.o
45obj-$(CONFIG_ADIR) += i8259.o indirect_pci.o pci_auto.o \ 46obj-$(CONFIG_ADIR) += i8259.o indirect_pci.o pci_auto.o \
46 todc_time.o 47 todc_time.o
48obj-$(CONFIG_BAMBOO) += indirect_pci.o pci_auto.o todc_time.o
47obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o 49obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o
48obj-$(CONFIG_EBONY) += indirect_pci.o pci_auto.o todc_time.o 50obj-$(CONFIG_EBONY) += indirect_pci.o pci_auto.o todc_time.o
49obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o 51obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o
diff --git a/arch/ppc/syslib/ibm440gx_common.c b/arch/ppc/syslib/ibm440gx_common.c
index 4ad85e0e0234..d4776af6a3ca 100644
--- a/arch/ppc/syslib/ibm440gx_common.c
+++ b/arch/ppc/syslib/ibm440gx_common.c
@@ -34,6 +34,10 @@ void __init ibm440gx_get_clocks(struct ibm44x_clocks* p, unsigned int sys_clk,
34 u32 plld = CPR_READ(DCRN_CPR_PLLD); 34 u32 plld = CPR_READ(DCRN_CPR_PLLD);
35 u32 uart0 = SDR_READ(DCRN_SDR_UART0); 35 u32 uart0 = SDR_READ(DCRN_SDR_UART0);
36 u32 uart1 = SDR_READ(DCRN_SDR_UART1); 36 u32 uart1 = SDR_READ(DCRN_SDR_UART1);
37#ifdef CONFIG_440EP
38 u32 uart2 = SDR_READ(DCRN_SDR_UART2);
39 u32 uart3 = SDR_READ(DCRN_SDR_UART3);
40#endif
37 41
38 /* Dividers */ 42 /* Dividers */
39 u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32); 43 u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32);
@@ -96,6 +100,17 @@ bypass:
96 p->uart1 = ser_clk; 100 p->uart1 = ser_clk;
97 else 101 else
98 p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256); 102 p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256);
103#ifdef CONFIG_440EP
104 if (uart2 & 0x00800000)
105 p->uart2 = ser_clk;
106 else
107 p->uart2 = p->plb / __fix_zero(uart2 & 0xff, 256);
108
109 if (uart3 & 0x00800000)
110 p->uart3 = ser_clk;
111 else
112 p->uart3 = p->plb / __fix_zero(uart3 & 0xff, 256);
113#endif
99} 114}
100 115
101/* Issue L2C diagnostic command */ 116/* Issue L2C diagnostic command */
diff --git a/arch/ppc/syslib/ibm44x_common.h b/arch/ppc/syslib/ibm44x_common.h
index b14eb603ce01..c16b6a5ac6ab 100644
--- a/arch/ppc/syslib/ibm44x_common.h
+++ b/arch/ppc/syslib/ibm44x_common.h
@@ -29,6 +29,10 @@ struct ibm44x_clocks {
29 unsigned int ebc; /* PerClk */ 29 unsigned int ebc; /* PerClk */
30 unsigned int uart0; 30 unsigned int uart0;
31 unsigned int uart1; 31 unsigned int uart1;
32#ifdef CONFIG_440EP
33 unsigned int uart2;
34 unsigned int uart3;
35#endif
32}; 36};
33 37
34/* common 44x platform init */ 38/* common 44x platform init */
diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h
index 87f051138b9d..21e41c9b7267 100644
--- a/include/asm-ppc/ibm44x.h
+++ b/include/asm-ppc/ibm44x.h
@@ -35,8 +35,10 @@
35#define PPC44x_LOW_SLOT 63 35#define PPC44x_LOW_SLOT 63
36 36
37/* LS 32-bits of UART0 physical address location for early serial text debug */ 37/* LS 32-bits of UART0 physical address location for early serial text debug */
38#ifdef CONFIG_440SP 38#if defined(CONFIG_440SP)
39#define UART0_PHYS_IO_BASE 0xf0000200 39#define UART0_PHYS_IO_BASE 0xf0000200
40#elif defined(CONFIG_440EP)
41#define UART0_PHYS_IO_BASE 0xe0000000
40#else 42#else
41#define UART0_PHYS_IO_BASE 0x40000200 43#define UART0_PHYS_IO_BASE 0x40000200
42#endif 44#endif
@@ -49,11 +51,16 @@
49/* 51/*
50 * Standard 4GB "page" definitions 52 * Standard 4GB "page" definitions
51 */ 53 */
52#ifdef CONFIG_440SP 54#if defined(CONFIG_440SP)
53#define PPC44x_IO_PAGE 0x0000000100000000ULL 55#define PPC44x_IO_PAGE 0x0000000100000000ULL
54#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL 56#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL
55#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE 57#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
56#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL 58#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL
59#elif defined(CONFIG_440EP)
60#define PPC44x_IO_PAGE 0x0000000000000000ULL
61#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL
62#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
63#define PPC44x_PCIMEM_PAGE 0x0000000000000000ULL
57#else 64#else
58#define PPC44x_IO_PAGE 0x0000000100000000ULL 65#define PPC44x_IO_PAGE 0x0000000100000000ULL
59#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL 66#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL
@@ -64,7 +71,7 @@
64/* 71/*
65 * 36-bit trap ranges 72 * 36-bit trap ranges
66 */ 73 */
67#ifdef CONFIG_440SP 74#if defined(CONFIG_440SP)
68#define PPC44x_IO_LO 0xf0000000UL 75#define PPC44x_IO_LO 0xf0000000UL
69#define PPC44x_IO_HI 0xf0000fffUL 76#define PPC44x_IO_HI 0xf0000fffUL
70#define PPC44x_PCI0CFG_LO 0x0ec00000UL 77#define PPC44x_PCI0CFG_LO 0x0ec00000UL
@@ -75,6 +82,13 @@
75#define PPC44x_PCI2CFG_HI 0x2ec00007UL 82#define PPC44x_PCI2CFG_HI 0x2ec00007UL
76#define PPC44x_PCIMEM_LO 0x80000000UL 83#define PPC44x_PCIMEM_LO 0x80000000UL
77#define PPC44x_PCIMEM_HI 0xdfffffffUL 84#define PPC44x_PCIMEM_HI 0xdfffffffUL
85#elif defined(CONFIG_440EP)
86#define PPC44x_IO_LO 0xef500000UL
87#define PPC44x_IO_HI 0xefffffffUL
88#define PPC44x_PCI0CFG_LO 0xeec00000UL
89#define PPC44x_PCI0CFG_HI 0xeecfffffUL
90#define PPC44x_PCIMEM_LO 0xa0000000UL
91#define PPC44x_PCIMEM_HI 0xdfffffffUL
78#else 92#else
79#define PPC44x_IO_LO 0x40000000UL 93#define PPC44x_IO_LO 0x40000000UL
80#define PPC44x_IO_HI 0x40000fffUL 94#define PPC44x_IO_HI 0x40000fffUL
@@ -152,6 +166,12 @@
152#define DCRN_SDR_UART0 0x0120 166#define DCRN_SDR_UART0 0x0120
153#define DCRN_SDR_UART1 0x0121 167#define DCRN_SDR_UART1 0x0121
154 168
169#ifdef CONFIG_440EP
170#define DCRN_SDR_UART2 0x0122
171#define DCRN_SDR_UART3 0x0123
172#define DCRN_SDR_CUST0 0x4000
173#endif
174
155/* SDR read/write helper macros */ 175/* SDR read/write helper macros */
156#define SDR_READ(offset) ({\ 176#define SDR_READ(offset) ({\
157 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ 177 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
@@ -169,6 +189,14 @@
169#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ 189#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
170#define DCRN_MAL_BASE 0x180 190#define DCRN_MAL_BASE 0x180
171 191
192#ifdef CONFIG_440EP
193#define DCRN_DMA2P40_BASE 0x300
194#define DCRN_DMA2P41_BASE 0x308
195#define DCRN_DMA2P42_BASE 0x310
196#define DCRN_DMA2P43_BASE 0x318
197#define DCRN_DMA2P4SR_BASE 0x320
198#endif
199
172/* UIC */ 200/* UIC */
173#define DCRN_UIC0_BASE 0xc0 201#define DCRN_UIC0_BASE 0xc0
174#define DCRN_UIC1_BASE 0xd0 202#define DCRN_UIC1_BASE 0xd0
diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h
index 35260afa33a9..e807be96e981 100644
--- a/include/asm-ppc/ibm4xx.h
+++ b/include/asm-ppc/ibm4xx.h
@@ -97,6 +97,10 @@ void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
97 97
98#elif CONFIG_44x 98#elif CONFIG_44x
99 99
100#if defined(CONFIG_BAMBOO)
101#include <platforms/4xx/bamboo.h>
102#endif
103
100#if defined(CONFIG_EBONY) 104#if defined(CONFIG_EBONY)
101#include <platforms/4xx/ebony.h> 105#include <platforms/4xx/ebony.h>
102#endif 106#endif
diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-ppc/ppc_asm.h
index f76221def484..bb53e2def363 100644
--- a/include/asm-ppc/ppc_asm.h
+++ b/include/asm-ppc/ppc_asm.h
@@ -186,6 +186,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
186#define PPC405_ERR77_SYNC 186#define PPC405_ERR77_SYNC
187#endif 187#endif
188 188
189#ifdef CONFIG_IBM440EP_ERR42
190#define PPC440EP_ERR42 isync
191#else
192#define PPC440EP_ERR42
193#endif
194
189/* The boring bits... */ 195/* The boring bits... */
190 196
191/* Condition Register Bit Fields */ 197/* Condition Register Bit Fields */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 22:17:45 -0500