diff options
author | Stephane Eranian <eranian@hpl.hp.com> | 2006-12-06 20:14:01 -0500 |
---|---|---|
committer | Andi Kleen <andi@basil.nowhere.org> | 2006-12-06 20:14:01 -0500 |
commit | 36b2a8d5aff4cb3ee83d5e40447a8f073bcfe2fb (patch) | |
tree | a7883c46dcc89ac79474ff4717ec923043adfd2f | |
parent | bd1d599518bf11992cc6d5b0df08da4a2b7b0db5 (diff) |
[PATCH] x86-64: add X86_FEATURE_PEBS and detection
Here is a patch (used by perfmon2) to detect the presence of the
Precise Event Based Sampling (PEBS) feature for Intel 64-bit processors.
The patch also adds the cpu_has_pebs macro.
changelog:
- adds X86_FEATURE_PEBS
- adds cpu_has_pebs to test for X86_FEATURE_PEBS
Signed-off-by: stephane eranian <eranian@hpl.hp.com>
Signed-off-by: Andi Kleen <ak@suse.de>
-rw-r--r-- | arch/x86_64/kernel/setup.c | 7 | ||||
-rw-r--r-- | include/asm-x86_64/cpufeature.h | 2 |
2 files changed, 9 insertions, 0 deletions
diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c index fc944b5e8f4a..619af2e2fa26 100644 --- a/arch/x86_64/kernel/setup.c +++ b/arch/x86_64/kernel/setup.c | |||
@@ -835,6 +835,13 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) | |||
835 | set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability); | 835 | set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability); |
836 | } | 836 | } |
837 | 837 | ||
838 | if (cpu_has_ds) { | ||
839 | unsigned int l1, l2; | ||
840 | rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); | ||
841 | if (!(l1 & (1<<12))) | ||
842 | set_bit(X86_FEATURE_PEBS, c->x86_capability); | ||
843 | } | ||
844 | |||
838 | n = c->extended_cpuid_level; | 845 | n = c->extended_cpuid_level; |
839 | if (n >= 0x80000008) { | 846 | if (n >= 0x80000008) { |
840 | unsigned eax = cpuid_eax(0x80000008); | 847 | unsigned eax = cpuid_eax(0x80000008); |
diff --git a/include/asm-x86_64/cpufeature.h b/include/asm-x86_64/cpufeature.h index 65eb39e8f3cc..d280384807ef 100644 --- a/include/asm-x86_64/cpufeature.h +++ b/include/asm-x86_64/cpufeature.h | |||
@@ -68,6 +68,7 @@ | |||
68 | #define X86_FEATURE_FXSAVE_LEAK (3*32+7) /* FIP/FOP/FDP leaks through FXSAVE */ | 68 | #define X86_FEATURE_FXSAVE_LEAK (3*32+7) /* FIP/FOP/FDP leaks through FXSAVE */ |
69 | #define X86_FEATURE_UP (3*32+8) /* SMP kernel running on UP */ | 69 | #define X86_FEATURE_UP (3*32+8) /* SMP kernel running on UP */ |
70 | #define X86_FEATURE_ARCH_PERFMON (3*32+9) /* Intel Architectural PerfMon */ | 70 | #define X86_FEATURE_ARCH_PERFMON (3*32+9) /* Intel Architectural PerfMon */ |
71 | #define X86_FEATURE_PEBS (3*32+10) /* Precise-Event Based Sampling */ | ||
71 | 72 | ||
72 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | 73 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ |
73 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ | 74 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ |
@@ -113,5 +114,6 @@ | |||
113 | #define cpu_has_centaur_mcr 0 | 114 | #define cpu_has_centaur_mcr 0 |
114 | #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH) | 115 | #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH) |
115 | #define cpu_has_ds boot_cpu_has(X86_FEATURE_DS) | 116 | #define cpu_has_ds boot_cpu_has(X86_FEATURE_DS) |
117 | #define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS) | ||
116 | 118 | ||
117 | #endif /* __ASM_X8664_CPUFEATURE_H */ | 119 | #endif /* __ASM_X8664_CPUFEATURE_H */ |