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authorPavel Machek <pavel@ucw.cz>2008-04-08 04:49:03 -0400
committerIngo Molnar <mingo@elte.hu>2008-05-12 15:28:10 -0400
commitaa134f1b09df6beaa4d031a50d5fda1f3cebce6c (patch)
tree3bd632e6fa8490cf5b472271d57c8c70abaa62b4
parent492c2e476eac010962850006c49df326919b284c (diff)
x86: iommu: use symbolic constants, not hardcoded numbers
Move symbolic constants into gart.h, and use them instead of hardcoded constant. Signed-off-by: Pavel Machek <pavel@suse.cz> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
-rw-r--r--arch/x86/kernel/pci-gart_64.c10
-rw-r--r--drivers/char/agp/amd64-agp.c25
-rw-r--r--include/asm-x86/gart.h21
3 files changed, 29 insertions, 27 deletions
diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c
index c07455d1695f..bffcf455c857 100644
--- a/arch/x86/kernel/pci-gart_64.c
+++ b/arch/x86/kernel/pci-gart_64.c
@@ -598,13 +598,13 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
598 dev = k8_northbridges[i]; 598 dev = k8_northbridges[i];
599 gatt_reg = __pa(gatt) >> 12; 599 gatt_reg = __pa(gatt) >> 12;
600 gatt_reg <<= 4; 600 gatt_reg <<= 4;
601 pci_write_config_dword(dev, 0x98, gatt_reg); 601 pci_write_config_dword(dev, AMD64_GARTTABLEBASE, gatt_reg);
602 pci_read_config_dword(dev, 0x90, &ctl); 602 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
603 603
604 ctl |= 1; 604 ctl |= GARTEN;
605 ctl &= ~((1<<4) | (1<<5)); 605 ctl &= ~(DISGARTCPU | DISGARTIO);
606 606
607 pci_write_config_dword(dev, 0x90, ctl); 607 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
608 } 608 }
609 flush_gart(); 609 flush_gart();
610 610
diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c
index d8200ac8f8cb..25d64224cdbb 100644
--- a/drivers/char/agp/amd64-agp.c
+++ b/drivers/char/agp/amd64-agp.c
@@ -16,28 +16,9 @@
16#include <asm/page.h> /* PAGE_SIZE */ 16#include <asm/page.h> /* PAGE_SIZE */
17#include <asm/e820.h> 17#include <asm/e820.h>
18#include <asm/k8.h> 18#include <asm/k8.h>
19#include <asm/gart.h>
19#include "agp.h" 20#include "agp.h"
20 21
21/* PTE bits. */
22#define GPTE_VALID 1
23#define GPTE_COHERENT 2
24
25/* Aperture control register bits. */
26#define GARTEN (1<<0)
27#define DISGARTCPU (1<<4)
28#define DISGARTIO (1<<5)
29
30/* GART cache control register bits. */
31#define INVGART (1<<0)
32#define GARTPTEERR (1<<1)
33
34/* K8 On-cpu GART registers */
35#define AMD64_GARTAPERTURECTL 0x90
36#define AMD64_GARTAPERTUREBASE 0x94
37#define AMD64_GARTTABLEBASE 0x98
38#define AMD64_GARTCACHECTL 0x9c
39#define AMD64_GARTEN (1<<0)
40
41/* NVIDIA K8 registers */ 22/* NVIDIA K8 registers */
42#define NVIDIA_X86_64_0_APBASE 0x10 23#define NVIDIA_X86_64_0_APBASE 0x10
43#define NVIDIA_X86_64_1_APBASE1 0x50 24#define NVIDIA_X86_64_1_APBASE1 0x50
@@ -165,7 +146,7 @@ static int amd64_fetch_size(void)
165 * In a multiprocessor x86-64 system, this function gets 146 * In a multiprocessor x86-64 system, this function gets
166 * called once for each CPU. 147 * called once for each CPU.
167 */ 148 */
168static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table) 149static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table)
169{ 150{
170 u64 aperturebase; 151 u64 aperturebase;
171 u32 tmp; 152 u32 tmp;
@@ -181,7 +162,7 @@ static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table)
181 addr >>= 12; 162 addr >>= 12;
182 tmp = (u32) addr<<4; 163 tmp = (u32) addr<<4;
183 tmp &= ~0xf; 164 tmp &= ~0xf;
184 pci_write_config_dword (hammer, AMD64_GARTTABLEBASE, tmp); 165 pci_write_config_dword(hammer, AMD64_GARTTABLEBASE, tmp);
185 166
186 /* Enable GART translation for this hammer. */ 167 /* Enable GART translation for this hammer. */
187 pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp); 168 pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp);
diff --git a/include/asm-x86/gart.h b/include/asm-x86/gart.h
index 90958ed993fa..248e5778e928 100644
--- a/include/asm-x86/gart.h
+++ b/include/asm-x86/gart.h
@@ -5,6 +5,7 @@ extern void pci_iommu_shutdown(void);
5extern void no_iommu_init(void); 5extern void no_iommu_init(void);
6extern int force_iommu, no_iommu; 6extern int force_iommu, no_iommu;
7extern int iommu_detected; 7extern int iommu_detected;
8extern int agp_amd64_init(void);
8#ifdef CONFIG_GART_IOMMU 9#ifdef CONFIG_GART_IOMMU
9extern void gart_iommu_init(void); 10extern void gart_iommu_init(void);
10extern void gart_iommu_shutdown(void); 11extern void gart_iommu_shutdown(void);
@@ -31,4 +32,24 @@ static inline void gart_iommu_shutdown(void)
31 32
32#endif 33#endif
33 34
35/* PTE bits. */
36#define GPTE_VALID 1
37#define GPTE_COHERENT 2
38
39/* Aperture control register bits. */
40#define GARTEN (1<<0)
41#define DISGARTCPU (1<<4)
42#define DISGARTIO (1<<5)
43
44/* GART cache control register bits. */
45#define INVGART (1<<0)
46#define GARTPTEERR (1<<1)
47
48/* K8 On-cpu GART registers */
49#define AMD64_GARTAPERTURECTL 0x90
50#define AMD64_GARTAPERTUREBASE 0x94
51#define AMD64_GARTTABLEBASE 0x98
52#define AMD64_GARTCACHECTL 0x9c
53#define AMD64_GARTEN (1<<0)
54
34#endif 55#endif