diff options
author | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2008-04-02 16:48:13 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@redhat.com> | 2008-04-16 20:41:36 -0400 |
commit | e9ec2c0f4bfbe0632b22a2c0b74d5e1e96aeab66 (patch) | |
tree | e65a632498dad6f7eaf77f1d2b00aa0c237d60a5 | |
parent | 8d7c294cae6fd1474d88267810d1965f60a903af (diff) |
e1000e: Make arrays out of these Rx/Tx registers
With multiple queues coming into the code these base control
registers need to be made into arrays.
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
-rw-r--r-- | drivers/net/e1000e/82571.c | 24 | ||||
-rw-r--r-- | drivers/net/e1000e/es2lan.c | 24 | ||||
-rw-r--r-- | drivers/net/e1000e/hw.h | 10 | ||||
-rw-r--r-- | drivers/net/e1000e/ich8lan.c | 24 | ||||
-rw-r--r-- | drivers/net/e1000e/netdev.c | 16 |
5 files changed, 50 insertions, 48 deletions
diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c index 9b46a00bb5f1..85e476426b76 100644 --- a/drivers/net/e1000e/82571.c +++ b/drivers/net/e1000e/82571.c | |||
@@ -836,19 +836,19 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw) | |||
836 | ret_val = e1000_setup_link_82571(hw); | 836 | ret_val = e1000_setup_link_82571(hw); |
837 | 837 | ||
838 | /* Set the transmit descriptor write-back policy */ | 838 | /* Set the transmit descriptor write-back policy */ |
839 | reg_data = er32(TXDCTL); | 839 | reg_data = er32(TXDCTL(0)); |
840 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | | 840 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
841 | E1000_TXDCTL_FULL_TX_DESC_WB | | 841 | E1000_TXDCTL_FULL_TX_DESC_WB | |
842 | E1000_TXDCTL_COUNT_DESC; | 842 | E1000_TXDCTL_COUNT_DESC; |
843 | ew32(TXDCTL, reg_data); | 843 | ew32(TXDCTL(0), reg_data); |
844 | 844 | ||
845 | /* ...for both queues. */ | 845 | /* ...for both queues. */ |
846 | if (mac->type != e1000_82573) { | 846 | if (mac->type != e1000_82573) { |
847 | reg_data = er32(TXDCTL1); | 847 | reg_data = er32(TXDCTL(1)); |
848 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | | 848 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
849 | E1000_TXDCTL_FULL_TX_DESC_WB | | 849 | E1000_TXDCTL_FULL_TX_DESC_WB | |
850 | E1000_TXDCTL_COUNT_DESC; | 850 | E1000_TXDCTL_COUNT_DESC; |
851 | ew32(TXDCTL1, reg_data); | 851 | ew32(TXDCTL(1), reg_data); |
852 | } else { | 852 | } else { |
853 | e1000e_enable_tx_pkt_filtering(hw); | 853 | e1000e_enable_tx_pkt_filtering(hw); |
854 | reg_data = er32(GCR); | 854 | reg_data = er32(GCR); |
@@ -878,17 +878,17 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) | |||
878 | u32 reg; | 878 | u32 reg; |
879 | 879 | ||
880 | /* Transmit Descriptor Control 0 */ | 880 | /* Transmit Descriptor Control 0 */ |
881 | reg = er32(TXDCTL); | 881 | reg = er32(TXDCTL(0)); |
882 | reg |= (1 << 22); | 882 | reg |= (1 << 22); |
883 | ew32(TXDCTL, reg); | 883 | ew32(TXDCTL(0), reg); |
884 | 884 | ||
885 | /* Transmit Descriptor Control 1 */ | 885 | /* Transmit Descriptor Control 1 */ |
886 | reg = er32(TXDCTL1); | 886 | reg = er32(TXDCTL(1)); |
887 | reg |= (1 << 22); | 887 | reg |= (1 << 22); |
888 | ew32(TXDCTL1, reg); | 888 | ew32(TXDCTL(1), reg); |
889 | 889 | ||
890 | /* Transmit Arbitration Control 0 */ | 890 | /* Transmit Arbitration Control 0 */ |
891 | reg = er32(TARC0); | 891 | reg = er32(TARC(0)); |
892 | reg &= ~(0xF << 27); /* 30:27 */ | 892 | reg &= ~(0xF << 27); /* 30:27 */ |
893 | switch (hw->mac.type) { | 893 | switch (hw->mac.type) { |
894 | case e1000_82571: | 894 | case e1000_82571: |
@@ -898,10 +898,10 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) | |||
898 | default: | 898 | default: |
899 | break; | 899 | break; |
900 | } | 900 | } |
901 | ew32(TARC0, reg); | 901 | ew32(TARC(0), reg); |
902 | 902 | ||
903 | /* Transmit Arbitration Control 1 */ | 903 | /* Transmit Arbitration Control 1 */ |
904 | reg = er32(TARC1); | 904 | reg = er32(TARC(1)); |
905 | switch (hw->mac.type) { | 905 | switch (hw->mac.type) { |
906 | case e1000_82571: | 906 | case e1000_82571: |
907 | case e1000_82572: | 907 | case e1000_82572: |
@@ -911,7 +911,7 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) | |||
911 | reg &= ~(1 << 28); | 911 | reg &= ~(1 << 28); |
912 | else | 912 | else |
913 | reg |= (1 << 28); | 913 | reg |= (1 << 28); |
914 | ew32(TARC1, reg); | 914 | ew32(TARC(1), reg); |
915 | break; | 915 | break; |
916 | default: | 916 | default: |
917 | break; | 917 | break; |
diff --git a/drivers/net/e1000e/es2lan.c b/drivers/net/e1000e/es2lan.c index 2689e4b83f9b..10e17cf6485e 100644 --- a/drivers/net/e1000e/es2lan.c +++ b/drivers/net/e1000e/es2lan.c | |||
@@ -792,16 +792,16 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) | |||
792 | ret_val = e1000e_setup_link(hw); | 792 | ret_val = e1000e_setup_link(hw); |
793 | 793 | ||
794 | /* Set the transmit descriptor write-back policy */ | 794 | /* Set the transmit descriptor write-back policy */ |
795 | reg_data = er32(TXDCTL); | 795 | reg_data = er32(TXDCTL(0)); |
796 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | | 796 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
797 | E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; | 797 | E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; |
798 | ew32(TXDCTL, reg_data); | 798 | ew32(TXDCTL(0), reg_data); |
799 | 799 | ||
800 | /* ...for both queues. */ | 800 | /* ...for both queues. */ |
801 | reg_data = er32(TXDCTL1); | 801 | reg_data = er32(TXDCTL(1)); |
802 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | | 802 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
803 | E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; | 803 | E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; |
804 | ew32(TXDCTL1, reg_data); | 804 | ew32(TXDCTL(1), reg_data); |
805 | 805 | ||
806 | /* Enable retransmit on late collisions */ | 806 | /* Enable retransmit on late collisions */ |
807 | reg_data = er32(TCTL); | 807 | reg_data = er32(TCTL); |
@@ -846,29 +846,29 @@ static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) | |||
846 | u32 reg; | 846 | u32 reg; |
847 | 847 | ||
848 | /* Transmit Descriptor Control 0 */ | 848 | /* Transmit Descriptor Control 0 */ |
849 | reg = er32(TXDCTL); | 849 | reg = er32(TXDCTL(0)); |
850 | reg |= (1 << 22); | 850 | reg |= (1 << 22); |
851 | ew32(TXDCTL, reg); | 851 | ew32(TXDCTL(0), reg); |
852 | 852 | ||
853 | /* Transmit Descriptor Control 1 */ | 853 | /* Transmit Descriptor Control 1 */ |
854 | reg = er32(TXDCTL1); | 854 | reg = er32(TXDCTL(1)); |
855 | reg |= (1 << 22); | 855 | reg |= (1 << 22); |
856 | ew32(TXDCTL1, reg); | 856 | ew32(TXDCTL(1), reg); |
857 | 857 | ||
858 | /* Transmit Arbitration Control 0 */ | 858 | /* Transmit Arbitration Control 0 */ |
859 | reg = er32(TARC0); | 859 | reg = er32(TARC(0)); |
860 | reg &= ~(0xF << 27); /* 30:27 */ | 860 | reg &= ~(0xF << 27); /* 30:27 */ |
861 | if (hw->phy.media_type != e1000_media_type_copper) | 861 | if (hw->phy.media_type != e1000_media_type_copper) |
862 | reg &= ~(1 << 20); | 862 | reg &= ~(1 << 20); |
863 | ew32(TARC0, reg); | 863 | ew32(TARC(0), reg); |
864 | 864 | ||
865 | /* Transmit Arbitration Control 1 */ | 865 | /* Transmit Arbitration Control 1 */ |
866 | reg = er32(TARC1); | 866 | reg = er32(TARC(1)); |
867 | if (er32(TCTL) & E1000_TCTL_MULR) | 867 | if (er32(TCTL) & E1000_TCTL_MULR) |
868 | reg &= ~(1 << 28); | 868 | reg &= ~(1 << 28); |
869 | else | 869 | else |
870 | reg |= (1 << 28); | 870 | reg |= (1 << 28); |
871 | ew32(TARC1, reg); | 871 | ew32(TARC(1), reg); |
872 | } | 872 | } |
873 | 873 | ||
874 | /** | 874 | /** |
diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h index 0b4145a73229..53f1ac6327fa 100644 --- a/drivers/net/e1000e/hw.h +++ b/drivers/net/e1000e/hw.h | |||
@@ -93,6 +93,8 @@ enum e1e_registers { | |||
93 | E1000_RDH = 0x02810, /* Rx Descriptor Head - RW */ | 93 | E1000_RDH = 0x02810, /* Rx Descriptor Head - RW */ |
94 | E1000_RDT = 0x02818, /* Rx Descriptor Tail - RW */ | 94 | E1000_RDT = 0x02818, /* Rx Descriptor Tail - RW */ |
95 | E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */ | 95 | E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */ |
96 | E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */ | ||
97 | #define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8)) | ||
96 | E1000_RADV = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */ | 98 | E1000_RADV = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */ |
97 | 99 | ||
98 | /* Convenience macros | 100 | /* Convenience macros |
@@ -111,11 +113,11 @@ enum e1e_registers { | |||
111 | E1000_TDH = 0x03810, /* Tx Descriptor Head - RW */ | 113 | E1000_TDH = 0x03810, /* Tx Descriptor Head - RW */ |
112 | E1000_TDT = 0x03818, /* Tx Descriptor Tail - RW */ | 114 | E1000_TDT = 0x03818, /* Tx Descriptor Tail - RW */ |
113 | E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */ | 115 | E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */ |
114 | E1000_TXDCTL = 0x03828, /* Tx Descriptor Control - RW */ | 116 | E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */ |
117 | #define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8)) | ||
115 | E1000_TADV = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */ | 118 | E1000_TADV = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */ |
116 | E1000_TARC0 = 0x03840, /* Tx Arbitration Count (0) */ | 119 | E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */ |
117 | E1000_TXDCTL1 = 0x03928, /* Tx Descriptor Control (1) - RW */ | 120 | #define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8)) |
118 | E1000_TARC1 = 0x03940, /* Tx Arbitration Count (1) */ | ||
119 | E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */ | 121 | E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */ |
120 | E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */ | 122 | E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */ |
121 | E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */ | 123 | E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */ |
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index e358a773e67a..bbb51e1a83b4 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c | |||
@@ -1753,18 +1753,18 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) | |||
1753 | ret_val = e1000_setup_link_ich8lan(hw); | 1753 | ret_val = e1000_setup_link_ich8lan(hw); |
1754 | 1754 | ||
1755 | /* Set the transmit descriptor write-back policy for both queues */ | 1755 | /* Set the transmit descriptor write-back policy for both queues */ |
1756 | txdctl = er32(TXDCTL); | 1756 | txdctl = er32(TXDCTL(0)); |
1757 | txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | | 1757 | txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | |
1758 | E1000_TXDCTL_FULL_TX_DESC_WB; | 1758 | E1000_TXDCTL_FULL_TX_DESC_WB; |
1759 | txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | | 1759 | txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | |
1760 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH; | 1760 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH; |
1761 | ew32(TXDCTL, txdctl); | 1761 | ew32(TXDCTL(0), txdctl); |
1762 | txdctl = er32(TXDCTL1); | 1762 | txdctl = er32(TXDCTL(1)); |
1763 | txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | | 1763 | txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | |
1764 | E1000_TXDCTL_FULL_TX_DESC_WB; | 1764 | E1000_TXDCTL_FULL_TX_DESC_WB; |
1765 | txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | | 1765 | txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | |
1766 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH; | 1766 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH; |
1767 | ew32(TXDCTL1, txdctl); | 1767 | ew32(TXDCTL(1), txdctl); |
1768 | 1768 | ||
1769 | /* | 1769 | /* |
1770 | * ICH8 has opposite polarity of no_snoop bits. | 1770 | * ICH8 has opposite polarity of no_snoop bits. |
@@ -1807,30 +1807,30 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) | |||
1807 | ew32(CTRL_EXT, reg); | 1807 | ew32(CTRL_EXT, reg); |
1808 | 1808 | ||
1809 | /* Transmit Descriptor Control 0 */ | 1809 | /* Transmit Descriptor Control 0 */ |
1810 | reg = er32(TXDCTL); | 1810 | reg = er32(TXDCTL(0)); |
1811 | reg |= (1 << 22); | 1811 | reg |= (1 << 22); |
1812 | ew32(TXDCTL, reg); | 1812 | ew32(TXDCTL(0), reg); |
1813 | 1813 | ||
1814 | /* Transmit Descriptor Control 1 */ | 1814 | /* Transmit Descriptor Control 1 */ |
1815 | reg = er32(TXDCTL1); | 1815 | reg = er32(TXDCTL(1)); |
1816 | reg |= (1 << 22); | 1816 | reg |= (1 << 22); |
1817 | ew32(TXDCTL1, reg); | 1817 | ew32(TXDCTL(1), reg); |
1818 | 1818 | ||
1819 | /* Transmit Arbitration Control 0 */ | 1819 | /* Transmit Arbitration Control 0 */ |
1820 | reg = er32(TARC0); | 1820 | reg = er32(TARC(0)); |
1821 | if (hw->mac.type == e1000_ich8lan) | 1821 | if (hw->mac.type == e1000_ich8lan) |
1822 | reg |= (1 << 28) | (1 << 29); | 1822 | reg |= (1 << 28) | (1 << 29); |
1823 | reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); | 1823 | reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); |
1824 | ew32(TARC0, reg); | 1824 | ew32(TARC(0), reg); |
1825 | 1825 | ||
1826 | /* Transmit Arbitration Control 1 */ | 1826 | /* Transmit Arbitration Control 1 */ |
1827 | reg = er32(TARC1); | 1827 | reg = er32(TARC(1)); |
1828 | if (er32(TCTL) & E1000_TCTL_MULR) | 1828 | if (er32(TCTL) & E1000_TCTL_MULR) |
1829 | reg &= ~(1 << 28); | 1829 | reg &= ~(1 << 28); |
1830 | else | 1830 | else |
1831 | reg |= (1 << 28); | 1831 | reg |= (1 << 28); |
1832 | reg |= (1 << 24) | (1 << 26) | (1 << 30); | 1832 | reg |= (1 << 24) | (1 << 26) | (1 << 30); |
1833 | ew32(TARC1, reg); | 1833 | ew32(TARC(1), reg); |
1834 | 1834 | ||
1835 | /* Device Status */ | 1835 | /* Device Status */ |
1836 | if (hw->mac.type == e1000_ich8lan) { | 1836 | if (hw->mac.type == e1000_ich8lan) { |
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c index d70bde03619e..b8bb4fedb2ba 100644 --- a/drivers/net/e1000e/netdev.c +++ b/drivers/net/e1000e/netdev.c | |||
@@ -1639,24 +1639,24 @@ static void e1000_configure_tx(struct e1000_adapter *adapter) | |||
1639 | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); | 1639 | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); |
1640 | 1640 | ||
1641 | if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { | 1641 | if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { |
1642 | tarc = er32(TARC0); | 1642 | tarc = er32(TARC(0)); |
1643 | /* | 1643 | /* |
1644 | * set the speed mode bit, we'll clear it if we're not at | 1644 | * set the speed mode bit, we'll clear it if we're not at |
1645 | * gigabit link later | 1645 | * gigabit link later |
1646 | */ | 1646 | */ |
1647 | #define SPEED_MODE_BIT (1 << 21) | 1647 | #define SPEED_MODE_BIT (1 << 21) |
1648 | tarc |= SPEED_MODE_BIT; | 1648 | tarc |= SPEED_MODE_BIT; |
1649 | ew32(TARC0, tarc); | 1649 | ew32(TARC(0), tarc); |
1650 | } | 1650 | } |
1651 | 1651 | ||
1652 | /* errata: program both queues to unweighted RR */ | 1652 | /* errata: program both queues to unweighted RR */ |
1653 | if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { | 1653 | if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { |
1654 | tarc = er32(TARC0); | 1654 | tarc = er32(TARC(0)); |
1655 | tarc |= 1; | 1655 | tarc |= 1; |
1656 | ew32(TARC0, tarc); | 1656 | ew32(TARC(0), tarc); |
1657 | tarc = er32(TARC1); | 1657 | tarc = er32(TARC(1)); |
1658 | tarc |= 1; | 1658 | tarc |= 1; |
1659 | ew32(TARC1, tarc); | 1659 | ew32(TARC(1), tarc); |
1660 | } | 1660 | } |
1661 | 1661 | ||
1662 | e1000e_config_collision_dist(hw); | 1662 | e1000e_config_collision_dist(hw); |
@@ -2775,9 +2775,9 @@ static void e1000_watchdog_task(struct work_struct *work) | |||
2775 | if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && | 2775 | if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && |
2776 | !txb2b) { | 2776 | !txb2b) { |
2777 | u32 tarc0; | 2777 | u32 tarc0; |
2778 | tarc0 = er32(TARC0); | 2778 | tarc0 = er32(TARC(0)); |
2779 | tarc0 &= ~SPEED_MODE_BIT; | 2779 | tarc0 &= ~SPEED_MODE_BIT; |
2780 | ew32(TARC0, tarc0); | 2780 | ew32(TARC(0), tarc0); |
2781 | } | 2781 | } |
2782 | 2782 | ||
2783 | /* | 2783 | /* |