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authorArnaud Patard <arnaud.patard@rtp-net.org>2005-05-07 12:51:51 -0400
committerJaroslav Kysela <perex@suse.cz>2005-05-29 04:06:22 -0400
commita488e033861363f64ed90d01622e0c30b382b753 (patch)
treeb506a8963ccfd18870a46d5a685063e45a90c88c
parent22bc30c84b4dc092deb2b14deb0603b257818e63 (diff)
[ALSA] cs4281 - fix DLLRDY not seen problem
CS4281 driver Reset the FPDN bit of the EPPMC register if needed. Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
-rw-r--r--sound/pci/cs4281.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/sound/pci/cs4281.c b/sound/pci/cs4281.c
index 8b42e8631f2a..b6e1854e9389 100644
--- a/sound/pci/cs4281.c
+++ b/sound/pci/cs4281.c
@@ -206,7 +206,10 @@ MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
206 206
207#define BA0_PMCS 0x0344 /* Power Management Control/Status */ 207#define BA0_PMCS 0x0344 /* Power Management Control/Status */
208#define BA0_CWPR 0x03e0 /* Configuration Write Protect */ 208#define BA0_CWPR 0x03e0 /* Configuration Write Protect */
209
209#define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */ 210#define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */
211#define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */
212
210#define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */ 213#define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */
211 214
212#define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */ 215#define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */
@@ -1461,6 +1464,11 @@ static int snd_cs4281_chip_init(cs4281_t *chip)
1461 int timeout; 1464 int timeout;
1462 int retry_count = 2; 1465 int retry_count = 2;
1463 1466
1467 /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
1468 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1469 if (tmp & BA0_EPPMC_FPDN)
1470 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1471
1464 __retry: 1472 __retry:
1465 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR); 1473 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1466 if (tmp != BA0_CFLR_DEFAULT) { 1474 if (tmp != BA0_CFLR_DEFAULT) {