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authorLinus Torvalds <torvalds@linux-foundation.org>2009-03-26 14:11:23 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-03-26 14:11:23 -0400
commit928a726b0e12184729900c076e13dbf1c511c96c (patch)
treef31a7f23c1b511ebb486598cc746786e1821d48c
parent8ff64b539bfd998792614481ccb67139b97075ef (diff)
parenteaeed5d31d8ded02fa0a4b608f57418cc0e65b07 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (96 commits) sh: add support for SMSC Polaris platform sh: fix the HD64461 level-triggered interrupts handling sh: sh-rtc wakeup support sh: sh-rtc invalid time rework sh: sh-rtc carry interrupt rework sh: disallow kexec virtual entry sh: kexec jump: fix for ftrace. sh: kexec: Drop SR.BL bit toggling. sh: add kexec jump support sh: rework kexec segment code sh: simplify kexec vbr code sh: Flush only the needed range when unmapping a VMA. sh: Update debugfs ASID dumping for 16-bit ASID support. sh: tlb-pteaex: Kill off legacy PTEA updates. sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores. sh: sh7763rdp: Change IRQ number for sh_eth of sh7763rdp sh: espt-giga board support sh: dma: Make G2 DMA configurable. sh: dma: Make PVR2 DMA configurable. sh: Move IRQ multi definition of DMAC to defconfig ...
Diffstat
-rw-r--r--arch/sh/Kconfig63
-rw-r--r--arch/sh/Kconfig.cpu3
-rw-r--r--arch/sh/Makefile1
-rw-r--r--arch/sh/boards/Kconfig27
-rw-r--r--arch/sh/boards/Makefile3
-rw-r--r--arch/sh/boards/board-ap325rxa.c11
-rw-r--r--arch/sh/boards/board-espt.c102
-rw-r--r--arch/sh/boards/board-polaris.c149
-rw-r--r--arch/sh/boards/board-sh7785lcr.c13
-rw-r--r--arch/sh/boards/board-urquell.c162
-rw-r--r--arch/sh/boards/mach-highlander/Kconfig2
-rw-r--r--arch/sh/boards/mach-hp6xx/pm_wakeup.S31
-rw-r--r--arch/sh/boards/mach-hp6xx/setup.c1
-rw-r--r--arch/sh/boards/mach-migor/setup.c9
-rw-r--r--arch/sh/boards/mach-rsk/Kconfig2
-rw-r--r--arch/sh/boards/mach-sh7763rdp/setup.c10
-rw-r--r--arch/sh/boot/Makefile20
-rw-r--r--arch/sh/cchips/hd6446x/hd64461.c30
-rw-r--r--arch/sh/configs/espt_defconfig1190
-rw-r--r--arch/sh/configs/polaris_defconfig969
-rw-r--r--arch/sh/configs/sh7785lcr_32bit_defconfig1553
-rw-r--r--arch/sh/configs/urquell_defconfig1332
-rw-r--r--arch/sh/drivers/dma/Kconfig40
-rw-r--r--arch/sh/drivers/dma/Makefile3
-rw-r--r--arch/sh/drivers/dma/dma-sh.c169
-rw-r--r--arch/sh/drivers/dma/dma-sh.h75
-rw-r--r--arch/sh/drivers/pci/pci-sh7780.c4
-rw-r--r--arch/sh/include/asm/addrspace.h4
-rw-r--r--arch/sh/include/asm/atomic-irq.h16
-rw-r--r--arch/sh/include/asm/bitops-llsc.h72
-rw-r--r--arch/sh/include/asm/clock.h1
-rw-r--r--arch/sh/include/asm/cmpxchg-llsc.h38
-rw-r--r--arch/sh/include/asm/cpu-features.h1
-rw-r--r--arch/sh/include/asm/dma-sh.h118
-rw-r--r--arch/sh/include/asm/dma.h4
-rw-r--r--arch/sh/include/asm/entry-macros.S5
-rw-r--r--arch/sh/include/asm/gpio.h70
-rw-r--r--arch/sh/include/asm/hd64461.h1
-rw-r--r--arch/sh/include/asm/io.h4
-rw-r--r--arch/sh/include/asm/kprobes.h2
-rw-r--r--arch/sh/include/asm/mmu_context.h15
-rw-r--r--arch/sh/include/asm/mmu_context_32.h12
-rw-r--r--arch/sh/include/asm/page.h7
-rw-r--r--arch/sh/include/asm/processor.h2
-rw-r--r--arch/sh/include/asm/processor_32.h15
-rw-r--r--arch/sh/include/asm/processor_64.h14
-rw-r--r--arch/sh/include/asm/ptrace.h8
-rw-r--r--arch/sh/include/asm/sections.h1
-rw-r--r--arch/sh/include/asm/suspend.h22
-rw-r--r--arch/sh/include/asm/timer.h4
-rw-r--r--arch/sh/include/asm/tlb.h100
-rw-r--r--arch/sh/include/cpu-sh3/cpu/dma.h17
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma-sh4a.h94
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma-sh7780.h39
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma.h30
-rw-r--r--arch/sh/include/cpu-sh4/cpu/freq.h4
-rw-r--r--arch/sh/include/cpu-sh4/cpu/mmu_context.h35
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7786.h192
-rw-r--r--arch/sh/include/mach-common/mach/urquell.h68
-rw-r--r--arch/sh/kernel/Makefile_321
-rw-r--r--arch/sh/kernel/asm-offsets.c8
-rw-r--r--arch/sh/kernel/cpu/Makefile1
-rw-r--r--arch/sh/kernel/cpu/clock.c95
-rw-r--r--arch/sh/kernel/cpu/sh2/setup-sh7619.c34
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-mxg.c65
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7201.c224
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7203.c236
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7206.c154
-rw-r--r--arch/sh/kernel/cpu/sh3/Makefile2
-rw-r--r--arch/sh/kernel/cpu/sh3/entry.S357
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c61
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c68
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c69
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c68
-rw-r--r--arch/sh/kernel/cpu/sh3/swsusp.S147
-rw-r--r--arch/sh/kernel/cpu/sh4/Makefile1
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c7
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c87
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile3
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7786.c148
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c950
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c34
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c34
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c34
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c34
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c114
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c97
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c95
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c490
-rw-r--r--arch/sh/kernel/cpu/shmobile/Makefile6
-rw-r--r--arch/sh/kernel/cpu/shmobile/pm.c92
-rw-r--r--arch/sh/kernel/cpu/shmobile/sleep.S125
-rw-r--r--arch/sh/kernel/gpio.c338
-rw-r--r--arch/sh/kernel/irq.c2
-rw-r--r--arch/sh/kernel/machine_kexec.c74
-rw-r--r--arch/sh/kernel/relocate_kernel.S203
-rw-r--r--arch/sh/kernel/setup.c3
-rw-r--r--arch/sh/kernel/swsusp.c38
-rw-r--r--arch/sh/kernel/time_32.c71
-rw-r--r--arch/sh/kernel/timers/timer-mtu2.c3
-rw-r--r--arch/sh/kernel/timers/timer-tmu.c21
-rw-r--r--arch/sh/kernel/vmlinux_32.lds.S5
-rw-r--r--arch/sh/mm/Kconfig29
-rw-r--r--arch/sh/mm/Makefile_327
-rw-r--r--arch/sh/mm/asids-debugfs.c4
-rw-r--r--arch/sh/mm/ioremap_32.c8
-rw-r--r--arch/sh/mm/pmb-fixed.c45
-rw-r--r--arch/sh/mm/pmb.c38
-rw-r--r--arch/sh/mm/tlb-pteaex.c96
-rw-r--r--arch/sh/oprofile/common.c1
-rw-r--r--arch/sh/tools/mach-types3
-rw-r--r--drivers/clocksource/Makefile1
-rw-r--r--drivers/clocksource/sh_cmt.c615
-rw-r--r--drivers/input/joystick/maplecontrol.c4
-rw-r--r--drivers/input/keyboard/maple_keyb.c37
-rw-r--r--drivers/input/keyboard/sh_keysc.c26
-rw-r--r--drivers/mtd/maps/Kconfig12
-rw-r--r--drivers/mtd/maps/Makefile1
-rw-r--r--drivers/mtd/maps/vmu-flash.c832
-rw-r--r--drivers/rtc/rtc-sh.c246
-rw-r--r--drivers/serial/sh-sci.c12
-rw-r--r--drivers/serial/sh-sci.h15
-rw-r--r--drivers/sh/intc.c47
-rw-r--r--drivers/sh/maple/maple.c472
-rw-r--r--drivers/sh/superhyway/superhyway.c4
-rw-r--r--drivers/usb/Kconfig1
-rw-r--r--drivers/usb/host/ohci-hcd.c3
-rw-r--r--drivers/video/pvr2fb.c16
-rw-r--r--drivers/video/sh_mobile_lcdcfb.c66
-rw-r--r--include/linux/maple.h62
-rw-r--r--include/linux/sh_cmt.h13
-rw-r--r--include/linux/sh_intc.h1
-rw-r--r--sound/sh/Kconfig1
133 files changed, 12275 insertions, 2131 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index ebabe518e729..8d50d527c595 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -107,6 +107,9 @@ config SYS_SUPPORTS_NUMA
107config SYS_SUPPORTS_PCI 107config SYS_SUPPORTS_PCI
108 bool 108 bool
109 109
110config SYS_SUPPORTS_CMT
111 bool
112
110config STACKTRACE_SUPPORT 113config STACKTRACE_SUPPORT
111 def_bool y 114 def_bool y
112 115
@@ -176,6 +179,10 @@ config CPU_SHX2
176config CPU_SHX3 179config CPU_SHX3
177 bool 180 bool
178 181
182config ARCH_SHMOBILE
183 bool
184 select ARCH_SUSPEND_POSSIBLE
185
179choice 186choice
180 prompt "Processor sub-type selection" 187 prompt "Processor sub-type selection"
181 188
@@ -188,6 +195,7 @@ choice
188config CPU_SUBTYPE_SH7619 195config CPU_SUBTYPE_SH7619
189 bool "Support SH7619 processor" 196 bool "Support SH7619 processor"
190 select CPU_SH2 197 select CPU_SH2
198 select SYS_SUPPORTS_CMT
191 199
192# SH-2A Processor Support 200# SH-2A Processor Support
193 201
@@ -200,15 +208,18 @@ config CPU_SUBTYPE_SH7203
200 bool "Support SH7203 processor" 208 bool "Support SH7203 processor"
201 select CPU_SH2A 209 select CPU_SH2A
202 select CPU_HAS_FPU 210 select CPU_HAS_FPU
211 select SYS_SUPPORTS_CMT
203 212
204config CPU_SUBTYPE_SH7206 213config CPU_SUBTYPE_SH7206
205 bool "Support SH7206 processor" 214 bool "Support SH7206 processor"
206 select CPU_SH2A 215 select CPU_SH2A
216 select SYS_SUPPORTS_CMT
207 217
208config CPU_SUBTYPE_SH7263 218config CPU_SUBTYPE_SH7263
209 bool "Support SH7263 processor" 219 bool "Support SH7263 processor"
210 select CPU_SH2A 220 select CPU_SH2A
211 select CPU_HAS_FPU 221 select CPU_HAS_FPU
222 select SYS_SUPPORTS_CMT
212 223
213config CPU_SUBTYPE_MXG 224config CPU_SUBTYPE_MXG
214 bool "Support MX-G processor" 225 bool "Support MX-G processor"
@@ -323,7 +334,9 @@ config CPU_SUBTYPE_SH7723
323 bool "Support SH7723 processor" 334 bool "Support SH7723 processor"
324 select CPU_SH4A 335 select CPU_SH4A
325 select CPU_SHX2 336 select CPU_SHX2
337 select ARCH_SHMOBILE
326 select ARCH_SPARSEMEM_ENABLE 338 select ARCH_SPARSEMEM_ENABLE
339 select SYS_SUPPORTS_CMT
327 help 340 help
328 Select SH7723 if you have an SH-MobileR2 CPU. 341 Select SH7723 if you have an SH-MobileR2 CPU.
329 342
@@ -348,6 +361,14 @@ config CPU_SUBTYPE_SH7785
348 select ARCH_SPARSEMEM_ENABLE 361 select ARCH_SPARSEMEM_ENABLE
349 select SYS_SUPPORTS_NUMA 362 select SYS_SUPPORTS_NUMA
350 363
364config CPU_SUBTYPE_SH7786
365 bool "Support SH7786 processor"
366 select CPU_SH4A
367 select CPU_SHX3
368 select CPU_HAS_PTEAEX
369 select ARCH_SPARSEMEM_ENABLE
370 select SYS_SUPPORTS_NUMA
371
351config CPU_SUBTYPE_SHX3 372config CPU_SUBTYPE_SHX3
352 bool "Support SH-X3 processor" 373 bool "Support SH-X3 processor"
353 select CPU_SH4A 374 select CPU_SH4A
@@ -362,20 +383,26 @@ config CPU_SUBTYPE_SHX3
362config CPU_SUBTYPE_SH7343 383config CPU_SUBTYPE_SH7343
363 bool "Support SH7343 processor" 384 bool "Support SH7343 processor"
364 select CPU_SH4AL_DSP 385 select CPU_SH4AL_DSP
386 select ARCH_SHMOBILE
387 select SYS_SUPPORTS_CMT
365 388
366config CPU_SUBTYPE_SH7722 389config CPU_SUBTYPE_SH7722
367 bool "Support SH7722 processor" 390 bool "Support SH7722 processor"
368 select CPU_SH4AL_DSP 391 select CPU_SH4AL_DSP
369 select CPU_SHX2 392 select CPU_SHX2
393 select ARCH_SHMOBILE
370 select ARCH_SPARSEMEM_ENABLE 394 select ARCH_SPARSEMEM_ENABLE
371 select SYS_SUPPORTS_NUMA 395 select SYS_SUPPORTS_NUMA
396 select SYS_SUPPORTS_CMT
372 397
373config CPU_SUBTYPE_SH7366 398config CPU_SUBTYPE_SH7366
374 bool "Support SH7366 processor" 399 bool "Support SH7366 processor"
375 select CPU_SH4AL_DSP 400 select CPU_SH4AL_DSP
376 select CPU_SHX2 401 select CPU_SHX2
402 select ARCH_SHMOBILE
377 select ARCH_SPARSEMEM_ENABLE 403 select ARCH_SPARSEMEM_ENABLE
378 select SYS_SUPPORTS_NUMA 404 select SYS_SUPPORTS_NUMA
405 select SYS_SUPPORTS_CMT
379 406
380# SH-5 Processor Support 407# SH-5 Processor Support
381 408
@@ -398,25 +425,34 @@ source "arch/sh/boards/Kconfig"
398menu "Timer and clock configuration" 425menu "Timer and clock configuration"
399 426
400config SH_TMU 427config SH_TMU
401 def_bool y 428 bool "TMU timer support"
402 prompt "TMU timer support"
403 depends on CPU_SH3 || CPU_SH4 429 depends on CPU_SH3 || CPU_SH4
430 default y
404 select GENERIC_TIME 431 select GENERIC_TIME
405 select GENERIC_CLOCKEVENTS 432 select GENERIC_CLOCKEVENTS
406 help 433 help
407 This enables the use of the TMU as the system timer. 434 This enables the use of the TMU as the system timer.
408 435
409config SH_CMT 436config SH_CMT
410 def_bool y 437 bool "CMT timer support"
411 prompt "CMT timer support" 438 depends on SYS_SUPPORTS_CMT && CPU_SH2
412 depends on CPU_SH2 && !CPU_SUBTYPE_MXG 439 default y
413 help 440 help
414 This enables the use of the CMT as the system timer. 441 This enables the use of the CMT as the system timer.
415 442
443#
444# Support for the new-style CMT driver. This will replace SH_CMT
445# once its other dependencies are merged.
446#
447config SH_TIMER_CMT
448 bool "CMT clockevents driver"
449 depends on SYS_SUPPORTS_CMT && !SH_CMT
450 select GENERIC_CLOCKEVENTS
451
416config SH_MTU2 452config SH_MTU2
417 def_bool n 453 bool "MTU2 timer support"
418 prompt "MTU2 timer support"
419 depends on CPU_SH2A 454 depends on CPU_SH2A
455 default y
420 help 456 help
421 This enables the use of the MTU2 as the system timer. 457 This enables the use of the MTU2 as the system timer.
422 458
@@ -426,7 +462,8 @@ config SH_TIMER_IRQ
426 CPU_SUBTYPE_SH7763 462 CPU_SUBTYPE_SH7763
427 default "86" if CPU_SUBTYPE_SH7619 463 default "86" if CPU_SUBTYPE_SH7619
428 default "140" if CPU_SUBTYPE_SH7206 464 default "140" if CPU_SUBTYPE_SH7206
429 default "142" if CPU_SUBTYPE_SH7203 465 default "142" if CPU_SUBTYPE_SH7203 && SH_CMT
466 default "153" if CPU_SUBTYPE_SH7203 && SH_MTU2
430 default "238" if CPU_SUBTYPE_MXG 467 default "238" if CPU_SUBTYPE_MXG
431 default "16" 468 default "16"
432 469
@@ -438,7 +475,8 @@ config SH_PCLK_FREQ
438 default "33333333" if CPU_SUBTYPE_SH7770 || CPU_SUBTYPE_SH7723 || \ 475 default "33333333" if CPU_SUBTYPE_SH7770 || CPU_SUBTYPE_SH7723 || \
439 CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \ 476 CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \
440 CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \ 477 CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \
441 CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG 478 CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG || \
479 CPU_SUBTYPE_SH7786
442 default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R 480 default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
443 default "66000000" if CPU_SUBTYPE_SH4_202 481 default "66000000" if CPU_SUBTYPE_SH4_202
444 default "50000000" 482 default "50000000"
@@ -521,6 +559,13 @@ config CRASH_DUMP
521 559
522 For more details see Documentation/kdump/kdump.txt 560 For more details see Documentation/kdump/kdump.txt
523 561
562config KEXEC_JUMP
563 bool "kexec jump (EXPERIMENTAL)"
564 depends on SUPERH32 && KEXEC && HIBERNATION && EXPERIMENTAL
565 help
566 Jump between original kernel and kexeced kernel and invoke
567 code via KEXEC
568
524config SECCOMP 569config SECCOMP
525 bool "Enable seccomp to safely compute untrusted bytecode" 570 bool "Enable seccomp to safely compute untrusted bytecode"
526 depends on PROC_FS 571 depends on PROC_FS
diff --git a/arch/sh/Kconfig.cpu b/arch/sh/Kconfig.cpu
index 0e27fe3b182b..c7d704381a6d 100644
--- a/arch/sh/Kconfig.cpu
+++ b/arch/sh/Kconfig.cpu
@@ -104,6 +104,9 @@ config CPU_HAS_SR_RB
104config CPU_HAS_PTEA 104config CPU_HAS_PTEA
105 bool 105 bool
106 106
107config CPU_HAS_PTEAEX
108 bool
109
107config CPU_HAS_DSP 110config CPU_HAS_DSP
108 bool 111 bool
109 112
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index 4067b0d9287b..bece1f7535f2 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -80,6 +80,7 @@ OBJCOPYFLAGS := -O binary -R .note -R .note.gnu.build-id -R .comment \
80defaultimage-$(CONFIG_SUPERH32) := zImage 80defaultimage-$(CONFIG_SUPERH32) := zImage
81defaultimage-$(CONFIG_SH_SH7785LCR) := uImage 81defaultimage-$(CONFIG_SH_SH7785LCR) := uImage
82defaultimage-$(CONFIG_SH_RSK) := uImage 82defaultimage-$(CONFIG_SH_RSK) := uImage
83defaultimage-$(CONFIG_SH_URQUELL) := uImage
83defaultimage-$(CONFIG_SH_7206_SOLUTION_ENGINE) := vmlinux 84defaultimage-$(CONFIG_SH_7206_SOLUTION_ENGINE) := vmlinux
84defaultimage-$(CONFIG_SH_7619_SOLUTION_ENGINE) := vmlinux 85defaultimage-$(CONFIG_SH_7619_SOLUTION_ENGINE) := vmlinux
85 86
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
index 861914747e4e..dcc1af8a2cfe 100644
--- a/arch/sh/boards/Kconfig
+++ b/arch/sh/boards/Kconfig
@@ -155,17 +155,22 @@ config SH_SH7785LCR
155 155
156config SH_SH7785LCR_29BIT_PHYSMAPS 156config SH_SH7785LCR_29BIT_PHYSMAPS
157 bool "SH7785LCR 29bit physmaps" 157 bool "SH7785LCR 29bit physmaps"
158 depends on SH_SH7785LCR 158 depends on SH_SH7785LCR && 29BIT
159 default y 159 default y
160 help 160 help
161 This board has 2 physical memory maps. It can be changed with 161 This board has 2 physical memory maps. It can be changed with
162 DIP switch(S2-5). If you set the DIP switch for S2-5 = ON, 162 DIP switch(S2-5). If you set the DIP switch for S2-5 = ON,
163 you can access all on-board device in 29bit address mode. 163 you can access all on-board device in 29bit address mode.
164 164
165config SH_URQUELL
166 bool "Urquell"
167 depends on CPU_SUBTYPE_SH7786
168 select ARCH_REQUIRE_GPIOLIB
169
165config SH_MIGOR 170config SH_MIGOR
166 bool "Migo-R" 171 bool "Migo-R"
167 depends on CPU_SUBTYPE_SH7722 172 depends on CPU_SUBTYPE_SH7722
168 select GENERIC_GPIO 173 select ARCH_REQUIRE_GPIOLIB
169 help 174 help
170 Select Migo-R if configuring for the SH7722 Migo-R platform 175 Select Migo-R if configuring for the SH7722 Migo-R platform
171 by Renesas System Solutions Asia Pte. Ltd. 176 by Renesas System Solutions Asia Pte. Ltd.
@@ -173,7 +178,7 @@ config SH_MIGOR
173config SH_AP325RXA 178config SH_AP325RXA
174 bool "AP-325RXA" 179 bool "AP-325RXA"
175 depends on CPU_SUBTYPE_SH7723 180 depends on CPU_SUBTYPE_SH7723
176 select GENERIC_GPIO 181 select ARCH_REQUIRE_GPIOLIB
177 help 182 help
178 Renesas "AP-325RXA" support. 183 Renesas "AP-325RXA" support.
179 Compatible with ALGO SYSTEM CO.,LTD. "AP-320A" 184 Compatible with ALGO SYSTEM CO.,LTD. "AP-320A"
@@ -185,6 +190,13 @@ config SH_SH7763RDP
185 Select SH7763RDP if configuring for a Renesas SH7763 190 Select SH7763RDP if configuring for a Renesas SH7763
186 evaluation board. 191 evaluation board.
187 192
193config SH_ESPT
194 bool "ESPT"
195 depends on CPU_SUBTYPE_SH7763
196 help
197 Select ESPT if configuring for a Renesas SH7763
198 with gigabit ether evaluation board.
199
188config SH_EDOSK7705 200config SH_EDOSK7705
189 bool "EDOSK7705" 201 bool "EDOSK7705"
190 depends on CPU_SUBTYPE_SH7705 202 depends on CPU_SUBTYPE_SH7705
@@ -240,7 +252,7 @@ config SH_X3PROTO
240config SH_MAGIC_PANEL_R2 252config SH_MAGIC_PANEL_R2
241 bool "Magic Panel R2" 253 bool "Magic Panel R2"
242 depends on CPU_SUBTYPE_SH7720 254 depends on CPU_SUBTYPE_SH7720
243 select GENERIC_GPIO 255 select ARCH_REQUIRE_GPIOLIB
244 help 256 help
245 Select Magic Panel R2 if configuring for Magic Panel R2. 257 Select Magic Panel R2 if configuring for Magic Panel R2.
246 258
@@ -249,6 +261,13 @@ config SH_CAYMAN
249 depends on CPU_SUBTYPE_SH5_101 || CPU_SUBTYPE_SH5_103 261 depends on CPU_SUBTYPE_SH5_101 || CPU_SUBTYPE_SH5_103
250 select SYS_SUPPORTS_PCI 262 select SYS_SUPPORTS_PCI
251 263
264config SH_POLARIS
265 bool "SMSC Polaris"
266 select CPU_HAS_IPR_IRQ
267 depends on CPU_SUBTYPE_SH7709
268 help
269 Select if configuring for an SMSC Polaris development board
270
252endmenu 271endmenu
253 272
254source "arch/sh/boards/mach-r2d/Kconfig" 273source "arch/sh/boards/mach-r2d/Kconfig"
diff --git a/arch/sh/boards/Makefile b/arch/sh/boards/Makefile
index 269ae2be49ef..7baa21090231 100644
--- a/arch/sh/boards/Makefile
+++ b/arch/sh/boards/Makefile
@@ -4,5 +4,8 @@
4obj-$(CONFIG_SH_AP325RXA) += board-ap325rxa.o 4obj-$(CONFIG_SH_AP325RXA) += board-ap325rxa.o
5obj-$(CONFIG_SH_MAGIC_PANEL_R2) += board-magicpanelr2.o 5obj-$(CONFIG_SH_MAGIC_PANEL_R2) += board-magicpanelr2.o
6obj-$(CONFIG_SH_SH7785LCR) += board-sh7785lcr.o 6obj-$(CONFIG_SH_SH7785LCR) += board-sh7785lcr.o
7obj-$(CONFIG_SH_URQUELL) += board-urquell.o
7obj-$(CONFIG_SH_SHMIN) += board-shmin.o 8obj-$(CONFIG_SH_SHMIN) += board-shmin.o
8obj-$(CONFIG_SH_EDOSK7760) += board-edosk7760.o 9obj-$(CONFIG_SH_EDOSK7760) += board-edosk7760.o
10obj-$(CONFIG_SH_ESPT) += board-espt.o
11obj-$(CONFIG_SH_POLARIS) += board-polaris.o
diff --git a/arch/sh/boards/board-ap325rxa.c b/arch/sh/boards/board-ap325rxa.c
index 15b6d450fbf0..a64e38841c49 100644
--- a/arch/sh/boards/board-ap325rxa.c
+++ b/arch/sh/boards/board-ap325rxa.c
@@ -166,6 +166,16 @@ static void ap320_wvga_power_on(void *board_data)
166 ctrl_outw(0x100, FPGA_BKLREG); 166 ctrl_outw(0x100, FPGA_BKLREG);
167} 167}
168 168
169static void ap320_wvga_power_off(void *board_data)
170{
171 /* backlight */
172 ctrl_outw(0, FPGA_BKLREG);
173 gpio_set_value(GPIO_PTS3, 1);
174
175 /* ASD AP-320/325 LCD OFF */
176 ctrl_outw(0, FPGA_LCDREG);
177}
178
169static struct sh_mobile_lcdc_info lcdc_info = { 179static struct sh_mobile_lcdc_info lcdc_info = {
170 .clock_source = LCDC_CLK_EXTERNAL, 180 .clock_source = LCDC_CLK_EXTERNAL,
171 .ch[0] = { 181 .ch[0] = {
@@ -191,6 +201,7 @@ static struct sh_mobile_lcdc_info lcdc_info = {
191 }, 201 },
192 .board_cfg = { 202 .board_cfg = {
193 .display_on = ap320_wvga_power_on, 203 .display_on = ap320_wvga_power_on,
204 .display_off = ap320_wvga_power_off,
194 }, 205 },
195 } 206 }
196}; 207};
diff --git a/arch/sh/boards/board-espt.c b/arch/sh/boards/board-espt.c
new file mode 100644
index 000000000000..d5ce5e18eb37
--- /dev/null
+++ b/arch/sh/boards/board-espt.c
@@ -0,0 +1,102 @@
1/*
2 * Data Technology Inc. ESPT-GIGA board suport
3 *
4 * Copyright (C) 2008, 2009 Renesas Solutions Corp.
5 * Copyright (C) 2008, 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/init.h>
12#include <linux/platform_device.h>
13#include <linux/interrupt.h>
14#include <linux/mtd/physmap.h>
15#include <linux/io.h>
16#include <asm/machvec.h>
17#include <asm/sizes.h>
18#include <asm/sh_eth.h>
19
20/* NOR Flash */
21static struct mtd_partition espt_nor_flash_partitions[] = {
22 {
23 .name = "U-Boot",
24 .offset = 0,
25 .size = (2 * SZ_128K),
26 .mask_flags = MTD_WRITEABLE, /* Read-only */
27 }, {
28 .name = "Linux-Kernel",
29 .offset = MTDPART_OFS_APPEND,
30 .size = (20 * SZ_128K),
31 }, {
32 .name = "Root Filesystem",
33 .offset = MTDPART_OFS_APPEND,
34 .size = MTDPART_SIZ_FULL,
35 },
36};
37
38static struct physmap_flash_data espt_nor_flash_data = {
39 .width = 2,
40 .parts = espt_nor_flash_partitions,
41 .nr_parts = ARRAY_SIZE(espt_nor_flash_partitions),
42};
43
44static struct resource espt_nor_flash_resources[] = {
45 [0] = {
46 .name = "NOR Flash",
47 .start = 0,
48 .end = SZ_8M - 1,
49 .flags = IORESOURCE_MEM,
50 },
51};
52
53static struct platform_device espt_nor_flash_device = {
54 .name = "physmap-flash",
55 .resource = espt_nor_flash_resources,
56 .num_resources = ARRAY_SIZE(espt_nor_flash_resources),
57 .dev = {
58 .platform_data = &espt_nor_flash_data,
59 },
60};
61
62/* SH-Ether */
63static struct resource sh_eth_resources[] = {
64 {
65 .start = 0xFEE00800, /* use eth1 */
66 .end = 0xFEE00F7C - 1,
67 .flags = IORESOURCE_MEM,
68 }, {
69 .start = 57, /* irq number */
70 .flags = IORESOURCE_IRQ,
71 },
72};
73
74static struct sh_eth_plat_data sh7763_eth_pdata = {
75 .phy = 0,
76 .edmac_endian = EDMAC_LITTLE_ENDIAN,
77};
78
79static struct platform_device espt_eth_device = {
80 .name = "sh-eth",
81 .resource = sh_eth_resources,
82 .num_resources = ARRAY_SIZE(sh_eth_resources),
83 .dev = {
84 .platform_data = &sh7763_eth_pdata,
85 },
86};
87
88static struct platform_device *espt_devices[] __initdata = {
89 &espt_nor_flash_device,
90 &espt_eth_device,
91};
92
93static int __init espt_devices_setup(void)
94{
95 return platform_add_devices(espt_devices,
96 ARRAY_SIZE(espt_devices));
97}
98device_initcall(espt_devices_setup);
99
100static struct sh_machine_vector mv_espt __initmv = {
101 .mv_name = "ESPT-GIGA",
102};
diff --git a/arch/sh/boards/board-polaris.c b/arch/sh/boards/board-polaris.c
new file mode 100644
index 000000000000..62607eb51004
--- /dev/null
+++ b/arch/sh/boards/board-polaris.c
@@ -0,0 +1,149 @@
1/*
2 * June 2006 steve.glendinning@smsc.com
3 *
4 * Polaris-specific resource declaration
5 *
6 */
7
8#include <linux/init.h>
9#include <linux/interrupt.h>
10#include <linux/irq.h>
11#include <linux/platform_device.h>
12#include <linux/smsc911x.h>
13#include <linux/io.h>
14#include <asm/irq.h>
15#include <asm/machvec.h>
16#include <asm/heartbeat.h>
17#include <cpu/gpio.h>
18#include <mach-se/mach/se.h>
19
20#define BCR2 (0xFFFFFF62)
21#define WCR2 (0xFFFFFF66)
22#define AREA5_WAIT_CTRL (0x1C00)
23#define WAIT_STATES_10 (0x7)
24
25static struct resource smsc911x_resources[] = {
26 [0] = {
27 .name = "smsc911x-memory",
28 .start = PA_EXT5,
29 .end = PA_EXT5 + 0x1fff,
30 .flags = IORESOURCE_MEM,
31 },
32 [1] = {
33 .name = "smsc911x-irq",
34 .start = IRQ0_IRQ,
35 .end = IRQ0_IRQ,
36 .flags = IORESOURCE_IRQ,
37 },
38};
39
40static struct smsc911x_platform_config smsc911x_config = {
41 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
42 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
43 .flags = SMSC911X_USE_32BIT,
44 .phy_interface = PHY_INTERFACE_MODE_MII,
45};
46
47static struct platform_device smsc911x_device = {
48 .name = "smsc911x",
49 .id = 0,
50 .num_resources = ARRAY_SIZE(smsc911x_resources),
51 .resource = smsc911x_resources,
52 .dev = {
53 .platform_data = &smsc911x_config,
54 },
55};
56
57static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
58
59static struct heartbeat_data heartbeat_data = {
60 .bit_pos = heartbeat_bit_pos,
61 .nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
62 .regsize = 8,
63};
64
65static struct resource heartbeat_resources[] = {
66 [0] = {
67 .start = PORT_PCDR,
68 .end = PORT_PCDR,
69 .flags = IORESOURCE_MEM,
70 },
71};
72
73static struct platform_device heartbeat_device = {
74 .name = "heartbeat",
75 .id = -1,
76 .dev = {
77 .platform_data = &heartbeat_data,
78 },
79 .num_resources = ARRAY_SIZE(heartbeat_resources),
80 .resource = heartbeat_resources,
81};
82
83static struct platform_device *polaris_devices[] __initdata = {
84 &smsc911x_device,
85 &heartbeat_device,
86};
87
88static int __init polaris_initialise(void)
89{
90 u16 wcr, bcr_mask;
91
92 printk(KERN_INFO "Configuring Polaris external bus\n");
93
94 /* Configure area 5 with 2 wait states */
95 wcr = ctrl_inw(WCR2);
96 wcr &= (~AREA5_WAIT_CTRL);
97 wcr |= (WAIT_STATES_10 << 10);
98 ctrl_outw(wcr, WCR2);
99
100 /* Configure area 5 for 32-bit access */
101 bcr_mask = ctrl_inw(BCR2);
102 bcr_mask |= 1 << 10;
103 ctrl_outw(bcr_mask, BCR2);
104
105 return platform_add_devices(polaris_devices,
106 ARRAY_SIZE(polaris_devices));
107}
108arch_initcall(polaris_initialise);
109
110static struct ipr_data ipr_irq_table[] = {
111 /* External IRQs */
112 { IRQ0_IRQ, 0, 0, 1, }, /* IRQ0 */
113 { IRQ1_IRQ, 0, 4, 1, }, /* IRQ1 */
114};
115
116static unsigned long ipr_offsets[] = {
117 INTC_IPRC
118};
119
120static struct ipr_desc ipr_irq_desc = {
121 .ipr_offsets = ipr_offsets,
122 .nr_offsets = ARRAY_SIZE(ipr_offsets),
123
124 .ipr_data = ipr_irq_table,
125 .nr_irqs = ARRAY_SIZE(ipr_irq_table),
126 .chip = {
127 .name = "sh7709-ext",
128 },
129};
130
131static void __init init_polaris_irq(void)
132{
133 /* Disable all interrupts */
134 ctrl_outw(0, BCR_ILCRA);
135 ctrl_outw(0, BCR_ILCRB);
136 ctrl_outw(0, BCR_ILCRC);
137 ctrl_outw(0, BCR_ILCRD);
138 ctrl_outw(0, BCR_ILCRE);
139 ctrl_outw(0, BCR_ILCRF);
140 ctrl_outw(0, BCR_ILCRG);
141
142 register_ipr_controller(&ipr_irq_desc);
143}
144
145static struct sh_machine_vector mv_polaris __initmv = {
146 .mv_name = "Polaris",
147 .mv_nr_irqs = 61,
148 .mv_init_irq = init_polaris_irq,
149};
diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c
index 38a64968d7bf..94c0296bc35d 100644
--- a/arch/sh/boards/board-sh7785lcr.c
+++ b/arch/sh/boards/board-sh7785lcr.c
@@ -275,7 +275,18 @@ void __init init_sh7785lcr_IRQ(void)
275 275
276static void sh7785lcr_power_off(void) 276static void sh7785lcr_power_off(void)
277{ 277{
278 ctrl_outb(0x01, P2SEGADDR(PLD_POFCR)); 278 unsigned char *p;
279
280 p = ioremap(PLD_POFCR, PLD_POFCR + 1);
281 if (!p) {
282 printk(KERN_ERR "%s: ioremap error.\n", __func__);
283 return;
284 }
285 *p = 0x01;
286 iounmap(p);
287 set_bl_bit();
288 while (1)
289 cpu_relax();
279} 290}
280 291
281/* Initialize the board */ 292/* Initialize the board */
diff --git a/arch/sh/boards/board-urquell.c b/arch/sh/boards/board-urquell.c
new file mode 100644
index 000000000000..17036ce20086
--- /dev/null
+++ b/arch/sh/boards/board-urquell.c
@@ -0,0 +1,162 @@
1/*
2 * Renesas Technology Corp. SH7786 Urquell Support.
3 *
4 * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/init.h>
12#include <linux/platform_device.h>
13#include <linux/fb.h>
14#include <linux/smc91x.h>
15#include <linux/mtd/physmap.h>
16#include <linux/delay.h>
17#include <linux/gpio.h>
18#include <linux/irq.h>
19#include <mach/urquell.h>
20#include <cpu/sh7786.h>
21#include <asm/heartbeat.h>
22#include <asm/sizes.h>
23
24static struct resource heartbeat_resources[] = {
25 [0] = {
26 .start = BOARDREG(SLEDR),
27 .end = BOARDREG(SLEDR),
28 .flags = IORESOURCE_MEM,
29 },
30};
31
32static struct heartbeat_data heartbeat_data = {
33 .regsize = 16,
34};
35
36static struct platform_device heartbeat_device = {
37 .name = "heartbeat",
38 .id = -1,
39 .dev = {
40 .platform_data = &heartbeat_data,
41 },
42 .num_resources = ARRAY_SIZE(heartbeat_resources),
43 .resource = heartbeat_resources,
44};
45
46static struct smc91x_platdata smc91x_info = {
47 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
48};
49
50static struct resource smc91x_eth_resources[] = {
51 [0] = {
52 .name = "SMC91C111" ,
53 .start = 0x05800300,
54 .end = 0x0580030f,
55 .flags = IORESOURCE_MEM,
56 },
57 [1] = {
58 .start = 11,
59 .flags = IORESOURCE_IRQ,
60 },
61};
62
63static struct platform_device smc91x_eth_device = {
64 .name = "smc91x",
65 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
66 .resource = smc91x_eth_resources,
67 .dev = {
68 .platform_data = &smc91x_info,
69 },
70};
71
72static struct mtd_partition nor_flash_partitions[] = {
73 {
74 .name = "loader",
75 .offset = 0x00000000,
76 .size = SZ_512K,
77 .mask_flags = MTD_WRITEABLE, /* Read-only */
78 },
79 {
80 .name = "bootenv",
81 .offset = MTDPART_OFS_APPEND,
82 .size = SZ_512K,
83 .mask_flags = MTD_WRITEABLE, /* Read-only */
84 },
85 {
86 .name = "kernel",
87 .offset = MTDPART_OFS_APPEND,
88 .size = SZ_4M,
89 },
90 {
91 .name = "data",
92 .offset = MTDPART_OFS_APPEND,
93 .size = MTDPART_SIZ_FULL,
94 },
95};
96
97static struct physmap_flash_data nor_flash_data = {
98 .width = 2,
99 .parts = nor_flash_partitions,
100 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
101};
102
103static struct resource nor_flash_resources[] = {
104 [0] = {
105 .start = NOR_FLASH_ADDR,
106 .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
107 .flags = IORESOURCE_MEM,
108 }
109};
110
111static struct platform_device nor_flash_device = {
112 .name = "physmap-flash",
113 .dev = {
114 .platform_data = &nor_flash_data,
115 },
116 .num_resources = ARRAY_SIZE(nor_flash_resources),
117 .resource = nor_flash_resources,
118};
119
120static struct platform_device *urquell_devices[] __initdata = {
121 &heartbeat_device,
122 &smc91x_eth_device,
123 &nor_flash_device,
124};
125
126static int __init urquell_devices_setup(void)
127{
128 /* USB */
129 gpio_request(GPIO_FN_USB_OVC0, NULL);
130 gpio_request(GPIO_FN_USB_PENC0, NULL);
131
132 return platform_add_devices(urquell_devices,
133 ARRAY_SIZE(urquell_devices));
134}
135device_initcall(urquell_devices_setup);
136
137static void urquell_power_off(void)
138{
139 __raw_writew(0xa5a5, UBOARDREG(SRSTR));
140}
141
142static void __init urquell_init_irq(void)
143{
144 plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK);
145}
146
147/* Initialize the board */
148static void __init urquell_setup(char **cmdline_p)
149{
150 printk(KERN_INFO "Renesas Technology Corp. Urquell support.\n");
151
152 pm_power_off = urquell_power_off;
153}
154
155/*
156 * The Machine Vector
157 */
158static struct sh_machine_vector mv_urquell __initmv = {
159 .mv_name = "Urquell",
160 .mv_setup = urquell_setup,
161 .mv_init_irq = urquell_init_irq,
162};
diff --git a/arch/sh/boards/mach-highlander/Kconfig b/arch/sh/boards/mach-highlander/Kconfig
index 08057f62687b..def49cc0a7b9 100644
--- a/arch/sh/boards/mach-highlander/Kconfig
+++ b/arch/sh/boards/mach-highlander/Kconfig
@@ -18,7 +18,7 @@ config SH_R7780MP
18config SH_R7785RP 18config SH_R7785RP
19 bool "R7785RP board support" 19 bool "R7785RP board support"
20 depends on CPU_SUBTYPE_SH7785 20 depends on CPU_SUBTYPE_SH7785
21 select GENERIC_GPIO 21 select ARCH_REQUIRE_GPIOLIB
22 22
23endchoice 23endchoice
24 24
diff --git a/arch/sh/boards/mach-hp6xx/pm_wakeup.S b/arch/sh/boards/mach-hp6xx/pm_wakeup.S
index 44b648cf6f23..4f18d44e0541 100644
--- a/arch/sh/boards/mach-hp6xx/pm_wakeup.S
+++ b/arch/sh/boards/mach-hp6xx/pm_wakeup.S
@@ -10,47 +10,32 @@
10#include <linux/linkage.h> 10#include <linux/linkage.h>
11#include <cpu/mmu_context.h> 11#include <cpu/mmu_context.h>
12 12
13#define k0 r0
14#define k1 r1
15#define k2 r2
16#define k3 r3
17#define k4 r4
18
19/* 13/*
20 * Kernel mode register usage: 14 * Kernel mode register usage:
21 * k0 scratch 15 * k0 scratch
22 * k1 scratch 16 * k1 scratch
23 * k2 scratch (Exception code) 17 * For more details, please have a look at entry.S
24 * k3 scratch (Return address)
25 * k4 scratch
26 * k5 reserved
27 * k6 Global Interrupt Mask (0--15 << 4)
28 * k7 CURRENT_THREAD_INFO (pointer to current thread info)
29 */ 18 */
30 19
20#define k0 r0
21#define k1 r1
22
31ENTRY(wakeup_start) 23ENTRY(wakeup_start)
32! clear STBY bit 24! clear STBY bit
33 mov #-126, k2 25 mov #-126, k1
34 and #127, k0 26 and #127, k0
35 mov.b k0, @k2 27 mov.b k0, @k1
36! enable refresh 28! enable refresh
37 mov.l 5f, k1 29 mov.l 5f, k1
38 mov.w 6f, k0 30 mov.w 6f, k0
39 mov.w k0, @k1 31 mov.w k0, @k1
40! jump to handler 32! jump to handler
41 mov.l 2f, k2
42 mov.l 3f, k3
43 mov.l @k2, k2
44
45 mov.l 4f, k1 33 mov.l 4f, k1
46 jmp @k1 34 jmp @k1
47 nop 35 nop
48 36
49 .align 2 37 .align 2
501: .long EXPEVT 384: .long handle_interrupt
512: .long INTEVT
523: .long ret_from_irq
534: .long handle_exception
545: .long 0xffffff68 395: .long 0xffffff68
556: .word 0x0524 406: .word 0x0524
56 41
diff --git a/arch/sh/boards/mach-hp6xx/setup.c b/arch/sh/boards/mach-hp6xx/setup.c
index 746742bdc014..8f305b36358b 100644
--- a/arch/sh/boards/mach-hp6xx/setup.c
+++ b/arch/sh/boards/mach-hp6xx/setup.c
@@ -115,7 +115,6 @@ static struct sh_machine_vector mv_hp6xx __initmv = {
115 .mv_setup = hp6xx_setup, 115 .mv_setup = hp6xx_setup,
116 /* IRQ's : CPU(64) + CCHIP(16) + FREE_TO_USE(6) */ 116 /* IRQ's : CPU(64) + CCHIP(16) + FREE_TO_USE(6) */
117 .mv_nr_irqs = HD64461_IRQBASE + HD64461_IRQ_NUM + 6, 117 .mv_nr_irqs = HD64461_IRQBASE + HD64461_IRQ_NUM + 6,
118 .mv_irq_demux = hd64461_irq_demux,
119 /* Enable IRQ0 -> IRQ3 in IRQ_MODE */ 118 /* Enable IRQ0 -> IRQ3 in IRQ_MODE */
120 .mv_init_irq = hp6xx_init_irq, 119 .mv_init_irq = hp6xx_init_irq,
121}; 120};
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c
index 28e56c5809a2..bc35b4cae6b3 100644
--- a/arch/sh/boards/mach-migor/setup.c
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -450,6 +450,14 @@ static struct spi_board_info migor_spi_devices[] = {
450 450
451static int __init migor_devices_setup(void) 451static int __init migor_devices_setup(void)
452{ 452{
453
454#ifdef CONFIG_PM
455 /* Let D11 LED show STATUS0 */
456 gpio_request(GPIO_FN_STATUS0, NULL);
457
458 /* Lit D12 LED show PDSTATUS */
459 gpio_request(GPIO_FN_PDSTATUS, NULL);
460#else
453 /* Lit D11 LED */ 461 /* Lit D11 LED */
454 gpio_request(GPIO_PTJ7, NULL); 462 gpio_request(GPIO_PTJ7, NULL);
455 gpio_direction_output(GPIO_PTJ7, 1); 463 gpio_direction_output(GPIO_PTJ7, 1);
@@ -459,6 +467,7 @@ static int __init migor_devices_setup(void)
459 gpio_request(GPIO_PTJ5, NULL); 467 gpio_request(GPIO_PTJ5, NULL);
460 gpio_direction_output(GPIO_PTJ5, 1); 468 gpio_direction_output(GPIO_PTJ5, 1);
461 gpio_export(GPIO_PTJ5, 0); 469 gpio_export(GPIO_PTJ5, 0);
470#endif
462 471
463 /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */ 472 /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
464 gpio_request(GPIO_FN_IRQ0, NULL); 473 gpio_request(GPIO_FN_IRQ0, NULL);
diff --git a/arch/sh/boards/mach-rsk/Kconfig b/arch/sh/boards/mach-rsk/Kconfig
index bff095dffc02..aeff3b042205 100644
--- a/arch/sh/boards/mach-rsk/Kconfig
+++ b/arch/sh/boards/mach-rsk/Kconfig
@@ -10,7 +10,7 @@ config SH_RSK7201
10 10
11config SH_RSK7203 11config SH_RSK7203
12 bool "RSK7203" 12 bool "RSK7203"
13 select GENERIC_GPIO 13 select ARCH_REQUIRE_GPIOLIB
14 depends on CPU_SUBTYPE_SH7203 14 depends on CPU_SUBTYPE_SH7203
15 15
16endchoice 16endchoice
diff --git a/arch/sh/boards/mach-sh7763rdp/setup.c b/arch/sh/boards/mach-sh7763rdp/setup.c
index 6f926fd2162b..390534a0b35c 100644
--- a/arch/sh/boards/mach-sh7763rdp/setup.c
+++ b/arch/sh/boards/mach-sh7763rdp/setup.c
@@ -63,15 +63,19 @@ static struct platform_device sh7763rdp_nor_flash_device = {
63 }, 63 },
64}; 64};
65 65
66/* SH-Ether */ 66/*
67 * SH-Ether
68 *
69 * SH Ether of SH7763 has multi IRQ handling.
70 * (57,58,59 -> 57)
71 */
67static struct resource sh_eth_resources[] = { 72static struct resource sh_eth_resources[] = {
68 { 73 {
69 .start = 0xFEE00800, /* use eth1 */ 74 .start = 0xFEE00800, /* use eth1 */
70 .end = 0xFEE00F7C - 1, 75 .end = 0xFEE00F7C - 1,
71 .flags = IORESOURCE_MEM, 76 .flags = IORESOURCE_MEM,
72 }, { 77 }, {
73 .start = 58, /* irq number */ 78 .start = 57, /* irq number */
74 .end = 58,
75 .flags = IORESOURCE_IRQ, 79 .flags = IORESOURCE_IRQ,
76 }, 80 },
77}; 81};
diff --git a/arch/sh/boot/Makefile b/arch/sh/boot/Makefile
index c16ccd4bfa16..95483d161258 100644
--- a/arch/sh/boot/Makefile
+++ b/arch/sh/boot/Makefile
@@ -33,20 +33,24 @@ $(obj)/zImage: $(obj)/compressed/vmlinux FORCE
33$(obj)/compressed/vmlinux: FORCE 33$(obj)/compressed/vmlinux: FORCE
34 $(Q)$(MAKE) $(build)=$(obj)/compressed $@ 34 $(Q)$(MAKE) $(build)=$(obj)/compressed $@
35 35
36ifeq ($(CONFIG_32BIT),y) 36KERNEL_MEMORY := 0x00000000
37KERNEL_LOAD := $(shell /bin/bash -c 'printf "0x%08x" \ 37ifeq ($(CONFIG_PMB_FIXED),y)
38 $$[$(CONFIG_PAGE_OFFSET) + \ 38KERNEL_MEMORY := $(shell /bin/bash -c 'printf "0x%08x" \
39 $(CONFIG_ZERO_PAGE_OFFSET)]') 39 $$[$(CONFIG_MEMORY_START) & 0x1fffffff]')
40else 40endif
41ifeq ($(CONFIG_29BIT),y)
42KERNEL_MEMORY := $(shell /bin/bash -c 'printf "0x%08x" \
43 $$[$(CONFIG_MEMORY_START)]')
44endif
45
41KERNEL_LOAD := $(shell /bin/bash -c 'printf "0x%08x" \ 46KERNEL_LOAD := $(shell /bin/bash -c 'printf "0x%08x" \
42 $$[$(CONFIG_PAGE_OFFSET) + \ 47 $$[$(CONFIG_PAGE_OFFSET) + \
43 $(CONFIG_MEMORY_START) + \ 48 $(KERNEL_MEMORY) + \
44 $(CONFIG_ZERO_PAGE_OFFSET)]') 49 $(CONFIG_ZERO_PAGE_OFFSET)]')
45endif
46 50
47KERNEL_ENTRY := $(shell /bin/bash -c 'printf "0x%08x" \ 51KERNEL_ENTRY := $(shell /bin/bash -c 'printf "0x%08x" \
48 $$[$(CONFIG_PAGE_OFFSET) + \ 52 $$[$(CONFIG_PAGE_OFFSET) + \
49 $(CONFIG_MEMORY_START) + \ 53 $(KERNEL_MEMORY) + \
50 $(CONFIG_ZERO_PAGE_OFFSET) + $(CONFIG_ENTRY_OFFSET)]') 54 $(CONFIG_ZERO_PAGE_OFFSET) + $(CONFIG_ENTRY_OFFSET)]')
51 55
52quiet_cmd_uimage = UIMAGE $@ 56quiet_cmd_uimage = UIMAGE $@
diff --git a/arch/sh/cchips/hd6446x/hd64461.c b/arch/sh/cchips/hd6446x/hd64461.c
index 27ceeb948bb1..25ef91061521 100644
--- a/arch/sh/cchips/hd6446x/hd64461.c
+++ b/arch/sh/cchips/hd6446x/hd64461.c
@@ -53,21 +53,22 @@ static struct irq_chip hd64461_irq_chip = {
53 .unmask = hd64461_unmask_irq, 53 .unmask = hd64461_unmask_irq,
54}; 54};
55 55
56int hd64461_irq_demux(int irq) 56static void hd64461_irq_demux(unsigned int irq, struct irq_desc *desc)
57{ 57{
58 if (irq == CONFIG_HD64461_IRQ) { 58 unsigned short intv = ctrl_inw(HD64461_NIRR);
59 unsigned short bit; 59 struct irq_desc *ext_desc;
60 unsigned short nirr = inw(HD64461_NIRR); 60 unsigned int ext_irq = HD64461_IRQBASE;
61 unsigned short nimr = inw(HD64461_NIMR); 61
62 int i; 62 intv &= (1 << HD64461_IRQ_NUM) - 1;
63 63
64 nirr &= ~nimr; 64 while (intv) {
65 for (bit = 1, i = 0; i < 16; bit <<= 1, i++) 65 if (intv & 1) {
66 if (nirr & bit) 66 ext_desc = irq_desc + ext_irq;
67 break; 67 handle_level_irq(ext_irq, ext_desc);
68 irq = HD64461_IRQBASE + i; 68 }
69 intv >>= 1;
70 ext_irq++;
69 } 71 }
70 return irq;
71} 72}
72 73
73int __init setup_hd64461(void) 74int __init setup_hd64461(void)
@@ -93,6 +94,9 @@ int __init setup_hd64461(void)
93 set_irq_chip_and_handler(i, &hd64461_irq_chip, 94 set_irq_chip_and_handler(i, &hd64461_irq_chip,
94 handle_level_irq); 95 handle_level_irq);
95 96
97 set_irq_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
98 set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);
99
96#ifdef CONFIG_HD64461_ENABLER 100#ifdef CONFIG_HD64461_ENABLER
97 printk(KERN_INFO "HD64461: enabling PCMCIA devices\n"); 101 printk(KERN_INFO "HD64461: enabling PCMCIA devices\n");
98 __raw_writeb(0x4c, HD64461_PCC1CSCIER); 102 __raw_writeb(0x4c, HD64461_PCC1CSCIER);
diff --git a/arch/sh/configs/espt_defconfig b/arch/sh/configs/espt_defconfig
new file mode 100644
index 000000000000..873ec42c6e69
--- /dev/null
+++ b/arch/sh/configs/espt_defconfig
@@ -0,0 +1,1190 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29-rc7
4# Tue Mar 17 13:25:58 2009
5#
6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y
11CONFIG_GENERIC_FIND_NEXT_BIT=y
12CONFIG_GENERIC_HWEIGHT=y
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
15CONFIG_GENERIC_IRQ_PROBE=y
16# CONFIG_GENERIC_GPIO is not set
17CONFIG_GENERIC_TIME=y
18CONFIG_GENERIC_CLOCKEVENTS=y
19# CONFIG_ARCH_SUSPEND_POSSIBLE is not set
20# CONFIG_ARCH_HIBERNATION_POSSIBLE is not set
21CONFIG_STACKTRACE_SUPPORT=y
22CONFIG_LOCKDEP_SUPPORT=y
23CONFIG_HAVE_LATENCYTOP_SUPPORT=y
24# CONFIG_ARCH_HAS_ILOG2_U32 is not set
25# CONFIG_ARCH_HAS_ILOG2_U64 is not set
26CONFIG_ARCH_NO_VIRT_TO_BUS=y
27CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
28
29#
30# General setup
31#
32CONFIG_EXPERIMENTAL=y
33CONFIG_BROKEN_ON_SMP=y
34CONFIG_INIT_ENV_ARG_LIMIT=32
35CONFIG_LOCALVERSION=""
36CONFIG_LOCALVERSION_AUTO=y
37CONFIG_SWAP=y
38CONFIG_SYSVIPC=y
39CONFIG_SYSVIPC_SYSCTL=y
40# CONFIG_POSIX_MQUEUE is not set
41# CONFIG_BSD_PROCESS_ACCT is not set
42# CONFIG_TASKSTATS is not set
43# CONFIG_AUDIT is not set
44
45#
46# RCU Subsystem
47#
48CONFIG_CLASSIC_RCU=y
49# CONFIG_TREE_RCU is not set
50# CONFIG_PREEMPT_RCU is not set
51# CONFIG_TREE_RCU_TRACE is not set
52# CONFIG_PREEMPT_RCU_TRACE is not set
53CONFIG_IKCONFIG=y
54CONFIG_IKCONFIG_PROC=y
55CONFIG_LOG_BUF_SHIFT=14
56CONFIG_GROUP_SCHED=y
57CONFIG_FAIR_GROUP_SCHED=y
58# CONFIG_RT_GROUP_SCHED is not set
59CONFIG_USER_SCHED=y
60# CONFIG_CGROUP_SCHED is not set
61# CONFIG_CGROUPS is not set
62CONFIG_SYSFS_DEPRECATED=y
63CONFIG_SYSFS_DEPRECATED_V2=y
64# CONFIG_RELAY is not set
65CONFIG_NAMESPACES=y
66CONFIG_UTS_NS=y
67CONFIG_IPC_NS=y
68# CONFIG_USER_NS is not set
69# CONFIG_PID_NS is not set
70# CONFIG_NET_NS is not set
71# CONFIG_BLK_DEV_INITRD is not set
72CONFIG_CC_OPTIMIZE_FOR_SIZE=y
73CONFIG_SYSCTL=y
74CONFIG_EMBEDDED=y
75CONFIG_UID16=y
76# CONFIG_SYSCTL_SYSCALL is not set
77CONFIG_KALLSYMS=y
78# CONFIG_KALLSYMS_EXTRA_PASS is not set
79CONFIG_HOTPLUG=y
80CONFIG_PRINTK=y
81CONFIG_BUG=y
82CONFIG_ELF_CORE=y
83CONFIG_COMPAT_BRK=y
84CONFIG_BASE_FULL=y
85CONFIG_FUTEX=y
86CONFIG_ANON_INODES=y
87CONFIG_EPOLL=y
88CONFIG_SIGNALFD=y
89CONFIG_TIMERFD=y
90CONFIG_EVENTFD=y
91CONFIG_SHMEM=y
92CONFIG_AIO=y
93CONFIG_VM_EVENT_COUNTERS=y
94CONFIG_SLAB=y
95# CONFIG_SLUB is not set
96# CONFIG_SLOB is not set
97CONFIG_PROFILING=y
98CONFIG_TRACEPOINTS=y
99# CONFIG_MARKERS is not set
100CONFIG_OPROFILE=y
101CONFIG_HAVE_OPROFILE=y
102# CONFIG_KPROBES is not set
103CONFIG_HAVE_IOREMAP_PROT=y
104CONFIG_HAVE_KPROBES=y
105CONFIG_HAVE_KRETPROBES=y
106CONFIG_HAVE_ARCH_TRACEHOOK=y
107CONFIG_HAVE_CLK=y
108CONFIG_HAVE_GENERIC_DMA_COHERENT=y
109CONFIG_SLABINFO=y
110CONFIG_RT_MUTEXES=y
111CONFIG_BASE_SMALL=0
112CONFIG_MODULES=y
113# CONFIG_MODULE_FORCE_LOAD is not set
114# CONFIG_MODULE_UNLOAD is not set
115# CONFIG_MODVERSIONS is not set
116# CONFIG_MODULE_SRCVERSION_ALL is not set
117CONFIG_BLOCK=y
118# CONFIG_LBD is not set
119# CONFIG_BLK_DEV_IO_TRACE is not set
120# CONFIG_BLK_DEV_BSG is not set
121# CONFIG_BLK_DEV_INTEGRITY is not set
122
123#
124# IO Schedulers
125#
126CONFIG_IOSCHED_NOOP=y
127CONFIG_IOSCHED_AS=y
128CONFIG_IOSCHED_DEADLINE=y
129CONFIG_IOSCHED_CFQ=y
130CONFIG_DEFAULT_AS=y
131# CONFIG_DEFAULT_DEADLINE is not set
132# CONFIG_DEFAULT_CFQ is not set
133# CONFIG_DEFAULT_NOOP is not set
134CONFIG_DEFAULT_IOSCHED="anticipatory"
135# CONFIG_FREEZER is not set
136
137#
138# System type
139#
140CONFIG_CPU_SH4=y
141CONFIG_CPU_SH4A=y
142# CONFIG_CPU_SUBTYPE_SH7619 is not set
143# CONFIG_CPU_SUBTYPE_SH7201 is not set
144# CONFIG_CPU_SUBTYPE_SH7203 is not set
145# CONFIG_CPU_SUBTYPE_SH7206 is not set
146# CONFIG_CPU_SUBTYPE_SH7263 is not set
147# CONFIG_CPU_SUBTYPE_MXG is not set
148# CONFIG_CPU_SUBTYPE_SH7705 is not set
149# CONFIG_CPU_SUBTYPE_SH7706 is not set
150# CONFIG_CPU_SUBTYPE_SH7707 is not set
151# CONFIG_CPU_SUBTYPE_SH7708 is not set
152# CONFIG_CPU_SUBTYPE_SH7709 is not set
153# CONFIG_CPU_SUBTYPE_SH7710 is not set
154# CONFIG_CPU_SUBTYPE_SH7712 is not set
155# CONFIG_CPU_SUBTYPE_SH7720 is not set
156# CONFIG_CPU_SUBTYPE_SH7721 is not set
157# CONFIG_CPU_SUBTYPE_SH7750 is not set
158# CONFIG_CPU_SUBTYPE_SH7091 is not set
159# CONFIG_CPU_SUBTYPE_SH7750R is not set
160# CONFIG_CPU_SUBTYPE_SH7750S is not set
161# CONFIG_CPU_SUBTYPE_SH7751 is not set
162# CONFIG_CPU_SUBTYPE_SH7751R is not set
163# CONFIG_CPU_SUBTYPE_SH7760 is not set
164# CONFIG_CPU_SUBTYPE_SH4_202 is not set
165# CONFIG_CPU_SUBTYPE_SH7723 is not set
166CONFIG_CPU_SUBTYPE_SH7763=y
167# CONFIG_CPU_SUBTYPE_SH7770 is not set
168# CONFIG_CPU_SUBTYPE_SH7780 is not set
169# CONFIG_CPU_SUBTYPE_SH7785 is not set
170# CONFIG_CPU_SUBTYPE_SH7786 is not set
171# CONFIG_CPU_SUBTYPE_SHX3 is not set
172# CONFIG_CPU_SUBTYPE_SH7343 is not set
173# CONFIG_CPU_SUBTYPE_SH7722 is not set
174# CONFIG_CPU_SUBTYPE_SH7366 is not set
175# CONFIG_CPU_SUBTYPE_SH5_101 is not set
176# CONFIG_CPU_SUBTYPE_SH5_103 is not set
177
178#
179# Memory management options
180#
181CONFIG_QUICKLIST=y
182CONFIG_MMU=y
183CONFIG_PAGE_OFFSET=0x80000000
184CONFIG_MEMORY_START=0x0c000000
185CONFIG_MEMORY_SIZE=0x04000000
186CONFIG_29BIT=y
187CONFIG_VSYSCALL=y
188CONFIG_ARCH_FLATMEM_ENABLE=y
189CONFIG_ARCH_SPARSEMEM_ENABLE=y
190CONFIG_ARCH_SPARSEMEM_DEFAULT=y
191CONFIG_MAX_ACTIVE_REGIONS=1
192CONFIG_ARCH_POPULATES_NODE_MAP=y
193CONFIG_ARCH_SELECT_MEMORY_MODEL=y
194CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
195CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
196CONFIG_PAGE_SIZE_4KB=y
197# CONFIG_PAGE_SIZE_8KB is not set
198# CONFIG_PAGE_SIZE_16KB is not set
199# CONFIG_PAGE_SIZE_64KB is not set
200CONFIG_ENTRY_OFFSET=0x00001000
201CONFIG_SELECT_MEMORY_MODEL=y
202# CONFIG_FLATMEM_MANUAL is not set
203# CONFIG_DISCONTIGMEM_MANUAL is not set
204CONFIG_SPARSEMEM_MANUAL=y
205CONFIG_SPARSEMEM=y
206CONFIG_HAVE_MEMORY_PRESENT=y
207CONFIG_SPARSEMEM_STATIC=y
208# CONFIG_MEMORY_HOTPLUG is not set
209CONFIG_PAGEFLAGS_EXTENDED=y
210CONFIG_SPLIT_PTLOCK_CPUS=4
211CONFIG_MIGRATION=y
212# CONFIG_PHYS_ADDR_T_64BIT is not set
213CONFIG_ZONE_DMA_FLAG=0
214CONFIG_NR_QUICK=2
215CONFIG_UNEVICTABLE_LRU=y
216
217#
218# Cache configuration
219#
220# CONFIG_SH_DIRECT_MAPPED is not set
221CONFIG_CACHE_WRITEBACK=y
222# CONFIG_CACHE_WRITETHROUGH is not set
223# CONFIG_CACHE_OFF is not set
224
225#
226# Processor features
227#
228CONFIG_CPU_LITTLE_ENDIAN=y
229# CONFIG_CPU_BIG_ENDIAN is not set
230CONFIG_SH_FPU=y
231# CONFIG_SH_STORE_QUEUES is not set
232CONFIG_CPU_HAS_INTEVT=y
233CONFIG_CPU_HAS_SR_RB=y
234CONFIG_CPU_HAS_FPU=y
235
236#
237# Board support
238#
239# CONFIG_SH_SH7763RDP is not set
240CONFIG_SH_ESPT=y
241
242#
243# Timer and clock configuration
244#
245CONFIG_SH_TMU=y
246CONFIG_SH_TIMER_IRQ=28
247CONFIG_SH_PCLK_FREQ=66666666
248# CONFIG_NO_HZ is not set
249# CONFIG_HIGH_RES_TIMERS is not set
250CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
251
252#
253# CPU Frequency scaling
254#
255# CONFIG_CPU_FREQ is not set
256
257#
258# DMA support
259#
260# CONFIG_SH_DMA is not set
261
262#
263# Companion Chips
264#
265
266#
267# Additional SuperH Device Drivers
268#
269# CONFIG_HEARTBEAT is not set
270# CONFIG_PUSH_SWITCH is not set
271
272#
273# Kernel features
274#
275# CONFIG_HZ_100 is not set
276CONFIG_HZ_250=y
277# CONFIG_HZ_300 is not set
278# CONFIG_HZ_1000 is not set
279CONFIG_HZ=250
280# CONFIG_SCHED_HRTICK is not set
281# CONFIG_KEXEC is not set
282# CONFIG_CRASH_DUMP is not set
283CONFIG_SECCOMP=y
284CONFIG_PREEMPT_NONE=y
285# CONFIG_PREEMPT_VOLUNTARY is not set
286# CONFIG_PREEMPT is not set
287CONFIG_GUSA=y
288
289#
290# Boot options
291#
292CONFIG_ZERO_PAGE_OFFSET=0x00001000
293CONFIG_BOOT_LINK_OFFSET=0x00800000
294CONFIG_CMDLINE_BOOL=y
295CONFIG_CMDLINE="console=ttySC0,115200 root=/dev/nfs ip=bootp"
296
297#
298# Bus options
299#
300# CONFIG_ARCH_SUPPORTS_MSI is not set
301# CONFIG_PCCARD is not set
302
303#
304# Executable file formats
305#
306CONFIG_BINFMT_ELF=y
307# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
308# CONFIG_HAVE_AOUT is not set
309# CONFIG_BINFMT_MISC is not set
310
311#
312# Power management options (EXPERIMENTAL)
313#
314# CONFIG_PM is not set
315# CONFIG_CPU_IDLE is not set
316CONFIG_NET=y
317
318#
319# Networking options
320#
321CONFIG_COMPAT_NET_DEV_OPS=y
322CONFIG_PACKET=y
323# CONFIG_PACKET_MMAP is not set
324CONFIG_UNIX=y
325CONFIG_XFRM=y
326# CONFIG_XFRM_USER is not set
327# CONFIG_XFRM_SUB_POLICY is not set
328# CONFIG_XFRM_MIGRATE is not set
329# CONFIG_XFRM_STATISTICS is not set
330# CONFIG_NET_KEY is not set
331CONFIG_INET=y
332# CONFIG_IP_MULTICAST is not set
333# CONFIG_IP_ADVANCED_ROUTER is not set
334CONFIG_IP_FIB_HASH=y
335CONFIG_IP_PNP=y
336CONFIG_IP_PNP_DHCP=y
337CONFIG_IP_PNP_BOOTP=y
338# CONFIG_IP_PNP_RARP is not set
339# CONFIG_NET_IPIP is not set
340# CONFIG_NET_IPGRE is not set
341# CONFIG_ARPD is not set
342# CONFIG_SYN_COOKIES is not set
343# CONFIG_INET_AH is not set
344# CONFIG_INET_ESP is not set
345# CONFIG_INET_IPCOMP is not set
346# CONFIG_INET_XFRM_TUNNEL is not set
347# CONFIG_INET_TUNNEL is not set
348CONFIG_INET_XFRM_MODE_TRANSPORT=y
349CONFIG_INET_XFRM_MODE_TUNNEL=y
350CONFIG_INET_XFRM_MODE_BEET=y
351# CONFIG_INET_LRO is not set
352CONFIG_INET_DIAG=y
353CONFIG_INET_TCP_DIAG=y
354# CONFIG_TCP_CONG_ADVANCED is not set
355CONFIG_TCP_CONG_CUBIC=y
356CONFIG_DEFAULT_TCP_CONG="cubic"
357# CONFIG_TCP_MD5SIG is not set
358# CONFIG_IPV6 is not set
359# CONFIG_NETWORK_SECMARK is not set
360# CONFIG_NETFILTER is not set
361# CONFIG_IP_DCCP is not set
362# CONFIG_IP_SCTP is not set
363# CONFIG_TIPC is not set
364# CONFIG_ATM is not set
365# CONFIG_BRIDGE is not set
366# CONFIG_NET_DSA is not set
367# CONFIG_VLAN_8021Q is not set
368# CONFIG_DECNET is not set
369# CONFIG_LLC2 is not set
370# CONFIG_IPX is not set
371# CONFIG_ATALK is not set
372# CONFIG_X25 is not set
373# CONFIG_LAPB is not set
374# CONFIG_ECONET is not set
375# CONFIG_WAN_ROUTER is not set
376# CONFIG_NET_SCHED is not set
377# CONFIG_DCB is not set
378
379#
380# Network testing
381#
382# CONFIG_NET_PKTGEN is not set
383# CONFIG_HAMRADIO is not set
384# CONFIG_CAN is not set
385# CONFIG_IRDA is not set
386# CONFIG_BT is not set
387# CONFIG_AF_RXRPC is not set
388# CONFIG_PHONET is not set
389# CONFIG_WIRELESS is not set
390# CONFIG_WIMAX is not set
391# CONFIG_RFKILL is not set
392# CONFIG_NET_9P is not set
393
394#
395# Device Drivers
396#
397
398#
399# Generic Driver Options
400#
401CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
402CONFIG_STANDALONE=y
403CONFIG_PREVENT_FIRMWARE_BUILD=y
404CONFIG_FW_LOADER=y
405CONFIG_FIRMWARE_IN_KERNEL=y
406CONFIG_EXTRA_FIRMWARE=""
407# CONFIG_SYS_HYPERVISOR is not set
408# CONFIG_CONNECTOR is not set
409CONFIG_MTD=y
410# CONFIG_MTD_DEBUG is not set
411# CONFIG_MTD_CONCAT is not set
412CONFIG_MTD_PARTITIONS=y
413# CONFIG_MTD_TESTS is not set
414# CONFIG_MTD_REDBOOT_PARTS is not set
415CONFIG_MTD_CMDLINE_PARTS=y
416# CONFIG_MTD_AR7_PARTS is not set
417
418#
419# User Modules And Translation Layers
420#
421CONFIG_MTD_CHAR=y
422CONFIG_MTD_BLKDEVS=y
423CONFIG_MTD_BLOCK=y
424# CONFIG_FTL is not set
425# CONFIG_NFTL is not set
426# CONFIG_INFTL is not set
427# CONFIG_RFD_FTL is not set
428# CONFIG_SSFDC is not set
429# CONFIG_MTD_OOPS is not set
430
431#
432# RAM/ROM/Flash chip drivers
433#
434CONFIG_MTD_CFI=y
435CONFIG_MTD_JEDECPROBE=y
436CONFIG_MTD_GEN_PROBE=y
437CONFIG_MTD_CFI_ADV_OPTIONS=y
438CONFIG_MTD_CFI_NOSWAP=y
439# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
440# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
441CONFIG_MTD_CFI_GEOMETRY=y
442# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
443CONFIG_MTD_MAP_BANK_WIDTH_2=y
444# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
445# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
446# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
447# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
448CONFIG_MTD_CFI_I1=y
449CONFIG_MTD_CFI_I2=y
450# CONFIG_MTD_CFI_I4 is not set
451# CONFIG_MTD_CFI_I8 is not set
452# CONFIG_MTD_OTP is not set
453# CONFIG_MTD_CFI_INTELEXT is not set
454CONFIG_MTD_CFI_AMDSTD=y
455# CONFIG_MTD_CFI_STAA is not set
456CONFIG_MTD_CFI_UTIL=y
457# CONFIG_MTD_RAM is not set
458# CONFIG_MTD_ROM is not set
459# CONFIG_MTD_ABSENT is not set
460
461#
462# Mapping drivers for chip access
463#
464CONFIG_MTD_COMPLEX_MAPPINGS=y
465CONFIG_MTD_PHYSMAP=y
466# CONFIG_MTD_PHYSMAP_COMPAT is not set
467# CONFIG_MTD_PLATRAM is not set
468
469#
470# Self-contained MTD device drivers
471#
472# CONFIG_MTD_SLRAM is not set
473# CONFIG_MTD_PHRAM is not set
474# CONFIG_MTD_MTDRAM is not set
475# CONFIG_MTD_BLOCK2MTD is not set
476
477#
478# Disk-On-Chip Device Drivers
479#
480# CONFIG_MTD_DOC2000 is not set
481# CONFIG_MTD_DOC2001 is not set
482# CONFIG_MTD_DOC2001PLUS is not set
483# CONFIG_MTD_NAND is not set
484# CONFIG_MTD_ONENAND is not set
485
486#
487# LPDDR flash memory drivers
488#
489# CONFIG_MTD_LPDDR is not set
490
491#
492# UBI - Unsorted block images
493#
494# CONFIG_MTD_UBI is not set
495# CONFIG_PARPORT is not set
496CONFIG_BLK_DEV=y
497# CONFIG_BLK_DEV_COW_COMMON is not set
498# CONFIG_BLK_DEV_LOOP is not set
499# CONFIG_BLK_DEV_NBD is not set
500# CONFIG_BLK_DEV_UB is not set
501# CONFIG_BLK_DEV_RAM is not set
502# CONFIG_CDROM_PKTCDVD is not set
503# CONFIG_ATA_OVER_ETH is not set
504# CONFIG_BLK_DEV_HD is not set
505# CONFIG_MISC_DEVICES is not set
506CONFIG_HAVE_IDE=y
507# CONFIG_IDE is not set
508
509#
510# SCSI device support
511#
512# CONFIG_RAID_ATTRS is not set
513CONFIG_SCSI=y
514CONFIG_SCSI_DMA=y
515# CONFIG_SCSI_TGT is not set
516# CONFIG_SCSI_NETLINK is not set
517CONFIG_SCSI_PROC_FS=y
518
519#
520# SCSI support type (disk, tape, CD-ROM)
521#
522CONFIG_BLK_DEV_SD=y
523# CONFIG_CHR_DEV_ST is not set
524# CONFIG_CHR_DEV_OSST is not set
525# CONFIG_BLK_DEV_SR is not set
526# CONFIG_CHR_DEV_SG is not set
527# CONFIG_CHR_DEV_SCH is not set
528
529#
530# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
531#
532# CONFIG_SCSI_MULTI_LUN is not set
533# CONFIG_SCSI_CONSTANTS is not set
534# CONFIG_SCSI_LOGGING is not set
535# CONFIG_SCSI_SCAN_ASYNC is not set
536CONFIG_SCSI_WAIT_SCAN=m
537
538#
539# SCSI Transports
540#
541# CONFIG_SCSI_SPI_ATTRS is not set
542# CONFIG_SCSI_FC_ATTRS is not set
543# CONFIG_SCSI_ISCSI_ATTRS is not set
544# CONFIG_SCSI_SAS_LIBSAS is not set
545# CONFIG_SCSI_SRP_ATTRS is not set
546CONFIG_SCSI_LOWLEVEL=y
547# CONFIG_ISCSI_TCP is not set
548# CONFIG_LIBFC is not set
549# CONFIG_SCSI_DEBUG is not set
550# CONFIG_SCSI_DH is not set
551# CONFIG_ATA is not set
552# CONFIG_MD is not set
553CONFIG_NETDEVICES=y
554# CONFIG_DUMMY is not set
555# CONFIG_BONDING is not set
556# CONFIG_MACVLAN is not set
557# CONFIG_EQUALIZER is not set
558# CONFIG_TUN is not set
559# CONFIG_VETH is not set
560CONFIG_PHYLIB=y
561
562#
563# MII PHY device drivers
564#
565# CONFIG_MARVELL_PHY is not set
566# CONFIG_DAVICOM_PHY is not set
567# CONFIG_QSEMI_PHY is not set
568# CONFIG_LXT_PHY is not set
569# CONFIG_CICADA_PHY is not set
570# CONFIG_VITESSE_PHY is not set
571# CONFIG_SMSC_PHY is not set
572# CONFIG_BROADCOM_PHY is not set
573# CONFIG_ICPLUS_PHY is not set
574# CONFIG_REALTEK_PHY is not set
575# CONFIG_NATIONAL_PHY is not set
576# CONFIG_STE10XP is not set
577# CONFIG_LSI_ET1011C_PHY is not set
578# CONFIG_FIXED_PHY is not set
579CONFIG_MDIO_BITBANG=y
580CONFIG_NET_ETHERNET=y
581CONFIG_MII=y
582# CONFIG_AX88796 is not set
583# CONFIG_STNIC is not set
584CONFIG_SH_ETH=y
585# CONFIG_SMC91X is not set
586# CONFIG_SMC911X is not set
587# CONFIG_SMSC911X is not set
588# CONFIG_IBM_NEW_EMAC_ZMII is not set
589# CONFIG_IBM_NEW_EMAC_RGMII is not set
590# CONFIG_IBM_NEW_EMAC_TAH is not set
591# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
592# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
593# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
594# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
595# CONFIG_B44 is not set
596# CONFIG_NETDEV_1000 is not set
597# CONFIG_NETDEV_10000 is not set
598
599#
600# Wireless LAN
601#
602# CONFIG_WLAN_PRE80211 is not set
603# CONFIG_WLAN_80211 is not set
604# CONFIG_IWLWIFI_LEDS is not set
605
606#
607# Enable WiMAX (Networking options) to see the WiMAX drivers
608#
609
610#
611# USB Network Adapters
612#
613# CONFIG_USB_CATC is not set
614# CONFIG_USB_KAWETH is not set
615# CONFIG_USB_PEGASUS is not set
616# CONFIG_USB_RTL8150 is not set
617# CONFIG_USB_USBNET is not set
618# CONFIG_WAN is not set
619# CONFIG_PPP is not set
620# CONFIG_SLIP is not set
621# CONFIG_NETCONSOLE is not set
622# CONFIG_NETPOLL is not set
623# CONFIG_NET_POLL_CONTROLLER is not set
624# CONFIG_ISDN is not set
625# CONFIG_PHONE is not set
626
627#
628# Input device support
629#
630CONFIG_INPUT=y
631# CONFIG_INPUT_FF_MEMLESS is not set
632# CONFIG_INPUT_POLLDEV is not set
633
634#
635# Userland interfaces
636#
637# CONFIG_INPUT_MOUSEDEV is not set
638# CONFIG_INPUT_JOYDEV is not set
639# CONFIG_INPUT_EVDEV is not set
640# CONFIG_INPUT_EVBUG is not set
641
642#
643# Input Device Drivers
644#
645# CONFIG_INPUT_KEYBOARD is not set
646# CONFIG_INPUT_MOUSE is not set
647# CONFIG_INPUT_JOYSTICK is not set
648# CONFIG_INPUT_TABLET is not set
649# CONFIG_INPUT_TOUCHSCREEN is not set
650# CONFIG_INPUT_MISC is not set
651
652#
653# Hardware I/O ports
654#
655# CONFIG_SERIO is not set
656# CONFIG_GAMEPORT is not set
657
658#
659# Character devices
660#
661CONFIG_VT=y
662CONFIG_CONSOLE_TRANSLATIONS=y
663CONFIG_VT_CONSOLE=y
664CONFIG_HW_CONSOLE=y
665# CONFIG_VT_HW_CONSOLE_BINDING is not set
666CONFIG_DEVKMEM=y
667# CONFIG_SERIAL_NONSTANDARD is not set
668
669#
670# Serial drivers
671#
672# CONFIG_SERIAL_8250 is not set
673
674#
675# Non-8250 serial port support
676#
677CONFIG_SERIAL_SH_SCI=y
678CONFIG_SERIAL_SH_SCI_NR_UARTS=3
679CONFIG_SERIAL_SH_SCI_CONSOLE=y
680CONFIG_SERIAL_CORE=y
681CONFIG_SERIAL_CORE_CONSOLE=y
682CONFIG_UNIX98_PTYS=y
683# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
684CONFIG_LEGACY_PTYS=y
685CONFIG_LEGACY_PTY_COUNT=256
686# CONFIG_IPMI_HANDLER is not set
687CONFIG_HW_RANDOM=y
688# CONFIG_R3964 is not set
689# CONFIG_RAW_DRIVER is not set
690# CONFIG_TCG_TPM is not set
691# CONFIG_I2C is not set
692# CONFIG_SPI is not set
693# CONFIG_W1 is not set
694# CONFIG_POWER_SUPPLY is not set
695# CONFIG_HWMON is not set
696# CONFIG_THERMAL is not set
697# CONFIG_THERMAL_HWMON is not set
698# CONFIG_WATCHDOG is not set
699CONFIG_SSB_POSSIBLE=y
700
701#
702# Sonics Silicon Backplane
703#
704# CONFIG_SSB is not set
705
706#
707# Multifunction device drivers
708#
709# CONFIG_MFD_CORE is not set
710# CONFIG_MFD_SM501 is not set
711# CONFIG_HTC_PASIC3 is not set
712# CONFIG_MFD_TMIO is not set
713# CONFIG_REGULATOR is not set
714
715#
716# Multimedia devices
717#
718
719#
720# Multimedia core support
721#
722# CONFIG_VIDEO_DEV is not set
723# CONFIG_DVB_CORE is not set
724# CONFIG_VIDEO_MEDIA is not set
725
726#
727# Multimedia drivers
728#
729# CONFIG_DAB is not set
730
731#
732# Graphics support
733#
734# CONFIG_VGASTATE is not set
735# CONFIG_VIDEO_OUTPUT_CONTROL is not set
736CONFIG_FB=y
737# CONFIG_FIRMWARE_EDID is not set
738# CONFIG_FB_DDC is not set
739# CONFIG_FB_BOOT_VESA_SUPPORT is not set
740CONFIG_FB_CFB_FILLRECT=y
741CONFIG_FB_CFB_COPYAREA=y
742CONFIG_FB_CFB_IMAGEBLIT=y
743# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
744# CONFIG_FB_SYS_FILLRECT is not set
745# CONFIG_FB_SYS_COPYAREA is not set
746# CONFIG_FB_SYS_IMAGEBLIT is not set
747CONFIG_FB_FOREIGN_ENDIAN=y
748CONFIG_FB_BOTH_ENDIAN=y
749# CONFIG_FB_BIG_ENDIAN is not set
750# CONFIG_FB_LITTLE_ENDIAN is not set
751# CONFIG_FB_SYS_FOPS is not set
752# CONFIG_FB_SVGALIB is not set
753# CONFIG_FB_MACMODES is not set
754# CONFIG_FB_BACKLIGHT is not set
755# CONFIG_FB_MODE_HELPERS is not set
756# CONFIG_FB_TILEBLITTING is not set
757
758#
759# Frame buffer hardware drivers
760#
761# CONFIG_FB_S1D13XXX is not set
762# CONFIG_FB_SH_MOBILE_LCDC is not set
763CONFIG_FB_SH7760=y
764# CONFIG_FB_VIRTUAL is not set
765# CONFIG_FB_METRONOME is not set
766# CONFIG_FB_MB862XX is not set
767# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
768
769#
770# Display device support
771#
772# CONFIG_DISPLAY_SUPPORT is not set
773
774#
775# Console display driver support
776#
777CONFIG_DUMMY_CONSOLE=y
778CONFIG_FRAMEBUFFER_CONSOLE=y
779# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
780# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
781# CONFIG_FONTS is not set
782CONFIG_FONT_8x8=y
783CONFIG_FONT_8x16=y
784CONFIG_LOGO=y
785CONFIG_LOGO_LINUX_MONO=y
786CONFIG_LOGO_LINUX_VGA16=y
787CONFIG_LOGO_LINUX_CLUT224=y
788CONFIG_LOGO_SUPERH_MONO=y
789CONFIG_LOGO_SUPERH_VGA16=y
790CONFIG_LOGO_SUPERH_CLUT224=y
791# CONFIG_SOUND is not set
792# CONFIG_HID_SUPPORT is not set
793CONFIG_USB_SUPPORT=y
794CONFIG_USB_ARCH_HAS_HCD=y
795CONFIG_USB_ARCH_HAS_OHCI=y
796# CONFIG_USB_ARCH_HAS_EHCI is not set
797CONFIG_USB=y
798# CONFIG_USB_DEBUG is not set
799# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
800
801#
802# Miscellaneous USB options
803#
804# CONFIG_USB_DEVICEFS is not set
805CONFIG_USB_DEVICE_CLASS=y
806# CONFIG_USB_DYNAMIC_MINORS is not set
807# CONFIG_USB_OTG is not set
808# CONFIG_USB_OTG_WHITELIST is not set
809# CONFIG_USB_OTG_BLACKLIST_HUB is not set
810CONFIG_USB_MON=y
811# CONFIG_USB_WUSB is not set
812# CONFIG_USB_WUSB_CBAF is not set
813
814#
815# USB Host Controller Drivers
816#
817# CONFIG_USB_C67X00_HCD is not set
818# CONFIG_USB_OXU210HP_HCD is not set
819# CONFIG_USB_ISP116X_HCD is not set
820CONFIG_USB_OHCI_HCD=y
821# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
822# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
823CONFIG_USB_OHCI_LITTLE_ENDIAN=y
824# CONFIG_USB_SL811_HCD is not set
825# CONFIG_USB_R8A66597_HCD is not set
826# CONFIG_USB_HWA_HCD is not set
827
828#
829# USB Device Class drivers
830#
831# CONFIG_USB_ACM is not set
832# CONFIG_USB_PRINTER is not set
833# CONFIG_USB_WDM is not set
834# CONFIG_USB_TMC is not set
835
836#
837# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
838#
839
840#
841# see USB_STORAGE Help for more information
842#
843CONFIG_USB_STORAGE=y
844# CONFIG_USB_STORAGE_DEBUG is not set
845# CONFIG_USB_STORAGE_DATAFAB is not set
846# CONFIG_USB_STORAGE_FREECOM is not set
847# CONFIG_USB_STORAGE_ISD200 is not set
848# CONFIG_USB_STORAGE_USBAT is not set
849# CONFIG_USB_STORAGE_SDDR09 is not set
850# CONFIG_USB_STORAGE_SDDR55 is not set
851# CONFIG_USB_STORAGE_JUMPSHOT is not set
852# CONFIG_USB_STORAGE_ALAUDA is not set
853# CONFIG_USB_STORAGE_ONETOUCH is not set
854# CONFIG_USB_STORAGE_KARMA is not set
855# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
856# CONFIG_USB_LIBUSUAL is not set
857
858#
859# USB Imaging devices
860#
861# CONFIG_USB_MDC800 is not set
862# CONFIG_USB_MICROTEK is not set
863
864#
865# USB port drivers
866#
867# CONFIG_USB_SERIAL is not set
868
869#
870# USB Miscellaneous drivers
871#
872# CONFIG_USB_EMI62 is not set
873# CONFIG_USB_EMI26 is not set
874# CONFIG_USB_ADUTUX is not set
875# CONFIG_USB_SEVSEG is not set
876# CONFIG_USB_RIO500 is not set
877# CONFIG_USB_LEGOTOWER is not set
878# CONFIG_USB_LCD is not set
879# CONFIG_USB_BERRY_CHARGE is not set
880# CONFIG_USB_LED is not set
881# CONFIG_USB_CYPRESS_CY7C63 is not set
882# CONFIG_USB_CYTHERM is not set
883# CONFIG_USB_PHIDGET is not set
884# CONFIG_USB_IDMOUSE is not set
885# CONFIG_USB_FTDI_ELAN is not set
886# CONFIG_USB_APPLEDISPLAY is not set
887# CONFIG_USB_LD is not set
888# CONFIG_USB_TRANCEVIBRATOR is not set
889# CONFIG_USB_IOWARRIOR is not set
890# CONFIG_USB_ISIGHTFW is not set
891# CONFIG_USB_VST is not set
892# CONFIG_USB_GADGET is not set
893
894#
895# OTG and related infrastructure
896#
897# CONFIG_MMC is not set
898# CONFIG_MEMSTICK is not set
899# CONFIG_NEW_LEDS is not set
900# CONFIG_ACCESSIBILITY is not set
901# CONFIG_RTC_CLASS is not set
902# CONFIG_DMADEVICES is not set
903# CONFIG_UIO is not set
904# CONFIG_STAGING is not set
905
906#
907# File systems
908#
909CONFIG_EXT2_FS=y
910# CONFIG_EXT2_FS_XATTR is not set
911# CONFIG_EXT2_FS_XIP is not set
912CONFIG_EXT3_FS=y
913CONFIG_EXT3_FS_XATTR=y
914# CONFIG_EXT3_FS_POSIX_ACL is not set
915# CONFIG_EXT3_FS_SECURITY is not set
916# CONFIG_EXT4_FS is not set
917CONFIG_JBD=y
918# CONFIG_JBD_DEBUG is not set
919CONFIG_FS_MBCACHE=y
920# CONFIG_REISERFS_FS is not set
921# CONFIG_JFS_FS is not set
922CONFIG_FS_POSIX_ACL=y
923CONFIG_FILE_LOCKING=y
924# CONFIG_XFS_FS is not set
925# CONFIG_OCFS2_FS is not set
926# CONFIG_BTRFS_FS is not set
927CONFIG_DNOTIFY=y
928CONFIG_INOTIFY=y
929CONFIG_INOTIFY_USER=y
930# CONFIG_QUOTA is not set
931CONFIG_AUTOFS_FS=y
932CONFIG_AUTOFS4_FS=y
933# CONFIG_FUSE_FS is not set
934CONFIG_GENERIC_ACL=y
935
936#
937# CD-ROM/DVD Filesystems
938#
939# CONFIG_ISO9660_FS is not set
940# CONFIG_UDF_FS is not set
941
942#
943# DOS/FAT/NT Filesystems
944#
945# CONFIG_MSDOS_FS is not set
946# CONFIG_VFAT_FS is not set
947# CONFIG_NTFS_FS is not set
948
949#
950# Pseudo filesystems
951#
952CONFIG_PROC_FS=y
953CONFIG_PROC_KCORE=y
954CONFIG_PROC_SYSCTL=y
955CONFIG_PROC_PAGE_MONITOR=y
956CONFIG_SYSFS=y
957CONFIG_TMPFS=y
958CONFIG_TMPFS_POSIX_ACL=y
959# CONFIG_HUGETLBFS is not set
960# CONFIG_HUGETLB_PAGE is not set
961# CONFIG_CONFIGFS_FS is not set
962CONFIG_MISC_FILESYSTEMS=y
963# CONFIG_ADFS_FS is not set
964# CONFIG_AFFS_FS is not set
965# CONFIG_HFS_FS is not set
966# CONFIG_HFSPLUS_FS is not set
967# CONFIG_BEFS_FS is not set
968# CONFIG_BFS_FS is not set
969# CONFIG_EFS_FS is not set
970# CONFIG_JFFS2_FS is not set
971CONFIG_CRAMFS=y
972# CONFIG_SQUASHFS is not set
973# CONFIG_VXFS_FS is not set
974# CONFIG_MINIX_FS is not set
975# CONFIG_OMFS_FS is not set
976# CONFIG_HPFS_FS is not set
977# CONFIG_QNX4FS_FS is not set
978CONFIG_ROMFS_FS=y
979# CONFIG_SYSV_FS is not set
980# CONFIG_UFS_FS is not set
981CONFIG_NETWORK_FILESYSTEMS=y
982CONFIG_NFS_FS=y
983# CONFIG_NFS_V3 is not set
984# CONFIG_NFS_V4 is not set
985CONFIG_ROOT_NFS=y
986# CONFIG_NFSD is not set
987CONFIG_LOCKD=y
988CONFIG_NFS_COMMON=y
989CONFIG_SUNRPC=y
990# CONFIG_SUNRPC_REGISTER_V4 is not set
991# CONFIG_RPCSEC_GSS_KRB5 is not set
992# CONFIG_RPCSEC_GSS_SPKM3 is not set
993# CONFIG_SMB_FS is not set
994# CONFIG_CIFS is not set
995# CONFIG_NCP_FS is not set
996# CONFIG_CODA_FS is not set
997# CONFIG_AFS_FS is not set
998
999#
1000# Partition Types
1001#
1002# CONFIG_PARTITION_ADVANCED is not set
1003CONFIG_MSDOS_PARTITION=y
1004CONFIG_NLS=y
1005CONFIG_NLS_DEFAULT="iso8859-1"
1006CONFIG_NLS_CODEPAGE_437=y
1007CONFIG_NLS_CODEPAGE_737=y
1008CONFIG_NLS_CODEPAGE_775=y
1009CONFIG_NLS_CODEPAGE_850=y
1010CONFIG_NLS_CODEPAGE_852=y
1011CONFIG_NLS_CODEPAGE_855=y
1012CONFIG_NLS_CODEPAGE_857=y
1013CONFIG_NLS_CODEPAGE_860=y
1014CONFIG_NLS_CODEPAGE_861=y
1015CONFIG_NLS_CODEPAGE_862=y
1016CONFIG_NLS_CODEPAGE_863=y
1017CONFIG_NLS_CODEPAGE_864=y
1018CONFIG_NLS_CODEPAGE_865=y
1019CONFIG_NLS_CODEPAGE_866=y
1020CONFIG_NLS_CODEPAGE_869=y
1021CONFIG_NLS_CODEPAGE_936=y
1022CONFIG_NLS_CODEPAGE_950=y
1023CONFIG_NLS_CODEPAGE_932=y
1024CONFIG_NLS_CODEPAGE_949=y
1025CONFIG_NLS_CODEPAGE_874=y
1026CONFIG_NLS_ISO8859_8=y
1027CONFIG_NLS_CODEPAGE_1250=y
1028CONFIG_NLS_CODEPAGE_1251=y
1029CONFIG_NLS_ASCII=y
1030CONFIG_NLS_ISO8859_1=y
1031CONFIG_NLS_ISO8859_2=y
1032CONFIG_NLS_ISO8859_3=y
1033CONFIG_NLS_ISO8859_4=y
1034CONFIG_NLS_ISO8859_5=y
1035CONFIG_NLS_ISO8859_6=y
1036CONFIG_NLS_ISO8859_7=y
1037CONFIG_NLS_ISO8859_9=y
1038CONFIG_NLS_ISO8859_13=y
1039CONFIG_NLS_ISO8859_14=y
1040CONFIG_NLS_ISO8859_15=y
1041CONFIG_NLS_KOI8_R=y
1042CONFIG_NLS_KOI8_U=y
1043CONFIG_NLS_UTF8=y
1044# CONFIG_DLM is not set
1045
1046#
1047# Kernel hacking
1048#
1049CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1050# CONFIG_PRINTK_TIME is not set
1051# CONFIG_ENABLE_WARN_DEPRECATED is not set
1052# CONFIG_ENABLE_MUST_CHECK is not set
1053CONFIG_FRAME_WARN=1024
1054# CONFIG_MAGIC_SYSRQ is not set
1055# CONFIG_UNUSED_SYMBOLS is not set
1056CONFIG_DEBUG_FS=y
1057# CONFIG_HEADERS_CHECK is not set
1058# CONFIG_DEBUG_KERNEL is not set
1059CONFIG_STACKTRACE=y
1060# CONFIG_DEBUG_BUGVERBOSE is not set
1061# CONFIG_DEBUG_MEMORY_INIT is not set
1062# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1063# CONFIG_LATENCYTOP is not set
1064CONFIG_NOP_TRACER=y
1065CONFIG_HAVE_FUNCTION_TRACER=y
1066CONFIG_HAVE_DYNAMIC_FTRACE=y
1067CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1068CONFIG_RING_BUFFER=y
1069CONFIG_TRACING=y
1070
1071#
1072# Tracers
1073#
1074# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
1075# CONFIG_SAMPLES is not set
1076CONFIG_HAVE_ARCH_KGDB=y
1077# CONFIG_SH_STANDARD_BIOS is not set
1078# CONFIG_EARLY_SCIF_CONSOLE is not set
1079# CONFIG_MORE_COMPILE_OPTIONS is not set
1080
1081#
1082# Security options
1083#
1084# CONFIG_KEYS is not set
1085# CONFIG_SECURITY is not set
1086# CONFIG_SECURITYFS is not set
1087# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1088CONFIG_CRYPTO=y
1089
1090#
1091# Crypto core or helper
1092#
1093# CONFIG_CRYPTO_FIPS is not set
1094# CONFIG_CRYPTO_MANAGER is not set
1095# CONFIG_CRYPTO_MANAGER2 is not set
1096# CONFIG_CRYPTO_GF128MUL is not set
1097# CONFIG_CRYPTO_NULL is not set
1098# CONFIG_CRYPTO_CRYPTD is not set
1099# CONFIG_CRYPTO_AUTHENC is not set
1100# CONFIG_CRYPTO_TEST is not set
1101
1102#
1103# Authenticated Encryption with Associated Data
1104#
1105# CONFIG_CRYPTO_CCM is not set
1106# CONFIG_CRYPTO_GCM is not set
1107# CONFIG_CRYPTO_SEQIV is not set
1108
1109#
1110# Block modes
1111#
1112# CONFIG_CRYPTO_CBC is not set
1113# CONFIG_CRYPTO_CTR is not set
1114# CONFIG_CRYPTO_CTS is not set
1115# CONFIG_CRYPTO_ECB is not set
1116# CONFIG_CRYPTO_LRW is not set
1117# CONFIG_CRYPTO_PCBC is not set
1118# CONFIG_CRYPTO_XTS is not set
1119
1120#
1121# Hash modes
1122#
1123# CONFIG_CRYPTO_HMAC is not set
1124# CONFIG_CRYPTO_XCBC is not set
1125
1126#
1127# Digest
1128#
1129# CONFIG_CRYPTO_CRC32C is not set
1130# CONFIG_CRYPTO_MD4 is not set
1131# CONFIG_CRYPTO_MD5 is not set
1132# CONFIG_CRYPTO_MICHAEL_MIC is not set
1133# CONFIG_CRYPTO_RMD128 is not set
1134# CONFIG_CRYPTO_RMD160 is not set
1135# CONFIG_CRYPTO_RMD256 is not set
1136# CONFIG_CRYPTO_RMD320 is not set
1137# CONFIG_CRYPTO_SHA1 is not set
1138# CONFIG_CRYPTO_SHA256 is not set
1139# CONFIG_CRYPTO_SHA512 is not set
1140# CONFIG_CRYPTO_TGR192 is not set
1141# CONFIG_CRYPTO_WP512 is not set
1142
1143#
1144# Ciphers
1145#
1146# CONFIG_CRYPTO_AES is not set
1147# CONFIG_CRYPTO_ANUBIS is not set
1148# CONFIG_CRYPTO_ARC4 is not set
1149# CONFIG_CRYPTO_BLOWFISH is not set
1150# CONFIG_CRYPTO_CAMELLIA is not set
1151# CONFIG_CRYPTO_CAST5 is not set
1152# CONFIG_CRYPTO_CAST6 is not set
1153# CONFIG_CRYPTO_DES is not set
1154# CONFIG_CRYPTO_FCRYPT is not set
1155# CONFIG_CRYPTO_KHAZAD is not set
1156# CONFIG_CRYPTO_SALSA20 is not set
1157# CONFIG_CRYPTO_SEED is not set
1158# CONFIG_CRYPTO_SERPENT is not set
1159# CONFIG_CRYPTO_TEA is not set
1160# CONFIG_CRYPTO_TWOFISH is not set
1161
1162#
1163# Compression
1164#
1165# CONFIG_CRYPTO_DEFLATE is not set
1166# CONFIG_CRYPTO_LZO is not set
1167
1168#
1169# Random Number Generation
1170#
1171# CONFIG_CRYPTO_ANSI_CPRNG is not set
1172CONFIG_CRYPTO_HW=y
1173
1174#
1175# Library routines
1176#
1177CONFIG_BITREVERSE=y
1178CONFIG_GENERIC_FIND_LAST_BIT=y
1179# CONFIG_CRC_CCITT is not set
1180# CONFIG_CRC16 is not set
1181CONFIG_CRC_T10DIF=y
1182# CONFIG_CRC_ITU_T is not set
1183CONFIG_CRC32=y
1184# CONFIG_CRC7 is not set
1185# CONFIG_LIBCRC32C is not set
1186CONFIG_ZLIB_INFLATE=y
1187CONFIG_PLIST=y
1188CONFIG_HAS_IOMEM=y
1189CONFIG_HAS_IOPORT=y
1190CONFIG_HAS_DMA=y
diff --git a/arch/sh/configs/polaris_defconfig b/arch/sh/configs/polaris_defconfig
new file mode 100644
index 000000000000..320def233b2f
--- /dev/null
+++ b/arch/sh/configs/polaris_defconfig
@@ -0,0 +1,969 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29-rc4
4# Wed Feb 11 18:41:59 2009
5#
6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y
11CONFIG_GENERIC_FIND_NEXT_BIT=y
12CONFIG_GENERIC_HWEIGHT=y
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
15CONFIG_GENERIC_IRQ_PROBE=y
16# CONFIG_GENERIC_GPIO is not set
17CONFIG_GENERIC_TIME=y
18CONFIG_GENERIC_CLOCKEVENTS=y
19# CONFIG_ARCH_SUSPEND_POSSIBLE is not set
20# CONFIG_ARCH_HIBERNATION_POSSIBLE is not set
21CONFIG_STACKTRACE_SUPPORT=y
22CONFIG_LOCKDEP_SUPPORT=y
23CONFIG_HAVE_LATENCYTOP_SUPPORT=y
24# CONFIG_ARCH_HAS_ILOG2_U32 is not set
25# CONFIG_ARCH_HAS_ILOG2_U64 is not set
26CONFIG_ARCH_NO_VIRT_TO_BUS=y
27CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
28
29#
30# General setup
31#
32CONFIG_EXPERIMENTAL=y
33CONFIG_BROKEN_ON_SMP=y
34CONFIG_LOCK_KERNEL=y
35CONFIG_INIT_ENV_ARG_LIMIT=32
36CONFIG_LOCALVERSION=""
37# CONFIG_LOCALVERSION_AUTO is not set
38# CONFIG_SWAP is not set
39CONFIG_SYSVIPC=y
40CONFIG_SYSVIPC_SYSCTL=y
41CONFIG_POSIX_MQUEUE=y
42CONFIG_BSD_PROCESS_ACCT=y
43CONFIG_BSD_PROCESS_ACCT_V3=y
44# CONFIG_TASKSTATS is not set
45CONFIG_AUDIT=y
46# CONFIG_AUDITSYSCALL is not set
47
48#
49# RCU Subsystem
50#
51CONFIG_CLASSIC_RCU=y
52# CONFIG_TREE_RCU is not set
53# CONFIG_PREEMPT_RCU is not set
54# CONFIG_TREE_RCU_TRACE is not set
55# CONFIG_PREEMPT_RCU_TRACE is not set
56# CONFIG_IKCONFIG is not set
57CONFIG_LOG_BUF_SHIFT=14
58CONFIG_GROUP_SCHED=y
59CONFIG_FAIR_GROUP_SCHED=y
60# CONFIG_RT_GROUP_SCHED is not set
61CONFIG_USER_SCHED=y
62# CONFIG_CGROUP_SCHED is not set
63# CONFIG_CGROUPS is not set
64CONFIG_SYSFS_DEPRECATED=y
65CONFIG_SYSFS_DEPRECATED_V2=y
66# CONFIG_RELAY is not set
67# CONFIG_NAMESPACES is not set
68# CONFIG_BLK_DEV_INITRD is not set
69# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
70CONFIG_SYSCTL=y
71CONFIG_EMBEDDED=y
72CONFIG_UID16=y
73CONFIG_SYSCTL_SYSCALL=y
74CONFIG_KALLSYMS=y
75CONFIG_KALLSYMS_ALL=y
76# CONFIG_KALLSYMS_EXTRA_PASS is not set
77CONFIG_HOTPLUG=y
78CONFIG_PRINTK=y
79CONFIG_BUG=y
80CONFIG_ELF_CORE=y
81CONFIG_COMPAT_BRK=y
82CONFIG_BASE_FULL=y
83CONFIG_FUTEX=y
84CONFIG_ANON_INODES=y
85CONFIG_EPOLL=y
86CONFIG_SIGNALFD=y
87CONFIG_TIMERFD=y
88CONFIG_EVENTFD=y
89CONFIG_SHMEM=y
90CONFIG_AIO=y
91CONFIG_VM_EVENT_COUNTERS=y
92CONFIG_SLAB=y
93# CONFIG_SLUB is not set
94# CONFIG_SLOB is not set
95# CONFIG_PROFILING is not set
96CONFIG_HAVE_OPROFILE=y
97# CONFIG_KPROBES is not set
98CONFIG_HAVE_IOREMAP_PROT=y
99CONFIG_HAVE_KPROBES=y
100CONFIG_HAVE_KRETPROBES=y
101CONFIG_HAVE_ARCH_TRACEHOOK=y
102CONFIG_HAVE_CLK=y
103CONFIG_HAVE_GENERIC_DMA_COHERENT=y
104CONFIG_SLABINFO=y
105CONFIG_RT_MUTEXES=y
106CONFIG_BASE_SMALL=0
107CONFIG_MODULES=y
108# CONFIG_MODULE_FORCE_LOAD is not set
109CONFIG_MODULE_UNLOAD=y
110# CONFIG_MODULE_FORCE_UNLOAD is not set
111CONFIG_MODVERSIONS=y
112# CONFIG_MODULE_SRCVERSION_ALL is not set
113CONFIG_BLOCK=y
114# CONFIG_LBD is not set
115# CONFIG_BLK_DEV_IO_TRACE is not set
116# CONFIG_BLK_DEV_BSG is not set
117# CONFIG_BLK_DEV_INTEGRITY is not set
118
119#
120# IO Schedulers
121#
122CONFIG_IOSCHED_NOOP=y
123# CONFIG_IOSCHED_AS is not set
124# CONFIG_IOSCHED_DEADLINE is not set
125CONFIG_IOSCHED_CFQ=y
126# CONFIG_DEFAULT_AS is not set
127# CONFIG_DEFAULT_DEADLINE is not set
128CONFIG_DEFAULT_CFQ=y
129# CONFIG_DEFAULT_NOOP is not set
130CONFIG_DEFAULT_IOSCHED="cfq"
131# CONFIG_FREEZER is not set
132
133#
134# System type
135#
136CONFIG_CPU_SH3=y
137# CONFIG_CPU_SUBTYPE_SH7619 is not set
138# CONFIG_CPU_SUBTYPE_SH7201 is not set
139# CONFIG_CPU_SUBTYPE_SH7203 is not set
140# CONFIG_CPU_SUBTYPE_SH7206 is not set
141# CONFIG_CPU_SUBTYPE_SH7263 is not set
142# CONFIG_CPU_SUBTYPE_MXG is not set
143# CONFIG_CPU_SUBTYPE_SH7705 is not set
144# CONFIG_CPU_SUBTYPE_SH7706 is not set
145# CONFIG_CPU_SUBTYPE_SH7707 is not set
146# CONFIG_CPU_SUBTYPE_SH7708 is not set
147CONFIG_CPU_SUBTYPE_SH7709=y
148# CONFIG_CPU_SUBTYPE_SH7710 is not set
149# CONFIG_CPU_SUBTYPE_SH7712 is not set
150# CONFIG_CPU_SUBTYPE_SH7720 is not set
151# CONFIG_CPU_SUBTYPE_SH7721 is not set
152# CONFIG_CPU_SUBTYPE_SH7750 is not set
153# CONFIG_CPU_SUBTYPE_SH7091 is not set
154# CONFIG_CPU_SUBTYPE_SH7750R is not set
155# CONFIG_CPU_SUBTYPE_SH7750S is not set
156# CONFIG_CPU_SUBTYPE_SH7751 is not set
157# CONFIG_CPU_SUBTYPE_SH7751R is not set
158# CONFIG_CPU_SUBTYPE_SH7760 is not set
159# CONFIG_CPU_SUBTYPE_SH4_202 is not set
160# CONFIG_CPU_SUBTYPE_SH7723 is not set
161# CONFIG_CPU_SUBTYPE_SH7763 is not set
162# CONFIG_CPU_SUBTYPE_SH7770 is not set
163# CONFIG_CPU_SUBTYPE_SH7780 is not set
164# CONFIG_CPU_SUBTYPE_SH7785 is not set
165# CONFIG_CPU_SUBTYPE_SHX3 is not set
166# CONFIG_CPU_SUBTYPE_SH7343 is not set
167# CONFIG_CPU_SUBTYPE_SH7722 is not set
168# CONFIG_CPU_SUBTYPE_SH7366 is not set
169# CONFIG_CPU_SUBTYPE_SH5_101 is not set
170# CONFIG_CPU_SUBTYPE_SH5_103 is not set
171
172#
173# Memory management options
174#
175CONFIG_QUICKLIST=y
176CONFIG_MMU=y
177CONFIG_PAGE_OFFSET=0x80000000
178CONFIG_MEMORY_START=0x0C000000
179CONFIG_MEMORY_SIZE=0x04000000
180CONFIG_29BIT=y
181CONFIG_VSYSCALL=y
182CONFIG_ARCH_FLATMEM_ENABLE=y
183CONFIG_ARCH_SPARSEMEM_ENABLE=y
184CONFIG_ARCH_SPARSEMEM_DEFAULT=y
185CONFIG_MAX_ACTIVE_REGIONS=1
186CONFIG_ARCH_POPULATES_NODE_MAP=y
187CONFIG_ARCH_SELECT_MEMORY_MODEL=y
188CONFIG_PAGE_SIZE_4KB=y
189# CONFIG_PAGE_SIZE_8KB is not set
190# CONFIG_PAGE_SIZE_16KB is not set
191# CONFIG_PAGE_SIZE_64KB is not set
192CONFIG_ENTRY_OFFSET=0x00001000
193CONFIG_SELECT_MEMORY_MODEL=y
194CONFIG_FLATMEM_MANUAL=y
195# CONFIG_DISCONTIGMEM_MANUAL is not set
196# CONFIG_SPARSEMEM_MANUAL is not set
197CONFIG_FLATMEM=y
198CONFIG_FLAT_NODE_MEM_MAP=y
199CONFIG_SPARSEMEM_STATIC=y
200CONFIG_PAGEFLAGS_EXTENDED=y
201CONFIG_SPLIT_PTLOCK_CPUS=4
202# CONFIG_PHYS_ADDR_T_64BIT is not set
203CONFIG_ZONE_DMA_FLAG=0
204CONFIG_NR_QUICK=2
205CONFIG_UNEVICTABLE_LRU=y
206
207#
208# Cache configuration
209#
210# CONFIG_SH_DIRECT_MAPPED is not set
211CONFIG_CACHE_WRITEBACK=y
212# CONFIG_CACHE_WRITETHROUGH is not set
213# CONFIG_CACHE_OFF is not set
214
215#
216# Processor features
217#
218CONFIG_CPU_LITTLE_ENDIAN=y
219# CONFIG_CPU_BIG_ENDIAN is not set
220CONFIG_SH_FPU_EMU=y
221CONFIG_SH_ADC=y
222CONFIG_CPU_HAS_INTEVT=y
223CONFIG_CPU_HAS_IPR_IRQ=y
224CONFIG_CPU_HAS_SR_RB=y
225
226#
227# Board support
228#
229# CONFIG_SH_SOLUTION_ENGINE is not set
230# CONFIG_SH_HP6XX is not set
231CONFIG_SH_POLARIS=y
232
233#
234# Timer and clock configuration
235#
236CONFIG_SH_TMU=y
237CONFIG_SH_TIMER_IRQ=16
238CONFIG_SH_PCLK_FREQ=33000000
239CONFIG_TICK_ONESHOT=y
240CONFIG_NO_HZ=y
241CONFIG_HIGH_RES_TIMERS=y
242CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
243
244#
245# CPU Frequency scaling
246#
247# CONFIG_CPU_FREQ is not set
248
249#
250# DMA support
251#
252CONFIG_SH_DMA_API=y
253CONFIG_SH_DMA=y
254CONFIG_NR_ONCHIP_DMA_CHANNELS=4
255# CONFIG_NR_DMA_CHANNELS_BOOL is not set
256
257#
258# Companion Chips
259#
260
261#
262# Additional SuperH Device Drivers
263#
264CONFIG_HEARTBEAT=y
265# CONFIG_PUSH_SWITCH is not set
266
267#
268# Kernel features
269#
270CONFIG_HZ_100=y
271# CONFIG_HZ_250 is not set
272# CONFIG_HZ_300 is not set
273# CONFIG_HZ_1000 is not set
274CONFIG_HZ=100
275CONFIG_SCHED_HRTICK=y
276# CONFIG_KEXEC is not set
277# CONFIG_CRASH_DUMP is not set
278# CONFIG_SECCOMP is not set
279# CONFIG_PREEMPT_NONE is not set
280# CONFIG_PREEMPT_VOLUNTARY is not set
281CONFIG_PREEMPT=y
282CONFIG_GUSA=y
283# CONFIG_GUSA_RB is not set
284
285#
286# Boot options
287#
288CONFIG_ZERO_PAGE_OFFSET=0x00001000
289CONFIG_BOOT_LINK_OFFSET=0x00800000
290CONFIG_CMDLINE_BOOL=y
291CONFIG_CMDLINE="console=ttySC1,115200 root=/dev/mtdblock2 rootfstype=jffs2 mem=63M mtdparts=physmap-flash.0:0x00100000(bootloader)ro,0x00500000(Kernel)ro,0x00A00000(Filesystem)"
292
293#
294# Bus options
295#
296# CONFIG_ARCH_SUPPORTS_MSI is not set
297# CONFIG_PCCARD is not set
298
299#
300# Executable file formats
301#
302CONFIG_BINFMT_ELF=y
303# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
304# CONFIG_HAVE_AOUT is not set
305# CONFIG_BINFMT_MISC is not set
306
307#
308# Power management options (EXPERIMENTAL)
309#
310# CONFIG_PM is not set
311# CONFIG_CPU_IDLE is not set
312CONFIG_NET=y
313
314#
315# Networking options
316#
317CONFIG_COMPAT_NET_DEV_OPS=y
318CONFIG_PACKET=y
319CONFIG_PACKET_MMAP=y
320CONFIG_UNIX=y
321# CONFIG_NET_KEY is not set
322CONFIG_INET=y
323CONFIG_IP_MULTICAST=y
324# CONFIG_IP_ADVANCED_ROUTER is not set
325CONFIG_IP_FIB_HASH=y
326# CONFIG_IP_PNP is not set
327# CONFIG_NET_IPIP is not set
328# CONFIG_NET_IPGRE is not set
329# CONFIG_IP_MROUTE is not set
330# CONFIG_ARPD is not set
331# CONFIG_SYN_COOKIES is not set
332# CONFIG_INET_AH is not set
333# CONFIG_INET_ESP is not set
334# CONFIG_INET_IPCOMP is not set
335# CONFIG_INET_XFRM_TUNNEL is not set
336# CONFIG_INET_TUNNEL is not set
337# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
338# CONFIG_INET_XFRM_MODE_TUNNEL is not set
339# CONFIG_INET_XFRM_MODE_BEET is not set
340# CONFIG_INET_LRO is not set
341CONFIG_INET_DIAG=y
342CONFIG_INET_TCP_DIAG=y
343# CONFIG_TCP_CONG_ADVANCED is not set
344CONFIG_TCP_CONG_CUBIC=y
345CONFIG_DEFAULT_TCP_CONG="cubic"
346# CONFIG_TCP_MD5SIG is not set
347# CONFIG_IPV6 is not set
348# CONFIG_NETWORK_SECMARK is not set
349# CONFIG_NETFILTER is not set
350# CONFIG_IP_DCCP is not set
351# CONFIG_IP_SCTP is not set
352# CONFIG_TIPC is not set
353# CONFIG_ATM is not set
354# CONFIG_BRIDGE is not set
355# CONFIG_NET_DSA is not set
356# CONFIG_VLAN_8021Q is not set
357# CONFIG_DECNET is not set
358# CONFIG_LLC2 is not set
359# CONFIG_IPX is not set
360# CONFIG_ATALK is not set
361# CONFIG_X25 is not set
362# CONFIG_LAPB is not set
363# CONFIG_ECONET is not set
364# CONFIG_WAN_ROUTER is not set
365# CONFIG_NET_SCHED is not set
366# CONFIG_DCB is not set
367
368#
369# Network testing
370#
371# CONFIG_NET_PKTGEN is not set
372# CONFIG_HAMRADIO is not set
373# CONFIG_CAN is not set
374# CONFIG_IRDA is not set
375# CONFIG_BT is not set
376# CONFIG_AF_RXRPC is not set
377# CONFIG_PHONET is not set
378# CONFIG_WIRELESS is not set
379# CONFIG_WIMAX is not set
380# CONFIG_RFKILL is not set
381# CONFIG_NET_9P is not set
382
383#
384# Device Drivers
385#
386
387#
388# Generic Driver Options
389#
390CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
391CONFIG_STANDALONE=y
392CONFIG_PREVENT_FIRMWARE_BUILD=y
393CONFIG_FW_LOADER=y
394# CONFIG_FIRMWARE_IN_KERNEL is not set
395CONFIG_EXTRA_FIRMWARE=""
396# CONFIG_DEBUG_DRIVER is not set
397# CONFIG_DEBUG_DEVRES is not set
398# CONFIG_SYS_HYPERVISOR is not set
399# CONFIG_CONNECTOR is not set
400CONFIG_MTD=y
401# CONFIG_MTD_DEBUG is not set
402# CONFIG_MTD_CONCAT is not set
403CONFIG_MTD_PARTITIONS=y
404# CONFIG_MTD_TESTS is not set
405# CONFIG_MTD_REDBOOT_PARTS is not set
406CONFIG_MTD_CMDLINE_PARTS=y
407# CONFIG_MTD_AR7_PARTS is not set
408
409#
410# User Modules And Translation Layers
411#
412CONFIG_MTD_CHAR=y
413CONFIG_MTD_BLKDEVS=y
414CONFIG_MTD_BLOCK=y
415# CONFIG_FTL is not set
416# CONFIG_NFTL is not set
417# CONFIG_INFTL is not set
418# CONFIG_RFD_FTL is not set
419# CONFIG_SSFDC is not set
420# CONFIG_MTD_OOPS is not set
421
422#
423# RAM/ROM/Flash chip drivers
424#
425CONFIG_MTD_CFI=y
426# CONFIG_MTD_JEDECPROBE is not set
427CONFIG_MTD_GEN_PROBE=y
428CONFIG_MTD_CFI_ADV_OPTIONS=y
429CONFIG_MTD_CFI_NOSWAP=y
430# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
431# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
432# CONFIG_MTD_CFI_GEOMETRY is not set
433CONFIG_MTD_MAP_BANK_WIDTH_1=y
434CONFIG_MTD_MAP_BANK_WIDTH_2=y
435CONFIG_MTD_MAP_BANK_WIDTH_4=y
436# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
437# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
438# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
439CONFIG_MTD_CFI_I1=y
440CONFIG_MTD_CFI_I2=y
441# CONFIG_MTD_CFI_I4 is not set
442# CONFIG_MTD_CFI_I8 is not set
443# CONFIG_MTD_OTP is not set
444CONFIG_MTD_CFI_INTELEXT=y
445# CONFIG_MTD_CFI_AMDSTD is not set
446# CONFIG_MTD_CFI_STAA is not set
447CONFIG_MTD_CFI_UTIL=y
448# CONFIG_MTD_RAM is not set
449# CONFIG_MTD_ROM is not set
450# CONFIG_MTD_ABSENT is not set
451
452#
453# Mapping drivers for chip access
454#
455# CONFIG_MTD_COMPLEX_MAPPINGS is not set
456CONFIG_MTD_PHYSMAP=y
457CONFIG_MTD_PHYSMAP_COMPAT=y
458CONFIG_MTD_PHYSMAP_START=0x00000000
459CONFIG_MTD_PHYSMAP_LEN=0x01000000
460CONFIG_MTD_PHYSMAP_BANKWIDTH=2
461# CONFIG_MTD_PLATRAM is not set
462
463#
464# Self-contained MTD device drivers
465#
466# CONFIG_MTD_SLRAM is not set
467# CONFIG_MTD_PHRAM is not set
468# CONFIG_MTD_MTDRAM is not set
469# CONFIG_MTD_BLOCK2MTD is not set
470
471#
472# Disk-On-Chip Device Drivers
473#
474# CONFIG_MTD_DOC2000 is not set
475# CONFIG_MTD_DOC2001 is not set
476# CONFIG_MTD_DOC2001PLUS is not set
477# CONFIG_MTD_NAND is not set
478# CONFIG_MTD_ONENAND is not set
479
480#
481# LPDDR flash memory drivers
482#
483# CONFIG_MTD_LPDDR is not set
484# CONFIG_MTD_QINFO_PROBE is not set
485
486#
487# UBI - Unsorted block images
488#
489# CONFIG_MTD_UBI is not set
490# CONFIG_PARPORT is not set
491CONFIG_BLK_DEV=y
492# CONFIG_BLK_DEV_COW_COMMON is not set
493# CONFIG_BLK_DEV_LOOP is not set
494# CONFIG_BLK_DEV_NBD is not set
495# CONFIG_BLK_DEV_RAM is not set
496# CONFIG_CDROM_PKTCDVD is not set
497# CONFIG_ATA_OVER_ETH is not set
498# CONFIG_BLK_DEV_HD is not set
499CONFIG_MISC_DEVICES=y
500# CONFIG_ENCLOSURE_SERVICES is not set
501# CONFIG_C2PORT is not set
502
503#
504# EEPROM support
505#
506# CONFIG_EEPROM_93CX6 is not set
507CONFIG_HAVE_IDE=y
508# CONFIG_IDE is not set
509
510#
511# SCSI device support
512#
513# CONFIG_RAID_ATTRS is not set
514# CONFIG_SCSI is not set
515# CONFIG_SCSI_DMA is not set
516# CONFIG_SCSI_NETLINK is not set
517# CONFIG_ATA is not set
518# CONFIG_MD is not set
519CONFIG_NETDEVICES=y
520# CONFIG_DUMMY is not set
521# CONFIG_BONDING is not set
522# CONFIG_MACVLAN is not set
523# CONFIG_EQUALIZER is not set
524# CONFIG_TUN is not set
525# CONFIG_VETH is not set
526CONFIG_PHYLIB=y
527
528#
529# MII PHY device drivers
530#
531# CONFIG_MARVELL_PHY is not set
532# CONFIG_DAVICOM_PHY is not set
533# CONFIG_QSEMI_PHY is not set
534# CONFIG_LXT_PHY is not set
535# CONFIG_CICADA_PHY is not set
536# CONFIG_VITESSE_PHY is not set
537CONFIG_SMSC_PHY=y
538# CONFIG_BROADCOM_PHY is not set
539# CONFIG_ICPLUS_PHY is not set
540# CONFIG_REALTEK_PHY is not set
541# CONFIG_NATIONAL_PHY is not set
542# CONFIG_STE10XP is not set
543# CONFIG_LSI_ET1011C_PHY is not set
544# CONFIG_FIXED_PHY is not set
545# CONFIG_MDIO_BITBANG is not set
546CONFIG_NET_ETHERNET=y
547CONFIG_MII=y
548# CONFIG_AX88796 is not set
549# CONFIG_STNIC is not set
550# CONFIG_SMC91X is not set
551# CONFIG_SMC911X is not set
552CONFIG_SMSC911X=y
553# CONFIG_IBM_NEW_EMAC_ZMII is not set
554# CONFIG_IBM_NEW_EMAC_RGMII is not set
555# CONFIG_IBM_NEW_EMAC_TAH is not set
556# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
557# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
558# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
559# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
560# CONFIG_B44 is not set
561# CONFIG_NETDEV_1000 is not set
562# CONFIG_NETDEV_10000 is not set
563
564#
565# Wireless LAN
566#
567# CONFIG_WLAN_PRE80211 is not set
568# CONFIG_WLAN_80211 is not set
569# CONFIG_IWLWIFI_LEDS is not set
570
571#
572# Enable WiMAX (Networking options) to see the WiMAX drivers
573#
574# CONFIG_WAN is not set
575# CONFIG_PPP is not set
576# CONFIG_SLIP is not set
577# CONFIG_NETCONSOLE is not set
578# CONFIG_NETPOLL is not set
579# CONFIG_NET_POLL_CONTROLLER is not set
580# CONFIG_ISDN is not set
581# CONFIG_PHONE is not set
582
583#
584# Input device support
585#
586CONFIG_INPUT=y
587# CONFIG_INPUT_FF_MEMLESS is not set
588# CONFIG_INPUT_POLLDEV is not set
589
590#
591# Userland interfaces
592#
593# CONFIG_INPUT_MOUSEDEV is not set
594# CONFIG_INPUT_JOYDEV is not set
595# CONFIG_INPUT_EVDEV is not set
596# CONFIG_INPUT_EVBUG is not set
597
598#
599# Input Device Drivers
600#
601# CONFIG_INPUT_KEYBOARD is not set
602# CONFIG_INPUT_MOUSE is not set
603# CONFIG_INPUT_JOYSTICK is not set
604# CONFIG_INPUT_TABLET is not set
605# CONFIG_INPUT_TOUCHSCREEN is not set
606# CONFIG_INPUT_MISC is not set
607
608#
609# Hardware I/O ports
610#
611# CONFIG_SERIO is not set
612# CONFIG_GAMEPORT is not set
613
614#
615# Character devices
616#
617CONFIG_VT=y
618CONFIG_CONSOLE_TRANSLATIONS=y
619CONFIG_VT_CONSOLE=y
620CONFIG_HW_CONSOLE=y
621CONFIG_VT_HW_CONSOLE_BINDING=y
622CONFIG_DEVKMEM=y
623CONFIG_SERIAL_NONSTANDARD=y
624# CONFIG_N_HDLC is not set
625# CONFIG_RISCOM8 is not set
626# CONFIG_SPECIALIX is not set
627# CONFIG_RIO is not set
628# CONFIG_STALDRV is not set
629
630#
631# Serial drivers
632#
633# CONFIG_SERIAL_8250 is not set
634
635#
636# Non-8250 serial port support
637#
638CONFIG_SERIAL_SH_SCI=y
639CONFIG_SERIAL_SH_SCI_NR_UARTS=3
640CONFIG_SERIAL_SH_SCI_CONSOLE=y
641CONFIG_SERIAL_CORE=y
642CONFIG_SERIAL_CORE_CONSOLE=y
643CONFIG_UNIX98_PTYS=y
644# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
645# CONFIG_LEGACY_PTYS is not set
646# CONFIG_IPMI_HANDLER is not set
647# CONFIG_HW_RANDOM is not set
648# CONFIG_R3964 is not set
649# CONFIG_RAW_DRIVER is not set
650# CONFIG_TCG_TPM is not set
651# CONFIG_I2C is not set
652# CONFIG_SPI is not set
653# CONFIG_W1 is not set
654# CONFIG_POWER_SUPPLY is not set
655# CONFIG_HWMON is not set
656# CONFIG_THERMAL is not set
657# CONFIG_THERMAL_HWMON is not set
658# CONFIG_WATCHDOG is not set
659CONFIG_SSB_POSSIBLE=y
660
661#
662# Sonics Silicon Backplane
663#
664# CONFIG_SSB is not set
665
666#
667# Multifunction device drivers
668#
669# CONFIG_MFD_CORE is not set
670# CONFIG_MFD_SM501 is not set
671# CONFIG_HTC_PASIC3 is not set
672# CONFIG_MFD_TMIO is not set
673# CONFIG_REGULATOR is not set
674
675#
676# Multimedia devices
677#
678
679#
680# Multimedia core support
681#
682# CONFIG_VIDEO_DEV is not set
683# CONFIG_DVB_CORE is not set
684# CONFIG_VIDEO_MEDIA is not set
685
686#
687# Multimedia drivers
688#
689# CONFIG_DAB is not set
690
691#
692# Graphics support
693#
694# CONFIG_VGASTATE is not set
695# CONFIG_VIDEO_OUTPUT_CONTROL is not set
696# CONFIG_FB is not set
697# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
698
699#
700# Display device support
701#
702# CONFIG_DISPLAY_SUPPORT is not set
703
704#
705# Console display driver support
706#
707CONFIG_DUMMY_CONSOLE=y
708# CONFIG_SOUND is not set
709# CONFIG_HID_SUPPORT is not set
710# CONFIG_USB_SUPPORT is not set
711# CONFIG_MMC is not set
712# CONFIG_MEMSTICK is not set
713# CONFIG_NEW_LEDS is not set
714# CONFIG_ACCESSIBILITY is not set
715CONFIG_RTC_LIB=y
716CONFIG_RTC_CLASS=y
717CONFIG_RTC_HCTOSYS=y
718CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
719# CONFIG_RTC_DEBUG is not set
720
721#
722# RTC interfaces
723#
724CONFIG_RTC_INTF_SYSFS=y
725CONFIG_RTC_INTF_PROC=y
726CONFIG_RTC_INTF_DEV=y
727# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
728# CONFIG_RTC_DRV_TEST is not set
729
730#
731# SPI RTC drivers
732#
733
734#
735# Platform RTC drivers
736#
737# CONFIG_RTC_DRV_DS1286 is not set
738# CONFIG_RTC_DRV_DS1511 is not set
739# CONFIG_RTC_DRV_DS1553 is not set
740# CONFIG_RTC_DRV_DS1742 is not set
741# CONFIG_RTC_DRV_STK17TA8 is not set
742# CONFIG_RTC_DRV_M48T86 is not set
743# CONFIG_RTC_DRV_M48T35 is not set
744# CONFIG_RTC_DRV_M48T59 is not set
745# CONFIG_RTC_DRV_BQ4802 is not set
746# CONFIG_RTC_DRV_V3020 is not set
747
748#
749# on-CPU RTC drivers
750#
751CONFIG_RTC_DRV_SH=y
752# CONFIG_DMADEVICES is not set
753# CONFIG_UIO is not set
754# CONFIG_STAGING is not set
755
756#
757# File systems
758#
759# CONFIG_EXT2_FS is not set
760# CONFIG_EXT3_FS is not set
761# CONFIG_EXT4_FS is not set
762# CONFIG_REISERFS_FS is not set
763# CONFIG_JFS_FS is not set
764# CONFIG_FS_POSIX_ACL is not set
765CONFIG_FILE_LOCKING=y
766# CONFIG_XFS_FS is not set
767# CONFIG_OCFS2_FS is not set
768# CONFIG_BTRFS_FS is not set
769# CONFIG_DNOTIFY is not set
770# CONFIG_INOTIFY is not set
771# CONFIG_QUOTA is not set
772# CONFIG_AUTOFS_FS is not set
773# CONFIG_AUTOFS4_FS is not set
774# CONFIG_FUSE_FS is not set
775
776#
777# CD-ROM/DVD Filesystems
778#
779# CONFIG_ISO9660_FS is not set
780# CONFIG_UDF_FS is not set
781
782#
783# DOS/FAT/NT Filesystems
784#
785# CONFIG_MSDOS_FS is not set
786# CONFIG_VFAT_FS is not set
787# CONFIG_NTFS_FS is not set
788
789#
790# Pseudo filesystems
791#
792CONFIG_PROC_FS=y
793CONFIG_PROC_KCORE=y
794CONFIG_PROC_SYSCTL=y
795CONFIG_PROC_PAGE_MONITOR=y
796CONFIG_SYSFS=y
797CONFIG_TMPFS=y
798# CONFIG_TMPFS_POSIX_ACL is not set
799# CONFIG_HUGETLBFS is not set
800# CONFIG_HUGETLB_PAGE is not set
801# CONFIG_CONFIGFS_FS is not set
802CONFIG_MISC_FILESYSTEMS=y
803# CONFIG_ADFS_FS is not set
804# CONFIG_AFFS_FS is not set
805# CONFIG_HFS_FS is not set
806# CONFIG_HFSPLUS_FS is not set
807# CONFIG_BEFS_FS is not set
808# CONFIG_BFS_FS is not set
809# CONFIG_EFS_FS is not set
810CONFIG_JFFS2_FS=y
811CONFIG_JFFS2_FS_DEBUG=0
812# CONFIG_JFFS2_FS_WRITEBUFFER is not set
813# CONFIG_JFFS2_SUMMARY is not set
814# CONFIG_JFFS2_FS_XATTR is not set
815# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
816CONFIG_JFFS2_ZLIB=y
817# CONFIG_JFFS2_LZO is not set
818CONFIG_JFFS2_RTIME=y
819# CONFIG_JFFS2_RUBIN is not set
820# CONFIG_CRAMFS is not set
821# CONFIG_SQUASHFS is not set
822# CONFIG_VXFS_FS is not set
823# CONFIG_MINIX_FS is not set
824# CONFIG_OMFS_FS is not set
825# CONFIG_HPFS_FS is not set
826# CONFIG_QNX4FS_FS is not set
827# CONFIG_ROMFS_FS is not set
828# CONFIG_SYSV_FS is not set
829# CONFIG_UFS_FS is not set
830CONFIG_NETWORK_FILESYSTEMS=y
831CONFIG_NFS_FS=y
832CONFIG_NFS_V3=y
833# CONFIG_NFS_V3_ACL is not set
834# CONFIG_NFS_V4 is not set
835# CONFIG_NFSD is not set
836CONFIG_LOCKD=y
837CONFIG_LOCKD_V4=y
838CONFIG_NFS_COMMON=y
839CONFIG_SUNRPC=y
840# CONFIG_SUNRPC_REGISTER_V4 is not set
841# CONFIG_RPCSEC_GSS_KRB5 is not set
842# CONFIG_RPCSEC_GSS_SPKM3 is not set
843# CONFIG_SMB_FS is not set
844# CONFIG_CIFS is not set
845# CONFIG_NCP_FS is not set
846# CONFIG_CODA_FS is not set
847# CONFIG_AFS_FS is not set
848
849#
850# Partition Types
851#
852# CONFIG_PARTITION_ADVANCED is not set
853CONFIG_MSDOS_PARTITION=y
854# CONFIG_NLS is not set
855# CONFIG_DLM is not set
856
857#
858# Kernel hacking
859#
860CONFIG_TRACE_IRQFLAGS_SUPPORT=y
861# CONFIG_PRINTK_TIME is not set
862CONFIG_ENABLE_WARN_DEPRECATED=y
863CONFIG_ENABLE_MUST_CHECK=y
864CONFIG_FRAME_WARN=1024
865# CONFIG_MAGIC_SYSRQ is not set
866# CONFIG_UNUSED_SYMBOLS is not set
867# CONFIG_DEBUG_FS is not set
868# CONFIG_HEADERS_CHECK is not set
869CONFIG_DEBUG_KERNEL=y
870CONFIG_DEBUG_SHIRQ=y
871CONFIG_DETECT_SOFTLOCKUP=y
872# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
873CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
874# CONFIG_SCHED_DEBUG is not set
875# CONFIG_SCHEDSTATS is not set
876# CONFIG_TIMER_STATS is not set
877# CONFIG_DEBUG_OBJECTS is not set
878# CONFIG_DEBUG_SLAB is not set
879CONFIG_DEBUG_PREEMPT=y
880CONFIG_DEBUG_RT_MUTEXES=y
881CONFIG_DEBUG_PI_LIST=y
882# CONFIG_RT_MUTEX_TESTER is not set
883CONFIG_DEBUG_SPINLOCK=y
884CONFIG_DEBUG_MUTEXES=y
885CONFIG_DEBUG_LOCK_ALLOC=y
886# CONFIG_PROVE_LOCKING is not set
887CONFIG_LOCKDEP=y
888# CONFIG_LOCK_STAT is not set
889# CONFIG_DEBUG_LOCKDEP is not set
890CONFIG_DEBUG_SPINLOCK_SLEEP=y
891# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
892CONFIG_STACKTRACE=y
893# CONFIG_DEBUG_KOBJECT is not set
894CONFIG_DEBUG_BUGVERBOSE=y
895CONFIG_DEBUG_INFO=y
896# CONFIG_DEBUG_VM is not set
897# CONFIG_DEBUG_WRITECOUNT is not set
898# CONFIG_DEBUG_MEMORY_INIT is not set
899# CONFIG_DEBUG_LIST is not set
900CONFIG_DEBUG_SG=y
901# CONFIG_DEBUG_NOTIFIERS is not set
902CONFIG_FRAME_POINTER=y
903# CONFIG_RCU_TORTURE_TEST is not set
904# CONFIG_RCU_CPU_STALL_DETECTOR is not set
905# CONFIG_BACKTRACE_SELF_TEST is not set
906# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
907# CONFIG_FAULT_INJECTION is not set
908# CONFIG_LATENCYTOP is not set
909CONFIG_SYSCTL_SYSCALL_CHECK=y
910CONFIG_HAVE_FUNCTION_TRACER=y
911CONFIG_HAVE_DYNAMIC_FTRACE=y
912CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
913
914#
915# Tracers
916#
917# CONFIG_FUNCTION_TRACER is not set
918# CONFIG_IRQSOFF_TRACER is not set
919# CONFIG_PREEMPT_TRACER is not set
920# CONFIG_SCHED_TRACER is not set
921# CONFIG_CONTEXT_SWITCH_TRACER is not set
922# CONFIG_BOOT_TRACER is not set
923# CONFIG_TRACE_BRANCH_PROFILING is not set
924# CONFIG_STACK_TRACER is not set
925# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
926# CONFIG_SAMPLES is not set
927CONFIG_HAVE_ARCH_KGDB=y
928# CONFIG_KGDB is not set
929# CONFIG_SH_STANDARD_BIOS is not set
930CONFIG_EARLY_SCIF_CONSOLE=y
931CONFIG_EARLY_SCIF_CONSOLE_PORT=0x00000000
932CONFIG_EARLY_PRINTK=y
933# CONFIG_DEBUG_BOOTMEM is not set
934# CONFIG_DEBUG_STACKOVERFLOW is not set
935# CONFIG_DEBUG_STACK_USAGE is not set
936# CONFIG_4KSTACKS is not set
937# CONFIG_IRQSTACKS is not set
938CONFIG_DUMP_CODE=y
939# CONFIG_SH_NO_BSS_INIT is not set
940# CONFIG_MORE_COMPILE_OPTIONS is not set
941
942#
943# Security options
944#
945# CONFIG_KEYS is not set
946# CONFIG_SECURITY is not set
947# CONFIG_SECURITYFS is not set
948# CONFIG_SECURITY_FILE_CAPABILITIES is not set
949# CONFIG_CRYPTO is not set
950
951#
952# Library routines
953#
954CONFIG_BITREVERSE=y
955CONFIG_GENERIC_FIND_LAST_BIT=y
956# CONFIG_CRC_CCITT is not set
957# CONFIG_CRC16 is not set
958# CONFIG_CRC_T10DIF is not set
959# CONFIG_CRC_ITU_T is not set
960CONFIG_CRC32=y
961# CONFIG_CRC7 is not set
962# CONFIG_LIBCRC32C is not set
963CONFIG_AUDIT_GENERIC=y
964CONFIG_ZLIB_INFLATE=y
965CONFIG_ZLIB_DEFLATE=y
966CONFIG_PLIST=y
967CONFIG_HAS_IOMEM=y
968CONFIG_HAS_IOPORT=y
969CONFIG_HAS_DMA=y
diff --git a/arch/sh/configs/sh7785lcr_32bit_defconfig b/arch/sh/configs/sh7785lcr_32bit_defconfig
new file mode 100644
index 000000000000..54e1dee8e24a
--- /dev/null
+++ b/arch/sh/configs/sh7785lcr_32bit_defconfig
@@ -0,0 +1,1553 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29-rc4
4# Fri Feb 20 18:25:29 2009
5#
6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y
11CONFIG_GENERIC_FIND_NEXT_BIT=y
12CONFIG_GENERIC_HWEIGHT=y
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
15CONFIG_GENERIC_IRQ_PROBE=y
16# CONFIG_GENERIC_GPIO is not set
17CONFIG_GENERIC_TIME=y
18CONFIG_GENERIC_CLOCKEVENTS=y
19# CONFIG_ARCH_SUSPEND_POSSIBLE is not set
20# CONFIG_ARCH_HIBERNATION_POSSIBLE is not set
21CONFIG_SYS_SUPPORTS_NUMA=y
22CONFIG_SYS_SUPPORTS_PCI=y
23CONFIG_STACKTRACE_SUPPORT=y
24CONFIG_LOCKDEP_SUPPORT=y
25CONFIG_HAVE_LATENCYTOP_SUPPORT=y
26# CONFIG_ARCH_HAS_ILOG2_U32 is not set
27# CONFIG_ARCH_HAS_ILOG2_U64 is not set
28CONFIG_ARCH_NO_VIRT_TO_BUS=y
29CONFIG_IO_TRAPPED=y
30CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
31
32#
33# General setup
34#
35CONFIG_EXPERIMENTAL=y
36CONFIG_BROKEN_ON_SMP=y
37CONFIG_LOCK_KERNEL=y
38CONFIG_INIT_ENV_ARG_LIMIT=32
39CONFIG_LOCALVERSION=""
40CONFIG_LOCALVERSION_AUTO=y
41CONFIG_SWAP=y
42CONFIG_SYSVIPC=y
43CONFIG_SYSVIPC_SYSCTL=y
44# CONFIG_POSIX_MQUEUE is not set
45CONFIG_BSD_PROCESS_ACCT=y
46# CONFIG_BSD_PROCESS_ACCT_V3 is not set
47# CONFIG_TASKSTATS is not set
48# CONFIG_AUDIT is not set
49
50#
51# RCU Subsystem
52#
53CONFIG_CLASSIC_RCU=y
54# CONFIG_TREE_RCU is not set
55# CONFIG_PREEMPT_RCU is not set
56# CONFIG_TREE_RCU_TRACE is not set
57# CONFIG_PREEMPT_RCU_TRACE is not set
58CONFIG_IKCONFIG=y
59CONFIG_IKCONFIG_PROC=y
60CONFIG_LOG_BUF_SHIFT=14
61CONFIG_GROUP_SCHED=y
62CONFIG_FAIR_GROUP_SCHED=y
63# CONFIG_RT_GROUP_SCHED is not set
64CONFIG_USER_SCHED=y
65# CONFIG_CGROUP_SCHED is not set
66# CONFIG_CGROUPS is not set
67CONFIG_SYSFS_DEPRECATED=y
68CONFIG_SYSFS_DEPRECATED_V2=y
69# CONFIG_RELAY is not set
70# CONFIG_NAMESPACES is not set
71# CONFIG_BLK_DEV_INITRD is not set
72CONFIG_CC_OPTIMIZE_FOR_SIZE=y
73CONFIG_SYSCTL=y
74CONFIG_EMBEDDED=y
75CONFIG_UID16=y
76CONFIG_SYSCTL_SYSCALL=y
77CONFIG_KALLSYMS=y
78# CONFIG_KALLSYMS_ALL is not set
79# CONFIG_KALLSYMS_EXTRA_PASS is not set
80CONFIG_HOTPLUG=y
81CONFIG_PRINTK=y
82CONFIG_BUG=y
83CONFIG_ELF_CORE=y
84CONFIG_COMPAT_BRK=y
85CONFIG_BASE_FULL=y
86CONFIG_FUTEX=y
87CONFIG_ANON_INODES=y
88CONFIG_EPOLL=y
89CONFIG_SIGNALFD=y
90CONFIG_TIMERFD=y
91CONFIG_EVENTFD=y
92CONFIG_SHMEM=y
93CONFIG_AIO=y
94CONFIG_VM_EVENT_COUNTERS=y
95CONFIG_PCI_QUIRKS=y
96CONFIG_SLAB=y
97# CONFIG_SLUB is not set
98# CONFIG_SLOB is not set
99CONFIG_PROFILING=y
100# CONFIG_OPROFILE is not set
101CONFIG_HAVE_OPROFILE=y
102# CONFIG_KPROBES is not set
103CONFIG_HAVE_IOREMAP_PROT=y
104CONFIG_HAVE_KPROBES=y
105CONFIG_HAVE_KRETPROBES=y
106CONFIG_HAVE_ARCH_TRACEHOOK=y
107CONFIG_HAVE_CLK=y
108CONFIG_HAVE_GENERIC_DMA_COHERENT=y
109CONFIG_SLABINFO=y
110CONFIG_RT_MUTEXES=y
111CONFIG_BASE_SMALL=0
112CONFIG_MODULES=y
113# CONFIG_MODULE_FORCE_LOAD is not set
114CONFIG_MODULE_UNLOAD=y
115# CONFIG_MODULE_FORCE_UNLOAD is not set
116# CONFIG_MODVERSIONS is not set
117# CONFIG_MODULE_SRCVERSION_ALL is not set
118CONFIG_BLOCK=y
119# CONFIG_LBD is not set
120# CONFIG_BLK_DEV_IO_TRACE is not set
121# CONFIG_BLK_DEV_BSG is not set
122# CONFIG_BLK_DEV_INTEGRITY is not set
123
124#
125# IO Schedulers
126#
127CONFIG_IOSCHED_NOOP=y
128CONFIG_IOSCHED_AS=y
129CONFIG_IOSCHED_DEADLINE=y
130CONFIG_IOSCHED_CFQ=y
131# CONFIG_DEFAULT_AS is not set
132# CONFIG_DEFAULT_DEADLINE is not set
133CONFIG_DEFAULT_CFQ=y
134# CONFIG_DEFAULT_NOOP is not set
135CONFIG_DEFAULT_IOSCHED="cfq"
136# CONFIG_FREEZER is not set
137
138#
139# System type
140#
141CONFIG_CPU_SH4=y
142CONFIG_CPU_SH4A=y
143CONFIG_CPU_SHX2=y
144# CONFIG_CPU_SUBTYPE_SH7619 is not set
145# CONFIG_CPU_SUBTYPE_SH7201 is not set
146# CONFIG_CPU_SUBTYPE_SH7203 is not set
147# CONFIG_CPU_SUBTYPE_SH7206 is not set
148# CONFIG_CPU_SUBTYPE_SH7263 is not set
149# CONFIG_CPU_SUBTYPE_MXG is not set
150# CONFIG_CPU_SUBTYPE_SH7705 is not set
151# CONFIG_CPU_SUBTYPE_SH7706 is not set
152# CONFIG_CPU_SUBTYPE_SH7707 is not set
153# CONFIG_CPU_SUBTYPE_SH7708 is not set
154# CONFIG_CPU_SUBTYPE_SH7709 is not set
155# CONFIG_CPU_SUBTYPE_SH7710 is not set
156# CONFIG_CPU_SUBTYPE_SH7712 is not set
157# CONFIG_CPU_SUBTYPE_SH7720 is not set
158# CONFIG_CPU_SUBTYPE_SH7721 is not set
159# CONFIG_CPU_SUBTYPE_SH7750 is not set
160# CONFIG_CPU_SUBTYPE_SH7091 is not set
161# CONFIG_CPU_SUBTYPE_SH7750R is not set
162# CONFIG_CPU_SUBTYPE_SH7750S is not set
163# CONFIG_CPU_SUBTYPE_SH7751 is not set
164# CONFIG_CPU_SUBTYPE_SH7751R is not set
165# CONFIG_CPU_SUBTYPE_SH7760 is not set
166# CONFIG_CPU_SUBTYPE_SH4_202 is not set
167# CONFIG_CPU_SUBTYPE_SH7723 is not set
168# CONFIG_CPU_SUBTYPE_SH7763 is not set
169# CONFIG_CPU_SUBTYPE_SH7770 is not set
170# CONFIG_CPU_SUBTYPE_SH7780 is not set
171CONFIG_CPU_SUBTYPE_SH7785=y
172# CONFIG_CPU_SUBTYPE_SHX3 is not set
173# CONFIG_CPU_SUBTYPE_SH7343 is not set
174# CONFIG_CPU_SUBTYPE_SH7722 is not set
175# CONFIG_CPU_SUBTYPE_SH7366 is not set
176# CONFIG_CPU_SUBTYPE_SH5_101 is not set
177# CONFIG_CPU_SUBTYPE_SH5_103 is not set
178
179#
180# Memory management options
181#
182CONFIG_QUICKLIST=y
183CONFIG_MMU=y
184CONFIG_PAGE_OFFSET=0x80000000
185CONFIG_MEMORY_START=0x40000000
186CONFIG_MEMORY_SIZE=0x20000000
187# CONFIG_29BIT is not set
188CONFIG_32BIT=y
189CONFIG_PMB_ENABLE=y
190# CONFIG_PMB is not set
191CONFIG_PMB_FIXED=y
192# CONFIG_X2TLB is not set
193CONFIG_VSYSCALL=y
194# CONFIG_NUMA is not set
195CONFIG_ARCH_FLATMEM_ENABLE=y
196CONFIG_ARCH_SPARSEMEM_ENABLE=y
197CONFIG_ARCH_SPARSEMEM_DEFAULT=y
198CONFIG_MAX_ACTIVE_REGIONS=2
199CONFIG_ARCH_POPULATES_NODE_MAP=y
200CONFIG_ARCH_SELECT_MEMORY_MODEL=y
201CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
202CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
203CONFIG_PAGE_SIZE_4KB=y
204# CONFIG_PAGE_SIZE_8KB is not set
205# CONFIG_PAGE_SIZE_16KB is not set
206# CONFIG_PAGE_SIZE_64KB is not set
207CONFIG_ENTRY_OFFSET=0x00001000
208CONFIG_SELECT_MEMORY_MODEL=y
209# CONFIG_FLATMEM_MANUAL is not set
210# CONFIG_DISCONTIGMEM_MANUAL is not set
211CONFIG_SPARSEMEM_MANUAL=y
212CONFIG_SPARSEMEM=y
213CONFIG_HAVE_MEMORY_PRESENT=y
214CONFIG_SPARSEMEM_STATIC=y
215# CONFIG_MEMORY_HOTPLUG is not set
216CONFIG_PAGEFLAGS_EXTENDED=y
217CONFIG_SPLIT_PTLOCK_CPUS=4
218CONFIG_MIGRATION=y
219# CONFIG_PHYS_ADDR_T_64BIT is not set
220CONFIG_ZONE_DMA_FLAG=0
221CONFIG_NR_QUICK=2
222CONFIG_UNEVICTABLE_LRU=y
223
224#
225# Cache configuration
226#
227# CONFIG_SH_DIRECT_MAPPED is not set
228CONFIG_CACHE_WRITEBACK=y
229# CONFIG_CACHE_WRITETHROUGH is not set
230# CONFIG_CACHE_OFF is not set
231
232#
233# Processor features
234#
235CONFIG_CPU_LITTLE_ENDIAN=y
236# CONFIG_CPU_BIG_ENDIAN is not set
237CONFIG_SH_FPU=y
238CONFIG_SH_STORE_QUEUES=y
239CONFIG_CPU_HAS_INTEVT=y
240CONFIG_CPU_HAS_SR_RB=y
241CONFIG_CPU_HAS_PTEA=y
242CONFIG_CPU_HAS_FPU=y
243
244#
245# Board support
246#
247# CONFIG_SH_HIGHLANDER is not set
248CONFIG_SH_SH7785LCR=y
249
250#
251# Timer and clock configuration
252#
253CONFIG_SH_TMU=y
254CONFIG_SH_TIMER_IRQ=28
255CONFIG_SH_PCLK_FREQ=50000000
256CONFIG_TICK_ONESHOT=y
257# CONFIG_NO_HZ is not set
258CONFIG_HIGH_RES_TIMERS=y
259CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
260
261#
262# CPU Frequency scaling
263#
264# CONFIG_CPU_FREQ is not set
265
266#
267# DMA support
268#
269# CONFIG_SH_DMA is not set
270
271#
272# Companion Chips
273#
274
275#
276# Additional SuperH Device Drivers
277#
278CONFIG_HEARTBEAT=y
279# CONFIG_PUSH_SWITCH is not set
280
281#
282# Kernel features
283#
284# CONFIG_HZ_100 is not set
285CONFIG_HZ_250=y
286# CONFIG_HZ_300 is not set
287# CONFIG_HZ_1000 is not set
288CONFIG_HZ=250
289CONFIG_SCHED_HRTICK=y
290CONFIG_KEXEC=y
291# CONFIG_CRASH_DUMP is not set
292# CONFIG_SECCOMP is not set
293# CONFIG_PREEMPT_NONE is not set
294# CONFIG_PREEMPT_VOLUNTARY is not set
295CONFIG_PREEMPT=y
296CONFIG_GUSA=y
297
298#
299# Boot options
300#
301CONFIG_ZERO_PAGE_OFFSET=0x00001000
302CONFIG_BOOT_LINK_OFFSET=0x00800000
303# CONFIG_CMDLINE_BOOL is not set
304
305#
306# Bus options
307#
308CONFIG_PCI=y
309CONFIG_SH_PCIDMA_NONCOHERENT=y
310CONFIG_PCI_AUTO=y
311CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
312# CONFIG_PCIEPORTBUS is not set
313# CONFIG_ARCH_SUPPORTS_MSI is not set
314CONFIG_PCI_LEGACY=y
315# CONFIG_PCI_DEBUG is not set
316# CONFIG_PCI_STUB is not set
317# CONFIG_PCCARD is not set
318# CONFIG_HOTPLUG_PCI is not set
319
320#
321# Executable file formats
322#
323CONFIG_BINFMT_ELF=y
324# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
325# CONFIG_HAVE_AOUT is not set
326# CONFIG_BINFMT_MISC is not set
327
328#
329# Power management options (EXPERIMENTAL)
330#
331# CONFIG_PM is not set
332# CONFIG_CPU_IDLE is not set
333CONFIG_NET=y
334
335#
336# Networking options
337#
338CONFIG_COMPAT_NET_DEV_OPS=y
339CONFIG_PACKET=y
340# CONFIG_PACKET_MMAP is not set
341CONFIG_UNIX=y
342CONFIG_XFRM=y
343# CONFIG_XFRM_USER is not set
344# CONFIG_XFRM_SUB_POLICY is not set
345# CONFIG_XFRM_MIGRATE is not set
346# CONFIG_XFRM_STATISTICS is not set
347# CONFIG_NET_KEY is not set
348CONFIG_INET=y
349# CONFIG_IP_MULTICAST is not set
350CONFIG_IP_ADVANCED_ROUTER=y
351CONFIG_ASK_IP_FIB_HASH=y
352# CONFIG_IP_FIB_TRIE is not set
353CONFIG_IP_FIB_HASH=y
354# CONFIG_IP_MULTIPLE_TABLES is not set
355# CONFIG_IP_ROUTE_MULTIPATH is not set
356# CONFIG_IP_ROUTE_VERBOSE is not set
357CONFIG_IP_PNP=y
358CONFIG_IP_PNP_DHCP=y
359# CONFIG_IP_PNP_BOOTP is not set
360# CONFIG_IP_PNP_RARP is not set
361# CONFIG_NET_IPIP is not set
362# CONFIG_NET_IPGRE is not set
363# CONFIG_ARPD is not set
364# CONFIG_SYN_COOKIES is not set
365# CONFIG_INET_AH is not set
366# CONFIG_INET_ESP is not set
367# CONFIG_INET_IPCOMP is not set
368# CONFIG_INET_XFRM_TUNNEL is not set
369# CONFIG_INET_TUNNEL is not set
370CONFIG_INET_XFRM_MODE_TRANSPORT=y
371CONFIG_INET_XFRM_MODE_TUNNEL=y
372CONFIG_INET_XFRM_MODE_BEET=y
373# CONFIG_INET_LRO is not set
374CONFIG_INET_DIAG=y
375CONFIG_INET_TCP_DIAG=y
376# CONFIG_TCP_CONG_ADVANCED is not set
377CONFIG_TCP_CONG_CUBIC=y
378CONFIG_DEFAULT_TCP_CONG="cubic"
379# CONFIG_TCP_MD5SIG is not set
380# CONFIG_IPV6 is not set
381# CONFIG_NETWORK_SECMARK is not set
382# CONFIG_NETFILTER is not set
383# CONFIG_IP_DCCP is not set
384# CONFIG_IP_SCTP is not set
385# CONFIG_TIPC is not set
386# CONFIG_ATM is not set
387# CONFIG_BRIDGE is not set
388# CONFIG_NET_DSA is not set
389# CONFIG_VLAN_8021Q is not set
390# CONFIG_DECNET is not set
391# CONFIG_LLC2 is not set
392# CONFIG_IPX is not set
393# CONFIG_ATALK is not set
394# CONFIG_X25 is not set
395# CONFIG_LAPB is not set
396# CONFIG_ECONET is not set
397# CONFIG_WAN_ROUTER is not set
398# CONFIG_NET_SCHED is not set
399# CONFIG_DCB is not set
400
401#
402# Network testing
403#
404# CONFIG_NET_PKTGEN is not set
405# CONFIG_HAMRADIO is not set
406# CONFIG_CAN is not set
407# CONFIG_IRDA is not set
408# CONFIG_BT is not set
409# CONFIG_AF_RXRPC is not set
410# CONFIG_PHONET is not set
411CONFIG_WIRELESS=y
412# CONFIG_CFG80211 is not set
413# CONFIG_WIRELESS_OLD_REGULATORY is not set
414CONFIG_WIRELESS_EXT=y
415CONFIG_WIRELESS_EXT_SYSFS=y
416# CONFIG_LIB80211 is not set
417# CONFIG_MAC80211 is not set
418# CONFIG_WIMAX is not set
419# CONFIG_RFKILL is not set
420# CONFIG_NET_9P is not set
421
422#
423# Device Drivers
424#
425
426#
427# Generic Driver Options
428#
429CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
430CONFIG_STANDALONE=y
431CONFIG_PREVENT_FIRMWARE_BUILD=y
432# CONFIG_FW_LOADER is not set
433# CONFIG_DEBUG_DRIVER is not set
434# CONFIG_DEBUG_DEVRES is not set
435# CONFIG_SYS_HYPERVISOR is not set
436# CONFIG_CONNECTOR is not set
437CONFIG_MTD=y
438# CONFIG_MTD_DEBUG is not set
439CONFIG_MTD_CONCAT=y
440CONFIG_MTD_PARTITIONS=y
441# CONFIG_MTD_TESTS is not set
442# CONFIG_MTD_REDBOOT_PARTS is not set
443# CONFIG_MTD_CMDLINE_PARTS is not set
444# CONFIG_MTD_AR7_PARTS is not set
445
446#
447# User Modules And Translation Layers
448#
449CONFIG_MTD_CHAR=y
450CONFIG_MTD_BLKDEVS=y
451CONFIG_MTD_BLOCK=y
452# CONFIG_FTL is not set
453# CONFIG_NFTL is not set
454# CONFIG_INFTL is not set
455# CONFIG_RFD_FTL is not set
456# CONFIG_SSFDC is not set
457# CONFIG_MTD_OOPS is not set
458
459#
460# RAM/ROM/Flash chip drivers
461#
462CONFIG_MTD_CFI=y
463# CONFIG_MTD_JEDECPROBE is not set
464CONFIG_MTD_GEN_PROBE=y
465# CONFIG_MTD_CFI_ADV_OPTIONS is not set
466CONFIG_MTD_MAP_BANK_WIDTH_1=y
467CONFIG_MTD_MAP_BANK_WIDTH_2=y
468CONFIG_MTD_MAP_BANK_WIDTH_4=y
469# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
470# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
471# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
472CONFIG_MTD_CFI_I1=y
473CONFIG_MTD_CFI_I2=y
474# CONFIG_MTD_CFI_I4 is not set
475# CONFIG_MTD_CFI_I8 is not set
476# CONFIG_MTD_CFI_INTELEXT is not set
477CONFIG_MTD_CFI_AMDSTD=y
478# CONFIG_MTD_CFI_STAA is not set
479CONFIG_MTD_CFI_UTIL=y
480# CONFIG_MTD_RAM is not set
481# CONFIG_MTD_ROM is not set
482# CONFIG_MTD_ABSENT is not set
483
484#
485# Mapping drivers for chip access
486#
487# CONFIG_MTD_COMPLEX_MAPPINGS is not set
488CONFIG_MTD_PHYSMAP=y
489# CONFIG_MTD_PHYSMAP_COMPAT is not set
490# CONFIG_MTD_INTEL_VR_NOR is not set
491# CONFIG_MTD_PLATRAM is not set
492
493#
494# Self-contained MTD device drivers
495#
496# CONFIG_MTD_PMC551 is not set
497# CONFIG_MTD_SLRAM is not set
498# CONFIG_MTD_PHRAM is not set
499# CONFIG_MTD_MTDRAM is not set
500# CONFIG_MTD_BLOCK2MTD is not set
501
502#
503# Disk-On-Chip Device Drivers
504#
505# CONFIG_MTD_DOC2000 is not set
506# CONFIG_MTD_DOC2001 is not set
507# CONFIG_MTD_DOC2001PLUS is not set
508# CONFIG_MTD_NAND is not set
509# CONFIG_MTD_ONENAND is not set
510
511#
512# LPDDR flash memory drivers
513#
514# CONFIG_MTD_LPDDR is not set
515# CONFIG_MTD_QINFO_PROBE is not set
516
517#
518# UBI - Unsorted block images
519#
520# CONFIG_MTD_UBI is not set
521# CONFIG_PARPORT is not set
522CONFIG_BLK_DEV=y
523# CONFIG_BLK_CPQ_CISS_DA is not set
524# CONFIG_BLK_DEV_DAC960 is not set
525# CONFIG_BLK_DEV_UMEM is not set
526# CONFIG_BLK_DEV_COW_COMMON is not set
527# CONFIG_BLK_DEV_LOOP is not set
528# CONFIG_BLK_DEV_NBD is not set
529# CONFIG_BLK_DEV_SX8 is not set
530# CONFIG_BLK_DEV_UB is not set
531CONFIG_BLK_DEV_RAM=y
532CONFIG_BLK_DEV_RAM_COUNT=16
533CONFIG_BLK_DEV_RAM_SIZE=4096
534# CONFIG_BLK_DEV_XIP is not set
535# CONFIG_CDROM_PKTCDVD is not set
536# CONFIG_ATA_OVER_ETH is not set
537# CONFIG_BLK_DEV_HD is not set
538# CONFIG_MISC_DEVICES is not set
539CONFIG_HAVE_IDE=y
540# CONFIG_IDE is not set
541
542#
543# SCSI device support
544#
545# CONFIG_RAID_ATTRS is not set
546CONFIG_SCSI=y
547CONFIG_SCSI_DMA=y
548# CONFIG_SCSI_TGT is not set
549# CONFIG_SCSI_NETLINK is not set
550CONFIG_SCSI_PROC_FS=y
551
552#
553# SCSI support type (disk, tape, CD-ROM)
554#
555CONFIG_BLK_DEV_SD=y
556# CONFIG_CHR_DEV_ST is not set
557# CONFIG_CHR_DEV_OSST is not set
558# CONFIG_BLK_DEV_SR is not set
559# CONFIG_CHR_DEV_SG is not set
560# CONFIG_CHR_DEV_SCH is not set
561
562#
563# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
564#
565# CONFIG_SCSI_MULTI_LUN is not set
566# CONFIG_SCSI_CONSTANTS is not set
567# CONFIG_SCSI_LOGGING is not set
568# CONFIG_SCSI_SCAN_ASYNC is not set
569CONFIG_SCSI_WAIT_SCAN=m
570
571#
572# SCSI Transports
573#
574# CONFIG_SCSI_SPI_ATTRS is not set
575# CONFIG_SCSI_FC_ATTRS is not set
576# CONFIG_SCSI_ISCSI_ATTRS is not set
577# CONFIG_SCSI_SAS_LIBSAS is not set
578# CONFIG_SCSI_SRP_ATTRS is not set
579# CONFIG_SCSI_LOWLEVEL is not set
580# CONFIG_SCSI_DH is not set
581CONFIG_ATA=y
582# CONFIG_ATA_NONSTANDARD is not set
583CONFIG_SATA_PMP=y
584# CONFIG_SATA_AHCI is not set
585# CONFIG_SATA_SIL24 is not set
586CONFIG_ATA_SFF=y
587# CONFIG_SATA_SVW is not set
588# CONFIG_ATA_PIIX is not set
589# CONFIG_SATA_MV is not set
590# CONFIG_SATA_NV is not set
591# CONFIG_PDC_ADMA is not set
592# CONFIG_SATA_QSTOR is not set
593# CONFIG_SATA_PROMISE is not set
594# CONFIG_SATA_SX4 is not set
595CONFIG_SATA_SIL=y
596# CONFIG_SATA_SIS is not set
597# CONFIG_SATA_ULI is not set
598# CONFIG_SATA_VIA is not set
599# CONFIG_SATA_VITESSE is not set
600# CONFIG_SATA_INIC162X is not set
601# CONFIG_PATA_ALI is not set
602# CONFIG_PATA_AMD is not set
603# CONFIG_PATA_ARTOP is not set
604# CONFIG_PATA_ATIIXP is not set
605# CONFIG_PATA_CMD640_PCI is not set
606# CONFIG_PATA_CMD64X is not set
607# CONFIG_PATA_CS5520 is not set
608# CONFIG_PATA_CS5530 is not set
609# CONFIG_PATA_CYPRESS is not set
610# CONFIG_PATA_EFAR is not set
611# CONFIG_ATA_GENERIC is not set
612# CONFIG_PATA_HPT366 is not set
613# CONFIG_PATA_HPT37X is not set
614# CONFIG_PATA_HPT3X2N is not set
615# CONFIG_PATA_HPT3X3 is not set
616# CONFIG_PATA_IT821X is not set
617# CONFIG_PATA_IT8213 is not set
618# CONFIG_PATA_JMICRON is not set
619# CONFIG_PATA_TRIFLEX is not set
620# CONFIG_PATA_MARVELL is not set
621# CONFIG_PATA_MPIIX is not set
622# CONFIG_PATA_OLDPIIX is not set
623# CONFIG_PATA_NETCELL is not set
624# CONFIG_PATA_NINJA32 is not set
625# CONFIG_PATA_NS87410 is not set
626# CONFIG_PATA_NS87415 is not set
627# CONFIG_PATA_OPTI is not set
628# CONFIG_PATA_OPTIDMA is not set
629# CONFIG_PATA_PDC_OLD is not set
630# CONFIG_PATA_RADISYS is not set
631# CONFIG_PATA_RZ1000 is not set
632# CONFIG_PATA_SC1200 is not set
633# CONFIG_PATA_SERVERWORKS is not set
634# CONFIG_PATA_PDC2027X is not set
635# CONFIG_PATA_SIL680 is not set
636# CONFIG_PATA_SIS is not set
637# CONFIG_PATA_VIA is not set
638# CONFIG_PATA_WINBOND is not set
639# CONFIG_PATA_PLATFORM is not set
640# CONFIG_PATA_SCH is not set
641# CONFIG_MD is not set
642# CONFIG_FUSION is not set
643
644#
645# IEEE 1394 (FireWire) support
646#
647
648#
649# Enable only one of the two stacks, unless you know what you are doing
650#
651# CONFIG_FIREWIRE is not set
652# CONFIG_IEEE1394 is not set
653# CONFIG_I2O is not set
654CONFIG_NETDEVICES=y
655# CONFIG_DUMMY is not set
656# CONFIG_BONDING is not set
657# CONFIG_MACVLAN is not set
658# CONFIG_EQUALIZER is not set
659# CONFIG_TUN is not set
660# CONFIG_VETH is not set
661# CONFIG_ARCNET is not set
662# CONFIG_NET_ETHERNET is not set
663CONFIG_MII=y
664CONFIG_NETDEV_1000=y
665# CONFIG_ACENIC is not set
666# CONFIG_DL2K is not set
667# CONFIG_E1000 is not set
668# CONFIG_E1000E is not set
669# CONFIG_IP1000 is not set
670# CONFIG_IGB is not set
671# CONFIG_NS83820 is not set
672# CONFIG_HAMACHI is not set
673# CONFIG_YELLOWFIN is not set
674CONFIG_R8169=y
675# CONFIG_SIS190 is not set
676# CONFIG_SKGE is not set
677# CONFIG_SKY2 is not set
678# CONFIG_VIA_VELOCITY is not set
679# CONFIG_TIGON3 is not set
680# CONFIG_BNX2 is not set
681# CONFIG_QLA3XXX is not set
682# CONFIG_ATL1 is not set
683# CONFIG_ATL1E is not set
684# CONFIG_JME is not set
685# CONFIG_NETDEV_10000 is not set
686# CONFIG_TR is not set
687
688#
689# Wireless LAN
690#
691# CONFIG_WLAN_PRE80211 is not set
692# CONFIG_WLAN_80211 is not set
693# CONFIG_IWLWIFI_LEDS is not set
694
695#
696# Enable WiMAX (Networking options) to see the WiMAX drivers
697#
698
699#
700# USB Network Adapters
701#
702# CONFIG_USB_CATC is not set
703# CONFIG_USB_KAWETH is not set
704# CONFIG_USB_PEGASUS is not set
705# CONFIG_USB_RTL8150 is not set
706# CONFIG_USB_USBNET is not set
707# CONFIG_WAN is not set
708# CONFIG_FDDI is not set
709# CONFIG_HIPPI is not set
710# CONFIG_PPP is not set
711# CONFIG_SLIP is not set
712# CONFIG_NET_FC is not set
713# CONFIG_NETCONSOLE is not set
714# CONFIG_NETPOLL is not set
715# CONFIG_NET_POLL_CONTROLLER is not set
716# CONFIG_ISDN is not set
717# CONFIG_PHONE is not set
718
719#
720# Input device support
721#
722CONFIG_INPUT=y
723CONFIG_INPUT_FF_MEMLESS=m
724# CONFIG_INPUT_POLLDEV is not set
725
726#
727# Userland interfaces
728#
729CONFIG_INPUT_MOUSEDEV=y
730# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
731CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
732CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
733# CONFIG_INPUT_JOYDEV is not set
734# CONFIG_INPUT_EVDEV is not set
735# CONFIG_INPUT_EVBUG is not set
736
737#
738# Input Device Drivers
739#
740CONFIG_INPUT_KEYBOARD=y
741# CONFIG_KEYBOARD_ATKBD is not set
742# CONFIG_KEYBOARD_SUNKBD is not set
743# CONFIG_KEYBOARD_LKKBD is not set
744# CONFIG_KEYBOARD_XTKBD is not set
745# CONFIG_KEYBOARD_NEWTON is not set
746# CONFIG_KEYBOARD_STOWAWAY is not set
747# CONFIG_KEYBOARD_SH_KEYSC is not set
748# CONFIG_INPUT_MOUSE is not set
749# CONFIG_INPUT_JOYSTICK is not set
750# CONFIG_INPUT_TABLET is not set
751# CONFIG_INPUT_TOUCHSCREEN is not set
752# CONFIG_INPUT_MISC is not set
753
754#
755# Hardware I/O ports
756#
757# CONFIG_SERIO is not set
758# CONFIG_GAMEPORT is not set
759
760#
761# Character devices
762#
763CONFIG_VT=y
764CONFIG_CONSOLE_TRANSLATIONS=y
765CONFIG_VT_CONSOLE=y
766CONFIG_HW_CONSOLE=y
767CONFIG_VT_HW_CONSOLE_BINDING=y
768CONFIG_DEVKMEM=y
769# CONFIG_SERIAL_NONSTANDARD is not set
770# CONFIG_NOZOMI is not set
771
772#
773# Serial drivers
774#
775# CONFIG_SERIAL_8250 is not set
776
777#
778# Non-8250 serial port support
779#
780CONFIG_SERIAL_SH_SCI=y
781CONFIG_SERIAL_SH_SCI_NR_UARTS=6
782CONFIG_SERIAL_SH_SCI_CONSOLE=y
783CONFIG_SERIAL_CORE=y
784CONFIG_SERIAL_CORE_CONSOLE=y
785# CONFIG_SERIAL_JSM is not set
786CONFIG_UNIX98_PTYS=y
787# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
788CONFIG_LEGACY_PTYS=y
789CONFIG_LEGACY_PTY_COUNT=256
790# CONFIG_IPMI_HANDLER is not set
791CONFIG_HW_RANDOM=y
792# CONFIG_R3964 is not set
793# CONFIG_APPLICOM is not set
794# CONFIG_RAW_DRIVER is not set
795# CONFIG_TCG_TPM is not set
796CONFIG_DEVPORT=y
797CONFIG_I2C=y
798CONFIG_I2C_BOARDINFO=y
799# CONFIG_I2C_CHARDEV is not set
800CONFIG_I2C_HELPER_AUTO=y
801CONFIG_I2C_ALGOPCA=y
802
803#
804# I2C Hardware Bus support
805#
806
807#
808# PC SMBus host controller drivers
809#
810# CONFIG_I2C_ALI1535 is not set
811# CONFIG_I2C_ALI1563 is not set
812# CONFIG_I2C_ALI15X3 is not set
813# CONFIG_I2C_AMD756 is not set
814# CONFIG_I2C_AMD8111 is not set
815# CONFIG_I2C_I801 is not set
816# CONFIG_I2C_ISCH is not set
817# CONFIG_I2C_PIIX4 is not set
818# CONFIG_I2C_NFORCE2 is not set
819# CONFIG_I2C_SIS5595 is not set
820# CONFIG_I2C_SIS630 is not set
821# CONFIG_I2C_SIS96X is not set
822# CONFIG_I2C_VIA is not set
823# CONFIG_I2C_VIAPRO is not set
824
825#
826# I2C system bus drivers (mostly embedded / system-on-chip)
827#
828# CONFIG_I2C_OCORES is not set
829# CONFIG_I2C_SH_MOBILE is not set
830# CONFIG_I2C_SIMTEC is not set
831
832#
833# External I2C/SMBus adapter drivers
834#
835# CONFIG_I2C_PARPORT_LIGHT is not set
836# CONFIG_I2C_TAOS_EVM is not set
837# CONFIG_I2C_TINY_USB is not set
838
839#
840# Graphics adapter I2C/DDC channel drivers
841#
842# CONFIG_I2C_VOODOO3 is not set
843
844#
845# Other I2C/SMBus bus drivers
846#
847CONFIG_I2C_PCA_PLATFORM=y
848# CONFIG_I2C_STUB is not set
849
850#
851# Miscellaneous I2C Chip support
852#
853# CONFIG_DS1682 is not set
854# CONFIG_SENSORS_PCF8574 is not set
855# CONFIG_PCF8575 is not set
856# CONFIG_SENSORS_PCA9539 is not set
857# CONFIG_SENSORS_PCF8591 is not set
858# CONFIG_SENSORS_MAX6875 is not set
859# CONFIG_SENSORS_TSL2550 is not set
860# CONFIG_I2C_DEBUG_CORE is not set
861# CONFIG_I2C_DEBUG_ALGO is not set
862# CONFIG_I2C_DEBUG_BUS is not set
863# CONFIG_I2C_DEBUG_CHIP is not set
864# CONFIG_SPI is not set
865# CONFIG_W1 is not set
866# CONFIG_POWER_SUPPLY is not set
867# CONFIG_HWMON is not set
868# CONFIG_THERMAL is not set
869# CONFIG_THERMAL_HWMON is not set
870# CONFIG_WATCHDOG is not set
871CONFIG_SSB_POSSIBLE=y
872
873#
874# Sonics Silicon Backplane
875#
876# CONFIG_SSB is not set
877
878#
879# Multifunction device drivers
880#
881# CONFIG_MFD_CORE is not set
882CONFIG_MFD_SM501=y
883# CONFIG_HTC_PASIC3 is not set
884# CONFIG_TWL4030_CORE is not set
885# CONFIG_MFD_TMIO is not set
886# CONFIG_PMIC_DA903X is not set
887# CONFIG_MFD_WM8400 is not set
888# CONFIG_MFD_WM8350_I2C is not set
889# CONFIG_MFD_PCF50633 is not set
890# CONFIG_REGULATOR is not set
891
892#
893# Multimedia devices
894#
895
896#
897# Multimedia core support
898#
899# CONFIG_VIDEO_DEV is not set
900# CONFIG_DVB_CORE is not set
901# CONFIG_VIDEO_MEDIA is not set
902
903#
904# Multimedia drivers
905#
906# CONFIG_DAB is not set
907
908#
909# Graphics support
910#
911# CONFIG_DRM is not set
912# CONFIG_VGASTATE is not set
913# CONFIG_VIDEO_OUTPUT_CONTROL is not set
914CONFIG_FB=y
915# CONFIG_FIRMWARE_EDID is not set
916# CONFIG_FB_DDC is not set
917# CONFIG_FB_BOOT_VESA_SUPPORT is not set
918CONFIG_FB_CFB_FILLRECT=y
919CONFIG_FB_CFB_COPYAREA=y
920CONFIG_FB_CFB_IMAGEBLIT=y
921# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
922CONFIG_FB_SYS_FILLRECT=m
923CONFIG_FB_SYS_COPYAREA=m
924CONFIG_FB_SYS_IMAGEBLIT=m
925# CONFIG_FB_FOREIGN_ENDIAN is not set
926CONFIG_FB_SYS_FOPS=m
927CONFIG_FB_DEFERRED_IO=y
928# CONFIG_FB_SVGALIB is not set
929# CONFIG_FB_MACMODES is not set
930# CONFIG_FB_BACKLIGHT is not set
931# CONFIG_FB_MODE_HELPERS is not set
932# CONFIG_FB_TILEBLITTING is not set
933
934#
935# Frame buffer hardware drivers
936#
937# CONFIG_FB_CIRRUS is not set
938# CONFIG_FB_PM2 is not set
939# CONFIG_FB_CYBER2000 is not set
940# CONFIG_FB_ASILIANT is not set
941# CONFIG_FB_IMSTT is not set
942# CONFIG_FB_S1D13XXX is not set
943# CONFIG_FB_NVIDIA is not set
944# CONFIG_FB_RIVA is not set
945# CONFIG_FB_MATROX is not set
946# CONFIG_FB_RADEON is not set
947# CONFIG_FB_ATY128 is not set
948# CONFIG_FB_ATY is not set
949# CONFIG_FB_S3 is not set
950# CONFIG_FB_SAVAGE is not set
951# CONFIG_FB_SIS is not set
952# CONFIG_FB_VIA is not set
953# CONFIG_FB_NEOMAGIC is not set
954# CONFIG_FB_KYRO is not set
955# CONFIG_FB_3DFX is not set
956# CONFIG_FB_VOODOO1 is not set
957# CONFIG_FB_VT8623 is not set
958# CONFIG_FB_TRIDENT is not set
959# CONFIG_FB_ARK is not set
960# CONFIG_FB_PM3 is not set
961# CONFIG_FB_CARMINE is not set
962CONFIG_FB_SH_MOBILE_LCDC=m
963CONFIG_FB_SM501=y
964# CONFIG_FB_VIRTUAL is not set
965# CONFIG_FB_METRONOME is not set
966# CONFIG_FB_MB862XX is not set
967# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
968
969#
970# Display device support
971#
972# CONFIG_DISPLAY_SUPPORT is not set
973
974#
975# Console display driver support
976#
977CONFIG_DUMMY_CONSOLE=y
978CONFIG_FRAMEBUFFER_CONSOLE=y
979# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
980# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
981# CONFIG_FONTS is not set
982CONFIG_FONT_8x8=y
983CONFIG_FONT_8x16=y
984CONFIG_LOGO=y
985# CONFIG_LOGO_LINUX_MONO is not set
986# CONFIG_LOGO_LINUX_VGA16 is not set
987CONFIG_LOGO_LINUX_CLUT224=y
988# CONFIG_LOGO_SUPERH_MONO is not set
989# CONFIG_LOGO_SUPERH_VGA16 is not set
990# CONFIG_LOGO_SUPERH_CLUT224 is not set
991# CONFIG_SOUND is not set
992CONFIG_HID_SUPPORT=y
993CONFIG_HID=y
994# CONFIG_HID_DEBUG is not set
995# CONFIG_HIDRAW is not set
996
997#
998# USB Input Devices
999#
1000CONFIG_USB_HID=y
1001# CONFIG_HID_PID is not set
1002# CONFIG_USB_HIDDEV is not set
1003
1004#
1005# Special HID drivers
1006#
1007CONFIG_HID_COMPAT=y
1008CONFIG_HID_A4TECH=y
1009CONFIG_HID_APPLE=y
1010CONFIG_HID_BELKIN=y
1011CONFIG_HID_CHERRY=y
1012CONFIG_HID_CHICONY=y
1013CONFIG_HID_CYPRESS=y
1014CONFIG_HID_EZKEY=y
1015CONFIG_HID_GYRATION=y
1016CONFIG_HID_LOGITECH=y
1017# CONFIG_LOGITECH_FF is not set
1018# CONFIG_LOGIRUMBLEPAD2_FF is not set
1019CONFIG_HID_MICROSOFT=y
1020CONFIG_HID_MONTEREY=y
1021# CONFIG_HID_NTRIG is not set
1022CONFIG_HID_PANTHERLORD=y
1023# CONFIG_PANTHERLORD_FF is not set
1024CONFIG_HID_PETALYNX=y
1025CONFIG_HID_SAMSUNG=y
1026CONFIG_HID_SONY=y
1027CONFIG_HID_SUNPLUS=y
1028# CONFIG_GREENASIA_FF is not set
1029# CONFIG_HID_TOPSEED is not set
1030CONFIG_THRUSTMASTER_FF=m
1031CONFIG_ZEROPLUS_FF=m
1032CONFIG_USB_SUPPORT=y
1033CONFIG_USB_ARCH_HAS_HCD=y
1034CONFIG_USB_ARCH_HAS_OHCI=y
1035CONFIG_USB_ARCH_HAS_EHCI=y
1036CONFIG_USB=y
1037# CONFIG_USB_DEBUG is not set
1038# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
1039
1040#
1041# Miscellaneous USB options
1042#
1043CONFIG_USB_DEVICEFS=y
1044CONFIG_USB_DEVICE_CLASS=y
1045# CONFIG_USB_DYNAMIC_MINORS is not set
1046# CONFIG_USB_OTG is not set
1047# CONFIG_USB_OTG_WHITELIST is not set
1048# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1049CONFIG_USB_MON=y
1050# CONFIG_USB_WUSB is not set
1051# CONFIG_USB_WUSB_CBAF is not set
1052
1053#
1054# USB Host Controller Drivers
1055#
1056# CONFIG_USB_C67X00_HCD is not set
1057CONFIG_USB_EHCI_HCD=m
1058# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
1059# CONFIG_USB_EHCI_TT_NEWSCHED is not set
1060# CONFIG_USB_OXU210HP_HCD is not set
1061# CONFIG_USB_ISP116X_HCD is not set
1062# CONFIG_USB_ISP1760_HCD is not set
1063CONFIG_USB_OHCI_HCD=m
1064# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1065# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
1066CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1067# CONFIG_USB_UHCI_HCD is not set
1068# CONFIG_USB_SL811_HCD is not set
1069CONFIG_USB_R8A66597_HCD=y
1070# CONFIG_USB_WHCI_HCD is not set
1071# CONFIG_USB_HWA_HCD is not set
1072
1073#
1074# USB Device Class drivers
1075#
1076# CONFIG_USB_ACM is not set
1077# CONFIG_USB_PRINTER is not set
1078# CONFIG_USB_WDM is not set
1079# CONFIG_USB_TMC is not set
1080
1081#
1082# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
1083#
1084
1085#
1086# see USB_STORAGE Help for more information
1087#
1088CONFIG_USB_STORAGE=y
1089# CONFIG_USB_STORAGE_DEBUG is not set
1090# CONFIG_USB_STORAGE_DATAFAB is not set
1091# CONFIG_USB_STORAGE_FREECOM is not set
1092# CONFIG_USB_STORAGE_ISD200 is not set
1093# CONFIG_USB_STORAGE_USBAT is not set
1094# CONFIG_USB_STORAGE_SDDR09 is not set
1095# CONFIG_USB_STORAGE_SDDR55 is not set
1096# CONFIG_USB_STORAGE_JUMPSHOT is not set
1097# CONFIG_USB_STORAGE_ALAUDA is not set
1098# CONFIG_USB_STORAGE_ONETOUCH is not set
1099# CONFIG_USB_STORAGE_KARMA is not set
1100# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1101# CONFIG_USB_LIBUSUAL is not set
1102
1103#
1104# USB Imaging devices
1105#
1106# CONFIG_USB_MDC800 is not set
1107# CONFIG_USB_MICROTEK is not set
1108
1109#
1110# USB port drivers
1111#
1112# CONFIG_USB_SERIAL is not set
1113
1114#
1115# USB Miscellaneous drivers
1116#
1117# CONFIG_USB_EMI62 is not set
1118# CONFIG_USB_EMI26 is not set
1119# CONFIG_USB_ADUTUX is not set
1120# CONFIG_USB_SEVSEG is not set
1121# CONFIG_USB_RIO500 is not set
1122# CONFIG_USB_LEGOTOWER is not set
1123# CONFIG_USB_LCD is not set
1124# CONFIG_USB_BERRY_CHARGE is not set
1125# CONFIG_USB_LED is not set
1126# CONFIG_USB_CYPRESS_CY7C63 is not set
1127# CONFIG_USB_CYTHERM is not set
1128# CONFIG_USB_PHIDGET is not set
1129# CONFIG_USB_IDMOUSE is not set
1130# CONFIG_USB_FTDI_ELAN is not set
1131# CONFIG_USB_APPLEDISPLAY is not set
1132# CONFIG_USB_SISUSBVGA is not set
1133# CONFIG_USB_LD is not set
1134# CONFIG_USB_TRANCEVIBRATOR is not set
1135# CONFIG_USB_IOWARRIOR is not set
1136CONFIG_USB_TEST=m
1137# CONFIG_USB_ISIGHTFW is not set
1138# CONFIG_USB_VST is not set
1139# CONFIG_USB_GADGET is not set
1140
1141#
1142# OTG and related infrastructure
1143#
1144# CONFIG_UWB is not set
1145# CONFIG_MMC is not set
1146# CONFIG_MEMSTICK is not set
1147# CONFIG_NEW_LEDS is not set
1148# CONFIG_ACCESSIBILITY is not set
1149# CONFIG_INFINIBAND is not set
1150CONFIG_RTC_LIB=y
1151CONFIG_RTC_CLASS=y
1152CONFIG_RTC_HCTOSYS=y
1153CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1154# CONFIG_RTC_DEBUG is not set
1155
1156#
1157# RTC interfaces
1158#
1159CONFIG_RTC_INTF_SYSFS=y
1160CONFIG_RTC_INTF_PROC=y
1161CONFIG_RTC_INTF_DEV=y
1162# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1163# CONFIG_RTC_DRV_TEST is not set
1164
1165#
1166# I2C RTC drivers
1167#
1168# CONFIG_RTC_DRV_DS1307 is not set
1169# CONFIG_RTC_DRV_DS1374 is not set
1170# CONFIG_RTC_DRV_DS1672 is not set
1171# CONFIG_RTC_DRV_MAX6900 is not set
1172CONFIG_RTC_DRV_RS5C372=y
1173# CONFIG_RTC_DRV_ISL1208 is not set
1174# CONFIG_RTC_DRV_X1205 is not set
1175# CONFIG_RTC_DRV_PCF8563 is not set
1176# CONFIG_RTC_DRV_PCF8583 is not set
1177# CONFIG_RTC_DRV_M41T80 is not set
1178# CONFIG_RTC_DRV_S35390A is not set
1179# CONFIG_RTC_DRV_FM3130 is not set
1180# CONFIG_RTC_DRV_RX8581 is not set
1181
1182#
1183# SPI RTC drivers
1184#
1185
1186#
1187# Platform RTC drivers
1188#
1189# CONFIG_RTC_DRV_DS1286 is not set
1190# CONFIG_RTC_DRV_DS1511 is not set
1191# CONFIG_RTC_DRV_DS1553 is not set
1192# CONFIG_RTC_DRV_DS1742 is not set
1193# CONFIG_RTC_DRV_STK17TA8 is not set
1194# CONFIG_RTC_DRV_M48T86 is not set
1195# CONFIG_RTC_DRV_M48T35 is not set
1196# CONFIG_RTC_DRV_M48T59 is not set
1197# CONFIG_RTC_DRV_BQ4802 is not set
1198# CONFIG_RTC_DRV_V3020 is not set
1199
1200#
1201# on-CPU RTC drivers
1202#
1203# CONFIG_RTC_DRV_SH is not set
1204# CONFIG_DMADEVICES is not set
1205# CONFIG_UIO is not set
1206# CONFIG_STAGING is not set
1207
1208#
1209# File systems
1210#
1211CONFIG_EXT2_FS=y
1212# CONFIG_EXT2_FS_XATTR is not set
1213# CONFIG_EXT2_FS_XIP is not set
1214CONFIG_EXT3_FS=y
1215CONFIG_EXT3_FS_XATTR=y
1216# CONFIG_EXT3_FS_POSIX_ACL is not set
1217# CONFIG_EXT3_FS_SECURITY is not set
1218# CONFIG_EXT4_FS is not set
1219CONFIG_JBD=y
1220CONFIG_FS_MBCACHE=y
1221# CONFIG_REISERFS_FS is not set
1222# CONFIG_JFS_FS is not set
1223CONFIG_FS_POSIX_ACL=y
1224CONFIG_FILE_LOCKING=y
1225# CONFIG_XFS_FS is not set
1226# CONFIG_OCFS2_FS is not set
1227# CONFIG_BTRFS_FS is not set
1228CONFIG_DNOTIFY=y
1229CONFIG_INOTIFY=y
1230CONFIG_INOTIFY_USER=y
1231# CONFIG_QUOTA is not set
1232# CONFIG_AUTOFS_FS is not set
1233# CONFIG_AUTOFS4_FS is not set
1234# CONFIG_FUSE_FS is not set
1235
1236#
1237# CD-ROM/DVD Filesystems
1238#
1239# CONFIG_ISO9660_FS is not set
1240# CONFIG_UDF_FS is not set
1241
1242#
1243# DOS/FAT/NT Filesystems
1244#
1245CONFIG_FAT_FS=y
1246CONFIG_MSDOS_FS=y
1247CONFIG_VFAT_FS=y
1248CONFIG_FAT_DEFAULT_CODEPAGE=437
1249CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1250CONFIG_NTFS_FS=y
1251# CONFIG_NTFS_DEBUG is not set
1252CONFIG_NTFS_RW=y
1253
1254#
1255# Pseudo filesystems
1256#
1257CONFIG_PROC_FS=y
1258CONFIG_PROC_KCORE=y
1259CONFIG_PROC_SYSCTL=y
1260CONFIG_PROC_PAGE_MONITOR=y
1261CONFIG_SYSFS=y
1262CONFIG_TMPFS=y
1263# CONFIG_TMPFS_POSIX_ACL is not set
1264# CONFIG_HUGETLBFS is not set
1265# CONFIG_HUGETLB_PAGE is not set
1266# CONFIG_CONFIGFS_FS is not set
1267CONFIG_MISC_FILESYSTEMS=y
1268# CONFIG_ADFS_FS is not set
1269# CONFIG_AFFS_FS is not set
1270# CONFIG_HFS_FS is not set
1271# CONFIG_HFSPLUS_FS is not set
1272# CONFIG_BEFS_FS is not set
1273# CONFIG_BFS_FS is not set
1274# CONFIG_EFS_FS is not set
1275# CONFIG_JFFS2_FS is not set
1276# CONFIG_CRAMFS is not set
1277# CONFIG_SQUASHFS is not set
1278# CONFIG_VXFS_FS is not set
1279CONFIG_MINIX_FS=y
1280# CONFIG_OMFS_FS is not set
1281# CONFIG_HPFS_FS is not set
1282# CONFIG_QNX4FS_FS is not set
1283# CONFIG_ROMFS_FS is not set
1284# CONFIG_SYSV_FS is not set
1285# CONFIG_UFS_FS is not set
1286CONFIG_NETWORK_FILESYSTEMS=y
1287CONFIG_NFS_FS=y
1288CONFIG_NFS_V3=y
1289# CONFIG_NFS_V3_ACL is not set
1290CONFIG_NFS_V4=y
1291CONFIG_ROOT_NFS=y
1292CONFIG_NFSD=y
1293CONFIG_NFSD_V3=y
1294# CONFIG_NFSD_V3_ACL is not set
1295CONFIG_NFSD_V4=y
1296CONFIG_LOCKD=y
1297CONFIG_LOCKD_V4=y
1298CONFIG_EXPORTFS=y
1299CONFIG_NFS_COMMON=y
1300CONFIG_SUNRPC=y
1301CONFIG_SUNRPC_GSS=y
1302# CONFIG_SUNRPC_REGISTER_V4 is not set
1303CONFIG_RPCSEC_GSS_KRB5=y
1304# CONFIG_RPCSEC_GSS_SPKM3 is not set
1305# CONFIG_SMB_FS is not set
1306# CONFIG_CIFS is not set
1307# CONFIG_NCP_FS is not set
1308# CONFIG_CODA_FS is not set
1309# CONFIG_AFS_FS is not set
1310
1311#
1312# Partition Types
1313#
1314# CONFIG_PARTITION_ADVANCED is not set
1315CONFIG_MSDOS_PARTITION=y
1316CONFIG_NLS=y
1317CONFIG_NLS_DEFAULT="iso8859-1"
1318CONFIG_NLS_CODEPAGE_437=y
1319# CONFIG_NLS_CODEPAGE_737 is not set
1320# CONFIG_NLS_CODEPAGE_775 is not set
1321# CONFIG_NLS_CODEPAGE_850 is not set
1322# CONFIG_NLS_CODEPAGE_852 is not set
1323# CONFIG_NLS_CODEPAGE_855 is not set
1324# CONFIG_NLS_CODEPAGE_857 is not set
1325# CONFIG_NLS_CODEPAGE_860 is not set
1326# CONFIG_NLS_CODEPAGE_861 is not set
1327# CONFIG_NLS_CODEPAGE_862 is not set
1328# CONFIG_NLS_CODEPAGE_863 is not set
1329# CONFIG_NLS_CODEPAGE_864 is not set
1330# CONFIG_NLS_CODEPAGE_865 is not set
1331# CONFIG_NLS_CODEPAGE_866 is not set
1332# CONFIG_NLS_CODEPAGE_869 is not set
1333# CONFIG_NLS_CODEPAGE_936 is not set
1334# CONFIG_NLS_CODEPAGE_950 is not set
1335CONFIG_NLS_CODEPAGE_932=y
1336# CONFIG_NLS_CODEPAGE_949 is not set
1337# CONFIG_NLS_CODEPAGE_874 is not set
1338# CONFIG_NLS_ISO8859_8 is not set
1339# CONFIG_NLS_CODEPAGE_1250 is not set
1340# CONFIG_NLS_CODEPAGE_1251 is not set
1341# CONFIG_NLS_ASCII is not set
1342CONFIG_NLS_ISO8859_1=y
1343# CONFIG_NLS_ISO8859_2 is not set
1344# CONFIG_NLS_ISO8859_3 is not set
1345# CONFIG_NLS_ISO8859_4 is not set
1346# CONFIG_NLS_ISO8859_5 is not set
1347# CONFIG_NLS_ISO8859_6 is not set
1348# CONFIG_NLS_ISO8859_7 is not set
1349# CONFIG_NLS_ISO8859_9 is not set
1350# CONFIG_NLS_ISO8859_13 is not set
1351# CONFIG_NLS_ISO8859_14 is not set
1352# CONFIG_NLS_ISO8859_15 is not set
1353# CONFIG_NLS_KOI8_R is not set
1354# CONFIG_NLS_KOI8_U is not set
1355# CONFIG_NLS_UTF8 is not set
1356# CONFIG_DLM is not set
1357
1358#
1359# Kernel hacking
1360#
1361CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1362# CONFIG_PRINTK_TIME is not set
1363# CONFIG_ENABLE_WARN_DEPRECATED is not set
1364# CONFIG_ENABLE_MUST_CHECK is not set
1365CONFIG_FRAME_WARN=1024
1366# CONFIG_MAGIC_SYSRQ is not set
1367# CONFIG_UNUSED_SYMBOLS is not set
1368# CONFIG_DEBUG_FS is not set
1369# CONFIG_HEADERS_CHECK is not set
1370CONFIG_DEBUG_KERNEL=y
1371# CONFIG_DEBUG_SHIRQ is not set
1372CONFIG_DETECT_SOFTLOCKUP=y
1373# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1374CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1375CONFIG_SCHED_DEBUG=y
1376# CONFIG_SCHEDSTATS is not set
1377# CONFIG_TIMER_STATS is not set
1378# CONFIG_DEBUG_OBJECTS is not set
1379# CONFIG_DEBUG_SLAB is not set
1380CONFIG_DEBUG_PREEMPT=y
1381# CONFIG_DEBUG_RT_MUTEXES is not set
1382# CONFIG_RT_MUTEX_TESTER is not set
1383# CONFIG_DEBUG_SPINLOCK is not set
1384# CONFIG_DEBUG_MUTEXES is not set
1385# CONFIG_DEBUG_LOCK_ALLOC is not set
1386# CONFIG_PROVE_LOCKING is not set
1387# CONFIG_LOCK_STAT is not set
1388# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1389# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1390# CONFIG_DEBUG_KOBJECT is not set
1391# CONFIG_DEBUG_BUGVERBOSE is not set
1392# CONFIG_DEBUG_INFO is not set
1393# CONFIG_DEBUG_VM is not set
1394# CONFIG_DEBUG_WRITECOUNT is not set
1395# CONFIG_DEBUG_MEMORY_INIT is not set
1396# CONFIG_DEBUG_LIST is not set
1397# CONFIG_DEBUG_SG is not set
1398# CONFIG_DEBUG_NOTIFIERS is not set
1399# CONFIG_FRAME_POINTER is not set
1400# CONFIG_RCU_TORTURE_TEST is not set
1401# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1402# CONFIG_BACKTRACE_SELF_TEST is not set
1403# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1404# CONFIG_FAULT_INJECTION is not set
1405# CONFIG_LATENCYTOP is not set
1406CONFIG_SYSCTL_SYSCALL_CHECK=y
1407CONFIG_HAVE_FUNCTION_TRACER=y
1408CONFIG_HAVE_DYNAMIC_FTRACE=y
1409CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1410
1411#
1412# Tracers
1413#
1414# CONFIG_FUNCTION_TRACER is not set
1415# CONFIG_IRQSOFF_TRACER is not set
1416# CONFIG_PREEMPT_TRACER is not set
1417# CONFIG_SCHED_TRACER is not set
1418# CONFIG_CONTEXT_SWITCH_TRACER is not set
1419# CONFIG_BOOT_TRACER is not set
1420# CONFIG_TRACE_BRANCH_PROFILING is not set
1421# CONFIG_STACK_TRACER is not set
1422# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
1423# CONFIG_SAMPLES is not set
1424CONFIG_HAVE_ARCH_KGDB=y
1425# CONFIG_KGDB is not set
1426# CONFIG_SH_STANDARD_BIOS is not set
1427# CONFIG_EARLY_SCIF_CONSOLE is not set
1428# CONFIG_DEBUG_BOOTMEM is not set
1429# CONFIG_DEBUG_STACKOVERFLOW is not set
1430# CONFIG_DEBUG_STACK_USAGE is not set
1431# CONFIG_4KSTACKS is not set
1432# CONFIG_IRQSTACKS is not set
1433# CONFIG_DUMP_CODE is not set
1434# CONFIG_SH_NO_BSS_INIT is not set
1435# CONFIG_MORE_COMPILE_OPTIONS is not set
1436
1437#
1438# Security options
1439#
1440# CONFIG_KEYS is not set
1441# CONFIG_SECURITY is not set
1442# CONFIG_SECURITYFS is not set
1443# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1444CONFIG_CRYPTO=y
1445
1446#
1447# Crypto core or helper
1448#
1449# CONFIG_CRYPTO_FIPS is not set
1450CONFIG_CRYPTO_ALGAPI=y
1451CONFIG_CRYPTO_ALGAPI2=y
1452CONFIG_CRYPTO_AEAD2=y
1453CONFIG_CRYPTO_BLKCIPHER=y
1454CONFIG_CRYPTO_BLKCIPHER2=y
1455CONFIG_CRYPTO_HASH=y
1456CONFIG_CRYPTO_HASH2=y
1457CONFIG_CRYPTO_RNG2=y
1458CONFIG_CRYPTO_MANAGER=y
1459CONFIG_CRYPTO_MANAGER2=y
1460# CONFIG_CRYPTO_GF128MUL is not set
1461# CONFIG_CRYPTO_NULL is not set
1462# CONFIG_CRYPTO_CRYPTD is not set
1463# CONFIG_CRYPTO_AUTHENC is not set
1464# CONFIG_CRYPTO_TEST is not set
1465
1466#
1467# Authenticated Encryption with Associated Data
1468#
1469# CONFIG_CRYPTO_CCM is not set
1470# CONFIG_CRYPTO_GCM is not set
1471# CONFIG_CRYPTO_SEQIV is not set
1472
1473#
1474# Block modes
1475#
1476CONFIG_CRYPTO_CBC=y
1477# CONFIG_CRYPTO_CTR is not set
1478# CONFIG_CRYPTO_CTS is not set
1479# CONFIG_CRYPTO_ECB is not set
1480# CONFIG_CRYPTO_LRW is not set
1481# CONFIG_CRYPTO_PCBC is not set
1482# CONFIG_CRYPTO_XTS is not set
1483
1484#
1485# Hash modes
1486#
1487CONFIG_CRYPTO_HMAC=y
1488# CONFIG_CRYPTO_XCBC is not set
1489
1490#
1491# Digest
1492#
1493# CONFIG_CRYPTO_CRC32C is not set
1494# CONFIG_CRYPTO_MD4 is not set
1495CONFIG_CRYPTO_MD5=y
1496# CONFIG_CRYPTO_MICHAEL_MIC is not set
1497# CONFIG_CRYPTO_RMD128 is not set
1498# CONFIG_CRYPTO_RMD160 is not set
1499# CONFIG_CRYPTO_RMD256 is not set
1500# CONFIG_CRYPTO_RMD320 is not set
1501# CONFIG_CRYPTO_SHA1 is not set
1502# CONFIG_CRYPTO_SHA256 is not set
1503# CONFIG_CRYPTO_SHA512 is not set
1504# CONFIG_CRYPTO_TGR192 is not set
1505# CONFIG_CRYPTO_WP512 is not set
1506
1507#
1508# Ciphers
1509#
1510# CONFIG_CRYPTO_AES is not set
1511# CONFIG_CRYPTO_ANUBIS is not set
1512# CONFIG_CRYPTO_ARC4 is not set
1513# CONFIG_CRYPTO_BLOWFISH is not set
1514# CONFIG_CRYPTO_CAMELLIA is not set
1515# CONFIG_CRYPTO_CAST5 is not set
1516# CONFIG_CRYPTO_CAST6 is not set
1517CONFIG_CRYPTO_DES=y
1518# CONFIG_CRYPTO_FCRYPT is not set
1519# CONFIG_CRYPTO_KHAZAD is not set
1520# CONFIG_CRYPTO_SALSA20 is not set
1521# CONFIG_CRYPTO_SEED is not set
1522# CONFIG_CRYPTO_SERPENT is not set
1523# CONFIG_CRYPTO_TEA is not set
1524# CONFIG_CRYPTO_TWOFISH is not set
1525
1526#
1527# Compression
1528#
1529# CONFIG_CRYPTO_DEFLATE is not set
1530# CONFIG_CRYPTO_LZO is not set
1531
1532#
1533# Random Number Generation
1534#
1535# CONFIG_CRYPTO_ANSI_CPRNG is not set
1536# CONFIG_CRYPTO_HW is not set
1537
1538#
1539# Library routines
1540#
1541CONFIG_BITREVERSE=y
1542CONFIG_GENERIC_FIND_LAST_BIT=y
1543# CONFIG_CRC_CCITT is not set
1544# CONFIG_CRC16 is not set
1545# CONFIG_CRC_T10DIF is not set
1546# CONFIG_CRC_ITU_T is not set
1547CONFIG_CRC32=y
1548# CONFIG_CRC7 is not set
1549# CONFIG_LIBCRC32C is not set
1550CONFIG_PLIST=y
1551CONFIG_HAS_IOMEM=y
1552CONFIG_HAS_IOPORT=y
1553CONFIG_HAS_DMA=y
diff --git a/arch/sh/configs/urquell_defconfig b/arch/sh/configs/urquell_defconfig
new file mode 100644
index 000000000000..be726c7cdf91
--- /dev/null
+++ b/arch/sh/configs/urquell_defconfig
@@ -0,0 +1,1332 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29-rc4
4# Thu Mar 5 17:28:13 2009
5#
6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y
11CONFIG_GENERIC_FIND_NEXT_BIT=y
12CONFIG_GENERIC_HWEIGHT=y
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
15CONFIG_GENERIC_IRQ_PROBE=y
16CONFIG_GENERIC_GPIO=y
17CONFIG_GENERIC_TIME=y
18CONFIG_GENERIC_CLOCKEVENTS=y
19# CONFIG_ARCH_SUSPEND_POSSIBLE is not set
20# CONFIG_ARCH_HIBERNATION_POSSIBLE is not set
21CONFIG_SYS_SUPPORTS_NUMA=y
22CONFIG_STACKTRACE_SUPPORT=y
23CONFIG_LOCKDEP_SUPPORT=y
24CONFIG_HAVE_LATENCYTOP_SUPPORT=y
25# CONFIG_ARCH_HAS_ILOG2_U32 is not set
26# CONFIG_ARCH_HAS_ILOG2_U64 is not set
27CONFIG_ARCH_NO_VIRT_TO_BUS=y
28CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
29
30#
31# General setup
32#
33CONFIG_EXPERIMENTAL=y
34CONFIG_BROKEN_ON_SMP=y
35CONFIG_LOCK_KERNEL=y
36CONFIG_INIT_ENV_ARG_LIMIT=32
37CONFIG_LOCALVERSION=""
38CONFIG_LOCALVERSION_AUTO=y
39CONFIG_SWAP=y
40CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set
43CONFIG_BSD_PROCESS_ACCT=y
44# CONFIG_BSD_PROCESS_ACCT_V3 is not set
45# CONFIG_TASKSTATS is not set
46# CONFIG_AUDIT is not set
47
48#
49# RCU Subsystem
50#
51CONFIG_CLASSIC_RCU=y
52# CONFIG_TREE_RCU is not set
53# CONFIG_PREEMPT_RCU is not set
54# CONFIG_TREE_RCU_TRACE is not set
55# CONFIG_PREEMPT_RCU_TRACE is not set
56CONFIG_IKCONFIG=y
57CONFIG_IKCONFIG_PROC=y
58CONFIG_LOG_BUF_SHIFT=14
59CONFIG_GROUP_SCHED=y
60CONFIG_FAIR_GROUP_SCHED=y
61# CONFIG_RT_GROUP_SCHED is not set
62CONFIG_USER_SCHED=y
63# CONFIG_CGROUP_SCHED is not set
64# CONFIG_CGROUPS is not set
65CONFIG_SYSFS_DEPRECATED=y
66CONFIG_SYSFS_DEPRECATED_V2=y
67# CONFIG_RELAY is not set
68# CONFIG_NAMESPACES is not set
69# CONFIG_BLK_DEV_INITRD is not set
70CONFIG_CC_OPTIMIZE_FOR_SIZE=y
71CONFIG_SYSCTL=y
72CONFIG_EMBEDDED=y
73CONFIG_UID16=y
74CONFIG_SYSCTL_SYSCALL=y
75CONFIG_KALLSYMS=y
76# CONFIG_KALLSYMS_EXTRA_PASS is not set
77CONFIG_HOTPLUG=y
78CONFIG_PRINTK=y
79CONFIG_BUG=y
80CONFIG_ELF_CORE=y
81CONFIG_COMPAT_BRK=y
82CONFIG_BASE_FULL=y
83CONFIG_FUTEX=y
84CONFIG_ANON_INODES=y
85CONFIG_EPOLL=y
86CONFIG_SIGNALFD=y
87CONFIG_TIMERFD=y
88CONFIG_EVENTFD=y
89CONFIG_SHMEM=y
90CONFIG_AIO=y
91CONFIG_VM_EVENT_COUNTERS=y
92CONFIG_SLAB=y
93# CONFIG_SLUB is not set
94# CONFIG_SLOB is not set
95CONFIG_PROFILING=y
96# CONFIG_OPROFILE is not set
97CONFIG_HAVE_OPROFILE=y
98# CONFIG_KPROBES is not set
99CONFIG_HAVE_IOREMAP_PROT=y
100CONFIG_HAVE_KPROBES=y
101CONFIG_HAVE_KRETPROBES=y
102CONFIG_HAVE_ARCH_TRACEHOOK=y
103CONFIG_HAVE_CLK=y
104CONFIG_HAVE_GENERIC_DMA_COHERENT=y
105CONFIG_SLABINFO=y
106CONFIG_RT_MUTEXES=y
107CONFIG_BASE_SMALL=0
108CONFIG_MODULES=y
109# CONFIG_MODULE_FORCE_LOAD is not set
110CONFIG_MODULE_UNLOAD=y
111# CONFIG_MODULE_FORCE_UNLOAD is not set
112# CONFIG_MODVERSIONS is not set
113# CONFIG_MODULE_SRCVERSION_ALL is not set
114CONFIG_BLOCK=y
115# CONFIG_LBD is not set
116# CONFIG_BLK_DEV_IO_TRACE is not set
117# CONFIG_BLK_DEV_BSG is not set
118# CONFIG_BLK_DEV_INTEGRITY is not set
119
120#
121# IO Schedulers
122#
123CONFIG_IOSCHED_NOOP=y
124CONFIG_IOSCHED_AS=y
125CONFIG_IOSCHED_DEADLINE=y
126CONFIG_IOSCHED_CFQ=y
127# CONFIG_DEFAULT_AS is not set
128# CONFIG_DEFAULT_DEADLINE is not set
129CONFIG_DEFAULT_CFQ=y
130# CONFIG_DEFAULT_NOOP is not set
131CONFIG_DEFAULT_IOSCHED="cfq"
132# CONFIG_FREEZER is not set
133
134#
135# System type
136#
137CONFIG_CPU_SH4=y
138CONFIG_CPU_SH4A=y
139CONFIG_CPU_SHX3=y
140# CONFIG_CPU_SUBTYPE_SH7619 is not set
141# CONFIG_CPU_SUBTYPE_SH7201 is not set
142# CONFIG_CPU_SUBTYPE_SH7203 is not set
143# CONFIG_CPU_SUBTYPE_SH7206 is not set
144# CONFIG_CPU_SUBTYPE_SH7263 is not set
145# CONFIG_CPU_SUBTYPE_MXG is not set
146# CONFIG_CPU_SUBTYPE_SH7705 is not set
147# CONFIG_CPU_SUBTYPE_SH7706 is not set
148# CONFIG_CPU_SUBTYPE_SH7707 is not set
149# CONFIG_CPU_SUBTYPE_SH7708 is not set
150# CONFIG_CPU_SUBTYPE_SH7709 is not set
151# CONFIG_CPU_SUBTYPE_SH7710 is not set
152# CONFIG_CPU_SUBTYPE_SH7712 is not set
153# CONFIG_CPU_SUBTYPE_SH7720 is not set
154# CONFIG_CPU_SUBTYPE_SH7721 is not set
155# CONFIG_CPU_SUBTYPE_SH7750 is not set
156# CONFIG_CPU_SUBTYPE_SH7091 is not set
157# CONFIG_CPU_SUBTYPE_SH7750R is not set
158# CONFIG_CPU_SUBTYPE_SH7750S is not set
159# CONFIG_CPU_SUBTYPE_SH7751 is not set
160# CONFIG_CPU_SUBTYPE_SH7751R is not set
161# CONFIG_CPU_SUBTYPE_SH7760 is not set
162# CONFIG_CPU_SUBTYPE_SH4_202 is not set
163# CONFIG_CPU_SUBTYPE_SH7723 is not set
164# CONFIG_CPU_SUBTYPE_SH7763 is not set
165# CONFIG_CPU_SUBTYPE_SH7770 is not set
166# CONFIG_CPU_SUBTYPE_SH7780 is not set
167# CONFIG_CPU_SUBTYPE_SH7785 is not set
168CONFIG_CPU_SUBTYPE_SH7786=y
169# CONFIG_CPU_SUBTYPE_SHX3 is not set
170# CONFIG_CPU_SUBTYPE_SH7343 is not set
171# CONFIG_CPU_SUBTYPE_SH7722 is not set
172# CONFIG_CPU_SUBTYPE_SH7366 is not set
173# CONFIG_CPU_SUBTYPE_SH5_101 is not set
174# CONFIG_CPU_SUBTYPE_SH5_103 is not set
175
176#
177# Memory management options
178#
179CONFIG_QUICKLIST=y
180CONFIG_MMU=y
181CONFIG_PAGE_OFFSET=0x80000000
182CONFIG_MEMORY_START=0x08000000
183CONFIG_MEMORY_SIZE=0x08000000
184CONFIG_29BIT=y
185# CONFIG_X2TLB is not set
186CONFIG_VSYSCALL=y
187# CONFIG_NUMA is not set
188CONFIG_ARCH_FLATMEM_ENABLE=y
189CONFIG_ARCH_SPARSEMEM_ENABLE=y
190CONFIG_ARCH_SPARSEMEM_DEFAULT=y
191CONFIG_MAX_ACTIVE_REGIONS=1
192CONFIG_ARCH_POPULATES_NODE_MAP=y
193CONFIG_ARCH_SELECT_MEMORY_MODEL=y
194CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
195CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
196CONFIG_PAGE_SIZE_4KB=y
197# CONFIG_PAGE_SIZE_8KB is not set
198# CONFIG_PAGE_SIZE_16KB is not set
199# CONFIG_PAGE_SIZE_64KB is not set
200CONFIG_ENTRY_OFFSET=0x00001000
201CONFIG_SELECT_MEMORY_MODEL=y
202# CONFIG_FLATMEM_MANUAL is not set
203# CONFIG_DISCONTIGMEM_MANUAL is not set
204CONFIG_SPARSEMEM_MANUAL=y
205CONFIG_SPARSEMEM=y
206CONFIG_HAVE_MEMORY_PRESENT=y
207CONFIG_SPARSEMEM_STATIC=y
208# CONFIG_MEMORY_HOTPLUG is not set
209CONFIG_PAGEFLAGS_EXTENDED=y
210CONFIG_SPLIT_PTLOCK_CPUS=4
211CONFIG_MIGRATION=y
212# CONFIG_PHYS_ADDR_T_64BIT is not set
213CONFIG_ZONE_DMA_FLAG=0
214CONFIG_NR_QUICK=2
215CONFIG_UNEVICTABLE_LRU=y
216
217#
218# Cache configuration
219#
220# CONFIG_SH_DIRECT_MAPPED is not set
221CONFIG_CACHE_WRITEBACK=y
222# CONFIG_CACHE_WRITETHROUGH is not set
223# CONFIG_CACHE_OFF is not set
224
225#
226# Processor features
227#
228CONFIG_CPU_LITTLE_ENDIAN=y
229# CONFIG_CPU_BIG_ENDIAN is not set
230CONFIG_SH_FPU=y
231CONFIG_SH_STORE_QUEUES=y
232CONFIG_CPU_HAS_INTEVT=y
233CONFIG_CPU_HAS_SR_RB=y
234CONFIG_CPU_HAS_FPU=y
235
236#
237# Board support
238#
239CONFIG_SH_URQUELL=y
240
241#
242# Timer and clock configuration
243#
244CONFIG_SH_TMU=y
245CONFIG_SH_TIMER_IRQ=16
246CONFIG_SH_PCLK_FREQ=33333333
247CONFIG_TICK_ONESHOT=y
248# CONFIG_NO_HZ is not set
249CONFIG_HIGH_RES_TIMERS=y
250CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
251
252#
253# CPU Frequency scaling
254#
255# CONFIG_CPU_FREQ is not set
256
257#
258# DMA support
259#
260# CONFIG_SH_DMA is not set
261
262#
263# Companion Chips
264#
265
266#
267# Additional SuperH Device Drivers
268#
269CONFIG_HEARTBEAT=y
270# CONFIG_PUSH_SWITCH is not set
271
272#
273# Kernel features
274#
275# CONFIG_HZ_100 is not set
276CONFIG_HZ_250=y
277# CONFIG_HZ_300 is not set
278# CONFIG_HZ_1000 is not set
279CONFIG_HZ=250
280CONFIG_SCHED_HRTICK=y
281CONFIG_KEXEC=y
282# CONFIG_CRASH_DUMP is not set
283# CONFIG_SECCOMP is not set
284# CONFIG_PREEMPT_NONE is not set
285# CONFIG_PREEMPT_VOLUNTARY is not set
286CONFIG_PREEMPT=y
287CONFIG_GUSA=y
288
289#
290# Boot options
291#
292CONFIG_ZERO_PAGE_OFFSET=0x00001000
293CONFIG_BOOT_LINK_OFFSET=0x00800000
294CONFIG_CMDLINE_BOOL=y
295CONFIG_CMDLINE="console=ttySC1, 38400 earlyprintk=serial ip=on ignore_loglevel root=/dev/nfs ip=dhcp memchunk.vpu=4m"
296
297#
298# Bus options
299#
300# CONFIG_ARCH_SUPPORTS_MSI is not set
301# CONFIG_PCCARD is not set
302
303#
304# Executable file formats
305#
306CONFIG_BINFMT_ELF=y
307# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
308# CONFIG_HAVE_AOUT is not set
309# CONFIG_BINFMT_MISC is not set
310
311#
312# Power management options (EXPERIMENTAL)
313#
314# CONFIG_PM is not set
315# CONFIG_CPU_IDLE is not set
316CONFIG_NET=y
317
318#
319# Networking options
320#
321CONFIG_COMPAT_NET_DEV_OPS=y
322CONFIG_PACKET=y
323# CONFIG_PACKET_MMAP is not set
324CONFIG_UNIX=y
325CONFIG_XFRM=y
326# CONFIG_XFRM_USER is not set
327# CONFIG_XFRM_SUB_POLICY is not set
328# CONFIG_XFRM_MIGRATE is not set
329# CONFIG_XFRM_STATISTICS is not set
330# CONFIG_NET_KEY is not set
331CONFIG_INET=y
332# CONFIG_IP_MULTICAST is not set
333CONFIG_IP_ADVANCED_ROUTER=y
334CONFIG_ASK_IP_FIB_HASH=y
335# CONFIG_IP_FIB_TRIE is not set
336CONFIG_IP_FIB_HASH=y
337# CONFIG_IP_MULTIPLE_TABLES is not set
338# CONFIG_IP_ROUTE_MULTIPATH is not set
339# CONFIG_IP_ROUTE_VERBOSE is not set
340CONFIG_IP_PNP=y
341CONFIG_IP_PNP_DHCP=y
342# CONFIG_IP_PNP_BOOTP is not set
343# CONFIG_IP_PNP_RARP is not set
344# CONFIG_NET_IPIP is not set
345# CONFIG_NET_IPGRE is not set
346# CONFIG_ARPD is not set
347# CONFIG_SYN_COOKIES is not set
348# CONFIG_INET_AH is not set
349# CONFIG_INET_ESP is not set
350# CONFIG_INET_IPCOMP is not set
351# CONFIG_INET_XFRM_TUNNEL is not set
352# CONFIG_INET_TUNNEL is not set
353CONFIG_INET_XFRM_MODE_TRANSPORT=y
354CONFIG_INET_XFRM_MODE_TUNNEL=y
355CONFIG_INET_XFRM_MODE_BEET=y
356# CONFIG_INET_LRO is not set
357CONFIG_INET_DIAG=y
358CONFIG_INET_TCP_DIAG=y
359# CONFIG_TCP_CONG_ADVANCED is not set
360CONFIG_TCP_CONG_CUBIC=y
361CONFIG_DEFAULT_TCP_CONG="cubic"
362# CONFIG_TCP_MD5SIG is not set
363# CONFIG_IPV6 is not set
364# CONFIG_NETWORK_SECMARK is not set
365# CONFIG_NETFILTER is not set
366# CONFIG_IP_DCCP is not set
367# CONFIG_IP_SCTP is not set
368# CONFIG_TIPC is not set
369# CONFIG_ATM is not set
370# CONFIG_BRIDGE is not set
371# CONFIG_NET_DSA is not set
372# CONFIG_VLAN_8021Q is not set
373# CONFIG_DECNET is not set
374# CONFIG_LLC2 is not set
375# CONFIG_IPX is not set
376# CONFIG_ATALK is not set
377# CONFIG_X25 is not set
378# CONFIG_LAPB is not set
379# CONFIG_ECONET is not set
380# CONFIG_WAN_ROUTER is not set
381# CONFIG_NET_SCHED is not set
382# CONFIG_DCB is not set
383
384#
385# Network testing
386#
387# CONFIG_NET_PKTGEN is not set
388# CONFIG_HAMRADIO is not set
389# CONFIG_CAN is not set
390# CONFIG_IRDA is not set
391# CONFIG_BT is not set
392# CONFIG_AF_RXRPC is not set
393# CONFIG_PHONET is not set
394CONFIG_WIRELESS=y
395# CONFIG_CFG80211 is not set
396# CONFIG_WIRELESS_OLD_REGULATORY is not set
397CONFIG_WIRELESS_EXT=y
398CONFIG_WIRELESS_EXT_SYSFS=y
399# CONFIG_LIB80211 is not set
400# CONFIG_MAC80211 is not set
401# CONFIG_WIMAX is not set
402# CONFIG_RFKILL is not set
403# CONFIG_NET_9P is not set
404
405#
406# Device Drivers
407#
408
409#
410# Generic Driver Options
411#
412CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
413CONFIG_STANDALONE=y
414CONFIG_PREVENT_FIRMWARE_BUILD=y
415# CONFIG_FW_LOADER is not set
416# CONFIG_SYS_HYPERVISOR is not set
417# CONFIG_CONNECTOR is not set
418CONFIG_MTD=y
419# CONFIG_MTD_DEBUG is not set
420CONFIG_MTD_CONCAT=y
421CONFIG_MTD_PARTITIONS=y
422# CONFIG_MTD_TESTS is not set
423# CONFIG_MTD_REDBOOT_PARTS is not set
424# CONFIG_MTD_CMDLINE_PARTS is not set
425# CONFIG_MTD_AR7_PARTS is not set
426
427#
428# User Modules And Translation Layers
429#
430CONFIG_MTD_CHAR=y
431CONFIG_MTD_BLKDEVS=y
432CONFIG_MTD_BLOCK=y
433# CONFIG_FTL is not set
434# CONFIG_NFTL is not set
435# CONFIG_INFTL is not set
436# CONFIG_RFD_FTL is not set
437# CONFIG_SSFDC is not set
438# CONFIG_MTD_OOPS is not set
439
440#
441# RAM/ROM/Flash chip drivers
442#
443CONFIG_MTD_CFI=y
444# CONFIG_MTD_JEDECPROBE is not set
445CONFIG_MTD_GEN_PROBE=y
446# CONFIG_MTD_CFI_ADV_OPTIONS is not set
447CONFIG_MTD_MAP_BANK_WIDTH_1=y
448CONFIG_MTD_MAP_BANK_WIDTH_2=y
449CONFIG_MTD_MAP_BANK_WIDTH_4=y
450# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
451# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
452# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
453CONFIG_MTD_CFI_I1=y
454CONFIG_MTD_CFI_I2=y
455# CONFIG_MTD_CFI_I4 is not set
456# CONFIG_MTD_CFI_I8 is not set
457# CONFIG_MTD_CFI_INTELEXT is not set
458CONFIG_MTD_CFI_AMDSTD=y
459# CONFIG_MTD_CFI_STAA is not set
460CONFIG_MTD_CFI_UTIL=y
461# CONFIG_MTD_RAM is not set
462# CONFIG_MTD_ROM is not set
463# CONFIG_MTD_ABSENT is not set
464
465#
466# Mapping drivers for chip access
467#
468# CONFIG_MTD_COMPLEX_MAPPINGS is not set
469CONFIG_MTD_PHYSMAP=y
470# CONFIG_MTD_PHYSMAP_COMPAT is not set
471# CONFIG_MTD_PLATRAM is not set
472
473#
474# Self-contained MTD device drivers
475#
476# CONFIG_MTD_SLRAM is not set
477# CONFIG_MTD_PHRAM is not set
478# CONFIG_MTD_MTDRAM is not set
479# CONFIG_MTD_BLOCK2MTD is not set
480
481#
482# Disk-On-Chip Device Drivers
483#
484# CONFIG_MTD_DOC2000 is not set
485# CONFIG_MTD_DOC2001 is not set
486# CONFIG_MTD_DOC2001PLUS is not set
487# CONFIG_MTD_NAND is not set
488# CONFIG_MTD_ONENAND is not set
489
490#
491# LPDDR flash memory drivers
492#
493# CONFIG_MTD_LPDDR is not set
494# CONFIG_MTD_QINFO_PROBE is not set
495
496#
497# UBI - Unsorted block images
498#
499# CONFIG_MTD_UBI is not set
500# CONFIG_PARPORT is not set
501CONFIG_BLK_DEV=y
502# CONFIG_BLK_DEV_COW_COMMON is not set
503# CONFIG_BLK_DEV_LOOP is not set
504# CONFIG_BLK_DEV_NBD is not set
505# CONFIG_BLK_DEV_UB is not set
506CONFIG_BLK_DEV_RAM=y
507CONFIG_BLK_DEV_RAM_COUNT=16
508CONFIG_BLK_DEV_RAM_SIZE=4096
509# CONFIG_BLK_DEV_XIP is not set
510# CONFIG_CDROM_PKTCDVD is not set
511# CONFIG_ATA_OVER_ETH is not set
512# CONFIG_BLK_DEV_HD is not set
513# CONFIG_MISC_DEVICES is not set
514CONFIG_HAVE_IDE=y
515# CONFIG_IDE is not set
516
517#
518# SCSI device support
519#
520# CONFIG_RAID_ATTRS is not set
521CONFIG_SCSI=y
522CONFIG_SCSI_DMA=y
523# CONFIG_SCSI_TGT is not set
524# CONFIG_SCSI_NETLINK is not set
525CONFIG_SCSI_PROC_FS=y
526
527#
528# SCSI support type (disk, tape, CD-ROM)
529#
530CONFIG_BLK_DEV_SD=y
531# CONFIG_CHR_DEV_ST is not set
532# CONFIG_CHR_DEV_OSST is not set
533# CONFIG_BLK_DEV_SR is not set
534# CONFIG_CHR_DEV_SG is not set
535# CONFIG_CHR_DEV_SCH is not set
536
537#
538# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
539#
540# CONFIG_SCSI_MULTI_LUN is not set
541# CONFIG_SCSI_CONSTANTS is not set
542# CONFIG_SCSI_LOGGING is not set
543# CONFIG_SCSI_SCAN_ASYNC is not set
544CONFIG_SCSI_WAIT_SCAN=m
545
546#
547# SCSI Transports
548#
549# CONFIG_SCSI_SPI_ATTRS is not set
550# CONFIG_SCSI_FC_ATTRS is not set
551# CONFIG_SCSI_ISCSI_ATTRS is not set
552# CONFIG_SCSI_SAS_LIBSAS is not set
553# CONFIG_SCSI_SRP_ATTRS is not set
554# CONFIG_SCSI_LOWLEVEL is not set
555# CONFIG_SCSI_DH is not set
556CONFIG_ATA=y
557# CONFIG_ATA_NONSTANDARD is not set
558CONFIG_SATA_PMP=y
559CONFIG_ATA_SFF=y
560# CONFIG_SATA_MV is not set
561# CONFIG_PATA_PLATFORM is not set
562# CONFIG_MD is not set
563CONFIG_NETDEVICES=y
564# CONFIG_DUMMY is not set
565# CONFIG_BONDING is not set
566# CONFIG_MACVLAN is not set
567# CONFIG_EQUALIZER is not set
568# CONFIG_TUN is not set
569# CONFIG_VETH is not set
570CONFIG_PHYLIB=y
571
572#
573# MII PHY device drivers
574#
575# CONFIG_MARVELL_PHY is not set
576# CONFIG_DAVICOM_PHY is not set
577# CONFIG_QSEMI_PHY is not set
578# CONFIG_LXT_PHY is not set
579# CONFIG_CICADA_PHY is not set
580# CONFIG_VITESSE_PHY is not set
581# CONFIG_SMSC_PHY is not set
582# CONFIG_BROADCOM_PHY is not set
583# CONFIG_ICPLUS_PHY is not set
584# CONFIG_REALTEK_PHY is not set
585# CONFIG_NATIONAL_PHY is not set
586# CONFIG_STE10XP is not set
587# CONFIG_LSI_ET1011C_PHY is not set
588# CONFIG_FIXED_PHY is not set
589# CONFIG_MDIO_BITBANG is not set
590CONFIG_NET_ETHERNET=y
591CONFIG_MII=y
592# CONFIG_AX88796 is not set
593# CONFIG_STNIC is not set
594CONFIG_SMC91X=y
595# CONFIG_SMC911X is not set
596# CONFIG_SMSC911X is not set
597# CONFIG_IBM_NEW_EMAC_ZMII is not set
598# CONFIG_IBM_NEW_EMAC_RGMII is not set
599# CONFIG_IBM_NEW_EMAC_TAH is not set
600# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
601# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
602# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
603# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
604# CONFIG_B44 is not set
605# CONFIG_NETDEV_1000 is not set
606# CONFIG_NETDEV_10000 is not set
607
608#
609# Wireless LAN
610#
611# CONFIG_WLAN_PRE80211 is not set
612# CONFIG_WLAN_80211 is not set
613# CONFIG_IWLWIFI_LEDS is not set
614
615#
616# Enable WiMAX (Networking options) to see the WiMAX drivers
617#
618
619#
620# USB Network Adapters
621#
622# CONFIG_USB_CATC is not set
623# CONFIG_USB_KAWETH is not set
624# CONFIG_USB_PEGASUS is not set
625# CONFIG_USB_RTL8150 is not set
626# CONFIG_USB_USBNET is not set
627# CONFIG_WAN is not set
628# CONFIG_PPP is not set
629# CONFIG_SLIP is not set
630# CONFIG_NETCONSOLE is not set
631# CONFIG_NETPOLL is not set
632# CONFIG_NET_POLL_CONTROLLER is not set
633# CONFIG_ISDN is not set
634# CONFIG_PHONE is not set
635
636#
637# Input device support
638#
639CONFIG_INPUT=y
640CONFIG_INPUT_FF_MEMLESS=m
641# CONFIG_INPUT_POLLDEV is not set
642
643#
644# Userland interfaces
645#
646CONFIG_INPUT_MOUSEDEV=y
647# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
648CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
649CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
650# CONFIG_INPUT_JOYDEV is not set
651# CONFIG_INPUT_EVDEV is not set
652# CONFIG_INPUT_EVBUG is not set
653
654#
655# Input Device Drivers
656#
657CONFIG_INPUT_KEYBOARD=y
658# CONFIG_KEYBOARD_ATKBD is not set
659# CONFIG_KEYBOARD_SUNKBD is not set
660# CONFIG_KEYBOARD_LKKBD is not set
661# CONFIG_KEYBOARD_XTKBD is not set
662# CONFIG_KEYBOARD_NEWTON is not set
663# CONFIG_KEYBOARD_STOWAWAY is not set
664# CONFIG_KEYBOARD_GPIO is not set
665# CONFIG_KEYBOARD_SH_KEYSC is not set
666# CONFIG_INPUT_MOUSE is not set
667# CONFIG_INPUT_JOYSTICK is not set
668# CONFIG_INPUT_TABLET is not set
669# CONFIG_INPUT_TOUCHSCREEN is not set
670# CONFIG_INPUT_MISC is not set
671
672#
673# Hardware I/O ports
674#
675# CONFIG_SERIO is not set
676# CONFIG_GAMEPORT is not set
677
678#
679# Character devices
680#
681CONFIG_VT=y
682CONFIG_CONSOLE_TRANSLATIONS=y
683CONFIG_VT_CONSOLE=y
684CONFIG_HW_CONSOLE=y
685CONFIG_VT_HW_CONSOLE_BINDING=y
686CONFIG_DEVKMEM=y
687# CONFIG_SERIAL_NONSTANDARD is not set
688
689#
690# Serial drivers
691#
692# CONFIG_SERIAL_8250 is not set
693
694#
695# Non-8250 serial port support
696#
697CONFIG_SERIAL_SH_SCI=y
698CONFIG_SERIAL_SH_SCI_NR_UARTS=6
699CONFIG_SERIAL_SH_SCI_CONSOLE=y
700CONFIG_SERIAL_CORE=y
701CONFIG_SERIAL_CORE_CONSOLE=y
702CONFIG_UNIX98_PTYS=y
703# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
704CONFIG_LEGACY_PTYS=y
705CONFIG_LEGACY_PTY_COUNT=256
706# CONFIG_IPMI_HANDLER is not set
707CONFIG_HW_RANDOM=y
708# CONFIG_R3964 is not set
709# CONFIG_RAW_DRIVER is not set
710# CONFIG_TCG_TPM is not set
711CONFIG_I2C=y
712CONFIG_I2C_BOARDINFO=y
713# CONFIG_I2C_CHARDEV is not set
714CONFIG_I2C_HELPER_AUTO=y
715CONFIG_I2C_ALGOPCA=y
716
717#
718# I2C Hardware Bus support
719#
720
721#
722# I2C system bus drivers (mostly embedded / system-on-chip)
723#
724# CONFIG_I2C_GPIO is not set
725# CONFIG_I2C_OCORES is not set
726# CONFIG_I2C_SH_MOBILE is not set
727# CONFIG_I2C_SIMTEC is not set
728
729#
730# External I2C/SMBus adapter drivers
731#
732# CONFIG_I2C_PARPORT_LIGHT is not set
733# CONFIG_I2C_TAOS_EVM is not set
734# CONFIG_I2C_TINY_USB is not set
735
736#
737# Other I2C/SMBus bus drivers
738#
739CONFIG_I2C_PCA_PLATFORM=y
740# CONFIG_I2C_STUB is not set
741
742#
743# Miscellaneous I2C Chip support
744#
745# CONFIG_DS1682 is not set
746# CONFIG_SENSORS_PCF8574 is not set
747# CONFIG_PCF8575 is not set
748# CONFIG_SENSORS_PCA9539 is not set
749# CONFIG_SENSORS_PCF8591 is not set
750# CONFIG_SENSORS_MAX6875 is not set
751# CONFIG_SENSORS_TSL2550 is not set
752# CONFIG_I2C_DEBUG_CORE is not set
753# CONFIG_I2C_DEBUG_ALGO is not set
754# CONFIG_I2C_DEBUG_BUS is not set
755# CONFIG_I2C_DEBUG_CHIP is not set
756# CONFIG_SPI is not set
757CONFIG_ARCH_REQUIRE_GPIOLIB=y
758CONFIG_GPIOLIB=y
759# CONFIG_GPIO_SYSFS is not set
760
761#
762# Memory mapped GPIO expanders:
763#
764
765#
766# I2C GPIO expanders:
767#
768# CONFIG_GPIO_MAX732X is not set
769# CONFIG_GPIO_PCA953X is not set
770# CONFIG_GPIO_PCF857X is not set
771
772#
773# PCI GPIO expanders:
774#
775
776#
777# SPI GPIO expanders:
778#
779# CONFIG_W1 is not set
780# CONFIG_POWER_SUPPLY is not set
781# CONFIG_HWMON is not set
782# CONFIG_THERMAL is not set
783# CONFIG_THERMAL_HWMON is not set
784# CONFIG_WATCHDOG is not set
785CONFIG_SSB_POSSIBLE=y
786
787#
788# Sonics Silicon Backplane
789#
790# CONFIG_SSB is not set
791
792#
793# Multifunction device drivers
794#
795# CONFIG_MFD_CORE is not set
796CONFIG_MFD_SM501=y
797# CONFIG_MFD_SM501_GPIO is not set
798# CONFIG_HTC_PASIC3 is not set
799# CONFIG_TPS65010 is not set
800# CONFIG_TWL4030_CORE is not set
801# CONFIG_MFD_TMIO is not set
802# CONFIG_PMIC_DA903X is not set
803# CONFIG_MFD_WM8400 is not set
804# CONFIG_MFD_WM8350_I2C is not set
805# CONFIG_MFD_PCF50633 is not set
806# CONFIG_REGULATOR is not set
807
808#
809# Multimedia devices
810#
811
812#
813# Multimedia core support
814#
815# CONFIG_VIDEO_DEV is not set
816# CONFIG_DVB_CORE is not set
817# CONFIG_VIDEO_MEDIA is not set
818
819#
820# Multimedia drivers
821#
822# CONFIG_DAB is not set
823
824#
825# Graphics support
826#
827# CONFIG_VGASTATE is not set
828# CONFIG_VIDEO_OUTPUT_CONTROL is not set
829CONFIG_FB=y
830# CONFIG_FIRMWARE_EDID is not set
831# CONFIG_FB_DDC is not set
832# CONFIG_FB_BOOT_VESA_SUPPORT is not set
833CONFIG_FB_CFB_FILLRECT=y
834CONFIG_FB_CFB_COPYAREA=y
835CONFIG_FB_CFB_IMAGEBLIT=y
836# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
837CONFIG_FB_SYS_FILLRECT=m
838CONFIG_FB_SYS_COPYAREA=m
839CONFIG_FB_SYS_IMAGEBLIT=m
840# CONFIG_FB_FOREIGN_ENDIAN is not set
841CONFIG_FB_SYS_FOPS=m
842CONFIG_FB_DEFERRED_IO=y
843# CONFIG_FB_SVGALIB is not set
844# CONFIG_FB_MACMODES is not set
845# CONFIG_FB_BACKLIGHT is not set
846# CONFIG_FB_MODE_HELPERS is not set
847# CONFIG_FB_TILEBLITTING is not set
848
849#
850# Frame buffer hardware drivers
851#
852# CONFIG_FB_S1D13XXX is not set
853CONFIG_FB_SH_MOBILE_LCDC=m
854CONFIG_FB_SM501=y
855# CONFIG_FB_VIRTUAL is not set
856# CONFIG_FB_METRONOME is not set
857# CONFIG_FB_MB862XX is not set
858# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
859
860#
861# Display device support
862#
863# CONFIG_DISPLAY_SUPPORT is not set
864
865#
866# Console display driver support
867#
868CONFIG_DUMMY_CONSOLE=y
869CONFIG_FRAMEBUFFER_CONSOLE=y
870# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
871# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
872# CONFIG_FONTS is not set
873CONFIG_FONT_8x8=y
874CONFIG_FONT_8x16=y
875CONFIG_LOGO=y
876# CONFIG_LOGO_LINUX_MONO is not set
877# CONFIG_LOGO_LINUX_VGA16 is not set
878CONFIG_LOGO_LINUX_CLUT224=y
879# CONFIG_LOGO_SUPERH_MONO is not set
880# CONFIG_LOGO_SUPERH_VGA16 is not set
881# CONFIG_LOGO_SUPERH_CLUT224 is not set
882# CONFIG_SOUND is not set
883CONFIG_HID_SUPPORT=y
884CONFIG_HID=y
885# CONFIG_HID_DEBUG is not set
886# CONFIG_HIDRAW is not set
887
888#
889# USB Input Devices
890#
891CONFIG_USB_HID=y
892# CONFIG_HID_PID is not set
893# CONFIG_USB_HIDDEV is not set
894
895#
896# Special HID drivers
897#
898CONFIG_HID_COMPAT=y
899CONFIG_HID_A4TECH=y
900CONFIG_HID_APPLE=y
901CONFIG_HID_BELKIN=y
902CONFIG_HID_CHERRY=y
903CONFIG_HID_CHICONY=y
904CONFIG_HID_CYPRESS=y
905CONFIG_HID_EZKEY=y
906CONFIG_HID_GYRATION=y
907CONFIG_HID_LOGITECH=y
908# CONFIG_LOGITECH_FF is not set
909# CONFIG_LOGIRUMBLEPAD2_FF is not set
910CONFIG_HID_MICROSOFT=y
911CONFIG_HID_MONTEREY=y
912# CONFIG_HID_NTRIG is not set
913CONFIG_HID_PANTHERLORD=y
914# CONFIG_PANTHERLORD_FF is not set
915CONFIG_HID_PETALYNX=y
916CONFIG_HID_SAMSUNG=y
917CONFIG_HID_SONY=y
918CONFIG_HID_SUNPLUS=y
919# CONFIG_GREENASIA_FF is not set
920# CONFIG_HID_TOPSEED is not set
921CONFIG_THRUSTMASTER_FF=m
922CONFIG_ZEROPLUS_FF=m
923CONFIG_USB_SUPPORT=y
924CONFIG_USB_ARCH_HAS_HCD=y
925# CONFIG_USB_ARCH_HAS_OHCI is not set
926# CONFIG_USB_ARCH_HAS_EHCI is not set
927CONFIG_USB=y
928# CONFIG_USB_DEBUG is not set
929CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
930
931#
932# Miscellaneous USB options
933#
934CONFIG_USB_DEVICEFS=y
935CONFIG_USB_DEVICE_CLASS=y
936# CONFIG_USB_DYNAMIC_MINORS is not set
937# CONFIG_USB_OTG is not set
938# CONFIG_USB_OTG_WHITELIST is not set
939# CONFIG_USB_OTG_BLACKLIST_HUB is not set
940CONFIG_USB_MON=y
941# CONFIG_USB_WUSB is not set
942# CONFIG_USB_WUSB_CBAF is not set
943
944#
945# USB Host Controller Drivers
946#
947# CONFIG_USB_C67X00_HCD is not set
948# CONFIG_USB_OXU210HP_HCD is not set
949# CONFIG_USB_ISP116X_HCD is not set
950# CONFIG_USB_SL811_HCD is not set
951# CONFIG_USB_R8A66597_HCD is not set
952# CONFIG_USB_HWA_HCD is not set
953
954#
955# USB Device Class drivers
956#
957# CONFIG_USB_ACM is not set
958# CONFIG_USB_PRINTER is not set
959# CONFIG_USB_WDM is not set
960# CONFIG_USB_TMC is not set
961
962#
963# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
964#
965
966#
967# see USB_STORAGE Help for more information
968#
969CONFIG_USB_STORAGE=y
970# CONFIG_USB_STORAGE_DEBUG is not set
971# CONFIG_USB_STORAGE_DATAFAB is not set
972# CONFIG_USB_STORAGE_FREECOM is not set
973# CONFIG_USB_STORAGE_ISD200 is not set
974# CONFIG_USB_STORAGE_USBAT is not set
975# CONFIG_USB_STORAGE_SDDR09 is not set
976# CONFIG_USB_STORAGE_SDDR55 is not set
977# CONFIG_USB_STORAGE_JUMPSHOT is not set
978# CONFIG_USB_STORAGE_ALAUDA is not set
979# CONFIG_USB_STORAGE_ONETOUCH is not set
980# CONFIG_USB_STORAGE_KARMA is not set
981# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
982# CONFIG_USB_LIBUSUAL is not set
983
984#
985# USB Imaging devices
986#
987# CONFIG_USB_MDC800 is not set
988# CONFIG_USB_MICROTEK is not set
989
990#
991# USB port drivers
992#
993# CONFIG_USB_SERIAL is not set
994
995#
996# USB Miscellaneous drivers
997#
998# CONFIG_USB_EMI62 is not set
999# CONFIG_USB_EMI26 is not set
1000# CONFIG_USB_ADUTUX is not set
1001# CONFIG_USB_SEVSEG is not set
1002# CONFIG_USB_RIO500 is not set
1003# CONFIG_USB_LEGOTOWER is not set
1004# CONFIG_USB_LCD is not set
1005# CONFIG_USB_BERRY_CHARGE is not set
1006# CONFIG_USB_LED is not set
1007# CONFIG_USB_CYPRESS_CY7C63 is not set
1008# CONFIG_USB_CYTHERM is not set
1009# CONFIG_USB_PHIDGET is not set
1010# CONFIG_USB_IDMOUSE is not set
1011# CONFIG_USB_FTDI_ELAN is not set
1012# CONFIG_USB_APPLEDISPLAY is not set
1013# CONFIG_USB_LD is not set
1014# CONFIG_USB_TRANCEVIBRATOR is not set
1015# CONFIG_USB_IOWARRIOR is not set
1016# CONFIG_USB_TEST is not set
1017# CONFIG_USB_ISIGHTFW is not set
1018# CONFIG_USB_VST is not set
1019# CONFIG_USB_GADGET is not set
1020
1021#
1022# OTG and related infrastructure
1023#
1024# CONFIG_USB_GPIO_VBUS is not set
1025# CONFIG_MMC is not set
1026# CONFIG_MEMSTICK is not set
1027# CONFIG_NEW_LEDS is not set
1028# CONFIG_ACCESSIBILITY is not set
1029# CONFIG_RTC_CLASS is not set
1030# CONFIG_DMADEVICES is not set
1031# CONFIG_UIO is not set
1032# CONFIG_STAGING is not set
1033
1034#
1035# File systems
1036#
1037CONFIG_EXT2_FS=y
1038# CONFIG_EXT2_FS_XATTR is not set
1039# CONFIG_EXT2_FS_XIP is not set
1040CONFIG_EXT3_FS=y
1041CONFIG_EXT3_FS_XATTR=y
1042# CONFIG_EXT3_FS_POSIX_ACL is not set
1043# CONFIG_EXT3_FS_SECURITY is not set
1044# CONFIG_EXT4_FS is not set
1045CONFIG_JBD=y
1046CONFIG_FS_MBCACHE=y
1047# CONFIG_REISERFS_FS is not set
1048# CONFIG_JFS_FS is not set
1049CONFIG_FS_POSIX_ACL=y
1050CONFIG_FILE_LOCKING=y
1051# CONFIG_XFS_FS is not set
1052# CONFIG_OCFS2_FS is not set
1053# CONFIG_BTRFS_FS is not set
1054CONFIG_DNOTIFY=y
1055CONFIG_INOTIFY=y
1056CONFIG_INOTIFY_USER=y
1057# CONFIG_QUOTA is not set
1058# CONFIG_AUTOFS_FS is not set
1059# CONFIG_AUTOFS4_FS is not set
1060# CONFIG_FUSE_FS is not set
1061
1062#
1063# CD-ROM/DVD Filesystems
1064#
1065# CONFIG_ISO9660_FS is not set
1066# CONFIG_UDF_FS is not set
1067
1068#
1069# DOS/FAT/NT Filesystems
1070#
1071CONFIG_FAT_FS=y
1072CONFIG_MSDOS_FS=y
1073CONFIG_VFAT_FS=y
1074CONFIG_FAT_DEFAULT_CODEPAGE=437
1075CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1076CONFIG_NTFS_FS=y
1077# CONFIG_NTFS_DEBUG is not set
1078CONFIG_NTFS_RW=y
1079
1080#
1081# Pseudo filesystems
1082#
1083CONFIG_PROC_FS=y
1084CONFIG_PROC_KCORE=y
1085CONFIG_PROC_SYSCTL=y
1086CONFIG_PROC_PAGE_MONITOR=y
1087CONFIG_SYSFS=y
1088CONFIG_TMPFS=y
1089# CONFIG_TMPFS_POSIX_ACL is not set
1090# CONFIG_HUGETLBFS is not set
1091# CONFIG_HUGETLB_PAGE is not set
1092# CONFIG_CONFIGFS_FS is not set
1093CONFIG_MISC_FILESYSTEMS=y
1094# CONFIG_ADFS_FS is not set
1095# CONFIG_AFFS_FS is not set
1096# CONFIG_HFS_FS is not set
1097# CONFIG_HFSPLUS_FS is not set
1098# CONFIG_BEFS_FS is not set
1099# CONFIG_BFS_FS is not set
1100# CONFIG_EFS_FS is not set
1101# CONFIG_JFFS2_FS is not set
1102# CONFIG_CRAMFS is not set
1103# CONFIG_SQUASHFS is not set
1104# CONFIG_VXFS_FS is not set
1105CONFIG_MINIX_FS=y
1106# CONFIG_OMFS_FS is not set
1107# CONFIG_HPFS_FS is not set
1108# CONFIG_QNX4FS_FS is not set
1109# CONFIG_ROMFS_FS is not set
1110# CONFIG_SYSV_FS is not set
1111# CONFIG_UFS_FS is not set
1112CONFIG_NETWORK_FILESYSTEMS=y
1113CONFIG_NFS_FS=y
1114CONFIG_NFS_V3=y
1115# CONFIG_NFS_V3_ACL is not set
1116CONFIG_NFS_V4=y
1117CONFIG_ROOT_NFS=y
1118CONFIG_NFSD=y
1119CONFIG_NFSD_V3=y
1120# CONFIG_NFSD_V3_ACL is not set
1121CONFIG_NFSD_V4=y
1122CONFIG_LOCKD=y
1123CONFIG_LOCKD_V4=y
1124CONFIG_EXPORTFS=y
1125CONFIG_NFS_COMMON=y
1126CONFIG_SUNRPC=y
1127CONFIG_SUNRPC_GSS=y
1128# CONFIG_SUNRPC_REGISTER_V4 is not set
1129CONFIG_RPCSEC_GSS_KRB5=y
1130# CONFIG_RPCSEC_GSS_SPKM3 is not set
1131# CONFIG_SMB_FS is not set
1132# CONFIG_CIFS is not set
1133# CONFIG_NCP_FS is not set
1134# CONFIG_CODA_FS is not set
1135# CONFIG_AFS_FS is not set
1136
1137#
1138# Partition Types
1139#
1140# CONFIG_PARTITION_ADVANCED is not set
1141CONFIG_MSDOS_PARTITION=y
1142CONFIG_NLS=y
1143CONFIG_NLS_DEFAULT="iso8859-1"
1144CONFIG_NLS_CODEPAGE_437=y
1145# CONFIG_NLS_CODEPAGE_737 is not set
1146# CONFIG_NLS_CODEPAGE_775 is not set
1147# CONFIG_NLS_CODEPAGE_850 is not set
1148# CONFIG_NLS_CODEPAGE_852 is not set
1149# CONFIG_NLS_CODEPAGE_855 is not set
1150# CONFIG_NLS_CODEPAGE_857 is not set
1151# CONFIG_NLS_CODEPAGE_860 is not set
1152# CONFIG_NLS_CODEPAGE_861 is not set
1153# CONFIG_NLS_CODEPAGE_862 is not set
1154# CONFIG_NLS_CODEPAGE_863 is not set
1155# CONFIG_NLS_CODEPAGE_864 is not set
1156# CONFIG_NLS_CODEPAGE_865 is not set
1157# CONFIG_NLS_CODEPAGE_866 is not set
1158# CONFIG_NLS_CODEPAGE_869 is not set
1159# CONFIG_NLS_CODEPAGE_936 is not set
1160# CONFIG_NLS_CODEPAGE_950 is not set
1161CONFIG_NLS_CODEPAGE_932=y
1162# CONFIG_NLS_CODEPAGE_949 is not set
1163# CONFIG_NLS_CODEPAGE_874 is not set
1164# CONFIG_NLS_ISO8859_8 is not set
1165# CONFIG_NLS_CODEPAGE_1250 is not set
1166# CONFIG_NLS_CODEPAGE_1251 is not set
1167# CONFIG_NLS_ASCII is not set
1168CONFIG_NLS_ISO8859_1=y
1169# CONFIG_NLS_ISO8859_2 is not set
1170# CONFIG_NLS_ISO8859_3 is not set
1171# CONFIG_NLS_ISO8859_4 is not set
1172# CONFIG_NLS_ISO8859_5 is not set
1173# CONFIG_NLS_ISO8859_6 is not set
1174# CONFIG_NLS_ISO8859_7 is not set
1175# CONFIG_NLS_ISO8859_9 is not set
1176# CONFIG_NLS_ISO8859_13 is not set
1177# CONFIG_NLS_ISO8859_14 is not set
1178# CONFIG_NLS_ISO8859_15 is not set
1179# CONFIG_NLS_KOI8_R is not set
1180# CONFIG_NLS_KOI8_U is not set
1181# CONFIG_NLS_UTF8 is not set
1182# CONFIG_DLM is not set
1183
1184#
1185# Kernel hacking
1186#
1187CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1188# CONFIG_PRINTK_TIME is not set
1189# CONFIG_ENABLE_WARN_DEPRECATED is not set
1190# CONFIG_ENABLE_MUST_CHECK is not set
1191CONFIG_FRAME_WARN=1024
1192# CONFIG_MAGIC_SYSRQ is not set
1193# CONFIG_UNUSED_SYMBOLS is not set
1194# CONFIG_DEBUG_FS is not set
1195# CONFIG_HEADERS_CHECK is not set
1196# CONFIG_DEBUG_KERNEL is not set
1197# CONFIG_DEBUG_BUGVERBOSE is not set
1198# CONFIG_DEBUG_MEMORY_INIT is not set
1199# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1200# CONFIG_LATENCYTOP is not set
1201CONFIG_SYSCTL_SYSCALL_CHECK=y
1202CONFIG_HAVE_FUNCTION_TRACER=y
1203CONFIG_HAVE_DYNAMIC_FTRACE=y
1204CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1205
1206#
1207# Tracers
1208#
1209# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
1210# CONFIG_SAMPLES is not set
1211CONFIG_HAVE_ARCH_KGDB=y
1212# CONFIG_SH_STANDARD_BIOS is not set
1213# CONFIG_EARLY_SCIF_CONSOLE is not set
1214# CONFIG_MORE_COMPILE_OPTIONS is not set
1215
1216#
1217# Security options
1218#
1219# CONFIG_KEYS is not set
1220# CONFIG_SECURITY is not set
1221# CONFIG_SECURITYFS is not set
1222# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1223CONFIG_CRYPTO=y
1224
1225#
1226# Crypto core or helper
1227#
1228# CONFIG_CRYPTO_FIPS is not set
1229CONFIG_CRYPTO_ALGAPI=y
1230CONFIG_CRYPTO_ALGAPI2=y
1231CONFIG_CRYPTO_AEAD2=y
1232CONFIG_CRYPTO_BLKCIPHER=y
1233CONFIG_CRYPTO_BLKCIPHER2=y
1234CONFIG_CRYPTO_HASH=y
1235CONFIG_CRYPTO_HASH2=y
1236CONFIG_CRYPTO_RNG2=y
1237CONFIG_CRYPTO_MANAGER=y
1238CONFIG_CRYPTO_MANAGER2=y
1239# CONFIG_CRYPTO_GF128MUL is not set
1240# CONFIG_CRYPTO_NULL is not set
1241# CONFIG_CRYPTO_CRYPTD is not set
1242# CONFIG_CRYPTO_AUTHENC is not set
1243# CONFIG_CRYPTO_TEST is not set
1244
1245#
1246# Authenticated Encryption with Associated Data
1247#
1248# CONFIG_CRYPTO_CCM is not set
1249# CONFIG_CRYPTO_GCM is not set
1250# CONFIG_CRYPTO_SEQIV is not set
1251
1252#
1253# Block modes
1254#
1255CONFIG_CRYPTO_CBC=y
1256# CONFIG_CRYPTO_CTR is not set
1257# CONFIG_CRYPTO_CTS is not set
1258# CONFIG_CRYPTO_ECB is not set
1259# CONFIG_CRYPTO_LRW is not set
1260# CONFIG_CRYPTO_PCBC is not set
1261# CONFIG_CRYPTO_XTS is not set
1262
1263#
1264# Hash modes
1265#
1266CONFIG_CRYPTO_HMAC=y
1267# CONFIG_CRYPTO_XCBC is not set
1268
1269#
1270# Digest
1271#
1272# CONFIG_CRYPTO_CRC32C is not set
1273# CONFIG_CRYPTO_MD4 is not set
1274CONFIG_CRYPTO_MD5=y
1275# CONFIG_CRYPTO_MICHAEL_MIC is not set
1276# CONFIG_CRYPTO_RMD128 is not set
1277# CONFIG_CRYPTO_RMD160 is not set
1278# CONFIG_CRYPTO_RMD256 is not set
1279# CONFIG_CRYPTO_RMD320 is not set
1280# CONFIG_CRYPTO_SHA1 is not set
1281# CONFIG_CRYPTO_SHA256 is not set
1282# CONFIG_CRYPTO_SHA512 is not set
1283# CONFIG_CRYPTO_TGR192 is not set
1284# CONFIG_CRYPTO_WP512 is not set
1285
1286#
1287# Ciphers
1288#
1289# CONFIG_CRYPTO_AES is not set
1290# CONFIG_CRYPTO_ANUBIS is not set
1291# CONFIG_CRYPTO_ARC4 is not set
1292# CONFIG_CRYPTO_BLOWFISH is not set
1293# CONFIG_CRYPTO_CAMELLIA is not set
1294# CONFIG_CRYPTO_CAST5 is not set
1295# CONFIG_CRYPTO_CAST6 is not set
1296CONFIG_CRYPTO_DES=y
1297# CONFIG_CRYPTO_FCRYPT is not set
1298# CONFIG_CRYPTO_KHAZAD is not set
1299# CONFIG_CRYPTO_SALSA20 is not set
1300# CONFIG_CRYPTO_SEED is not set
1301# CONFIG_CRYPTO_SERPENT is not set
1302# CONFIG_CRYPTO_TEA is not set
1303# CONFIG_CRYPTO_TWOFISH is not set
1304
1305#
1306# Compression
1307#
1308# CONFIG_CRYPTO_DEFLATE is not set
1309# CONFIG_CRYPTO_LZO is not set
1310
1311#
1312# Random Number Generation
1313#
1314# CONFIG_CRYPTO_ANSI_CPRNG is not set
1315# CONFIG_CRYPTO_HW is not set
1316
1317#
1318# Library routines
1319#
1320CONFIG_BITREVERSE=y
1321CONFIG_GENERIC_FIND_LAST_BIT=y
1322# CONFIG_CRC_CCITT is not set
1323# CONFIG_CRC16 is not set
1324# CONFIG_CRC_T10DIF is not set
1325# CONFIG_CRC_ITU_T is not set
1326CONFIG_CRC32=y
1327# CONFIG_CRC7 is not set
1328# CONFIG_LIBCRC32C is not set
1329CONFIG_PLIST=y
1330CONFIG_HAS_IOMEM=y
1331CONFIG_HAS_IOPORT=y
1332CONFIG_HAS_DMA=y
diff --git a/arch/sh/drivers/dma/Kconfig b/arch/sh/drivers/dma/Kconfig
index 01936368b8b0..f13a05285a9d 100644
--- a/arch/sh/drivers/dma/Kconfig
+++ b/arch/sh/drivers/dma/Kconfig
@@ -9,13 +9,21 @@ config SH_DMA
9 select SH_DMA_API 9 select SH_DMA_API
10 default n 10 default n
11 11
12config SH_DMA_IRQ_MULTI
13 bool
14 depends on SH_DMA
15 default y if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || \
16 CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || \
17 CPU_SUBTYPE_SH7091 || CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7764 || \
18 CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
19
12config NR_ONCHIP_DMA_CHANNELS 20config NR_ONCHIP_DMA_CHANNELS
13 int 21 int
14 depends on SH_DMA 22 depends on SH_DMA
15 default "6" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721 23 default "4" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7750S
16 default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R 24 default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || CPU_SUBTYPE_SH7760
17 default "12" if CPU_SUBTYPE_SH7780 25 default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
18 default "4" 26 default "6"
19 help 27 help
20 This allows you to specify the number of channels that the on-chip 28 This allows you to specify the number of channels that the on-chip
21 DMAC supports. This will be 4 for SH7750/SH7751 and 8 for the 29 DMAC supports. This will be 4 for SH7750/SH7751 and 8 for the
@@ -46,4 +54,28 @@ config SH_DMABRG
46 of the SH7760. 54 of the SH7760.
47 Say Y if you want to use Audio/USB DMA on your SH7760 board. 55 Say Y if you want to use Audio/USB DMA on your SH7760 board.
48 56
57config PVR2_DMA
58 tristate "PowerVR 2 DMAC support"
59 depends on SH_DREAMCAST && SH_DMA
60 help
61 Selecting this will enable support for the PVR2 DMA controller.
62 As this chains off of the on-chip DMAC, that must also be
63 enabled by default.
64
65 This is primarily used by the pvr2fb framebuffer driver for
66 certain optimizations, but is not necessary for functionality.
67
68 If in doubt, say N.
69
70config G2_DMA
71 tristate "G2 Bus DMA support"
72 depends on SH_DREAMCAST
73 select SH_DMA_API
74 help
75 This enables support for the DMA controller for the Dreamcast's
76 G2 bus. Drivers that want this will generally enable this on
77 their own.
78
79 If in doubt, say N.
80
49endmenu 81endmenu
diff --git a/arch/sh/drivers/dma/Makefile b/arch/sh/drivers/dma/Makefile
index ab956adacb47..c6068137b46f 100644
--- a/arch/sh/drivers/dma/Makefile
+++ b/arch/sh/drivers/dma/Makefile
@@ -4,5 +4,6 @@
4 4
5obj-$(CONFIG_SH_DMA_API) += dma-api.o dma-sysfs.o 5obj-$(CONFIG_SH_DMA_API) += dma-api.o dma-sysfs.o
6obj-$(CONFIG_SH_DMA) += dma-sh.o 6obj-$(CONFIG_SH_DMA) += dma-sh.o
7obj-$(CONFIG_SH_DREAMCAST) += dma-pvr2.o dma-g2.o 7obj-$(CONFIG_PVR2_DMA) += dma-pvr2.o
8obj-$(CONFIG_G2_DMA) += dma-g2.o
8obj-$(CONFIG_SH_DMABRG) += dmabrg.o 9obj-$(CONFIG_SH_DMABRG) += dmabrg.o
diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c
index 50887a592dd0..37fb5b8bbc3f 100644
--- a/arch/sh/drivers/dma/dma-sh.c
+++ b/arch/sh/drivers/dma/dma-sh.c
@@ -17,28 +17,16 @@
17#include <mach-dreamcast/mach/dma.h> 17#include <mach-dreamcast/mach/dma.h>
18#include <asm/dma.h> 18#include <asm/dma.h>
19#include <asm/io.h> 19#include <asm/io.h>
20#include "dma-sh.h" 20#include <asm/dma-sh.h>
21 21
22static int dmte_irq_map[] = { 22#if defined(DMAE1_IRQ)
23 DMTE0_IRQ, 23#define NR_DMAE 2
24 DMTE1_IRQ, 24#else
25 DMTE2_IRQ, 25#define NR_DMAE 1
26 DMTE3_IRQ,
27#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
28 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
29 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
30 defined(CONFIG_CPU_SUBTYPE_SH7760) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7780)
33 DMTE4_IRQ,
34 DMTE5_IRQ,
35#endif
36#if defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
37 defined(CONFIG_CPU_SUBTYPE_SH7760) || \
38 defined(CONFIG_CPU_SUBTYPE_SH7780)
39 DMTE6_IRQ,
40 DMTE7_IRQ,
41#endif 26#endif
27
28static const char *dmae_name[] = {
29 "DMAC Address Error0", "DMAC Address Error1"
42}; 30};
43 31
44static inline unsigned int get_dmte_irq(unsigned int chan) 32static inline unsigned int get_dmte_irq(unsigned int chan)
@@ -46,7 +34,14 @@ static inline unsigned int get_dmte_irq(unsigned int chan)
46 unsigned int irq = 0; 34 unsigned int irq = 0;
47 if (chan < ARRAY_SIZE(dmte_irq_map)) 35 if (chan < ARRAY_SIZE(dmte_irq_map))
48 irq = dmte_irq_map[chan]; 36 irq = dmte_irq_map[chan];
37
38#if defined(CONFIG_SH_DMA_IRQ_MULTI)
39 if (irq > DMTE6_IRQ)
40 return DMTE6_IRQ;
41 return DMTE0_IRQ;
42#else
49 return irq; 43 return irq;
44#endif
50} 45}
51 46
52/* 47/*
@@ -59,7 +54,7 @@ static inline unsigned int get_dmte_irq(unsigned int chan)
59 */ 54 */
60static inline unsigned int calc_xmit_shift(struct dma_channel *chan) 55static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
61{ 56{
62 u32 chcr = ctrl_inl(CHCR[chan->chan]); 57 u32 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
63 58
64 return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT]; 59 return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT];
65} 60}
@@ -75,13 +70,13 @@ static irqreturn_t dma_tei(int irq, void *dev_id)
75 struct dma_channel *chan = dev_id; 70 struct dma_channel *chan = dev_id;
76 u32 chcr; 71 u32 chcr;
77 72
78 chcr = ctrl_inl(CHCR[chan->chan]); 73 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
79 74
80 if (!(chcr & CHCR_TE)) 75 if (!(chcr & CHCR_TE))
81 return IRQ_NONE; 76 return IRQ_NONE;
82 77
83 chcr &= ~(CHCR_IE | CHCR_DE); 78 chcr &= ~(CHCR_IE | CHCR_DE);
84 ctrl_outl(chcr, CHCR[chan->chan]); 79 ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
85 80
86 wake_up(&chan->wait_queue); 81 wake_up(&chan->wait_queue);
87 82
@@ -94,7 +89,12 @@ static int sh_dmac_request_dma(struct dma_channel *chan)
94 return 0; 89 return 0;
95 90
96 return request_irq(get_dmte_irq(chan->chan), dma_tei, 91 return request_irq(get_dmte_irq(chan->chan), dma_tei,
97 IRQF_DISABLED, chan->dev_id, chan); 92#if defined(CONFIG_SH_DMA_IRQ_MULTI)
93 IRQF_SHARED,
94#else
95 IRQF_DISABLED,
96#endif
97 chan->dev_id, chan);
98} 98}
99 99
100static void sh_dmac_free_dma(struct dma_channel *chan) 100static void sh_dmac_free_dma(struct dma_channel *chan)
@@ -115,7 +115,7 @@ sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
115 chan->flags &= ~DMA_TEI_CAPABLE; 115 chan->flags &= ~DMA_TEI_CAPABLE;
116 } 116 }
117 117
118 ctrl_outl(chcr, CHCR[chan->chan]); 118 ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
119 119
120 chan->flags |= DMA_CONFIGURED; 120 chan->flags |= DMA_CONFIGURED;
121 return 0; 121 return 0;
@@ -126,13 +126,13 @@ static void sh_dmac_enable_dma(struct dma_channel *chan)
126 int irq; 126 int irq;
127 u32 chcr; 127 u32 chcr;
128 128
129 chcr = ctrl_inl(CHCR[chan->chan]); 129 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
130 chcr |= CHCR_DE; 130 chcr |= CHCR_DE;
131 131
132 if (chan->flags & DMA_TEI_CAPABLE) 132 if (chan->flags & DMA_TEI_CAPABLE)
133 chcr |= CHCR_IE; 133 chcr |= CHCR_IE;
134 134
135 ctrl_outl(chcr, CHCR[chan->chan]); 135 ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
136 136
137 if (chan->flags & DMA_TEI_CAPABLE) { 137 if (chan->flags & DMA_TEI_CAPABLE) {
138 irq = get_dmte_irq(chan->chan); 138 irq = get_dmte_irq(chan->chan);
@@ -150,9 +150,9 @@ static void sh_dmac_disable_dma(struct dma_channel *chan)
150 disable_irq(irq); 150 disable_irq(irq);
151 } 151 }
152 152
153 chcr = ctrl_inl(CHCR[chan->chan]); 153 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
154 chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE); 154 chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
155 ctrl_outl(chcr, CHCR[chan->chan]); 155 ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
156} 156}
157 157
158static int sh_dmac_xfer_dma(struct dma_channel *chan) 158static int sh_dmac_xfer_dma(struct dma_channel *chan)
@@ -183,12 +183,13 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)
183 */ 183 */
184 if (chan->sar || (mach_is_dreamcast() && 184 if (chan->sar || (mach_is_dreamcast() &&
185 chan->chan == PVR2_CASCADE_CHAN)) 185 chan->chan == PVR2_CASCADE_CHAN))
186 ctrl_outl(chan->sar, SAR[chan->chan]); 186 ctrl_outl(chan->sar, (dma_base_addr[chan->chan]+SAR));
187 if (chan->dar || (mach_is_dreamcast() && 187 if (chan->dar || (mach_is_dreamcast() &&
188 chan->chan == PVR2_CASCADE_CHAN)) 188 chan->chan == PVR2_CASCADE_CHAN))
189 ctrl_outl(chan->dar, DAR[chan->chan]); 189 ctrl_outl(chan->dar, (dma_base_addr[chan->chan] + DAR));
190 190
191 ctrl_outl(chan->count >> calc_xmit_shift(chan), DMATCR[chan->chan]); 191 ctrl_outl(chan->count >> calc_xmit_shift(chan),
192 (dma_base_addr[chan->chan] + TCR));
192 193
193 sh_dmac_enable_dma(chan); 194 sh_dmac_enable_dma(chan);
194 195
@@ -197,36 +198,26 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)
197 198
198static int sh_dmac_get_dma_residue(struct dma_channel *chan) 199static int sh_dmac_get_dma_residue(struct dma_channel *chan)
199{ 200{
200 if (!(ctrl_inl(CHCR[chan->chan]) & CHCR_DE)) 201 if (!(ctrl_inl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE))
201 return 0; 202 return 0;
202 203
203 return ctrl_inl(DMATCR[chan->chan]) << calc_xmit_shift(chan); 204 return ctrl_inl(dma_base_addr[chan->chan] + TCR)
205 << calc_xmit_shift(chan);
204} 206}
205 207
206#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 208static inline int dmaor_reset(int no)
207 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
208 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
209 defined(CONFIG_CPU_SUBTYPE_SH7709)
210#define dmaor_read_reg() ctrl_inw(DMAOR)
211#define dmaor_write_reg(data) ctrl_outw(data, DMAOR)
212#else
213#define dmaor_read_reg() ctrl_inl(DMAOR)
214#define dmaor_write_reg(data) ctrl_outl(data, DMAOR)
215#endif
216
217static inline int dmaor_reset(void)
218{ 209{
219 unsigned long dmaor = dmaor_read_reg(); 210 unsigned long dmaor = dmaor_read_reg(no);
220 211
221 /* Try to clear the error flags first, incase they are set */ 212 /* Try to clear the error flags first, incase they are set */
222 dmaor &= ~(DMAOR_NMIF | DMAOR_AE); 213 dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
223 dmaor_write_reg(dmaor); 214 dmaor_write_reg(no, dmaor);
224 215
225 dmaor |= DMAOR_INIT; 216 dmaor |= DMAOR_INIT;
226 dmaor_write_reg(dmaor); 217 dmaor_write_reg(no, dmaor);
227 218
228 /* See if we got an error again */ 219 /* See if we got an error again */
229 if ((dmaor_read_reg() & (DMAOR_AE | DMAOR_NMIF))) { 220 if ((dmaor_read_reg(no) & (DMAOR_AE | DMAOR_NMIF))) {
230 printk(KERN_ERR "dma-sh: Can't initialize DMAOR.\n"); 221 printk(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
231 return -EINVAL; 222 return -EINVAL;
232 } 223 }
@@ -237,10 +228,33 @@ static inline int dmaor_reset(void)
237#if defined(CONFIG_CPU_SH4) 228#if defined(CONFIG_CPU_SH4)
238static irqreturn_t dma_err(int irq, void *dummy) 229static irqreturn_t dma_err(int irq, void *dummy)
239{ 230{
240 dmaor_reset(); 231#if defined(CONFIG_SH_DMA_IRQ_MULTI)
232 int cnt = 0;
233 switch (irq) {
234#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ)
235 case DMTE6_IRQ:
236 cnt++;
237#endif
238 case DMTE0_IRQ:
239 if (dmaor_read_reg(cnt) & (DMAOR_NMIF | DMAOR_AE)) {
240 disable_irq(irq);
241 /* DMA multi and error IRQ */
242 return IRQ_HANDLED;
243 }
244 default:
245 return IRQ_NONE;
246 }
247#else
248 dmaor_reset(0);
249#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
250 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
251 defined(CONFIG_CPU_SUBTYPE_SH7785)
252 dmaor_reset(1);
253#endif
241 disable_irq(irq); 254 disable_irq(irq);
242 255
243 return IRQ_HANDLED; 256 return IRQ_HANDLED;
257#endif
244} 258}
245#endif 259#endif
246 260
@@ -259,24 +273,59 @@ static struct dma_info sh_dmac_info = {
259 .flags = DMAC_CHANNELS_TEI_CAPABLE, 273 .flags = DMAC_CHANNELS_TEI_CAPABLE,
260}; 274};
261 275
276#ifdef CONFIG_CPU_SH4
277static unsigned int get_dma_error_irq(int n)
278{
279#if defined(CONFIG_SH_DMA_IRQ_MULTI)
280 return (n == 0) ? get_dmte_irq(0) : get_dmte_irq(6);
281#else
282 return (n == 0) ? DMAE0_IRQ :
283#if defined(DMAE1_IRQ)
284 DMAE1_IRQ;
285#else
286 -1;
287#endif
288#endif
289}
290#endif
291
262static int __init sh_dmac_init(void) 292static int __init sh_dmac_init(void)
263{ 293{
264 struct dma_info *info = &sh_dmac_info; 294 struct dma_info *info = &sh_dmac_info;
265 int i; 295 int i;
266 296
267#ifdef CONFIG_CPU_SH4 297#ifdef CONFIG_CPU_SH4
268 i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0); 298 int n;
269 if (unlikely(i < 0)) 299
270 return i; 300 for (n = 0; n < NR_DMAE; n++) {
301 i = request_irq(get_dma_error_irq(n), dma_err,
302#if defined(CONFIG_SH_DMA_IRQ_MULTI)
303 IRQF_SHARED,
304#else
305 IRQF_DISABLED,
271#endif 306#endif
307 dmae_name[n], (void *)dmae_name[n]);
308 if (unlikely(i < 0)) {
309 printk(KERN_ERR "%s request_irq fail\n", dmae_name[n]);
310 return i;
311 }
312 }
313#endif /* CONFIG_CPU_SH4 */
272 314
273 /* 315 /*
274 * Initialize DMAOR, and clean up any error flags that may have 316 * Initialize DMAOR, and clean up any error flags that may have
275 * been set. 317 * been set.
276 */ 318 */
277 i = dmaor_reset(); 319 i = dmaor_reset(0);
320 if (unlikely(i != 0))
321 return i;
322#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
323 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
324 defined(CONFIG_CPU_SUBTYPE_SH7785)
325 i = dmaor_reset(1);
278 if (unlikely(i != 0)) 326 if (unlikely(i != 0))
279 return i; 327 return i;
328#endif
280 329
281 return register_dmac(info); 330 return register_dmac(info);
282} 331}
@@ -284,8 +333,12 @@ static int __init sh_dmac_init(void)
284static void __exit sh_dmac_exit(void) 333static void __exit sh_dmac_exit(void)
285{ 334{
286#ifdef CONFIG_CPU_SH4 335#ifdef CONFIG_CPU_SH4
287 free_irq(DMAE_IRQ, 0); 336 int n;
288#endif 337
338 for (n = 0; n < NR_DMAE; n++) {
339 free_irq(get_dma_error_irq(n), (void *)dmae_name[n]);
340 }
341#endif /* CONFIG_CPU_SH4 */
289 unregister_dmac(&sh_dmac_info); 342 unregister_dmac(&sh_dmac_info);
290} 343}
291 344
diff --git a/arch/sh/drivers/dma/dma-sh.h b/arch/sh/drivers/dma/dma-sh.h
deleted file mode 100644
index 05fecd5428e4..000000000000
--- a/arch/sh/drivers/dma/dma-sh.h
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * arch/sh/drivers/dma/dma-sh.h
3 *
4 * Copyright (C) 2000 Takashi YOSHII
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __DMA_SH_H
12#define __DMA_SH_H
13
14#include <cpu/dma.h>
15
16/* Definitions for the SuperH DMAC */
17#define REQ_L 0x00000000
18#define REQ_E 0x00080000
19#define RACK_H 0x00000000
20#define RACK_L 0x00040000
21#define ACK_R 0x00000000
22#define ACK_W 0x00020000
23#define ACK_H 0x00000000
24#define ACK_L 0x00010000
25#define DM_INC 0x00004000
26#define DM_DEC 0x00008000
27#define SM_INC 0x00001000
28#define SM_DEC 0x00002000
29#define RS_IN 0x00000200
30#define RS_OUT 0x00000300
31#define TS_BLK 0x00000040
32#define TM_BUR 0x00000020
33#define CHCR_DE 0x00000001
34#define CHCR_TE 0x00000002
35#define CHCR_IE 0x00000004
36
37/* DMAOR definitions */
38#define DMAOR_AE 0x00000004
39#define DMAOR_NMIF 0x00000002
40#define DMAOR_DME 0x00000001
41
42/*
43 * Define the default configuration for dual address memory-memory transfer.
44 * The 0x400 value represents auto-request, external->external.
45 */
46#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_32)
47
48#define MAX_DMAC_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
49
50/*
51 * Subtypes that have fewer channels than this simply need to change
52 * CONFIG_NR_ONCHIP_DMA_CHANNELS. Likewise, subtypes with a larger number
53 * of channels should expand on this.
54 *
55 * For most subtypes we can easily figure these values out with some
56 * basic calculation, unfortunately on other subtypes these are more
57 * scattered, so we just leave it unrolled for simplicity.
58 */
59#define SAR ((unsigned long[]){SH_DMAC_BASE + 0x00, SH_DMAC_BASE + 0x10, \
60 SH_DMAC_BASE + 0x20, SH_DMAC_BASE + 0x30, \
61 SH_DMAC_BASE + 0x50, SH_DMAC_BASE + 0x60})
62#define DAR ((unsigned long[]){SH_DMAC_BASE + 0x04, SH_DMAC_BASE + 0x14, \
63 SH_DMAC_BASE + 0x24, SH_DMAC_BASE + 0x34, \
64 SH_DMAC_BASE + 0x54, SH_DMAC_BASE + 0x64})
65#define DMATCR ((unsigned long[]){SH_DMAC_BASE + 0x08, SH_DMAC_BASE + 0x18, \
66 SH_DMAC_BASE + 0x28, SH_DMAC_BASE + 0x38, \
67 SH_DMAC_BASE + 0x58, SH_DMAC_BASE + 0x68})
68#define CHCR ((unsigned long[]){SH_DMAC_BASE + 0x0c, SH_DMAC_BASE + 0x1c, \
69 SH_DMAC_BASE + 0x2c, SH_DMAC_BASE + 0x3c, \
70 SH_DMAC_BASE + 0x5c, SH_DMAC_BASE + 0x6c})
71
72#define DMAOR (SH_DMAC_BASE + 0x40)
73
74#endif /* __DMA_SH_H */
75
diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c
index 078dc44d6b08..773d575a04b9 100644
--- a/arch/sh/drivers/pci/pci-sh7780.c
+++ b/arch/sh/drivers/pci/pci-sh7780.c
@@ -127,8 +127,8 @@ int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
127 pci_write_reg(word, SH4_PCILSR0); 127 pci_write_reg(word, SH4_PCILSR0);
128 pci_write_reg(0x00000001, SH4_PCILSR1); 128 pci_write_reg(0x00000001, SH4_PCILSR1);
129 /* Set the values on window 0 PCI config registers */ 129 /* Set the values on window 0 PCI config registers */
130 word = (CONFIG_MEMORY_SIZE > 0x08000000) ? 0x10000000 : 0x08000000; 130 word = CONFIG_MEMORY_START | (CONFIG_MEMORY_SIZE - 0x01000000);
131 pci_write_reg(word | 0xa0000000, SH4_PCILAR0); 131 pci_write_reg(word, SH4_PCILAR0);
132 pci_write_reg(word, SH7780_PCIMBAR0); 132 pci_write_reg(word, SH7780_PCIMBAR0);
133 /* Set the values on window 1 PCI config registers */ 133 /* Set the values on window 1 PCI config registers */
134 pci_write_reg(0x00000000, SH4_PCILAR1); 134 pci_write_reg(0x00000000, SH4_PCILAR1);
diff --git a/arch/sh/include/asm/addrspace.h b/arch/sh/include/asm/addrspace.h
index 36736c7e93db..80d40813e057 100644
--- a/arch/sh/include/asm/addrspace.h
+++ b/arch/sh/include/asm/addrspace.h
@@ -31,7 +31,7 @@
31/* Returns the physical address of a PnSEG (n=1,2) address */ 31/* Returns the physical address of a PnSEG (n=1,2) address */
32#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) 32#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
33 33
34#ifdef CONFIG_29BIT 34#if defined(CONFIG_29BIT) || defined(CONFIG_PMB_FIXED)
35/* 35/*
36 * Map an address to a certain privileged segment 36 * Map an address to a certain privileged segment
37 */ 37 */
@@ -43,7 +43,7 @@
43 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG)) 43 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
44#define P4SEGADDR(a) \ 44#define P4SEGADDR(a) \
45 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG)) 45 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
46#endif /* 29BIT */ 46#endif /* 29BIT || PMB_FIXED */
47#endif /* P1SEG */ 47#endif /* P1SEG */
48 48
49/* Check if an address can be reached in 29 bits */ 49/* Check if an address can be reached in 29 bits */
diff --git a/arch/sh/include/asm/atomic-irq.h b/arch/sh/include/asm/atomic-irq.h
index 74f7943cff6f..a0b348068cae 100644
--- a/arch/sh/include/asm/atomic-irq.h
+++ b/arch/sh/include/asm/atomic-irq.h
@@ -11,7 +11,7 @@ static inline void atomic_add(int i, atomic_t *v)
11 unsigned long flags; 11 unsigned long flags;
12 12
13 local_irq_save(flags); 13 local_irq_save(flags);
14 *(long *)v += i; 14 v->counter += i;
15 local_irq_restore(flags); 15 local_irq_restore(flags);
16} 16}
17 17
@@ -20,7 +20,7 @@ static inline void atomic_sub(int i, atomic_t *v)
20 unsigned long flags; 20 unsigned long flags;
21 21
22 local_irq_save(flags); 22 local_irq_save(flags);
23 *(long *)v -= i; 23 v->counter -= i;
24 local_irq_restore(flags); 24 local_irq_restore(flags);
25} 25}
26 26
@@ -29,9 +29,9 @@ static inline int atomic_add_return(int i, atomic_t *v)
29 unsigned long temp, flags; 29 unsigned long temp, flags;
30 30
31 local_irq_save(flags); 31 local_irq_save(flags);
32 temp = *(long *)v; 32 temp = v->counter;
33 temp += i; 33 temp += i;
34 *(long *)v = temp; 34 v->counter = temp;
35 local_irq_restore(flags); 35 local_irq_restore(flags);
36 36
37 return temp; 37 return temp;
@@ -42,9 +42,9 @@ static inline int atomic_sub_return(int i, atomic_t *v)
42 unsigned long temp, flags; 42 unsigned long temp, flags;
43 43
44 local_irq_save(flags); 44 local_irq_save(flags);
45 temp = *(long *)v; 45 temp = v->counter;
46 temp -= i; 46 temp -= i;
47 *(long *)v = temp; 47 v->counter = temp;
48 local_irq_restore(flags); 48 local_irq_restore(flags);
49 49
50 return temp; 50 return temp;
@@ -55,7 +55,7 @@ static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
55 unsigned long flags; 55 unsigned long flags;
56 56
57 local_irq_save(flags); 57 local_irq_save(flags);
58 *(long *)v &= ~mask; 58 v->counter &= ~mask;
59 local_irq_restore(flags); 59 local_irq_restore(flags);
60} 60}
61 61
@@ -64,7 +64,7 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
64 unsigned long flags; 64 unsigned long flags;
65 65
66 local_irq_save(flags); 66 local_irq_save(flags);
67 *(long *)v |= mask; 67 v->counter |= mask;
68 local_irq_restore(flags); 68 local_irq_restore(flags);
69} 69}
70 70
diff --git a/arch/sh/include/asm/bitops-llsc.h b/arch/sh/include/asm/bitops-llsc.h
index 1d2fc0b010ad..d8328be06191 100644
--- a/arch/sh/include/asm/bitops-llsc.h
+++ b/arch/sh/include/asm/bitops-llsc.h
@@ -1,7 +1,7 @@
1#ifndef __ASM_SH_BITOPS_LLSC_H 1#ifndef __ASM_SH_BITOPS_LLSC_H
2#define __ASM_SH_BITOPS_LLSC_H 2#define __ASM_SH_BITOPS_LLSC_H
3 3
4static inline void set_bit(int nr, volatile void * addr) 4static inline void set_bit(int nr, volatile void *addr)
5{ 5{
6 int mask; 6 int mask;
7 volatile unsigned int *a = addr; 7 volatile unsigned int *a = addr;
@@ -13,16 +13,16 @@ static inline void set_bit(int nr, volatile void * addr)
13 __asm__ __volatile__ ( 13 __asm__ __volatile__ (
14 "1: \n\t" 14 "1: \n\t"
15 "movli.l @%1, %0 ! set_bit \n\t" 15 "movli.l @%1, %0 ! set_bit \n\t"
16 "or %3, %0 \n\t" 16 "or %2, %0 \n\t"
17 "movco.l %0, @%1 \n\t" 17 "movco.l %0, @%1 \n\t"
18 "bf 1b \n\t" 18 "bf 1b \n\t"
19 : "=&z" (tmp), "=r" (a) 19 : "=&z" (tmp)
20 : "1" (a), "r" (mask) 20 : "r" (a), "r" (mask)
21 : "t", "memory" 21 : "t", "memory"
22 ); 22 );
23} 23}
24 24
25static inline void clear_bit(int nr, volatile void * addr) 25static inline void clear_bit(int nr, volatile void *addr)
26{ 26{
27 int mask; 27 int mask;
28 volatile unsigned int *a = addr; 28 volatile unsigned int *a = addr;
@@ -34,16 +34,16 @@ static inline void clear_bit(int nr, volatile void * addr)
34 __asm__ __volatile__ ( 34 __asm__ __volatile__ (
35 "1: \n\t" 35 "1: \n\t"
36 "movli.l @%1, %0 ! clear_bit \n\t" 36 "movli.l @%1, %0 ! clear_bit \n\t"
37 "and %3, %0 \n\t" 37 "and %2, %0 \n\t"
38 "movco.l %0, @%1 \n\t" 38 "movco.l %0, @%1 \n\t"
39 "bf 1b \n\t" 39 "bf 1b \n\t"
40 : "=&z" (tmp), "=r" (a) 40 : "=&z" (tmp)
41 : "1" (a), "r" (~mask) 41 : "r" (a), "r" (~mask)
42 : "t", "memory" 42 : "t", "memory"
43 ); 43 );
44} 44}
45 45
46static inline void change_bit(int nr, volatile void * addr) 46static inline void change_bit(int nr, volatile void *addr)
47{ 47{
48 int mask; 48 int mask;
49 volatile unsigned int *a = addr; 49 volatile unsigned int *a = addr;
@@ -55,16 +55,16 @@ static inline void change_bit(int nr, volatile void * addr)
55 __asm__ __volatile__ ( 55 __asm__ __volatile__ (
56 "1: \n\t" 56 "1: \n\t"
57 "movli.l @%1, %0 ! change_bit \n\t" 57 "movli.l @%1, %0 ! change_bit \n\t"
58 "xor %3, %0 \n\t" 58 "xor %2, %0 \n\t"
59 "movco.l %0, @%1 \n\t" 59 "movco.l %0, @%1 \n\t"
60 "bf 1b \n\t" 60 "bf 1b \n\t"
61 : "=&z" (tmp), "=r" (a) 61 : "=&z" (tmp)
62 : "1" (a), "r" (mask) 62 : "r" (a), "r" (mask)
63 : "t", "memory" 63 : "t", "memory"
64 ); 64 );
65} 65}
66 66
67static inline int test_and_set_bit(int nr, volatile void * addr) 67static inline int test_and_set_bit(int nr, volatile void *addr)
68{ 68{
69 int mask, retval; 69 int mask, retval;
70 volatile unsigned int *a = addr; 70 volatile unsigned int *a = addr;
@@ -75,21 +75,21 @@ static inline int test_and_set_bit(int nr, volatile void * addr)
75 75
76 __asm__ __volatile__ ( 76 __asm__ __volatile__ (
77 "1: \n\t" 77 "1: \n\t"
78 "movli.l @%1, %0 ! test_and_set_bit \n\t" 78 "movli.l @%2, %0 ! test_and_set_bit \n\t"
79 "mov %0, %2 \n\t" 79 "mov %0, %1 \n\t"
80 "or %4, %0 \n\t" 80 "or %3, %0 \n\t"
81 "movco.l %0, @%1 \n\t" 81 "movco.l %0, @%2 \n\t"
82 "bf 1b \n\t" 82 "bf 1b \n\t"
83 "and %4, %2 \n\t" 83 "and %3, %1 \n\t"
84 : "=&z" (tmp), "=r" (a), "=&r" (retval) 84 : "=&z" (tmp), "=&r" (retval)
85 : "1" (a), "r" (mask) 85 : "r" (a), "r" (mask)
86 : "t", "memory" 86 : "t", "memory"
87 ); 87 );
88 88
89 return retval != 0; 89 return retval != 0;
90} 90}
91 91
92static inline int test_and_clear_bit(int nr, volatile void * addr) 92static inline int test_and_clear_bit(int nr, volatile void *addr)
93{ 93{
94 int mask, retval; 94 int mask, retval;
95 volatile unsigned int *a = addr; 95 volatile unsigned int *a = addr;
@@ -100,22 +100,22 @@ static inline int test_and_clear_bit(int nr, volatile void * addr)
100 100
101 __asm__ __volatile__ ( 101 __asm__ __volatile__ (
102 "1: \n\t" 102 "1: \n\t"
103 "movli.l @%1, %0 ! test_and_clear_bit \n\t" 103 "movli.l @%2, %0 ! test_and_clear_bit \n\t"
104 "mov %0, %2 \n\t" 104 "mov %0, %1 \n\t"
105 "and %5, %0 \n\t" 105 "and %4, %0 \n\t"
106 "movco.l %0, @%1 \n\t" 106 "movco.l %0, @%2 \n\t"
107 "bf 1b \n\t" 107 "bf 1b \n\t"
108 "and %4, %2 \n\t" 108 "and %3, %1 \n\t"
109 "synco \n\t" 109 "synco \n\t"
110 : "=&z" (tmp), "=r" (a), "=&r" (retval) 110 : "=&z" (tmp), "=&r" (retval)
111 : "1" (a), "r" (mask), "r" (~mask) 111 : "r" (a), "r" (mask), "r" (~mask)
112 : "t", "memory" 112 : "t", "memory"
113 ); 113 );
114 114
115 return retval != 0; 115 return retval != 0;
116} 116}
117 117
118static inline int test_and_change_bit(int nr, volatile void * addr) 118static inline int test_and_change_bit(int nr, volatile void *addr)
119{ 119{
120 int mask, retval; 120 int mask, retval;
121 volatile unsigned int *a = addr; 121 volatile unsigned int *a = addr;
@@ -126,15 +126,15 @@ static inline int test_and_change_bit(int nr, volatile void * addr)
126 126
127 __asm__ __volatile__ ( 127 __asm__ __volatile__ (
128 "1: \n\t" 128 "1: \n\t"
129 "movli.l @%1, %0 ! test_and_change_bit \n\t" 129 "movli.l @%2, %0 ! test_and_change_bit \n\t"
130 "mov %0, %2 \n\t" 130 "mov %0, %1 \n\t"
131 "xor %4, %0 \n\t" 131 "xor %3, %0 \n\t"
132 "movco.l %0, @%1 \n\t" 132 "movco.l %0, @%2 \n\t"
133 "bf 1b \n\t" 133 "bf 1b \n\t"
134 "and %4, %2 \n\t" 134 "and %3, %1 \n\t"
135 "synco \n\t" 135 "synco \n\t"
136 : "=&z" (tmp), "=r" (a), "=&r" (retval) 136 : "=&z" (tmp), "=&r" (retval)
137 : "1" (a), "r" (mask) 137 : "r" (a), "r" (mask)
138 : "t", "memory" 138 : "t", "memory"
139 ); 139 );
140 140
diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h
index f9c88583d90a..2f6c9627bc1f 100644
--- a/arch/sh/include/asm/clock.h
+++ b/arch/sh/include/asm/clock.h
@@ -15,6 +15,7 @@ struct clk_ops {
15 void (*disable)(struct clk *clk); 15 void (*disable)(struct clk *clk);
16 void (*recalc)(struct clk *clk); 16 void (*recalc)(struct clk *clk);
17 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id); 17 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
18 int (*set_parent)(struct clk *clk, struct clk *parent);
18 long (*round_rate)(struct clk *clk, unsigned long rate); 19 long (*round_rate)(struct clk *clk, unsigned long rate);
19}; 20};
20 21
diff --git a/arch/sh/include/asm/cmpxchg-llsc.h b/arch/sh/include/asm/cmpxchg-llsc.h
index aee3bf286581..0fac3da536ca 100644
--- a/arch/sh/include/asm/cmpxchg-llsc.h
+++ b/arch/sh/include/asm/cmpxchg-llsc.h
@@ -8,14 +8,14 @@ static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
8 8
9 __asm__ __volatile__ ( 9 __asm__ __volatile__ (
10 "1: \n\t" 10 "1: \n\t"
11 "movli.l @%1, %0 ! xchg_u32 \n\t" 11 "movli.l @%2, %0 ! xchg_u32 \n\t"
12 "mov %0, %2 \n\t" 12 "mov %0, %1 \n\t"
13 "mov %4, %0 \n\t" 13 "mov %3, %0 \n\t"
14 "movco.l %0, @%1 \n\t" 14 "movco.l %0, @%2 \n\t"
15 "bf 1b \n\t" 15 "bf 1b \n\t"
16 "synco \n\t" 16 "synco \n\t"
17 : "=&z"(tmp), "=r" (m), "=&r" (retval) 17 : "=&z"(tmp), "=&r" (retval)
18 : "1" (m), "r" (val) 18 : "r" (m), "r" (val)
19 : "t", "memory" 19 : "t", "memory"
20 ); 20 );
21 21
@@ -29,14 +29,14 @@ static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
29 29
30 __asm__ __volatile__ ( 30 __asm__ __volatile__ (
31 "1: \n\t" 31 "1: \n\t"
32 "movli.l @%1, %0 ! xchg_u8 \n\t" 32 "movli.l @%2, %0 ! xchg_u8 \n\t"
33 "mov %0, %2 \n\t" 33 "mov %0, %1 \n\t"
34 "mov %4, %0 \n\t" 34 "mov %3, %0 \n\t"
35 "movco.l %0, @%1 \n\t" 35 "movco.l %0, @%2 \n\t"
36 "bf 1b \n\t" 36 "bf 1b \n\t"
37 "synco \n\t" 37 "synco \n\t"
38 : "=&z"(tmp), "=r" (m), "=&r" (retval) 38 : "=&z"(tmp), "=&r" (retval)
39 : "1" (m), "r" (val & 0xff) 39 : "r" (m), "r" (val & 0xff)
40 : "t", "memory" 40 : "t", "memory"
41 ); 41 );
42 42
@@ -51,17 +51,17 @@ __cmpxchg_u32(volatile int *m, unsigned long old, unsigned long new)
51 51
52 __asm__ __volatile__ ( 52 __asm__ __volatile__ (
53 "1: \n\t" 53 "1: \n\t"
54 "movli.l @%1, %0 ! __cmpxchg_u32 \n\t" 54 "movli.l @%2, %0 ! __cmpxchg_u32 \n\t"
55 "mov %0, %2 \n\t" 55 "mov %0, %1 \n\t"
56 "cmp/eq %2, %4 \n\t" 56 "cmp/eq %1, %3 \n\t"
57 "bf 2f \n\t" 57 "bf 2f \n\t"
58 "mov %5, %0 \n\t" 58 "mov %3, %0 \n\t"
59 "2: \n\t" 59 "2: \n\t"
60 "movco.l %0, @%1 \n\t" 60 "movco.l %0, @%2 \n\t"
61 "bf 1b \n\t" 61 "bf 1b \n\t"
62 "synco \n\t" 62 "synco \n\t"
63 : "=&z" (tmp), "=r" (m), "=&r" (retval) 63 : "=&z" (tmp), "=&r" (retval)
64 : "1" (m), "r" (old), "r" (new) 64 : "r" (m), "r" (old), "r" (new)
65 : "t", "memory" 65 : "t", "memory"
66 ); 66 );
67 67
diff --git a/arch/sh/include/asm/cpu-features.h b/arch/sh/include/asm/cpu-features.h
index 86308aa39731..694abe490edb 100644
--- a/arch/sh/include/asm/cpu-features.h
+++ b/arch/sh/include/asm/cpu-features.h
@@ -21,5 +21,6 @@
21#define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */ 21#define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */
22#define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */ 22#define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */
23#define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */ 23#define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */
24#define CPU_HAS_PTEAEX 0x0200 /* PTE ASID Extension support */
24 25
25#endif /* __ASM_SH_CPU_FEATURES_H */ 26#endif /* __ASM_SH_CPU_FEATURES_H */
diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h
new file mode 100644
index 000000000000..0c8f8e14622a
--- /dev/null
+++ b/arch/sh/include/asm/dma-sh.h
@@ -0,0 +1,118 @@
1/*
2 * arch/sh/include/asm/dma-sh.h
3 *
4 * Copyright (C) 2000 Takashi YOSHII
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __DMA_SH_H
12#define __DMA_SH_H
13
14#include <asm/dma.h>
15#include <cpu/dma.h>
16
17/* DMAOR contorl: The DMAOR access size is different by CPU.*/
18#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
19 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
20 defined(CONFIG_CPU_SUBTYPE_SH7785)
21#define dmaor_read_reg(n) \
22 (n ? ctrl_inw(SH_DMAC_BASE1 + DMAOR) \
23 : ctrl_inw(SH_DMAC_BASE0 + DMAOR))
24#define dmaor_write_reg(n, data) \
25 (n ? ctrl_outw(data, SH_DMAC_BASE1 + DMAOR) \
26 : ctrl_outw(data, SH_DMAC_BASE0 + DMAOR))
27#else /* Other CPU */
28#define dmaor_read_reg(n) ctrl_inw(SH_DMAC_BASE0 + DMAOR)
29#define dmaor_write_reg(n, data) ctrl_outw(data, SH_DMAC_BASE0 + DMAOR)
30#endif
31
32static int dmte_irq_map[] __maybe_unused = {
33#if (MAX_DMA_CHANNELS >= 4)
34 DMTE0_IRQ,
35 DMTE0_IRQ + 1,
36 DMTE0_IRQ + 2,
37 DMTE0_IRQ + 3,
38#endif
39#if (MAX_DMA_CHANNELS >= 6)
40 DMTE4_IRQ,
41 DMTE4_IRQ + 1,
42#endif
43#if (MAX_DMA_CHANNELS >= 8)
44 DMTE6_IRQ,
45 DMTE6_IRQ + 1,
46#endif
47#if (MAX_DMA_CHANNELS >= 12)
48 DMTE8_IRQ,
49 DMTE9_IRQ,
50 DMTE10_IRQ,
51 DMTE11_IRQ,
52#endif
53};
54
55/* Definitions for the SuperH DMAC */
56#define REQ_L 0x00000000
57#define REQ_E 0x00080000
58#define RACK_H 0x00000000
59#define RACK_L 0x00040000
60#define ACK_R 0x00000000
61#define ACK_W 0x00020000
62#define ACK_H 0x00000000
63#define ACK_L 0x00010000
64#define DM_INC 0x00004000
65#define DM_DEC 0x00008000
66#define SM_INC 0x00001000
67#define SM_DEC 0x00002000
68#define RS_IN 0x00000200
69#define RS_OUT 0x00000300
70#define TS_BLK 0x00000040
71#define TM_BUR 0x00000020
72#define CHCR_DE 0x00000001
73#define CHCR_TE 0x00000002
74#define CHCR_IE 0x00000004
75
76/* DMAOR definitions */
77#define DMAOR_AE 0x00000004
78#define DMAOR_NMIF 0x00000002
79#define DMAOR_DME 0x00000001
80
81/*
82 * Define the default configuration for dual address memory-memory transfer.
83 * The 0x400 value represents auto-request, external->external.
84 */
85#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_32)
86
87/* DMA base address */
88static u32 dma_base_addr[] __maybe_unused = {
89#if (MAX_DMA_CHANNELS >= 4)
90 SH_DMAC_BASE0 + 0x00, /* channel 0 */
91 SH_DMAC_BASE0 + 0x10,
92 SH_DMAC_BASE0 + 0x20,
93 SH_DMAC_BASE0 + 0x30,
94#endif
95#if (MAX_DMA_CHANNELS >= 6)
96 SH_DMAC_BASE0 + 0x50,
97 SH_DMAC_BASE0 + 0x60,
98#endif
99#if (MAX_DMA_CHANNELS >= 8)
100 SH_DMAC_BASE1 + 0x00,
101 SH_DMAC_BASE1 + 0x10,
102#endif
103#if (MAX_DMA_CHANNELS >= 12)
104 SH_DMAC_BASE1 + 0x20,
105 SH_DMAC_BASE1 + 0x30,
106 SH_DMAC_BASE1 + 0x50,
107 SH_DMAC_BASE1 + 0x60, /* channel 11 */
108#endif
109};
110
111/* DMA register */
112#define SAR 0x00
113#define DAR 0x04
114#define TCR 0x08
115#define CHCR 0x0C
116#define DMAOR 0x40
117
118#endif /* __DMA_SH_H */
diff --git a/arch/sh/include/asm/dma.h b/arch/sh/include/asm/dma.h
index beca7128e2ab..6bd178473878 100644
--- a/arch/sh/include/asm/dma.h
+++ b/arch/sh/include/asm/dma.h
@@ -25,9 +25,9 @@
25#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000) 25#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
26 26
27#ifdef CONFIG_NR_DMA_CHANNELS 27#ifdef CONFIG_NR_DMA_CHANNELS
28# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS) 28# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS)
29#else 29#else
30# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS) 30# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
31#endif 31#endif
32 32
33/* 33/*
diff --git a/arch/sh/include/asm/entry-macros.S b/arch/sh/include/asm/entry-macros.S
index 2dab0b8d9454..3a4752a65722 100644
--- a/arch/sh/include/asm/entry-macros.S
+++ b/arch/sh/include/asm/entry-macros.S
@@ -31,3 +31,8 @@
31#endif 31#endif
32 .endm 32 .endm
33 33
34#if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4)
35# define PREF(x) pref @x
36#else
37# define PREF(x) nop
38#endif
diff --git a/arch/sh/include/asm/gpio.h b/arch/sh/include/asm/gpio.h
index 90673658eb14..61f93da2c62e 100644
--- a/arch/sh/include/asm/gpio.h
+++ b/arch/sh/include/asm/gpio.h
@@ -19,8 +19,42 @@
19#include <cpu/gpio.h> 19#include <cpu/gpio.h>
20#endif 20#endif
21 21
22#define ARCH_NR_GPIOS 512
23#include <asm-generic/gpio.h>
24
25#ifdef CONFIG_GPIOLIB
26
27static inline int gpio_get_value(unsigned gpio)
28{
29 return __gpio_get_value(gpio);
30}
31
32static inline void gpio_set_value(unsigned gpio, int value)
33{
34 __gpio_set_value(gpio, value);
35}
36
37static inline int gpio_cansleep(unsigned gpio)
38{
39 return __gpio_cansleep(gpio);
40}
41
42static inline int gpio_to_irq(unsigned gpio)
43{
44 WARN_ON(1);
45 return -ENOSYS;
46}
47
48static inline int irq_to_gpio(unsigned int irq)
49{
50 WARN_ON(1);
51 return -EINVAL;
52}
53
54#endif /* CONFIG_GPIOLIB */
55
22typedef unsigned short pinmux_enum_t; 56typedef unsigned short pinmux_enum_t;
23typedef unsigned char pinmux_flag_t; 57typedef unsigned short pinmux_flag_t;
24 58
25#define PINMUX_TYPE_NONE 0 59#define PINMUX_TYPE_NONE 0
26#define PINMUX_TYPE_FUNCTION 1 60#define PINMUX_TYPE_FUNCTION 1
@@ -34,6 +68,11 @@ typedef unsigned char pinmux_flag_t;
34#define PINMUX_FLAG_WANT_PULLUP (1 << 3) 68#define PINMUX_FLAG_WANT_PULLUP (1 << 3)
35#define PINMUX_FLAG_WANT_PULLDOWN (1 << 4) 69#define PINMUX_FLAG_WANT_PULLDOWN (1 << 4)
36 70
71#define PINMUX_FLAG_DBIT_SHIFT 5
72#define PINMUX_FLAG_DBIT (0x1f << PINMUX_FLAG_DBIT_SHIFT)
73#define PINMUX_FLAG_DREG_SHIFT 10
74#define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT)
75
37struct pinmux_gpio { 76struct pinmux_gpio {
38 pinmux_enum_t enum_id; 77 pinmux_enum_t enum_id;
39 pinmux_flag_t flags; 78 pinmux_flag_t flags;
@@ -54,7 +93,7 @@ struct pinmux_cfg_reg {
54 .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) \ 93 .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) \
55 94
56struct pinmux_data_reg { 95struct pinmux_data_reg {
57 unsigned long reg, reg_width; 96 unsigned long reg, reg_width, reg_shadow;
58 pinmux_enum_t *enum_ids; 97 pinmux_enum_t *enum_ids;
59}; 98};
60 99
@@ -89,34 +128,9 @@ struct pinmux_info {
89 unsigned int gpio_data_size; 128 unsigned int gpio_data_size;
90 129
91 unsigned long *gpio_in_use; 130 unsigned long *gpio_in_use;
131 struct gpio_chip chip;
92}; 132};
93 133
94int register_pinmux(struct pinmux_info *pip); 134int register_pinmux(struct pinmux_info *pip);
95 135
96int __gpio_request(unsigned gpio);
97static inline int gpio_request(unsigned gpio, const char *label)
98{
99 return __gpio_request(gpio);
100}
101void gpio_free(unsigned gpio);
102int gpio_direction_input(unsigned gpio);
103int gpio_direction_output(unsigned gpio, int value);
104int gpio_get_value(unsigned gpio);
105void gpio_set_value(unsigned gpio, int value);
106
107/* IRQ modes are unspported */
108static inline int gpio_to_irq(unsigned gpio)
109{
110 WARN_ON(1);
111 return -EINVAL;
112}
113
114static inline int irq_to_gpio(unsigned irq)
115{
116 WARN_ON(1);
117 return -EINVAL;
118}
119
120#include <asm-generic/gpio.h>
121
122#endif /* __ASM_SH_GPIO_H */ 136#endif /* __ASM_SH_GPIO_H */
diff --git a/arch/sh/include/asm/hd64461.h b/arch/sh/include/asm/hd64461.h
index 8c1353baf00f..52b4b6238277 100644
--- a/arch/sh/include/asm/hd64461.h
+++ b/arch/sh/include/asm/hd64461.h
@@ -242,7 +242,6 @@
242#include <asm/io_generic.h> 242#include <asm/io_generic.h>
243 243
244/* arch/sh/cchips/hd6446x/hd64461/setup.c */ 244/* arch/sh/cchips/hd6446x/hd64461/setup.c */
245int hd64461_irq_demux(int irq);
246void hd64461_register_irq_demux(int irq, 245void hd64461_register_irq_demux(int irq,
247 int (*demux) (int irq, void *dev), void *dev); 246 int (*demux) (int irq, void *dev), void *dev);
248void hd64461_unregister_irq_demux(int irq); 247void hd64461_unregister_irq_demux(int irq);
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 61f6dae40534..0454f8d68059 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -238,7 +238,7 @@ extern void onchip_unmap(unsigned long vaddr);
238static inline void __iomem * 238static inline void __iomem *
239__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags) 239__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
240{ 240{
241#ifdef CONFIG_SUPERH32 241#if defined(CONFIG_SUPERH32) && !defined(CONFIG_PMB_FIXED)
242 unsigned long last_addr = offset + size - 1; 242 unsigned long last_addr = offset + size - 1;
243#endif 243#endif
244 void __iomem *ret; 244 void __iomem *ret;
@@ -247,7 +247,7 @@ __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
247 if (ret) 247 if (ret)
248 return ret; 248 return ret;
249 249
250#ifdef CONFIG_SUPERH32 250#if defined(CONFIG_SUPERH32) && !defined(CONFIG_PMB_FIXED)
251 /* 251 /*
252 * For P1 and P2 space this is trivial, as everything is already 252 * For P1 and P2 space this is trivial, as everything is already
253 * mapped. Uncached access for P1 addresses are done through P2. 253 * mapped. Uncached access for P1 addresses are done through P2.
diff --git a/arch/sh/include/asm/kprobes.h b/arch/sh/include/asm/kprobes.h
index 6078d8e551d4..613644a758e8 100644
--- a/arch/sh/include/asm/kprobes.h
+++ b/arch/sh/include/asm/kprobes.h
@@ -16,7 +16,7 @@ typedef u16 kprobe_opcode_t;
16 ? (MAX_STACK_SIZE) \ 16 ? (MAX_STACK_SIZE) \
17 : (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR))) 17 : (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR)))
18 18
19#define regs_return_value(regs) ((regs)->regs[0]) 19#define regs_return_value(_regs) ((_regs)->regs[0])
20#define flush_insn_slot(p) do { } while (0) 20#define flush_insn_slot(p) do { } while (0)
21#define kretprobe_blacklist_size 0 21#define kretprobe_blacklist_size 0
22 22
diff --git a/arch/sh/include/asm/mmu_context.h b/arch/sh/include/asm/mmu_context.h
index 5d9157bd474d..2a9c55f1a83f 100644
--- a/arch/sh/include/asm/mmu_context.h
+++ b/arch/sh/include/asm/mmu_context.h
@@ -19,13 +19,18 @@
19 * (a) TLB cache version (or round, cycle whatever expression you like) 19 * (a) TLB cache version (or round, cycle whatever expression you like)
20 * (b) ASID (Address Space IDentifier) 20 * (b) ASID (Address Space IDentifier)
21 */ 21 */
22#ifdef CONFIG_CPU_HAS_PTEAEX
23#define MMU_CONTEXT_ASID_MASK 0x0000ffff
24#else
22#define MMU_CONTEXT_ASID_MASK 0x000000ff 25#define MMU_CONTEXT_ASID_MASK 0x000000ff
23#define MMU_CONTEXT_VERSION_MASK 0xffffff00 26#endif
24#define MMU_CONTEXT_FIRST_VERSION 0x00000100
25#define NO_CONTEXT 0UL
26 27
27/* ASID is 8-bit value, so it can't be 0x100 */ 28#define MMU_CONTEXT_VERSION_MASK (~0UL & ~MMU_CONTEXT_ASID_MASK)
28#define MMU_NO_ASID 0x100 29#define MMU_CONTEXT_FIRST_VERSION (MMU_CONTEXT_ASID_MASK + 1)
30
31/* Impossible ASID value, to differentiate from NO_CONTEXT. */
32#define MMU_NO_ASID MMU_CONTEXT_FIRST_VERSION
33#define NO_CONTEXT 0UL
29 34
30#define asid_cache(cpu) (cpu_data[cpu].asid_cache) 35#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
31 36
diff --git a/arch/sh/include/asm/mmu_context_32.h b/arch/sh/include/asm/mmu_context_32.h
index f4f9aebd68b7..8ef800c549ab 100644
--- a/arch/sh/include/asm/mmu_context_32.h
+++ b/arch/sh/include/asm/mmu_context_32.h
@@ -10,6 +10,17 @@ static inline void destroy_context(struct mm_struct *mm)
10 /* Do nothing */ 10 /* Do nothing */
11} 11}
12 12
13#ifdef CONFIG_CPU_HAS_PTEAEX
14static inline void set_asid(unsigned long asid)
15{
16 __raw_writel(asid, MMU_PTEAEX);
17}
18
19static inline unsigned long get_asid(void)
20{
21 return __raw_readl(MMU_PTEAEX) & MMU_CONTEXT_ASID_MASK;
22}
23#else
13static inline void set_asid(unsigned long asid) 24static inline void set_asid(unsigned long asid)
14{ 25{
15 unsigned long __dummy; 26 unsigned long __dummy;
@@ -33,6 +44,7 @@ static inline unsigned long get_asid(void)
33 asid &= MMU_CONTEXT_ASID_MASK; 44 asid &= MMU_CONTEXT_ASID_MASK;
34 return asid; 45 return asid;
35} 46}
47#endif /* CONFIG_CPU_HAS_PTEAEX */
36 48
37/* MMU_TTB is used for optimizing the fault handling. */ 49/* MMU_TTB is used for optimizing the fault handling. */
38static inline void set_TTB(pgd_t *pgd) 50static inline void set_TTB(pgd_t *pgd)
diff --git a/arch/sh/include/asm/page.h b/arch/sh/include/asm/page.h
index 5871d78e47e5..9c6d21ec0240 100644
--- a/arch/sh/include/asm/page.h
+++ b/arch/sh/include/asm/page.h
@@ -129,7 +129,12 @@ typedef struct page *pgtable_t;
129 * is not visible (it is part of the PMB mapping) and so needs to be 129 * is not visible (it is part of the PMB mapping) and so needs to be
130 * added or subtracted as required. 130 * added or subtracted as required.
131 */ 131 */
132#ifdef CONFIG_32BIT 132#if defined(CONFIG_PMB_FIXED)
133/* phys = virt - PAGE_OFFSET - (__MEMORY_START & 0xe0000000) */
134#define PMB_OFFSET (PAGE_OFFSET - PXSEG(__MEMORY_START))
135#define __pa(x) ((unsigned long)(x) - PMB_OFFSET)
136#define __va(x) ((void *)((unsigned long)(x) + PMB_OFFSET))
137#elif defined(CONFIG_32BIT)
133#define __pa(x) ((unsigned long)(x)-PAGE_OFFSET+__MEMORY_START) 138#define __pa(x) ((unsigned long)(x)-PAGE_OFFSET+__MEMORY_START)
134#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET-__MEMORY_START)) 139#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET-__MEMORY_START))
135#else 140#else
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index 1ef4b24d7619..1fd58b421438 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -31,7 +31,7 @@ enum cpu_type {
31 CPU_SH7760, CPU_SH4_202, CPU_SH4_501, 31 CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
32 32
33 /* SH-4A types */ 33 /* SH-4A types */
34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, 34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
35 CPU_SH7723, CPU_SHX3, 35 CPU_SH7723, CPU_SHX3,
36 36
37 /* SH4AL-DSP types */ 37 /* SH4AL-DSP types */
diff --git a/arch/sh/include/asm/processor_32.h b/arch/sh/include/asm/processor_32.h
index d79063c5eb9c..efdd78a53b11 100644
--- a/arch/sh/include/asm/processor_32.h
+++ b/arch/sh/include/asm/processor_32.h
@@ -108,12 +108,12 @@ extern int ubc_usercnt;
108/* 108/*
109 * Do necessary setup to start up a newly executed thread. 109 * Do necessary setup to start up a newly executed thread.
110 */ 110 */
111#define start_thread(regs, new_pc, new_sp) \ 111#define start_thread(_regs, new_pc, new_sp) \
112 set_fs(USER_DS); \ 112 set_fs(USER_DS); \
113 regs->pr = 0; \ 113 _regs->pr = 0; \
114 regs->sr = SR_FD; /* User mode. */ \ 114 _regs->sr = SR_FD; /* User mode. */ \
115 regs->pc = new_pc; \ 115 _regs->pc = new_pc; \
116 regs->regs[15] = new_sp 116 _regs->regs[15] = new_sp
117 117
118/* Forward declaration, a strange C thing */ 118/* Forward declaration, a strange C thing */
119struct task_struct; 119struct task_struct;
@@ -189,10 +189,9 @@ extern unsigned long get_wchan(struct task_struct *p);
189#define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc) 189#define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc)
190#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[15]) 190#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[15])
191 191
192#define user_stack_pointer(regs) ((regs)->regs[15]) 192#define user_stack_pointer(_regs) ((_regs)->regs[15])
193 193
194#if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH3) || \ 194#if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4)
195 defined(CONFIG_CPU_SH4)
196#define PREFETCH_STRIDE L1_CACHE_BYTES 195#define PREFETCH_STRIDE L1_CACHE_BYTES
197#define ARCH_HAS_PREFETCH 196#define ARCH_HAS_PREFETCH
198#define ARCH_HAS_PREFETCHW 197#define ARCH_HAS_PREFETCHW
diff --git a/arch/sh/include/asm/processor_64.h b/arch/sh/include/asm/processor_64.h
index 803177fcf086..5727d31b0ccf 100644
--- a/arch/sh/include/asm/processor_64.h
+++ b/arch/sh/include/asm/processor_64.h
@@ -145,13 +145,13 @@ struct thread_struct {
145 */ 145 */
146#define SR_USER (SR_MMU | SR_FD) 146#define SR_USER (SR_MMU | SR_FD)
147 147
148#define start_thread(regs, new_pc, new_sp) \ 148#define start_thread(_regs, new_pc, new_sp) \
149 set_fs(USER_DS); \ 149 set_fs(USER_DS); \
150 regs->sr = SR_USER; /* User mode. */ \ 150 _regs->sr = SR_USER; /* User mode. */ \
151 regs->pc = new_pc - 4; /* Compensate syscall exit */ \ 151 _regs->pc = new_pc - 4; /* Compensate syscall exit */ \
152 regs->pc |= 1; /* Set SHmedia ! */ \ 152 _regs->pc |= 1; /* Set SHmedia ! */ \
153 regs->regs[18] = 0; \ 153 _regs->regs[18] = 0; \
154 regs->regs[15] = new_sp 154 _regs->regs[15] = new_sp
155 155
156/* Forward declaration, a strange C thing */ 156/* Forward declaration, a strange C thing */
157struct task_struct; 157struct task_struct;
@@ -226,7 +226,7 @@ extern unsigned long get_wchan(struct task_struct *p);
226#define KSTK_EIP(tsk) ((tsk)->thread.pc) 226#define KSTK_EIP(tsk) ((tsk)->thread.pc)
227#define KSTK_ESP(tsk) ((tsk)->thread.sp) 227#define KSTK_ESP(tsk) ((tsk)->thread.sp)
228 228
229#define user_stack_pointer(regs) ((regs)->regs[15]) 229#define user_stack_pointer(_regs) ((_regs)->regs[15])
230 230
231#endif /* __ASSEMBLY__ */ 231#endif /* __ASSEMBLY__ */
232#endif /* __ASM_SH_PROCESSOR_64_H */ 232#endif /* __ASM_SH_PROCESSOR_64_H */
diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h
index 12912ab80c15..81c6568fdb3e 100644
--- a/arch/sh/include/asm/ptrace.h
+++ b/arch/sh/include/asm/ptrace.h
@@ -122,14 +122,12 @@ extern void user_disable_single_step(struct task_struct *);
122#ifdef CONFIG_SH_DSP 122#ifdef CONFIG_SH_DSP
123#define task_pt_regs(task) \ 123#define task_pt_regs(task) \
124 ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \ 124 ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
125 - sizeof(struct pt_dspregs) - sizeof(unsigned long)) - 1) 125 - sizeof(struct pt_dspregs)) - 1)
126#define task_pt_dspregs(task) \ 126#define task_pt_dspregs(task) \
127 ((struct pt_dspregs *) (task_stack_page(task) + THREAD_SIZE \ 127 ((struct pt_dspregs *) (task_stack_page(task) + THREAD_SIZE) - 1)
128 - sizeof(unsigned long)) - 1)
129#else 128#else
130#define task_pt_regs(task) \ 129#define task_pt_regs(task) \
131 ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \ 130 ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE) - 1)
132 - sizeof(unsigned long)) - 1)
133#endif 131#endif
134 132
135static inline unsigned long profile_pc(struct pt_regs *regs) 133static inline unsigned long profile_pc(struct pt_regs *regs)
diff --git a/arch/sh/include/asm/sections.h b/arch/sh/include/asm/sections.h
index 8f8f4ad400df..01a4076a3719 100644
--- a/arch/sh/include/asm/sections.h
+++ b/arch/sh/include/asm/sections.h
@@ -3,6 +3,7 @@
3 3
4#include <asm-generic/sections.h> 4#include <asm-generic/sections.h>
5 5
6extern void __nosave_begin, __nosave_end;
6extern long __machvec_start, __machvec_end; 7extern long __machvec_start, __machvec_end;
7extern char __uncached_start, __uncached_end; 8extern char __uncached_start, __uncached_end;
8extern char _ebss[]; 9extern char _ebss[];
diff --git a/arch/sh/include/asm/suspend.h b/arch/sh/include/asm/suspend.h
new file mode 100644
index 000000000000..b1b995370e79
--- /dev/null
+++ b/arch/sh/include/asm/suspend.h
@@ -0,0 +1,22 @@
1#ifndef _ASM_SH_SUSPEND_H
2#define _ASM_SH_SUSPEND_H
3
4#ifndef __ASSEMBLY__
5static inline int arch_prepare_suspend(void) { return 0; }
6
7#include <asm/ptrace.h>
8
9struct swsusp_arch_regs {
10 struct pt_regs user_regs;
11 unsigned long bank1_regs[8];
12};
13#endif
14
15/* flags passed to assembly suspend code */
16#define SUSP_SH_SLEEP (1 << 0) /* Regular sleep mode */
17#define SUSP_SH_STANDBY (1 << 1) /* SH-Mobile Software standby mode */
18#define SUSP_SH_RSTANDBY (1 << 2) /* SH-Mobile R-standby mode */
19#define SUSP_SH_USTANDBY (1 << 3) /* SH-Mobile U-standby mode */
20#define SUSP_SH_SF (1 << 4) /* Enable self-refresh */
21
22#endif /* _ASM_SH_SUSPEND_H */
diff --git a/arch/sh/include/asm/timer.h b/arch/sh/include/asm/timer.h
index a7ca3a195bb5..4c3b66e30af2 100644
--- a/arch/sh/include/asm/timer.h
+++ b/arch/sh/include/asm/timer.h
@@ -9,7 +9,6 @@ struct sys_timer_ops {
9 int (*init)(void); 9 int (*init)(void);
10 int (*start)(void); 10 int (*start)(void);
11 int (*stop)(void); 11 int (*stop)(void);
12 cycle_t (*read)(void);
13#ifndef CONFIG_GENERIC_TIME 12#ifndef CONFIG_GENERIC_TIME
14 unsigned long (*get_offset)(void); 13 unsigned long (*get_offset)(void);
15#endif 14#endif
@@ -39,6 +38,7 @@ struct sys_timer *get_sys_timer(void);
39 38
40/* arch/sh/kernel/time.c */ 39/* arch/sh/kernel/time.c */
41void handle_timer_tick(void); 40void handle_timer_tick(void);
42extern unsigned long sh_hpt_frequency; 41
42extern struct clocksource clocksource_sh;
43 43
44#endif /* __ASM_SH_TIMER_H */ 44#endif /* __ASM_SH_TIMER_H */
diff --git a/arch/sh/include/asm/tlb.h b/arch/sh/include/asm/tlb.h
index 88ff1ae8a6b8..9c16f737074a 100644
--- a/arch/sh/include/asm/tlb.h
+++ b/arch/sh/include/asm/tlb.h
@@ -6,22 +6,106 @@
6#endif 6#endif
7 7
8#ifndef __ASSEMBLY__ 8#ifndef __ASSEMBLY__
9#include <linux/pagemap.h>
10
11#ifdef CONFIG_MMU
12#include <asm/pgalloc.h>
13#include <asm/tlbflush.h>
14
15/*
16 * TLB handling. This allows us to remove pages from the page
17 * tables, and efficiently handle the TLB issues.
18 */
19struct mmu_gather {
20 struct mm_struct *mm;
21 unsigned int fullmm;
22 unsigned long start, end;
23};
9 24
10#define tlb_start_vma(tlb, vma) \ 25DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
11 flush_cache_range(vma, vma->vm_start, vma->vm_end)
12 26
13#define tlb_end_vma(tlb, vma) \ 27static inline void init_tlb_gather(struct mmu_gather *tlb)
14 flush_tlb_range(vma, vma->vm_start, vma->vm_end) 28{
29 tlb->start = TASK_SIZE;
30 tlb->end = 0;
15 31
16#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0) 32 if (tlb->fullmm) {
33 tlb->start = 0;
34 tlb->end = TASK_SIZE;
35 }
36}
37
38static inline struct mmu_gather *
39tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
40{
41 struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
42
43 tlb->mm = mm;
44 tlb->fullmm = full_mm_flush;
45
46 init_tlb_gather(tlb);
47
48 return tlb;
49}
50
51static inline void
52tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
53{
54 if (tlb->fullmm)
55 flush_tlb_mm(tlb->mm);
56
57 /* keep the page table cache within bounds */
58 check_pgt_cache();
59
60 put_cpu_var(mmu_gathers);
61}
62
63static inline void
64tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep, unsigned long address)
65{
66 if (tlb->start > address)
67 tlb->start = address;
68 if (tlb->end < address + PAGE_SIZE)
69 tlb->end = address + PAGE_SIZE;
70}
17 71
18/* 72/*
19 * Flush whole TLBs for MM 73 * In the case of tlb vma handling, we can optimise these away in the
74 * case where we're doing a full MM flush. When we're doing a munmap,
75 * the vmas are adjusted to only cover the region to be torn down.
20 */ 76 */
21#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) 77static inline void
78tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
79{
80 if (!tlb->fullmm)
81 flush_cache_range(vma, vma->vm_start, vma->vm_end);
82}
83
84static inline void
85tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
86{
87 if (!tlb->fullmm && tlb->end) {
88 flush_tlb_range(vma, tlb->start, tlb->end);
89 init_tlb_gather(tlb);
90 }
91}
92
93#define tlb_remove_page(tlb,page) free_page_and_swap_cache(page)
94#define pte_free_tlb(tlb, ptep) pte_free((tlb)->mm, ptep)
95#define pmd_free_tlb(tlb, pmdp) pmd_free((tlb)->mm, pmdp)
96#define pud_free_tlb(tlb, pudp) pud_free((tlb)->mm, pudp)
97
98#define tlb_migrate_finish(mm) do { } while (0)
99
100#else /* CONFIG_MMU */
101
102#define tlb_start_vma(tlb, vma) do { } while (0)
103#define tlb_end_vma(tlb, vma) do { } while (0)
104#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
105#define tlb_flush(tlb) do { } while (0)
22 106
23#include <linux/pagemap.h>
24#include <asm-generic/tlb.h> 107#include <asm-generic/tlb.h>
25 108
109#endif /* CONFIG_MMU */
26#endif /* __ASSEMBLY__ */ 110#endif /* __ASSEMBLY__ */
27#endif /* __ASM_SH_TLB_H */ 111#endif /* __ASM_SH_TLB_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/dma.h b/arch/sh/include/cpu-sh3/cpu/dma.h
index 6813c3220a1d..0ea15f3f2363 100644
--- a/arch/sh/include/cpu-sh3/cpu/dma.h
+++ b/arch/sh/include/cpu-sh3/cpu/dma.h
@@ -1,22 +1,17 @@
1#ifndef __ASM_CPU_SH3_DMA_H 1#ifndef __ASM_CPU_SH3_DMA_H
2#define __ASM_CPU_SH3_DMA_H 2#define __ASM_CPU_SH3_DMA_H
3 3
4
5#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 4#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7721) 5 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
7#define SH_DMAC_BASE 0xa4010020 6 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
8#else 7 defined(CONFIG_CPU_SUBTYPE_SH7712)
9#define SH_DMAC_BASE 0xa4000020 8#define SH_DMAC_BASE0 0xa4010020
9#else /* SH7705/06/07/09 */
10#define SH_DMAC_BASE0 0xa4000020
10#endif 11#endif
11 12
12#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
13#define DMTE0_IRQ 48 13#define DMTE0_IRQ 48
14#define DMTE1_IRQ 49
15#define DMTE2_IRQ 50
16#define DMTE3_IRQ 51
17#define DMTE4_IRQ 76 14#define DMTE4_IRQ 76
18#define DMTE5_IRQ 77
19#endif
20 15
21/* Definitions for the SuperH DMAC */ 16/* Definitions for the SuperH DMAC */
22#define TM_BURST 0x00000020 17#define TM_BURST 0x00000020
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
new file mode 100644
index 000000000000..0ed5178fed69
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
@@ -0,0 +1,94 @@
1#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
2#define __ASM_SH_CPU_SH4_DMA_SH7780_H
3
4#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
5 defined(CONFIG_CPU_SUBTYPE_SH7722) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7730)
7#define DMTE0_IRQ 48
8#define DMTE4_IRQ 76
9#define DMAE0_IRQ 78 /* DMA Error IRQ*/
10#define SH_DMAC_BASE0 0xFE008020
11#define SH_DMARS_BASE 0xFE009000
12#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7764)
14#define DMTE0_IRQ 34
15#define DMTE4_IRQ 44
16#define DMAE0_IRQ 38
17#define SH_DMAC_BASE0 0xFF608020
18#define SH_DMARS_BASE 0xFF609000
19#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
20#define DMTE0_IRQ 48 /* DMAC0A*/
21#define DMTE4_IRQ 40 /* DMAC0B */
22#define DMTE6_IRQ 42
23#define DMTE8_IRQ 76 /* DMAC1A */
24#define DMTE9_IRQ 77
25#define DMTE10_IRQ 72 /* DMAC1B */
26#define DMTE11_IRQ 73
27#define DMAE0_IRQ 78 /* DMA Error IRQ*/
28#define DMAE1_IRQ 74 /* DMA Error IRQ*/
29#define SH_DMAC_BASE0 0xFE008020
30#define SH_DMAC_BASE1 0xFDC08020
31#define SH_DMARS_BASE 0xFDC09000
32#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
33#define DMTE0_IRQ 34
34#define DMTE4_IRQ 44
35#define DMTE6_IRQ 46
36#define DMTE8_IRQ 92
37#define DMTE9_IRQ 93
38#define DMTE10_IRQ 94
39#define DMTE11_IRQ 95
40#define DMAE0_IRQ 38 /* DMA Error IRQ */
41#define SH_DMAC_BASE0 0xFC808020
42#define SH_DMAC_BASE1 0xFC818020
43#define SH_DMARS_BASE 0xFC809000
44#else /* SH7785 */
45#define DMTE0_IRQ 33
46#define DMTE4_IRQ 37
47#define DMTE6_IRQ 52
48#define DMTE8_IRQ 54
49#define DMTE9_IRQ 55
50#define DMTE10_IRQ 56
51#define DMTE11_IRQ 57
52#define DMAE0_IRQ 39 /* DMA Error IRQ0 */
53#define DMAE1_IRQ 58 /* DMA Error IRQ1 */
54#define SH_DMAC_BASE0 0xFC808020
55#define SH_DMAC_BASE1 0xFCC08020
56#define SH_DMARS_BASE 0xFC809000
57#endif
58
59#define REQ_HE 0x000000C0
60#define REQ_H 0x00000080
61#define REQ_LE 0x00000040
62#define TM_BURST 0x0000020
63#define TS_8 0x00000000
64#define TS_16 0x00000008
65#define TS_32 0x00000010
66#define TS_16BLK 0x00000018
67#define TS_32BLK 0x00100000
68
69/*
70 * The SuperH DMAC supports a number of transmit sizes, we list them here,
71 * with their respective values as they appear in the CHCR registers.
72 *
73 * Defaults to a 64-bit transfer size.
74 */
75enum {
76 XMIT_SZ_8BIT,
77 XMIT_SZ_16BIT,
78 XMIT_SZ_32BIT,
79 XMIT_SZ_128BIT,
80 XMIT_SZ_256BIT,
81};
82
83/*
84 * The DMA count is defined as the number of bytes to transfer.
85 */
86static unsigned int ts_shift[] __maybe_unused = {
87 [XMIT_SZ_8BIT] = 0,
88 [XMIT_SZ_16BIT] = 1,
89 [XMIT_SZ_32BIT] = 2,
90 [XMIT_SZ_128BIT] = 4,
91 [XMIT_SZ_256BIT] = 5,
92};
93
94#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh7780.h b/arch/sh/include/cpu-sh4/cpu/dma-sh7780.h
deleted file mode 100644
index 71b426a6e482..000000000000
--- a/arch/sh/include/cpu-sh4/cpu/dma-sh7780.h
+++ /dev/null
@@ -1,39 +0,0 @@
1#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
2#define __ASM_SH_CPU_SH4_DMA_SH7780_H
3
4#define REQ_HE 0x000000C0
5#define REQ_H 0x00000080
6#define REQ_LE 0x00000040
7#define TM_BURST 0x0000020
8#define TS_8 0x00000000
9#define TS_16 0x00000008
10#define TS_32 0x00000010
11#define TS_16BLK 0x00000018
12#define TS_32BLK 0x00100000
13
14/*
15 * The SuperH DMAC supports a number of transmit sizes, we list them here,
16 * with their respective values as they appear in the CHCR registers.
17 *
18 * Defaults to a 64-bit transfer size.
19 */
20enum {
21 XMIT_SZ_8BIT,
22 XMIT_SZ_16BIT,
23 XMIT_SZ_32BIT,
24 XMIT_SZ_128BIT,
25 XMIT_SZ_256BIT,
26};
27
28/*
29 * The DMA count is defined as the number of bytes to transfer.
30 */
31static unsigned int ts_shift[] __maybe_unused = {
32 [XMIT_SZ_8BIT] = 0,
33 [XMIT_SZ_16BIT] = 1,
34 [XMIT_SZ_32BIT] = 2,
35 [XMIT_SZ_128BIT] = 4,
36 [XMIT_SZ_256BIT] = 5,
37};
38
39#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma.h b/arch/sh/include/cpu-sh4/cpu/dma.h
index 235b7cd1fc9a..bcb30246e85c 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma.h
@@ -1,31 +1,29 @@
1#ifndef __ASM_CPU_SH4_DMA_H 1#ifndef __ASM_CPU_SH4_DMA_H
2#define __ASM_CPU_SH4_DMA_H 2#define __ASM_CPU_SH4_DMA_H
3 3
4#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
5
6/* SH7751/7760/7780 DMA IRQ sources */ 4/* SH7751/7760/7780 DMA IRQ sources */
7#define DMTE0_IRQ 34
8#define DMTE1_IRQ 35
9#define DMTE2_IRQ 36
10#define DMTE3_IRQ 37
11#define DMTE4_IRQ 44
12#define DMTE5_IRQ 45
13#define DMTE6_IRQ 46
14#define DMTE7_IRQ 47
15#define DMAE_IRQ 38
16 5
17#ifdef CONFIG_CPU_SH4A 6#ifdef CONFIG_CPU_SH4A
18#define SH_DMAC_BASE 0xfc808020
19 7
8#define DMAOR_INIT (DMAOR_DME)
20#define CHCR_TS_MASK 0x18 9#define CHCR_TS_MASK 0x18
21#define CHCR_TS_SHIFT 3 10#define CHCR_TS_SHIFT 3
22 11
23#include <cpu/dma-sh7780.h> 12#include <cpu/dma-sh4a.h>
24#else 13#else /* CONFIG_CPU_SH4A */
25#define SH_DMAC_BASE 0xffa00000 14/*
15 * SH7750/SH7751/SH7760
16 */
17#define DMTE0_IRQ 34
18#define DMTE4_IRQ 44
19#define DMTE6_IRQ 46
20#define DMAE0_IRQ 38
26 21
22#define DMAOR_INIT (0x8000|DMAOR_DME)
23#define SH_DMAC_BASE0 0xffa00000
24#define SH_DMAC_BASE1 0xffa00070
27/* Definitions for the SuperH DMAC */ 25/* Definitions for the SuperH DMAC */
28#define TM_BURST 0x0000080 26#define TM_BURST 0x00000080
29#define TS_8 0x00000010 27#define TS_8 0x00000010
30#define TS_16 0x00000020 28#define TS_16 0x00000020
31#define TS_32 0x00000030 29#define TS_32 0x00000030
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h
index c23af81c2e70..749d1c434337 100644
--- a/arch/sh/include/cpu-sh4/cpu/freq.h
+++ b/arch/sh/include/cpu-sh4/cpu/freq.h
@@ -29,6 +29,10 @@
29#define FRQCR0 0xffc80000 29#define FRQCR0 0xffc80000
30#define FRQCR1 0xffc80004 30#define FRQCR1 0xffc80004
31#define FRQMR1 0xffc80014 31#define FRQMR1 0xffc80014
32#elif defined(CONFIG_CPU_SUBTYPE_SH7786)
33#define FRQCR0 0xffc40000
34#define FRQCR1 0xffc40004
35#define FRQMR1 0xffc40014
32#elif defined(CONFIG_CPU_SUBTYPE_SHX3) 36#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
33#define FRQCR 0xffc00014 37#define FRQCR 0xffc00014
34#else 38#else
diff --git a/arch/sh/include/cpu-sh4/cpu/mmu_context.h b/arch/sh/include/cpu-sh4/cpu/mmu_context.h
index 9ea8eb27b18e..3ce7ef6c2978 100644
--- a/arch/sh/include/cpu-sh4/cpu/mmu_context.h
+++ b/arch/sh/include/cpu-sh4/cpu/mmu_context.h
@@ -14,28 +14,35 @@
14#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */ 14#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
15#define MMU_TTB 0xFF000008 /* Translation table base register */ 15#define MMU_TTB 0xFF000008 /* Translation table base register */
16#define MMU_TEA 0xFF00000C /* TLB Exception Address */ 16#define MMU_TEA 0xFF00000C /* TLB Exception Address */
17#define MMU_PTEA 0xFF000034 /* Page table entry assistance register */ 17#define MMU_PTEA 0xFF000034 /* PTE assistance register */
18#define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */
18 19
19#define MMUCR 0xFF000010 /* MMU Control Register */ 20#define MMUCR 0xFF000010 /* MMU Control Register */
20 21
21#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
22#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 22#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
23#define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000
23#define MMU_PAGE_ASSOC_BIT 0x80 24#define MMU_PAGE_ASSOC_BIT 0x80
24 25
25#define MMUCR_TI (1<<2) 26#define MMUCR_TI (1<<2)
26 27
27#ifdef CONFIG_X2TLB
28#define MMUCR_ME (1 << 7)
29#else
30#define MMUCR_ME (0)
31#endif
32
33#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40) 28#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40)
34#define MMUCR_SE (1 << 4) 29#define MMUCR_SE (1 << 4)
35#else 30#else
36#define MMUCR_SE (0) 31#define MMUCR_SE (0)
37#endif 32#endif
38 33
34#ifdef CONFIG_CPU_HAS_PTEAEX
35#define MMUCR_AEX (1 << 6)
36#else
37#define MMUCR_AEX (0)
38#endif
39
40#ifdef CONFIG_X2TLB
41#define MMUCR_ME (1 << 7)
42#else
43#define MMUCR_ME (0)
44#endif
45
39#ifdef CONFIG_SH_STORE_QUEUES 46#ifdef CONFIG_SH_STORE_QUEUES
40#define MMUCR_SQMD (1 << 9) 47#define MMUCR_SQMD (1 << 9)
41#else 48#else
@@ -43,17 +50,7 @@
43#endif 50#endif
44 51
45#define MMU_NTLB_ENTRIES 64 52#define MMU_NTLB_ENTRIES 64
46#define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE) 53#define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE|MMUCR_AEX)
47
48#define MMU_ITLB_DATA_ARRAY 0xF3000000
49#define MMU_UTLB_DATA_ARRAY 0xF7000000
50
51#define MMU_UTLB_ENTRIES 64
52#define MMU_U_ENTRY_SHIFT 8
53#define MMU_UTLB_VALID 0x100
54#define MMU_ITLB_ENTRIES 4
55#define MMU_I_ENTRY_SHIFT 8
56#define MMU_ITLB_VALID 0x100
57 54
58#define TRA 0xff000020 55#define TRA 0xff000020
59#define EXPEVT 0xff000024 56#define EXPEVT 0xff000024
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7786.h b/arch/sh/include/cpu-sh4/cpu/sh7786.h
new file mode 100644
index 000000000000..48688adc0c84
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sh7786.h
@@ -0,0 +1,192 @@
1/*
2 * SH7786 Pinmux
3 *
4 * Copyright (C) 2008, 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on sh7785.h
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13
14#ifndef __CPU_SH7786_H__
15#define __CPU_SH7786_H__
16
17enum {
18 /* PA */
19 GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,
20 GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
21
22 /* PB */
23 GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
24 GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0,
25
26 /* PC */
27 GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
28 GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
29
30 /* PD */
31 GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
32 GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
33
34 /* PE */
35 GPIO_PE5, GPIO_PE4, GPIO_PE3, GPIO_PE2,
36 GPIO_PE1, GPIO_PE0,
37
38 /* PF */
39 GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
40 GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
41
42 /* PG */
43 GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
44 GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
45
46 /* PH */
47 GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
48 GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
49
50 /* PJ */
51 GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
52 GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,
53
54 GPIO_FN_CDE,
55 GPIO_FN_ETH_MAGIC,
56 GPIO_FN_DISP,
57 GPIO_FN_ETH_LINK,
58 GPIO_FN_DR5,
59 GPIO_FN_ETH_TX_ER,
60 GPIO_FN_DR4,
61 GPIO_FN_ETH_TX_EN,
62 GPIO_FN_DR3,
63 GPIO_FN_ETH_TXD3,
64 GPIO_FN_DR2,
65 GPIO_FN_ETH_TXD2,
66 GPIO_FN_DR1,
67 GPIO_FN_ETH_TXD1,
68 GPIO_FN_DR0,
69 GPIO_FN_ETH_TXD0,
70 GPIO_FN_VSYNC,
71 GPIO_FN_HSPI_CLK,
72 GPIO_FN_ODDF,
73 GPIO_FN_HSPI_CS,
74 GPIO_FN_DG5,
75 GPIO_FN_ETH_MDIO,
76 GPIO_FN_DG4,
77 GPIO_FN_ETH_RX_CLK,
78 GPIO_FN_DG3,
79 GPIO_FN_ETH_MDC,
80 GPIO_FN_DG2,
81 GPIO_FN_ETH_COL,
82 GPIO_FN_DG1,
83 GPIO_FN_ETH_TX_CLK,
84 GPIO_FN_DG0,
85 GPIO_FN_ETH_CRS,
86 GPIO_FN_DCLKIN,
87 GPIO_FN_HSPI_RX,
88 GPIO_FN_HSYNC,
89 GPIO_FN_HSPI_TX,
90 GPIO_FN_DB5,
91 GPIO_FN_ETH_RXD3,
92 GPIO_FN_DB4,
93 GPIO_FN_ETH_RXD2,
94 GPIO_FN_DB3,
95 GPIO_FN_ETH_RXD1,
96 GPIO_FN_DB2,
97 GPIO_FN_ETH_RXD0,
98 GPIO_FN_DB1,
99 GPIO_FN_ETH_RX_DV,
100 GPIO_FN_DB0,
101 GPIO_FN_ETH_RX_ER,
102 GPIO_FN_DCLKOUT,
103 GPIO_FN_SCIF1_SLK,
104 GPIO_FN_SCIF1_RXD,
105 GPIO_FN_SCIF1_TXD,
106 GPIO_FN_DACK1,
107 GPIO_FN_BACK,
108 GPIO_FN_FALE,
109 GPIO_FN_DACK0,
110 GPIO_FN_FCLE,
111 GPIO_FN_DREQ1,
112 GPIO_FN_BREQ,
113 GPIO_FN_USB_OVC1,
114 GPIO_FN_DREQ0,
115 GPIO_FN_USB_OVC0,
116 GPIO_FN_USB_PENC1,
117 GPIO_FN_USB_PENC0,
118 GPIO_FN_HAC1_SDOUT,
119 GPIO_FN_SSI1_SDATA,
120 GPIO_FN_SDIF1CMD,
121 GPIO_FN_HAC1_SDIN,
122 GPIO_FN_SSI1_SCK,
123 GPIO_FN_SDIF1CD,
124 GPIO_FN_HAC1_SYNC,
125 GPIO_FN_SSI1_WS,
126 GPIO_FN_SDIF1WP,
127 GPIO_FN_HAC1_BITCLK,
128 GPIO_FN_SSI1_CLK,
129 GPIO_FN_SDIF1CLK,
130 GPIO_FN_HAC0_SDOUT,
131 GPIO_FN_SSI0_SDATA,
132 GPIO_FN_SDIF1D3,
133 GPIO_FN_HAC0_SDIN,
134 GPIO_FN_SSI0_SCK,
135 GPIO_FN_SDIF1D2,
136 GPIO_FN_HAC0_SYNC,
137 GPIO_FN_SSI0_WS,
138 GPIO_FN_SDIF1D1,
139 GPIO_FN_HAC0_BITCLK,
140 GPIO_FN_SSI0_CLK,
141 GPIO_FN_SDIF1D0,
142 GPIO_FN_SCIF3_SCK,
143 GPIO_FN_SSI2_SDATA,
144 GPIO_FN_SCIF3_RXD,
145 GPIO_FN_TCLK,
146 GPIO_FN_SSI2_SCK,
147 GPIO_FN_SCIF3_TXD,
148 GPIO_FN_HAC_RES,
149 GPIO_FN_SSI2_WS,
150 GPIO_FN_DACK3,
151 GPIO_FN_SDIF0CMD,
152 GPIO_FN_DACK2,
153 GPIO_FN_SDIF0CD,
154 GPIO_FN_DREQ3,
155 GPIO_FN_SDIF0WP,
156 GPIO_FN_SCIF0_CTS,
157 GPIO_FN_DREQ2,
158 GPIO_FN_SDIF0CLK,
159 GPIO_FN_SCIF0_RTS,
160 GPIO_FN_IRL7,
161 GPIO_FN_SDIF0D3,
162 GPIO_FN_SCIF0_SCK,
163 GPIO_FN_IRL6,
164 GPIO_FN_SDIF0D2,
165 GPIO_FN_SCIF0_RXD,
166 GPIO_FN_IRL5,
167 GPIO_FN_SDIF0D1,
168 GPIO_FN_SCIF0_TXD,
169 GPIO_FN_IRL4,
170 GPIO_FN_SDIF0D0,
171 GPIO_FN_SCIF5_SCK,
172 GPIO_FN_FRB,
173 GPIO_FN_SCIF5_RXD,
174 GPIO_FN_IOIS16,
175 GPIO_FN_SCIF5_TXD,
176 GPIO_FN_CE2B,
177 GPIO_FN_DRAK3,
178 GPIO_FN_CE2A,
179 GPIO_FN_SCIF4_SCK,
180 GPIO_FN_DRAK2,
181 GPIO_FN_SSI3_WS,
182 GPIO_FN_SCIF4_RXD,
183 GPIO_FN_DRAK1,
184 GPIO_FN_SSI3_SDATA,
185 GPIO_FN_FSTATUS,
186 GPIO_FN_SCIF4_TXD,
187 GPIO_FN_DRAK0,
188 GPIO_FN_SSI3_SCK,
189 GPIO_FN_FSE,
190};
191
192#endif /* __CPU_SH7786_H__ */
diff --git a/arch/sh/include/mach-common/mach/urquell.h b/arch/sh/include/mach-common/mach/urquell.h
new file mode 100644
index 000000000000..14b3e1d01777
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/urquell.h
@@ -0,0 +1,68 @@
1#ifndef __MACH_URQUELL_H
2#define __MACH_URQUELL_H
3
4/*
5 * ------ 0x00000000 ------------------------------------
6 * CS0 | (SW1,SW47) EEPROM, SRAM, NOR FLASH
7 * -----+ 0x04000000 ------------------------------------
8 * CS1 | (SW47) SRAM, SRAM-LAN-PCMCIA, NOR FLASH
9 * -----+ 0x08000000 ------------------------------------
10 * CS2 | DDR3
11 * CS3 |
12 * -----+ 0x10000000 ------------------------------------
13 * CS4 | PCIe
14 * -----+ 0x14000000 ------------------------------------
15 * CS5 | (SW47) LRAM/URAM, SRAM-LAN-PCMCIA
16 * -----+ 0x18000000 ------------------------------------
17 * CS6 | ATA, NAND FLASH
18 * -----+ 0x1c000000 ------------------------------------
19 * CS7 | SH7786 register
20 * -----+------------------------------------------------
21 */
22
23#define NOR_FLASH_ADDR 0x00000000
24#define NOR_FLASH_SIZE 0x04000000
25
26#define CS1_BASE 0x05000000
27#define CS5_BASE 0x15000000
28#define FPGA_BASE CS1_BASE
29
30#define BOARDREG(ofs) (FPGA_BASE + ofs##_OFS)
31#define UBOARDREG(ofs) (0xa0000000 + FPGA_BASE + ofs##_OFS)
32
33#define SRSTR_OFS 0x0000 /* System reset register */
34#define BDMR_OFS 0x0010 /* Board operating mode resister */
35#define IRL0SR_OFS 0x0020 /* IRL0 Status register */
36#define IRL0MSKR_OFS 0x0030 /* IRL0 Mask register */
37#define IRL1SR_OFS 0x0040 /* IRL1 Status register */
38#define IRL1MSKR_OFS 0x0050 /* IRL1 Mask register */
39#define IRL2SR_OFS 0x0060 /* IRL2 Status register */
40#define IRL2MSKR_OFS 0x0070 /* IRL2 Mask register */
41#define IRL3SR_OFS 0x0080 /* IRL3 Status register */
42#define IRL3MSKR_OFS 0x0090 /* IRL3 Mask register */
43#define SOFTINTR_OFS 0x0120 /* Softwear Interrupt register */
44#define SLEDR_OFS 0x0130 /* LED control resister */
45#define MAPSCIFSWR_OFS 0x0140 /* Map/SCIF Switch register */
46#define FPVERR_OFS 0x0150 /* FPGA Version register */
47#define FPDATER_OFS 0x0160 /* FPGA Date register */
48#define FPYEARR_OFS 0x0170 /* FPGA Year register */
49#define TCLKCR_OFS 0x0180 /* TCLK Control register */
50#define DIPSWMR_OFS 0x1000 /* DIPSW monitor register */
51#define FPODR_OFS 0x1010 /* Output port data register */
52#define ATACNR_OFS 0x1020 /* ATA-CN Control/status register */
53#define FPINDR_OFS 0x1030 /* Input port data register */
54#define MDSWMR_OFS 0x1040 /* MODE SW monitor register */
55#define DDR3BUPCR_OFS 0x1050 /* DDR3 Backup control register */
56#define SSICODECCR_OFS 0x1060 /* SSI-CODEC control register */
57#define PCIESLOTSR_OFS 0x1070 /* PCIexpress Slot status register */
58#define ETHERPORTSR_OFS 0x1080 /* EtherPhy Port status register */
59#define LATCHCR_OFS 0x3000 /* Latch control register */
60#define LATCUAR_OFS 0x3010 /* Latch upper address register */
61#define LATCLAR_OFS 0x3012 /* Latch lower address register */
62#define LATCLUDR_OFS 0x3024 /* Latch D31-16 register */
63#define LATCLLDR_OFS 0x3026 /* Latch D15-0 register */
64
65#define CHARLED_OFS 0x2000 /* Character LED */
66
67#endif /* __MACH_URQUELL_H */
68
diff --git a/arch/sh/kernel/Makefile_32 b/arch/sh/kernel/Makefile_32
index 2e1b86e16ab5..82a3a150c00d 100644
--- a/arch/sh/kernel/Makefile_32
+++ b/arch/sh/kernel/Makefile_32
@@ -30,5 +30,6 @@ obj-$(CONFIG_KPROBES) += kprobes.o
30obj-$(CONFIG_GENERIC_GPIO) += gpio.o 30obj-$(CONFIG_GENERIC_GPIO) += gpio.o
31obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o 31obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
32obj-$(CONFIG_DUMP_CODE) += disassemble.o 32obj-$(CONFIG_DUMP_CODE) += disassemble.o
33obj-$(CONFIG_HIBERNATION) += swsusp.o
33 34
34EXTRA_CFLAGS += -Werror 35EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/kernel/asm-offsets.c b/arch/sh/kernel/asm-offsets.c
index 57cf0e0680f3..99aceb28ee24 100644
--- a/arch/sh/kernel/asm-offsets.c
+++ b/arch/sh/kernel/asm-offsets.c
@@ -12,8 +12,10 @@
12#include <linux/types.h> 12#include <linux/types.h>
13#include <linux/mm.h> 13#include <linux/mm.h>
14#include <linux/kbuild.h> 14#include <linux/kbuild.h>
15#include <linux/suspend.h>
15 16
16#include <asm/thread_info.h> 17#include <asm/thread_info.h>
18#include <asm/suspend.h>
17 19
18int main(void) 20int main(void)
19{ 21{
@@ -25,5 +27,11 @@ int main(void)
25 DEFINE(TI_PRE_COUNT, offsetof(struct thread_info, preempt_count)); 27 DEFINE(TI_PRE_COUNT, offsetof(struct thread_info, preempt_count));
26 DEFINE(TI_RESTART_BLOCK,offsetof(struct thread_info, restart_block)); 28 DEFINE(TI_RESTART_BLOCK,offsetof(struct thread_info, restart_block));
27 29
30#ifdef CONFIG_HIBERNATION
31 DEFINE(PBE_ADDRESS, offsetof(struct pbe, address));
32 DEFINE(PBE_ORIG_ADDRESS, offsetof(struct pbe, orig_address));
33 DEFINE(PBE_NEXT, offsetof(struct pbe, next));
34 DEFINE(SWSUSP_ARCH_REGS_SIZE, sizeof(struct swsusp_arch_regs));
35#endif
28 return 0; 36 return 0;
29} 37}
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index f471d242774e..2600641a483f 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CPU_SH5) = sh5/
11# Special cases for family ancestry. 11# Special cases for family ancestry.
12 12
13obj-$(CONFIG_CPU_SH4A) += sh4a/ 13obj-$(CONFIG_CPU_SH4A) += sh4a/
14obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/
14 15
15# Common interfaces. 16# Common interfaces.
16 17
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index 7b17137536d6..1dc896483b59 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -20,6 +20,8 @@
20#include <linux/mutex.h> 20#include <linux/mutex.h>
21#include <linux/list.h> 21#include <linux/list.h>
22#include <linux/kref.h> 22#include <linux/kref.h>
23#include <linux/kobject.h>
24#include <linux/sysdev.h>
23#include <linux/seq_file.h> 25#include <linux/seq_file.h>
24#include <linux/err.h> 26#include <linux/err.h>
25#include <linux/platform_device.h> 27#include <linux/platform_device.h>
@@ -239,6 +241,35 @@ void clk_recalc_rate(struct clk *clk)
239} 241}
240EXPORT_SYMBOL_GPL(clk_recalc_rate); 242EXPORT_SYMBOL_GPL(clk_recalc_rate);
241 243
244int clk_set_parent(struct clk *clk, struct clk *parent)
245{
246 int ret = -EINVAL;
247 struct clk *old;
248
249 if (!parent || !clk)
250 return ret;
251
252 old = clk->parent;
253 if (likely(clk->ops && clk->ops->set_parent)) {
254 unsigned long flags;
255 spin_lock_irqsave(&clock_lock, flags);
256 ret = clk->ops->set_parent(clk, parent);
257 spin_unlock_irqrestore(&clock_lock, flags);
258 clk->parent = (ret ? old : parent);
259 }
260
261 if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
262 propagate_rate(clk);
263 return ret;
264}
265EXPORT_SYMBOL_GPL(clk_set_parent);
266
267struct clk *clk_get_parent(struct clk *clk)
268{
269 return clk->parent;
270}
271EXPORT_SYMBOL_GPL(clk_get_parent);
272
242long clk_round_rate(struct clk *clk, unsigned long rate) 273long clk_round_rate(struct clk *clk, unsigned long rate)
243{ 274{
244 if (likely(clk->ops && clk->ops->round_rate)) { 275 if (likely(clk->ops && clk->ops->round_rate)) {
@@ -329,6 +360,70 @@ static int show_clocks(char *buf, char **start, off_t off,
329 return p - buf; 360 return p - buf;
330} 361}
331 362
363#ifdef CONFIG_PM
364static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state)
365{
366 static pm_message_t prev_state;
367 struct clk *clkp;
368
369 switch (state.event) {
370 case PM_EVENT_ON:
371 /* Resumeing from hibernation */
372 if (prev_state.event == PM_EVENT_FREEZE) {
373 list_for_each_entry(clkp, &clock_list, node)
374 if (likely(clkp->ops)) {
375 unsigned long rate = clkp->rate;
376
377 if (likely(clkp->ops->set_parent))
378 clkp->ops->set_parent(clkp,
379 clkp->parent);
380 if (likely(clkp->ops->set_rate))
381 clkp->ops->set_rate(clkp,
382 rate, NO_CHANGE);
383 else if (likely(clkp->ops->recalc))
384 clkp->ops->recalc(clkp);
385 }
386 }
387 break;
388 case PM_EVENT_FREEZE:
389 break;
390 case PM_EVENT_SUSPEND:
391 break;
392 }
393
394 prev_state = state;
395 return 0;
396}
397
398static int clks_sysdev_resume(struct sys_device *dev)
399{
400 return clks_sysdev_suspend(dev, PMSG_ON);
401}
402
403static struct sysdev_class clks_sysdev_class = {
404 .name = "clks",
405};
406
407static struct sysdev_driver clks_sysdev_driver = {
408 .suspend = clks_sysdev_suspend,
409 .resume = clks_sysdev_resume,
410};
411
412static struct sys_device clks_sysdev_dev = {
413 .cls = &clks_sysdev_class,
414};
415
416static int __init clk_sysdev_init(void)
417{
418 sysdev_class_register(&clks_sysdev_class);
419 sysdev_driver_register(&clks_sysdev_class, &clks_sysdev_driver);
420 sysdev_register(&clks_sysdev_dev);
421
422 return 0;
423}
424subsys_initcall(clk_sysdev_init);
425#endif
426
332int __init clk_init(void) 427int __init clk_init(void)
333{ 428{
334 int i, ret = 0; 429 int i, ret = 0;
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index 56e5878e5516..0e32d8e448ca 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -2,6 +2,7 @@
2 * SH7619 Setup 2 * SH7619 Setup
3 * 3 *
4 * Copyright (C) 2006 Yoshinori Sato 4 * Copyright (C) 2006 Yoshinori Sato
5 * Copyright (C) 2009 Paul Mundt
5 * 6 *
6 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
@@ -18,15 +19,10 @@ enum {
18 /* interrupt sources */ 19 /* interrupt sources */
19 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 20 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
20 WDT, EDMAC, CMT0, CMT1, 21 WDT, EDMAC, CMT0, CMT1,
21 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI, 22 SCIF0, SCIF1, SCIF2,
22 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
23 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
24 HIF_HIFI, HIF_HIFBI, 23 HIF_HIFI, HIF_HIFBI,
25 DMAC0, DMAC1, DMAC2, DMAC3, 24 DMAC0, DMAC1, DMAC2, DMAC3,
26 SIOF, 25 SIOF,
27
28 /* interrupt groups */
29 SCIF0, SCIF1, SCIF2,
30}; 26};
31 27
32static struct intc_vect vectors[] __initdata = { 28static struct intc_vect vectors[] __initdata = {
@@ -36,24 +32,18 @@ static struct intc_vect vectors[] __initdata = {
36 INTC_IRQ(IRQ6, 82), INTC_IRQ(IRQ7, 83), 32 INTC_IRQ(IRQ6, 82), INTC_IRQ(IRQ7, 83),
37 INTC_IRQ(WDT, 84), INTC_IRQ(EDMAC, 85), 33 INTC_IRQ(WDT, 84), INTC_IRQ(EDMAC, 85),
38 INTC_IRQ(CMT0, 86), INTC_IRQ(CMT1, 87), 34 INTC_IRQ(CMT0, 86), INTC_IRQ(CMT1, 87),
39 INTC_IRQ(SCIF0_ERI, 88), INTC_IRQ(SCIF0_RXI, 89), 35 INTC_IRQ(SCIF0, 88), INTC_IRQ(SCIF0, 89),
40 INTC_IRQ(SCIF0_BRI, 90), INTC_IRQ(SCIF0_TXI, 91), 36 INTC_IRQ(SCIF0, 90), INTC_IRQ(SCIF0, 91),
41 INTC_IRQ(SCIF1_ERI, 92), INTC_IRQ(SCIF1_RXI, 93), 37 INTC_IRQ(SCIF1, 92), INTC_IRQ(SCIF1, 93),
42 INTC_IRQ(SCIF1_BRI, 94), INTC_IRQ(SCIF1_TXI, 95), 38 INTC_IRQ(SCIF1, 94), INTC_IRQ(SCIF1, 95),
43 INTC_IRQ(SCIF2_ERI, 96), INTC_IRQ(SCIF2_RXI, 97), 39 INTC_IRQ(SCIF2, 96), INTC_IRQ(SCIF2, 97),
44 INTC_IRQ(SCIF2_BRI, 98), INTC_IRQ(SCIF2_TXI, 99), 40 INTC_IRQ(SCIF2, 98), INTC_IRQ(SCIF2, 99),
45 INTC_IRQ(HIF_HIFI, 100), INTC_IRQ(HIF_HIFBI, 101), 41 INTC_IRQ(HIF_HIFI, 100), INTC_IRQ(HIF_HIFBI, 101),
46 INTC_IRQ(DMAC0, 104), INTC_IRQ(DMAC1, 105), 42 INTC_IRQ(DMAC0, 104), INTC_IRQ(DMAC1, 105),
47 INTC_IRQ(DMAC2, 106), INTC_IRQ(DMAC3, 107), 43 INTC_IRQ(DMAC2, 106), INTC_IRQ(DMAC3, 107),
48 INTC_IRQ(SIOF, 108), 44 INTC_IRQ(SIOF, 108),
49}; 45};
50 46
51static struct intc_group groups[] __initdata = {
52 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
53 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
54 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
55};
56
57static struct intc_prio_reg prio_registers[] __initdata = { 47static struct intc_prio_reg prio_registers[] __initdata = {
58 { 0xf8140006, 0, 16, 4, /* IPRA */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, 48 { 0xf8140006, 0, 16, 4, /* IPRA */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
59 { 0xf8140008, 0, 16, 4, /* IPRB */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, 49 { 0xf8140008, 0, 16, 4, /* IPRB */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
@@ -64,7 +54,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
64 { 0xf8080008, 0, 16, 4, /* IPRG */ { SIOF } }, 54 { 0xf8080008, 0, 16, 4, /* IPRG */ { SIOF } },
65}; 55};
66 56
67static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, groups, 57static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
68 NULL, prio_registers, NULL); 58 NULL, prio_registers, NULL);
69 59
70static struct plat_sci_port sci_platform_data[] = { 60static struct plat_sci_port sci_platform_data[] = {
@@ -72,17 +62,17 @@ static struct plat_sci_port sci_platform_data[] = {
72 .mapbase = 0xf8400000, 62 .mapbase = 0xf8400000,
73 .flags = UPF_BOOT_AUTOCONF, 63 .flags = UPF_BOOT_AUTOCONF,
74 .type = PORT_SCIF, 64 .type = PORT_SCIF,
75 .irqs = { 88, 89, 91, 90}, 65 .irqs = { 88, 88, 88, 88 },
76 }, { 66 }, {
77 .mapbase = 0xf8410000, 67 .mapbase = 0xf8410000,
78 .flags = UPF_BOOT_AUTOCONF, 68 .flags = UPF_BOOT_AUTOCONF,
79 .type = PORT_SCIF, 69 .type = PORT_SCIF,
80 .irqs = { 92, 93, 95, 94}, 70 .irqs = { 92, 92, 92, 92 },
81 }, { 71 }, {
82 .mapbase = 0xf8420000, 72 .mapbase = 0xf8420000,
83 .flags = UPF_BOOT_AUTOCONF, 73 .flags = UPF_BOOT_AUTOCONF,
84 .type = PORT_SCIF, 74 .type = PORT_SCIF,
85 .irqs = { 96, 97, 99, 98}, 75 .irqs = { 96, 96, 96, 96 },
86 }, { 76 }, {
87 .flags = 0, 77 .flags = 0,
88 } 78 }
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index e611d79fac4c..844293723cfc 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Renesas MX-G (R8A03022BG) Setup 2 * Renesas MX-G (R8A03022BG) Setup
3 * 3 *
4 * Copyright (C) 2008 Paul Mundt 4 * Copyright (C) 2008, 2009 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
@@ -20,23 +20,15 @@ enum {
20 IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, IRQ15, 20 IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, IRQ15,
21 21
22 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, 22 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
23
24 SINT8, SINT7, SINT6, SINT5, SINT4, SINT3, SINT2, SINT1, 23 SINT8, SINT7, SINT6, SINT5, SINT4, SINT3, SINT2, SINT1,
25 24
26 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, 25 SCIF0, SCIF1,
27 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
28 26
29 MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D, 27 MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5
30 MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F, 28 MTU2_TGI3B, MTU2_TGI3C,
31 MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
32 MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
33 MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
34 MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
35 MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W,
36 29
37 /* interrupt groups */ 30 /* interrupt groups */
38 PINT, SCIF0, SCIF1, 31 PINT,
39 MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5
40}; 32};
41 33
42static struct intc_vect vectors[] __initdata = { 34static struct intc_vect vectors[] __initdata = {
@@ -59,47 +51,36 @@ static struct intc_vect vectors[] __initdata = {
59 INTC_IRQ(SINT4, 98), INTC_IRQ(SINT3, 99), 51 INTC_IRQ(SINT4, 98), INTC_IRQ(SINT3, 99),
60 INTC_IRQ(SINT2, 100), INTC_IRQ(SINT1, 101), 52 INTC_IRQ(SINT2, 100), INTC_IRQ(SINT1, 101),
61 53
62 INTC_IRQ(SCIF0_RXI, 220), INTC_IRQ(SCIF0_TXI, 221), 54 INTC_IRQ(SCIF0, 220), INTC_IRQ(SCIF0, 221),
63 INTC_IRQ(SCIF0_BRI, 222), INTC_IRQ(SCIF0_ERI, 223), 55 INTC_IRQ(SCIF0, 222), INTC_IRQ(SCIF0, 223),
64 INTC_IRQ(SCIF1_RXI, 224), INTC_IRQ(SCIF1_TXI, 225), 56 INTC_IRQ(SCIF1, 224), INTC_IRQ(SCIF1, 225),
65 INTC_IRQ(SCIF1_BRI, 226), INTC_IRQ(SCIF1_ERI, 227), 57 INTC_IRQ(SCIF1, 226), INTC_IRQ(SCIF1, 227),
66 58
67 INTC_IRQ(MTU2_TGI0A, 228), INTC_IRQ(MTU2_TGI0B, 229), 59 INTC_IRQ(MTU2_GROUP1, 228), INTC_IRQ(MTU2_GROUP1, 229),
68 INTC_IRQ(MTU2_TGI0C, 230), INTC_IRQ(MTU2_TGI0D, 231), 60 INTC_IRQ(MTU2_GROUP1, 230), INTC_IRQ(MTU2_GROUP1, 231),
69 INTC_IRQ(MTU2_TCI0V, 232), INTC_IRQ(MTU2_TGI0E, 233), 61 INTC_IRQ(MTU2_GROUP1, 232), INTC_IRQ(MTU2_GROUP1, 233),
70 62
71 INTC_IRQ(MTU2_TGI0F, 234), INTC_IRQ(MTU2_TGI1A, 235), 63 INTC_IRQ(MTU2_GROUP2, 234), INTC_IRQ(MTU2_GROUP2, 235),
72 INTC_IRQ(MTU2_TGI1B, 236), INTC_IRQ(MTU2_TCI1V, 237), 64 INTC_IRQ(MTU2_GROUP2, 236), INTC_IRQ(MTU2_GROUP2, 237),
73 INTC_IRQ(MTU2_TCI1U, 238), INTC_IRQ(MTU2_TGI2A, 239), 65 INTC_IRQ(MTU2_GROUP2, 238), INTC_IRQ(MTU2_GROUP2, 239),
74 66
75 INTC_IRQ(MTU2_TGI2B, 240), INTC_IRQ(MTU2_TCI2V, 241), 67 INTC_IRQ(MTU2_GROUP3, 240), INTC_IRQ(MTU2_GROUP3, 241),
76 INTC_IRQ(MTU2_TCI2U, 242), INTC_IRQ(MTU2_TGI3A, 243), 68 INTC_IRQ(MTU2_GROUP3, 242), INTC_IRQ(MTU2_GROUP3, 243),
77 69
78 INTC_IRQ(MTU2_TGI3B, 244), 70 INTC_IRQ(MTU2_TGI3B, 244),
79 INTC_IRQ(MTU2_TGI3C, 245), 71 INTC_IRQ(MTU2_TGI3C, 245),
80 72
81 INTC_IRQ(MTU2_TGI3D, 246), INTC_IRQ(MTU2_TCI3V, 247), 73 INTC_IRQ(MTU2_GROUP4, 246), INTC_IRQ(MTU2_GROUP4, 247),
82 INTC_IRQ(MTU2_TGI4A, 248), INTC_IRQ(MTU2_TGI4B, 249), 74 INTC_IRQ(MTU2_GROUP4, 248), INTC_IRQ(MTU2_GROUP4, 249),
83 INTC_IRQ(MTU2_TGI4C, 250), INTC_IRQ(MTU2_TGI4D, 251), 75 INTC_IRQ(MTU2_GROUP4, 250), INTC_IRQ(MTU2_GROUP4, 251),
84 76
85 INTC_IRQ(MTU2_TCI4V, 252), INTC_IRQ(MTU2_TGI5U, 253), 77 INTC_IRQ(MTU2_GROUP5, 252), INTC_IRQ(MTU2_GROUP5, 253),
86 INTC_IRQ(MTU2_TGI5V, 254), INTC_IRQ(MTU2_TGI5W, 255), 78 INTC_IRQ(MTU2_GROUP5, 254), INTC_IRQ(MTU2_GROUP5, 255),
87}; 79};
88 80
89static struct intc_group groups[] __initdata = { 81static struct intc_group groups[] __initdata = {
90 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, 82 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
91 PINT4, PINT5, PINT6, PINT7), 83 PINT4, PINT5, PINT6, PINT7),
92 INTC_GROUP(MTU2_GROUP1, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
93 MTU2_TCI0V, MTU2_TGI0E),
94 INTC_GROUP(MTU2_GROUP2, MTU2_TGI0F, MTU2_TGI1A, MTU2_TGI1B,
95 MTU2_TCI1V, MTU2_TCI1U, MTU2_TGI2A),
96 INTC_GROUP(MTU2_GROUP3, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
97 MTU2_TGI3A),
98 INTC_GROUP(MTU2_GROUP4, MTU2_TGI3D, MTU2_TCI3V, MTU2_TGI4A,
99 MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
100 INTC_GROUP(MTU2_GROUP5, MTU2_TCI4V, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
101 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
102 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
103}; 84};
104 85
105static struct intc_prio_reg prio_registers[] __initdata = { 86static struct intc_prio_reg prio_registers[] __initdata = {
@@ -137,7 +118,7 @@ static struct plat_sci_port sci_platform_data[] = {
137 .mapbase = 0xff804000, 118 .mapbase = 0xff804000,
138 .flags = UPF_BOOT_AUTOCONF, 119 .flags = UPF_BOOT_AUTOCONF,
139 .type = PORT_SCIF, 120 .type = PORT_SCIF,
140 .irqs = { 223, 220, 221, 222 }, 121 .irqs = { 220, 220, 220, 220 },
141 }, { 122 }, {
142 .flags = 0, 123 .flags = 0,
143 } 124 }
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index 0631e421c022..00f42f9e3f5c 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -2,6 +2,7 @@
2 * SH7201 setup 2 * SH7201 setup
3 * 3 *
4 * Copyright (C) 2008 Peter Griffin pgriffin@mpc-data.co.uk 4 * Copyright (C) 2008 Peter Griffin pgriffin@mpc-data.co.uk
5 * Copyright (C) 2009 Paul Mundt
5 * 6 *
6 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
@@ -18,57 +19,32 @@ enum {
18 /* interrupt sources */ 19 /* interrupt sources */
19 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 20 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
20 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, 21 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
22
21 ADC_ADI, 23 ADC_ADI,
22 MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D, 24
23 MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F, 25 MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
24 MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U, 26 MTU23_ABCD, MTU24_ABCD, MTU25_UVW, MTU2_TCI3V, MTU2_TCI4V,
25 MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U, 27
26 MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V, 28 RTC, WDT,
27 MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V, 29
28 MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W, 30 IIC30, IIC31, IIC32,
29 RTC_ARM, RTC_PRD, RTC_CUP,
30 WDT,
31 IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, IIC30_TEI,
32 IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, IIC31_TEI,
33 IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, IIC32_TEI,
34 31
35 DMAC0_DMINT0, DMAC1_DMINT1, 32 DMAC0_DMINT0, DMAC1_DMINT1,
36 DMAC2_DMINT2, DMAC3_DMINT3, 33 DMAC2_DMINT2, DMAC3_DMINT3,
37 34
38 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, 35 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
39 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
40 SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
41 SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
42 SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
43 SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
44 SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
45 SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
46 36
47 DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6, 37 DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6,
48 DMAC7_DMINT7, 38 DMAC7_DMINT7,
49 39
50 RCAN0_ERS, RCAN0_OVR, 40 RCAN0, RCAN1,
51 RCAN0_SLE,
52 RCAN0_RM0, RCAN0_RM1,
53
54 RCAN1_ERS, RCAN1_OVR,
55 RCAN1_SLE,
56 RCAN1_RM0, RCAN1_RM1,
57 41
58 SSI0_SSII, SSI1_SSII, 42 SSI0_SSII, SSI1_SSII,
59 43
60 TMR0_CMIA0, TMR0_CMIB0, TMR0_OVI0, 44 TMR0, TMR1,
61 TMR1_CMIA1, TMR1_CMIB1, TMR1_OVI1,
62 45
63 /* interrupt groups */ 46 /* interrupt groups */
64 47 PINT,
65 IRQ, PINT, ADC,
66 MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
67 MTU23_ABCD, MTU24_ABCD, MTU25_UVW,
68 RTC, IIC30, IIC31, IIC32,
69 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
70 RCAN0, RCAN1, TMR0, TMR1
71
72}; 48};
73 49
74static struct intc_vect vectors[] __initdata = { 50static struct intc_vect vectors[] __initdata = {
@@ -76,6 +52,7 @@ static struct intc_vect vectors[] __initdata = {
76 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), 52 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
77 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), 53 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
78 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), 54 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
55
79 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), 56 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
80 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), 57 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
81 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), 58 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
@@ -83,123 +60,92 @@ static struct intc_vect vectors[] __initdata = {
83 60
84 INTC_IRQ(ADC_ADI, 92), 61 INTC_IRQ(ADC_ADI, 92),
85 62
86 INTC_IRQ(MTU2_TGI0A, 108), INTC_IRQ(MTU2_TGI0B, 109), 63 INTC_IRQ(MTU20_ABCD, 108), INTC_IRQ(MTU20_ABCD, 109),
87 INTC_IRQ(MTU2_TGI0C, 110), INTC_IRQ(MTU2_TGI0D, 111), 64 INTC_IRQ(MTU20_ABCD, 110), INTC_IRQ(MTU20_ABCD, 111),
88 INTC_IRQ(MTU2_TCI0V, 112), 65
89 INTC_IRQ(MTU2_TGI0E, 113), INTC_IRQ(MTU2_TGI0F, 114), 66 INTC_IRQ(MTU20_VEF, 112), INTC_IRQ(MTU20_VEF, 113),
67 INTC_IRQ(MTU20_VEF, 114),
68
69 INTC_IRQ(MTU21_AB, 116), INTC_IRQ(MTU21_AB, 117),
70 INTC_IRQ(MTU21_VU, 120), INTC_IRQ(MTU21_VU, 121),
90 71
91 INTC_IRQ(MTU2_TGI1A, 116), INTC_IRQ(MTU2_TGI1B, 117), 72 INTC_IRQ(MTU22_AB, 124), INTC_IRQ(MTU22_AB, 125),
92 INTC_IRQ(MTU2_TCI1V, 120), INTC_IRQ(MTU2_TCI1U, 121), 73 INTC_IRQ(MTU22_VU, 128), INTC_IRQ(MTU22_VU, 129),
93 74
94 INTC_IRQ(MTU2_TGI2A, 124), INTC_IRQ(MTU2_TGI2B, 125), 75 INTC_IRQ(MTU23_ABCD, 132), INTC_IRQ(MTU23_ABCD, 133),
95 INTC_IRQ(MTU2_TCI2V, 128), INTC_IRQ(MTU2_TCI2U, 129), 76 INTC_IRQ(MTU23_ABCD, 134), INTC_IRQ(MTU23_ABCD, 135),
96 77
97 INTC_IRQ(MTU2_TGI3A, 132), INTC_IRQ(MTU2_TGI3B, 133),
98 INTC_IRQ(MTU2_TGI3C, 134), INTC_IRQ(MTU2_TGI3D, 135),
99 INTC_IRQ(MTU2_TCI3V, 136), 78 INTC_IRQ(MTU2_TCI3V, 136),
100 79
101 INTC_IRQ(MTU2_TGI4A, 140), INTC_IRQ(MTU2_TGI4B, 141), 80 INTC_IRQ(MTU24_ABCD, 140), INTC_IRQ(MTU24_ABCD, 141),
102 INTC_IRQ(MTU2_TGI4C, 142), INTC_IRQ(MTU2_TGI4D, 143), 81 INTC_IRQ(MTU24_ABCD, 142), INTC_IRQ(MTU24_ABCD, 143),
82
103 INTC_IRQ(MTU2_TCI4V, 144), 83 INTC_IRQ(MTU2_TCI4V, 144),
104 84
105 INTC_IRQ(MTU2_TGI5U, 148), INTC_IRQ(MTU2_TGI5V, 149), 85 INTC_IRQ(MTU25_UVW, 148), INTC_IRQ(MTU25_UVW, 149),
106 INTC_IRQ(MTU2_TGI5W, 150), 86 INTC_IRQ(MTU25_UVW, 150),
87
88 INTC_IRQ(RTC, 152), INTC_IRQ(RTC, 153),
89 INTC_IRQ(RTC, 154),
107 90
108 INTC_IRQ(RTC_ARM, 152), INTC_IRQ(RTC_PRD, 153), 91 INTC_IRQ(WDT, 156),
109 INTC_IRQ(RTC_CUP, 154), INTC_IRQ(WDT, 156),
110 92
111 INTC_IRQ(IIC30_STPI, 157), INTC_IRQ(IIC30_NAKI, 158), 93 INTC_IRQ(IIC30, 157), INTC_IRQ(IIC30, 158),
112 INTC_IRQ(IIC30_RXI, 159), INTC_IRQ(IIC30_TXI, 160), 94 INTC_IRQ(IIC30, 159), INTC_IRQ(IIC30, 160),
113 INTC_IRQ(IIC30_TEI, 161), 95 INTC_IRQ(IIC30, 161),
114 96
115 INTC_IRQ(IIC31_STPI, 164), INTC_IRQ(IIC31_NAKI, 165), 97 INTC_IRQ(IIC31, 164), INTC_IRQ(IIC31, 165),
116 INTC_IRQ(IIC31_RXI, 166), INTC_IRQ(IIC31_TXI, 167), 98 INTC_IRQ(IIC31, 166), INTC_IRQ(IIC31, 167),
117 INTC_IRQ(IIC31_TEI, 168), 99 INTC_IRQ(IIC31, 168),
118 100
119 INTC_IRQ(IIC32_STPI, 170), INTC_IRQ(IIC32_NAKI, 171), 101 INTC_IRQ(IIC32, 170), INTC_IRQ(IIC32, 171),
120 INTC_IRQ(IIC32_RXI, 172), INTC_IRQ(IIC32_TXI, 173), 102 INTC_IRQ(IIC32, 172), INTC_IRQ(IIC32, 173),
121 INTC_IRQ(IIC32_TEI, 174), 103 INTC_IRQ(IIC32, 174),
122 104
123 INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177), 105 INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177),
124 INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179), 106 INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179),
125 107
126 INTC_IRQ(SCIF0_BRI, 180), INTC_IRQ(SCIF0_ERI, 181), 108 INTC_IRQ(SCIF0, 180), INTC_IRQ(SCIF0, 181),
127 INTC_IRQ(SCIF0_RXI, 182), INTC_IRQ(SCIF0_TXI, 183), 109 INTC_IRQ(SCIF0, 182), INTC_IRQ(SCIF0, 183),
128 INTC_IRQ(SCIF1_BRI, 184), INTC_IRQ(SCIF1_ERI, 185), 110 INTC_IRQ(SCIF1, 184), INTC_IRQ(SCIF1, 185),
129 INTC_IRQ(SCIF1_RXI, 186), INTC_IRQ(SCIF1_TXI, 187), 111 INTC_IRQ(SCIF1, 186), INTC_IRQ(SCIF1, 187),
130 INTC_IRQ(SCIF2_BRI, 188), INTC_IRQ(SCIF2_ERI, 189), 112 INTC_IRQ(SCIF2, 188), INTC_IRQ(SCIF2, 189),
131 INTC_IRQ(SCIF2_RXI, 190), INTC_IRQ(SCIF2_TXI, 191), 113 INTC_IRQ(SCIF2, 190), INTC_IRQ(SCIF2, 191),
132 INTC_IRQ(SCIF3_BRI, 192), INTC_IRQ(SCIF3_ERI, 193), 114 INTC_IRQ(SCIF3, 192), INTC_IRQ(SCIF3, 193),
133 INTC_IRQ(SCIF3_RXI, 194), INTC_IRQ(SCIF3_TXI, 195), 115 INTC_IRQ(SCIF3, 194), INTC_IRQ(SCIF3, 195),
134 INTC_IRQ(SCIF4_BRI, 196), INTC_IRQ(SCIF4_ERI, 197), 116 INTC_IRQ(SCIF4, 196), INTC_IRQ(SCIF4, 197),
135 INTC_IRQ(SCIF4_RXI, 198), INTC_IRQ(SCIF4_TXI, 199), 117 INTC_IRQ(SCIF4, 198), INTC_IRQ(SCIF4, 199),
136 INTC_IRQ(SCIF5_BRI, 200), INTC_IRQ(SCIF5_ERI, 201), 118 INTC_IRQ(SCIF5, 200), INTC_IRQ(SCIF5, 201),
137 INTC_IRQ(SCIF5_RXI, 202), INTC_IRQ(SCIF5_TXI, 203), 119 INTC_IRQ(SCIF5, 202), INTC_IRQ(SCIF5, 203),
138 INTC_IRQ(SCIF6_BRI, 204), INTC_IRQ(SCIF6_ERI, 205), 120 INTC_IRQ(SCIF6, 204), INTC_IRQ(SCIF6, 205),
139 INTC_IRQ(SCIF6_RXI, 206), INTC_IRQ(SCIF6_TXI, 207), 121 INTC_IRQ(SCIF6, 206), INTC_IRQ(SCIF6, 207),
140 INTC_IRQ(SCIF7_BRI, 208), INTC_IRQ(SCIF7_ERI, 209), 122 INTC_IRQ(SCIF7, 208), INTC_IRQ(SCIF7, 209),
141 INTC_IRQ(SCIF7_RXI, 210), INTC_IRQ(SCIF7_TXI, 211), 123 INTC_IRQ(SCIF7, 210), INTC_IRQ(SCIF7, 211),
142 124
143 INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216), 125 INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216),
144 INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218), 126 INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218),
145 INTC_IRQ(DMAC7_DMINT7, 219), 127 INTC_IRQ(DMAC7_DMINT7, 219),
146 128
147 INTC_IRQ(RCAN0_ERS, 228), INTC_IRQ(RCAN0_OVR, 229), 129 INTC_IRQ(RCAN0, 228), INTC_IRQ(RCAN0, 229),
148 INTC_IRQ(RCAN0_SLE, 230), 130 INTC_IRQ(RCAN0, 230),
149 INTC_IRQ(RCAN0_RM0, 231), INTC_IRQ(RCAN0_RM1, 232), 131 INTC_IRQ(RCAN0, 231), INTC_IRQ(RCAN0, 232),
150 132
151 INTC_IRQ(RCAN1_ERS, 234), INTC_IRQ(RCAN1_OVR, 235), 133 INTC_IRQ(RCAN1, 234), INTC_IRQ(RCAN1, 235),
152 INTC_IRQ(RCAN1_SLE, 236), 134 INTC_IRQ(RCAN1, 236),
153 INTC_IRQ(RCAN1_RM0, 237), INTC_IRQ(RCAN1_RM1, 238), 135 INTC_IRQ(RCAN1, 237), INTC_IRQ(RCAN1, 238),
154 136
155 INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245), 137 INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245),
156 138
157 INTC_IRQ(TMR0_CMIA0, 246), INTC_IRQ(TMR0_CMIB0, 247), 139 INTC_IRQ(TMR0, 246), INTC_IRQ(TMR0, 247),
158 INTC_IRQ(TMR0_OVI0, 248), 140 INTC_IRQ(TMR0, 248),
159
160 INTC_IRQ(TMR1_CMIA1, 252), INTC_IRQ(TMR1_CMIB1, 253),
161 INTC_IRQ(TMR1_OVI1, 254),
162 141
142 INTC_IRQ(TMR1, 252), INTC_IRQ(TMR1, 253),
143 INTC_IRQ(TMR1, 254),
163}; 144};
164 145
165static struct intc_group groups[] __initdata = { 146static struct intc_group groups[] __initdata = {
166 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, 147 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
167 PINT4, PINT5, PINT6, PINT7), 148 PINT4, PINT5, PINT6, PINT7),
168 INTC_GROUP(MTU20_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D),
169 INTC_GROUP(MTU20_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F),
170
171 INTC_GROUP(MTU21_AB, MTU2_TGI1A, MTU2_TGI1B),
172 INTC_GROUP(MTU21_VU, MTU2_TCI1V, MTU2_TCI1U),
173 INTC_GROUP(MTU22_AB, MTU2_TGI2A, MTU2_TGI2B),
174 INTC_GROUP(MTU22_VU, MTU2_TCI2V, MTU2_TCI2U),
175 INTC_GROUP(MTU23_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D),
176 INTC_GROUP(MTU24_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
177 INTC_GROUP(MTU25_UVW, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
178 INTC_GROUP(RTC, RTC_ARM, RTC_PRD, RTC_CUP ),
179
180 INTC_GROUP(IIC30, IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI,
181 IIC30_TEI),
182 INTC_GROUP(IIC31, IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI,
183 IIC31_TEI),
184 INTC_GROUP(IIC32, IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI,
185 IIC32_TEI),
186
187 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
188 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
189 INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
190 INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
191 INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
192 INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
193 INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
194 INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
195
196 INTC_GROUP(RCAN0, RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1,
197 RCAN0_SLE),
198 INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1,
199 RCAN1_SLE),
200
201 INTC_GROUP(TMR0, TMR0_CMIA0, TMR0_CMIB0, TMR0_OVI0),
202 INTC_GROUP(TMR1, TMR1_CMIA1, TMR1_CMIB1, TMR1_OVI1),
203}; 149};
204 150
205static struct intc_prio_reg prio_registers[] __initdata = { 151static struct intc_prio_reg prio_registers[] __initdata = {
@@ -212,7 +158,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
212 158
213 { 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } }, 159 { 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } },
214 { 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } }, 160 { 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } },
215 { 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0 , SCIF1 } }, 161 { 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0, SCIF1 } },
216 { 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } }, 162 { 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } },
217 { 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } }, 163 { 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } },
218 { 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } }, 164 { 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } },
@@ -234,42 +180,42 @@ static struct plat_sci_port sci_platform_data[] = {
234 .mapbase = 0xfffe8000, 180 .mapbase = 0xfffe8000,
235 .flags = UPF_BOOT_AUTOCONF, 181 .flags = UPF_BOOT_AUTOCONF,
236 .type = PORT_SCIF, 182 .type = PORT_SCIF,
237 .irqs = { 181, 182, 183, 180} 183 .irqs = { 180, 180, 180, 180 }
238 }, { 184 }, {
239 .mapbase = 0xfffe8800, 185 .mapbase = 0xfffe8800,
240 .flags = UPF_BOOT_AUTOCONF, 186 .flags = UPF_BOOT_AUTOCONF,
241 .type = PORT_SCIF, 187 .type = PORT_SCIF,
242 .irqs = { 185, 186, 187, 184} 188 .irqs = { 184, 184, 184, 184 }
243 }, { 189 }, {
244 .mapbase = 0xfffe9000, 190 .mapbase = 0xfffe9000,
245 .flags = UPF_BOOT_AUTOCONF, 191 .flags = UPF_BOOT_AUTOCONF,
246 .type = PORT_SCIF, 192 .type = PORT_SCIF,
247 .irqs = { 189, 186, 187, 188} 193 .irqs = { 188, 188, 188, 188 }
248 }, { 194 }, {
249 .mapbase = 0xfffe9800, 195 .mapbase = 0xfffe9800,
250 .flags = UPF_BOOT_AUTOCONF, 196 .flags = UPF_BOOT_AUTOCONF,
251 .type = PORT_SCIF, 197 .type = PORT_SCIF,
252 .irqs = { 193, 194, 195, 192} 198 .irqs = { 192, 192, 192, 192 }
253 }, { 199 }, {
254 .mapbase = 0xfffea000, 200 .mapbase = 0xfffea000,
255 .flags = UPF_BOOT_AUTOCONF, 201 .flags = UPF_BOOT_AUTOCONF,
256 .type = PORT_SCIF, 202 .type = PORT_SCIF,
257 .irqs = { 196, 198, 199, 196} 203 .irqs = { 196, 196, 196, 196 }
258 }, { 204 }, {
259 .mapbase = 0xfffea800, 205 .mapbase = 0xfffea800,
260 .flags = UPF_BOOT_AUTOCONF, 206 .flags = UPF_BOOT_AUTOCONF,
261 .type = PORT_SCIF, 207 .type = PORT_SCIF,
262 .irqs = { 201, 202, 203, 200} 208 .irqs = { 200, 200, 200, 200 }
263 }, { 209 }, {
264 .mapbase = 0xfffeb000, 210 .mapbase = 0xfffeb000,
265 .flags = UPF_BOOT_AUTOCONF, 211 .flags = UPF_BOOT_AUTOCONF,
266 .type = PORT_SCIF, 212 .type = PORT_SCIF,
267 .irqs = { 205, 206, 207, 204} 213 .irqs = { 204, 204, 204, 204 }
268 }, { 214 }, {
269 .mapbase = 0xfffeb800, 215 .mapbase = 0xfffeb800,
270 .flags = UPF_BOOT_AUTOCONF, 216 .flags = UPF_BOOT_AUTOCONF,
271 .type = PORT_SCIF, 217 .type = PORT_SCIF,
272 .irqs = { 209, 210, 211, 208} 218 .irqs = { 208, 208, 208, 208 }
273 }, { 219 }, {
274 .flags = 0, 220 .flags = 0,
275 } 221 }
@@ -290,17 +236,7 @@ static struct resource rtc_resources[] = {
290 .flags = IORESOURCE_IO, 236 .flags = IORESOURCE_IO,
291 }, 237 },
292 [1] = { 238 [1] = {
293 /* Period IRQ */ 239 /* Shared Period/Carry/Alarm IRQ */
294 .start = 153,
295 .flags = IORESOURCE_IRQ,
296 },
297 [2] = {
298 /* Carry IRQ */
299 .start = 154,
300 .flags = IORESOURCE_IRQ,
301 },
302 [3] = {
303 /* Alarm IRQ */
304 .start = 152, 240 .start = 152,
305 .flags = IORESOURCE_IRQ, 241 .flags = IORESOURCE_IRQ,
306 }, 242 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index e98dc4450352..820dfb2e8656 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH7203 and SH7263 Setup 2 * SH7203 and SH7263 Setup
3 * 3 *
4 * Copyright (C) 2007 Paul Mundt 4 * Copyright (C) 2007 - 2009 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
@@ -18,50 +18,27 @@ enum {
18 /* interrupt sources */ 18 /* interrupt sources */
19 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 19 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
20 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, 20 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
21 DMAC0_DEI, DMAC0_HEI, DMAC1_DEI, DMAC1_HEI, 21 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
22 DMAC2_DEI, DMAC2_HEI, DMAC3_DEI, DMAC3_HEI,
23 DMAC4_DEI, DMAC4_HEI, DMAC5_DEI, DMAC5_HEI,
24 DMAC6_DEI, DMAC6_HEI, DMAC7_DEI, DMAC7_HEI,
25 USB, LCDC, CMT0, CMT1, BSC, WDT, 22 USB, LCDC, CMT0, CMT1, BSC, WDT,
26 MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
27 MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
28 MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
29 MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
30 MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
31 MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
32 ADC_ADI,
33 IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, IIC30_TEI,
34 IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, IIC31_TEI,
35 IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, IIC32_TEI,
36 IIC33_STPI, IIC33_NAKI, IIC33_RXI, IIC33_TXI, IIC33_TEI,
37 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
38 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
39 SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
40 SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
41 SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI,
42 SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI,
43 SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,
44 23
45 /* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */ 24 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
46 ROMDEC_ISY, ROMDEC_IERR, ROMDEC_IARG, ROMDEC_ISEC, ROMDEC_IBUF, 25 MTU3_ABCD, MTU4_ABCD, MTU2_TCI3V, MTU2_TCI4V,
47 ROMDEC_IREADY,
48 26
49 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 27 ADC_ADI,
28
29 IIC30, IIC31, IIC32, IIC33,
30 SCIF0, SCIF1, SCIF2, SCIF3,
50 31
51 SDHI3, SDHI0, SDHI1, 32 SSU0, SSU1,
52 33
53 RTC_ARM, RTC_PRD, RTC_CUP, 34 SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,
54 RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1, RCAN0_SLE,
55 RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1, RCAN1_SLE,
56 35
57 SRC_OVF, SRC_ODFI, SRC_IDEI, IEBI, 36 /* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */
37 ROMDEC, FLCTL, SDHI, RTC, RCAN0, RCAN1,
38 SRC, IEBI,
58 39
59 /* interrupt groups */ 40 /* interrupt groups */
60 PINT, DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, 41 PINT,
61 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
62 MTU3_ABCD, MTU4_ABCD,
63 IIC30, IIC31, IIC32, IIC33, SCIF0, SCIF1, SCIF2, SCIF3,
64 SSU0, SSU1, ROMDEC, SDHI, FLCTL, RTC, RCAN0, RCAN1, SRC
65}; 42};
66 43
67static struct intc_vect vectors[] __initdata = { 44static struct intc_vect vectors[] __initdata = {
@@ -73,79 +50,80 @@ static struct intc_vect vectors[] __initdata = {
73 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), 50 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
74 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), 51 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
75 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), 52 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
76 INTC_IRQ(DMAC0_DEI, 108), INTC_IRQ(DMAC0_HEI, 109), 53 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
77 INTC_IRQ(DMAC1_DEI, 112), INTC_IRQ(DMAC1_HEI, 113), 54 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
78 INTC_IRQ(DMAC2_DEI, 116), INTC_IRQ(DMAC2_HEI, 117), 55 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
79 INTC_IRQ(DMAC3_DEI, 120), INTC_IRQ(DMAC3_HEI, 121), 56 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
80 INTC_IRQ(DMAC4_DEI, 124), INTC_IRQ(DMAC4_HEI, 125), 57 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
81 INTC_IRQ(DMAC5_DEI, 128), INTC_IRQ(DMAC5_HEI, 129), 58 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
82 INTC_IRQ(DMAC6_DEI, 132), INTC_IRQ(DMAC6_HEI, 133), 59 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
83 INTC_IRQ(DMAC7_DEI, 136), INTC_IRQ(DMAC7_HEI, 137), 60 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
84 INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141), 61 INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
85 INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143), 62 INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143),
86 INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145), 63 INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
87 INTC_IRQ(MTU2_TGI0A, 146), INTC_IRQ(MTU2_TGI0B, 147), 64 INTC_IRQ(MTU0_ABCD, 146), INTC_IRQ(MTU0_ABCD, 147),
88 INTC_IRQ(MTU2_TGI0C, 148), INTC_IRQ(MTU2_TGI0D, 149), 65 INTC_IRQ(MTU0_ABCD, 148), INTC_IRQ(MTU0_ABCD, 149),
89 INTC_IRQ(MTU2_TCI0V, 150), 66 INTC_IRQ(MTU0_VEF, 150),
90 INTC_IRQ(MTU2_TGI0E, 151), INTC_IRQ(MTU2_TGI0F, 152), 67 INTC_IRQ(MTU0_VEF, 151), INTC_IRQ(MTU0_VEF, 152),
91 INTC_IRQ(MTU2_TGI1A, 153), INTC_IRQ(MTU2_TGI1B, 154), 68 INTC_IRQ(MTU1_AB, 153), INTC_IRQ(MTU1_AB, 154),
92 INTC_IRQ(MTU2_TCI1V, 155), INTC_IRQ(MTU2_TCI1U, 156), 69 INTC_IRQ(MTU1_VU, 155), INTC_IRQ(MTU1_VU, 156),
93 INTC_IRQ(MTU2_TGI2A, 157), INTC_IRQ(MTU2_TGI2B, 158), 70 INTC_IRQ(MTU2_AB, 157), INTC_IRQ(MTU2_AB, 158),
94 INTC_IRQ(MTU2_TCI2V, 159), INTC_IRQ(MTU2_TCI2U, 160), 71 INTC_IRQ(MTU2_VU, 159), INTC_IRQ(MTU2_VU, 160),
95 INTC_IRQ(MTU2_TGI3A, 161), INTC_IRQ(MTU2_TGI3B, 162), 72 INTC_IRQ(MTU3_ABCD, 161), INTC_IRQ(MTU3_ABCD, 162),
96 INTC_IRQ(MTU2_TGI3C, 163), INTC_IRQ(MTU2_TGI3D, 164), 73 INTC_IRQ(MTU3_ABCD, 163), INTC_IRQ(MTU3_ABCD, 164),
97 INTC_IRQ(MTU2_TCI3V, 165), 74 INTC_IRQ(MTU2_TCI3V, 165),
98 INTC_IRQ(MTU2_TGI4A, 166), INTC_IRQ(MTU2_TGI4B, 167), 75 INTC_IRQ(MTU4_ABCD, 166), INTC_IRQ(MTU4_ABCD, 167),
99 INTC_IRQ(MTU2_TGI4C, 168), INTC_IRQ(MTU2_TGI4D, 169), 76 INTC_IRQ(MTU4_ABCD, 168), INTC_IRQ(MTU4_ABCD, 169),
100 INTC_IRQ(MTU2_TCI4V, 170), 77 INTC_IRQ(MTU2_TCI4V, 170),
101 INTC_IRQ(ADC_ADI, 171), 78 INTC_IRQ(ADC_ADI, 171),
102 INTC_IRQ(IIC30_STPI, 172), INTC_IRQ(IIC30_NAKI, 173), 79 INTC_IRQ(IIC30, 172), INTC_IRQ(IIC30, 173),
103 INTC_IRQ(IIC30_RXI, 174), INTC_IRQ(IIC30_TXI, 175), 80 INTC_IRQ(IIC30, 174), INTC_IRQ(IIC30, 175),
104 INTC_IRQ(IIC30_TEI, 176), 81 INTC_IRQ(IIC30, 176),
105 INTC_IRQ(IIC31_STPI, 177), INTC_IRQ(IIC31_NAKI, 178), 82 INTC_IRQ(IIC31, 177), INTC_IRQ(IIC31, 178),
106 INTC_IRQ(IIC31_RXI, 179), INTC_IRQ(IIC31_TXI, 180), 83 INTC_IRQ(IIC31, 179), INTC_IRQ(IIC31, 180),
107 INTC_IRQ(IIC31_TEI, 181), 84 INTC_IRQ(IIC31, 181),
108 INTC_IRQ(IIC32_STPI, 182), INTC_IRQ(IIC32_NAKI, 183), 85 INTC_IRQ(IIC32, 182), INTC_IRQ(IIC32, 183),
109 INTC_IRQ(IIC32_RXI, 184), INTC_IRQ(IIC32_TXI, 185), 86 INTC_IRQ(IIC32, 184), INTC_IRQ(IIC32, 185),
110 INTC_IRQ(IIC32_TEI, 186), 87 INTC_IRQ(IIC32, 186),
111 INTC_IRQ(IIC33_STPI, 187), INTC_IRQ(IIC33_NAKI, 188), 88 INTC_IRQ(IIC33, 187), INTC_IRQ(IIC33, 188),
112 INTC_IRQ(IIC33_RXI, 189), INTC_IRQ(IIC33_TXI, 190), 89 INTC_IRQ(IIC33, 189), INTC_IRQ(IIC33, 190),
113 INTC_IRQ(IIC33_TEI, 191), 90 INTC_IRQ(IIC33, 191),
114 INTC_IRQ(SCIF0_BRI, 192), INTC_IRQ(SCIF0_ERI, 193), 91 INTC_IRQ(SCIF0, 192), INTC_IRQ(SCIF0, 193),
115 INTC_IRQ(SCIF0_RXI, 194), INTC_IRQ(SCIF0_TXI, 195), 92 INTC_IRQ(SCIF0, 194), INTC_IRQ(SCIF0, 195),
116 INTC_IRQ(SCIF1_BRI, 196), INTC_IRQ(SCIF1_ERI, 197), 93 INTC_IRQ(SCIF1, 196), INTC_IRQ(SCIF1, 197),
117 INTC_IRQ(SCIF1_RXI, 198), INTC_IRQ(SCIF1_TXI, 199), 94 INTC_IRQ(SCIF1, 198), INTC_IRQ(SCIF1, 199),
118 INTC_IRQ(SCIF2_BRI, 200), INTC_IRQ(SCIF2_ERI, 201), 95 INTC_IRQ(SCIF2, 200), INTC_IRQ(SCIF2, 201),
119 INTC_IRQ(SCIF2_RXI, 202), INTC_IRQ(SCIF2_TXI, 203), 96 INTC_IRQ(SCIF2, 202), INTC_IRQ(SCIF2, 203),
120 INTC_IRQ(SCIF3_BRI, 204), INTC_IRQ(SCIF3_ERI, 205), 97 INTC_IRQ(SCIF3, 204), INTC_IRQ(SCIF3, 205),
121 INTC_IRQ(SCIF3_RXI, 206), INTC_IRQ(SCIF3_TXI, 207), 98 INTC_IRQ(SCIF3, 206), INTC_IRQ(SCIF3, 207),
122 INTC_IRQ(SSU0_SSERI, 208), INTC_IRQ(SSU0_SSRXI, 209), 99 INTC_IRQ(SSU0, 208), INTC_IRQ(SSU0, 209),
123 INTC_IRQ(SSU0_SSTXI, 210), 100 INTC_IRQ(SSU0, 210),
124 INTC_IRQ(SSU1_SSERI, 211), INTC_IRQ(SSU1_SSRXI, 212), 101 INTC_IRQ(SSU1, 211), INTC_IRQ(SSU1, 212),
125 INTC_IRQ(SSU1_SSTXI, 213), 102 INTC_IRQ(SSU1, 213),
126 INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215), 103 INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215),
127 INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217), 104 INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217),
128 INTC_IRQ(FLCTL_FLSTEI, 224), INTC_IRQ(FLCTL_FLTENDI, 225), 105 INTC_IRQ(FLCTL, 224), INTC_IRQ(FLCTL, 225),
129 INTC_IRQ(FLCTL_FLTREQ0I, 226), INTC_IRQ(FLCTL_FLTREQ1I, 227), 106 INTC_IRQ(FLCTL, 226), INTC_IRQ(FLCTL, 227),
130 INTC_IRQ(RTC_ARM, 231), INTC_IRQ(RTC_PRD, 232), 107 INTC_IRQ(RTC, 231), INTC_IRQ(RTC, 232),
131 INTC_IRQ(RTC_CUP, 233), 108 INTC_IRQ(RTC, 233),
132 INTC_IRQ(RCAN0_ERS, 234), INTC_IRQ(RCAN0_OVR, 235), 109 INTC_IRQ(RCAN0, 234), INTC_IRQ(RCAN0, 235),
133 INTC_IRQ(RCAN0_RM0, 236), INTC_IRQ(RCAN0_RM1, 237), 110 INTC_IRQ(RCAN0, 236), INTC_IRQ(RCAN0, 237),
134 INTC_IRQ(RCAN0_SLE, 238), 111 INTC_IRQ(RCAN0, 238),
135 INTC_IRQ(RCAN1_ERS, 239), INTC_IRQ(RCAN1_OVR, 240), 112 INTC_IRQ(RCAN1, 239), INTC_IRQ(RCAN1, 240),
136 INTC_IRQ(RCAN1_RM0, 241), INTC_IRQ(RCAN1_RM1, 242), 113 INTC_IRQ(RCAN1, 241), INTC_IRQ(RCAN1, 242),
137 INTC_IRQ(RCAN1_SLE, 243), 114 INTC_IRQ(RCAN1, 243),
138 115
139 /* SH7263-specific trash */ 116 /* SH7263-specific trash */
140#ifdef CONFIG_CPU_SUBTYPE_SH7263 117#ifdef CONFIG_CPU_SUBTYPE_SH7263
141 INTC_IRQ(ROMDEC_ISY, 218), INTC_IRQ(ROMDEC_IERR, 219), 118 INTC_IRQ(ROMDEC, 218), INTC_IRQ(ROMDEC, 219),
142 INTC_IRQ(ROMDEC_IARG, 220), INTC_IRQ(ROMDEC_ISEC, 221), 119 INTC_IRQ(ROMDEC, 220), INTC_IRQ(ROMDEC, 221),
143 INTC_IRQ(ROMDEC_IBUF, 222), INTC_IRQ(ROMDEC_IREADY, 223), 120 INTC_IRQ(ROMDEC, 222), INTC_IRQ(ROMDEC, 223),
144 121
145 INTC_IRQ(SDHI3, 228), INTC_IRQ(SDHI0, 229), INTC_IRQ(SDHI1, 230), 122 INTC_IRQ(SDHI, 228), INTC_IRQ(SDHI, 229),
123 INTC_IRQ(SDHI, 230),
146 124
147 INTC_IRQ(SRC_OVF, 244), INTC_IRQ(SRC_ODFI, 245), 125 INTC_IRQ(SRC, 244), INTC_IRQ(SRC, 245),
148 INTC_IRQ(SRC_IDEI, 246), 126 INTC_IRQ(SRC, 246),
149 127
150 INTC_IRQ(IEBI, 247), 128 INTC_IRQ(IEBI, 247),
151#endif 129#endif
@@ -154,50 +132,6 @@ static struct intc_vect vectors[] __initdata = {
154static struct intc_group groups[] __initdata = { 132static struct intc_group groups[] __initdata = {
155 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, 133 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
156 PINT4, PINT5, PINT6, PINT7), 134 PINT4, PINT5, PINT6, PINT7),
157 INTC_GROUP(DMAC0, DMAC0_DEI, DMAC0_HEI),
158 INTC_GROUP(DMAC1, DMAC1_DEI, DMAC1_HEI),
159 INTC_GROUP(DMAC2, DMAC2_DEI, DMAC2_HEI),
160 INTC_GROUP(DMAC3, DMAC3_DEI, DMAC3_HEI),
161 INTC_GROUP(DMAC4, DMAC4_DEI, DMAC4_HEI),
162 INTC_GROUP(DMAC5, DMAC5_DEI, DMAC5_HEI),
163 INTC_GROUP(DMAC6, DMAC6_DEI, DMAC6_HEI),
164 INTC_GROUP(DMAC7, DMAC7_DEI, DMAC7_HEI),
165 INTC_GROUP(MTU0_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D),
166 INTC_GROUP(MTU0_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F),
167 INTC_GROUP(MTU1_AB, MTU2_TGI1A, MTU2_TGI1B),
168 INTC_GROUP(MTU1_VU, MTU2_TCI1V, MTU2_TCI1U),
169 INTC_GROUP(MTU2_AB, MTU2_TGI2A, MTU2_TGI2B),
170 INTC_GROUP(MTU2_VU, MTU2_TCI2V, MTU2_TCI2U),
171 INTC_GROUP(MTU3_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D),
172 INTC_GROUP(MTU4_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
173 INTC_GROUP(IIC30, IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI,
174 IIC30_TEI),
175 INTC_GROUP(IIC31, IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI,
176 IIC31_TEI),
177 INTC_GROUP(IIC32, IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI,
178 IIC32_TEI),
179 INTC_GROUP(IIC33, IIC33_STPI, IIC33_NAKI, IIC33_RXI, IIC33_TXI,
180 IIC33_TEI),
181 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
182 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
183 INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
184 INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
185 INTC_GROUP(SSU0, SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI),
186 INTC_GROUP(SSU1, SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI),
187 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I,
188 FLCTL_FLTREQ1I),
189 INTC_GROUP(RTC, RTC_ARM, RTC_PRD, RTC_CUP),
190 INTC_GROUP(RCAN0, RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1,
191 RCAN0_SLE),
192 INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1,
193 RCAN1_SLE),
194
195#ifdef CONFIG_CPU_SUBTYPE_SH7263
196 INTC_GROUP(ROMDEC, ROMDEC_ISY, ROMDEC_IERR, ROMDEC_IARG,
197 ROMDEC_ISEC, ROMDEC_IBUF, ROMDEC_IREADY),
198 INTC_GROUP(SDHI, SDHI3, SDHI0, SDHI1),
199 INTC_GROUP(SRC, SRC_OVF, SRC_ODFI, SRC_IDEI),
200#endif
201}; 135};
202 136
203static struct intc_prio_reg prio_registers[] __initdata = { 137static struct intc_prio_reg prio_registers[] __initdata = {
@@ -242,22 +176,22 @@ static struct plat_sci_port sci_platform_data[] = {
242 .mapbase = 0xfffe8000, 176 .mapbase = 0xfffe8000,
243 .flags = UPF_BOOT_AUTOCONF, 177 .flags = UPF_BOOT_AUTOCONF,
244 .type = PORT_SCIF, 178 .type = PORT_SCIF,
245 .irqs = { 193, 194, 195, 192 }, 179 .irqs = { 192, 192, 192, 192 },
246 }, { 180 }, {
247 .mapbase = 0xfffe8800, 181 .mapbase = 0xfffe8800,
248 .flags = UPF_BOOT_AUTOCONF, 182 .flags = UPF_BOOT_AUTOCONF,
249 .type = PORT_SCIF, 183 .type = PORT_SCIF,
250 .irqs = { 197, 198, 199, 196 }, 184 .irqs = { 196, 196, 196, 196 },
251 }, { 185 }, {
252 .mapbase = 0xfffe9000, 186 .mapbase = 0xfffe9000,
253 .flags = UPF_BOOT_AUTOCONF, 187 .flags = UPF_BOOT_AUTOCONF,
254 .type = PORT_SCIF, 188 .type = PORT_SCIF,
255 .irqs = { 201, 202, 203, 200 }, 189 .irqs = { 200, 200, 200, 200 },
256 }, { 190 }, {
257 .mapbase = 0xfffe9800, 191 .mapbase = 0xfffe9800,
258 .flags = UPF_BOOT_AUTOCONF, 192 .flags = UPF_BOOT_AUTOCONF,
259 .type = PORT_SCIF, 193 .type = PORT_SCIF,
260 .irqs = { 205, 206, 207, 204 }, 194 .irqs = { 204, 204, 204, 204 },
261 }, { 195 }, {
262 .flags = 0, 196 .flags = 0,
263 } 197 }
@@ -278,17 +212,7 @@ static struct resource rtc_resources[] = {
278 .flags = IORESOURCE_IO, 212 .flags = IORESOURCE_IO,
279 }, 213 },
280 [1] = { 214 [1] = {
281 /* Period IRQ */ 215 /* Shared Period/Carry/Alarm IRQ */
282 .start = 232,
283 .flags = IORESOURCE_IRQ,
284 },
285 [2] = {
286 /* Carry IRQ */
287 .start = 233,
288 .flags = IORESOURCE_IRQ,
289 },
290 [3] = {
291 /* Alarm IRQ */
292 .start = 231, 216 .start = 231,
293 .flags = IORESOURCE_IRQ, 217 .flags = IORESOURCE_IRQ,
294 }, 218 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index e6d4ec445dd8..c46a8355726d 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -2,6 +2,7 @@
2 * SH7206 Setup 2 * SH7206 Setup
3 * 3 *
4 * Copyright (C) 2006 Yoshinori Sato 4 * Copyright (C) 2006 Yoshinori Sato
5 * Copyright (C) 2009 Paul Mundt
5 * 6 *
6 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
@@ -19,34 +20,23 @@ enum {
19 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 20 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
20 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, 21 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
21 ADC_ADI0, ADC_ADI1, 22 ADC_ADI0, ADC_ADI1,
22 DMAC0_DEI, DMAC0_HEI, DMAC1_DEI, DMAC1_HEI, 23
23 DMAC2_DEI, DMAC2_HEI, DMAC3_DEI, DMAC3_HEI, 24 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
24 DMAC4_DEI, DMAC4_HEI, DMAC5_DEI, DMAC5_HEI, 25
25 DMAC6_DEI, DMAC6_HEI, DMAC7_DEI, DMAC7_HEI, 26 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
27 MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S,
28 IIC3,
29
26 CMT0, CMT1, BSC, WDT, 30 CMT0, CMT1, BSC, WDT,
27 MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D, 31
28 MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F, 32 MTU2_TCI3V, MTU2_TCI4V, MTU2S_TCI3V, MTU2S_TCI4V,
29 MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U, 33
30 MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
31 MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
32 MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
33 MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W,
34 POE2_OEI1, POE2_OEI2,
35 MTU2S_TGI3A, MTU2S_TGI3B, MTU2S_TGI3C, MTU2S_TGI3D, MTU2S_TCI3V,
36 MTU2S_TGI4A, MTU2S_TGI4B, MTU2S_TGI4C, MTU2S_TGI4D, MTU2S_TCI4V,
37 MTU2S_TGI5U, MTU2S_TGI5V, MTU2S_TGI5W,
38 POE2_OEI3, 34 POE2_OEI3,
39 IIC3_STPI, IIC3_NAKI, IIC3_RXI, IIC3_TXI, IIC3_TEI, 35
40 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, 36 SCIF0, SCIF1, SCIF2, SCIF3,
41 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
42 SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
43 SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
44 37
45 /* interrupt groups */ 38 /* interrupt groups */
46 PINT, DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, 39 PINT,
47 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
48 MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S,
49 IIC3, SCIF0, SCIF1, SCIF2, SCIF3,
50}; 40};
51 41
52static struct intc_vect vectors[] __initdata = { 42static struct intc_vect vectors[] __initdata = {
@@ -59,86 +49,58 @@ static struct intc_vect vectors[] __initdata = {
59 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), 49 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
60 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), 50 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
61 INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96), 51 INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96),
62 INTC_IRQ(DMAC0_DEI, 108), INTC_IRQ(DMAC0_HEI, 109), 52 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
63 INTC_IRQ(DMAC1_DEI, 112), INTC_IRQ(DMAC1_HEI, 113), 53 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
64 INTC_IRQ(DMAC2_DEI, 116), INTC_IRQ(DMAC2_HEI, 117), 54 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
65 INTC_IRQ(DMAC3_DEI, 120), INTC_IRQ(DMAC3_HEI, 121), 55 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
66 INTC_IRQ(DMAC4_DEI, 124), INTC_IRQ(DMAC4_HEI, 125), 56 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
67 INTC_IRQ(DMAC5_DEI, 128), INTC_IRQ(DMAC5_HEI, 129), 57 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
68 INTC_IRQ(DMAC6_DEI, 132), INTC_IRQ(DMAC6_HEI, 133), 58 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
69 INTC_IRQ(DMAC7_DEI, 136), INTC_IRQ(DMAC7_HEI, 137), 59 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
70 INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144), 60 INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144),
71 INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152), 61 INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
72 INTC_IRQ(MTU2_TGI0A, 156), INTC_IRQ(MTU2_TGI0B, 157), 62 INTC_IRQ(MTU0_ABCD, 156), INTC_IRQ(MTU0_ABCD, 157),
73 INTC_IRQ(MTU2_TGI0C, 158), INTC_IRQ(MTU2_TGI0D, 159), 63 INTC_IRQ(MTU0_ABCD, 158), INTC_IRQ(MTU0_ABCD, 159),
74 INTC_IRQ(MTU2_TCI0V, 160), 64 INTC_IRQ(MTU0_VEF, 160), INTC_IRQ(MTU0_VEF, 161),
75 INTC_IRQ(MTU2_TGI0E, 161), INTC_IRQ(MTU2_TGI0F, 162), 65 INTC_IRQ(MTU0_VEF, 162),
76 INTC_IRQ(MTU2_TGI1A, 164), INTC_IRQ(MTU2_TGI1B, 165), 66 INTC_IRQ(MTU1_AB, 164), INTC_IRQ(MTU1_AB, 165),
77 INTC_IRQ(MTU2_TCI1V, 168), INTC_IRQ(MTU2_TCI1U, 169), 67 INTC_IRQ(MTU1_VU, 168), INTC_IRQ(MTU1_VU, 169),
78 INTC_IRQ(MTU2_TGI2A, 172), INTC_IRQ(MTU2_TGI2B, 173), 68 INTC_IRQ(MTU2_AB, 172), INTC_IRQ(MTU2_AB, 173),
79 INTC_IRQ(MTU2_TCI2V, 176), INTC_IRQ(MTU2_TCI2U, 177), 69 INTC_IRQ(MTU2_VU, 176), INTC_IRQ(MTU2_VU, 177),
80 INTC_IRQ(MTU2_TGI3A, 180), INTC_IRQ(MTU2_TGI3B, 181), 70 INTC_IRQ(MTU3_ABCD, 180), INTC_IRQ(MTU3_ABCD, 181),
81 INTC_IRQ(MTU2_TGI3C, 182), INTC_IRQ(MTU2_TGI3D, 183), 71 INTC_IRQ(MTU3_ABCD, 182), INTC_IRQ(MTU3_ABCD, 183),
82 INTC_IRQ(MTU2_TCI3V, 184), 72 INTC_IRQ(MTU2_TCI3V, 184),
83 INTC_IRQ(MTU2_TGI4A, 188), INTC_IRQ(MTU2_TGI4B, 189), 73 INTC_IRQ(MTU4_ABCD, 188), INTC_IRQ(MTU4_ABCD, 189),
84 INTC_IRQ(MTU2_TGI4C, 190), INTC_IRQ(MTU2_TGI4D, 191), 74 INTC_IRQ(MTU4_ABCD, 190), INTC_IRQ(MTU4_ABCD, 191),
85 INTC_IRQ(MTU2_TCI4V, 192), 75 INTC_IRQ(MTU2_TCI4V, 192),
86 INTC_IRQ(MTU2_TGI5U, 196), INTC_IRQ(MTU2_TGI5V, 197), 76 INTC_IRQ(MTU5, 196), INTC_IRQ(MTU5, 197),
87 INTC_IRQ(MTU2_TGI5W, 198), 77 INTC_IRQ(MTU5, 198),
88 INTC_IRQ(POE2_OEI1, 200), INTC_IRQ(POE2_OEI2, 201), 78 INTC_IRQ(POE2_12, 200), INTC_IRQ(POE2_12, 201),
89 INTC_IRQ(MTU2S_TGI3A, 204), INTC_IRQ(MTU2S_TGI3B, 205), 79 INTC_IRQ(MTU3S_ABCD, 204), INTC_IRQ(MTU3S_ABCD, 205),
90 INTC_IRQ(MTU2S_TGI3C, 206), INTC_IRQ(MTU2S_TGI3D, 207), 80 INTC_IRQ(MTU3S_ABCD, 206), INTC_IRQ(MTU3S_ABCD, 207),
91 INTC_IRQ(MTU2S_TCI3V, 208), 81 INTC_IRQ(MTU2S_TCI3V, 208),
92 INTC_IRQ(MTU2S_TGI4A, 212), INTC_IRQ(MTU2S_TGI4B, 213), 82 INTC_IRQ(MTU4S_ABCD, 212), INTC_IRQ(MTU4S_ABCD, 213),
93 INTC_IRQ(MTU2S_TGI4C, 214), INTC_IRQ(MTU2S_TGI4D, 215), 83 INTC_IRQ(MTU4S_ABCD, 214), INTC_IRQ(MTU4S_ABCD, 215),
94 INTC_IRQ(MTU2S_TCI4V, 216), 84 INTC_IRQ(MTU2S_TCI4V, 216),
95 INTC_IRQ(MTU2S_TGI5U, 220), INTC_IRQ(MTU2S_TGI5V, 221), 85 INTC_IRQ(MTU5S, 220), INTC_IRQ(MTU5S, 221),
96 INTC_IRQ(MTU2S_TGI5W, 222), 86 INTC_IRQ(MTU5S, 222),
97 INTC_IRQ(POE2_OEI3, 224), 87 INTC_IRQ(POE2_OEI3, 224),
98 INTC_IRQ(IIC3_STPI, 228), INTC_IRQ(IIC3_NAKI, 229), 88 INTC_IRQ(IIC3, 228), INTC_IRQ(IIC3, 229),
99 INTC_IRQ(IIC3_RXI, 230), INTC_IRQ(IIC3_TXI, 231), 89 INTC_IRQ(IIC3, 230), INTC_IRQ(IIC3, 231),
100 INTC_IRQ(IIC3_TEI, 232), 90 INTC_IRQ(IIC3, 232),
101 INTC_IRQ(SCIF0_BRI, 240), INTC_IRQ(SCIF0_ERI, 241), 91 INTC_IRQ(SCIF0, 240), INTC_IRQ(SCIF0, 241),
102 INTC_IRQ(SCIF0_RXI, 242), INTC_IRQ(SCIF0_TXI, 243), 92 INTC_IRQ(SCIF0, 242), INTC_IRQ(SCIF0, 243),
103 INTC_IRQ(SCIF1_BRI, 244), INTC_IRQ(SCIF1_ERI, 245), 93 INTC_IRQ(SCIF1, 244), INTC_IRQ(SCIF1, 245),
104 INTC_IRQ(SCIF1_RXI, 246), INTC_IRQ(SCIF1_TXI, 247), 94 INTC_IRQ(SCIF1, 246), INTC_IRQ(SCIF1, 247),
105 INTC_IRQ(SCIF2_BRI, 248), INTC_IRQ(SCIF2_ERI, 249), 95 INTC_IRQ(SCIF2, 248), INTC_IRQ(SCIF2, 249),
106 INTC_IRQ(SCIF2_RXI, 250), INTC_IRQ(SCIF2_TXI, 251), 96 INTC_IRQ(SCIF2, 250), INTC_IRQ(SCIF2, 251),
107 INTC_IRQ(SCIF3_BRI, 252), INTC_IRQ(SCIF3_ERI, 253), 97 INTC_IRQ(SCIF3, 252), INTC_IRQ(SCIF3, 253),
108 INTC_IRQ(SCIF3_RXI, 254), INTC_IRQ(SCIF3_TXI, 255), 98 INTC_IRQ(SCIF3, 254), INTC_IRQ(SCIF3, 255),
109}; 99};
110 100
111static struct intc_group groups[] __initdata = { 101static struct intc_group groups[] __initdata = {
112 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, 102 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
113 PINT4, PINT5, PINT6, PINT7), 103 PINT4, PINT5, PINT6, PINT7),
114 INTC_GROUP(DMAC0, DMAC0_DEI, DMAC0_HEI),
115 INTC_GROUP(DMAC1, DMAC1_DEI, DMAC1_HEI),
116 INTC_GROUP(DMAC2, DMAC2_DEI, DMAC2_HEI),
117 INTC_GROUP(DMAC3, DMAC3_DEI, DMAC3_HEI),
118 INTC_GROUP(DMAC4, DMAC4_DEI, DMAC4_HEI),
119 INTC_GROUP(DMAC5, DMAC5_DEI, DMAC5_HEI),
120 INTC_GROUP(DMAC6, DMAC6_DEI, DMAC6_HEI),
121 INTC_GROUP(DMAC7, DMAC7_DEI, DMAC7_HEI),
122 INTC_GROUP(MTU0_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D),
123 INTC_GROUP(MTU0_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F),
124 INTC_GROUP(MTU1_AB, MTU2_TGI1A, MTU2_TGI1B),
125 INTC_GROUP(MTU1_VU, MTU2_TCI1V, MTU2_TCI1U),
126 INTC_GROUP(MTU2_AB, MTU2_TGI2A, MTU2_TGI2B),
127 INTC_GROUP(MTU2_VU, MTU2_TCI2V, MTU2_TCI2U),
128 INTC_GROUP(MTU3_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D),
129 INTC_GROUP(MTU4_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
130 INTC_GROUP(MTU5, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
131 INTC_GROUP(POE2_12, POE2_OEI1, POE2_OEI2),
132 INTC_GROUP(MTU3S_ABCD, MTU2S_TGI3A, MTU2S_TGI3B,
133 MTU2S_TGI3C, MTU2S_TGI3D),
134 INTC_GROUP(MTU4S_ABCD, MTU2S_TGI4A, MTU2S_TGI4B,
135 MTU2S_TGI4C, MTU2S_TGI4D),
136 INTC_GROUP(MTU5S, MTU2S_TGI5U, MTU2S_TGI5V, MTU2S_TGI5W),
137 INTC_GROUP(IIC3, IIC3_STPI, IIC3_NAKI, IIC3_RXI, IIC3_TXI, IIC3_TEI),
138 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
139 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
140 INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
141 INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
142}; 104};
143 105
144static struct intc_prio_reg prio_registers[] __initdata = { 106static struct intc_prio_reg prio_registers[] __initdata = {
@@ -174,22 +136,22 @@ static struct plat_sci_port sci_platform_data[] = {
174 .mapbase = 0xfffe8000, 136 .mapbase = 0xfffe8000,
175 .flags = UPF_BOOT_AUTOCONF, 137 .flags = UPF_BOOT_AUTOCONF,
176 .type = PORT_SCIF, 138 .type = PORT_SCIF,
177 .irqs = { 241, 242, 243, 240 }, 139 .irqs = { 240, 240, 240, 240 },
178 }, { 140 }, {
179 .mapbase = 0xfffe8800, 141 .mapbase = 0xfffe8800,
180 .flags = UPF_BOOT_AUTOCONF, 142 .flags = UPF_BOOT_AUTOCONF,
181 .type = PORT_SCIF, 143 .type = PORT_SCIF,
182 .irqs = { 245, 246, 247, 244 }, 144 .irqs = { 244, 244, 244, 244 },
183 }, { 145 }, {
184 .mapbase = 0xfffe9000, 146 .mapbase = 0xfffe9000,
185 .flags = UPF_BOOT_AUTOCONF, 147 .flags = UPF_BOOT_AUTOCONF,
186 .type = PORT_SCIF, 148 .type = PORT_SCIF,
187 .irqs = { 249, 250, 251, 248 }, 149 .irqs = { 248, 248, 248, 248 },
188 }, { 150 }, {
189 .mapbase = 0xfffe9800, 151 .mapbase = 0xfffe9800,
190 .flags = UPF_BOOT_AUTOCONF, 152 .flags = UPF_BOOT_AUTOCONF,
191 .type = PORT_SCIF, 153 .type = PORT_SCIF,
192 .irqs = { 253, 254, 255, 252 }, 154 .irqs = { 252, 252, 252, 252 },
193 }, { 155 }, {
194 .flags = 0, 156 .flags = 0,
195 } 157 }
diff --git a/arch/sh/kernel/cpu/sh3/Makefile b/arch/sh/kernel/cpu/sh3/Makefile
index e07c69e16d9b..ecab274141a8 100644
--- a/arch/sh/kernel/cpu/sh3/Makefile
+++ b/arch/sh/kernel/cpu/sh3/Makefile
@@ -4,6 +4,8 @@
4 4
5obj-y := ex.o probe.o entry.o setup-sh3.o 5obj-y := ex.o probe.o entry.o setup-sh3.o
6 6
7obj-$(CONFIG_HIBERNATION) += swsusp.o
8
7# CPU subtype setup 9# CPU subtype setup
8obj-$(CONFIG_CPU_SUBTYPE_SH7705) += setup-sh7705.o 10obj-$(CONFIG_CPU_SUBTYPE_SH7705) += setup-sh7705.o
9obj-$(CONFIG_CPU_SUBTYPE_SH7706) += setup-sh770x.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7706) += setup-sh770x.o
diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S
index b4106d0c68ec..55da0ff9848d 100644
--- a/arch/sh/kernel/cpu/sh3/entry.S
+++ b/arch/sh/kernel/cpu/sh3/entry.S
@@ -16,6 +16,7 @@
16#include <asm/unistd.h> 16#include <asm/unistd.h>
17#include <cpu/mmu_context.h> 17#include <cpu/mmu_context.h>
18#include <asm/page.h> 18#include <asm/page.h>
19#include <asm/cache.h>
19 20
20! NOTE: 21! NOTE:
21! GNU as (as of 2.9.1) changes bf/s into bt/s and bra, when the address 22! GNU as (as of 2.9.1) changes bf/s into bt/s and bra, when the address
@@ -187,44 +188,35 @@ call_dae:
187#if defined(CONFIG_SH_STANDARD_BIOS) 188#if defined(CONFIG_SH_STANDARD_BIOS)
188 /* Unwind the stack and jmp to the debug entry */ 189 /* Unwind the stack and jmp to the debug entry */
189ENTRY(sh_bios_handler) 190ENTRY(sh_bios_handler)
190 mov.l @r15+, r0 191 mov.l 1f, r8
191 mov.l @r15+, r1 192 bsr restore_regs
192 mov.l @r15+, r2 193 nop
193 mov.l @r15+, r3 194
194 mov.l @r15+, r4 195 lds k2, pr ! restore pr
195 mov.l @r15+, r5 196 mov k4, r15
196 mov.l @r15+, r6
197 mov.l @r15+, r7
198 stc sr, r8
199 mov.l 1f, r9 ! BL =1, RB=1, IMASK=0x0F
200 or r9, r8
201 ldc r8, sr ! here, change the register bank
202 mov.l @r15+, r8
203 mov.l @r15+, r9
204 mov.l @r15+, r10
205 mov.l @r15+, r11
206 mov.l @r15+, r12
207 mov.l @r15+, r13
208 mov.l @r15+, r14
209 mov.l @r15+, k0
210 ldc.l @r15+, spc
211 lds.l @r15+, pr
212 mov.l @r15+, k1
213 ldc.l @r15+, gbr
214 lds.l @r15+, mach
215 lds.l @r15+, macl
216 mov k0, r15
217 ! 197 !
218 mov.l 2f, k0 198 mov.l 2f, k0
219 mov.l @k0, k0 199 mov.l @k0, k0
220 jmp @k0 200 jmp @k0
221 ldc k1, ssr 201 ldc k3, ssr
222 .align 2 202 .align 2
2231: .long 0x300000f0 2031: .long 0x300000f0
2242: .long gdb_vbr_vector 2042: .long gdb_vbr_vector
225#endif /* CONFIG_SH_STANDARD_BIOS */ 205#endif /* CONFIG_SH_STANDARD_BIOS */
226 206
227restore_all: 207! restore_regs()
208! - restore r0, r1, r2, r3, r4, r5, r6, r7 from the stack
209! - switch bank
210! - restore r8, r9, r10, r11, r12, r13, r14, r15 from the stack
211! - restore spc, pr*, ssr, gbr, mach, macl, skip default tra
212! k2 returns original pr
213! k3 returns original sr
214! k4 returns original stack pointer
215! r8 passes SR bitmask, overwritten with restored data on return
216! r9 trashed
217! BL=0 on entry, on exit BL=1 (depending on r8).
218
219ENTRY(restore_regs)
228 mov.l @r15+, r0 220 mov.l @r15+, r0
229 mov.l @r15+, r1 221 mov.l @r15+, r1
230 mov.l @r15+, r2 222 mov.l @r15+, r2
@@ -234,10 +226,9 @@ restore_all:
234 mov.l @r15+, r6 226 mov.l @r15+, r6
235 mov.l @r15+, r7 227 mov.l @r15+, r7
236 ! 228 !
237 stc sr, r8 229 stc sr, r9
238 mov.l 7f, r9 230 or r8, r9
239 or r9, r8 ! BL =1, RB=1 231 ldc r9, sr
240 ldc r8, sr ! here, change the register bank
241 ! 232 !
242 mov.l @r15+, r8 233 mov.l @r15+, r8
243 mov.l @r15+, r9 234 mov.l @r15+, r9
@@ -248,12 +239,20 @@ restore_all:
248 mov.l @r15+, r14 239 mov.l @r15+, r14
249 mov.l @r15+, k4 ! original stack pointer 240 mov.l @r15+, k4 ! original stack pointer
250 ldc.l @r15+, spc 241 ldc.l @r15+, spc
251 lds.l @r15+, pr 242 mov.l @r15+, k2 ! original PR
252 mov.l @r15+, k3 ! original SR 243 mov.l @r15+, k3 ! original SR
253 ldc.l @r15+, gbr 244 ldc.l @r15+, gbr
254 lds.l @r15+, mach 245 lds.l @r15+, mach
255 lds.l @r15+, macl 246 lds.l @r15+, macl
256 add #4, r15 ! Skip syscall number 247 rts
248 add #4, r15 ! Skip syscall number
249
250restore_all:
251 mov.l 7f, r8
252 bsr restore_regs
253 nop
254
255 lds k2, pr ! restore pr
257 ! 256 !
258#ifdef CONFIG_SH_DSP 257#ifdef CONFIG_SH_DSP
259 mov.l @r15+, k0 ! DSP mode marker 258 mov.l @r15+, k0 ! DSP mode marker
@@ -294,7 +293,7 @@ skip_restore:
294 mov #0xf0, k1 293 mov #0xf0, k1
295 extu.b k1, k1 294 extu.b k1, k1
296 not k1, k1 295 not k1, k1
297 and k1, k2 ! Mask orignal SR value 296 and k1, k2 ! Mask original SR value
298 ! 297 !
299 mov k3, k0 ! Calculate IMASK-bits 298 mov k3, k0 ! Calculate IMASK-bits
300 shlr2 k0 299 shlr2 k0
@@ -313,7 +312,6 @@ skip_restore:
313 mov #0, k1 312 mov #0, k1
314 mov.b k1, @k0 313 mov.b k1, @k0
315#endif 314#endif
316 mov.l @r15+, k2 ! restore EXPEVT
317 mov k4, r15 315 mov k4, r15
318 rte 316 rte
319 nop 317 nop
@@ -336,81 +334,55 @@ skip_restore:
336ENTRY(vbr_base) 334ENTRY(vbr_base)
337 .long 0 335 .long 0
338! 336!
337! 0x100: General exception vector
338!
339 .balign 256,0,256 339 .balign 256,0,256
340general_exception: 340general_exception:
341 mov.l 1f, k2 341#ifndef CONFIG_CPU_SUBTYPE_SHX3
342 mov.l 2f, k3 342 bra handle_exception
343#ifdef CONFIG_CPU_SUBTYPE_SHX3 343 sts pr, k3 ! save original pr value in k3
344 mov.l @k2, k2 344#else
345 mov.l 1f, k4
346 mov.l @k4, k4
345 347
346 ! Is EXPEVT larger than 0x800? 348 ! Is EXPEVT larger than 0x800?
347 mov #0x8, k0 349 mov #0x8, k0
348 shll8 k0 350 shll8 k0
349 cmp/hs k0, k2 351 cmp/hs k0, k4
350 bf 0f 352 bf 0f
351 353
352 ! then add 0x580 (k2 is 0xd80 or 0xda0) 354 ! then add 0x580 (k2 is 0xd80 or 0xda0)
353 mov #0x58, k0 355 mov #0x58, k0
354 shll2 k0 356 shll2 k0
355 shll2 k0 357 shll2 k0
356 add k0, k2 358 add k0, k4
3570: 3590:
358 bra handle_exception 360 ! Setup stack and save DSP context (k0 contains original r15 on return)
361 bsr prepare_stack_save_dsp
359 nop 362 nop
360#else
361 bra handle_exception
362 mov.l @k2, k2
363#endif
364 .align 2
3651: .long EXPEVT
3662: .long ret_from_exception
367!
368!
369 363
370 .balign 1024,0,1024 364 ! Save registers / Switch to bank 0
371tlb_miss: 365 mov k4, k2 ! keep vector in k2
372 mov.l 1f, k2 366 mov.l 1f, k4 ! SR bits to clear in k4
373 mov.l 4f, k3 367 bsr save_regs ! needs original pr value in k3
374 bra handle_exception 368 nop
375 mov.l @k2, k2 369
376! 370 bra handle_exception_special
377 .balign 512,0,512
378interrupt:
379 mov.l 3f, k3
380#if defined(CONFIG_KGDB)
381 mov.l 2f, k2
382 ! Debounce (filter nested NMI)
383 mov.l @k2, k0
384 mov.l 5f, k1
385 cmp/eq k1, k0
386 bf 0f
387 mov.l 6f, k1
388 tas.b @k1
389 bt 0f
390 rte
391 nop 371 nop
392 .align 2
3932: .long INTEVT
3945: .long NMI_VEC
3956: .long in_nmi
3960:
397#endif /* defined(CONFIG_KGDB) */
398 bra handle_exception
399 mov #-1, k2 ! interrupt exception marker
400 372
401 .align 2 373 .align 2
4021: .long EXPEVT 3741: .long EXPEVT
4033: .long ret_from_irq 375#endif
4044: .long ret_from_exception
405 376
406! 377! prepare_stack_save_dsp()
407! 378! - roll back gRB
408 .align 2 379! - switch to kernel stack
409ENTRY(handle_exception) 380! - save DSP
410 ! Using k0, k1 for scratch registers (r0_bank1, r1_bank), 381! k0 returns original sp (after roll back)
411 ! save all registers onto stack. 382! k1 trashed
412 ! 383! k2 trashed
413 384
385prepare_stack_save_dsp:
414#ifdef CONFIG_GUSA 386#ifdef CONFIG_GUSA
415 ! Check for roll back gRB (User and Kernel) 387 ! Check for roll back gRB (User and Kernel)
416 mov r15, k0 388 mov r15, k0
@@ -430,7 +402,7 @@ ENTRY(handle_exception)
4302: mov k1, r15 ! SP = r1 4022: mov k1, r15 ! SP = r1
4311: 4031:
432#endif 404#endif
433 405 ! Switch to kernel stack if needed
434 stc ssr, k0 ! Is it from kernel space? 406 stc ssr, k0 ! Is it from kernel space?
435 shll k0 ! Check MD bit (bit30) by shifting it into... 407 shll k0 ! Check MD bit (bit30) by shifting it into...
436 shll k0 ! ...the T bit 408 shll k0 ! ...the T bit
@@ -443,18 +415,17 @@ ENTRY(handle_exception)
443 add current, k1 415 add current, k1
444 mov k1, r15 ! change to kernel stack 416 mov k1, r15 ! change to kernel stack
445 ! 417 !
4461: mov.l 2f, k1 4181:
447 !
448#ifdef CONFIG_SH_DSP 419#ifdef CONFIG_SH_DSP
449 mov.l r2, @-r15 ! Save r2, we need another reg 420 ! Save DSP context if needed
450 stc sr, k4 421 stc sr, k1
451 mov.l 1f, r2 422 mov #0x10, k2
452 tst r2, k4 ! Check if in DSP mode 423 shll8 k2 ! DSP=1 (0x00001000)
453 mov.l @r15+, r2 ! Restore r2 now 424 tst k2, k1 ! Check if in DSP mode (passed in k2)
454 bt/s skip_save 425 bt/s skip_save
455 mov #0, k4 ! Set marker for no stack frame 426 mov #0, k1 ! Set marker for no stack frame
456 427
457 mov r2, k4 ! Backup r2 (in k4) for later 428 mov k2, k1 ! Save has-frame marker
458 429
459 ! Save DSP registers on stack 430 ! Save DSP registers on stack
460 stc.l mod, @-r15 431 stc.l mod, @-r15
@@ -473,35 +444,74 @@ ENTRY(handle_exception)
473 ! as we're not at all interested in supporting ancient toolchains at 444 ! as we're not at all interested in supporting ancient toolchains at
474 ! this point. -- PFM. 445 ! this point. -- PFM.
475 446
476 mov r15, r2 447 mov r15, k2
477 .word 0xf653 ! movs.l a1, @-r2 448 .word 0xf653 ! movs.l a1, @-r2
478 .word 0xf6f3 ! movs.l a0g, @-r2 449 .word 0xf6f3 ! movs.l a0g, @-r2
479 .word 0xf6d3 ! movs.l a1g, @-r2 450 .word 0xf6d3 ! movs.l a1g, @-r2
480 .word 0xf6c3 ! movs.l m0, @-r2 451 .word 0xf6c3 ! movs.l m0, @-r2
481 .word 0xf6e3 ! movs.l m1, @-r2 452 .word 0xf6e3 ! movs.l m1, @-r2
482 mov r2, r15 453 mov k2, r15
483 454
484 mov k4, r2 ! Restore r2
485 mov.l 1f, k4 ! Force DSP stack frame
486skip_save: 455skip_save:
487 mov.l k4, @-r15 ! Push DSP mode marker onto stack 456 mov.l k1, @-r15 ! Push DSP mode marker onto stack
488#endif 457#endif
489 ! Save the user registers on the stack. 458 rts
490 mov.l k2, @-r15 ! EXPEVT 459 nop
491 460!
492 mov #-1, k4 461! 0x400: Instruction and Data TLB miss exception vector
493 mov.l k4, @-r15 ! set TRA (default: -1) 462!
494 ! 463 .balign 1024,0,1024
464tlb_miss:
465 sts pr, k3 ! save original pr value in k3
466
467handle_exception:
468 mova exception_data, k0
469
470 ! Setup stack and save DSP context (k0 contains original r15 on return)
471 bsr prepare_stack_save_dsp
472 PREF(k0)
473
474 ! Save registers / Switch to bank 0
475 mov.l 5f, k2 ! vector register address
476 mov.l 1f, k4 ! SR bits to clear in k4
477 bsr save_regs ! needs original pr value in k3
478 mov.l @k2, k2 ! read out vector and keep in k2
479
480handle_exception_special:
481 ! Setup return address and jump to exception handler
482 mov.l 7f, r9 ! fetch return address
483 stc r2_bank, r0 ! k2 (vector)
484 mov.l 6f, r10
485 shlr2 r0
486 shlr r0
487 mov.l @(r0, r10), r10
488 jmp @r10
489 lds r9, pr ! put return address in pr
490
491 .align L1_CACHE_SHIFT
492
493! save_regs()
494! - save default tra, macl, mach, gbr, ssr, pr* and spc on the stack
495! - save r15*, r14, r13, r12, r11, r10, r9, r8 on the stack
496! - switch bank
497! - save r7, r6, r5, r4, r3, r2, r1, r0 on the stack
498! k0 contains original stack pointer*
499! k1 trashed
500! k3 passes original pr*
501! k4 passes SR bitmask
502! BL=1 on entry, on exit BL=0.
503
504ENTRY(save_regs)
505 mov #-1, r1
506 mov.l k1, @-r15 ! set TRA (default: -1)
495 sts.l macl, @-r15 507 sts.l macl, @-r15
496 sts.l mach, @-r15 508 sts.l mach, @-r15
497 stc.l gbr, @-r15 509 stc.l gbr, @-r15
498 stc.l ssr, @-r15 510 stc.l ssr, @-r15
499 sts.l pr, @-r15 511 mov.l k3, @-r15 ! original pr in k3
500 stc.l spc, @-r15 512 stc.l spc, @-r15
501 ! 513
502 lds k3, pr ! Set the return address to pr 514 mov.l k0, @-r15 ! original stack pointer in k0
503 !
504 mov.l k0, @-r15 ! save orignal stack
505 mov.l r14, @-r15 515 mov.l r14, @-r15
506 mov.l r13, @-r15 516 mov.l r13, @-r15
507 mov.l r12, @-r15 517 mov.l r12, @-r15
@@ -509,13 +519,23 @@ skip_save:
509 mov.l r10, @-r15 519 mov.l r10, @-r15
510 mov.l r9, @-r15 520 mov.l r9, @-r15
511 mov.l r8, @-r15 521 mov.l r8, @-r15
512 ! 522
513 stc sr, r8 ! Back to normal register bank, and 523 mov.l 0f, k3 ! SR bits to set in k3
514 or k1, r8 ! Block all interrupts 524
515 mov.l 3f, k1 525 ! fall-through
516 and k1, r8 ! ... 526
517 ldc r8, sr ! ...changed here. 527! save_low_regs()
518 ! 528! - modify SR for bank switch
529! - save r7, r6, r5, r4, r3, r2, r1, r0 on the stack
530! k3 passes bits to set in SR
531! k4 passes bits to clear in SR
532
533ENTRY(save_low_regs)
534 stc sr, r8
535 or k3, r8
536 and k4, r8
537 ldc r8, sr
538
519 mov.l r7, @-r15 539 mov.l r7, @-r15
520 mov.l r6, @-r15 540 mov.l r6, @-r15
521 mov.l r5, @-r15 541 mov.l r5, @-r15
@@ -523,52 +543,63 @@ skip_save:
523 mov.l r3, @-r15 543 mov.l r3, @-r15
524 mov.l r2, @-r15 544 mov.l r2, @-r15
525 mov.l r1, @-r15 545 mov.l r1, @-r15
526 mov.l r0, @-r15
527
528 /*
529 * This gets a bit tricky.. in the INTEVT case we don't want to use
530 * the VBR offset as a destination in the jump call table, since all
531 * of the destinations are the same. In this case, (interrupt) sets
532 * a marker in r2 (now r2_bank since SR.RB changed), which we check
533 * to determine the exception type. For all other exceptions, we
534 * forcibly read EXPEVT from memory and fix up the jump address, in
535 * the interrupt exception case we jump to do_IRQ() and defer the
536 * INTEVT read until there. As a bonus, we can also clean up the SR.RB
537 * checks that do_IRQ() was doing..
538 */
539 stc r2_bank, r8
540 cmp/pz r8
541 bf interrupt_exception
542 shlr2 r8
543 shlr r8
544 mov.l 4f, r9
545 add r8, r9
546 mov.l @r9, r9
547 jmp @r9
548 nop
549 rts 546 rts
550 nop 547 mov.l r0, @-r15
551 548
549!
550! 0x600: Interrupt / NMI vector
551!
552 .balign 512,0,512
553ENTRY(handle_interrupt)
554#if defined(CONFIG_KGDB)
555 mov.l 2f, k2
556 ! Debounce (filter nested NMI)
557 mov.l @k2, k0
558 mov.l 9f, k1
559 cmp/eq k1, k0
560 bf 11f
561 mov.l 10f, k1
562 tas.b @k1
563 bt 11f
564 rte
565 nop
552 .align 2 566 .align 2
5531: .long 0x00001000 ! DSP=1 5679: .long NMI_VEC
5542: .long 0x000080f0 ! FD=1, IMASK=15 56810: .long in_nmi
5553: .long 0xcfffffff ! RB=0, BL=0 56911:
5564: .long exception_handling_table 570#endif /* defined(CONFIG_KGDB) */
571 sts pr, k3 ! save original pr value in k3
572 mova exception_data, k0
557 573
558interrupt_exception: 574 ! Setup stack and save DSP context (k0 contains original r15 on return)
559 mov.l 1f, r9 575 bsr prepare_stack_save_dsp
576 PREF(k0)
577
578 ! Save registers / Switch to bank 0
579 mov.l 1f, k4 ! SR bits to clear in k4
580 bsr save_regs ! needs original pr value in k3
581 mov #-1, k2 ! default vector kept in k2
582
583 ! Setup return address and jump to do_IRQ
584 mov.l 4f, r9 ! fetch return address
585 lds r9, pr ! put return address in pr
560 mov.l 2f, r4 586 mov.l 2f, r4
561 mov.l @r4, r4 587 mov.l 3f, r9
588 mov.l @r4, r4 ! pass INTEVT vector as arg0
562 jmp @r9 589 jmp @r9
563 mov r15, r5 590 mov r15, r5 ! pass saved registers as arg1
564 rts
565 nop
566
567 .align 2
5681: .long do_IRQ
5692: .long INTEVT
570 591
571 .align 2
572ENTRY(exception_none) 592ENTRY(exception_none)
573 rts 593 rts
574 nop 594 nop
595
596 .align L1_CACHE_SHIFT
597exception_data:
5980: .long 0x000080f0 ! FD=1, IMASK=15
5991: .long 0xcfffffff ! RB=0, BL=0
6002: .long INTEVT
6013: .long do_IRQ
6024: .long ret_from_irq
6035: .long EXPEVT
6046: .long exception_handling_table
6057: .long ret_from_exception
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index 6468ae86b944..63b67badd67e 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH7705 Setup 2 * SH7705 Setup
3 * 3 *
4 * Copyright (C) 2006, 2007 Paul Mundt 4 * Copyright (C) 2006 - 2009 Paul Mundt
5 * Copyright (C) 2007 Nobuhiro Iwamatsu 5 * Copyright (C) 2007 Nobuhiro Iwamatsu
6 * 6 *
7 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
@@ -21,51 +21,36 @@ enum {
21 /* interrupt sources */ 21 /* interrupt sources */
22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
23 PINT07, PINT815, 23 PINT07, PINT815,
24 DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3, 24
25 SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, 25 DMAC, SCIF0, SCIF2, ADC_ADI, USB,
26 SCIF2_ERI, SCIF2_RXI, SCIF2_TXI, 26
27 ADC_ADI,
28 USB_USI0, USB_USI1,
29 TPU0, TPU1, TPU2, TPU3, 27 TPU0, TPU1, TPU2, TPU3,
30 TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, 28 TMU0, TMU1, TMU2,
31 RTC_ATI, RTC_PRI, RTC_CUI,
32 WDT,
33 REF_RCMI,
34 29
35 /* interrupt groups */ 30 RTC, WDT, REF_RCMI,
36 RTC, TMU2, DMAC, USB, SCIF2, SCIF0,
37}; 31};
38 32
39static struct intc_vect vectors[] __initdata = { 33static struct intc_vect vectors[] __initdata = {
40 /* IRQ0->5 are handled in setup-sh3.c */ 34 /* IRQ0->5 are handled in setup-sh3.c */
41 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720), 35 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
42 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), 36 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
43 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860), 37 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
44 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0), 38 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
45 INTC_VECT(SCIF0_TXI, 0x8e0), 39 INTC_VECT(SCIF0, 0x8e0),
46 INTC_VECT(SCIF2_ERI, 0x900), INTC_VECT(SCIF2_RXI, 0x920), 40 INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
47 INTC_VECT(SCIF2_TXI, 0x960), 41 INTC_VECT(SCIF2, 0x960),
48 INTC_VECT(ADC_ADI, 0x980), 42 INTC_VECT(ADC_ADI, 0x980),
49 INTC_VECT(USB_USI0, 0xa20), INTC_VECT(USB_USI1, 0xa40), 43 INTC_VECT(USB, 0xa20), INTC_VECT(USB, 0xa40),
50 INTC_VECT(TPU0, 0xc00), INTC_VECT(TPU1, 0xc20), 44 INTC_VECT(TPU0, 0xc00), INTC_VECT(TPU1, 0xc20),
51 INTC_VECT(TPU2, 0xc80), INTC_VECT(TPU3, 0xca0), 45 INTC_VECT(TPU2, 0xc80), INTC_VECT(TPU3, 0xca0),
52 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 46 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
53 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 47 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
54 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 48 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
55 INTC_VECT(RTC_CUI, 0x4c0), 49 INTC_VECT(RTC, 0x4c0),
56 INTC_VECT(WDT, 0x560), 50 INTC_VECT(WDT, 0x560),
57 INTC_VECT(REF_RCMI, 0x580), 51 INTC_VECT(REF_RCMI, 0x580),
58}; 52};
59 53
60static struct intc_group groups[] __initdata = {
61 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
62 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
63 INTC_GROUP(DMAC, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
64 INTC_GROUP(USB, USB_USI0, USB_USI1),
65 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
66 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
67};
68
69static struct intc_prio_reg prio_registers[] __initdata = { 54static struct intc_prio_reg prio_registers[] __initdata = {
70 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 55 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
71 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } }, 56 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },
@@ -78,7 +63,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
78 63
79}; 64};
80 65
81static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, groups, 66static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL,
82 NULL, prio_registers, NULL); 67 NULL, prio_registers, NULL);
83 68
84static struct plat_sci_port sci_platform_data[] = { 69static struct plat_sci_port sci_platform_data[] = {
@@ -86,12 +71,12 @@ static struct plat_sci_port sci_platform_data[] = {
86 .mapbase = 0xa4410000, 71 .mapbase = 0xa4410000,
87 .flags = UPF_BOOT_AUTOCONF, 72 .flags = UPF_BOOT_AUTOCONF,
88 .type = PORT_SCIF, 73 .type = PORT_SCIF,
89 .irqs = { 56, 57, 59 }, 74 .irqs = { 56, 56, 56 },
90 }, { 75 }, {
91 .mapbase = 0xa4400000, 76 .mapbase = 0xa4400000,
92 .flags = UPF_BOOT_AUTOCONF, 77 .flags = UPF_BOOT_AUTOCONF,
93 .type = PORT_SCIF, 78 .type = PORT_SCIF,
94 .irqs = { 52, 53, 55 }, 79 .irqs = { 52, 52, 52 },
95 }, { 80 }, {
96 .flags = 0, 81 .flags = 0,
97 } 82 }
@@ -115,14 +100,6 @@ static struct resource rtc_resources[] = {
115 .start = 20, 100 .start = 20,
116 .flags = IORESOURCE_IRQ, 101 .flags = IORESOURCE_IRQ,
117 }, 102 },
118 [2] = {
119 .start = 21,
120 .flags = IORESOURCE_IRQ,
121 },
122 [3] = {
123 .start = 22,
124 .flags = IORESOURCE_IRQ,
125 },
126}; 103};
127 104
128static struct sh_rtc_platform_info rtc_info = { 105static struct sh_rtc_platform_info rtc_info = {
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index 93c55e2ed952..a74f960b5e79 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -2,6 +2,7 @@
2 * SH3 Setup code for SH7706, SH7707, SH7708, SH7709 2 * SH3 Setup code for SH7706, SH7707, SH7708, SH7709
3 * 3 *
4 * Copyright (C) 2007 Magnus Damm 4 * Copyright (C) 2007 Magnus Damm
5 * Copyright (C) 2009 Paul Mundt
5 * 6 *
6 * Based on setup-sh7709.c 7 * Based on setup-sh7709.c
7 * 8 *
@@ -24,46 +25,37 @@ enum {
24 /* interrupt sources */ 25 /* interrupt sources */
25 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 26 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
26 PINT07, PINT815, 27 PINT07, PINT815,
27 DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3, 28 DMAC, SCIF0, SCIF2, SCI, ADC_ADI,
28 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
29 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
30 SCI_ERI, SCI_RXI, SCI_TXI, SCI_TEI,
31 ADC_ADI,
32 LCDC, PCC0, PCC1, 29 LCDC, PCC0, PCC1,
33 TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, 30 TMU0, TMU1, TMU2,
34 RTC_ATI, RTC_PRI, RTC_CUI, 31 RTC, WDT, REF,
35 WDT,
36 REF_RCMI, REF_ROVI,
37
38 /* interrupt groups */
39 RTC, REF, TMU2, DMAC, SCI, SCIF2, SCIF0,
40}; 32};
41 33
42static struct intc_vect vectors[] __initdata = { 34static struct intc_vect vectors[] __initdata = {
43 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 35 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
44 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 36 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
45 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 37 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
46 INTC_VECT(RTC_CUI, 0x4c0), 38 INTC_VECT(RTC, 0x4c0),
47 INTC_VECT(SCI_ERI, 0x4e0), INTC_VECT(SCI_RXI, 0x500), 39 INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),
48 INTC_VECT(SCI_TXI, 0x520), INTC_VECT(SCI_TEI, 0x540), 40 INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),
49 INTC_VECT(WDT, 0x560), 41 INTC_VECT(WDT, 0x560),
50 INTC_VECT(REF_RCMI, 0x580), 42 INTC_VECT(REF, 0x580),
51 INTC_VECT(REF_ROVI, 0x5a0), 43 INTC_VECT(REF, 0x5a0),
52#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 44#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
53 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 45 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
54 defined(CONFIG_CPU_SUBTYPE_SH7709) 46 defined(CONFIG_CPU_SUBTYPE_SH7709)
55 /* IRQ0->5 are handled in setup-sh3.c */ 47 /* IRQ0->5 are handled in setup-sh3.c */
56 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), 48 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
57 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860), 49 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
58 INTC_VECT(ADC_ADI, 0x980), 50 INTC_VECT(ADC_ADI, 0x980),
59 INTC_VECT(SCIF2_ERI, 0x900), INTC_VECT(SCIF2_RXI, 0x920), 51 INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
60 INTC_VECT(SCIF2_BRI, 0x940), INTC_VECT(SCIF2_TXI, 0x960), 52 INTC_VECT(SCIF2, 0x940), INTC_VECT(SCIF2, 0x960),
61#endif 53#endif
62#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 54#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
63 defined(CONFIG_CPU_SUBTYPE_SH7709) 55 defined(CONFIG_CPU_SUBTYPE_SH7709)
64 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720), 56 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
65 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0), 57 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
66 INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0), 58 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
67#endif 59#endif
68#if defined(CONFIG_CPU_SUBTYPE_SH7707) 60#if defined(CONFIG_CPU_SUBTYPE_SH7707)
69 INTC_VECT(LCDC, 0x9a0), 61 INTC_VECT(LCDC, 0x9a0),
@@ -71,16 +63,6 @@ static struct intc_vect vectors[] __initdata = {
71#endif 63#endif
72}; 64};
73 65
74static struct intc_group groups[] __initdata = {
75 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
76 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
77 INTC_GROUP(REF, REF_RCMI, REF_ROVI),
78 INTC_GROUP(DMAC, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
79 INTC_GROUP(SCI, SCI_ERI, SCI_RXI, SCI_TXI, SCI_TEI),
80 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
81 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
82};
83
84static struct intc_prio_reg prio_registers[] __initdata = { 66static struct intc_prio_reg prio_registers[] __initdata = {
85 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 67 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
86 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } }, 68 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
@@ -101,7 +83,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
101#endif 83#endif
102}; 84};
103 85
104static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, groups, 86static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, NULL,
105 NULL, prio_registers, NULL); 87 NULL, prio_registers, NULL);
106 88
107static struct resource rtc_resources[] = { 89static struct resource rtc_resources[] = {
@@ -111,14 +93,6 @@ static struct resource rtc_resources[] = {
111 .flags = IORESOURCE_IO, 93 .flags = IORESOURCE_IO,
112 }, 94 },
113 [1] = { 95 [1] = {
114 .start = 21,
115 .flags = IORESOURCE_IRQ,
116 },
117 [2] = {
118 .start = 22,
119 .flags = IORESOURCE_IRQ,
120 },
121 [3] = {
122 .start = 20, 96 .start = 20,
123 .flags = IORESOURCE_IRQ, 97 .flags = IORESOURCE_IRQ,
124 }, 98 },
@@ -136,7 +110,7 @@ static struct plat_sci_port sci_platform_data[] = {
136 .mapbase = 0xfffffe80, 110 .mapbase = 0xfffffe80,
137 .flags = UPF_BOOT_AUTOCONF, 111 .flags = UPF_BOOT_AUTOCONF,
138 .type = PORT_SCI, 112 .type = PORT_SCI,
139 .irqs = { 23, 24, 25, 0 }, 113 .irqs = { 23, 23, 23, 0 },
140 }, 114 },
141#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 115#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
142 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 116 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
@@ -145,7 +119,7 @@ static struct plat_sci_port sci_platform_data[] = {
145 .mapbase = 0xa4000150, 119 .mapbase = 0xa4000150,
146 .flags = UPF_BOOT_AUTOCONF, 120 .flags = UPF_BOOT_AUTOCONF,
147 .type = PORT_SCIF, 121 .type = PORT_SCIF,
148 .irqs = { 56, 57, 59, 58 }, 122 .irqs = { 56, 56, 56, 56 },
149 }, 123 },
150#endif 124#endif
151#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 125#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
@@ -154,7 +128,7 @@ static struct plat_sci_port sci_platform_data[] = {
154 .mapbase = 0xa4000140, 128 .mapbase = 0xa4000140,
155 .flags = UPF_BOOT_AUTOCONF, 129 .flags = UPF_BOOT_AUTOCONF,
156 .type = PORT_IRDA, 130 .type = PORT_IRDA,
157 .irqs = { 52, 53, 55, 54 }, 131 .irqs = { 52, 52, 52, 52 },
158 }, 132 },
159#endif 133#endif
160 { 134 {
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 77eee481de47..335098b66e2f 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH3 Setup code for SH7710, SH7712 2 * SH3 Setup code for SH7710, SH7712
3 * 3 *
4 * Copyright (C) 2006, 2007 Paul Mundt 4 * Copyright (C) 2006 - 2009 Paul Mundt
5 * Copyright (C) 2007 Nobuhiro Iwamatsu 5 * Copyright (C) 2007 Nobuhiro Iwamatsu
6 * 6 *
7 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
@@ -20,59 +20,40 @@ enum {
20 20
21 /* interrupt sources */ 21 /* interrupt sources */
22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
23 DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3, 23 DMAC1, SCIF0, SCIF1, DMAC2, IPSEC,
24 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
25 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
26 DMAC_DEI4, DMAC_DEI5,
27 IPSEC,
28 EDMAC0, EDMAC1, EDMAC2, 24 EDMAC0, EDMAC1, EDMAC2,
29 SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI, 25 SIOF0, SIOF1,
30 SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI,
31 TMU0, TMU1, TMU2,
32 RTC_ATI, RTC_PRI, RTC_CUI,
33 WDT,
34 REF,
35 26
36 /* interrupt groups */ 27 TMU0, TMU1, TMU2,
37 RTC, DMAC1, SCIF0, SCIF1, DMAC2, SIOF0, SIOF1, 28 RTC, WDT, REF,
38}; 29};
39 30
40static struct intc_vect vectors[] __initdata = { 31static struct intc_vect vectors[] __initdata = {
41 /* IRQ0->5 are handled in setup-sh3.c */ 32 /* IRQ0->5 are handled in setup-sh3.c */
42 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), 33 INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820),
43 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860), 34 INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860),
44 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0), 35 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
45 INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0), 36 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
46 INTC_VECT(SCIF1_ERI, 0x900), INTC_VECT(SCIF1_RXI, 0x920), 37 INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920),
47 INTC_VECT(SCIF1_BRI, 0x940), INTC_VECT(SCIF1_TXI, 0x960), 38 INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960),
48 INTC_VECT(DMAC_DEI4, 0xb80), INTC_VECT(DMAC_DEI5, 0xba0), 39 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
49#ifdef CONFIG_CPU_SUBTYPE_SH7710 40#ifdef CONFIG_CPU_SUBTYPE_SH7710
50 INTC_VECT(IPSEC, 0xbe0), 41 INTC_VECT(IPSEC, 0xbe0),
51#endif 42#endif
52 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20), 43 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
53 INTC_VECT(EDMAC2, 0xc40), 44 INTC_VECT(EDMAC2, 0xc40),
54 INTC_VECT(SIOF0_ERI, 0xe00), INTC_VECT(SIOF0_TXI, 0xe20), 45 INTC_VECT(SIOF0, 0xe00), INTC_VECT(SIOF0, 0xe20),
55 INTC_VECT(SIOF0_RXI, 0xe40), INTC_VECT(SIOF0_CCI, 0xe60), 46 INTC_VECT(SIOF0, 0xe40), INTC_VECT(SIOF0, 0xe60),
56 INTC_VECT(SIOF1_ERI, 0xe80), INTC_VECT(SIOF1_TXI, 0xea0), 47 INTC_VECT(SIOF1, 0xe80), INTC_VECT(SIOF1, 0xea0),
57 INTC_VECT(SIOF1_RXI, 0xec0), INTC_VECT(SIOF1_CCI, 0xee0), 48 INTC_VECT(SIOF1, 0xec0), INTC_VECT(SIOF1, 0xee0),
58 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 49 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
59 INTC_VECT(TMU2, 0x440), 50 INTC_VECT(TMU2, 0x440),
60 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 51 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
61 INTC_VECT(RTC_CUI, 0x4c0), 52 INTC_VECT(RTC, 0x4c0),
62 INTC_VECT(WDT, 0x560), 53 INTC_VECT(WDT, 0x560),
63 INTC_VECT(REF, 0x580), 54 INTC_VECT(REF, 0x580),
64}; 55};
65 56
66static struct intc_group groups[] __initdata = {
67 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
68 INTC_GROUP(DMAC1, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
69 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
70 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
71 INTC_GROUP(DMAC2, DMAC_DEI4, DMAC_DEI5),
72 INTC_GROUP(SIOF0, SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI),
73 INTC_GROUP(SIOF1, SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI),
74};
75
76static struct intc_prio_reg prio_registers[] __initdata = { 57static struct intc_prio_reg prio_registers[] __initdata = {
77 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 58 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
78 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, 59 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
@@ -85,7 +66,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
85 { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } }, 66 { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
86}; 67};
87 68
88static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups, 69static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, NULL,
89 NULL, prio_registers, NULL); 70 NULL, prio_registers, NULL);
90 71
91static struct resource rtc_resources[] = { 72static struct resource rtc_resources[] = {
@@ -98,14 +79,6 @@ static struct resource rtc_resources[] = {
98 .start = 20, 79 .start = 20,
99 .flags = IORESOURCE_IRQ, 80 .flags = IORESOURCE_IRQ,
100 }, 81 },
101 [2] = {
102 .start = 21,
103 .flags = IORESOURCE_IRQ,
104 },
105 [3] = {
106 .start = 22,
107 .flags = IORESOURCE_IRQ,
108 },
109}; 82};
110 83
111static struct sh_rtc_platform_info rtc_info = { 84static struct sh_rtc_platform_info rtc_info = {
@@ -127,12 +100,12 @@ static struct plat_sci_port sci_platform_data[] = {
127 .mapbase = 0xa4400000, 100 .mapbase = 0xa4400000,
128 .flags = UPF_BOOT_AUTOCONF, 101 .flags = UPF_BOOT_AUTOCONF,
129 .type = PORT_SCIF, 102 .type = PORT_SCIF,
130 .irqs = { 52, 53, 55, 54 }, 103 .irqs = { 52, 52, 52, 52 },
131 }, { 104 }, {
132 .mapbase = 0xa4410000, 105 .mapbase = 0xa4410000,
133 .flags = UPF_BOOT_AUTOCONF, 106 .flags = UPF_BOOT_AUTOCONF,
134 .type = PORT_SCIF, 107 .type = PORT_SCIF,
135 .irqs = { 56, 57, 59, 58 }, 108 .irqs = { 56, 56, 56, 56 },
136 }, { 109 }, {
137 110
138 .flags = 0, 111 .flags = 0,
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index f807a21b066c..003874a2fd2a 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -2,6 +2,7 @@
2 * SH7720 Setup 2 * SH7720 Setup
3 * 3 *
4 * Copyright (C) 2007 Markus Brunner, Mark Jonas 4 * Copyright (C) 2007 Markus Brunner, Mark Jonas
5 * Copyright (C) 2009 Paul Mundt
5 * 6 *
6 * Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c: 7 * Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c:
7 * 8 *
@@ -26,17 +27,7 @@ static struct resource rtc_resources[] = {
26 .flags = IORESOURCE_IO, 27 .flags = IORESOURCE_IO,
27 }, 28 },
28 [1] = { 29 [1] = {
29 /* Period IRQ */ 30 /* Shared Period/Carry/Alarm IRQ */
30 .start = 21,
31 .flags = IORESOURCE_IRQ,
32 },
33 [2] = {
34 /* Carry IRQ */
35 .start = 22,
36 .flags = IORESOURCE_IRQ,
37 },
38 [3] = {
39 /* Alarm IRQ */
40 .start = 20, 31 .start = 20,
41 .flags = IORESOURCE_IRQ, 32 .flags = IORESOURCE_IRQ,
42 }, 33 },
@@ -150,62 +141,49 @@ enum {
150 UNUSED = 0, 141 UNUSED = 0,
151 142
152 /* interrupt sources */ 143 /* interrupt sources */
153 TMU0, TMU1, TMU2, RTC_ATI, RTC_PRI, RTC_CUI, 144 TMU0, TMU1, TMU2, RTC,
154 WDT, REF_RCMI, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND, 145 WDT, REF_RCMI, SIM,
155 IRQ0, IRQ1, IRQ2, IRQ3, 146 IRQ0, IRQ1, IRQ2, IRQ3,
156 USBF_SPD, TMU_SUNI, IRQ5, IRQ4, 147 USBF_SPD, TMU_SUNI, IRQ5, IRQ4,
157 DMAC1_DEI0, DMAC1_DEI1, DMAC1_DEI2, DMAC1_DEI3, LCDC, SSL, 148 DMAC1, LCDC, SSL,
158 ADC, DMAC2_DEI4, DMAC2_DEI5, USBFI0, USBFI1, CMT, 149 ADC, DMAC2, USBFI, CMT,
159 SCIF0, SCIF1, 150 SCIF0, SCIF1,
160 PINT07, PINT815, TPU0, TPU1, TPU2, TPU3, IIC, 151 PINT07, PINT815, TPU, IIC,
161 SIOF0, SIOF1, MMCI0, MMCI1, MMCI2, MMCI3, PCC, 152 SIOF0, SIOF1, MMC, PCC,
162 USBHI, AFEIF, 153 USBHI, AFEIF,
163 H_UDI, 154 H_UDI,
164 /* interrupt groups */
165 TMU, RTC, SIM, DMAC1, USBFI, DMAC2, USB, TPU, MMC,
166}; 155};
167 156
168static struct intc_vect vectors[] __initdata = { 157static struct intc_vect vectors[] __initdata = {
169 /* IRQ0->5 are handled in setup-sh3.c */ 158 /* IRQ0->5 are handled in setup-sh3.c */
170 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 159 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
171 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC_ATI, 0x480), 160 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC, 0x480),
172 INTC_VECT(RTC_PRI, 0x4a0), INTC_VECT(RTC_CUI, 0x4c0), 161 INTC_VECT(RTC, 0x4a0), INTC_VECT(RTC, 0x4c0),
173 INTC_VECT(SIM_ERI, 0x4e0), INTC_VECT(SIM_RXI, 0x500), 162 INTC_VECT(SIM, 0x4e0), INTC_VECT(SIM, 0x500),
174 INTC_VECT(SIM_TXI, 0x520), INTC_VECT(SIM_TEND, 0x540), 163 INTC_VECT(SIM, 0x520), INTC_VECT(SIM, 0x540),
175 INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580), 164 INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580),
176 /* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0), 165 /* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0),
177 INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1_DEI0, 0x800), 166 INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1, 0x800),
178 INTC_VECT(DMAC1_DEI1, 0x820), INTC_VECT(DMAC1_DEI2, 0x840), 167 INTC_VECT(DMAC1, 0x820), INTC_VECT(DMAC1, 0x840),
179 INTC_VECT(DMAC1_DEI3, 0x860), INTC_VECT(LCDC, 0x900), 168 INTC_VECT(DMAC1, 0x860), INTC_VECT(LCDC, 0x900),
180#if defined(CONFIG_CPU_SUBTYPE_SH7720) 169#if defined(CONFIG_CPU_SUBTYPE_SH7720)
181 INTC_VECT(SSL, 0x980), 170 INTC_VECT(SSL, 0x980),
182#endif 171#endif
183 INTC_VECT(USBFI0, 0xa20), INTC_VECT(USBFI1, 0xa40), 172 INTC_VECT(USBFI, 0xa20), INTC_VECT(USBFI, 0xa40),
184 INTC_VECT(USBHI, 0xa60), 173 INTC_VECT(USBHI, 0xa60),
185 INTC_VECT(DMAC2_DEI4, 0xb80), INTC_VECT(DMAC2_DEI5, 0xba0), 174 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
186 INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00), 175 INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00),
187 INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80), 176 INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80),
188 INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00), 177 INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00),
189 INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU0, 0xd80), 178 INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU, 0xd80),
190 INTC_VECT(TPU1, 0xda0), INTC_VECT(TPU2, 0xdc0), 179 INTC_VECT(TPU, 0xda0), INTC_VECT(TPU, 0xdc0),
191 INTC_VECT(TPU3, 0xde0), INTC_VECT(IIC, 0xe00), 180 INTC_VECT(TPU, 0xde0), INTC_VECT(IIC, 0xe00),
192 INTC_VECT(MMCI0, 0xe80), INTC_VECT(MMCI1, 0xea0), 181 INTC_VECT(MMC, 0xe80), INTC_VECT(MMC, 0xea0),
193 INTC_VECT(MMCI2, 0xec0), INTC_VECT(MMCI3, 0xee0), 182 INTC_VECT(MMC, 0xec0), INTC_VECT(MMC, 0xee0),
194 INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60), 183 INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60),
195 INTC_VECT(AFEIF, 0xfe0), 184 INTC_VECT(AFEIF, 0xfe0),
196}; 185};
197 186
198static struct intc_group groups[] __initdata = {
199 INTC_GROUP(TMU, TMU0, TMU1, TMU2),
200 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
201 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND),
202 INTC_GROUP(DMAC1, DMAC1_DEI0, DMAC1_DEI1, DMAC1_DEI2, DMAC1_DEI3),
203 INTC_GROUP(USBFI, USBFI0, USBFI1),
204 INTC_GROUP(DMAC2, DMAC2_DEI4, DMAC2_DEI5),
205 INTC_GROUP(TPU, TPU0, TPU1, TPU2, TPU3),
206 INTC_GROUP(MMC, MMCI0, MMCI1, MMCI2, MMCI3),
207};
208
209static struct intc_prio_reg prio_registers[] __initdata = { 187static struct intc_prio_reg prio_registers[] __initdata = {
210 { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 188 { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
211 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } }, 189 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
@@ -219,7 +197,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
219 { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } }, 197 { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } },
220}; 198};
221 199
222static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, groups, 200static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, NULL,
223 NULL, prio_registers, NULL); 201 NULL, prio_registers, NULL);
224 202
225void __init plat_irq_setup(void) 203void __init plat_irq_setup(void)
diff --git a/arch/sh/kernel/cpu/sh3/swsusp.S b/arch/sh/kernel/cpu/sh3/swsusp.S
new file mode 100644
index 000000000000..01145426a2b8
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh3/swsusp.S
@@ -0,0 +1,147 @@
1/*
2 * arch/sh/kernel/cpu/sh3/swsusp.S
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/sys.h>
11#include <linux/errno.h>
12#include <linux/linkage.h>
13#include <asm/asm-offsets.h>
14#include <asm/page.h>
15
16#define k0 r0
17#define k1 r1
18#define k2 r2
19#define k3 r3
20#define k4 r4
21
22! swsusp_arch_resume()
23! - copy restore_pblist pages
24! - restore registers from swsusp_arch_regs_cpu0
25
26ENTRY(swsusp_arch_resume)
27 mov.l 1f, r15
28 mov.l 2f, r4
29 mov.l @r4, r4
30
31swsusp_copy_loop:
32 mov r4, r0
33 cmp/eq #0, r0
34 bt swsusp_restore_regs
35
36 mov.l @(PBE_ADDRESS, r4), r2
37 mov.l @(PBE_ORIG_ADDRESS, r4), r5
38
39 mov #(PAGE_SIZE >> 10), r3
40 shll8 r3
41 shlr2 r3 /* PAGE_SIZE / 16 */
42swsusp_copy_page:
43 dt r3
44 mov.l @r2+,r1 /* 16n+0 */
45 mov.l r1,@r5
46 add #4,r5
47 mov.l @r2+,r1 /* 16n+4 */
48 mov.l r1,@r5
49 add #4,r5
50 mov.l @r2+,r1 /* 16n+8 */
51 mov.l r1,@r5
52 add #4,r5
53 mov.l @r2+,r1 /* 16n+12 */
54 mov.l r1,@r5
55 bf/s swsusp_copy_page
56 add #4,r5
57
58 bra swsusp_copy_loop
59 mov.l @(PBE_NEXT, r4), r4
60
61swsusp_restore_regs:
62 ! BL=0: R7->R0 is bank0
63 mov.l 3f, r8
64 mov.l 4f, r5
65 jsr @r5
66 nop
67
68 ! BL=1: R7->R0 is bank1
69 lds k2, pr
70 ldc k3, ssr
71
72 mov.l @r15+, r0
73 mov.l @r15+, r1
74 mov.l @r15+, r2
75 mov.l @r15+, r3
76 mov.l @r15+, r4
77 mov.l @r15+, r5
78 mov.l @r15+, r6
79 mov.l @r15+, r7
80
81 rte
82 nop
83 ! BL=0: R7->R0 is bank0
84
85 .align 2
861: .long swsusp_arch_regs_cpu0
872: .long restore_pblist
883: .long 0x20000000 ! RB=1
894: .long restore_regs
90
91! swsusp_arch_suspend()
92! - prepare pc for resume, return from function without swsusp_save on resume
93! - save registers in swsusp_arch_regs_cpu0
94! - call swsusp_save write suspend image
95
96ENTRY(swsusp_arch_suspend)
97 sts pr, r0 ! save pr in r0
98 mov r15, r2 ! save sp in r2
99 mov r8, r5 ! save r8 in r5
100 stc sr, r1
101 ldc r1, ssr ! save sr in ssr
102 mov.l 1f, r1
103 ldc r1, spc ! setup pc value for resuming
104 mov.l 5f, r15 ! use swsusp_arch_regs_cpu0 as stack
105 mov.l 6f, r3
106 add r3, r15 ! save from top of structure
107
108 ! BL=0: R7->R0 is bank0
109 mov.l 2f, r3 ! get new SR value for bank1
110 mov #0, r4
111 mov.l 7f, r1
112 jsr @r1 ! switch to bank1 and save bank1 r7->r0
113 not r4, r4
114
115 ! BL=1: R7->R0 is bank1
116 stc r2_bank, k0 ! fetch old sp from r2_bank0
117 mov.l 3f, k4 ! SR bits to clear in k4
118 mov.l 8f, k1
119 jsr @k1 ! switch to bank0 and save all regs
120 stc r0_bank, k3 ! fetch old pr from r0_bank0
121
122 ! BL=0: R7->R0 is bank0
123 mov r2, r15 ! restore old sp
124 mov r5, r8 ! restore old r8
125 stc ssr, r1
126 ldc r1, sr ! restore old sr
127 lds r0, pr ! restore old pr
128 mov.l 4f, r0
129 jmp @r0
130 nop
131
132swsusp_call_save:
133 mov r2, r15 ! restore old sp
134 mov r5, r8 ! restore old r8
135 lds r0, pr ! restore old pr
136 rts
137 mov #0, r0
138
139 .align 2
1401: .long swsusp_call_save
1412: .long 0x20000000 ! RB=1
1423: .long 0xdfffffff ! RB=0
1434: .long swsusp_save
1445: .long swsusp_arch_regs_cpu0
1456: .long SWSUSP_ARCH_REGS_SIZE
1467: .long save_low_regs
1478: .long save_regs
diff --git a/arch/sh/kernel/cpu/sh4/Makefile b/arch/sh/kernel/cpu/sh4/Makefile
index d608557c7a3f..203b18347b83 100644
--- a/arch/sh/kernel/cpu/sh4/Makefile
+++ b/arch/sh/kernel/cpu/sh4/Makefile
@@ -5,6 +5,7 @@
5obj-y := probe.o common.o 5obj-y := probe.o common.o
6common-y += $(addprefix ../sh3/, entry.o ex.o) 6common-y += $(addprefix ../sh3/, entry.o ex.o)
7 7
8obj-$(CONFIG_HIBERNATION) += $(addprefix ../sh3/, swsusp.o)
8obj-$(CONFIG_SH_FPU) += fpu.o softfloat.o 9obj-$(CONFIG_SH_FPU) += fpu.o softfloat.o
9obj-$(CONFIG_SH_STORE_QUEUES) += sq.o 10obj-$(CONFIG_SH_STORE_QUEUES) += sq.o
10 11
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 2e42572b1b11..3d3a3c4425a9 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -129,6 +129,13 @@ int __init detect_cpu_and_cache_system(void)
129 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | 129 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
130 CPU_HAS_LLSC; 130 CPU_HAS_LLSC;
131 break; 131 break;
132 case 0x4004:
133 boot_cpu_data.type = CPU_SH7786;
134 boot_cpu_data.icache.ways = 4;
135 boot_cpu_data.dcache.ways = 4;
136 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
137 CPU_HAS_LLSC | CPU_HAS_PTEAEX;
138 break;
132 case 0x3008: 139 case 0x3008:
133 boot_cpu_data.icache.ways = 4; 140 boot_cpu_data.icache.ways = 4;
134 boot_cpu_data.dcache.ways = 4; 141 boot_cpu_data.dcache.ways = 4;
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index ec884039b914..a1c80d909cd6 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -21,17 +21,7 @@ static struct resource rtc_resources[] = {
21 .flags = IORESOURCE_IO, 21 .flags = IORESOURCE_IO,
22 }, 22 },
23 [1] = { 23 [1] = {
24 /* Period IRQ */ 24 /* Shared Period/Carry/Alarm IRQ */
25 .start = 21,
26 .flags = IORESOURCE_IRQ,
27 },
28 [2] = {
29 /* Carry IRQ */
30 .start = 22,
31 .flags = IORESOURCE_IRQ,
32 },
33 [3] = {
34 /* Alarm IRQ */
35 .start = 20, 25 .start = 20,
36 .flags = IORESOURCE_IRQ, 26 .flags = IORESOURCE_IRQ,
37 }, 27 },
@@ -50,13 +40,13 @@ static struct plat_sci_port sci_platform_data[] = {
50 .mapbase = 0xffe00000, 40 .mapbase = 0xffe00000,
51 .flags = UPF_BOOT_AUTOCONF, 41 .flags = UPF_BOOT_AUTOCONF,
52 .type = PORT_SCI, 42 .type = PORT_SCI,
53 .irqs = { 23, 24, 25, 0 }, 43 .irqs = { 23, 23, 23, 0 },
54 }, { 44 }, {
55#endif 45#endif
56 .mapbase = 0xffe80000, 46 .mapbase = 0xffe80000,
57 .flags = UPF_BOOT_AUTOCONF, 47 .flags = UPF_BOOT_AUTOCONF,
58 .type = PORT_SCIF, 48 .type = PORT_SCIF,
59 .irqs = { 40, 41, 43, 42 }, 49 .irqs = { 40, 40, 40, 40 },
60 }, { 50 }, {
61 .flags = 0, 51 .flags = 0,
62 } 52 }
@@ -87,43 +77,27 @@ enum {
87 77
88 /* interrupt sources */ 78 /* interrupt sources */
89 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */ 79 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
90 HUDI, GPIOI, 80 HUDI, GPIOI, DMAC,
91 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
92 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
93 DMAC_DMAE,
94 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 81 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
95 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, 82 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
96 TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, 83 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
97 RTC_ATI, RTC_PRI, RTC_CUI,
98 SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
99 SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
100 WDT,
101 REF_RCMI, REF_ROVI,
102 84
103 /* interrupt groups */ 85 /* interrupt groups */
104 DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, 86 PCIC1,
105}; 87};
106 88
107static struct intc_vect vectors[] __initdata = { 89static struct intc_vect vectors[] __initdata = {
108 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 90 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
109 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 91 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
110 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 92 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
111 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 93 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
112 INTC_VECT(RTC_CUI, 0x4c0), 94 INTC_VECT(RTC, 0x4c0),
113 INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500), 95 INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
114 INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540), 96 INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
115 INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720), 97 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
116 INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760), 98 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
117 INTC_VECT(WDT, 0x560), 99 INTC_VECT(WDT, 0x560),
118 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), 100 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
119};
120
121static struct intc_group groups[] __initdata = {
122 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
123 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
124 INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
125 INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
126 INTC_GROUP(REF, REF_RCMI, REF_ROVI),
127}; 101};
128 102
129static struct intc_prio_reg prio_registers[] __initdata = { 103static struct intc_prio_reg prio_registers[] __initdata = {
@@ -136,7 +110,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
136 PCIC1, PCIC0_PCISERR } }, 110 PCIC1, PCIC0_PCISERR } },
137}; 111};
138 112
139static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups, 113static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
140 NULL, prio_registers, NULL); 114 NULL, prio_registers, NULL);
141 115
142/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ 116/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
@@ -145,39 +119,28 @@ static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups,
145 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 119 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
146 defined(CONFIG_CPU_SUBTYPE_SH7091) 120 defined(CONFIG_CPU_SUBTYPE_SH7091)
147static struct intc_vect vectors_dma4[] __initdata = { 121static struct intc_vect vectors_dma4[] __initdata = {
148 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 122 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
149 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 123 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
150 INTC_VECT(DMAC_DMAE, 0x6c0), 124 INTC_VECT(DMAC, 0x6c0),
151};
152
153static struct intc_group groups_dma4[] __initdata = {
154 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
155 DMAC_DMTE3, DMAC_DMAE),
156}; 125};
157 126
158static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4", 127static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
159 vectors_dma4, groups_dma4, 128 vectors_dma4, NULL,
160 NULL, prio_registers, NULL); 129 NULL, prio_registers, NULL);
161#endif 130#endif
162 131
163/* SH7750R and SH7751R both have 8-channel DMA controllers */ 132/* SH7750R and SH7751R both have 8-channel DMA controllers */
164#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R) 133#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
165static struct intc_vect vectors_dma8[] __initdata = { 134static struct intc_vect vectors_dma8[] __initdata = {
166 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 135 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
167 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 136 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
168 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), 137 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
169 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), 138 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
170 INTC_VECT(DMAC_DMAE, 0x6c0), 139 INTC_VECT(DMAC, 0x6c0),
171};
172
173static struct intc_group groups_dma8[] __initdata = {
174 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
175 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
176 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
177}; 140};
178 141
179static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8", 142static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
180 vectors_dma8, groups_dma8, 143 vectors_dma8, NULL,
181 NULL, prio_registers, NULL); 144 NULL, prio_registers, NULL);
182#endif 145#endif
183 146
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 8e344ec5847e..1a92361feeb9 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o
7obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o 7obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
8obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o 8obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
9obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o 9obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o 12obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
@@ -21,6 +22,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o
21clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o 22clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
22clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o 23clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
23clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o 24clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
25clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o
24clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o 26clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o
25clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o 27clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
26clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7722.o 28clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7722.o
@@ -31,6 +33,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
31pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o 33pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o
32pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o 34pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o
33pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o 35pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
36pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
34 37
35obj-y += $(clock-y) 38obj-y += $(clock-y)
36obj-$(CONFIG_SMP) += $(smp-y) 39obj-$(CONFIG_SMP) += $(smp-y)
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
new file mode 100644
index 000000000000..f84a9c134471
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -0,0 +1,148 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/clock-sh7786.c
3 *
4 * SH7786 support for the clock framework
5 *
6 * Copyright (C) 2008, 2009 Renesas Solutions Corp.
7 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 *
9 * Based on SH7785
10 * Copyright (C) 2007 Paul Mundt
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
15 */
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <asm/clock.h>
19#include <asm/freq.h>
20#include <asm/io.h>
21
22static int ifc_divisors[] = { 1, 2, 4, 1 };
23static int sfc_divisors[] = { 1, 1, 4, 1 };
24static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 1,
25 24, 32, 1, 1, 1, 1, 1, 1 };
26static int mfc_divisors[] = { 1, 1, 4, 1 };
27static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 16, 1,
28 24, 32, 1, 48, 1, 1, 1, 1 };
29
30static void master_clk_init(struct clk *clk)
31{
32 clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
33}
34
35static struct clk_ops sh7786_master_clk_ops = {
36 .init = master_clk_init,
37};
38
39static void module_clk_recalc(struct clk *clk)
40{
41 int idx = (ctrl_inl(FRQMR1) & 0x000f);
42 clk->rate = clk->parent->rate / pfc_divisors[idx];
43}
44
45static struct clk_ops sh7786_module_clk_ops = {
46 .recalc = module_clk_recalc,
47};
48
49static void bus_clk_recalc(struct clk *clk)
50{
51 int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
52 clk->rate = clk->parent->rate / bfc_divisors[idx];
53}
54
55static struct clk_ops sh7786_bus_clk_ops = {
56 .recalc = bus_clk_recalc,
57};
58
59static void cpu_clk_recalc(struct clk *clk)
60{
61 int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
62 clk->rate = clk->parent->rate / ifc_divisors[idx];
63}
64
65static struct clk_ops sh7786_cpu_clk_ops = {
66 .recalc = cpu_clk_recalc,
67};
68
69static struct clk_ops *sh7786_clk_ops[] = {
70 &sh7786_master_clk_ops,
71 &sh7786_module_clk_ops,
72 &sh7786_bus_clk_ops,
73 &sh7786_cpu_clk_ops,
74};
75
76void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
77{
78 if (idx < ARRAY_SIZE(sh7786_clk_ops))
79 *ops = sh7786_clk_ops[idx];
80}
81
82static void shyway_clk_recalc(struct clk *clk)
83{
84 int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
85 clk->rate = clk->parent->rate / sfc_divisors[idx];
86}
87
88static struct clk_ops sh7786_shyway_clk_ops = {
89 .recalc = shyway_clk_recalc,
90};
91
92static struct clk sh7786_shyway_clk = {
93 .name = "shyway_clk",
94 .flags = CLK_ALWAYS_ENABLED,
95 .ops = &sh7786_shyway_clk_ops,
96};
97
98static void ddr_clk_recalc(struct clk *clk)
99{
100 int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
101 clk->rate = clk->parent->rate / mfc_divisors[idx];
102}
103
104static struct clk_ops sh7786_ddr_clk_ops = {
105 .recalc = ddr_clk_recalc,
106};
107
108static struct clk sh7786_ddr_clk = {
109 .name = "ddr_clk",
110 .flags = CLK_ALWAYS_ENABLED,
111 .ops = &sh7786_ddr_clk_ops,
112};
113
114/*
115 * Additional SH7786-specific on-chip clocks that aren't already part of the
116 * clock framework
117 */
118static struct clk *sh7786_onchip_clocks[] = {
119 &sh7786_shyway_clk,
120 &sh7786_ddr_clk,
121};
122
123static int __init sh7786_clk_init(void)
124{
125 struct clk *clk = clk_get(NULL, "master_clk");
126 int i;
127
128 for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
129 struct clk *clkp = sh7786_onchip_clocks[i];
130
131 clkp->parent = clk;
132 clk_register(clkp);
133 clk_enable(clkp);
134 }
135
136 /*
137 * Now that we have the rest of the clocks registered, we need to
138 * force the parent clock to propagate so that these clocks will
139 * automatically figure out their rate. We cheat by handing the
140 * parent clock its current rate and forcing child propagation.
141 */
142 clk_set_rate(clk, clk_get_rate(clk));
143
144 clk_put(clk);
145
146 return 0;
147}
148arch_initcall(sh7786_clk_init);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
new file mode 100644
index 000000000000..373b3447bfdf
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
@@ -0,0 +1,950 @@
1/*
2 * SH7786 Pinmux
3 *
4 * Copyright (C) 2008, 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on SH7785 pinmux
8 *
9 * Copyright (C) 2008 Magnus Damm
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/gpio.h>
19#include <cpu/sh7786.h>
20
21enum {
22 PINMUX_RESERVED = 0,
23
24 PINMUX_DATA_BEGIN,
25 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
26 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
27 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
28 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
29 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
30 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
31 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
32 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
33 PE7_DATA, PE6_DATA,
34 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
35 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
36 PG7_DATA, PG6_DATA, PG5_DATA,
37 PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
38 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
39 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
40 PJ3_DATA, PJ2_DATA, PJ1_DATA,
41 PINMUX_DATA_END,
42
43 PINMUX_INPUT_BEGIN,
44 PA7_IN, PA6_IN, PA5_IN, PA4_IN,
45 PA3_IN, PA2_IN, PA1_IN, PA0_IN,
46 PB7_IN, PB6_IN, PB5_IN, PB4_IN,
47 PB3_IN, PB2_IN, PB1_IN, PB0_IN,
48 PC7_IN, PC6_IN, PC5_IN, PC4_IN,
49 PC3_IN, PC2_IN, PC1_IN, PC0_IN,
50 PD7_IN, PD6_IN, PD5_IN, PD4_IN,
51 PD3_IN, PD2_IN, PD1_IN, PD0_IN,
52 PE7_IN, PE6_IN,
53 PF7_IN, PF6_IN, PF5_IN, PF4_IN,
54 PF3_IN, PF2_IN, PF1_IN, PF0_IN,
55 PG7_IN, PG6_IN, PG5_IN,
56 PH7_IN, PH6_IN, PH5_IN, PH4_IN,
57 PH3_IN, PH2_IN, PH1_IN, PH0_IN,
58 PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
59 PJ3_IN, PJ2_IN, PJ1_IN,
60 PINMUX_INPUT_END,
61
62 PINMUX_INPUT_PULLUP_BEGIN,
63 PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
64 PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
65 PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
66 PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
67 PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
68 PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
69 PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
70 PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
71 PE7_IN_PU, PE6_IN_PU,
72 PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
73 PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
74 PG7_IN_PU, PG6_IN_PU, PG5_IN_PU,
75 PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU,
76 PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
77 PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU,
78 PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU,
79 PINMUX_INPUT_PULLUP_END,
80
81 PINMUX_OUTPUT_BEGIN,
82 PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
83 PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
84 PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
85 PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
86 PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
87 PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
88 PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
89 PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
90 PE7_OUT, PE6_OUT,
91 PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
92 PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
93 PG7_OUT, PG6_OUT, PG5_OUT,
94 PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT,
95 PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
96 PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
97 PJ3_OUT, PJ2_OUT, PJ1_OUT,
98 PINMUX_OUTPUT_END,
99
100 PINMUX_FUNCTION_BEGIN,
101 PA7_FN, PA6_FN, PA5_FN, PA4_FN,
102 PA3_FN, PA2_FN, PA1_FN, PA0_FN,
103 PB7_FN, PB6_FN, PB5_FN, PB4_FN,
104 PB3_FN, PB2_FN, PB1_FN, PB0_FN,
105 PC7_FN, PC6_FN, PC5_FN, PC4_FN,
106 PC3_FN, PC2_FN, PC1_FN, PC0_FN,
107 PD7_FN, PD6_FN, PD5_FN, PD4_FN,
108 PD3_FN, PD2_FN, PD1_FN, PD0_FN,
109 PE7_FN, PE6_FN,
110 PF7_FN, PF6_FN, PF5_FN, PF4_FN,
111 PF3_FN, PF2_FN, PF1_FN, PF0_FN,
112 PG7_FN, PG6_FN, PG5_FN,
113 PH7_FN, PH6_FN, PH5_FN, PH4_FN,
114 PH3_FN, PH2_FN, PH1_FN, PH0_FN,
115 PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN,
116 PJ3_FN, PJ2_FN, PJ1_FN,
117 P1MSEL14_0, P1MSEL14_1,
118 P1MSEL13_0, P1MSEL13_1,
119 P1MSEL12_0, P1MSEL12_1,
120 P1MSEL11_0, P1MSEL11_1,
121 P1MSEL10_0, P1MSEL10_1,
122 P1MSEL9_0, P1MSEL9_1,
123 P1MSEL8_0, P1MSEL8_1,
124 P1MSEL7_0, P1MSEL7_1,
125 P1MSEL6_0, P1MSEL6_1,
126 P1MSEL5_0, P1MSEL5_1,
127 P1MSEL4_0, P1MSEL4_1,
128 P1MSEL3_0, P1MSEL3_1,
129 P1MSEL2_0, P1MSEL2_1,
130 P1MSEL1_0, P1MSEL1_1,
131 P1MSEL0_0, P1MSEL0_1,
132
133 P2MSEL15_0, P2MSEL15_1,
134 P2MSEL14_0, P2MSEL14_1,
135 P2MSEL13_0, P2MSEL13_1,
136 P2MSEL12_0, P2MSEL12_1,
137 P2MSEL11_0, P2MSEL11_1,
138 P2MSEL10_0, P2MSEL10_1,
139 P2MSEL9_0, P2MSEL9_1,
140 P2MSEL8_0, P2MSEL8_1,
141 P2MSEL7_0, P2MSEL7_1,
142 P2MSEL6_0, P2MSEL6_1,
143 P2MSEL5_0, P2MSEL5_1,
144 P2MSEL4_0, P2MSEL4_1,
145 P2MSEL3_0, P2MSEL3_1,
146 P2MSEL2_0, P2MSEL2_1,
147 P2MSEL1_0, P2MSEL1_1,
148 P2MSEL0_0, P2MSEL0_1,
149 PINMUX_FUNCTION_END,
150
151 PINMUX_MARK_BEGIN,
152 CDE_MARK,
153 ETH_MAGIC_MARK,
154 DISP_MARK,
155 ETH_LINK_MARK,
156 DR5_MARK,
157 ETH_TX_ER_MARK,
158 DR4_MARK,
159 ETH_TX_EN_MARK,
160 DR3_MARK,
161 ETH_TXD3_MARK,
162 DR2_MARK,
163 ETH_TXD2_MARK,
164 DR1_MARK,
165 ETH_TXD1_MARK,
166 DR0_MARK,
167 ETH_TXD0_MARK,
168
169 VSYNC_MARK,
170 HSPI_CLK_MARK,
171 ODDF_MARK,
172 HSPI_CS_MARK,
173 DG5_MARK,
174 ETH_MDIO_MARK,
175 DG4_MARK,
176 ETH_RX_CLK_MARK,
177 DG3_MARK,
178 ETH_MDC_MARK,
179 DG2_MARK,
180 ETH_COL_MARK,
181 DG1_MARK,
182 ETH_TX_CLK_MARK,
183 DG0_MARK,
184 ETH_CRS_MARK,
185
186 DCLKIN_MARK,
187 HSPI_RX_MARK,
188 HSYNC_MARK,
189 HSPI_TX_MARK,
190 DB5_MARK,
191 ETH_RXD3_MARK,
192 DB4_MARK,
193 ETH_RXD2_MARK,
194 DB3_MARK,
195 ETH_RXD1_MARK,
196 DB2_MARK,
197 ETH_RXD0_MARK,
198 DB1_MARK,
199 ETH_RX_DV_MARK,
200 DB0_MARK,
201 ETH_RX_ER_MARK,
202
203 DCLKOUT_MARK,
204 SCIF1_SLK_MARK,
205 SCIF1_RXD_MARK,
206 SCIF1_TXD_MARK,
207 DACK1_MARK,
208 BACK_MARK,
209 FALE_MARK,
210 DACK0_MARK,
211 FCLE_MARK,
212 DREQ1_MARK,
213 BREQ_MARK,
214 USB_OVC1_MARK,
215 DREQ0_MARK,
216 USB_OVC0_MARK,
217
218 USB_PENC1_MARK,
219 USB_PENC0_MARK,
220
221 HAC1_SDOUT_MARK,
222 SSI1_SDATA_MARK,
223 SDIF1CMD_MARK,
224 HAC1_SDIN_MARK,
225 SSI1_SCK_MARK,
226 SDIF1CD_MARK,
227 HAC1_SYNC_MARK,
228 SSI1_WS_MARK,
229 SDIF1WP_MARK,
230 HAC1_BITCLK_MARK,
231 SSI1_CLK_MARK,
232 SDIF1CLK_MARK,
233 HAC0_SDOUT_MARK,
234 SSI0_SDATA_MARK,
235 SDIF1D3_MARK,
236 HAC0_SDIN_MARK,
237 SSI0_SCK_MARK,
238 SDIF1D2_MARK,
239 HAC0_SYNC_MARK,
240 SSI0_WS_MARK,
241 SDIF1D1_MARK,
242 HAC0_BITCLK_MARK,
243 SSI0_CLK_MARK,
244 SDIF1D0_MARK,
245
246 SCIF3_SCK_MARK,
247 SSI2_SDATA_MARK,
248 SCIF3_RXD_MARK,
249 TCLK_MARK,
250 SSI2_SCK_MARK,
251 SCIF3_TXD_MARK,
252 HAC_RES_MARK,
253 SSI2_WS_MARK,
254
255 DACK3_MARK,
256 SDIF0CMD_MARK,
257 DACK2_MARK,
258 SDIF0CD_MARK,
259 DREQ3_MARK,
260 SDIF0WP_MARK,
261 SCIF0_CTS_MARK,
262 DREQ2_MARK,
263 SDIF0CLK_MARK,
264 SCIF0_RTS_MARK,
265 IRL7_MARK,
266 SDIF0D3_MARK,
267 SCIF0_SCK_MARK,
268 IRL6_MARK,
269 SDIF0D2_MARK,
270 SCIF0_RXD_MARK,
271 IRL5_MARK,
272 SDIF0D1_MARK,
273 SCIF0_TXD_MARK,
274 IRL4_MARK,
275 SDIF0D0_MARK,
276
277 SCIF5_SCK_MARK,
278 FRB_MARK,
279 SCIF5_RXD_MARK,
280 IOIS16_MARK,
281 SCIF5_TXD_MARK,
282 CE2B_MARK,
283 DRAK3_MARK,
284 CE2A_MARK,
285 SCIF4_SCK_MARK,
286 DRAK2_MARK,
287 SSI3_WS_MARK,
288 SCIF4_RXD_MARK,
289 DRAK1_MARK,
290 SSI3_SDATA_MARK,
291 FSTATUS_MARK,
292 SCIF4_TXD_MARK,
293 DRAK0_MARK,
294 SSI3_SCK_MARK,
295 FSE_MARK,
296 PINMUX_MARK_END,
297};
298
299static pinmux_enum_t pinmux_data[] = {
300
301 /* PA GPIO */
302 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
303 PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
304 PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
305 PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
306 PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
307 PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
308 PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
309 PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
310
311 /* PB GPIO */
312 PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
313 PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
314 PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
315 PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
316 PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
317 PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
318 PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
319 PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
320
321 /* PC GPIO */
322 PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
323 PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
324 PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
325 PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
326 PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
327 PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
328 PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
329 PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
330
331 /* PD GPIO */
332 PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
333 PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
334 PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
335 PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
336 PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
337 PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
338 PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
339 PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
340
341 /* PE GPIO */
342 PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
343 PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
344
345 /* PF GPIO */
346 PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
347 PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
348 PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
349 PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
350 PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
351 PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
352 PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
353 PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
354
355 /* PG GPIO */
356 PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
357 PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
358 PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
359
360 /* PH GPIO */
361 PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU),
362 PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU),
363 PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
364 PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
365 PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
366 PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
367 PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
368 PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
369
370 /* PJ GPIO */
371 PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU),
372 PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU),
373 PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU),
374 PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU),
375 PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU),
376 PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU),
377 PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU),
378
379 /* PA FN */
380 PINMUX_MARK_BEGIN,
381 PINMUX_DATA(CDE_MARK, P1MSEL2_0, PA7_FN),
382 PINMUX_DATA(DISP_MARK, P1MSEL2_0, PA6_FN),
383 PINMUX_DATA(DR5_MARK, P1MSEL2_0, PA5_FN),
384 PINMUX_DATA(DR4_MARK, P1MSEL2_0, PA4_FN),
385 PINMUX_DATA(DR3_MARK, P1MSEL2_0, PA3_FN),
386 PINMUX_DATA(DR2_MARK, P1MSEL2_0, PA2_FN),
387 PINMUX_DATA(DR1_MARK, P1MSEL2_0, PA1_FN),
388 PINMUX_DATA(DR0_MARK, P1MSEL2_0, PA0_FN),
389 PINMUX_DATA(ETH_MAGIC_MARK, P1MSEL2_1, PA7_FN),
390 PINMUX_DATA(ETH_LINK_MARK, P1MSEL2_1, PA6_FN),
391 PINMUX_DATA(ETH_TX_ER_MARK, P1MSEL2_1, PA5_FN),
392 PINMUX_DATA(ETH_TX_EN_MARK, P1MSEL2_1, PA4_FN),
393 PINMUX_DATA(ETH_TXD3_MARK, P1MSEL2_1, PA3_FN),
394 PINMUX_DATA(ETH_TXD2_MARK, P1MSEL2_1, PA2_FN),
395 PINMUX_DATA(ETH_TXD1_MARK, P1MSEL2_1, PA1_FN),
396 PINMUX_DATA(ETH_TXD0_MARK, P1MSEL2_1, PA0_FN),
397
398 /* PB FN */
399 PINMUX_DATA(VSYNC_MARK, P1MSEL3_0, PB7_FN),
400 PINMUX_DATA(ODDF_MARK, P1MSEL3_0, PB6_FN),
401 PINMUX_DATA(DG5_MARK, P1MSEL2_0, PB5_FN),
402 PINMUX_DATA(DG4_MARK, P1MSEL2_0, PB4_FN),
403 PINMUX_DATA(DG3_MARK, P1MSEL2_0, PB3_FN),
404 PINMUX_DATA(DG2_MARK, P1MSEL2_0, PB2_FN),
405 PINMUX_DATA(DG1_MARK, P1MSEL2_0, PB1_FN),
406 PINMUX_DATA(DG0_MARK, P1MSEL2_0, PB0_FN),
407 PINMUX_DATA(HSPI_CLK_MARK, P1MSEL3_1, PB7_FN),
408 PINMUX_DATA(HSPI_CS_MARK, P1MSEL3_1, PB6_FN),
409 PINMUX_DATA(ETH_MDIO_MARK, P1MSEL2_1, PB5_FN),
410 PINMUX_DATA(ETH_RX_CLK_MARK, P1MSEL2_1, PB4_FN),
411 PINMUX_DATA(ETH_MDC_MARK, P1MSEL2_1, PB3_FN),
412 PINMUX_DATA(ETH_COL_MARK, P1MSEL2_1, PB2_FN),
413 PINMUX_DATA(ETH_TX_CLK_MARK, P1MSEL2_1, PB1_FN),
414 PINMUX_DATA(ETH_CRS_MARK, P1MSEL2_1, PB0_FN),
415
416 /* PC FN */
417 PINMUX_DATA(DCLKIN_MARK, P1MSEL3_0, PC7_FN),
418 PINMUX_DATA(HSYNC_MARK, P1MSEL3_0, PC6_FN),
419 PINMUX_DATA(DB5_MARK, P1MSEL2_0, PC5_FN),
420 PINMUX_DATA(DB4_MARK, P1MSEL2_0, PC4_FN),
421 PINMUX_DATA(DB3_MARK, P1MSEL2_0, PC3_FN),
422 PINMUX_DATA(DB2_MARK, P1MSEL2_0, PC2_FN),
423 PINMUX_DATA(DB1_MARK, P1MSEL2_0, PC1_FN),
424 PINMUX_DATA(DB0_MARK, P1MSEL2_0, PC0_FN),
425
426 PINMUX_DATA(HSPI_RX_MARK, P1MSEL3_1, PC7_FN),
427 PINMUX_DATA(HSPI_TX_MARK, P1MSEL3_1, PC6_FN),
428 PINMUX_DATA(ETH_RXD3_MARK, P1MSEL2_1, PC5_FN),
429 PINMUX_DATA(ETH_RXD2_MARK, P1MSEL2_1, PC4_FN),
430 PINMUX_DATA(ETH_RXD1_MARK, P1MSEL2_1, PC3_FN),
431 PINMUX_DATA(ETH_RXD0_MARK, P1MSEL2_1, PC2_FN),
432 PINMUX_DATA(ETH_RX_DV_MARK, P1MSEL2_1, PC1_FN),
433 PINMUX_DATA(ETH_RX_ER_MARK, P1MSEL2_1, PC0_FN),
434
435 /* PD FN */
436 PINMUX_DATA(DCLKOUT_MARK, PD7_FN),
437 PINMUX_DATA(SCIF1_SLK_MARK, PD6_FN),
438 PINMUX_DATA(SCIF1_RXD_MARK, PD5_FN),
439 PINMUX_DATA(SCIF1_TXD_MARK, PD4_FN),
440 PINMUX_DATA(DACK1_MARK, P1MSEL13_1, P1MSEL12_0, PD3_FN),
441 PINMUX_DATA(BACK_MARK, P1MSEL13_0, P1MSEL12_1, PD3_FN),
442 PINMUX_DATA(FALE_MARK, P1MSEL13_0, P1MSEL12_0, PD3_FN),
443 PINMUX_DATA(DACK0_MARK, P1MSEL14_1, PD2_FN),
444 PINMUX_DATA(FCLE_MARK, P1MSEL14_0, PD2_FN),
445 PINMUX_DATA(DREQ1_MARK, P1MSEL10_0, P1MSEL9_1, PD1_FN),
446 PINMUX_DATA(BREQ_MARK, P1MSEL10_1, P1MSEL9_0, PD1_FN),
447 PINMUX_DATA(USB_OVC1_MARK, P1MSEL10_0, P1MSEL9_0, PD1_FN),
448 PINMUX_DATA(DREQ0_MARK, P1MSEL11_1, PD0_FN),
449 PINMUX_DATA(USB_OVC0_MARK, P1MSEL11_0, PD0_FN),
450
451 /* PE FN */
452 PINMUX_DATA(USB_PENC1_MARK, PE7_FN),
453 PINMUX_DATA(USB_PENC0_MARK, PE6_FN),
454
455 /* PF FN */
456 PINMUX_DATA(HAC1_SDOUT_MARK, P2MSEL15_0, P2MSEL14_0, PF7_FN),
457 PINMUX_DATA(HAC1_SDIN_MARK, P2MSEL15_0, P2MSEL14_0, PF6_FN),
458 PINMUX_DATA(HAC1_SYNC_MARK, P2MSEL15_0, P2MSEL14_0, PF5_FN),
459 PINMUX_DATA(HAC1_BITCLK_MARK, P2MSEL15_0, P2MSEL14_0, PF4_FN),
460 PINMUX_DATA(HAC0_SDOUT_MARK, P2MSEL13_0, P2MSEL12_0, PF3_FN),
461 PINMUX_DATA(HAC0_SDIN_MARK, P2MSEL13_0, P2MSEL12_0, PF2_FN),
462 PINMUX_DATA(HAC0_SYNC_MARK, P2MSEL13_0, P2MSEL12_0, PF1_FN),
463 PINMUX_DATA(HAC0_BITCLK_MARK, P2MSEL13_0, P2MSEL12_0, PF0_FN),
464 PINMUX_DATA(SSI1_SDATA_MARK, P2MSEL15_0, P2MSEL14_1, PF7_FN),
465 PINMUX_DATA(SSI1_SCK_MARK, P2MSEL15_0, P2MSEL14_1, PF6_FN),
466 PINMUX_DATA(SSI1_WS_MARK, P2MSEL15_0, P2MSEL14_1, PF5_FN),
467 PINMUX_DATA(SSI1_CLK_MARK, P2MSEL15_0, P2MSEL14_1, PF4_FN),
468 PINMUX_DATA(SSI0_SDATA_MARK, P2MSEL13_0, P2MSEL12_1, PF3_FN),
469 PINMUX_DATA(SSI0_SCK_MARK, P2MSEL13_0, P2MSEL12_1, PF2_FN),
470 PINMUX_DATA(SSI0_WS_MARK, P2MSEL13_0, P2MSEL12_1, PF1_FN),
471 PINMUX_DATA(SSI0_CLK_MARK, P2MSEL13_0, P2MSEL12_1, PF0_FN),
472 PINMUX_DATA(SDIF1CMD_MARK, P2MSEL15_1, P2MSEL14_0, PF7_FN),
473 PINMUX_DATA(SDIF1CD_MARK, P2MSEL15_1, P2MSEL14_0, PF6_FN),
474 PINMUX_DATA(SDIF1WP_MARK, P2MSEL15_1, P2MSEL14_0, PF5_FN),
475 PINMUX_DATA(SDIF1CLK_MARK, P2MSEL15_1, P2MSEL14_0, PF4_FN),
476 PINMUX_DATA(SDIF1D3_MARK, P2MSEL13_1, P2MSEL12_0, PF3_FN),
477 PINMUX_DATA(SDIF1D2_MARK, P2MSEL13_1, P2MSEL12_0, PF2_FN),
478 PINMUX_DATA(SDIF1D1_MARK, P2MSEL13_1, P2MSEL12_0, PF1_FN),
479 PINMUX_DATA(SDIF1D0_MARK, P2MSEL13_1, P2MSEL12_0, PF0_FN),
480
481 /* PG FN */
482 PINMUX_DATA(SCIF3_SCK_MARK, P1MSEL8_0, PG7_FN),
483 PINMUX_DATA(SSI2_SDATA_MARK, P1MSEL8_1, PG7_FN),
484 PINMUX_DATA(SCIF3_RXD_MARK, P1MSEL7_0, P1MSEL6_0, PG6_FN),
485 PINMUX_DATA(SSI2_SCK_MARK, P1MSEL7_1, P1MSEL6_0, PG6_FN),
486 PINMUX_DATA(TCLK_MARK, P1MSEL7_0, P1MSEL6_1, PG6_FN),
487 PINMUX_DATA(SCIF3_TXD_MARK, P1MSEL5_0, P1MSEL4_0, PG5_FN),
488 PINMUX_DATA(SSI2_WS_MARK, P1MSEL5_1, P1MSEL4_0, PG5_FN),
489 PINMUX_DATA(HAC_RES_MARK, P1MSEL5_0, P1MSEL4_1, PG5_FN),
490
491 /* PH FN */
492 PINMUX_DATA(DACK3_MARK, P2MSEL4_0, PH7_FN),
493 PINMUX_DATA(SDIF0CMD_MARK, P2MSEL4_1, PH7_FN),
494 PINMUX_DATA(DACK2_MARK, P2MSEL4_0, PH6_FN),
495 PINMUX_DATA(SDIF0CD_MARK, P2MSEL4_1, PH6_FN),
496 PINMUX_DATA(DREQ3_MARK, P2MSEL4_0, PH5_FN),
497 PINMUX_DATA(SDIF0WP_MARK, P2MSEL4_1, PH5_FN),
498 PINMUX_DATA(DREQ2_MARK, P2MSEL3_0, P2MSEL2_1, PH4_FN),
499 PINMUX_DATA(SDIF0CLK_MARK, P2MSEL3_1, P2MSEL2_0, PH4_FN),
500 PINMUX_DATA(SCIF0_CTS_MARK, P2MSEL3_0, P2MSEL2_0, PH4_FN),
501 PINMUX_DATA(SDIF0D3_MARK, P2MSEL1_1, P2MSEL0_0, PH3_FN),
502 PINMUX_DATA(SCIF0_RTS_MARK, P2MSEL1_0, P2MSEL0_0, PH3_FN),
503 PINMUX_DATA(IRL7_MARK, P2MSEL1_0, P2MSEL0_1, PH3_FN),
504 PINMUX_DATA(SDIF0D2_MARK, P2MSEL1_1, P2MSEL0_0, PH2_FN),
505 PINMUX_DATA(SCIF0_SCK_MARK, P2MSEL1_0, P2MSEL0_0, PH2_FN),
506 PINMUX_DATA(IRL6_MARK, P2MSEL1_0, P2MSEL0_1, PH2_FN),
507 PINMUX_DATA(SDIF0D1_MARK, P2MSEL1_1, P2MSEL0_0, PH1_FN),
508 PINMUX_DATA(SCIF0_RXD_MARK, P2MSEL1_0, P2MSEL0_0, PH1_FN),
509 PINMUX_DATA(IRL5_MARK, P2MSEL1_0, P2MSEL0_1, PH1_FN),
510 PINMUX_DATA(SDIF0D0_MARK, P2MSEL1_1, P2MSEL0_0, PH0_FN),
511 PINMUX_DATA(SCIF0_TXD_MARK, P2MSEL1_0, P2MSEL0_0, PH0_FN),
512 PINMUX_DATA(IRL4_MARK, P2MSEL1_0, P2MSEL0_1, PH0_FN),
513
514 /* PJ FN */
515 PINMUX_DATA(SCIF5_SCK_MARK, P2MSEL11_1, PJ7_FN),
516 PINMUX_DATA(FRB_MARK, P2MSEL11_0, PJ7_FN),
517 PINMUX_DATA(SCIF5_RXD_MARK, P2MSEL10_0, PJ6_FN),
518 PINMUX_DATA(IOIS16_MARK, P2MSEL10_1, PJ6_FN),
519 PINMUX_DATA(SCIF5_TXD_MARK, P2MSEL10_0, PJ5_FN),
520 PINMUX_DATA(CE2B_MARK, P2MSEL10_1, PJ5_FN),
521 PINMUX_DATA(DRAK3_MARK, P2MSEL7_0, PJ4_FN),
522 PINMUX_DATA(CE2A_MARK, P2MSEL7_1, PJ4_FN),
523 PINMUX_DATA(SCIF4_SCK_MARK, P2MSEL9_0, P2MSEL8_0, PJ3_FN),
524 PINMUX_DATA(DRAK2_MARK, P2MSEL9_0, P2MSEL8_1, PJ3_FN),
525 PINMUX_DATA(SSI3_WS_MARK, P2MSEL9_1, P2MSEL8_0, PJ3_FN),
526 PINMUX_DATA(SCIF4_RXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ2_FN),
527 PINMUX_DATA(DRAK1_MARK, P2MSEL6_0, P2MSEL5_1, PJ2_FN),
528 PINMUX_DATA(FSTATUS_MARK, P2MSEL6_0, P2MSEL5_0, PJ2_FN),
529 PINMUX_DATA(SSI3_SDATA_MARK, P2MSEL6_1, P2MSEL5_1, PJ2_FN),
530 PINMUX_DATA(SCIF4_TXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ1_FN),
531 PINMUX_DATA(DRAK0_MARK, P2MSEL6_0, P2MSEL5_1, PJ1_FN),
532 PINMUX_DATA(FSE_MARK, P2MSEL6_0, P2MSEL5_0, PJ1_FN),
533 PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN),
534};
535
536static struct pinmux_gpio pinmux_gpios[] = {
537 /* PA */
538 PINMUX_GPIO(GPIO_PA7, PA7_DATA),
539 PINMUX_GPIO(GPIO_PA6, PA6_DATA),
540 PINMUX_GPIO(GPIO_PA5, PA5_DATA),
541 PINMUX_GPIO(GPIO_PA4, PA4_DATA),
542 PINMUX_GPIO(GPIO_PA3, PA3_DATA),
543 PINMUX_GPIO(GPIO_PA2, PA2_DATA),
544 PINMUX_GPIO(GPIO_PA1, PA1_DATA),
545 PINMUX_GPIO(GPIO_PA0, PA0_DATA),
546
547 /* PB */
548 PINMUX_GPIO(GPIO_PB7, PB7_DATA),
549 PINMUX_GPIO(GPIO_PB6, PB6_DATA),
550 PINMUX_GPIO(GPIO_PB5, PB5_DATA),
551 PINMUX_GPIO(GPIO_PB4, PB4_DATA),
552 PINMUX_GPIO(GPIO_PB3, PB3_DATA),
553 PINMUX_GPIO(GPIO_PB2, PB2_DATA),
554 PINMUX_GPIO(GPIO_PB1, PB1_DATA),
555 PINMUX_GPIO(GPIO_PB0, PB0_DATA),
556
557 /* PC */
558 PINMUX_GPIO(GPIO_PC7, PC7_DATA),
559 PINMUX_GPIO(GPIO_PC6, PC6_DATA),
560 PINMUX_GPIO(GPIO_PC5, PC5_DATA),
561 PINMUX_GPIO(GPIO_PC4, PC4_DATA),
562 PINMUX_GPIO(GPIO_PC3, PC3_DATA),
563 PINMUX_GPIO(GPIO_PC2, PC2_DATA),
564 PINMUX_GPIO(GPIO_PC1, PC1_DATA),
565 PINMUX_GPIO(GPIO_PC0, PC0_DATA),
566
567 /* PD */
568 PINMUX_GPIO(GPIO_PD7, PD7_DATA),
569 PINMUX_GPIO(GPIO_PD6, PD6_DATA),
570 PINMUX_GPIO(GPIO_PD5, PD5_DATA),
571 PINMUX_GPIO(GPIO_PD4, PD4_DATA),
572 PINMUX_GPIO(GPIO_PD3, PD3_DATA),
573 PINMUX_GPIO(GPIO_PD2, PD2_DATA),
574 PINMUX_GPIO(GPIO_PD1, PD1_DATA),
575 PINMUX_GPIO(GPIO_PD0, PD0_DATA),
576
577 /* PE */
578 PINMUX_GPIO(GPIO_PE5, PE7_DATA),
579 PINMUX_GPIO(GPIO_PE4, PE6_DATA),
580
581 /* PF */
582 PINMUX_GPIO(GPIO_PF7, PF7_DATA),
583 PINMUX_GPIO(GPIO_PF6, PF6_DATA),
584 PINMUX_GPIO(GPIO_PF5, PF5_DATA),
585 PINMUX_GPIO(GPIO_PF4, PF4_DATA),
586 PINMUX_GPIO(GPIO_PF3, PF3_DATA),
587 PINMUX_GPIO(GPIO_PF2, PF2_DATA),
588 PINMUX_GPIO(GPIO_PF1, PF1_DATA),
589 PINMUX_GPIO(GPIO_PF0, PF0_DATA),
590
591 /* PG */
592 PINMUX_GPIO(GPIO_PG7, PG7_DATA),
593 PINMUX_GPIO(GPIO_PG6, PG6_DATA),
594 PINMUX_GPIO(GPIO_PG5, PG5_DATA),
595
596 /* PH */
597 PINMUX_GPIO(GPIO_PH7, PH7_DATA),
598 PINMUX_GPIO(GPIO_PH6, PH6_DATA),
599 PINMUX_GPIO(GPIO_PH5, PH5_DATA),
600 PINMUX_GPIO(GPIO_PH4, PH4_DATA),
601 PINMUX_GPIO(GPIO_PH3, PH3_DATA),
602 PINMUX_GPIO(GPIO_PH2, PH2_DATA),
603 PINMUX_GPIO(GPIO_PH1, PH1_DATA),
604 PINMUX_GPIO(GPIO_PH0, PH0_DATA),
605
606 /* PJ */
607 PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
608 PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
609 PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
610 PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
611 PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
612 PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
613 PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
614
615 /* FN */
616 PINMUX_GPIO(GPIO_FN_CDE, CDE_MARK),
617 PINMUX_GPIO(GPIO_FN_ETH_MAGIC, ETH_MAGIC_MARK),
618 PINMUX_GPIO(GPIO_FN_DISP, DISP_MARK),
619 PINMUX_GPIO(GPIO_FN_ETH_LINK, ETH_LINK_MARK),
620 PINMUX_GPIO(GPIO_FN_DR5, DR5_MARK),
621 PINMUX_GPIO(GPIO_FN_ETH_TX_ER, ETH_TX_ER_MARK),
622 PINMUX_GPIO(GPIO_FN_DR4, DR4_MARK),
623 PINMUX_GPIO(GPIO_FN_ETH_TX_EN, ETH_TX_EN_MARK),
624 PINMUX_GPIO(GPIO_FN_DR3, DR3_MARK),
625 PINMUX_GPIO(GPIO_FN_ETH_TXD3, ETH_TXD3_MARK),
626 PINMUX_GPIO(GPIO_FN_DR2, DR2_MARK),
627 PINMUX_GPIO(GPIO_FN_ETH_TXD2, ETH_TXD2_MARK),
628 PINMUX_GPIO(GPIO_FN_DR1, DR1_MARK),
629 PINMUX_GPIO(GPIO_FN_ETH_TXD1, ETH_TXD1_MARK),
630 PINMUX_GPIO(GPIO_FN_DR0, DR0_MARK),
631 PINMUX_GPIO(GPIO_FN_ETH_TXD0, ETH_TXD0_MARK),
632 PINMUX_GPIO(GPIO_FN_VSYNC, VSYNC_MARK),
633 PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK),
634 PINMUX_GPIO(GPIO_FN_ODDF, ODDF_MARK),
635 PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK),
636 PINMUX_GPIO(GPIO_FN_DG5, DG5_MARK),
637 PINMUX_GPIO(GPIO_FN_ETH_MDIO, ETH_MDIO_MARK),
638 PINMUX_GPIO(GPIO_FN_DG4, DG4_MARK),
639 PINMUX_GPIO(GPIO_FN_ETH_RX_CLK, ETH_RX_CLK_MARK),
640 PINMUX_GPIO(GPIO_FN_DG3, DG3_MARK),
641 PINMUX_GPIO(GPIO_FN_ETH_MDC, ETH_MDC_MARK),
642 PINMUX_GPIO(GPIO_FN_DG2, DG2_MARK),
643 PINMUX_GPIO(GPIO_FN_ETH_COL, ETH_COL_MARK),
644 PINMUX_GPIO(GPIO_FN_DG1, DG1_MARK),
645 PINMUX_GPIO(GPIO_FN_ETH_TX_CLK, ETH_TX_CLK_MARK),
646 PINMUX_GPIO(GPIO_FN_DG0, DG0_MARK),
647 PINMUX_GPIO(GPIO_FN_ETH_CRS, ETH_CRS_MARK),
648 PINMUX_GPIO(GPIO_FN_DCLKIN, DCLKIN_MARK),
649 PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK),
650 PINMUX_GPIO(GPIO_FN_HSYNC, HSYNC_MARK),
651 PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK),
652 PINMUX_GPIO(GPIO_FN_DB5, DB5_MARK),
653 PINMUX_GPIO(GPIO_FN_ETH_RXD3, ETH_RXD3_MARK),
654 PINMUX_GPIO(GPIO_FN_DB4, DB4_MARK),
655 PINMUX_GPIO(GPIO_FN_ETH_RXD2, ETH_RXD2_MARK),
656 PINMUX_GPIO(GPIO_FN_DB3, DB3_MARK),
657 PINMUX_GPIO(GPIO_FN_ETH_RXD1, ETH_RXD1_MARK),
658 PINMUX_GPIO(GPIO_FN_DB2, DB2_MARK),
659 PINMUX_GPIO(GPIO_FN_ETH_RXD0, ETH_RXD0_MARK),
660 PINMUX_GPIO(GPIO_FN_DB1, DB1_MARK),
661 PINMUX_GPIO(GPIO_FN_ETH_RX_DV, ETH_RX_DV_MARK),
662 PINMUX_GPIO(GPIO_FN_DB0, DB0_MARK),
663 PINMUX_GPIO(GPIO_FN_ETH_RX_ER, ETH_RX_ER_MARK),
664 PINMUX_GPIO(GPIO_FN_DCLKOUT, DCLKOUT_MARK),
665 PINMUX_GPIO(GPIO_FN_SCIF1_SLK, SCIF1_SLK_MARK),
666 PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
667 PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
668 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
669 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
670 PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK),
671 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
672 PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK),
673 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
674 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
675 PINMUX_GPIO(GPIO_FN_USB_OVC1, USB_OVC1_MARK),
676 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
677 PINMUX_GPIO(GPIO_FN_USB_OVC0, USB_OVC0_MARK),
678 PINMUX_GPIO(GPIO_FN_USB_PENC1, USB_PENC1_MARK),
679 PINMUX_GPIO(GPIO_FN_USB_PENC0, USB_PENC0_MARK),
680 PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK),
681 PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK),
682 PINMUX_GPIO(GPIO_FN_SDIF1CMD, SDIF1CMD_MARK),
683 PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK),
684 PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK),
685 PINMUX_GPIO(GPIO_FN_SDIF1CD, SDIF1CD_MARK),
686 PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK),
687 PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK),
688 PINMUX_GPIO(GPIO_FN_SDIF1WP, SDIF1WP_MARK),
689 PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK),
690 PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK),
691 PINMUX_GPIO(GPIO_FN_SDIF1CLK, SDIF1CLK_MARK),
692 PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK),
693 PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK),
694 PINMUX_GPIO(GPIO_FN_SDIF1D3, SDIF1D3_MARK),
695 PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK),
696 PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK),
697 PINMUX_GPIO(GPIO_FN_SDIF1D2, SDIF1D2_MARK),
698 PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK),
699 PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK),
700 PINMUX_GPIO(GPIO_FN_SDIF1D1, SDIF1D1_MARK),
701 PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK),
702 PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK),
703 PINMUX_GPIO(GPIO_FN_SDIF1D0, SDIF1D0_MARK),
704 PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK),
705 PINMUX_GPIO(GPIO_FN_SSI2_SDATA, SSI2_SDATA_MARK),
706 PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK),
707 PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
708 PINMUX_GPIO(GPIO_FN_SSI2_SCK, SSI2_SCK_MARK),
709 PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK),
710 PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK),
711 PINMUX_GPIO(GPIO_FN_SSI2_WS, SSI2_WS_MARK),
712 PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
713 PINMUX_GPIO(GPIO_FN_SDIF0CMD, SDIF0CMD_MARK),
714 PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
715 PINMUX_GPIO(GPIO_FN_SDIF0CD, SDIF0CD_MARK),
716 PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
717 PINMUX_GPIO(GPIO_FN_SDIF0WP, SDIF0WP_MARK),
718 PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK),
719 PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
720 PINMUX_GPIO(GPIO_FN_SDIF0CLK, SDIF0CLK_MARK),
721 PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK),
722 PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK),
723 PINMUX_GPIO(GPIO_FN_SDIF0D3, SDIF0D3_MARK),
724 PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
725 PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK),
726 PINMUX_GPIO(GPIO_FN_SDIF0D2, SDIF0D2_MARK),
727 PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
728 PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK),
729 PINMUX_GPIO(GPIO_FN_SDIF0D1, SDIF0D1_MARK),
730 PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
731 PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK),
732 PINMUX_GPIO(GPIO_FN_SDIF0D0, SDIF0D0_MARK),
733 PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK),
734 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
735 PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK),
736 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
737 PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK),
738 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
739 PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK),
740 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
741 PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK),
742 PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK),
743 PINMUX_GPIO(GPIO_FN_SSI3_WS, SSI3_WS_MARK),
744 PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK),
745 PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK),
746 PINMUX_GPIO(GPIO_FN_SSI3_SDATA, SSI3_SDATA_MARK),
747 PINMUX_GPIO(GPIO_FN_FSTATUS, FSTATUS_MARK),
748 PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK),
749 PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK),
750 PINMUX_GPIO(GPIO_FN_SSI3_SCK, SSI3_SCK_MARK),
751 PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK),
752};
753
754static struct pinmux_cfg_reg pinmux_config_regs[] = {
755 { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) {
756 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
757 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
758 PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
759 PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
760 PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
761 PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
762 PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
763 PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU }
764 },
765 { PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2) {
766 PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
767 PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
768 PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
769 PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
770 PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
771 PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
772 PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
773 PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU }
774 },
775 { PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2) {
776 PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
777 PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
778 PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
779 PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
780 PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
781 PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
782 PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
783 PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU }
784 },
785 { PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2) {
786 PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
787 PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
788 PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
789 PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
790 PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
791 PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
792 PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
793 PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU }
794 },
795 { PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2) {
796 PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
797 PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
798 0, 0, 0, 0,
799 0, 0, 0, 0,
800 0, 0, 0, 0,
801 0, 0, 0, 0,
802 0, 0, 0, 0,
803 0, 0, 0, 0, }
804 },
805 { PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2) {
806 PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
807 PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
808 PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
809 PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
810 PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
811 PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
812 PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
813 PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU }
814 },
815 { PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2) {
816 PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
817 PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
818 PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
819 0, 0, 0, 0,
820 0, 0, 0, 0,
821 0, 0, 0, 0,
822 0, 0, 0, 0,
823 0, 0, 0, 0, }
824 },
825 { PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2) {
826 PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU,
827 PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU,
828 PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
829 PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
830 PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
831 PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
832 PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
833 PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU }
834 },
835 { PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2) {
836 PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU,
837 PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU,
838 PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU,
839 PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU,
840 PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU,
841 PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU,
842 PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU,
843 0, 0, 0, 0, }
844 },
845 { PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1) {
846 0, 0,
847 P1MSEL14_0, P1MSEL14_1,
848 P1MSEL13_0, P1MSEL13_1,
849 P1MSEL12_0, P1MSEL12_1,
850 P1MSEL11_0, P1MSEL11_1,
851 P1MSEL10_0, P1MSEL10_1,
852 P1MSEL9_0, P1MSEL9_1,
853 P1MSEL8_0, P1MSEL8_1,
854 P1MSEL7_0, P1MSEL7_1,
855 P1MSEL6_0, P1MSEL6_1,
856 P1MSEL5_0, P1MSEL5_1,
857 P1MSEL4_0, P1MSEL4_1,
858 P1MSEL3_0, P1MSEL3_1,
859 P1MSEL2_0, P1MSEL2_1,
860 P1MSEL1_0, P1MSEL1_1,
861 P1MSEL0_0, P1MSEL0_1 }
862 },
863 { PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1) {
864 P2MSEL15_0, P2MSEL15_1,
865 P2MSEL14_0, P2MSEL14_1,
866 P2MSEL13_0, P2MSEL13_1,
867 P2MSEL12_0, P2MSEL12_1,
868 P2MSEL11_0, P2MSEL11_1,
869 P2MSEL10_0, P2MSEL10_1,
870 P2MSEL9_0, P2MSEL9_1,
871 P2MSEL8_0, P2MSEL8_1,
872 P2MSEL7_0, P2MSEL7_1,
873 P2MSEL6_0, P2MSEL6_1,
874 P2MSEL5_0, P2MSEL5_1,
875 P2MSEL4_0, P2MSEL4_1,
876 P2MSEL3_0, P2MSEL3_1,
877 P2MSEL2_0, P2MSEL2_1,
878 P2MSEL1_0, P2MSEL1_1,
879 P2MSEL0_0, P2MSEL0_1 }
880 },
881 {}
882};
883
884static struct pinmux_data_reg pinmux_data_regs[] = {
885 { PINMUX_DATA_REG("PADR", 0xffcc0020, 8) {
886 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
887 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
888 },
889 { PINMUX_DATA_REG("PBDR", 0xffcc0022, 8) {
890 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
891 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA }
892 },
893 { PINMUX_DATA_REG("PCDR", 0xffcc0024, 8) {
894 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
895 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
896 },
897 { PINMUX_DATA_REG("PDDR", 0xffcc0026, 8) {
898 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
899 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
900 },
901 { PINMUX_DATA_REG("PEDR", 0xffcc0028, 8) {
902 PE7_DATA, PE6_DATA,
903 0, 0, 0, 0, 0, 0 }
904 },
905 { PINMUX_DATA_REG("PFDR", 0xffcc002a, 8) {
906 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
907 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
908 },
909 { PINMUX_DATA_REG("PGDR", 0xffcc002c, 8) {
910 PG7_DATA, PG6_DATA, PG5_DATA, 0,
911 0, 0, 0, 0 }
912 },
913 { PINMUX_DATA_REG("PHDR", 0xffcc002e, 8) {
914 PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
915 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA }
916 },
917 { PINMUX_DATA_REG("PJDR", 0xffcc0030, 8) {
918 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
919 PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 }
920 },
921 { },
922};
923
924static struct pinmux_info sh7786_pinmux_info = {
925 .name = "sh7786_pfc",
926 .reserved_id = PINMUX_RESERVED,
927 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
928 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
929 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
930 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
931 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
932 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
933
934 .first_gpio = GPIO_PA7,
935 .last_gpio = GPIO_FN_FSE,
936
937 .gpios = pinmux_gpios,
938 .cfg_regs = pinmux_config_regs,
939 .data_regs = pinmux_data_regs,
940
941 .gpio_data = pinmux_data,
942 .gpio_data_size = ARRAY_SIZE(pinmux_data),
943};
944
945static int __init plat_pinmux_setup(void)
946{
947 return register_pinmux(&sh7786_pinmux_info);
948}
949
950arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index 4ff4dc64520c..c1549382c87c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -12,6 +12,7 @@
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/uio_driver.h> 14#include <linux/uio_driver.h>
15#include <linux/sh_cmt.h>
15#include <asm/clock.h> 16#include <asm/clock.h>
16 17
17static struct resource iic0_resources[] = { 18static struct resource iic0_resources[] = {
@@ -140,6 +141,38 @@ static struct platform_device jpu_device = {
140 .num_resources = ARRAY_SIZE(jpu_resources), 141 .num_resources = ARRAY_SIZE(jpu_resources),
141}; 142};
142 143
144static struct sh_cmt_config cmt_platform_data = {
145 .name = "CMT",
146 .channel_offset = 0x60,
147 .timer_bit = 5,
148 .clk = "cmt0",
149 .clockevent_rating = 125,
150 .clocksource_rating = 200,
151};
152
153static struct resource cmt_resources[] = {
154 [0] = {
155 .name = "CMT",
156 .start = 0x044a0060,
157 .end = 0x044a006b,
158 .flags = IORESOURCE_MEM,
159 },
160 [1] = {
161 .start = 104,
162 .flags = IORESOURCE_IRQ,
163 },
164};
165
166static struct platform_device cmt_device = {
167 .name = "sh_cmt",
168 .id = 0,
169 .dev = {
170 .platform_data = &cmt_platform_data,
171 },
172 .resource = cmt_resources,
173 .num_resources = ARRAY_SIZE(cmt_resources),
174};
175
143static struct plat_sci_port sci_platform_data[] = { 176static struct plat_sci_port sci_platform_data[] = {
144 { 177 {
145 .mapbase = 0xffe00000, 178 .mapbase = 0xffe00000,
@@ -175,6 +208,7 @@ static struct platform_device sci_device = {
175}; 208};
176 209
177static struct platform_device *sh7343_devices[] __initdata = { 210static struct platform_device *sh7343_devices[] __initdata = {
211 &cmt_device,
178 &iic0_device, 212 &iic0_device,
179 &iic1_device, 213 &iic1_device,
180 &sci_device, 214 &sci_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 839ae97a7fd2..93ecf8ed5c6c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -14,6 +14,7 @@
14#include <linux/serial.h> 14#include <linux/serial.h>
15#include <linux/serial_sci.h> 15#include <linux/serial_sci.h>
16#include <linux/uio_driver.h> 16#include <linux/uio_driver.h>
17#include <linux/sh_cmt.h>
17#include <asm/clock.h> 18#include <asm/clock.h>
18 19
19static struct resource iic_resources[] = { 20static struct resource iic_resources[] = {
@@ -147,6 +148,38 @@ static struct platform_device veu1_device = {
147 .num_resources = ARRAY_SIZE(veu1_resources), 148 .num_resources = ARRAY_SIZE(veu1_resources),
148}; 149};
149 150
151static struct sh_cmt_config cmt_platform_data = {
152 .name = "CMT",
153 .channel_offset = 0x60,
154 .timer_bit = 5,
155 .clk = "cmt0",
156 .clockevent_rating = 125,
157 .clocksource_rating = 200,
158};
159
160static struct resource cmt_resources[] = {
161 [0] = {
162 .name = "CMT",
163 .start = 0x044a0060,
164 .end = 0x044a006b,
165 .flags = IORESOURCE_MEM,
166 },
167 [1] = {
168 .start = 104,
169 .flags = IORESOURCE_IRQ,
170 },
171};
172
173static struct platform_device cmt_device = {
174 .name = "sh_cmt",
175 .id = 0,
176 .dev = {
177 .platform_data = &cmt_platform_data,
178 },
179 .resource = cmt_resources,
180 .num_resources = ARRAY_SIZE(cmt_resources),
181};
182
150static struct plat_sci_port sci_platform_data[] = { 183static struct plat_sci_port sci_platform_data[] = {
151 { 184 {
152 .mapbase = 0xffe00000, 185 .mapbase = 0xffe00000,
@@ -167,6 +200,7 @@ static struct platform_device sci_device = {
167}; 200};
168 201
169static struct platform_device *sh7366_devices[] __initdata = { 202static struct platform_device *sh7366_devices[] __initdata = {
203 &cmt_device,
170 &iic_device, 204 &iic_device,
171 &sci_device, 205 &sci_device,
172 &usb_host_device, 206 &usb_host_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 5146afc156e0..0e5d204bc792 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -13,6 +13,7 @@
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/mm.h> 14#include <linux/mm.h>
15#include <linux/uio_driver.h> 15#include <linux/uio_driver.h>
16#include <linux/sh_cmt.h>
16#include <asm/clock.h> 17#include <asm/clock.h>
17#include <asm/mmzone.h> 18#include <asm/mmzone.h>
18 19
@@ -176,6 +177,38 @@ static struct platform_device jpu_device = {
176 .num_resources = ARRAY_SIZE(jpu_resources), 177 .num_resources = ARRAY_SIZE(jpu_resources),
177}; 178};
178 179
180static struct sh_cmt_config cmt_platform_data = {
181 .name = "CMT",
182 .channel_offset = 0x60,
183 .timer_bit = 5,
184 .clk = "cmt0",
185 .clockevent_rating = 125,
186 .clocksource_rating = 200,
187};
188
189static struct resource cmt_resources[] = {
190 [0] = {
191 .name = "CMT",
192 .start = 0x044a0060,
193 .end = 0x044a006b,
194 .flags = IORESOURCE_MEM,
195 },
196 [1] = {
197 .start = 104,
198 .flags = IORESOURCE_IRQ,
199 },
200};
201
202static struct platform_device cmt_device = {
203 .name = "sh_cmt",
204 .id = 0,
205 .dev = {
206 .platform_data = &cmt_platform_data,
207 },
208 .resource = cmt_resources,
209 .num_resources = ARRAY_SIZE(cmt_resources),
210};
211
179static struct plat_sci_port sci_platform_data[] = { 212static struct plat_sci_port sci_platform_data[] = {
180 { 213 {
181 .mapbase = 0xffe00000, 214 .mapbase = 0xffe00000,
@@ -209,6 +242,7 @@ static struct platform_device sci_device = {
209}; 242};
210 243
211static struct platform_device *sh7722_devices[] __initdata = { 244static struct platform_device *sh7722_devices[] __initdata = {
245 &cmt_device,
212 &rtc_device, 246 &rtc_device,
213 &usbf_device, 247 &usbf_device,
214 &iic_device, 248 &iic_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 849770d780ae..5338dacbcfba 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -13,6 +13,7 @@
13#include <linux/mm.h> 13#include <linux/mm.h>
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/uio_driver.h> 15#include <linux/uio_driver.h>
16#include <linux/sh_cmt.h>
16#include <asm/clock.h> 17#include <asm/clock.h>
17#include <asm/mmzone.h> 18#include <asm/mmzone.h>
18 19
@@ -100,6 +101,38 @@ static struct platform_device veu1_device = {
100 .num_resources = ARRAY_SIZE(veu1_resources), 101 .num_resources = ARRAY_SIZE(veu1_resources),
101}; 102};
102 103
104static struct sh_cmt_config cmt_platform_data = {
105 .name = "CMT",
106 .channel_offset = 0x60,
107 .timer_bit = 5,
108 .clk = "cmt0",
109 .clockevent_rating = 125,
110 .clocksource_rating = 200,
111};
112
113static struct resource cmt_resources[] = {
114 [0] = {
115 .name = "CMT",
116 .start = 0x044a0060,
117 .end = 0x044a006b,
118 .flags = IORESOURCE_MEM,
119 },
120 [1] = {
121 .start = 104,
122 .flags = IORESOURCE_IRQ,
123 },
124};
125
126static struct platform_device cmt_device = {
127 .name = "sh_cmt",
128 .id = 0,
129 .dev = {
130 .platform_data = &cmt_platform_data,
131 },
132 .resource = cmt_resources,
133 .num_resources = ARRAY_SIZE(cmt_resources),
134};
135
103static struct plat_sci_port sci_platform_data[] = { 136static struct plat_sci_port sci_platform_data[] = {
104 { 137 {
105 .mapbase = 0xffe00000, 138 .mapbase = 0xffe00000,
@@ -221,6 +254,7 @@ static struct platform_device iic_device = {
221}; 254};
222 255
223static struct platform_device *sh7723_devices[] __initdata = { 256static struct platform_device *sh7723_devices[] __initdata = {
257 &cmt_device,
224 &sci_device, 258 &sci_device,
225 &rtc_device, 259 &rtc_device,
226 &iic_device, 260 &iic_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 3c5b629887a8..bdf0f61ae1ed 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 2006 Paul Mundt 4 * Copyright (C) 2006 Paul Mundt
5 * Copyright (C) 2007 Yoshihiro Shimoda 5 * Copyright (C) 2007 Yoshihiro Shimoda
6 * Copyright (C) 2008 Nobuhiro Iwamatsu 6 * Copyright (C) 2008, 2009 Nobuhiro Iwamatsu
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -22,18 +22,8 @@ static struct resource rtc_resources[] = {
22 .flags = IORESOURCE_IO, 22 .flags = IORESOURCE_IO,
23 }, 23 },
24 [1] = { 24 [1] = {
25 /* Period IRQ */ 25 /* Shared Period/Carry/Alarm IRQ */
26 .start = 21, 26 .start = 20,
27 .flags = IORESOURCE_IRQ,
28 },
29 [2] = {
30 /* Carry IRQ */
31 .start = 22,
32 .flags = IORESOURCE_IRQ,
33 },
34 [3] = {
35 /* Alarm IRQ */
36 .start = 20,
37 .flags = IORESOURCE_IRQ, 27 .flags = IORESOURCE_IRQ,
38 }, 28 },
39}; 29};
@@ -50,17 +40,17 @@ static struct plat_sci_port sci_platform_data[] = {
50 .mapbase = 0xffe00000, 40 .mapbase = 0xffe00000,
51 .flags = UPF_BOOT_AUTOCONF, 41 .flags = UPF_BOOT_AUTOCONF,
52 .type = PORT_SCIF, 42 .type = PORT_SCIF,
53 .irqs = { 40, 41, 43, 42 }, 43 .irqs = { 40, 40, 40, 40 },
54 }, { 44 }, {
55 .mapbase = 0xffe08000, 45 .mapbase = 0xffe08000,
56 .flags = UPF_BOOT_AUTOCONF, 46 .flags = UPF_BOOT_AUTOCONF,
57 .type = PORT_SCIF, 47 .type = PORT_SCIF,
58 .irqs = { 76, 77, 79, 78 }, 48 .irqs = { 76, 76, 76, 76 },
59 }, { 49 }, {
60 .mapbase = 0xffe10000, 50 .mapbase = 0xffe10000,
61 .flags = UPF_BOOT_AUTOCONF, 51 .flags = UPF_BOOT_AUTOCONF,
62 .type = PORT_SCIF, 52 .type = PORT_SCIF,
63 .irqs = { 104, 105, 107, 106 }, 53 .irqs = { 104, 104, 104, 104 },
64 }, { 54 }, {
65 .flags = 0, 55 .flags = 0,
66 } 56 }
@@ -148,93 +138,65 @@ enum {
148 IRL_HHLL, IRL_HHLH, IRL_HHHL, 138 IRL_HHLL, IRL_HHLH, IRL_HHHL,
149 139
150 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 140 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
151 RTC_ATI, RTC_PRI, RTC_CUI, 141 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
152 WDT, TMU0, TMU1, TMU2, TMU2_TICPI, 142 HUDI, LCDC, DMAC, SCIF0, IIC0, IIC1, CMT, GETHER, HAC,
153 HUDI, LCDC, 143 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
154 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMAE, 144 STIF0, STIF1, SCIF1, SIOF0, SIOF1, SIOF2,
155 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI, 145 USBH, USBF, TPU, PCC, MMCIF, SIM,
156 DMAC0_DMINT4, DMAC0_DMINT5,
157 IIC0, IIC1,
158 CMT,
159 GEINT0, GEINT1, GEINT2,
160 HAC,
161 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
162 PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
163 STIF0, STIF1,
164 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
165 SIOF0, SIOF1, SIOF2,
166 USBH, USBFI0, USBFI1,
167 TPU, PCC,
168 MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
169 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND,
170 TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3, 146 TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3,
171 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, 147 SCIF2, GPIO,
172 GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3,
173 148
174 /* interrupt groups */ 149 /* interrupt groups */
175 150
176 TMU012, TMU345, RTC, DMAC, SCIF0, GETHER, PCIC5, 151 TMU012, TMU345,
177 SCIF1, USBF, MMCIF, SIM, SCIF2, GPIO,
178}; 152};
179 153
180static struct intc_vect vectors[] __initdata = { 154static struct intc_vect vectors[] __initdata = {
181 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 155 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
182 INTC_VECT(RTC_CUI, 0x4c0), 156 INTC_VECT(RTC, 0x4c0),
183 INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580), 157 INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
184 INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0), 158 INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),
185 INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600), 159 INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600),
186 INTC_VECT(LCDC, 0x620), 160 INTC_VECT(LCDC, 0x620),
187 INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660), 161 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
188 INTC_VECT(DMAC0_DMINT2, 0x680), INTC_VECT(DMAC0_DMINT3, 0x6a0), 162 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
189 INTC_VECT(DMAC0_DMAE, 0x6c0), 163 INTC_VECT(DMAC, 0x6c0),
190 INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720), 164 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
191 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760), 165 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
192 INTC_VECT(DMAC0_DMINT4, 0x780), INTC_VECT(DMAC0_DMINT5, 0x7a0), 166 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
193 INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0), 167 INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0),
194 INTC_VECT(CMT, 0x900), INTC_VECT(GEINT0, 0x920), 168 INTC_VECT(CMT, 0x900), INTC_VECT(GETHER, 0x920),
195 INTC_VECT(GEINT1, 0x940), INTC_VECT(GEINT2, 0x960), 169 INTC_VECT(GETHER, 0x940), INTC_VECT(GETHER, 0x960),
196 INTC_VECT(HAC, 0x980), 170 INTC_VECT(HAC, 0x980),
197 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), 171 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
198 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), 172 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
199 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0), 173 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
200 INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0), 174 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
201 INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20), 175 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
202 INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60), 176 INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60),
203 INTC_VECT(SCIF1_ERI, 0xb80), INTC_VECT(SCIF1_RXI, 0xba0), 177 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
204 INTC_VECT(SCIF1_BRI, 0xbc0), INTC_VECT(SCIF1_TXI, 0xbe0), 178 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
205 INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20), 179 INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20),
206 INTC_VECT(USBH, 0xc60), INTC_VECT(USBFI0, 0xc80), 180 INTC_VECT(USBH, 0xc60), INTC_VECT(USBF, 0xc80),
207 INTC_VECT(USBFI1, 0xca0), 181 INTC_VECT(USBF, 0xca0),
208 INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0), 182 INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),
209 INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20), 183 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
210 INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60), 184 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
211 INTC_VECT(SIM_ERI, 0xd80), INTC_VECT(SIM_RXI, 0xda0), 185 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
212 INTC_VECT(SIM_TXI, 0xdc0), INTC_VECT(SIM_TEND, 0xde0), 186 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
213 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 187 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
214 INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60), 188 INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60),
215 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0), 189 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
216 INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0), 190 INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0),
217 INTC_VECT(SCIF2_ERI, 0xf00), INTC_VECT(SCIF2_RXI, 0xf20), 191 INTC_VECT(SCIF2, 0xf00), INTC_VECT(SCIF2, 0xf20),
218 INTC_VECT(SCIF2_BRI, 0xf40), INTC_VECT(SCIF2_TXI, 0xf60), 192 INTC_VECT(SCIF2, 0xf40), INTC_VECT(SCIF2, 0xf60),
219 INTC_VECT(GPIO_CH0, 0xf80), INTC_VECT(GPIO_CH1, 0xfa0), 193 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
220 INTC_VECT(GPIO_CH2, 0xfc0), INTC_VECT(GPIO_CH3, 0xfe0), 194 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
221}; 195};
222 196
223static struct intc_group groups[] __initdata = { 197static struct intc_group groups[] __initdata = {
224 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 198 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
225 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 199 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
226 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
227 INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
228 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
229 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
230 INTC_GROUP(GETHER, GEINT0, GEINT1, GEINT2),
231 INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
232 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
233 INTC_GROUP(USBF, USBFI0, USBFI1),
234 INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
235 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND),
236 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
237 INTC_GROUP(GPIO, GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3),
238}; 200};
239 201
240static struct intc_mask_reg mask_registers[] __initdata = { 202static struct intc_mask_reg mask_registers[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index fb8200cc7440..6f7227cd65bf 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -20,17 +20,7 @@ static struct resource rtc_resources[] = {
20 .flags = IORESOURCE_IO, 20 .flags = IORESOURCE_IO,
21 }, 21 },
22 [1] = { 22 [1] = {
23 /* Period IRQ */ 23 /* Shared Period/Carry/Alarm IRQ */
24 .start = 21,
25 .flags = IORESOURCE_IRQ,
26 },
27 [2] = {
28 /* Carry IRQ */
29 .start = 22,
30 .flags = IORESOURCE_IRQ,
31 },
32 [3] = {
33 /* Alarm IRQ */
34 .start = 20, 24 .start = 20,
35 .flags = IORESOURCE_IRQ, 25 .flags = IORESOURCE_IRQ,
36 }, 26 },
@@ -48,12 +38,12 @@ static struct plat_sci_port sci_platform_data[] = {
48 .mapbase = 0xffe00000, 38 .mapbase = 0xffe00000,
49 .flags = UPF_BOOT_AUTOCONF, 39 .flags = UPF_BOOT_AUTOCONF,
50 .type = PORT_SCIF, 40 .type = PORT_SCIF,
51 .irqs = { 40, 41, 43, 42 }, 41 .irqs = { 40, 40, 40, 40 },
52 }, { 42 }, {
53 .mapbase = 0xffe10000, 43 .mapbase = 0xffe10000,
54 .flags = UPF_BOOT_AUTOCONF, 44 .flags = UPF_BOOT_AUTOCONF,
55 .type = PORT_SCIF, 45 .type = PORT_SCIF,
56 .irqs = { 76, 77, 79, 78 }, 46 .irqs = { 76, 76, 76, 76 },
57 }, { 47 }, {
58 .flags = 0, 48 .flags = 0,
59 } 49 }
@@ -90,82 +80,55 @@ enum {
90 IRL_HHLL, IRL_HHLH, IRL_HHHL, 80 IRL_HHLL, IRL_HHLH, IRL_HHHL,
91 81
92 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 82 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
93 RTC_ATI, RTC_PRI, RTC_CUI, 83 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
94 WDT, 84 HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC,
95 TMU0, TMU1, TMU2, TMU2_TICPI, 85 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
96 HUDI, 86 SCIF1, SIOF, HSPI, MMCIF, TMU3, TMU4, TMU5, SSI, FLCTL, GPIO,
97 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMAE,
98 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
99 DMAC0_DMINT4, DMAC0_DMINT5, DMAC1_DMINT6, DMAC1_DMINT7,
100 CMT, HAC,
101 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
102 PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
103 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
104 SIOF, HSPI,
105 MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
106 DMAC1_DMINT8, DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11,
107 TMU3, TMU4, TMU5,
108 SSI,
109 FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1,
110 GPIOI0, GPIOI1, GPIOI2, GPIOI3,
111 87
112 /* interrupt groups */ 88 /* interrupt groups */
113 89
114 RTC, TMU012, DMAC0, SCIF0, DMAC45, DMAC1, 90 TMU012, TMU345,
115 PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO,
116}; 91};
117 92
118static struct intc_vect vectors[] __initdata = { 93static struct intc_vect vectors[] __initdata = {
119 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 94 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
120 INTC_VECT(RTC_CUI, 0x4c0), 95 INTC_VECT(RTC, 0x4c0),
121 INTC_VECT(WDT, 0x560), 96 INTC_VECT(WDT, 0x560),
122 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), 97 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
123 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), 98 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
124 INTC_VECT(HUDI, 0x600), 99 INTC_VECT(HUDI, 0x600),
125 INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660), 100 INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
126 INTC_VECT(DMAC0_DMINT2, 0x680), INTC_VECT(DMAC0_DMINT3, 0x6a0), 101 INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
127 INTC_VECT(DMAC0_DMAE, 0x6c0), 102 INTC_VECT(DMAC0, 0x6c0),
128 INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720), 103 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
129 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760), 104 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
130 INTC_VECT(DMAC0_DMINT4, 0x780), INTC_VECT(DMAC0_DMINT5, 0x7a0), 105 INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
131 INTC_VECT(DMAC1_DMINT6, 0x7c0), INTC_VECT(DMAC1_DMINT7, 0x7e0), 106 INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0),
132 INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980), 107 INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
133 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), 108 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
134 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), 109 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
135 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0), 110 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
136 INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0), 111 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
137 INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20), 112 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
138 INTC_VECT(SCIF1_ERI, 0xb80), INTC_VECT(SCIF1_RXI, 0xba0), 113 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
139 INTC_VECT(SCIF1_BRI, 0xbc0), INTC_VECT(SCIF1_TXI, 0xbe0), 114 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
140 INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80), 115 INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
141 INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20), 116 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
142 INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60), 117 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
143 INTC_VECT(DMAC1_DMINT8, 0xd80), INTC_VECT(DMAC1_DMINT9, 0xda0), 118 INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0),
144 INTC_VECT(DMAC1_DMINT10, 0xdc0), INTC_VECT(DMAC1_DMINT11, 0xde0), 119 INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0),
145 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 120 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
146 INTC_VECT(TMU5, 0xe40), 121 INTC_VECT(TMU5, 0xe40),
147 INTC_VECT(SSI, 0xe80), 122 INTC_VECT(SSI, 0xe80),
148 INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20), 123 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
149 INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60), 124 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
150 INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0), 125 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
151 INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0), 126 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
152}; 127};
153 128
154static struct intc_group groups[] __initdata = { 129static struct intc_group groups[] __initdata = {
155 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
156 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 130 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
157 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
158 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
159 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
160 INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
161 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
162 INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
163 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
164 INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
165 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 131 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
166 INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
167 FLCTL_FLTRQ0, FLCTL_FLTRQ1),
168 INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
169}; 132};
170 133
171static struct intc_mask_reg mask_registers[] __initdata = { 134static struct intc_mask_reg mask_registers[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 30baa63b24c8..d80802a49dbd 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -20,18 +20,13 @@ static struct plat_sci_port sci_platform_data[] = {
20 .mapbase = 0xffea0000, 20 .mapbase = 0xffea0000,
21 .flags = UPF_BOOT_AUTOCONF, 21 .flags = UPF_BOOT_AUTOCONF,
22 .type = PORT_SCIF, 22 .type = PORT_SCIF,
23 .irqs = { 40, 41, 43, 42 }, 23 .irqs = { 40, 40, 40, 40 },
24 }, { 24 }, {
25 .mapbase = 0xffeb0000, 25 .mapbase = 0xffeb0000,
26 .flags = UPF_BOOT_AUTOCONF, 26 .flags = UPF_BOOT_AUTOCONF,
27 .type = PORT_SCIF, 27 .type = PORT_SCIF,
28 .irqs = { 44, 45, 47, 46 }, 28 .irqs = { 44, 44, 44, 44 },
29 }, 29 }, {
30
31 /*
32 * The rest of these all have multiplexed IRQs
33 */
34 {
35 .mapbase = 0xffec0000, 30 .mapbase = 0xffec0000,
36 .flags = UPF_BOOT_AUTOCONF, 31 .flags = UPF_BOOT_AUTOCONF,
37 .type = PORT_SCIF, 32 .type = PORT_SCIF,
@@ -91,33 +86,19 @@ enum {
91 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 86 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
92 87
93 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 88 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
94 WDT, 89 WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
95 TMU0, TMU1, TMU2, TMU2_TICPI, 90 HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
96 HUDI,
97 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
98 DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
99 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
100 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
101 DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
102 DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
103 HSPI,
104 SCIF2, SCIF3, SCIF4, SCIF5, 91 SCIF2, SCIF3, SCIF4, SCIF5,
105 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, 92 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
106 PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0, 93 SIOF, MMCIF, DU, GDTA,
107 SIOF,
108 MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
109 DU,
110 GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI,
111 TMU3, TMU4, TMU5, 94 TMU3, TMU4, TMU5,
112 SSI0, SSI1, 95 SSI0, SSI1,
113 HAC0, HAC1, 96 HAC0, HAC1,
114 FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1, 97 FLCTL, GPIO,
115 GPIOI0, GPIOI1, GPIOI2, GPIOI3,
116 98
117 /* interrupt groups */ 99 /* interrupt groups */
118 100
119 TMU012, DMAC0, SCIF0, SCIF1, DMAC1, 101 TMU012, TMU345
120 PCIC5, MMCIF, GDTA, TMU345, FLCTL, GPIO
121}; 102};
122 103
123static struct intc_vect vectors[] __initdata = { 104static struct intc_vect vectors[] __initdata = {
@@ -125,57 +106,45 @@ static struct intc_vect vectors[] __initdata = {
125 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), 106 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
126 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), 107 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
127 INTC_VECT(HUDI, 0x600), 108 INTC_VECT(HUDI, 0x600),
128 INTC_VECT(DMAC0_DMINT0, 0x620), INTC_VECT(DMAC0_DMINT1, 0x640), 109 INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
129 INTC_VECT(DMAC0_DMINT2, 0x660), INTC_VECT(DMAC0_DMINT3, 0x680), 110 INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
130 INTC_VECT(DMAC0_DMINT4, 0x6a0), INTC_VECT(DMAC0_DMINT5, 0x6c0), 111 INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
131 INTC_VECT(DMAC0_DMAE, 0x6e0), 112 INTC_VECT(DMAC0, 0x6e0),
132 INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720), 113 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
133 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760), 114 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
134 INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0), 115 INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
135 INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0), 116 INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
136 INTC_VECT(DMAC1_DMINT6, 0x880), INTC_VECT(DMAC1_DMINT7, 0x8a0), 117 INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
137 INTC_VECT(DMAC1_DMINT8, 0x8c0), INTC_VECT(DMAC1_DMINT9, 0x8e0), 118 INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
138 INTC_VECT(DMAC1_DMINT10, 0x900), INTC_VECT(DMAC1_DMINT11, 0x920), 119 INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
139 INTC_VECT(DMAC1_DMAE, 0x940), 120 INTC_VECT(DMAC1, 0x940),
140 INTC_VECT(HSPI, 0x960), 121 INTC_VECT(HSPI, 0x960),
141 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0), 122 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
142 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0), 123 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
143 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), 124 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
144 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), 125 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
145 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0), 126 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
146 INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0), 127 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
147 INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20), 128 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
148 INTC_VECT(SIOF, 0xc00), 129 INTC_VECT(SIOF, 0xc00),
149 INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20), 130 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
150 INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60), 131 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
151 INTC_VECT(DU, 0xd80), 132 INTC_VECT(DU, 0xd80),
152 INTC_VECT(GDTA_GACLI, 0xda0), INTC_VECT(GDTA_GAMCI, 0xdc0), 133 INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
153 INTC_VECT(GDTA_GAERI, 0xde0), 134 INTC_VECT(GDTA, 0xde0),
154 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 135 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
155 INTC_VECT(TMU5, 0xe40), 136 INTC_VECT(TMU5, 0xe40),
156 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0), 137 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
157 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0), 138 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
158 INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20), 139 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
159 INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60), 140 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
160 INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0), 141 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
161 INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0), 142 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
162}; 143};
163 144
164static struct intc_group groups[] __initdata = { 145static struct intc_group groups[] __initdata = {
165 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 146 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
166 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
167 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
168 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
169 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
170 INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
171 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE),
172 INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
173 INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
174 INTC_GROUP(GDTA, GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI),
175 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 147 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
176 INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
177 FLCTL_FLTRQ0, FLCTL_FLTRQ1),
178 INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
179}; 148};
180 149
181static struct intc_mask_reg mask_registers[] __initdata = { 150static struct intc_mask_reg mask_registers[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
new file mode 100644
index 000000000000..5a47e1cf442e
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -0,0 +1,490 @@
1/*
2 * SH7786 Setup
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on SH7785 Setup
8 *
9 * Copyright (C) 2007 Paul Mundt
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/platform_device.h>
16#include <linux/init.h>
17#include <linux/serial.h>
18#include <linux/serial_sci.h>
19#include <linux/io.h>
20#include <linux/mm.h>
21#include <linux/dma-mapping.h>
22#include <asm/mmzone.h>
23
24static struct plat_sci_port sci_platform_data[] = {
25 {
26 .mapbase = 0xffea0000,
27 .flags = UPF_BOOT_AUTOCONF,
28 .type = PORT_SCIF,
29 .irqs = { 40, 41, 43, 42 },
30 },
31 /*
32 * The rest of these all have multiplexed IRQs
33 */
34 {
35 .mapbase = 0xffeb0000,
36 .flags = UPF_BOOT_AUTOCONF,
37 .type = PORT_SCIF,
38 .irqs = { 44, 44, 44, 44 },
39 }, {
40 .mapbase = 0xffec0000,
41 .flags = UPF_BOOT_AUTOCONF,
42 .type = PORT_SCIF,
43 .irqs = { 50, 50, 50, 50 },
44 }, {
45 .mapbase = 0xffed0000,
46 .flags = UPF_BOOT_AUTOCONF,
47 .type = PORT_SCIF,
48 .irqs = { 51, 51, 51, 51 },
49 }, {
50 .mapbase = 0xffee0000,
51 .flags = UPF_BOOT_AUTOCONF,
52 .type = PORT_SCIF,
53 .irqs = { 52, 52, 52, 52 },
54 }, {
55 .mapbase = 0xffef0000,
56 .flags = UPF_BOOT_AUTOCONF,
57 .type = PORT_SCIF,
58 .irqs = { 53, 53, 53, 53 },
59 }, {
60 .flags = 0,
61 }
62};
63
64static struct platform_device sci_device = {
65 .name = "sh-sci",
66 .id = -1,
67 .dev = {
68 .platform_data = sci_platform_data,
69 },
70};
71
72static struct resource usb_ohci_resources[] = {
73 [0] = {
74 .start = 0xffe70400,
75 .end = 0xffe704ff,
76 .flags = IORESOURCE_MEM,
77 },
78 [1] = {
79 .start = 77,
80 .end = 77,
81 .flags = IORESOURCE_IRQ,
82 },
83};
84
85static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32);
86static struct platform_device usb_ohci_device = {
87 .name = "sh_ohci",
88 .id = -1,
89 .dev = {
90 .dma_mask = &usb_ohci_dma_mask,
91 .coherent_dma_mask = DMA_BIT_MASK(32),
92 },
93 .num_resources = ARRAY_SIZE(usb_ohci_resources),
94 .resource = usb_ohci_resources,
95};
96
97static struct platform_device *sh7786_devices[] __initdata = {
98 &sci_device,
99 &usb_ohci_device,
100};
101
102
103/*
104 * Please call this function if your platform board
105 * use external clock for USB
106 * */
107#define USBCTL0 0xffe70858
108#define CLOCK_MODE_MASK 0xffffff7f
109#define EXT_CLOCK_MODE 0x00000080
110void __init sh7786_usb_use_exclock(void)
111{
112 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
113 __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
114}
115
116#define USBINITREG1 0xffe70094
117#define USBINITREG2 0xffe7009c
118#define USBINITVAL1 0x00ff0040
119#define USBINITVAL2 0x00000001
120
121#define USBPCTL1 0xffe70804
122#define USBST 0xffe70808
123#define PHY_ENB 0x00000001
124#define PLL_ENB 0x00000002
125#define PHY_RST 0x00000004
126#define ACT_PLL_STATUS 0xc0000000
127static void __init sh7786_usb_setup(void)
128{
129 int i = 1000000;
130
131 /*
132 * USB initial settings
133 *
134 * The following settings are necessary
135 * for using the USB modules.
136 *
137 * see "USB Inital Settings" for detail
138 */
139 __raw_writel(USBINITVAL1, USBINITREG1);
140 __raw_writel(USBINITVAL2, USBINITREG2);
141
142 /*
143 * Set the PHY and PLL enable bit
144 */
145 __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
146 while (i-- &&
147 ((__raw_readl(USBST) & ACT_PLL_STATUS) != ACT_PLL_STATUS))
148 cpu_relax();
149
150 if (i) {
151 /* Set the PHY RST bit */
152 __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
153 printk(KERN_INFO "sh7786 usb setup done\n");
154 }
155}
156
157static int __init sh7786_devices_setup(void)
158{
159 sh7786_usb_setup();
160 return platform_add_devices(sh7786_devices,
161 ARRAY_SIZE(sh7786_devices));
162}
163device_initcall(sh7786_devices_setup);
164
165enum {
166 UNUSED = 0,
167
168 /* interrupt sources */
169
170 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
171 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
172 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
173 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
174
175 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
176 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
177 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
178 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
179
180 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
181 WDT,
182 TMU0_0, TMU0_1, TMU0_2, TMU0_3,
183 TMU1_0, TMU1_1, TMU1_2,
184 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
185 HUDI1, HUDI0,
186 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
187 HPB_0, HPB_1, HPB_2,
188 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
189 SCIF1,
190 TMU2, TMU3,
191 SCIF2, SCIF3, SCIF4, SCIF5,
192 Eth_0, Eth_1,
193 PCIeC0_0, PCIeC0_1, PCIeC0_2,
194 PCIeC1_0, PCIeC1_1, PCIeC1_2,
195 USB,
196 I2C0, I2C1,
197 DU,
198 SSI0, SSI1, SSI2, SSI3,
199 PCIeC2_0, PCIeC2_1, PCIeC2_2,
200 HAC0, HAC1,
201 FLCTL,
202 HSPI,
203 GPIO0, GPIO1,
204 Thermal,
205 INTC0, INTC1, INTC2, INTC3, INTC4, INTC5, INTC6, INTC7,
206
207 /* interrupt groups */
208};
209
210static struct intc_vect vectors[] __initdata = {
211 INTC_VECT(WDT, 0x3e0),
212 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
213 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
214 INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
215 INTC_VECT(TMU1_2, 0x4c0),
216 INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
217 INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
218 INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
219 INTC_VECT(DMAC0_6, 0x5c0),
220 INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
221 INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
222 INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
223 INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
224 INTC_VECT(HPB_2, 0x6e0),
225 INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
226 INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
227 INTC_VECT(SCIF1, 0x780),
228 INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
229 INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
230 INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
231 INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
232 INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
233 INTC_VECT(PCIeC0_2, 0xb20),
234 INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
235 INTC_VECT(PCIeC1_2, 0xb80),
236 INTC_VECT(USB, 0xba0),
237 INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
238 INTC_VECT(DU, 0xd00),
239 INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
240 INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
241 INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
242 INTC_VECT(PCIeC2_2, 0xde0),
243 INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
244 INTC_VECT(FLCTL, 0xe40),
245 INTC_VECT(HSPI, 0xe80),
246 INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
247 INTC_VECT(Thermal, 0xee0),
248};
249
250/* FIXME: Main CPU support only now */
251#if 1 /* Main CPU */
252#define CnINTMSK0 0xfe410030
253#define CnINTMSK1 0xfe410040
254#define CnINTMSKCLR0 0xfe410050
255#define CnINTMSKCLR1 0xfe410060
256#define CnINT2MSKR0 0xfe410a20
257#define CnINT2MSKR1 0xfe410a24
258#define CnINT2MSKR2 0xfe410a28
259#define CnINT2MSKR3 0xfe410a2c
260#define CnINT2MSKCR0 0xfe410a30
261#define CnINT2MSKCR1 0xfe410a34
262#define CnINT2MSKCR2 0xfe410a38
263#define CnINT2MSKCR3 0xfe410a3c
264#else /* Sub CPU */
265#define CnINTMSK0 0xfe410034
266#define CnINTMSK1 0xfe410044
267#define CnINTMSKCLR0 0xfe410054
268#define CnINTMSKCLR1 0xfe410064
269#define CnINT2MSKR0 0xfe410b20
270#define CnINT2MSKR1 0xfe410b24
271#define CnINT2MSKR2 0xfe410b28
272#define CnINT2MSKR3 0xfe410b2c
273#define CnINT2MSKCR0 0xfe410b30
274#define CnINT2MSKCR1 0xfe410b34
275#define CnINT2MSKCR2 0xfe410b38
276#define CnINT2MSKCR3 0xfe410b3c
277#endif
278
279#define INTMSK2 0xfe410068
280#define INTMSKCLR2 0xfe41006c
281
282static struct intc_mask_reg mask_registers[] __initdata = {
283 { CnINTMSK0, CnINTMSKCLR0, 32,
284 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
285 { INTMSK2, INTMSKCLR2, 32,
286 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
287 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
288 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
289 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
290 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
291 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
292 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
293 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
294 { CnINT2MSKR0, CnINT2MSKCR0 , 32,
295 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
296 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } },
297 { CnINT2MSKR1, CnINT2MSKCR1, 32,
298 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
299 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
300 HUDI1, HUDI0,
301 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
302 HPB_0, HPB_1, HPB_2,
303 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
304 SCIF1,
305 TMU2, TMU3, 0, } },
306 { CnINT2MSKR2, CnINT2MSKCR2, 32,
307 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
308 Eth_0, Eth_1,
309 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
310 PCIeC0_0, PCIeC0_1, PCIeC0_2,
311 PCIeC1_0, PCIeC1_1, PCIeC1_2,
312 USB, 0, 0 } },
313 { CnINT2MSKR3, CnINT2MSKCR3, 32,
314 { 0, 0, 0, 0, 0, 0,
315 I2C0, I2C1,
316 DU, SSI0, SSI1, SSI2, SSI3,
317 PCIeC2_0, PCIeC2_1, PCIeC2_2,
318 HAC0, HAC1,
319 FLCTL, 0,
320 HSPI, GPIO0, GPIO1, Thermal,
321 0, 0, 0, 0, 0, 0, 0, 0 } },
322};
323
324static struct intc_prio_reg prio_registers[] __initdata = {
325 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
326 IRQ4, IRQ5, IRQ6, IRQ7 } },
327 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
328 { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
329 TMU0_2, TMU0_3 } },
330 { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
331 TMU1_2, 0 } },
332 { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
333 DMAC0_2, DMAC0_3 } },
334 { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
335 DMAC0_6, HUDI1 } },
336 { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
337 DMAC1_1, DMAC1_2 } },
338 { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
339 HPB_1, HPB_2 } },
340 { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
341 SCIF0_2, SCIF0_3 } },
342 { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
343 { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
344 { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
345 Eth_0, Eth_1 } },
346 { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
347 { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
348 { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
349 { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
350 { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
351 PCIeC1_0, PCIeC1_1 } },
352 { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
353 { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
354 { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
355 { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
356 { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
357 PCIeC2_1, PCIeC2_2 } },
358 { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
359 { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
360 GPIO1, Thermal } },
361 { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
362 { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
363};
364
365static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL,
366 mask_registers, prio_registers, NULL);
367
368/* Support for external interrupt pins in IRQ mode */
369
370static struct intc_vect vectors_irq0123[] __initdata = {
371 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
372 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
373};
374
375static struct intc_vect vectors_irq4567[] __initdata = {
376 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
377 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
378};
379
380static struct intc_sense_reg sense_registers[] __initdata = {
381 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
382 IRQ4, IRQ5, IRQ6, IRQ7 } },
383};
384
385static struct intc_mask_reg ack_registers[] __initdata = {
386 { 0xfe410024, 0, 32, /* INTREQ */
387 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
388};
389
390static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
391 vectors_irq0123, NULL, mask_registers,
392 prio_registers, sense_registers, ack_registers);
393
394static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
395 vectors_irq4567, NULL, mask_registers,
396 prio_registers, sense_registers, ack_registers);
397
398/* External interrupt pins in IRL mode */
399
400static struct intc_vect vectors_irl0123[] __initdata = {
401 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
402 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
403 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
404 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
405 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
406 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
407 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
408 INTC_VECT(IRL0_HHHL, 0x3c0),
409};
410
411static struct intc_vect vectors_irl4567[] __initdata = {
412 INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
413 INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
414 INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
415 INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
416 INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
417 INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
418 INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
419 INTC_VECT(IRL4_HHHL, 0xac0),
420};
421
422static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
423 NULL, mask_registers, NULL, NULL);
424
425static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
426 NULL, mask_registers, NULL, NULL);
427
428#define INTC_ICR0 0xfe410000
429#define INTC_INTMSK0 CnINTMSK0
430#define INTC_INTMSK1 CnINTMSK1
431#define INTC_INTMSK2 INTMSK2
432#define INTC_INTMSKCLR1 CnINTMSKCLR1
433#define INTC_INTMSKCLR2 INTMSKCLR2
434
435void __init plat_irq_setup(void)
436{
437 /* disable IRQ3-0 + IRQ7-4 */
438 ctrl_outl(0xff000000, INTC_INTMSK0);
439
440 /* disable IRL3-0 + IRL7-4 */
441 ctrl_outl(0xc0000000, INTC_INTMSK1);
442 ctrl_outl(0xfffefffe, INTC_INTMSK2);
443
444 /* select IRL mode for IRL3-0 + IRL7-4 */
445 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
446
447 register_intc_controller(&intc_desc);
448}
449
450void __init plat_irq_setup_pins(int mode)
451{
452 switch (mode) {
453 case IRQ_MODE_IRQ7654:
454 /* select IRQ mode for IRL7-4 */
455 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
456 register_intc_controller(&intc_desc_irq4567);
457 break;
458 case IRQ_MODE_IRQ3210:
459 /* select IRQ mode for IRL3-0 */
460 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
461 register_intc_controller(&intc_desc_irq0123);
462 break;
463 case IRQ_MODE_IRL7654:
464 /* enable IRL7-4 but don't provide any masking */
465 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
466 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
467 break;
468 case IRQ_MODE_IRL3210:
469 /* enable IRL0-3 but don't provide any masking */
470 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
471 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
472 break;
473 case IRQ_MODE_IRL7654_MASK:
474 /* enable IRL7-4 and mask using cpu intc controller */
475 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
476 register_intc_controller(&intc_desc_irl4567);
477 break;
478 case IRQ_MODE_IRL3210_MASK:
479 /* enable IRL0-3 and mask using cpu intc controller */
480 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
481 register_intc_controller(&intc_desc_irl0123);
482 break;
483 default:
484 BUG();
485 }
486}
487
488void __init plat_mem_setup(void)
489{
490}
diff --git a/arch/sh/kernel/cpu/shmobile/Makefile b/arch/sh/kernel/cpu/shmobile/Makefile
new file mode 100644
index 000000000000..08bfa7c7db29
--- /dev/null
+++ b/arch/sh/kernel/cpu/shmobile/Makefile
@@ -0,0 +1,6 @@
1#
2# Makefile for the Linux/SuperH SH-Mobile backends.
3#
4
5# Power Management & Sleep mode
6obj-$(CONFIG_PM) += pm.o sleep.o
diff --git a/arch/sh/kernel/cpu/shmobile/pm.c b/arch/sh/kernel/cpu/shmobile/pm.c
new file mode 100644
index 000000000000..8c067adf6830
--- /dev/null
+++ b/arch/sh/kernel/cpu/shmobile/pm.c
@@ -0,0 +1,92 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/pm-sh_mobile.c
3 *
4 * Power management support code for SuperH Mobile
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <linux/suspend.h>
16#include <asm/suspend.h>
17#include <asm/uaccess.h>
18
19/*
20 * Sleep modes available on SuperH Mobile:
21 *
22 * Sleep mode is just plain "sleep" instruction
23 * Sleep Self-Refresh mode is above plus RAM put in Self-Refresh
24 * Standby Self-Refresh mode is above plus stopped clocks
25 */
26#define SUSP_MODE_SLEEP (SUSP_SH_SLEEP)
27#define SUSP_MODE_SLEEP_SF (SUSP_SH_SLEEP | SUSP_SH_SF)
28#define SUSP_MODE_STANDBY_SF (SUSP_SH_STANDBY | SUSP_SH_SF)
29
30/*
31 * The following modes are not there yet:
32 *
33 * R-standby mode is unsupported, but will be added in the future
34 * U-standby mode is low priority since it needs bootloader hacks
35 *
36 * All modes should be tied in with cpuidle. But before that can
37 * happen we need to keep track of enabled hardware blocks so we
38 * can avoid entering sleep modes that stop clocks to hardware
39 * blocks that are in use even though the cpu core is idle.
40 */
41
42extern const unsigned char sh_mobile_standby[];
43extern const unsigned int sh_mobile_standby_size;
44
45static void sh_mobile_call_standby(unsigned long mode)
46{
47 extern void *vbr_base;
48 void *onchip_mem = (void *)0xe5200000; /* ILRAM */
49 void (*standby_onchip_mem)(unsigned long) = onchip_mem;
50
51 /* Note: Wake up from sleep may generate exceptions!
52 * Setup VBR to point to on-chip ram if self-refresh is
53 * going to be used.
54 */
55 if (mode & SUSP_SH_SF)
56 asm volatile("ldc %0, vbr" : : "r" (onchip_mem) : "memory");
57
58 /* Copy the assembly snippet to the otherwise ununsed ILRAM */
59 memcpy(onchip_mem, sh_mobile_standby, sh_mobile_standby_size);
60 wmb();
61 ctrl_barrier();
62
63 /* Let assembly snippet in on-chip memory handle the rest */
64 standby_onchip_mem(mode);
65
66 /* Put VBR back in System RAM again */
67 if (mode & SUSP_SH_SF)
68 asm volatile("ldc %0, vbr" : : "r" (&vbr_base) : "memory");
69}
70
71static int sh_pm_enter(suspend_state_t state)
72{
73 local_irq_disable();
74 set_bl_bit();
75 sh_mobile_call_standby(SUSP_MODE_STANDBY_SF);
76 local_irq_disable();
77 clear_bl_bit();
78 return 0;
79}
80
81static struct platform_suspend_ops sh_pm_ops = {
82 .enter = sh_pm_enter,
83 .valid = suspend_valid_only_mem,
84};
85
86static int __init sh_pm_init(void)
87{
88 suspend_set_ops(&sh_pm_ops);
89 return 0;
90}
91
92late_initcall(sh_pm_init);
diff --git a/arch/sh/kernel/cpu/shmobile/sleep.S b/arch/sh/kernel/cpu/shmobile/sleep.S
new file mode 100644
index 000000000000..5d888ef53d82
--- /dev/null
+++ b/arch/sh/kernel/cpu/shmobile/sleep.S
@@ -0,0 +1,125 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/sleep-sh_mobile.S
3 *
4 * Sleep mode and Standby modes support for SuperH Mobile
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/sys.h>
14#include <linux/errno.h>
15#include <linux/linkage.h>
16#include <asm/asm-offsets.h>
17#include <asm/suspend.h>
18
19/* manage self-refresh and enter standby mode.
20 * this code will be copied to on-chip memory and executed from there.
21 */
22
23 .balign 4096,0,4096
24ENTRY(sh_mobile_standby)
25 mov r4, r0
26
27 tst #SUSP_SH_SF, r0
28 bt skip_set_sf
29
30 /* SDRAM: disable power down and put in self-refresh mode */
31 mov.l 1f, r4
32 mov.l 2f, r1
33 mov.l @r4, r2
34 or r1, r2
35 mov.l 3f, r3
36 and r3, r2
37 mov.l r2, @r4
38
39skip_set_sf:
40 tst #SUSP_SH_SLEEP, r0
41 bt test_standby
42
43 /* set mode to "sleep mode" */
44 bra do_sleep
45 mov #0x00, r1
46
47test_standby:
48 tst #SUSP_SH_STANDBY, r0
49 bt test_rstandby
50
51 /* set mode to "software standby mode" */
52 bra do_sleep
53 mov #0x80, r1
54
55test_rstandby:
56 tst #SUSP_SH_RSTANDBY, r0
57 bt test_ustandby
58
59 /* set mode to "r-standby mode" */
60 bra do_sleep
61 mov #0x20, r1
62
63test_ustandby:
64 tst #SUSP_SH_USTANDBY, r0
65 bt done_sleep
66
67 /* set mode to "u-standby mode" */
68 mov #0x10, r1
69
70 /* fall-through */
71
72do_sleep:
73 /* setup and enter selected standby mode */
74 mov.l 5f, r4
75 mov.l r1, @r4
76 sleep
77
78done_sleep:
79 /* reset standby mode to sleep mode */
80 mov.l 5f, r4
81 mov #0x00, r1
82 mov.l r1, @r4
83
84 tst #SUSP_SH_SF, r0
85 bt skip_restore_sf
86
87 /* SDRAM: set auto-refresh mode */
88 mov.l 1f, r4
89 mov.l @r4, r2
90 mov.l 4f, r3
91 and r3, r2
92 mov.l r2, @r4
93 mov.l 6f, r4
94 mov.l 7f, r1
95 mov.l 8f, r2
96 mov.l @r4, r3
97 mov #-1, r4
98 add r4, r3
99 or r2, r3
100 mov.l r3, @r1
101skip_restore_sf:
102 rts
103 nop
104
105 .balign 4
1061: .long 0xfe400008 /* SDCR0 */
1072: .long 0x00000400
1083: .long 0xffff7fff
1094: .long 0xfffffbff
1105: .long 0xa4150020 /* STBCR */
1116: .long 0xfe40001c /* RTCOR */
1127: .long 0xfe400018 /* RTCNT */
1138: .long 0xa55a0000
114
115/* interrupt vector @ 0x600 */
116 .balign 0x400,0,0x400
117 .long 0xdeadbeef
118 .balign 0x200,0,0x200
119 /* sh7722 will end up here in sleep mode */
120 rte
121 nop
122sh_mobile_standby_end:
123
124ENTRY(sh_mobile_standby_size)
125 .long sh_mobile_standby_end - sh_mobile_standby
diff --git a/arch/sh/kernel/gpio.c b/arch/sh/kernel/gpio.c
index d37165361034..d22e5af699f9 100644
--- a/arch/sh/kernel/gpio.c
+++ b/arch/sh/kernel/gpio.c
@@ -19,36 +19,75 @@
19#include <linux/bitops.h> 19#include <linux/bitops.h>
20#include <linux/gpio.h> 20#include <linux/gpio.h>
21 21
22static struct pinmux_info *registered_gpio; 22static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
23{
24 if (enum_id < r->begin)
25 return 0;
23 26
24static struct pinmux_info *gpio_controller(unsigned gpio) 27 if (enum_id > r->end)
28 return 0;
29
30 return 1;
31}
32
33static unsigned long gpio_read_raw_reg(unsigned long reg,
34 unsigned long reg_width)
25{ 35{
26 if (!registered_gpio) 36 switch (reg_width) {
27 return NULL; 37 case 8:
38 return ctrl_inb(reg);
39 case 16:
40 return ctrl_inw(reg);
41 case 32:
42 return ctrl_inl(reg);
43 }
28 44
29 if (gpio < registered_gpio->first_gpio) 45 BUG();
30 return NULL; 46 return 0;
47}
31 48
32 if (gpio > registered_gpio->last_gpio) 49static void gpio_write_raw_reg(unsigned long reg,
33 return NULL; 50 unsigned long reg_width,
51 unsigned long data)
52{
53 switch (reg_width) {
54 case 8:
55 ctrl_outb(data, reg);
56 return;
57 case 16:
58 ctrl_outw(data, reg);
59 return;
60 case 32:
61 ctrl_outl(data, reg);
62 return;
63 }
34 64
35 return registered_gpio; 65 BUG();
36} 66}
37 67
38static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) 68static void gpio_write_bit(struct pinmux_data_reg *dr,
69 unsigned long in_pos, unsigned long value)
39{ 70{
40 if (enum_id < r->begin) 71 unsigned long pos;
41 return 0;
42 72
43 if (enum_id > r->end) 73 pos = dr->reg_width - (in_pos + 1);
44 return 0;
45 74
46 return 1; 75#ifdef DEBUG
76 pr_info("write_bit addr = %lx, value = %ld, pos = %ld, "
77 "r_width = %ld\n",
78 dr->reg, !!value, pos, dr->reg_width);
79#endif
80
81 if (value)
82 set_bit(pos, &dr->reg_shadow);
83 else
84 clear_bit(pos, &dr->reg_shadow);
85
86 gpio_write_raw_reg(dr->reg, dr->reg_width, dr->reg_shadow);
47} 87}
48 88
49static int read_write_reg(unsigned long reg, unsigned long reg_width, 89static int gpio_read_reg(unsigned long reg, unsigned long reg_width,
50 unsigned long field_width, unsigned long in_pos, 90 unsigned long field_width, unsigned long in_pos)
51 unsigned long value, int do_write)
52{ 91{
53 unsigned long data, mask, pos; 92 unsigned long data, mask, pos;
54 93
@@ -57,52 +96,53 @@ static int read_write_reg(unsigned long reg, unsigned long reg_width,
57 pos = reg_width - ((in_pos + 1) * field_width); 96 pos = reg_width - ((in_pos + 1) * field_width);
58 97
59#ifdef DEBUG 98#ifdef DEBUG
60 pr_info("%s, addr = %lx, value = %ld, pos = %ld, " 99 pr_info("read_reg: addr = %lx, pos = %ld, "
61 "r_width = %ld, f_width = %ld\n", 100 "r_width = %ld, f_width = %ld\n",
62 do_write ? "write" : "read", reg, value, pos, 101 reg, pos, reg_width, field_width);
63 reg_width, field_width);
64#endif 102#endif
65 103
66 switch (reg_width) { 104 data = gpio_read_raw_reg(reg, reg_width);
67 case 8: 105 return (data >> pos) & mask;
68 data = ctrl_inb(reg); 106}
69 break;
70 case 16:
71 data = ctrl_inw(reg);
72 break;
73 case 32:
74 data = ctrl_inl(reg);
75 break;
76 }
77 107
78 if (!do_write) 108static void gpio_write_reg(unsigned long reg, unsigned long reg_width,
79 return (data >> pos) & mask; 109 unsigned long field_width, unsigned long in_pos,
110 unsigned long value)
111{
112 unsigned long mask, pos;
80 113
81 data &= ~(mask << pos); 114 mask = (1 << field_width) - 1;
82 data |= value << pos; 115 pos = reg_width - ((in_pos + 1) * field_width);
116
117#ifdef DEBUG
118 pr_info("write_reg addr = %lx, value = %ld, pos = %ld, "
119 "r_width = %ld, f_width = %ld\n",
120 reg, value, pos, reg_width, field_width);
121#endif
122
123 mask = ~(mask << pos);
124 value = value << pos;
83 125
84 switch (reg_width) { 126 switch (reg_width) {
85 case 8: 127 case 8:
86 ctrl_outb(data, reg); 128 ctrl_outb((ctrl_inb(reg) & mask) | value, reg);
87 break; 129 break;
88 case 16: 130 case 16:
89 ctrl_outw(data, reg); 131 ctrl_outw((ctrl_inw(reg) & mask) | value, reg);
90 break; 132 break;
91 case 32: 133 case 32:
92 ctrl_outl(data, reg); 134 ctrl_outl((ctrl_inl(reg) & mask) | value, reg);
93 break; 135 break;
94 } 136 }
95 return 0;
96} 137}
97 138
98static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio, 139static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
99 struct pinmux_data_reg **drp, int *bitp)
100{ 140{
101 pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id; 141 struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
102 struct pinmux_data_reg *data_reg; 142 struct pinmux_data_reg *data_reg;
103 int k, n; 143 int k, n;
104 144
105 if (!enum_in_range(enum_id, &gpioc->data)) 145 if (!enum_in_range(gpiop->enum_id, &gpioc->data))
106 return -1; 146 return -1;
107 147
108 k = 0; 148 k = 0;
@@ -113,19 +153,58 @@ static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
113 break; 153 break;
114 154
115 for (n = 0; n < data_reg->reg_width; n++) { 155 for (n = 0; n < data_reg->reg_width; n++) {
116 if (data_reg->enum_ids[n] == enum_id) { 156 if (data_reg->enum_ids[n] == gpiop->enum_id) {
117 *drp = data_reg; 157 gpiop->flags &= ~PINMUX_FLAG_DREG;
118 *bitp = n; 158 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
159 gpiop->flags &= ~PINMUX_FLAG_DBIT;
160 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
119 return 0; 161 return 0;
120
121 } 162 }
122 } 163 }
123 k++; 164 k++;
124 } 165 }
125 166
167 BUG();
168
126 return -1; 169 return -1;
127} 170}
128 171
172static void setup_data_regs(struct pinmux_info *gpioc)
173{
174 struct pinmux_data_reg *drp;
175 int k;
176
177 for (k = gpioc->first_gpio; k <= gpioc->last_gpio; k++)
178 setup_data_reg(gpioc, k);
179
180 k = 0;
181 while (1) {
182 drp = gpioc->data_regs + k;
183
184 if (!drp->reg_width)
185 break;
186
187 drp->reg_shadow = gpio_read_raw_reg(drp->reg, drp->reg_width);
188 k++;
189 }
190}
191
192static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
193 struct pinmux_data_reg **drp, int *bitp)
194{
195 struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
196 int k, n;
197
198 if (!enum_in_range(gpiop->enum_id, &gpioc->data))
199 return -1;
200
201 k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
202 n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
203 *drp = gpioc->data_regs + k;
204 *bitp = n;
205 return 0;
206}
207
129static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id, 208static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
130 struct pinmux_cfg_reg **crp, int *indexp, 209 struct pinmux_cfg_reg **crp, int *indexp,
131 unsigned long **cntp) 210 unsigned long **cntp)
@@ -187,9 +266,9 @@ static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
187 return -1; 266 return -1;
188} 267}
189 268
190static int write_config_reg(struct pinmux_info *gpioc, 269static void write_config_reg(struct pinmux_info *gpioc,
191 struct pinmux_cfg_reg *crp, 270 struct pinmux_cfg_reg *crp,
192 int index) 271 int index)
193{ 272{
194 unsigned long ncomb, pos, value; 273 unsigned long ncomb, pos, value;
195 274
@@ -197,8 +276,7 @@ static int write_config_reg(struct pinmux_info *gpioc,
197 pos = index / ncomb; 276 pos = index / ncomb;
198 value = index % ncomb; 277 value = index % ncomb;
199 278
200 return read_write_reg(crp->reg, crp->reg_width, 279 gpio_write_reg(crp->reg, crp->reg_width, crp->field_width, pos, value);
201 crp->field_width, pos, value, 1);
202} 280}
203 281
204static int check_config_reg(struct pinmux_info *gpioc, 282static int check_config_reg(struct pinmux_info *gpioc,
@@ -211,8 +289,8 @@ static int check_config_reg(struct pinmux_info *gpioc,
211 pos = index / ncomb; 289 pos = index / ncomb;
212 value = index % ncomb; 290 value = index % ncomb;
213 291
214 if (read_write_reg(crp->reg, crp->reg_width, 292 if (gpio_read_reg(crp->reg, crp->reg_width,
215 crp->field_width, pos, 0, 0) == value) 293 crp->field_width, pos) == value)
216 return 0; 294 return 0;
217 295
218 return -1; 296 return -1;
@@ -220,8 +298,8 @@ static int check_config_reg(struct pinmux_info *gpioc,
220 298
221enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE }; 299enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
222 300
223int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio, 301static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
224 int pinmux_type, int cfg_mode) 302 int pinmux_type, int cfg_mode)
225{ 303{
226 struct pinmux_cfg_reg *cr = NULL; 304 struct pinmux_cfg_reg *cr = NULL;
227 pinmux_enum_t enum_id; 305 pinmux_enum_t enum_id;
@@ -287,8 +365,7 @@ int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
287 break; 365 break;
288 366
289 case GPIO_CFG_REQ: 367 case GPIO_CFG_REQ:
290 if (write_config_reg(gpioc, cr, index) != 0) 368 write_config_reg(gpioc, cr, index);
291 goto out_err;
292 *cntp = *cntp + 1; 369 *cntp = *cntp + 1;
293 break; 370 break;
294 371
@@ -305,9 +382,14 @@ int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
305 382
306static DEFINE_SPINLOCK(gpio_lock); 383static DEFINE_SPINLOCK(gpio_lock);
307 384
308int __gpio_request(unsigned gpio) 385static struct pinmux_info *chip_to_pinmux(struct gpio_chip *chip)
309{ 386{
310 struct pinmux_info *gpioc = gpio_controller(gpio); 387 return container_of(chip, struct pinmux_info, chip);
388}
389
390static int sh_gpio_request(struct gpio_chip *chip, unsigned offset)
391{
392 struct pinmux_info *gpioc = chip_to_pinmux(chip);
311 struct pinmux_data_reg *dummy; 393 struct pinmux_data_reg *dummy;
312 unsigned long flags; 394 unsigned long flags;
313 int i, ret, pinmux_type; 395 int i, ret, pinmux_type;
@@ -319,29 +401,30 @@ int __gpio_request(unsigned gpio)
319 401
320 spin_lock_irqsave(&gpio_lock, flags); 402 spin_lock_irqsave(&gpio_lock, flags);
321 403
322 if ((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE) 404 if ((gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
323 goto err_unlock; 405 goto err_unlock;
324 406
325 /* setup pin function here if no data is associated with pin */ 407 /* setup pin function here if no data is associated with pin */
326 408
327 if (get_data_reg(gpioc, gpio, &dummy, &i) != 0) 409 if (get_data_reg(gpioc, offset, &dummy, &i) != 0)
328 pinmux_type = PINMUX_TYPE_FUNCTION; 410 pinmux_type = PINMUX_TYPE_FUNCTION;
329 else 411 else
330 pinmux_type = PINMUX_TYPE_GPIO; 412 pinmux_type = PINMUX_TYPE_GPIO;
331 413
332 if (pinmux_type == PINMUX_TYPE_FUNCTION) { 414 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
333 if (pinmux_config_gpio(gpioc, gpio, 415 if (pinmux_config_gpio(gpioc, offset,
334 pinmux_type, 416 pinmux_type,
335 GPIO_CFG_DRYRUN) != 0) 417 GPIO_CFG_DRYRUN) != 0)
336 goto err_unlock; 418 goto err_unlock;
337 419
338 if (pinmux_config_gpio(gpioc, gpio, 420 if (pinmux_config_gpio(gpioc, offset,
339 pinmux_type, 421 pinmux_type,
340 GPIO_CFG_REQ) != 0) 422 GPIO_CFG_REQ) != 0)
341 BUG(); 423 BUG();
342 } 424 }
343 425
344 gpioc->gpios[gpio].flags = pinmux_type; 426 gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
427 gpioc->gpios[offset].flags |= pinmux_type;
345 428
346 ret = 0; 429 ret = 0;
347 err_unlock: 430 err_unlock:
@@ -349,11 +432,10 @@ int __gpio_request(unsigned gpio)
349 err_out: 432 err_out:
350 return ret; 433 return ret;
351} 434}
352EXPORT_SYMBOL(__gpio_request);
353 435
354void gpio_free(unsigned gpio) 436static void sh_gpio_free(struct gpio_chip *chip, unsigned offset)
355{ 437{
356 struct pinmux_info *gpioc = gpio_controller(gpio); 438 struct pinmux_info *gpioc = chip_to_pinmux(chip);
357 unsigned long flags; 439 unsigned long flags;
358 int pinmux_type; 440 int pinmux_type;
359 441
@@ -362,20 +444,23 @@ void gpio_free(unsigned gpio)
362 444
363 spin_lock_irqsave(&gpio_lock, flags); 445 spin_lock_irqsave(&gpio_lock, flags);
364 446
365 pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE; 447 pinmux_type = gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE;
366 pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE); 448 pinmux_config_gpio(gpioc, offset, pinmux_type, GPIO_CFG_FREE);
367 gpioc->gpios[gpio].flags = PINMUX_TYPE_NONE; 449 gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
450 gpioc->gpios[offset].flags |= PINMUX_TYPE_NONE;
368 451
369 spin_unlock_irqrestore(&gpio_lock, flags); 452 spin_unlock_irqrestore(&gpio_lock, flags);
370} 453}
371EXPORT_SYMBOL(gpio_free);
372 454
373static int pinmux_direction(struct pinmux_info *gpioc, 455static int pinmux_direction(struct pinmux_info *gpioc,
374 unsigned gpio, int new_pinmux_type) 456 unsigned gpio, int new_pinmux_type)
375{ 457{
376 int ret, pinmux_type; 458 int pinmux_type;
459 int ret = -EINVAL;
460
461 if (!gpioc)
462 goto err_out;
377 463
378 ret = -EINVAL;
379 pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE; 464 pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
380 465
381 switch (pinmux_type) { 466 switch (pinmux_type) {
@@ -401,102 +486,99 @@ static int pinmux_direction(struct pinmux_info *gpioc,
401 GPIO_CFG_REQ) != 0) 486 GPIO_CFG_REQ) != 0)
402 BUG(); 487 BUG();
403 488
404 gpioc->gpios[gpio].flags = new_pinmux_type; 489 gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
490 gpioc->gpios[gpio].flags |= new_pinmux_type;
405 491
406 ret = 0; 492 ret = 0;
407 err_out: 493 err_out:
408 return ret; 494 return ret;
409} 495}
410 496
411int gpio_direction_input(unsigned gpio) 497static int sh_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
412{ 498{
413 struct pinmux_info *gpioc = gpio_controller(gpio); 499 struct pinmux_info *gpioc = chip_to_pinmux(chip);
414 unsigned long flags; 500 unsigned long flags;
415 int ret = -EINVAL; 501 int ret;
416
417 if (!gpioc)
418 goto err_out;
419 502
420 spin_lock_irqsave(&gpio_lock, flags); 503 spin_lock_irqsave(&gpio_lock, flags);
421 ret = pinmux_direction(gpioc, gpio, PINMUX_TYPE_INPUT); 504 ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_INPUT);
422 spin_unlock_irqrestore(&gpio_lock, flags); 505 spin_unlock_irqrestore(&gpio_lock, flags);
423 err_out: 506
424 return ret; 507 return ret;
425} 508}
426EXPORT_SYMBOL(gpio_direction_input);
427 509
428static int __gpio_get_set_value(struct pinmux_info *gpioc, 510static void sh_gpio_set_value(struct pinmux_info *gpioc,
429 unsigned gpio, int value, 511 unsigned gpio, int value)
430 int do_write)
431{ 512{
432 struct pinmux_data_reg *dr = NULL; 513 struct pinmux_data_reg *dr = NULL;
433 int bit = 0; 514 int bit = 0;
434 515
435 if (get_data_reg(gpioc, gpio, &dr, &bit) != 0) 516 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
436 BUG(); 517 BUG();
437 else 518 else
438 value = read_write_reg(dr->reg, dr->reg_width, 519 gpio_write_bit(dr, bit, value);
439 1, bit, !!value, do_write);
440
441 return value;
442} 520}
443 521
444int gpio_direction_output(unsigned gpio, int value) 522static int sh_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
523 int value)
445{ 524{
446 struct pinmux_info *gpioc = gpio_controller(gpio); 525 struct pinmux_info *gpioc = chip_to_pinmux(chip);
447 unsigned long flags; 526 unsigned long flags;
448 int ret = -EINVAL; 527 int ret;
449
450 if (!gpioc)
451 goto err_out;
452 528
529 sh_gpio_set_value(gpioc, offset, value);
453 spin_lock_irqsave(&gpio_lock, flags); 530 spin_lock_irqsave(&gpio_lock, flags);
454 __gpio_get_set_value(gpioc, gpio, value, 1); 531 ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_OUTPUT);
455 ret = pinmux_direction(gpioc, gpio, PINMUX_TYPE_OUTPUT);
456 spin_unlock_irqrestore(&gpio_lock, flags); 532 spin_unlock_irqrestore(&gpio_lock, flags);
457 err_out: 533
458 return ret; 534 return ret;
459} 535}
460EXPORT_SYMBOL(gpio_direction_output);
461 536
462int gpio_get_value(unsigned gpio) 537static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
463{ 538{
464 struct pinmux_info *gpioc = gpio_controller(gpio); 539 struct pinmux_data_reg *dr = NULL;
465 unsigned long flags; 540 int bit = 0;
466 int value = 0;
467 541
468 if (!gpioc) 542 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0) {
469 BUG(); 543 BUG();
470 else { 544 return 0;
471 spin_lock_irqsave(&gpio_lock, flags);
472 value = __gpio_get_set_value(gpioc, gpio, 0, 0);
473 spin_unlock_irqrestore(&gpio_lock, flags);
474 } 545 }
475 546
476 return value; 547 return gpio_read_reg(dr->reg, dr->reg_width, 1, bit);
477} 548}
478EXPORT_SYMBOL(gpio_get_value);
479 549
480void gpio_set_value(unsigned gpio, int value) 550static int sh_gpio_get(struct gpio_chip *chip, unsigned offset)
481{ 551{
482 struct pinmux_info *gpioc = gpio_controller(gpio); 552 return sh_gpio_get_value(chip_to_pinmux(chip), offset);
483 unsigned long flags; 553}
484 554
485 if (!gpioc) 555static void sh_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
486 BUG(); 556{
487 else { 557 sh_gpio_set_value(chip_to_pinmux(chip), offset, value);
488 spin_lock_irqsave(&gpio_lock, flags);
489 __gpio_get_set_value(gpioc, gpio, value, 1);
490 spin_unlock_irqrestore(&gpio_lock, flags);
491 }
492} 558}
493EXPORT_SYMBOL(gpio_set_value);
494 559
495int register_pinmux(struct pinmux_info *pip) 560int register_pinmux(struct pinmux_info *pip)
496{ 561{
497 registered_gpio = pip; 562 struct gpio_chip *chip = &pip->chip;
498 pr_info("pinmux: %s handling gpio %d -> %d\n", 563
564 pr_info("sh pinmux: %s handling gpio %d -> %d\n",
499 pip->name, pip->first_gpio, pip->last_gpio); 565 pip->name, pip->first_gpio, pip->last_gpio);
500 566
501 return 0; 567 setup_data_regs(pip);
568
569 chip->request = sh_gpio_request;
570 chip->free = sh_gpio_free;
571 chip->direction_input = sh_gpio_direction_input;
572 chip->get = sh_gpio_get;
573 chip->direction_output = sh_gpio_direction_output;
574 chip->set = sh_gpio_set;
575
576 WARN_ON(pip->first_gpio != 0); /* needs testing */
577
578 chip->label = pip->name;
579 chip->owner = THIS_MODULE;
580 chip->base = pip->first_gpio;
581 chip->ngpio = (pip->last_gpio - pip->first_gpio) + 1;
582
583 return gpiochip_add(chip);
502} 584}
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index 64b7690c664c..90d63aefd275 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -106,7 +106,7 @@ asmlinkage int do_IRQ(unsigned int irq, struct pt_regs *regs)
106 } 106 }
107#endif 107#endif
108 108
109 irq = irq_demux(evt2irq(irq)); 109 irq = irq_demux(intc_evt2irq(irq));
110 110
111#ifdef CONFIG_IRQSTACKS 111#ifdef CONFIG_IRQSTACKS
112 curctx = (union irq_ctx *)current_thread_info(); 112 curctx = (union irq_ctx *)current_thread_info();
diff --git a/arch/sh/kernel/machine_kexec.c b/arch/sh/kernel/machine_kexec.c
index 94df56b0d1f6..7ea2704ea033 100644
--- a/arch/sh/kernel/machine_kexec.c
+++ b/arch/sh/kernel/machine_kexec.c
@@ -14,21 +14,22 @@
14#include <linux/delay.h> 14#include <linux/delay.h>
15#include <linux/reboot.h> 15#include <linux/reboot.h>
16#include <linux/numa.h> 16#include <linux/numa.h>
17#include <linux/ftrace.h>
18#include <linux/suspend.h>
17#include <asm/pgtable.h> 19#include <asm/pgtable.h>
18#include <asm/pgalloc.h> 20#include <asm/pgalloc.h>
19#include <asm/mmu_context.h> 21#include <asm/mmu_context.h>
20#include <asm/io.h> 22#include <asm/io.h>
21#include <asm/cacheflush.h> 23#include <asm/cacheflush.h>
22 24
23typedef NORET_TYPE void (*relocate_new_kernel_t)( 25typedef void (*relocate_new_kernel_t)(unsigned long indirection_page,
24 unsigned long indirection_page, 26 unsigned long reboot_code_buffer,
25 unsigned long reboot_code_buffer, 27 unsigned long start_address);
26 unsigned long start_address,
27 unsigned long vbr_reg) ATTRIB_NORET;
28 28
29extern const unsigned char relocate_new_kernel[]; 29extern const unsigned char relocate_new_kernel[];
30extern const unsigned int relocate_new_kernel_size; 30extern const unsigned int relocate_new_kernel_size;
31extern void *gdb_vbr_vector; 31extern void *gdb_vbr_vector;
32extern void *vbr_base;
32 33
33void machine_shutdown(void) 34void machine_shutdown(void)
34{ 35{
@@ -45,6 +46,12 @@ void machine_crash_shutdown(struct pt_regs *regs)
45 */ 46 */
46int machine_kexec_prepare(struct kimage *image) 47int machine_kexec_prepare(struct kimage *image)
47{ 48{
49 /* older versions of kexec-tools are passing
50 * the zImage entry point as a virtual address.
51 */
52 if (image->start != PHYSADDR(image->start))
53 return -EINVAL; /* upgrade your kexec-tools */
54
48 return 0; 55 return 0;
49} 56}
50 57
@@ -73,17 +80,33 @@ static void kexec_info(struct kimage *image)
73 */ 80 */
74void machine_kexec(struct kimage *image) 81void machine_kexec(struct kimage *image)
75{ 82{
76
77 unsigned long page_list; 83 unsigned long page_list;
78 unsigned long reboot_code_buffer; 84 unsigned long reboot_code_buffer;
79 unsigned long vbr_reg;
80 relocate_new_kernel_t rnk; 85 relocate_new_kernel_t rnk;
86 unsigned long entry;
87 unsigned long *ptr;
88 int save_ftrace_enabled;
89
90 /*
91 * Nicked from the mips version of machine_kexec():
92 * The generic kexec code builds a page list with physical
93 * addresses. Use phys_to_virt() to convert them to virtual.
94 */
95 for (ptr = &image->head; (entry = *ptr) && !(entry & IND_DONE);
96 ptr = (entry & IND_INDIRECTION) ?
97 phys_to_virt(entry & PAGE_MASK) : ptr + 1) {
98 if (*ptr & IND_SOURCE || *ptr & IND_INDIRECTION ||
99 *ptr & IND_DESTINATION)
100 *ptr = (unsigned long) phys_to_virt(*ptr);
101 }
81 102
82#if defined(CONFIG_SH_STANDARD_BIOS) 103#ifdef CONFIG_KEXEC_JUMP
83 vbr_reg = ((unsigned long )gdb_vbr_vector) - 0x100; 104 if (image->preserve_context)
84#else 105 save_processor_state();
85 vbr_reg = 0x80000000; // dummy
86#endif 106#endif
107
108 save_ftrace_enabled = __ftrace_enabled_save();
109
87 /* Interrupts aren't acceptable while we reboot */ 110 /* Interrupts aren't acceptable while we reboot */
88 local_irq_disable(); 111 local_irq_disable();
89 112
@@ -97,12 +120,37 @@ void machine_kexec(struct kimage *image)
97 memcpy((void *)reboot_code_buffer, relocate_new_kernel, 120 memcpy((void *)reboot_code_buffer, relocate_new_kernel,
98 relocate_new_kernel_size); 121 relocate_new_kernel_size);
99 122
100 kexec_info(image); 123 kexec_info(image);
101 flush_cache_all(); 124 flush_cache_all();
102 125
126#if defined(CONFIG_SH_STANDARD_BIOS)
127 asm volatile("ldc %0, vbr" :
128 : "r" (((unsigned long) gdb_vbr_vector) - 0x100)
129 : "memory");
130#endif
131
103 /* now call it */ 132 /* now call it */
104 rnk = (relocate_new_kernel_t) reboot_code_buffer; 133 rnk = (relocate_new_kernel_t) reboot_code_buffer;
105 (*rnk)(page_list, reboot_code_buffer, P2SEGADDR(image->start), vbr_reg); 134 (*rnk)(page_list, reboot_code_buffer,
135 (unsigned long)phys_to_virt(image->start));
136
137#ifdef CONFIG_KEXEC_JUMP
138 asm volatile("ldc %0, vbr" : : "r" (&vbr_base) : "memory");
139
140 if (image->preserve_context)
141 restore_processor_state();
142
143 /* Convert page list back to physical addresses, what a mess. */
144 for (ptr = &image->head; (entry = *ptr) && !(entry & IND_DONE);
145 ptr = (*ptr & IND_INDIRECTION) ?
146 phys_to_virt(*ptr & PAGE_MASK) : ptr + 1) {
147 if (*ptr & IND_SOURCE || *ptr & IND_INDIRECTION ||
148 *ptr & IND_DESTINATION)
149 *ptr = virt_to_phys(*ptr);
150 }
151#endif
152
153 __ftrace_enabled_restore(save_ftrace_enabled);
106} 154}
107 155
108void arch_crash_save_vmcoreinfo(void) 156void arch_crash_save_vmcoreinfo(void)
diff --git a/arch/sh/kernel/relocate_kernel.S b/arch/sh/kernel/relocate_kernel.S
index c66cb3209db5..fcc9934fb97b 100644
--- a/arch/sh/kernel/relocate_kernel.S
+++ b/arch/sh/kernel/relocate_kernel.S
@@ -4,6 +4,8 @@
4 * 4 *
5 * LANDISK/sh4 is supported. Maybe, SH archtecture works well. 5 * LANDISK/sh4 is supported. Maybe, SH archtecture works well.
6 * 6 *
7 * 2009-03-18 Magnus Damm - Added Kexec Jump support
8 *
7 * This source code is licensed under the GNU General Public License, 9 * This source code is licensed under the GNU General Public License,
8 * Version 2. See the file COPYING for more details. 10 * Version 2. See the file COPYING for more details.
9 */ 11 */
@@ -16,23 +18,141 @@ relocate_new_kernel:
16 /* r4 = indirection_page */ 18 /* r4 = indirection_page */
17 /* r5 = reboot_code_buffer */ 19 /* r5 = reboot_code_buffer */
18 /* r6 = start_address */ 20 /* r6 = start_address */
19 /* r7 = vbr_reg */
20 21
21 mov.l 10f,r8 /* PAGE_SIZE */ 22 mov.l 10f, r0 /* PAGE_SIZE */
22 mov.l 11f,r9 /* P2SEG */ 23 add r5, r0 /* setup new stack at end of control page */
24
25 /* save r15->r8 to new stack */
26 mov.l r15, @-r0
27 mov r0, r15
28 mov.l r14, @-r15
29 mov.l r13, @-r15
30 mov.l r12, @-r15
31 mov.l r11, @-r15
32 mov.l r10, @-r15
33 mov.l r9, @-r15
34 mov.l r8, @-r15
35
36 /* save other random registers */
37 sts.l macl, @-r15
38 sts.l mach, @-r15
39 stc.l gbr, @-r15
40 stc.l ssr, @-r15
41 stc.l sr, @-r15
42 sts.l pr, @-r15
43 stc.l spc, @-r15
44
45 /* switch to bank1 and save r7->r0 */
46 mov.l 12f, r9
47 stc sr, r8
48 or r9, r8
49 ldc r8, sr
50 mov.l r7, @-r15
51 mov.l r6, @-r15
52 mov.l r5, @-r15
53 mov.l r4, @-r15
54 mov.l r3, @-r15
55 mov.l r2, @-r15
56 mov.l r1, @-r15
57 mov.l r0, @-r15
58
59 /* switch to bank0 and save r7->r0 */
60 mov.l 12f, r9
61 not r9, r9
62 stc sr, r8
63 and r9, r8
64 ldc r8, sr
65 mov.l r7, @-r15
66 mov.l r6, @-r15
67 mov.l r5, @-r15
68 mov.l r4, @-r15
69 mov.l r3, @-r15
70 mov.l r2, @-r15
71 mov.l r1, @-r15
72 mov.l r0, @-r15
73
74 mov.l r4, @-r15 /* save indirection page again */
75
76 bsr swap_pages /* swap pages before jumping to new kernel */
77 nop
78
79 mova 11f, r0
80 mov.l r15, @r0 /* save pointer to stack */
81
82 jsr @r6 /* hand over control to new kernel */
83 nop
84
85 mov.l 11f, r15 /* get pointer to stack */
86 mov.l @r15+, r4 /* restore r4 to get indirection page */
23 87
24 /* stack setting */ 88 bsr swap_pages /* swap pages back to previous state */
25 add r8,r5 89 nop
26 mov r5,r15
27 90
91 /* make sure bank0 is active and restore r0->r7 */
92 mov.l 12f, r9
93 not r9, r9
94 stc sr, r8
95 and r9, r8
96 ldc r8, sr
97 mov.l @r15+, r0
98 mov.l @r15+, r1
99 mov.l @r15+, r2
100 mov.l @r15+, r3
101 mov.l @r15+, r4
102 mov.l @r15+, r5
103 mov.l @r15+, r6
104 mov.l @r15+, r7
105
106 /* switch to bank1 and restore r0->r7 */
107 mov.l 12f, r9
108 stc sr, r8
109 or r9, r8
110 ldc r8, sr
111 mov.l @r15+, r0
112 mov.l @r15+, r1
113 mov.l @r15+, r2
114 mov.l @r15+, r3
115 mov.l @r15+, r4
116 mov.l @r15+, r5
117 mov.l @r15+, r6
118 mov.l @r15+, r7
119
120 /* switch back to bank0 */
121 mov.l 12f, r9
122 not r9, r9
123 stc sr, r8
124 and r9, r8
125 ldc r8, sr
126
127 /* restore other random registers */
128 ldc.l @r15+, spc
129 lds.l @r15+, pr
130 ldc.l @r15+, sr
131 ldc.l @r15+, ssr
132 ldc.l @r15+, gbr
133 lds.l @r15+, mach
134 lds.l @r15+, macl
135
136 /* restore r8->r15 */
137 mov.l @r15+, r8
138 mov.l @r15+, r9
139 mov.l @r15+, r10
140 mov.l @r15+, r11
141 mov.l @r15+, r12
142 mov.l @r15+, r13
143 mov.l @r15+, r14
144 mov.l @r15+, r15
145 rts
146 nop
147
148swap_pages:
28 bra 1f 149 bra 1f
29 mov r4,r0 /* cmd = indirection_page */ 150 mov r4,r0 /* cmd = indirection_page */
300: 1510:
31 mov.l @r4+,r0 /* cmd = *ind++ */ 152 mov.l @r4+,r0 /* cmd = *ind++ */
32 153
331: /* addr = (cmd | P2SEG) & 0xfffffff0 */ 1541: /* addr = cmd & 0xfffffff0 */
34 mov r0,r2 155 mov r0,r2
35 or r9,r2
36 mov #-16,r1 156 mov #-16,r1
37 and r1,r2 157 and r1,r2
38 158
@@ -40,57 +160,70 @@ relocate_new_kernel:
40 tst #1,r0 160 tst #1,r0
41 bt 2f 161 bt 2f
42 bra 0b 162 bra 0b
43 mov r2,r5 163 mov r2,r5
44 164
452: /* else if(cmd & IND_INDIRECTION) ind = addr */ 1652: /* else if(cmd & IND_INDIRECTION) ind = addr */
46 tst #2,r0 166 tst #2,r0
47 bt 3f 167 bt 3f
48 bra 0b 168 bra 0b
49 mov r2,r4 169 mov r2,r4
50 170
513: /* else if(cmd & IND_DONE) goto 6 */ 1713: /* else if(cmd & IND_DONE) return */
52 tst #4,r0 172 tst #4,r0
53 bt 4f 173 bt 4f
54 bra 6f 174 rts
55 nop 175 nop
56 176
574: /* else if(cmd & IND_SOURCE) memcpy(dst,addr,PAGE_SIZE) */ 1774: /* else if(cmd & IND_SOURCE) memcpy(dst,addr,PAGE_SIZE) */
58 tst #8,r0 178 tst #8,r0
59 bt 0b 179 bt 0b
60 180
61 mov r8,r3 181 mov.l 10f,r3 /* PAGE_SIZE */
62 shlr2 r3 182 shlr2 r3
63 shlr2 r3 183 shlr2 r3
645: 1845:
65 dt r3 185 dt r3
66 mov.l @r2+,r1 /* 16n+0 */ 186
67 mov.l r1,@r5 187 /* regular kexec just overwrites the destination page
68 add #4,r5 188 * with the contents of the source page.
69 mov.l @r2+,r1 /* 16n+4 */ 189 * for the kexec jump case we need to swap the contents
70 mov.l r1,@r5 190 * of the pages.
71 add #4,r5 191 * to keep it simple swap the contents for both cases.
72 mov.l @r2+,r1 /* 16n+8 */ 192 */
73 mov.l r1,@r5 193 mov.l @(0, r2), r8
74 add #4,r5 194 mov.l @(0, r5), r1
75 mov.l @r2+,r1 /* 16n+12 */ 195 mov.l r8, @(0, r5)
76 mov.l r1,@r5 196 mov.l r1, @(0, r2)
77 add #4,r5 197
198 mov.l @(4, r2), r8
199 mov.l @(4, r5), r1
200 mov.l r8, @(4, r5)
201 mov.l r1, @(4, r2)
202
203 mov.l @(8, r2), r8
204 mov.l @(8, r5), r1
205 mov.l r8, @(8, r5)
206 mov.l r1, @(8, r2)
207
208 mov.l @(12, r2), r8
209 mov.l @(12, r5), r1
210 mov.l r8, @(12, r5)
211 mov.l r1, @(12, r2)
212
213 add #16,r5
214 add #16,r2
78 bf 5b 215 bf 5b
79 216
80 bra 0b 217 bra 0b
81 nop 218 nop
826:
83#ifdef CONFIG_SH_STANDARD_BIOS
84 ldc r7, vbr
85#endif
86 jmp @r6
87 nop
88 219
89 .align 2 220 .align 2
9010: 22110:
91 .long PAGE_SIZE 222 .long PAGE_SIZE
9211: 22311:
93 .long P2SEG 224 .long 0
22512:
226 .long 0x20000000 ! RB=1
94 227
95relocate_new_kernel_end: 228relocate_new_kernel_end:
96 229
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 370d2cfa34eb..24c60251f680 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -432,6 +432,7 @@ static const char *cpu_name[] = {
432 [CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770", 432 [CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770",
433 [CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781", 433 [CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781",
434 [CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785", 434 [CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
435 [CPU_SH7786] = "SH7786",
435 [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3", 436 [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
436 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103", 437 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
437 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723", 438 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
@@ -448,7 +449,7 @@ EXPORT_SYMBOL(get_cpu_subtype);
448/* Symbolic CPU flags, keep in sync with asm/cpu-features.h */ 449/* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
449static const char *cpu_flags[] = { 450static const char *cpu_flags[] = {
450 "none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr", 451 "none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
451 "ptea", "llsc", "l2", "op32", NULL 452 "ptea", "llsc", "l2", "op32", "pteaex", NULL
452}; 453};
453 454
454static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c) 455static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
diff --git a/arch/sh/kernel/swsusp.c b/arch/sh/kernel/swsusp.c
new file mode 100644
index 000000000000..12b64a0f2f01
--- /dev/null
+++ b/arch/sh/kernel/swsusp.c
@@ -0,0 +1,38 @@
1/*
2 * swsusp.c - SuperH hibernation support
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/mm.h>
12#include <linux/sched.h>
13#include <linux/suspend.h>
14#include <asm/suspend.h>
15#include <asm/sections.h>
16#include <asm/tlbflush.h>
17#include <asm/page.h>
18#include <asm/fpu.h>
19
20struct swsusp_arch_regs swsusp_arch_regs_cpu0;
21
22int pfn_is_nosave(unsigned long pfn)
23{
24 unsigned long begin_pfn = __pa(&__nosave_begin) >> PAGE_SHIFT;
25 unsigned long end_pfn = PAGE_ALIGN(__pa(&__nosave_end)) >> PAGE_SHIFT;
26
27 return (pfn >= begin_pfn) && (pfn < end_pfn);
28}
29
30void save_processor_state(void)
31{
32 init_fpu(current);
33}
34
35void restore_processor_state(void)
36{
37 local_flush_tlb_all();
38}
diff --git a/arch/sh/kernel/time_32.c b/arch/sh/kernel/time_32.c
index 8457f83242c5..c34e1e0f9b02 100644
--- a/arch/sh/kernel/time_32.c
+++ b/arch/sh/kernel/time_32.c
@@ -41,14 +41,6 @@ static int null_rtc_set_time(const time_t secs)
41 return 0; 41 return 0;
42} 42}
43 43
44/*
45 * Null high precision timer functions for systems lacking one.
46 */
47static cycle_t null_hpt_read(void)
48{
49 return 0;
50}
51
52void (*rtc_sh_get_time)(struct timespec *) = null_rtc_get_time; 44void (*rtc_sh_get_time)(struct timespec *) = null_rtc_get_time;
53int (*rtc_sh_set_time)(const time_t) = null_rtc_set_time; 45int (*rtc_sh_set_time)(const time_t) = null_rtc_set_time;
54 46
@@ -112,7 +104,6 @@ int do_settimeofday(struct timespec *tv)
112EXPORT_SYMBOL(do_settimeofday); 104EXPORT_SYMBOL(do_settimeofday);
113#endif /* !CONFIG_GENERIC_TIME */ 105#endif /* !CONFIG_GENERIC_TIME */
114 106
115#ifndef CONFIG_GENERIC_CLOCKEVENTS
116/* last time the RTC clock got updated */ 107/* last time the RTC clock got updated */
117static long last_rtc_update; 108static long last_rtc_update;
118 109
@@ -156,7 +147,6 @@ void handle_timer_tick(void)
156 update_process_times(user_mode(get_irq_regs())); 147 update_process_times(user_mode(get_irq_regs()));
157#endif 148#endif
158} 149}
159#endif /* !CONFIG_GENERIC_CLOCKEVENTS */
160 150
161#ifdef CONFIG_PM 151#ifdef CONFIG_PM
162int timer_suspend(struct sys_device *dev, pm_message_t state) 152int timer_suspend(struct sys_device *dev, pm_message_t state)
@@ -189,7 +179,12 @@ static struct sysdev_class timer_sysclass = {
189 179
190static int __init timer_init_sysfs(void) 180static int __init timer_init_sysfs(void)
191{ 181{
192 int ret = sysdev_class_register(&timer_sysclass); 182 int ret;
183
184 if (!sys_timer)
185 return 0;
186
187 ret = sysdev_class_register(&timer_sysclass);
193 if (ret != 0) 188 if (ret != 0)
194 return ret; 189 return ret;
195 190
@@ -200,42 +195,21 @@ device_initcall(timer_init_sysfs);
200 195
201void (*board_time_init)(void); 196void (*board_time_init)(void);
202 197
203/* 198struct clocksource clocksource_sh = {
204 * Shamelessly based on the MIPS and Sparc64 work.
205 */
206static unsigned long timer_ticks_per_nsec_quotient __read_mostly;
207unsigned long sh_hpt_frequency = 0;
208
209#define NSEC_PER_CYC_SHIFT 10
210
211static struct clocksource clocksource_sh = {
212 .name = "SuperH", 199 .name = "SuperH",
213 .rating = 200,
214 .mask = CLOCKSOURCE_MASK(32),
215 .read = null_hpt_read,
216 .shift = 16,
217 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
218}; 200};
219 201
220static void __init init_sh_clocksource(void)
221{
222 if (!sh_hpt_frequency || clocksource_sh.read == null_hpt_read)
223 return;
224
225 clocksource_sh.mult = clocksource_hz2mult(sh_hpt_frequency,
226 clocksource_sh.shift);
227
228 timer_ticks_per_nsec_quotient =
229 clocksource_hz2mult(sh_hpt_frequency, NSEC_PER_CYC_SHIFT);
230
231 clocksource_register(&clocksource_sh);
232}
233
234#ifdef CONFIG_GENERIC_TIME 202#ifdef CONFIG_GENERIC_TIME
235unsigned long long sched_clock(void) 203unsigned long long sched_clock(void)
236{ 204{
237 unsigned long long ticks = clocksource_sh.read(); 205 unsigned long long cycles;
238 return (ticks * timer_ticks_per_nsec_quotient) >> NSEC_PER_CYC_SHIFT; 206
207 /* jiffies based sched_clock if no clocksource is installed */
208 if (!clocksource_sh.rating)
209 return (unsigned long long)jiffies * (NSEC_PER_SEC / HZ);
210
211 cycles = clocksource_sh.read();
212 return cyc2ns(&clocksource_sh, cycles);
239} 213}
240#endif 214#endif
241 215
@@ -259,17 +233,8 @@ void __init time_init(void)
259 * initialized for us. 233 * initialized for us.
260 */ 234 */
261 sys_timer = get_sys_timer(); 235 sys_timer = get_sys_timer();
262 printk(KERN_INFO "Using %s for system timer\n", sys_timer->name); 236 if (unlikely(!sys_timer))
263 237 panic("System timer missing.\n");
264
265 if (sys_timer->ops->read)
266 clocksource_sh.read = sys_timer->ops->read;
267
268 init_sh_clocksource();
269
270 if (sh_hpt_frequency)
271 printk("Using %lu.%03lu MHz high precision timer.\n",
272 ((sh_hpt_frequency + 500) / 1000) / 1000,
273 ((sh_hpt_frequency + 500) / 1000) % 1000);
274 238
239 printk(KERN_INFO "Using %s for system timer\n", sys_timer->name);
275} 240}
diff --git a/arch/sh/kernel/timers/timer-mtu2.c b/arch/sh/kernel/timers/timer-mtu2.c
index c3d237e1d566..9a77ae86b403 100644
--- a/arch/sh/kernel/timers/timer-mtu2.c
+++ b/arch/sh/kernel/timers/timer-mtu2.c
@@ -35,7 +35,8 @@
35#define MTU2_TSR_1 0xfffe4385 35#define MTU2_TSR_1 0xfffe4385
36#define MTU2_TCNT_1 0xfffe4386 /* 16-bit counter */ 36#define MTU2_TCNT_1 0xfffe4386 /* 16-bit counter */
37 37
38#if defined(CONFIG_CPU_SUBTYPE_SH7201) 38#if defined(CONFIG_CPU_SUBTYPE_SH7201) || \
39 defined(CONFIG_CPU_SUBTYPE_SH7203)
39#define MTU2_TGRA_1 0xfffe4388 40#define MTU2_TGRA_1 0xfffe4388
40#else 41#else
41#define MTU2_TGRA_1 0xfffe438a 42#define MTU2_TGRA_1 0xfffe438a
diff --git a/arch/sh/kernel/timers/timer-tmu.c b/arch/sh/kernel/timers/timer-tmu.c
index 0db3f9510336..10b5a6f17cc0 100644
--- a/arch/sh/kernel/timers/timer-tmu.c
+++ b/arch/sh/kernel/timers/timer-tmu.c
@@ -146,7 +146,14 @@ static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
146 _tmu_clear_status(TMU0); 146 _tmu_clear_status(TMU0);
147 _tmu_set_irq(TMU0,tmu0_clockevent.mode != CLOCK_EVT_MODE_ONESHOT); 147 _tmu_set_irq(TMU0,tmu0_clockevent.mode != CLOCK_EVT_MODE_ONESHOT);
148 148
149 evt->event_handler(evt); 149 switch (tmu0_clockevent.mode) {
150 case CLOCK_EVT_MODE_ONESHOT:
151 case CLOCK_EVT_MODE_PERIODIC:
152 evt->event_handler(evt);
153 break;
154 default:
155 break;
156 }
150 157
151 return IRQ_HANDLED; 158 return IRQ_HANDLED;
152} 159}
@@ -237,6 +244,7 @@ static int tmu_timer_init(void)
237 !defined(CONFIG_CPU_SUBTYPE_SH7721) && \ 244 !defined(CONFIG_CPU_SUBTYPE_SH7721) && \
238 !defined(CONFIG_CPU_SUBTYPE_SH7760) && \ 245 !defined(CONFIG_CPU_SUBTYPE_SH7760) && \
239 !defined(CONFIG_CPU_SUBTYPE_SH7785) && \ 246 !defined(CONFIG_CPU_SUBTYPE_SH7785) && \
247 !defined(CONFIG_CPU_SUBTYPE_SH7786) && \
240 !defined(CONFIG_CPU_SUBTYPE_SHX3) 248 !defined(CONFIG_CPU_SUBTYPE_SHX3)
241 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR); 249 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
242#endif 250#endif
@@ -254,7 +262,14 @@ static int tmu_timer_init(void)
254 262
255 _tmu_start(TMU1); 263 _tmu_start(TMU1);
256 264
257 sh_hpt_frequency = clk_get_rate(&tmu1_clk); 265 clocksource_sh.rating = 200;
266 clocksource_sh.mask = CLOCKSOURCE_MASK(32);
267 clocksource_sh.read = tmu_timer_read;
268 clocksource_sh.shift = 10;
269 clocksource_sh.mult = clocksource_hz2mult(clk_get_rate(&tmu1_clk),
270 clocksource_sh.shift);
271 clocksource_sh.flags = CLOCK_SOURCE_IS_CONTINUOUS;
272 clocksource_register(&clocksource_sh);
258 273
259 tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC, 274 tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC,
260 tmu0_clockevent.shift); 275 tmu0_clockevent.shift);
@@ -264,6 +279,7 @@ static int tmu_timer_init(void)
264 clockevent_delta2ns(1, &tmu0_clockevent); 279 clockevent_delta2ns(1, &tmu0_clockevent);
265 280
266 tmu0_clockevent.cpumask = cpumask_of(0); 281 tmu0_clockevent.cpumask = cpumask_of(0);
282 tmu0_clockevent.rating = 100;
267 283
268 clockevents_register_device(&tmu0_clockevent); 284 clockevents_register_device(&tmu0_clockevent);
269 285
@@ -274,7 +290,6 @@ static struct sys_timer_ops tmu_timer_ops = {
274 .init = tmu_timer_init, 290 .init = tmu_timer_init,
275 .start = tmu_timer_start, 291 .start = tmu_timer_start,
276 .stop = tmu_timer_stop, 292 .stop = tmu_timer_stop,
277 .read = tmu_timer_read,
278}; 293};
279 294
280struct sys_timer tmu_timer = { 295struct sys_timer tmu_timer = {
diff --git a/arch/sh/kernel/vmlinux_32.lds.S b/arch/sh/kernel/vmlinux_32.lds.S
index 7b4b82bd1156..d0b2a715cd14 100644
--- a/arch/sh/kernel/vmlinux_32.lds.S
+++ b/arch/sh/kernel/vmlinux_32.lds.S
@@ -15,7 +15,10 @@ OUTPUT_ARCH(sh)
15ENTRY(_start) 15ENTRY(_start)
16SECTIONS 16SECTIONS
17{ 17{
18#ifdef CONFIG_32BIT 18#ifdef CONFIG_PMB_FIXED
19 . = CONFIG_PAGE_OFFSET + (CONFIG_MEMORY_START & 0x1fffffff) +
20 CONFIG_ZERO_PAGE_OFFSET;
21#elif defined(CONFIG_32BIT)
19 . = CONFIG_PAGE_OFFSET + CONFIG_ZERO_PAGE_OFFSET; 22 . = CONFIG_PAGE_OFFSET + CONFIG_ZERO_PAGE_OFFSET;
20#else 23#else
21 . = CONFIG_PAGE_OFFSET + CONFIG_MEMORY_START + CONFIG_ZERO_PAGE_OFFSET; 24 . = CONFIG_PAGE_OFFSET + CONFIG_MEMORY_START + CONFIG_ZERO_PAGE_OFFSET;
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 555ec9714b9e..10c24356d2d5 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -57,7 +57,7 @@ config 32BIT
57 bool 57 bool
58 default y if CPU_SH5 58 default y if CPU_SH5
59 59
60config PMB 60config PMB_ENABLE
61 bool "Support 32-bit physical addressing through PMB" 61 bool "Support 32-bit physical addressing through PMB"
62 depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) 62 depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
63 select 32BIT 63 select 32BIT
@@ -67,6 +67,33 @@ config PMB
67 32-bits through the SH-4A PMB. If this is not set, legacy 67 32-bits through the SH-4A PMB. If this is not set, legacy
68 29-bit physical addressing will be used. 68 29-bit physical addressing will be used.
69 69
70choice
71 prompt "PMB handling type"
72 depends on PMB_ENABLE
73 default PMB_FIXED
74
75config PMB
76 bool "PMB"
77 depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
78 select 32BIT
79 help
80 If you say Y here, physical addressing will be extended to
81 32-bits through the SH-4A PMB. If this is not set, legacy
82 29-bit physical addressing will be used.
83
84config PMB_FIXED
85 bool "fixed PMB"
86 depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || \
87 CPU_SUBTYPE_SH7785)
88 select 32BIT
89 help
90 If this option is enabled, fixed PMB mappings are inherited
91 from the boot loader, and the kernel does not attempt dynamic
92 management. This is the closest to legacy 29-bit physical mode,
93 and allows systems to support up to 512MiB of system memory.
94
95endchoice
96
70config X2TLB 97config X2TLB
71 bool "Enable extended TLB mode" 98 bool "Enable extended TLB mode"
72 depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL 99 depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL
diff --git a/arch/sh/mm/Makefile_32 b/arch/sh/mm/Makefile_32
index cb2f3f299591..986a1e055834 100644
--- a/arch/sh/mm/Makefile_32
+++ b/arch/sh/mm/Makefile_32
@@ -25,8 +25,10 @@ obj-$(CONFIG_CPU_SH4) += cache-debugfs.o
25endif 25endif
26 26
27ifdef CONFIG_MMU 27ifdef CONFIG_MMU
28obj-$(CONFIG_CPU_SH3) += tlb-sh3.o 28tlb-$(CONFIG_CPU_SH3) := tlb-sh3.o
29obj-$(CONFIG_CPU_SH4) += tlb-sh4.o 29tlb-$(CONFIG_CPU_SH4) := tlb-sh4.o
30tlb-$(CONFIG_CPU_HAS_PTEAEX) := tlb-pteaex.o
31obj-y += $(tlb-y)
30ifndef CONFIG_CACHE_OFF 32ifndef CONFIG_CACHE_OFF
31obj-$(CONFIG_CPU_SH4) += pg-sh4.o 33obj-$(CONFIG_CPU_SH4) += pg-sh4.o
32obj-$(CONFIG_SH7705_CACHE_32KB) += pg-sh7705.o 34obj-$(CONFIG_SH7705_CACHE_32KB) += pg-sh7705.o
@@ -35,6 +37,7 @@ endif
35 37
36obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o 38obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
37obj-$(CONFIG_PMB) += pmb.o 39obj-$(CONFIG_PMB) += pmb.o
40obj-$(CONFIG_PMB_FIXED) += pmb-fixed.o
38obj-$(CONFIG_NUMA) += numa.o 41obj-$(CONFIG_NUMA) += numa.o
39 42
40EXTRA_CFLAGS += -Werror 43EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/mm/asids-debugfs.c b/arch/sh/mm/asids-debugfs.c
index 8e912a15e94f..cd8c3bf39b5a 100644
--- a/arch/sh/mm/asids-debugfs.c
+++ b/arch/sh/mm/asids-debugfs.c
@@ -37,10 +37,8 @@ static int asids_seq_show(struct seq_file *file, void *iter)
37 continue; 37 continue;
38 38
39 if (p->mm) 39 if (p->mm)
40 seq_printf(file, "%5d : %02lx\n", pid, 40 seq_printf(file, "%5d : %04lx\n", pid,
41 cpu_asid(smp_processor_id(), p->mm)); 41 cpu_asid(smp_processor_id(), p->mm));
42 else
43 seq_printf(file, "%5d : (none)\n", pid);
44 } 42 }
45 43
46 read_unlock(&tasklist_lock); 44 read_unlock(&tasklist_lock);
diff --git a/arch/sh/mm/ioremap_32.c b/arch/sh/mm/ioremap_32.c
index 32946fba123e..60cc486d2c2c 100644
--- a/arch/sh/mm/ioremap_32.c
+++ b/arch/sh/mm/ioremap_32.c
@@ -59,11 +59,13 @@ void __iomem *__ioremap(unsigned long phys_addr, unsigned long size,
59 if (is_pci_memaddr(phys_addr) && is_pci_memaddr(last_addr)) 59 if (is_pci_memaddr(phys_addr) && is_pci_memaddr(last_addr))
60 return (void __iomem *)phys_addr; 60 return (void __iomem *)phys_addr;
61 61
62#if !defined(CONFIG_PMB_FIXED)
62 /* 63 /*
63 * Don't allow anybody to remap normal RAM that we're using.. 64 * Don't allow anybody to remap normal RAM that we're using..
64 */ 65 */
65 if (phys_addr < virt_to_phys(high_memory)) 66 if (phys_addr < virt_to_phys(high_memory))
66 return NULL; 67 return NULL;
68#endif
67 69
68 /* 70 /*
69 * Mappings have to be page-aligned 71 * Mappings have to be page-aligned
@@ -81,7 +83,7 @@ void __iomem *__ioremap(unsigned long phys_addr, unsigned long size,
81 area->phys_addr = phys_addr; 83 area->phys_addr = phys_addr;
82 orig_addr = addr = (unsigned long)area->addr; 84 orig_addr = addr = (unsigned long)area->addr;
83 85
84#ifdef CONFIG_32BIT 86#ifdef CONFIG_PMB
85 /* 87 /*
86 * First try to remap through the PMB once a valid VMA has been 88 * First try to remap through the PMB once a valid VMA has been
87 * established. Smaller allocations (or the rest of the size 89 * established. Smaller allocations (or the rest of the size
@@ -119,10 +121,10 @@ void __iounmap(void __iomem *addr)
119 unsigned long seg = PXSEG(vaddr); 121 unsigned long seg = PXSEG(vaddr);
120 struct vm_struct *p; 122 struct vm_struct *p;
121 123
122 if (seg < P3SEG || seg >= P3_ADDR_MAX || is_pci_memaddr(vaddr)) 124 if (seg < P3SEG || vaddr >= P3_ADDR_MAX || is_pci_memaddr(vaddr))
123 return; 125 return;
124 126
125#ifdef CONFIG_32BIT 127#ifdef CONFIG_PMB
126 /* 128 /*
127 * Purge any PMB entries that may have been established for this 129 * Purge any PMB entries that may have been established for this
128 * mapping, then proceed with conventional VMA teardown. 130 * mapping, then proceed with conventional VMA teardown.
diff --git a/arch/sh/mm/pmb-fixed.c b/arch/sh/mm/pmb-fixed.c
new file mode 100644
index 000000000000..43c8eac4d8a1
--- /dev/null
+++ b/arch/sh/mm/pmb-fixed.c
@@ -0,0 +1,45 @@
1/*
2 * arch/sh/mm/fixed_pmb.c
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/init.h>
11#include <linux/mm.h>
12#include <linux/io.h>
13#include <asm/mmu.h>
14#include <asm/mmu_context.h>
15
16static int __uses_jump_to_uncached fixed_pmb_init(void)
17{
18 int i;
19 unsigned long addr, data;
20
21 jump_to_uncached();
22
23 for (i = 0; i < PMB_ENTRY_MAX; i++) {
24 addr = PMB_DATA + (i << PMB_E_SHIFT);
25 data = ctrl_inl(addr);
26 if (!(data & PMB_V))
27 continue;
28
29 if (data & PMB_C) {
30#if defined(CONFIG_CACHE_WRITETHROUGH)
31 data |= PMB_WT;
32#elif defined(CONFIG_CACHE_WRITEBACK)
33 data &= ~PMB_WT;
34#else
35 data &= ~(PMB_C | PMB_WT);
36#endif
37 }
38 ctrl_outl(data, addr);
39 }
40
41 back_to_cached();
42
43 return 0;
44}
45arch_initcall(fixed_pmb_init);
diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c
index 84241676265e..b1a714a92b14 100644
--- a/arch/sh/mm/pmb.c
+++ b/arch/sh/mm/pmb.c
@@ -15,6 +15,8 @@
15 */ 15 */
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/sysdev.h>
19#include <linux/cpu.h>
18#include <linux/module.h> 20#include <linux/module.h>
19#include <linux/slab.h> 21#include <linux/slab.h>
20#include <linux/bitops.h> 22#include <linux/bitops.h>
@@ -402,3 +404,39 @@ static int __init pmb_debugfs_init(void)
402 return 0; 404 return 0;
403} 405}
404postcore_initcall(pmb_debugfs_init); 406postcore_initcall(pmb_debugfs_init);
407
408#ifdef CONFIG_PM
409static int pmb_sysdev_suspend(struct sys_device *dev, pm_message_t state)
410{
411 static pm_message_t prev_state;
412
413 /* Restore the PMB after a resume from hibernation */
414 if (state.event == PM_EVENT_ON &&
415 prev_state.event == PM_EVENT_FREEZE) {
416 struct pmb_entry *pmbe;
417 spin_lock_irq(&pmb_list_lock);
418 for (pmbe = pmb_list; pmbe; pmbe = pmbe->next)
419 set_pmb_entry(pmbe);
420 spin_unlock_irq(&pmb_list_lock);
421 }
422 prev_state = state;
423 return 0;
424}
425
426static int pmb_sysdev_resume(struct sys_device *dev)
427{
428 return pmb_sysdev_suspend(dev, PMSG_ON);
429}
430
431static struct sysdev_driver pmb_sysdev_driver = {
432 .suspend = pmb_sysdev_suspend,
433 .resume = pmb_sysdev_resume,
434};
435
436static int __init pmb_sysdev_init(void)
437{
438 return sysdev_driver_register(&cpu_sysdev_class, &pmb_sysdev_driver);
439}
440
441subsys_initcall(pmb_sysdev_init);
442#endif
diff --git a/arch/sh/mm/tlb-pteaex.c b/arch/sh/mm/tlb-pteaex.c
new file mode 100644
index 000000000000..2aab3ea934d7
--- /dev/null
+++ b/arch/sh/mm/tlb-pteaex.c
@@ -0,0 +1,96 @@
1/*
2 * arch/sh/mm/tlb-pteaex.c
3 *
4 * TLB operations for SH-X3 CPUs featuring PTE ASID Extensions.
5 *
6 * Copyright (C) 2009 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/kernel.h>
13#include <linux/mm.h>
14#include <linux/io.h>
15#include <asm/system.h>
16#include <asm/mmu_context.h>
17#include <asm/cacheflush.h>
18
19void update_mmu_cache(struct vm_area_struct * vma,
20 unsigned long address, pte_t pte)
21{
22 unsigned long flags;
23 unsigned long pteval;
24 unsigned long vpn;
25
26 /* Ptrace may call this routine. */
27 if (vma && current->active_mm != vma->vm_mm)
28 return;
29
30#ifndef CONFIG_CACHE_OFF
31 {
32 unsigned long pfn = pte_pfn(pte);
33
34 if (pfn_valid(pfn)) {
35 struct page *page = pfn_to_page(pfn);
36
37 if (!test_bit(PG_mapped, &page->flags)) {
38 unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
39 __flush_wback_region((void *)P1SEGADDR(phys),
40 PAGE_SIZE);
41 __set_bit(PG_mapped, &page->flags);
42 }
43 }
44 }
45#endif
46
47 local_irq_save(flags);
48
49 /* Set PTEH register */
50 vpn = address & MMU_VPN_MASK;
51 __raw_writel(vpn, MMU_PTEH);
52
53 /* Set PTEAEX */
54 __raw_writel(get_asid(), MMU_PTEAEX);
55
56 pteval = pte.pte_low;
57
58 /* Set PTEA register */
59#ifdef CONFIG_X2TLB
60 /*
61 * For the extended mode TLB this is trivial, only the ESZ and
62 * EPR bits need to be written out to PTEA, with the remainder of
63 * the protection bits (with the exception of the compat-mode SZ
64 * and PR bits, which are cleared) being written out in PTEL.
65 */
66 __raw_writel(pte.pte_high, MMU_PTEA);
67#endif
68
69 /* Set PTEL register */
70 pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
71#ifdef CONFIG_CACHE_WRITETHROUGH
72 pteval |= _PAGE_WT;
73#endif
74 /* conveniently, we want all the software flags to be 0 anyway */
75 __raw_writel(pteval, MMU_PTEL);
76
77 /* Load the TLB */
78 asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
79 local_irq_restore(flags);
80}
81
82/*
83 * While SH-X2 extended TLB mode splits out the memory-mapped I/UTLB
84 * data arrays, SH-X3 cores with PTEAEX split out the memory-mapped
85 * address arrays. In compat mode the second array is inaccessible, while
86 * in extended mode, the legacy 8-bit ASID field in address array 1 has
87 * undefined behaviour.
88 */
89void __uses_jump_to_uncached local_flush_tlb_one(unsigned long asid,
90 unsigned long page)
91{
92 jump_to_uncached();
93 __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT);
94 __raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
95 back_to_cached();
96}
diff --git a/arch/sh/oprofile/common.c b/arch/sh/oprofile/common.c
index 1d97d64cb95f..1b9d4304b3bf 100644
--- a/arch/sh/oprofile/common.c
+++ b/arch/sh/oprofile/common.c
@@ -107,6 +107,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
107 case CPU_SH7780: 107 case CPU_SH7780:
108 case CPU_SH7781: 108 case CPU_SH7781:
109 case CPU_SH7785: 109 case CPU_SH7785:
110 case CPU_SH7786:
110 case CPU_SH7723: 111 case CPU_SH7723:
111 case CPU_SHX3: 112 case CPU_SHX3:
112 lmodel = &op_model_sh4a_ops; 113 lmodel = &op_model_sh4a_ops;
diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types
index 284b7e867496..8477b5d884fd 100644
--- a/arch/sh/tools/mach-types
+++ b/arch/sh/tools/mach-types
@@ -52,3 +52,6 @@ RSK7203 SH_RSK7203
52AP325RXA SH_AP325RXA 52AP325RXA SH_AP325RXA
53SH7763RDP SH_SH7763RDP 53SH7763RDP SH_SH7763RDP
54SH7785LCR SH_SH7785LCR 54SH7785LCR SH_SH7785LCR
55URQUELL SH_URQUELL
56ESPT SH_ESPT
57POLARIS SH_POLARIS
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 1525882190fd..1efb2879a94f 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
2obj-$(CONFIG_X86_CYCLONE_TIMER) += cyclone.o 2obj-$(CONFIG_X86_CYCLONE_TIMER) += cyclone.o
3obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o 3obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
4obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o 4obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
5obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o
diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
new file mode 100644
index 000000000000..7783b42f6914
--- /dev/null
+++ b/drivers/clocksource/sh_cmt.c
@@ -0,0 +1,615 @@
1/*
2 * SuperH Timer Support - CMT
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/bootmem.h>
22#include <linux/platform_device.h>
23#include <linux/spinlock.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/io.h>
27#include <linux/clk.h>
28#include <linux/irq.h>
29#include <linux/err.h>
30#include <linux/clocksource.h>
31#include <linux/clockchips.h>
32#include <linux/sh_cmt.h>
33
34struct sh_cmt_priv {
35 void __iomem *mapbase;
36 struct clk *clk;
37 unsigned long width; /* 16 or 32 bit version of hardware block */
38 unsigned long overflow_bit;
39 unsigned long clear_bits;
40 struct irqaction irqaction;
41 struct platform_device *pdev;
42
43 unsigned long flags;
44 unsigned long match_value;
45 unsigned long next_match_value;
46 unsigned long max_match_value;
47 unsigned long rate;
48 spinlock_t lock;
49 struct clock_event_device ced;
50 unsigned long total_cycles;
51};
52
53static DEFINE_SPINLOCK(sh_cmt_lock);
54
55#define CMSTR -1 /* shared register */
56#define CMCSR 0 /* channel register */
57#define CMCNT 1 /* channel register */
58#define CMCOR 2 /* channel register */
59
60static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
61{
62 struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
63 void __iomem *base = p->mapbase;
64 unsigned long offs;
65
66 if (reg_nr == CMSTR) {
67 offs = 0;
68 base -= cfg->channel_offset;
69 } else
70 offs = reg_nr;
71
72 if (p->width == 16)
73 offs <<= 1;
74 else {
75 offs <<= 2;
76 if ((reg_nr == CMCNT) || (reg_nr == CMCOR))
77 return ioread32(base + offs);
78 }
79
80 return ioread16(base + offs);
81}
82
83static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr,
84 unsigned long value)
85{
86 struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
87 void __iomem *base = p->mapbase;
88 unsigned long offs;
89
90 if (reg_nr == CMSTR) {
91 offs = 0;
92 base -= cfg->channel_offset;
93 } else
94 offs = reg_nr;
95
96 if (p->width == 16)
97 offs <<= 1;
98 else {
99 offs <<= 2;
100 if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) {
101 iowrite32(value, base + offs);
102 return;
103 }
104 }
105
106 iowrite16(value, base + offs);
107}
108
109static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
110 int *has_wrapped)
111{
112 unsigned long v1, v2, v3;
113
114 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
115 do {
116 v1 = sh_cmt_read(p, CMCNT);
117 v2 = sh_cmt_read(p, CMCNT);
118 v3 = sh_cmt_read(p, CMCNT);
119 } while (unlikely((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1)
120 || (v3 > v1 && v3 < v2)));
121
122 *has_wrapped = sh_cmt_read(p, CMCSR) & p->overflow_bit;
123 return v2;
124}
125
126
127static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
128{
129 struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
130 unsigned long flags, value;
131
132 /* start stop register shared by multiple timer channels */
133 spin_lock_irqsave(&sh_cmt_lock, flags);
134 value = sh_cmt_read(p, CMSTR);
135
136 if (start)
137 value |= 1 << cfg->timer_bit;
138 else
139 value &= ~(1 << cfg->timer_bit);
140
141 sh_cmt_write(p, CMSTR, value);
142 spin_unlock_irqrestore(&sh_cmt_lock, flags);
143}
144
145static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
146{
147 struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
148 int ret;
149
150 /* enable clock */
151 ret = clk_enable(p->clk);
152 if (ret) {
153 pr_err("sh_cmt: cannot enable clock \"%s\"\n", cfg->clk);
154 return ret;
155 }
156 *rate = clk_get_rate(p->clk) / 8;
157
158 /* make sure channel is disabled */
159 sh_cmt_start_stop_ch(p, 0);
160
161 /* configure channel, periodic mode and maximum timeout */
162 if (p->width == 16)
163 sh_cmt_write(p, CMCSR, 0);
164 else
165 sh_cmt_write(p, CMCSR, 0x01a4);
166
167 sh_cmt_write(p, CMCOR, 0xffffffff);
168 sh_cmt_write(p, CMCNT, 0);
169
170 /* enable channel */
171 sh_cmt_start_stop_ch(p, 1);
172 return 0;
173}
174
175static void sh_cmt_disable(struct sh_cmt_priv *p)
176{
177 /* disable channel */
178 sh_cmt_start_stop_ch(p, 0);
179
180 /* stop clock */
181 clk_disable(p->clk);
182}
183
184/* private flags */
185#define FLAG_CLOCKEVENT (1 << 0)
186#define FLAG_CLOCKSOURCE (1 << 1)
187#define FLAG_REPROGRAM (1 << 2)
188#define FLAG_SKIPEVENT (1 << 3)
189#define FLAG_IRQCONTEXT (1 << 4)
190
191static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p,
192 int absolute)
193{
194 unsigned long new_match;
195 unsigned long value = p->next_match_value;
196 unsigned long delay = 0;
197 unsigned long now = 0;
198 int has_wrapped;
199
200 now = sh_cmt_get_counter(p, &has_wrapped);
201 p->flags |= FLAG_REPROGRAM; /* force reprogram */
202
203 if (has_wrapped) {
204 /* we're competing with the interrupt handler.
205 * -> let the interrupt handler reprogram the timer.
206 * -> interrupt number two handles the event.
207 */
208 p->flags |= FLAG_SKIPEVENT;
209 return;
210 }
211
212 if (absolute)
213 now = 0;
214
215 do {
216 /* reprogram the timer hardware,
217 * but don't save the new match value yet.
218 */
219 new_match = now + value + delay;
220 if (new_match > p->max_match_value)
221 new_match = p->max_match_value;
222
223 sh_cmt_write(p, CMCOR, new_match);
224
225 now = sh_cmt_get_counter(p, &has_wrapped);
226 if (has_wrapped && (new_match > p->match_value)) {
227 /* we are changing to a greater match value,
228 * so this wrap must be caused by the counter
229 * matching the old value.
230 * -> first interrupt reprograms the timer.
231 * -> interrupt number two handles the event.
232 */
233 p->flags |= FLAG_SKIPEVENT;
234 break;
235 }
236
237 if (has_wrapped) {
238 /* we are changing to a smaller match value,
239 * so the wrap must be caused by the counter
240 * matching the new value.
241 * -> save programmed match value.
242 * -> let isr handle the event.
243 */
244 p->match_value = new_match;
245 break;
246 }
247
248 /* be safe: verify hardware settings */
249 if (now < new_match) {
250 /* timer value is below match value, all good.
251 * this makes sure we won't miss any match events.
252 * -> save programmed match value.
253 * -> let isr handle the event.
254 */
255 p->match_value = new_match;
256 break;
257 }
258
259 /* the counter has reached a value greater
260 * than our new match value. and since the
261 * has_wrapped flag isn't set we must have
262 * programmed a too close event.
263 * -> increase delay and retry.
264 */
265 if (delay)
266 delay <<= 1;
267 else
268 delay = 1;
269
270 if (!delay)
271 pr_warning("sh_cmt: too long delay\n");
272
273 } while (delay);
274}
275
276static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
277{
278 unsigned long flags;
279
280 if (delta > p->max_match_value)
281 pr_warning("sh_cmt: delta out of range\n");
282
283 spin_lock_irqsave(&p->lock, flags);
284 p->next_match_value = delta;
285 sh_cmt_clock_event_program_verify(p, 0);
286 spin_unlock_irqrestore(&p->lock, flags);
287}
288
289static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
290{
291 struct sh_cmt_priv *p = dev_id;
292
293 /* clear flags */
294 sh_cmt_write(p, CMCSR, sh_cmt_read(p, CMCSR) & p->clear_bits);
295
296 /* update clock source counter to begin with if enabled
297 * the wrap flag should be cleared by the timer specific
298 * isr before we end up here.
299 */
300 if (p->flags & FLAG_CLOCKSOURCE)
301 p->total_cycles += p->match_value;
302
303 if (!(p->flags & FLAG_REPROGRAM))
304 p->next_match_value = p->max_match_value;
305
306 p->flags |= FLAG_IRQCONTEXT;
307
308 if (p->flags & FLAG_CLOCKEVENT) {
309 if (!(p->flags & FLAG_SKIPEVENT)) {
310 if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) {
311 p->next_match_value = p->max_match_value;
312 p->flags |= FLAG_REPROGRAM;
313 }
314
315 p->ced.event_handler(&p->ced);
316 }
317 }
318
319 p->flags &= ~FLAG_SKIPEVENT;
320
321 if (p->flags & FLAG_REPROGRAM) {
322 p->flags &= ~FLAG_REPROGRAM;
323 sh_cmt_clock_event_program_verify(p, 1);
324
325 if (p->flags & FLAG_CLOCKEVENT)
326 if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN)
327 || (p->match_value == p->next_match_value))
328 p->flags &= ~FLAG_REPROGRAM;
329 }
330
331 p->flags &= ~FLAG_IRQCONTEXT;
332
333 return IRQ_HANDLED;
334}
335
336static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag)
337{
338 int ret = 0;
339 unsigned long flags;
340
341 spin_lock_irqsave(&p->lock, flags);
342
343 if (!(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
344 ret = sh_cmt_enable(p, &p->rate);
345
346 if (ret)
347 goto out;
348 p->flags |= flag;
349
350 /* setup timeout if no clockevent */
351 if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT)))
352 sh_cmt_set_next(p, p->max_match_value);
353 out:
354 spin_unlock_irqrestore(&p->lock, flags);
355
356 return ret;
357}
358
359static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag)
360{
361 unsigned long flags;
362 unsigned long f;
363
364 spin_lock_irqsave(&p->lock, flags);
365
366 f = p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
367 p->flags &= ~flag;
368
369 if (f && !(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
370 sh_cmt_disable(p);
371
372 /* adjust the timeout to maximum if only clocksource left */
373 if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE))
374 sh_cmt_set_next(p, p->max_match_value);
375
376 spin_unlock_irqrestore(&p->lock, flags);
377}
378
379static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced)
380{
381 return container_of(ced, struct sh_cmt_priv, ced);
382}
383
384static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic)
385{
386 struct clock_event_device *ced = &p->ced;
387
388 sh_cmt_start(p, FLAG_CLOCKEVENT);
389
390 /* TODO: calculate good shift from rate and counter bit width */
391
392 ced->shift = 32;
393 ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
394 ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced);
395 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
396
397 if (periodic)
398 sh_cmt_set_next(p, (p->rate + HZ/2) / HZ);
399 else
400 sh_cmt_set_next(p, p->max_match_value);
401}
402
403static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
404 struct clock_event_device *ced)
405{
406 struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
407
408 /* deal with old setting first */
409 switch (ced->mode) {
410 case CLOCK_EVT_MODE_PERIODIC:
411 case CLOCK_EVT_MODE_ONESHOT:
412 sh_cmt_stop(p, FLAG_CLOCKEVENT);
413 break;
414 default:
415 break;
416 }
417
418 switch (mode) {
419 case CLOCK_EVT_MODE_PERIODIC:
420 pr_info("sh_cmt: %s used for periodic clock events\n",
421 ced->name);
422 sh_cmt_clock_event_start(p, 1);
423 break;
424 case CLOCK_EVT_MODE_ONESHOT:
425 pr_info("sh_cmt: %s used for oneshot clock events\n",
426 ced->name);
427 sh_cmt_clock_event_start(p, 0);
428 break;
429 case CLOCK_EVT_MODE_SHUTDOWN:
430 case CLOCK_EVT_MODE_UNUSED:
431 sh_cmt_stop(p, FLAG_CLOCKEVENT);
432 break;
433 default:
434 break;
435 }
436}
437
438static int sh_cmt_clock_event_next(unsigned long delta,
439 struct clock_event_device *ced)
440{
441 struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
442
443 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
444 if (likely(p->flags & FLAG_IRQCONTEXT))
445 p->next_match_value = delta;
446 else
447 sh_cmt_set_next(p, delta);
448
449 return 0;
450}
451
452static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
453 char *name, unsigned long rating)
454{
455 struct clock_event_device *ced = &p->ced;
456
457 memset(ced, 0, sizeof(*ced));
458
459 ced->name = name;
460 ced->features = CLOCK_EVT_FEAT_PERIODIC;
461 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
462 ced->rating = rating;
463 ced->cpumask = cpumask_of(0);
464 ced->set_next_event = sh_cmt_clock_event_next;
465 ced->set_mode = sh_cmt_clock_event_mode;
466
467 pr_info("sh_cmt: %s used for clock events\n", ced->name);
468 ced->mult = 1; /* work around misplaced WARN_ON() in clockevents.c */
469 clockevents_register_device(ced);
470}
471
472int sh_cmt_register(struct sh_cmt_priv *p, char *name,
473 unsigned long clockevent_rating,
474 unsigned long clocksource_rating)
475{
476 if (p->width == (sizeof(p->max_match_value) * 8))
477 p->max_match_value = ~0;
478 else
479 p->max_match_value = (1 << p->width) - 1;
480
481 p->match_value = p->max_match_value;
482 spin_lock_init(&p->lock);
483
484 if (clockevent_rating)
485 sh_cmt_register_clockevent(p, name, clockevent_rating);
486
487 return 0;
488}
489
490static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
491{
492 struct sh_cmt_config *cfg = pdev->dev.platform_data;
493 struct resource *res;
494 int irq, ret;
495 ret = -ENXIO;
496
497 memset(p, 0, sizeof(*p));
498 p->pdev = pdev;
499
500 if (!cfg) {
501 dev_err(&p->pdev->dev, "missing platform data\n");
502 goto err0;
503 }
504
505 platform_set_drvdata(pdev, p);
506
507 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
508 if (!res) {
509 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
510 goto err0;
511 }
512
513 irq = platform_get_irq(p->pdev, 0);
514 if (irq < 0) {
515 dev_err(&p->pdev->dev, "failed to get irq\n");
516 goto err0;
517 }
518
519 /* map memory, let mapbase point to our channel */
520 p->mapbase = ioremap_nocache(res->start, resource_size(res));
521 if (p->mapbase == NULL) {
522 pr_err("sh_cmt: failed to remap I/O memory\n");
523 goto err0;
524 }
525
526 /* request irq using setup_irq() (too early for request_irq()) */
527 p->irqaction.name = cfg->name;
528 p->irqaction.handler = sh_cmt_interrupt;
529 p->irqaction.dev_id = p;
530 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
531 p->irqaction.mask = CPU_MASK_NONE;
532 ret = setup_irq(irq, &p->irqaction);
533 if (ret) {
534 pr_err("sh_cmt: failed to request irq %d\n", irq);
535 goto err1;
536 }
537
538 /* get hold of clock */
539 p->clk = clk_get(&p->pdev->dev, cfg->clk);
540 if (IS_ERR(p->clk)) {
541 pr_err("sh_cmt: cannot get clock \"%s\"\n", cfg->clk);
542 ret = PTR_ERR(p->clk);
543 goto err2;
544 }
545
546 if (resource_size(res) == 6) {
547 p->width = 16;
548 p->overflow_bit = 0x80;
549 p->clear_bits = ~0xc0;
550 } else {
551 p->width = 32;
552 p->overflow_bit = 0x8000;
553 p->clear_bits = ~0xc000;
554 }
555
556 return sh_cmt_register(p, cfg->name,
557 cfg->clockevent_rating,
558 cfg->clocksource_rating);
559 err2:
560 free_irq(irq, p);
561 err1:
562 iounmap(p->mapbase);
563 err0:
564 return ret;
565}
566
567static int __devinit sh_cmt_probe(struct platform_device *pdev)
568{
569 struct sh_cmt_priv *p = platform_get_drvdata(pdev);
570 int ret;
571
572 p = kmalloc(sizeof(*p), GFP_KERNEL);
573 if (p == NULL) {
574 dev_err(&pdev->dev, "failed to allocate driver data\n");
575 return -ENOMEM;
576 }
577
578 ret = sh_cmt_setup(p, pdev);
579 if (ret) {
580 kfree(p);
581
582 platform_set_drvdata(pdev, NULL);
583 }
584 return ret;
585}
586
587static int __devexit sh_cmt_remove(struct platform_device *pdev)
588{
589 return -EBUSY; /* cannot unregister clockevent and clocksource */
590}
591
592static struct platform_driver sh_cmt_device_driver = {
593 .probe = sh_cmt_probe,
594 .remove = __devexit_p(sh_cmt_remove),
595 .driver = {
596 .name = "sh_cmt",
597 }
598};
599
600static int __init sh_cmt_init(void)
601{
602 return platform_driver_register(&sh_cmt_device_driver);
603}
604
605static void __exit sh_cmt_exit(void)
606{
607 platform_driver_unregister(&sh_cmt_device_driver);
608}
609
610module_init(sh_cmt_init);
611module_exit(sh_cmt_exit);
612
613MODULE_AUTHOR("Magnus Damm");
614MODULE_DESCRIPTION("SuperH CMT Timer Driver");
615MODULE_LICENSE("GPL v2");
diff --git a/drivers/input/joystick/maplecontrol.c b/drivers/input/joystick/maplecontrol.c
index e50047bfe938..77cfde571bd9 100644
--- a/drivers/input/joystick/maplecontrol.c
+++ b/drivers/input/joystick/maplecontrol.c
@@ -3,7 +3,7 @@
3 * Based on drivers/usb/iforce.c 3 * Based on drivers/usb/iforce.c
4 * 4 *
5 * Copyright Yaegashi Takeshi, 2001 5 * Copyright Yaegashi Takeshi, 2001
6 * Adrian McMenamin, 2008 6 * Adrian McMenamin, 2008 - 2009
7 */ 7 */
8 8
9#include <linux/kernel.h> 9#include <linux/kernel.h>
@@ -29,7 +29,7 @@ static void dc_pad_callback(struct mapleq *mq)
29 struct maple_device *mapledev = mq->dev; 29 struct maple_device *mapledev = mq->dev;
30 struct dc_pad *pad = maple_get_drvdata(mapledev); 30 struct dc_pad *pad = maple_get_drvdata(mapledev);
31 struct input_dev *dev = pad->dev; 31 struct input_dev *dev = pad->dev;
32 unsigned char *res = mq->recvbuf; 32 unsigned char *res = mq->recvbuf->buf;
33 33
34 buttons = ~le16_to_cpup((__le16 *)(res + 8)); 34 buttons = ~le16_to_cpup((__le16 *)(res + 8));
35 35
diff --git a/drivers/input/keyboard/maple_keyb.c b/drivers/input/keyboard/maple_keyb.c
index 22f17a593be7..5aa2361aef95 100644
--- a/drivers/input/keyboard/maple_keyb.c
+++ b/drivers/input/keyboard/maple_keyb.c
@@ -1,8 +1,8 @@
1/* 1/*
2 * SEGA Dreamcast keyboard driver 2 * SEGA Dreamcast keyboard driver
3 * Based on drivers/usb/usbkbd.c 3 * Based on drivers/usb/usbkbd.c
4 * Copyright YAEGASHI Takeshi, 2001 4 * Copyright (c) YAEGASHI Takeshi, 2001
5 * Porting to 2.6 Copyright Adrian McMenamin, 2007, 2008 5 * Porting to 2.6 Copyright (c) Adrian McMenamin, 2007 - 2009
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
@@ -33,7 +33,7 @@ static DEFINE_MUTEX(maple_keyb_mutex);
33 33
34#define NR_SCANCODES 256 34#define NR_SCANCODES 256
35 35
36MODULE_AUTHOR("YAEGASHI Takeshi, Adrian McMenamin"); 36MODULE_AUTHOR("Adrian McMenamin <adrian@mcmen.demon.co.uk");
37MODULE_DESCRIPTION("SEGA Dreamcast keyboard driver"); 37MODULE_DESCRIPTION("SEGA Dreamcast keyboard driver");
38MODULE_LICENSE("GPL"); 38MODULE_LICENSE("GPL");
39 39
@@ -115,7 +115,7 @@ static void dc_scan_kbd(struct dc_kbd *kbd)
115 input_event(dev, EV_MSC, MSC_SCAN, code); 115 input_event(dev, EV_MSC, MSC_SCAN, code);
116 input_report_key(dev, keycode, 0); 116 input_report_key(dev, keycode, 0);
117 } else 117 } else
118 printk(KERN_DEBUG "maple_keyb: " 118 dev_dbg(&dev->dev,
119 "Unknown key (scancode %#x) released.", 119 "Unknown key (scancode %#x) released.",
120 code); 120 code);
121 } 121 }
@@ -127,7 +127,7 @@ static void dc_scan_kbd(struct dc_kbd *kbd)
127 input_event(dev, EV_MSC, MSC_SCAN, code); 127 input_event(dev, EV_MSC, MSC_SCAN, code);
128 input_report_key(dev, keycode, 1); 128 input_report_key(dev, keycode, 1);
129 } else 129 } else
130 printk(KERN_DEBUG "maple_keyb: " 130 dev_dbg(&dev->dev,
131 "Unknown key (scancode %#x) pressed.", 131 "Unknown key (scancode %#x) pressed.",
132 code); 132 code);
133 } 133 }
@@ -140,7 +140,7 @@ static void dc_kbd_callback(struct mapleq *mq)
140{ 140{
141 struct maple_device *mapledev = mq->dev; 141 struct maple_device *mapledev = mq->dev;
142 struct dc_kbd *kbd = maple_get_drvdata(mapledev); 142 struct dc_kbd *kbd = maple_get_drvdata(mapledev);
143 unsigned long *buf = mq->recvbuf; 143 unsigned long *buf = (unsigned long *)(mq->recvbuf->buf);
144 144
145 /* 145 /*
146 * We should always get the lock because the only 146 * We should always get the lock because the only
@@ -159,22 +159,27 @@ static void dc_kbd_callback(struct mapleq *mq)
159 159
160static int probe_maple_kbd(struct device *dev) 160static int probe_maple_kbd(struct device *dev)
161{ 161{
162 struct maple_device *mdev = to_maple_dev(dev); 162 struct maple_device *mdev;
163 struct maple_driver *mdrv = to_maple_driver(dev->driver); 163 struct maple_driver *mdrv;
164 int i, error; 164 int i, error;
165 struct dc_kbd *kbd; 165 struct dc_kbd *kbd;
166 struct input_dev *idev; 166 struct input_dev *idev;
167 167
168 if (!(mdev->function & MAPLE_FUNC_KEYBOARD)) 168 mdev = to_maple_dev(dev);
169 return -EINVAL; 169 mdrv = to_maple_driver(dev->driver);
170 170
171 kbd = kzalloc(sizeof(struct dc_kbd), GFP_KERNEL); 171 kbd = kzalloc(sizeof(struct dc_kbd), GFP_KERNEL);
172 idev = input_allocate_device(); 172 if (!kbd) {
173 if (!kbd || !idev) {
174 error = -ENOMEM; 173 error = -ENOMEM;
175 goto fail; 174 goto fail;
176 } 175 }
177 176
177 idev = input_allocate_device();
178 if (!idev) {
179 error = -ENOMEM;
180 goto fail_idev_alloc;
181 }
182
178 kbd->dev = idev; 183 kbd->dev = idev;
179 memcpy(kbd->keycode, dc_kbd_keycode, sizeof(kbd->keycode)); 184 memcpy(kbd->keycode, dc_kbd_keycode, sizeof(kbd->keycode));
180 185
@@ -195,7 +200,7 @@ static int probe_maple_kbd(struct device *dev)
195 200
196 error = input_register_device(idev); 201 error = input_register_device(idev);
197 if (error) 202 if (error)
198 goto fail; 203 goto fail_register;
199 204
200 /* Maple polling is locked to VBLANK - which may be just 50/s */ 205 /* Maple polling is locked to VBLANK - which may be just 50/s */
201 maple_getcond_callback(mdev, dc_kbd_callback, HZ/50, 206 maple_getcond_callback(mdev, dc_kbd_callback, HZ/50,
@@ -207,10 +212,12 @@ static int probe_maple_kbd(struct device *dev)
207 212
208 return error; 213 return error;
209 214
210fail: 215fail_register:
216 maple_set_drvdata(mdev, NULL);
211 input_free_device(idev); 217 input_free_device(idev);
218fail_idev_alloc:
212 kfree(kbd); 219 kfree(kbd);
213 maple_set_drvdata(mdev, NULL); 220fail:
214 return error; 221 return error;
215} 222}
216 223
diff --git a/drivers/input/keyboard/sh_keysc.c b/drivers/input/keyboard/sh_keysc.c
index 5c8a1bcf7ca7..e1480fb11de3 100644
--- a/drivers/input/keyboard/sh_keysc.c
+++ b/drivers/input/keyboard/sh_keysc.c
@@ -219,6 +219,8 @@ static int __devinit sh_keysc_probe(struct platform_device *pdev)
219 pdata->scan_timing, priv->iomem_base + KYCR1_OFFS); 219 pdata->scan_timing, priv->iomem_base + KYCR1_OFFS);
220 iowrite16(0, priv->iomem_base + KYOUTDR_OFFS); 220 iowrite16(0, priv->iomem_base + KYOUTDR_OFFS);
221 iowrite16(KYCR2_IRQ_LEVEL, priv->iomem_base + KYCR2_OFFS); 221 iowrite16(KYCR2_IRQ_LEVEL, priv->iomem_base + KYCR2_OFFS);
222
223 device_init_wakeup(&pdev->dev, 1);
222 return 0; 224 return 0;
223 err5: 225 err5:
224 free_irq(irq, pdev); 226 free_irq(irq, pdev);
@@ -253,17 +255,33 @@ static int __devexit sh_keysc_remove(struct platform_device *pdev)
253 return 0; 255 return 0;
254} 256}
255 257
258static int sh_keysc_suspend(struct device *dev)
259{
260 struct platform_device *pdev = to_platform_device(dev);
261 struct sh_keysc_priv *priv = platform_get_drvdata(pdev);
262 unsigned short value;
263
264 value = ioread16(priv->iomem_base + KYCR1_OFFS);
265
266 if (device_may_wakeup(dev))
267 value |= 0x80;
268 else
269 value &= ~0x80;
256 270
257#define sh_keysc_suspend NULL 271 iowrite16(value, priv->iomem_base + KYCR1_OFFS);
258#define sh_keysc_resume NULL 272 return 0;
273}
274
275static struct dev_pm_ops sh_keysc_dev_pm_ops = {
276 .suspend = sh_keysc_suspend,
277};
259 278
260struct platform_driver sh_keysc_device_driver = { 279struct platform_driver sh_keysc_device_driver = {
261 .probe = sh_keysc_probe, 280 .probe = sh_keysc_probe,
262 .remove = __devexit_p(sh_keysc_remove), 281 .remove = __devexit_p(sh_keysc_remove),
263 .suspend = sh_keysc_suspend,
264 .resume = sh_keysc_resume,
265 .driver = { 282 .driver = {
266 .name = "sh_keysc", 283 .name = "sh_keysc",
284 .pm = &sh_keysc_dev_pm_ops,
267 } 285 }
268}; 286};
269 287
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index 043d50fb6ef6..729f899a5cd5 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -551,5 +551,15 @@ config MTD_PLATRAM
551 551
552 This selection automatically selects the map_ram driver. 552 This selection automatically selects the map_ram driver.
553 553
554endmenu 554config MTD_VMU
555 tristate "Map driver for Dreamcast VMU"
556 depends on MAPLE
557 help
558 This driver enables access to the Dreamcast Visual Memory Unit (VMU).
559
560 Most Dreamcast users will want to say Y here.
555 561
562 To build this as a module select M here, the module will be called
563 vmu-flash.
564
565endmenu
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
index 6d9ba35caf11..26b28a7a90b5 100644
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -61,3 +61,4 @@ obj-$(CONFIG_MTD_PLATRAM) += plat-ram.o
61obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o 61obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o
62obj-$(CONFIG_MTD_INTEL_VR_NOR) += intel_vr_nor.o 62obj-$(CONFIG_MTD_INTEL_VR_NOR) += intel_vr_nor.o
63obj-$(CONFIG_MTD_BFIN_ASYNC) += bfin-async-flash.o 63obj-$(CONFIG_MTD_BFIN_ASYNC) += bfin-async-flash.o
64obj-$(CONFIG_MTD_VMU) += vmu-flash.o
diff --git a/drivers/mtd/maps/vmu-flash.c b/drivers/mtd/maps/vmu-flash.c
new file mode 100644
index 000000000000..1f73297e7776
--- /dev/null
+++ b/drivers/mtd/maps/vmu-flash.c
@@ -0,0 +1,832 @@
1/* vmu-flash.c
2 * Driver for SEGA Dreamcast Visual Memory Unit
3 *
4 * Copyright (c) Adrian McMenamin 2002 - 2009
5 * Copyright (c) Paul Mundt 2001
6 *
7 * Licensed under version 2 of the
8 * GNU General Public Licence
9 */
10#include <linux/init.h>
11#include <linux/sched.h>
12#include <linux/delay.h>
13#include <linux/maple.h>
14#include <linux/mtd/mtd.h>
15#include <linux/mtd/map.h>
16
17struct vmu_cache {
18 unsigned char *buffer; /* Cache */
19 unsigned int block; /* Which block was cached */
20 unsigned long jiffies_atc; /* When was it cached? */
21 int valid;
22};
23
24struct mdev_part {
25 struct maple_device *mdev;
26 int partition;
27};
28
29struct vmupart {
30 u16 user_blocks;
31 u16 root_block;
32 u16 numblocks;
33 char *name;
34 struct vmu_cache *pcache;
35};
36
37struct memcard {
38 u16 tempA;
39 u16 tempB;
40 u32 partitions;
41 u32 blocklen;
42 u32 writecnt;
43 u32 readcnt;
44 u32 removeable;
45 int partition;
46 int read;
47 unsigned char *blockread;
48 struct vmupart *parts;
49 struct mtd_info *mtd;
50};
51
52struct vmu_block {
53 unsigned int num; /* block number */
54 unsigned int ofs; /* block offset */
55};
56
57static struct vmu_block *ofs_to_block(unsigned long src_ofs,
58 struct mtd_info *mtd, int partition)
59{
60 struct vmu_block *vblock;
61 struct maple_device *mdev;
62 struct memcard *card;
63 struct mdev_part *mpart;
64 int num;
65
66 mpart = mtd->priv;
67 mdev = mpart->mdev;
68 card = maple_get_drvdata(mdev);
69
70 if (src_ofs >= card->parts[partition].numblocks * card->blocklen)
71 goto failed;
72
73 num = src_ofs / card->blocklen;
74 if (num > card->parts[partition].numblocks)
75 goto failed;
76
77 vblock = kmalloc(sizeof(struct vmu_block), GFP_KERNEL);
78 if (!vblock)
79 goto failed;
80
81 vblock->num = num;
82 vblock->ofs = src_ofs % card->blocklen;
83 return vblock;
84
85failed:
86 return NULL;
87}
88
89/* Maple bus callback function for reads */
90static void vmu_blockread(struct mapleq *mq)
91{
92 struct maple_device *mdev;
93 struct memcard *card;
94
95 mdev = mq->dev;
96 card = maple_get_drvdata(mdev);
97 /* copy the read in data */
98
99 if (unlikely(!card->blockread))
100 return;
101
102 memcpy(card->blockread, mq->recvbuf->buf + 12,
103 card->blocklen/card->readcnt);
104
105}
106
107/* Interface with maple bus to read blocks
108 * caching the results so that other parts
109 * of the driver can access block reads */
110static int maple_vmu_read_block(unsigned int num, unsigned char *buf,
111 struct mtd_info *mtd)
112{
113 struct memcard *card;
114 struct mdev_part *mpart;
115 struct maple_device *mdev;
116 int partition, error = 0, x, wait;
117 unsigned char *blockread = NULL;
118 struct vmu_cache *pcache;
119 __be32 sendbuf;
120
121 mpart = mtd->priv;
122 mdev = mpart->mdev;
123 partition = mpart->partition;
124 card = maple_get_drvdata(mdev);
125 pcache = card->parts[partition].pcache;
126 pcache->valid = 0;
127
128 /* prepare the cache for this block */
129 if (!pcache->buffer) {
130 pcache->buffer = kmalloc(card->blocklen, GFP_KERNEL);
131 if (!pcache->buffer) {
132 dev_err(&mdev->dev, "VMU at (%d, %d) - read fails due"
133 " to lack of memory\n", mdev->port,
134 mdev->unit);
135 error = -ENOMEM;
136 goto outB;
137 }
138 }
139
140 /*
141 * Reads may be phased - again the hardware spec
142 * supports this - though may not be any devices in
143 * the wild that implement it, but we will here
144 */
145 for (x = 0; x < card->readcnt; x++) {
146 sendbuf = cpu_to_be32(partition << 24 | x << 16 | num);
147
148 if (atomic_read(&mdev->busy) == 1) {
149 wait_event_interruptible_timeout(mdev->maple_wait,
150 atomic_read(&mdev->busy) == 0, HZ);
151 if (atomic_read(&mdev->busy) == 1) {
152 dev_notice(&mdev->dev, "VMU at (%d, %d)"
153 " is busy\n", mdev->port, mdev->unit);
154 error = -EAGAIN;
155 goto outB;
156 }
157 }
158
159 atomic_set(&mdev->busy, 1);
160 blockread = kmalloc(card->blocklen/card->readcnt, GFP_KERNEL);
161 if (!blockread) {
162 error = -ENOMEM;
163 atomic_set(&mdev->busy, 0);
164 goto outB;
165 }
166 card->blockread = blockread;
167
168 maple_getcond_callback(mdev, vmu_blockread, 0,
169 MAPLE_FUNC_MEMCARD);
170 error = maple_add_packet(mdev, MAPLE_FUNC_MEMCARD,
171 MAPLE_COMMAND_BREAD, 2, &sendbuf);
172 /* Very long timeouts seem to be needed when box is stressed */
173 wait = wait_event_interruptible_timeout(mdev->maple_wait,
174 (atomic_read(&mdev->busy) == 0 ||
175 atomic_read(&mdev->busy) == 2), HZ * 3);
176 /*
177 * MTD layer does not handle hotplugging well
178 * so have to return errors when VMU is unplugged
179 * in the middle of a read (busy == 2)
180 */
181 if (error || atomic_read(&mdev->busy) == 2) {
182 if (atomic_read(&mdev->busy) == 2)
183 error = -ENXIO;
184 atomic_set(&mdev->busy, 0);
185 card->blockread = NULL;
186 goto outA;
187 }
188 if (wait == 0 || wait == -ERESTARTSYS) {
189 card->blockread = NULL;
190 atomic_set(&mdev->busy, 0);
191 error = -EIO;
192 list_del_init(&(mdev->mq->list));
193 kfree(mdev->mq->sendbuf);
194 mdev->mq->sendbuf = NULL;
195 if (wait == -ERESTARTSYS) {
196 dev_warn(&mdev->dev, "VMU read on (%d, %d)"
197 " interrupted on block 0x%X\n",
198 mdev->port, mdev->unit, num);
199 } else
200 dev_notice(&mdev->dev, "VMU read on (%d, %d)"
201 " timed out on block 0x%X\n",
202 mdev->port, mdev->unit, num);
203 goto outA;
204 }
205
206 memcpy(buf + (card->blocklen/card->readcnt) * x, blockread,
207 card->blocklen/card->readcnt);
208
209 memcpy(pcache->buffer + (card->blocklen/card->readcnt) * x,
210 card->blockread, card->blocklen/card->readcnt);
211 card->blockread = NULL;
212 pcache->block = num;
213 pcache->jiffies_atc = jiffies;
214 pcache->valid = 1;
215 kfree(blockread);
216 }
217
218 return error;
219
220outA:
221 kfree(blockread);
222outB:
223 return error;
224}
225
226/* communicate with maple bus for phased writing */
227static int maple_vmu_write_block(unsigned int num, const unsigned char *buf,
228 struct mtd_info *mtd)
229{
230 struct memcard *card;
231 struct mdev_part *mpart;
232 struct maple_device *mdev;
233 int partition, error, locking, x, phaselen, wait;
234 __be32 *sendbuf;
235
236 mpart = mtd->priv;
237 mdev = mpart->mdev;
238 partition = mpart->partition;
239 card = maple_get_drvdata(mdev);
240
241 phaselen = card->blocklen/card->writecnt;
242
243 sendbuf = kmalloc(phaselen + 4, GFP_KERNEL);
244 if (!sendbuf) {
245 error = -ENOMEM;
246 goto fail_nosendbuf;
247 }
248 for (x = 0; x < card->writecnt; x++) {
249 sendbuf[0] = cpu_to_be32(partition << 24 | x << 16 | num);
250 memcpy(&sendbuf[1], buf + phaselen * x, phaselen);
251 /* wait until the device is not busy doing something else
252 * or 1 second - which ever is longer */
253 if (atomic_read(&mdev->busy) == 1) {
254 wait_event_interruptible_timeout(mdev->maple_wait,
255 atomic_read(&mdev->busy) == 0, HZ);
256 if (atomic_read(&mdev->busy) == 1) {
257 error = -EBUSY;
258 dev_notice(&mdev->dev, "VMU write at (%d, %d)"
259 "failed - device is busy\n",
260 mdev->port, mdev->unit);
261 goto fail_nolock;
262 }
263 }
264 atomic_set(&mdev->busy, 1);
265
266 locking = maple_add_packet(mdev, MAPLE_FUNC_MEMCARD,
267 MAPLE_COMMAND_BWRITE, phaselen / 4 + 2, sendbuf);
268 wait = wait_event_interruptible_timeout(mdev->maple_wait,
269 atomic_read(&mdev->busy) == 0, HZ/10);
270 if (locking) {
271 error = -EIO;
272 atomic_set(&mdev->busy, 0);
273 goto fail_nolock;
274 }
275 if (atomic_read(&mdev->busy) == 2) {
276 atomic_set(&mdev->busy, 0);
277 } else if (wait == 0 || wait == -ERESTARTSYS) {
278 error = -EIO;
279 dev_warn(&mdev->dev, "Write at (%d, %d) of block"
280 " 0x%X at phase %d failed: could not"
281 " communicate with VMU", mdev->port,
282 mdev->unit, num, x);
283 atomic_set(&mdev->busy, 0);
284 kfree(mdev->mq->sendbuf);
285 mdev->mq->sendbuf = NULL;
286 list_del_init(&(mdev->mq->list));
287 goto fail_nolock;
288 }
289 }
290 kfree(sendbuf);
291
292 return card->blocklen;
293
294fail_nolock:
295 kfree(sendbuf);
296fail_nosendbuf:
297 dev_err(&mdev->dev, "VMU (%d, %d): write failed\n", mdev->port,
298 mdev->unit);
299 return error;
300}
301
302/* mtd function to simulate reading byte by byte */
303static unsigned char vmu_flash_read_char(unsigned long ofs, int *retval,
304 struct mtd_info *mtd)
305{
306 struct vmu_block *vblock;
307 struct memcard *card;
308 struct mdev_part *mpart;
309 struct maple_device *mdev;
310 unsigned char *buf, ret;
311 int partition, error;
312
313 mpart = mtd->priv;
314 mdev = mpart->mdev;
315 partition = mpart->partition;
316 card = maple_get_drvdata(mdev);
317 *retval = 0;
318
319 buf = kmalloc(card->blocklen, GFP_KERNEL);
320 if (!buf) {
321 *retval = 1;
322 ret = -ENOMEM;
323 goto finish;
324 }
325
326 vblock = ofs_to_block(ofs, mtd, partition);
327 if (!vblock) {
328 *retval = 3;
329 ret = -ENOMEM;
330 goto out_buf;
331 }
332
333 error = maple_vmu_read_block(vblock->num, buf, mtd);
334 if (error) {
335 ret = error;
336 *retval = 2;
337 goto out_vblock;
338 }
339
340 ret = buf[vblock->ofs];
341
342out_vblock:
343 kfree(vblock);
344out_buf:
345 kfree(buf);
346finish:
347 return ret;
348}
349
350/* mtd higher order function to read flash */
351static int vmu_flash_read(struct mtd_info *mtd, loff_t from, size_t len,
352 size_t *retlen, u_char *buf)
353{
354 struct maple_device *mdev;
355 struct memcard *card;
356 struct mdev_part *mpart;
357 struct vmu_cache *pcache;
358 struct vmu_block *vblock;
359 int index = 0, retval, partition, leftover, numblocks;
360 unsigned char cx;
361
362 if (len < 1)
363 return -EIO;
364
365 mpart = mtd->priv;
366 mdev = mpart->mdev;
367 partition = mpart->partition;
368 card = maple_get_drvdata(mdev);
369
370 numblocks = card->parts[partition].numblocks;
371 if (from + len > numblocks * card->blocklen)
372 len = numblocks * card->blocklen - from;
373 if (len == 0)
374 return -EIO;
375 /* Have we cached this bit already? */
376 pcache = card->parts[partition].pcache;
377 do {
378 vblock = ofs_to_block(from + index, mtd, partition);
379 if (!vblock)
380 return -ENOMEM;
381 /* Have we cached this and is the cache valid and timely? */
382 if (pcache->valid &&
383 time_before(jiffies, pcache->jiffies_atc + HZ) &&
384 (pcache->block == vblock->num)) {
385 /* we have cached it, so do necessary copying */
386 leftover = card->blocklen - vblock->ofs;
387 if (vblock->ofs + len - index < card->blocklen) {
388 /* only a bit of this block to copy */
389 memcpy(buf + index,
390 pcache->buffer + vblock->ofs,
391 len - index);
392 index = len;
393 } else {
394 /* otherwise copy remainder of whole block */
395 memcpy(buf + index, pcache->buffer +
396 vblock->ofs, leftover);
397 index += leftover;
398 }
399 } else {
400 /*
401 * Not cached so read one byte -
402 * but cache the rest of the block
403 */
404 cx = vmu_flash_read_char(from + index, &retval, mtd);
405 if (retval) {
406 *retlen = index;
407 kfree(vblock);
408 return cx;
409 }
410 memset(buf + index, cx, 1);
411 index++;
412 }
413 kfree(vblock);
414 } while (len > index);
415 *retlen = index;
416
417 return 0;
418}
419
420static int vmu_flash_write(struct mtd_info *mtd, loff_t to, size_t len,
421 size_t *retlen, const u_char *buf)
422{
423 struct maple_device *mdev;
424 struct memcard *card;
425 struct mdev_part *mpart;
426 int index = 0, partition, error = 0, numblocks;
427 struct vmu_cache *pcache;
428 struct vmu_block *vblock;
429 unsigned char *buffer;
430
431 mpart = mtd->priv;
432 mdev = mpart->mdev;
433 partition = mpart->partition;
434 card = maple_get_drvdata(mdev);
435
436 /* simple sanity checks */
437 if (len < 1) {
438 error = -EIO;
439 goto failed;
440 }
441 numblocks = card->parts[partition].numblocks;
442 if (to + len > numblocks * card->blocklen)
443 len = numblocks * card->blocklen - to;
444 if (len == 0) {
445 error = -EIO;
446 goto failed;
447 }
448
449 vblock = ofs_to_block(to, mtd, partition);
450 if (!vblock) {
451 error = -ENOMEM;
452 goto failed;
453 }
454
455 buffer = kmalloc(card->blocklen, GFP_KERNEL);
456 if (!buffer) {
457 error = -ENOMEM;
458 goto fail_buffer;
459 }
460
461 do {
462 /* Read in the block we are to write to */
463 error = maple_vmu_read_block(vblock->num, buffer, mtd);
464 if (error)
465 goto fail_io;
466
467 do {
468 buffer[vblock->ofs] = buf[index];
469 vblock->ofs++;
470 index++;
471 if (index >= len)
472 break;
473 } while (vblock->ofs < card->blocklen);
474
475 /* write out new buffer */
476 error = maple_vmu_write_block(vblock->num, buffer, mtd);
477 /* invalidate the cache */
478 pcache = card->parts[partition].pcache;
479 pcache->valid = 0;
480
481 if (error != card->blocklen)
482 goto fail_io;
483
484 vblock->num++;
485 vblock->ofs = 0;
486 } while (len > index);
487
488 kfree(buffer);
489 *retlen = index;
490 kfree(vblock);
491 return 0;
492
493fail_io:
494 kfree(buffer);
495fail_buffer:
496 kfree(vblock);
497failed:
498 dev_err(&mdev->dev, "VMU write failing with error %d\n", error);
499 return error;
500}
501
502static void vmu_flash_sync(struct mtd_info *mtd)
503{
504 /* Do nothing here */
505}
506
507/* Maple bus callback function to recursively query hardware details */
508static void vmu_queryblocks(struct mapleq *mq)
509{
510 struct maple_device *mdev;
511 unsigned short *res;
512 struct memcard *card;
513 __be32 partnum;
514 struct vmu_cache *pcache;
515 struct mdev_part *mpart;
516 struct mtd_info *mtd_cur;
517 struct vmupart *part_cur;
518 int error;
519
520 mdev = mq->dev;
521 card = maple_get_drvdata(mdev);
522 res = (unsigned short *) (mq->recvbuf->buf);
523 card->tempA = res[12];
524 card->tempB = res[6];
525
526 dev_info(&mdev->dev, "VMU device at partition %d has %d user "
527 "blocks with a root block at %d\n", card->partition,
528 card->tempA, card->tempB);
529
530 part_cur = &card->parts[card->partition];
531 part_cur->user_blocks = card->tempA;
532 part_cur->root_block = card->tempB;
533 part_cur->numblocks = card->tempB + 1;
534 part_cur->name = kmalloc(12, GFP_KERNEL);
535 if (!part_cur->name)
536 goto fail_name;
537
538 sprintf(part_cur->name, "vmu%d.%d.%d",
539 mdev->port, mdev->unit, card->partition);
540 mtd_cur = &card->mtd[card->partition];
541 mtd_cur->name = part_cur->name;
542 mtd_cur->type = 8;
543 mtd_cur->flags = MTD_WRITEABLE|MTD_NO_ERASE;
544 mtd_cur->size = part_cur->numblocks * card->blocklen;
545 mtd_cur->erasesize = card->blocklen;
546 mtd_cur->write = vmu_flash_write;
547 mtd_cur->read = vmu_flash_read;
548 mtd_cur->sync = vmu_flash_sync;
549 mtd_cur->writesize = card->blocklen;
550
551 mpart = kmalloc(sizeof(struct mdev_part), GFP_KERNEL);
552 if (!mpart)
553 goto fail_mpart;
554
555 mpart->mdev = mdev;
556 mpart->partition = card->partition;
557 mtd_cur->priv = mpart;
558 mtd_cur->owner = THIS_MODULE;
559
560 pcache = kzalloc(sizeof(struct vmu_cache), GFP_KERNEL);
561 if (!pcache)
562 goto fail_cache_create;
563 part_cur->pcache = pcache;
564
565 error = add_mtd_device(mtd_cur);
566 if (error)
567 goto fail_mtd_register;
568
569 maple_getcond_callback(mdev, NULL, 0,
570 MAPLE_FUNC_MEMCARD);
571
572 /*
573 * Set up a recursive call to the (probably theoretical)
574 * second or more partition
575 */
576 if (++card->partition < card->partitions) {
577 partnum = cpu_to_be32(card->partition << 24);
578 maple_getcond_callback(mdev, vmu_queryblocks, 0,
579 MAPLE_FUNC_MEMCARD);
580 maple_add_packet(mdev, MAPLE_FUNC_MEMCARD,
581 MAPLE_COMMAND_GETMINFO, 2, &partnum);
582 }
583 return;
584
585fail_mtd_register:
586 dev_err(&mdev->dev, "Could not register maple device at (%d, %d)"
587 "error is 0x%X\n", mdev->port, mdev->unit, error);
588 for (error = 0; error <= card->partition; error++) {
589 kfree(((card->parts)[error]).pcache);
590 ((card->parts)[error]).pcache = NULL;
591 }
592fail_cache_create:
593fail_mpart:
594 for (error = 0; error <= card->partition; error++) {
595 kfree(((card->mtd)[error]).priv);
596 ((card->mtd)[error]).priv = NULL;
597 }
598 maple_getcond_callback(mdev, NULL, 0,
599 MAPLE_FUNC_MEMCARD);
600 kfree(part_cur->name);
601fail_name:
602 return;
603}
604
605/* Handles very basic info about the flash, queries for details */
606static int __devinit vmu_connect(struct maple_device *mdev)
607{
608 unsigned long test_flash_data, basic_flash_data;
609 int c, error;
610 struct memcard *card;
611 u32 partnum = 0;
612
613 test_flash_data = be32_to_cpu(mdev->devinfo.function);
614 /* Need to count how many bits are set - to find out which
615 * function_data element has details of the memory card:
616 * using Brian Kernighan's/Peter Wegner's method */
617 for (c = 0; test_flash_data; c++)
618 test_flash_data &= test_flash_data - 1;
619
620 basic_flash_data = be32_to_cpu(mdev->devinfo.function_data[c - 1]);
621
622 card = kmalloc(sizeof(struct memcard), GFP_KERNEL);
623 if (!card) {
624 error = ENOMEM;
625 goto fail_nomem;
626 }
627
628 card->partitions = (basic_flash_data >> 24 & 0xFF) + 1;
629 card->blocklen = ((basic_flash_data >> 16 & 0xFF) + 1) << 5;
630 card->writecnt = basic_flash_data >> 12 & 0xF;
631 card->readcnt = basic_flash_data >> 8 & 0xF;
632 card->removeable = basic_flash_data >> 7 & 1;
633
634 card->partition = 0;
635
636 /*
637 * Not sure there are actually any multi-partition devices in the
638 * real world, but the hardware supports them, so, so will we
639 */
640 card->parts = kmalloc(sizeof(struct vmupart) * card->partitions,
641 GFP_KERNEL);
642 if (!card->parts) {
643 error = -ENOMEM;
644 goto fail_partitions;
645 }
646
647 card->mtd = kmalloc(sizeof(struct mtd_info) * card->partitions,
648 GFP_KERNEL);
649 if (!card->mtd) {
650 error = -ENOMEM;
651 goto fail_mtd_info;
652 }
653
654 maple_set_drvdata(mdev, card);
655
656 /*
657 * We want to trap meminfo not get cond
658 * so set interval to zero, but rely on maple bus
659 * driver to pass back the results of the meminfo
660 */
661 maple_getcond_callback(mdev, vmu_queryblocks, 0,
662 MAPLE_FUNC_MEMCARD);
663
664 /* Make sure we are clear to go */
665 if (atomic_read(&mdev->busy) == 1) {
666 wait_event_interruptible_timeout(mdev->maple_wait,
667 atomic_read(&mdev->busy) == 0, HZ);
668 if (atomic_read(&mdev->busy) == 1) {
669 dev_notice(&mdev->dev, "VMU at (%d, %d) is busy\n",
670 mdev->port, mdev->unit);
671 error = -EAGAIN;
672 goto fail_device_busy;
673 }
674 }
675
676 atomic_set(&mdev->busy, 1);
677
678 /*
679 * Set up the minfo call: vmu_queryblocks will handle
680 * the information passed back
681 */
682 error = maple_add_packet(mdev, MAPLE_FUNC_MEMCARD,
683 MAPLE_COMMAND_GETMINFO, 2, &partnum);
684 if (error) {
685 dev_err(&mdev->dev, "Could not lock VMU at (%d, %d)"
686 " error is 0x%X\n", mdev->port, mdev->unit, error);
687 goto fail_mtd_info;
688 }
689 return 0;
690
691fail_device_busy:
692 kfree(card->mtd);
693fail_mtd_info:
694 kfree(card->parts);
695fail_partitions:
696 kfree(card);
697fail_nomem:
698 return error;
699}
700
701static void __devexit vmu_disconnect(struct maple_device *mdev)
702{
703 struct memcard *card;
704 struct mdev_part *mpart;
705 int x;
706
707 mdev->callback = NULL;
708 card = maple_get_drvdata(mdev);
709 for (x = 0; x < card->partitions; x++) {
710 mpart = ((card->mtd)[x]).priv;
711 mpart->mdev = NULL;
712 del_mtd_device(&((card->mtd)[x]));
713 kfree(((card->parts)[x]).name);
714 }
715 kfree(card->parts);
716 kfree(card->mtd);
717 kfree(card);
718}
719
720/* Callback to handle eccentricities of both mtd subsystem
721 * and general flakyness of Dreamcast VMUs
722 */
723static int vmu_can_unload(struct maple_device *mdev)
724{
725 struct memcard *card;
726 int x;
727 struct mtd_info *mtd;
728
729 card = maple_get_drvdata(mdev);
730 for (x = 0; x < card->partitions; x++) {
731 mtd = &((card->mtd)[x]);
732 if (mtd->usecount > 0)
733 return 0;
734 }
735 return 1;
736}
737
738#define ERRSTR "VMU at (%d, %d) file error -"
739
740static void vmu_file_error(struct maple_device *mdev, void *recvbuf)
741{
742 enum maple_file_errors error = ((int *)recvbuf)[1];
743
744 switch (error) {
745
746 case MAPLE_FILEERR_INVALID_PARTITION:
747 dev_notice(&mdev->dev, ERRSTR " invalid partition number\n",
748 mdev->port, mdev->unit);
749 break;
750
751 case MAPLE_FILEERR_PHASE_ERROR:
752 dev_notice(&mdev->dev, ERRSTR " phase error\n",
753 mdev->port, mdev->unit);
754 break;
755
756 case MAPLE_FILEERR_INVALID_BLOCK:
757 dev_notice(&mdev->dev, ERRSTR " invalid block number\n",
758 mdev->port, mdev->unit);
759 break;
760
761 case MAPLE_FILEERR_WRITE_ERROR:
762 dev_notice(&mdev->dev, ERRSTR " write error\n",
763 mdev->port, mdev->unit);
764 break;
765
766 case MAPLE_FILEERR_INVALID_WRITE_LENGTH:
767 dev_notice(&mdev->dev, ERRSTR " invalid write length\n",
768 mdev->port, mdev->unit);
769 break;
770
771 case MAPLE_FILEERR_BAD_CRC:
772 dev_notice(&mdev->dev, ERRSTR " bad CRC\n",
773 mdev->port, mdev->unit);
774 break;
775
776 default:
777 dev_notice(&mdev->dev, ERRSTR " 0x%X\n",
778 mdev->port, mdev->unit, error);
779 }
780}
781
782
783static int __devinit probe_maple_vmu(struct device *dev)
784{
785 int error;
786 struct maple_device *mdev = to_maple_dev(dev);
787 struct maple_driver *mdrv = to_maple_driver(dev->driver);
788
789 mdev->can_unload = vmu_can_unload;
790 mdev->fileerr_handler = vmu_file_error;
791 mdev->driver = mdrv;
792
793 error = vmu_connect(mdev);
794 if (error)
795 return error;
796
797 return 0;
798}
799
800static int __devexit remove_maple_vmu(struct device *dev)
801{
802 struct maple_device *mdev = to_maple_dev(dev);
803
804 vmu_disconnect(mdev);
805 return 0;
806}
807
808static struct maple_driver vmu_flash_driver = {
809 .function = MAPLE_FUNC_MEMCARD,
810 .drv = {
811 .name = "Dreamcast_visual_memory",
812 .probe = probe_maple_vmu,
813 .remove = __devexit_p(remove_maple_vmu),
814 },
815};
816
817static int __init vmu_flash_map_init(void)
818{
819 return maple_driver_register(&vmu_flash_driver);
820}
821
822static void __exit vmu_flash_map_exit(void)
823{
824 maple_driver_unregister(&vmu_flash_driver);
825}
826
827module_init(vmu_flash_map_init);
828module_exit(vmu_flash_map_exit);
829
830MODULE_LICENSE("GPL");
831MODULE_AUTHOR("Adrian McMenamin");
832MODULE_DESCRIPTION("Flash mapping for Sega Dreamcast visual memory");
diff --git a/drivers/rtc/rtc-sh.c b/drivers/rtc/rtc-sh.c
index 1c3fc6b428e9..4898f7fe8518 100644
--- a/drivers/rtc/rtc-sh.c
+++ b/drivers/rtc/rtc-sh.c
@@ -28,7 +28,7 @@
28#include <asm/rtc.h> 28#include <asm/rtc.h>
29 29
30#define DRV_NAME "sh-rtc" 30#define DRV_NAME "sh-rtc"
31#define DRV_VERSION "0.2.0" 31#define DRV_VERSION "0.2.1"
32 32
33#define RTC_REG(r) ((r) * rtc_reg_size) 33#define RTC_REG(r) ((r) * rtc_reg_size)
34 34
@@ -99,56 +99,51 @@ struct sh_rtc {
99 unsigned short periodic_freq; 99 unsigned short periodic_freq;
100}; 100};
101 101
102static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id) 102static int __sh_rtc_interrupt(struct sh_rtc *rtc)
103{ 103{
104 struct sh_rtc *rtc = dev_id; 104 unsigned int tmp, pending;
105 unsigned int tmp;
106
107 spin_lock(&rtc->lock);
108 105
109 tmp = readb(rtc->regbase + RCR1); 106 tmp = readb(rtc->regbase + RCR1);
107 pending = tmp & RCR1_CF;
110 tmp &= ~RCR1_CF; 108 tmp &= ~RCR1_CF;
111 writeb(tmp, rtc->regbase + RCR1); 109 writeb(tmp, rtc->regbase + RCR1);
112 110
113 /* Users have requested One x Second IRQ */ 111 /* Users have requested One x Second IRQ */
114 if (rtc->periodic_freq & PF_OXS) 112 if (pending && rtc->periodic_freq & PF_OXS)
115 rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF); 113 rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF);
116 114
117 spin_unlock(&rtc->lock); 115 return pending;
118
119 return IRQ_HANDLED;
120} 116}
121 117
122static irqreturn_t sh_rtc_alarm(int irq, void *dev_id) 118static int __sh_rtc_alarm(struct sh_rtc *rtc)
123{ 119{
124 struct sh_rtc *rtc = dev_id; 120 unsigned int tmp, pending;
125 unsigned int tmp;
126
127 spin_lock(&rtc->lock);
128 121
129 tmp = readb(rtc->regbase + RCR1); 122 tmp = readb(rtc->regbase + RCR1);
123 pending = tmp & RCR1_AF;
130 tmp &= ~(RCR1_AF | RCR1_AIE); 124 tmp &= ~(RCR1_AF | RCR1_AIE);
131 writeb(tmp, rtc->regbase + RCR1); 125 writeb(tmp, rtc->regbase + RCR1);
132
133 rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
134 126
135 spin_unlock(&rtc->lock); 127 if (pending)
128 rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
136 129
137 return IRQ_HANDLED; 130 return pending;
138} 131}
139 132
140static irqreturn_t sh_rtc_periodic(int irq, void *dev_id) 133static int __sh_rtc_periodic(struct sh_rtc *rtc)
141{ 134{
142 struct sh_rtc *rtc = dev_id;
143 struct rtc_device *rtc_dev = rtc->rtc_dev; 135 struct rtc_device *rtc_dev = rtc->rtc_dev;
144 unsigned int tmp; 136 struct rtc_task *irq_task;
145 137 unsigned int tmp, pending;
146 spin_lock(&rtc->lock);
147 138
148 tmp = readb(rtc->regbase + RCR2); 139 tmp = readb(rtc->regbase + RCR2);
140 pending = tmp & RCR2_PEF;
149 tmp &= ~RCR2_PEF; 141 tmp &= ~RCR2_PEF;
150 writeb(tmp, rtc->regbase + RCR2); 142 writeb(tmp, rtc->regbase + RCR2);
151 143
144 if (!pending)
145 return 0;
146
152 /* Half period enabled than one skipped and the next notified */ 147 /* Half period enabled than one skipped and the next notified */
153 if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT)) 148 if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT))
154 rtc->periodic_freq &= ~PF_COUNT; 149 rtc->periodic_freq &= ~PF_COUNT;
@@ -157,16 +152,65 @@ static irqreturn_t sh_rtc_periodic(int irq, void *dev_id)
157 rtc->periodic_freq |= PF_COUNT; 152 rtc->periodic_freq |= PF_COUNT;
158 if (rtc->periodic_freq & PF_KOU) { 153 if (rtc->periodic_freq & PF_KOU) {
159 spin_lock(&rtc_dev->irq_task_lock); 154 spin_lock(&rtc_dev->irq_task_lock);
160 if (rtc_dev->irq_task) 155 irq_task = rtc_dev->irq_task;
161 rtc_dev->irq_task->func(rtc_dev->irq_task->private_data); 156 if (irq_task)
157 irq_task->func(irq_task->private_data);
162 spin_unlock(&rtc_dev->irq_task_lock); 158 spin_unlock(&rtc_dev->irq_task_lock);
163 } else 159 } else
164 rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF); 160 rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF);
165 } 161 }
166 162
163 return pending;
164}
165
166static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id)
167{
168 struct sh_rtc *rtc = dev_id;
169 int ret;
170
171 spin_lock(&rtc->lock);
172 ret = __sh_rtc_interrupt(rtc);
173 spin_unlock(&rtc->lock);
174
175 return IRQ_RETVAL(ret);
176}
177
178static irqreturn_t sh_rtc_alarm(int irq, void *dev_id)
179{
180 struct sh_rtc *rtc = dev_id;
181 int ret;
182
183 spin_lock(&rtc->lock);
184 ret = __sh_rtc_alarm(rtc);
185 spin_unlock(&rtc->lock);
186
187 return IRQ_RETVAL(ret);
188}
189
190static irqreturn_t sh_rtc_periodic(int irq, void *dev_id)
191{
192 struct sh_rtc *rtc = dev_id;
193 int ret;
194
195 spin_lock(&rtc->lock);
196 ret = __sh_rtc_periodic(rtc);
167 spin_unlock(&rtc->lock); 197 spin_unlock(&rtc->lock);
168 198
169 return IRQ_HANDLED; 199 return IRQ_RETVAL(ret);
200}
201
202static irqreturn_t sh_rtc_shared(int irq, void *dev_id)
203{
204 struct sh_rtc *rtc = dev_id;
205 int ret;
206
207 spin_lock(&rtc->lock);
208 ret = __sh_rtc_interrupt(rtc);
209 ret |= __sh_rtc_alarm(rtc);
210 ret |= __sh_rtc_periodic(rtc);
211 spin_unlock(&rtc->lock);
212
213 return IRQ_RETVAL(ret);
170} 214}
171 215
172static inline void sh_rtc_setpie(struct device *dev, unsigned int enable) 216static inline void sh_rtc_setpie(struct device *dev, unsigned int enable)
@@ -275,6 +319,25 @@ static int sh_rtc_proc(struct device *dev, struct seq_file *seq)
275 return 0; 319 return 0;
276} 320}
277 321
322static inline void sh_rtc_setcie(struct device *dev, unsigned int enable)
323{
324 struct sh_rtc *rtc = dev_get_drvdata(dev);
325 unsigned int tmp;
326
327 spin_lock_irq(&rtc->lock);
328
329 tmp = readb(rtc->regbase + RCR1);
330
331 if (!enable)
332 tmp &= ~RCR1_CIE;
333 else
334 tmp |= RCR1_CIE;
335
336 writeb(tmp, rtc->regbase + RCR1);
337
338 spin_unlock_irq(&rtc->lock);
339}
340
278static int sh_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) 341static int sh_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
279{ 342{
280 struct sh_rtc *rtc = dev_get_drvdata(dev); 343 struct sh_rtc *rtc = dev_get_drvdata(dev);
@@ -291,9 +354,11 @@ static int sh_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
291 break; 354 break;
292 case RTC_UIE_OFF: 355 case RTC_UIE_OFF:
293 rtc->periodic_freq &= ~PF_OXS; 356 rtc->periodic_freq &= ~PF_OXS;
357 sh_rtc_setcie(dev, 0);
294 break; 358 break;
295 case RTC_UIE_ON: 359 case RTC_UIE_ON:
296 rtc->periodic_freq |= PF_OXS; 360 rtc->periodic_freq |= PF_OXS;
361 sh_rtc_setcie(dev, 1);
297 break; 362 break;
298 case RTC_IRQP_READ: 363 case RTC_IRQP_READ:
299 ret = put_user(rtc->rtc_dev->irq_freq, 364 ret = put_user(rtc->rtc_dev->irq_freq,
@@ -356,18 +421,17 @@ static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
356 tm->tm_sec--; 421 tm->tm_sec--;
357#endif 422#endif
358 423
424 /* only keep the carry interrupt enabled if UIE is on */
425 if (!(rtc->periodic_freq & PF_OXS))
426 sh_rtc_setcie(dev, 0);
427
359 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 428 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
360 "mday=%d, mon=%d, year=%d, wday=%d\n", 429 "mday=%d, mon=%d, year=%d, wday=%d\n",
361 __func__, 430 __func__,
362 tm->tm_sec, tm->tm_min, tm->tm_hour, 431 tm->tm_sec, tm->tm_min, tm->tm_hour,
363 tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday); 432 tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday);
364 433
365 if (rtc_valid_tm(tm) < 0) { 434 return rtc_valid_tm(tm);
366 dev_err(dev, "invalid date\n");
367 rtc_time_to_tm(0, tm);
368 }
369
370 return 0;
371} 435}
372 436
373static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm) 437static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm)
@@ -572,7 +636,7 @@ static int __devinit sh_rtc_probe(struct platform_device *pdev)
572{ 636{
573 struct sh_rtc *rtc; 637 struct sh_rtc *rtc;
574 struct resource *res; 638 struct resource *res;
575 unsigned int tmp; 639 struct rtc_time r;
576 int ret; 640 int ret;
577 641
578 rtc = kzalloc(sizeof(struct sh_rtc), GFP_KERNEL); 642 rtc = kzalloc(sizeof(struct sh_rtc), GFP_KERNEL);
@@ -585,26 +649,12 @@ static int __devinit sh_rtc_probe(struct platform_device *pdev)
585 ret = platform_get_irq(pdev, 0); 649 ret = platform_get_irq(pdev, 0);
586 if (unlikely(ret <= 0)) { 650 if (unlikely(ret <= 0)) {
587 ret = -ENOENT; 651 ret = -ENOENT;
588 dev_err(&pdev->dev, "No IRQ for period\n"); 652 dev_err(&pdev->dev, "No IRQ resource\n");
589 goto err_badres; 653 goto err_badres;
590 } 654 }
591 rtc->periodic_irq = ret; 655 rtc->periodic_irq = ret;
592 656 rtc->carry_irq = platform_get_irq(pdev, 1);
593 ret = platform_get_irq(pdev, 1); 657 rtc->alarm_irq = platform_get_irq(pdev, 2);
594 if (unlikely(ret <= 0)) {
595 ret = -ENOENT;
596 dev_err(&pdev->dev, "No IRQ for carry\n");
597 goto err_badres;
598 }
599 rtc->carry_irq = ret;
600
601 ret = platform_get_irq(pdev, 2);
602 if (unlikely(ret <= 0)) {
603 ret = -ENOENT;
604 dev_err(&pdev->dev, "No IRQ for alarm\n");
605 goto err_badres;
606 }
607 rtc->alarm_irq = ret;
608 658
609 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 659 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
610 if (unlikely(res == NULL)) { 660 if (unlikely(res == NULL)) {
@@ -646,47 +696,66 @@ static int __devinit sh_rtc_probe(struct platform_device *pdev)
646 } 696 }
647 697
648 rtc->rtc_dev->max_user_freq = 256; 698 rtc->rtc_dev->max_user_freq = 256;
649 rtc->rtc_dev->irq_freq = 1;
650 rtc->periodic_freq = 0x60;
651 699
652 platform_set_drvdata(pdev, rtc); 700 platform_set_drvdata(pdev, rtc);
653 701
654 /* register periodic/carry/alarm irqs */ 702 if (rtc->carry_irq <= 0) {
655 ret = request_irq(rtc->periodic_irq, sh_rtc_periodic, IRQF_DISABLED, 703 /* register shared periodic/carry/alarm irq */
656 "sh-rtc period", rtc); 704 ret = request_irq(rtc->periodic_irq, sh_rtc_shared,
657 if (unlikely(ret)) { 705 IRQF_DISABLED, "sh-rtc", rtc);
658 dev_err(&pdev->dev, 706 if (unlikely(ret)) {
659 "request period IRQ failed with %d, IRQ %d\n", ret, 707 dev_err(&pdev->dev,
660 rtc->periodic_irq); 708 "request IRQ failed with %d, IRQ %d\n", ret,
661 goto err_unmap; 709 rtc->periodic_irq);
662 } 710 goto err_unmap;
711 }
712 } else {
713 /* register periodic/carry/alarm irqs */
714 ret = request_irq(rtc->periodic_irq, sh_rtc_periodic,
715 IRQF_DISABLED, "sh-rtc period", rtc);
716 if (unlikely(ret)) {
717 dev_err(&pdev->dev,
718 "request period IRQ failed with %d, IRQ %d\n",
719 ret, rtc->periodic_irq);
720 goto err_unmap;
721 }
663 722
664 ret = request_irq(rtc->carry_irq, sh_rtc_interrupt, IRQF_DISABLED, 723 ret = request_irq(rtc->carry_irq, sh_rtc_interrupt,
665 "sh-rtc carry", rtc); 724 IRQF_DISABLED, "sh-rtc carry", rtc);
666 if (unlikely(ret)) { 725 if (unlikely(ret)) {
667 dev_err(&pdev->dev, 726 dev_err(&pdev->dev,
668 "request carry IRQ failed with %d, IRQ %d\n", ret, 727 "request carry IRQ failed with %d, IRQ %d\n",
669 rtc->carry_irq); 728 ret, rtc->carry_irq);
670 free_irq(rtc->periodic_irq, rtc); 729 free_irq(rtc->periodic_irq, rtc);
671 goto err_unmap; 730 goto err_unmap;
672 } 731 }
673 732
674 ret = request_irq(rtc->alarm_irq, sh_rtc_alarm, IRQF_DISABLED, 733 ret = request_irq(rtc->alarm_irq, sh_rtc_alarm,
675 "sh-rtc alarm", rtc); 734 IRQF_DISABLED, "sh-rtc alarm", rtc);
676 if (unlikely(ret)) { 735 if (unlikely(ret)) {
677 dev_err(&pdev->dev, 736 dev_err(&pdev->dev,
678 "request alarm IRQ failed with %d, IRQ %d\n", ret, 737 "request alarm IRQ failed with %d, IRQ %d\n",
679 rtc->alarm_irq); 738 ret, rtc->alarm_irq);
680 free_irq(rtc->carry_irq, rtc); 739 free_irq(rtc->carry_irq, rtc);
681 free_irq(rtc->periodic_irq, rtc); 740 free_irq(rtc->periodic_irq, rtc);
682 goto err_unmap; 741 goto err_unmap;
742 }
683 } 743 }
684 744
685 tmp = readb(rtc->regbase + RCR1); 745 /* everything disabled by default */
686 tmp &= ~RCR1_CF; 746 rtc->periodic_freq = 0;
687 tmp |= RCR1_CIE; 747 rtc->rtc_dev->irq_freq = 0;
688 writeb(tmp, rtc->regbase + RCR1); 748 sh_rtc_setpie(&pdev->dev, 0);
749 sh_rtc_setaie(&pdev->dev, 0);
750 sh_rtc_setcie(&pdev->dev, 0);
751
752 /* reset rtc to epoch 0 if time is invalid */
753 if (rtc_read_time(rtc->rtc_dev, &r) < 0) {
754 rtc_time_to_tm(0, &r);
755 rtc_set_time(rtc->rtc_dev, &r);
756 }
689 757
758 device_init_wakeup(&pdev->dev, 1);
690 return 0; 759 return 0;
691 760
692err_unmap: 761err_unmap:
@@ -708,10 +777,13 @@ static int __devexit sh_rtc_remove(struct platform_device *pdev)
708 777
709 sh_rtc_setpie(&pdev->dev, 0); 778 sh_rtc_setpie(&pdev->dev, 0);
710 sh_rtc_setaie(&pdev->dev, 0); 779 sh_rtc_setaie(&pdev->dev, 0);
780 sh_rtc_setcie(&pdev->dev, 0);
711 781
712 free_irq(rtc->carry_irq, rtc);
713 free_irq(rtc->periodic_irq, rtc); 782 free_irq(rtc->periodic_irq, rtc);
714 free_irq(rtc->alarm_irq, rtc); 783 if (rtc->carry_irq > 0) {
784 free_irq(rtc->carry_irq, rtc);
785 free_irq(rtc->alarm_irq, rtc);
786 }
715 787
716 release_resource(rtc->res); 788 release_resource(rtc->res);
717 789
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index 557b54ab2f25..dbf5357a77b3 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -139,7 +139,7 @@ static void sci_poll_put_char(struct uart_port *port, unsigned char c)
139 } while (!(status & SCxSR_TDxE(port))); 139 } while (!(status & SCxSR_TDxE(port)));
140 140
141 sci_in(port, SCxSR); /* Dummy read */ 141 sci_in(port, SCxSR); /* Dummy read */
142 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); 142 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
143 sci_out(port, SCxTDR, c); 143 sci_out(port, SCxTDR, c);
144} 144}
145#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ 145#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
@@ -263,6 +263,7 @@ static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
263#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 263#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
264 defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 264 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
265 defined(CONFIG_CPU_SUBTYPE_SH7785) || \ 265 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
266 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
266 defined(CONFIG_CPU_SUBTYPE_SHX3) 267 defined(CONFIG_CPU_SUBTYPE_SHX3)
267static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) 268static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
268{ 269{
@@ -284,7 +285,8 @@ static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
284 285
285#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ 286#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
286 defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 287 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
287 defined(CONFIG_CPU_SUBTYPE_SH7785) 288 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
289 defined(CONFIG_CPU_SUBTYPE_SH7786)
288static inline int scif_txroom(struct uart_port *port) 290static inline int scif_txroom(struct uart_port *port)
289{ 291{
290 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff); 292 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
@@ -1095,6 +1097,7 @@ static void serial_console_write(struct console *co, const char *s,
1095 unsigned count) 1097 unsigned count)
1096{ 1098{
1097 struct uart_port *port = &serial_console_port->port; 1099 struct uart_port *port = &serial_console_port->port;
1100 unsigned short bits;
1098 int i; 1101 int i;
1099 1102
1100 for (i = 0; i < count; i++) { 1103 for (i = 0; i < count; i++) {
@@ -1103,6 +1106,11 @@ static void serial_console_write(struct console *co, const char *s,
1103 1106
1104 sci_poll_put_char(port, *s++); 1107 sci_poll_put_char(port, *s++);
1105 } 1108 }
1109
1110 /* wait until fifo is empty and last bit has been transmitted */
1111 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1112 while ((sci_in(port, SCxSR) & bits) != bits)
1113 cpu_relax();
1106} 1114}
1107 1115
1108static int __init serial_console_setup(struct console *co, char *options) 1116static int __init serial_console_setup(struct console *co, char *options)
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index 022e89ffec1d..d0aa82d7fce0 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -1,6 +1,6 @@
1#include <linux/serial_core.h> 1#include <linux/serial_core.h>
2#include <asm/io.h> 2#include <asm/io.h>
3#include <asm/gpio.h> 3#include <linux/gpio.h>
4 4
5#if defined(CONFIG_H83007) || defined(CONFIG_H83068) 5#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
6#include <asm/regs306x.h> 6#include <asm/regs306x.h>
@@ -126,7 +126,8 @@
126# define SCSPTR1 0xffe10024 /* 16 bit SCIF */ 126# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
127# define SCIF_ORER 0x0001 /* Overrun error bit */ 127# define SCIF_ORER 0x0001 /* Overrun error bit */
128# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 128# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
129#elif defined(CONFIG_CPU_SUBTYPE_SH7785) 129#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
130 defined(CONFIG_CPU_SUBTYPE_SH7786)
130# define SCSPTR0 0xffea0024 /* 16 bit SCIF */ 131# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
131# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ 132# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
132# define SCSPTR2 0xffec0024 /* 16 bit SCIF */ 133# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
@@ -182,6 +183,7 @@
182 defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 183 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
183 defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 184 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
184 defined(CONFIG_CPU_SUBTYPE_SH7785) || \ 185 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
186 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
185 defined(CONFIG_CPU_SUBTYPE_SHX3) 187 defined(CONFIG_CPU_SUBTYPE_SHX3)
186#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ 188#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
187#else 189#else
@@ -413,7 +415,8 @@ SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
413SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) 415SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
414#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ 416#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
415 defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 417 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
416 defined(CONFIG_CPU_SUBTYPE_SH7785) 418 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
419 defined(CONFIG_CPU_SUBTYPE_SH7786)
417SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 420SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
418SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 421SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
419SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 422SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
@@ -644,7 +647,8 @@ static inline int sci_rxd_in(struct uart_port *port)
644 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 647 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
645 return 1; 648 return 1;
646} 649}
647#elif defined(CONFIG_CPU_SUBTYPE_SH7785) 650#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
651 defined(CONFIG_CPU_SUBTYPE_SH7786)
648static inline int sci_rxd_in(struct uart_port *port) 652static inline int sci_rxd_in(struct uart_port *port)
649{ 653{
650 if (port->mapbase == 0xffea0000) 654 if (port->mapbase == 0xffea0000)
@@ -746,7 +750,8 @@ static inline int sci_rxd_in(struct uart_port *port)
746 */ 750 */
747 751
748#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 752#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
749 defined(CONFIG_CPU_SUBTYPE_SH7785) 753 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
754 defined(CONFIG_CPU_SUBTYPE_SH7786)
750#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) 755#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
751#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 756#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
752 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 757 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
diff --git a/drivers/sh/intc.c b/drivers/sh/intc.c
index 58d24c5a76ce..2269fbcaa182 100644
--- a/drivers/sh/intc.c
+++ b/drivers/sh/intc.c
@@ -568,6 +568,10 @@ static void __init intc_register_irq(struct intc_desc *desc,
568 if (!data[0] && data[1]) 568 if (!data[0] && data[1])
569 primary = 1; 569 primary = 1;
570 570
571 if (!data[0] && !data[1])
572 pr_warning("intc: missing unique irq mask for "
573 "irq %d (vect 0x%04x)\n", irq, irq2evt(irq));
574
571 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1); 575 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
572 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1); 576 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
573 577
@@ -641,6 +645,17 @@ static unsigned int __init save_reg(struct intc_desc_int *d,
641 return 0; 645 return 0;
642} 646}
643 647
648static unsigned char *intc_evt2irq_table;
649
650unsigned int intc_evt2irq(unsigned int vector)
651{
652 unsigned int irq = evt2irq(vector);
653
654 if (intc_evt2irq_table && intc_evt2irq_table[irq])
655 irq = intc_evt2irq_table[irq];
656
657 return irq;
658}
644 659
645void __init register_intc_controller(struct intc_desc *desc) 660void __init register_intc_controller(struct intc_desc *desc)
646{ 661{
@@ -705,9 +720,41 @@ void __init register_intc_controller(struct intc_desc *desc)
705 720
706 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ 721 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
707 722
723 /* keep the first vector only if same enum is used multiple times */
724 for (i = 0; i < desc->nr_vectors; i++) {
725 struct intc_vect *vect = desc->vectors + i;
726 int first_irq = evt2irq(vect->vect);
727
728 if (!vect->enum_id)
729 continue;
730
731 for (k = i + 1; k < desc->nr_vectors; k++) {
732 struct intc_vect *vect2 = desc->vectors + k;
733
734 if (vect->enum_id != vect2->enum_id)
735 continue;
736
737 vect2->enum_id = 0;
738
739 if (!intc_evt2irq_table)
740 intc_evt2irq_table = alloc_bootmem(NR_IRQS);
741
742 if (!intc_evt2irq_table) {
743 pr_warning("intc: cannot allocate evt2irq!\n");
744 continue;
745 }
746
747 intc_evt2irq_table[evt2irq(vect2->vect)] = first_irq;
748 }
749 }
750
751 /* register the vectors one by one */
708 for (i = 0; i < desc->nr_vectors; i++) { 752 for (i = 0; i < desc->nr_vectors; i++) {
709 struct intc_vect *vect = desc->vectors + i; 753 struct intc_vect *vect = desc->vectors + i;
710 754
755 if (!vect->enum_id)
756 continue;
757
711 intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect)); 758 intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));
712 } 759 }
713} 760}
diff --git a/drivers/sh/maple/maple.c b/drivers/sh/maple/maple.c
index 63f0de29aa14..c71bb4b4ce84 100644
--- a/drivers/sh/maple/maple.c
+++ b/drivers/sh/maple/maple.c
@@ -1,16 +1,10 @@
1/* 1/*
2 * Core maple bus functionality 2 * Core maple bus functionality
3 * 3 *
4 * Copyright (C) 2007, 2008 Adrian McMenamin 4 * Copyright (C) 2007 - 2009 Adrian McMenamin
5 * Copyright (C) 2001 - 2008 Paul Mundt 5 * Copyright (C) 2001 - 2008 Paul Mundt
6 * 6 * Copyright (C) 2000 - 2001 YAEGASHI Takeshi
7 * Based on 2.4 code by:
8 *
9 * Copyright (C) 2000-2001 YAEGASHI Takeshi
10 * Copyright (C) 2001 M. R. Brown 7 * Copyright (C) 2001 M. R. Brown
11 * Copyright (C) 2001 Paul Mundt
12 *
13 * and others.
14 * 8 *
15 * This file is subject to the terms and conditions of the GNU General Public 9 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive 10 * License. See the file "COPYING" in the main directory of this archive
@@ -32,7 +26,7 @@
32#include <mach/dma.h> 26#include <mach/dma.h>
33#include <mach/sysasic.h> 27#include <mach/sysasic.h>
34 28
35MODULE_AUTHOR("Yaegashi Takeshi, Paul Mundt, M. R. Brown, Adrian McMenamin"); 29MODULE_AUTHOR("Adrian McMenamin <adrian@mcmen.demon.co.uk>");
36MODULE_DESCRIPTION("Maple bus driver for Dreamcast"); 30MODULE_DESCRIPTION("Maple bus driver for Dreamcast");
37MODULE_LICENSE("GPL v2"); 31MODULE_LICENSE("GPL v2");
38MODULE_SUPPORTED_DEVICE("{{SEGA, Dreamcast/Maple}}"); 32MODULE_SUPPORTED_DEVICE("{{SEGA, Dreamcast/Maple}}");
@@ -49,7 +43,7 @@ static LIST_HEAD(maple_sentq);
49/* mutex to protect queue of waiting packets */ 43/* mutex to protect queue of waiting packets */
50static DEFINE_MUTEX(maple_wlist_lock); 44static DEFINE_MUTEX(maple_wlist_lock);
51 45
52static struct maple_driver maple_dummy_driver; 46static struct maple_driver maple_unsupported_device;
53static struct device maple_bus; 47static struct device maple_bus;
54static int subdevice_map[MAPLE_PORTS]; 48static int subdevice_map[MAPLE_PORTS];
55static unsigned long *maple_sendbuf, *maple_sendptr, *maple_lastptr; 49static unsigned long *maple_sendbuf, *maple_sendptr, *maple_lastptr;
@@ -62,8 +56,9 @@ struct maple_device_specify {
62 int unit; 56 int unit;
63}; 57};
64 58
65static bool checked[4]; 59static bool checked[MAPLE_PORTS];
66static struct maple_device *baseunits[4]; 60static bool empty[MAPLE_PORTS];
61static struct maple_device *baseunits[MAPLE_PORTS];
67 62
68/** 63/**
69 * maple_driver_register - register a maple driver 64 * maple_driver_register - register a maple driver
@@ -97,12 +92,20 @@ void maple_driver_unregister(struct maple_driver *drv)
97EXPORT_SYMBOL_GPL(maple_driver_unregister); 92EXPORT_SYMBOL_GPL(maple_driver_unregister);
98 93
99/* set hardware registers to enable next round of dma */ 94/* set hardware registers to enable next round of dma */
100static void maplebus_dma_reset(void) 95static void maple_dma_reset(void)
101{ 96{
102 ctrl_outl(MAPLE_MAGIC, MAPLE_RESET); 97 ctrl_outl(MAPLE_MAGIC, MAPLE_RESET);
103 /* set trig type to 0 for software trigger, 1 for hardware (VBLANK) */ 98 /* set trig type to 0 for software trigger, 1 for hardware (VBLANK) */
104 ctrl_outl(1, MAPLE_TRIGTYPE); 99 ctrl_outl(1, MAPLE_TRIGTYPE);
105 ctrl_outl(MAPLE_2MBPS | MAPLE_TIMEOUT(50000), MAPLE_SPEED); 100 /*
101 * Maple system register
102 * bits 31 - 16 timeout in units of 20nsec
103 * bit 12 hard trigger - set 0 to keep responding to VBLANK
104 * bits 9 - 8 set 00 for 2 Mbps, 01 for 1 Mbps
105 * bits 3 - 0 delay (in 1.3ms) between VBLANK and start of DMA
106 * max delay is 11
107 */
108 ctrl_outl(MAPLE_2MBPS | MAPLE_TIMEOUT(0xFFFF), MAPLE_SPEED);
106 ctrl_outl(PHYSADDR(maple_sendbuf), MAPLE_DMAADDR); 109 ctrl_outl(PHYSADDR(maple_sendbuf), MAPLE_DMAADDR);
107 ctrl_outl(1, MAPLE_ENABLE); 110 ctrl_outl(1, MAPLE_ENABLE);
108} 111}
@@ -134,21 +137,16 @@ static void maple_release_device(struct device *dev)
134{ 137{
135 struct maple_device *mdev; 138 struct maple_device *mdev;
136 struct mapleq *mq; 139 struct mapleq *mq;
137 if (!dev) 140
138 return;
139 mdev = to_maple_dev(dev); 141 mdev = to_maple_dev(dev);
140 mq = mdev->mq; 142 mq = mdev->mq;
141 if (mq) { 143 kmem_cache_free(maple_queue_cache, mq->recvbuf);
142 if (mq->recvbufdcsp) 144 kfree(mq);
143 kmem_cache_free(maple_queue_cache, mq->recvbufdcsp);
144 kfree(mq);
145 mq = NULL;
146 }
147 kfree(mdev); 145 kfree(mdev);
148} 146}
149 147
150/** 148/**
151 * maple_add_packet - add a single instruction to the queue 149 * maple_add_packet - add a single instruction to the maple bus queue
152 * @mdev: maple device 150 * @mdev: maple device
153 * @function: function on device being queried 151 * @function: function on device being queried
154 * @command: maple command to add 152 * @command: maple command to add
@@ -158,68 +156,12 @@ static void maple_release_device(struct device *dev)
158int maple_add_packet(struct maple_device *mdev, u32 function, u32 command, 156int maple_add_packet(struct maple_device *mdev, u32 function, u32 command,
159 size_t length, void *data) 157 size_t length, void *data)
160{ 158{
161 int locking, ret = 0; 159 int ret = 0;
162 void *sendbuf = NULL;
163
164 mutex_lock(&maple_wlist_lock);
165 /* bounce if device already locked */
166 locking = mutex_is_locked(&mdev->mq->mutex);
167 if (locking) {
168 ret = -EBUSY;
169 goto out;
170 }
171
172 mutex_lock(&mdev->mq->mutex);
173
174 if (length) {
175 sendbuf = kmalloc(length * 4, GFP_KERNEL);
176 if (!sendbuf) {
177 mutex_unlock(&mdev->mq->mutex);
178 ret = -ENOMEM;
179 goto out;
180 }
181 ((__be32 *)sendbuf)[0] = cpu_to_be32(function);
182 }
183
184 mdev->mq->command = command;
185 mdev->mq->length = length;
186 if (length > 1)
187 memcpy(sendbuf + 4, data, (length - 1) * 4);
188 mdev->mq->sendbuf = sendbuf;
189
190 list_add(&mdev->mq->list, &maple_waitq);
191out:
192 mutex_unlock(&maple_wlist_lock);
193 return ret;
194}
195EXPORT_SYMBOL_GPL(maple_add_packet);
196
197/**
198 * maple_add_packet_sleeps - add a single instruction to the queue
199 * @mdev: maple device
200 * @function: function on device being queried
201 * @command: maple command to add
202 * @length: length of command string (in 32 bit words)
203 * @data: remainder of command string
204 *
205 * Same as maple_add_packet(), but waits for the lock to become free.
206 */
207int maple_add_packet_sleeps(struct maple_device *mdev, u32 function,
208 u32 command, size_t length, void *data)
209{
210 int locking, ret = 0;
211 void *sendbuf = NULL; 160 void *sendbuf = NULL;
212 161
213 locking = mutex_lock_interruptible(&mdev->mq->mutex);
214 if (locking) {
215 ret = -EIO;
216 goto out;
217 }
218
219 if (length) { 162 if (length) {
220 sendbuf = kmalloc(length * 4, GFP_KERNEL); 163 sendbuf = kzalloc(length * 4, GFP_KERNEL);
221 if (!sendbuf) { 164 if (!sendbuf) {
222 mutex_unlock(&mdev->mq->mutex);
223 ret = -ENOMEM; 165 ret = -ENOMEM;
224 goto out; 166 goto out;
225 } 167 }
@@ -233,38 +175,35 @@ int maple_add_packet_sleeps(struct maple_device *mdev, u32 function,
233 mdev->mq->sendbuf = sendbuf; 175 mdev->mq->sendbuf = sendbuf;
234 176
235 mutex_lock(&maple_wlist_lock); 177 mutex_lock(&maple_wlist_lock);
236 list_add(&mdev->mq->list, &maple_waitq); 178 list_add_tail(&mdev->mq->list, &maple_waitq);
237 mutex_unlock(&maple_wlist_lock); 179 mutex_unlock(&maple_wlist_lock);
238out: 180out:
239 return ret; 181 return ret;
240} 182}
241EXPORT_SYMBOL_GPL(maple_add_packet_sleeps); 183EXPORT_SYMBOL_GPL(maple_add_packet);
242 184
243static struct mapleq *maple_allocq(struct maple_device *mdev) 185static struct mapleq *maple_allocq(struct maple_device *mdev)
244{ 186{
245 struct mapleq *mq; 187 struct mapleq *mq;
246 188
247 mq = kmalloc(sizeof(*mq), GFP_KERNEL); 189 mq = kzalloc(sizeof(*mq), GFP_KERNEL);
248 if (!mq) 190 if (!mq)
249 goto failed_nomem; 191 goto failed_nomem;
250 192
193 INIT_LIST_HEAD(&mq->list);
251 mq->dev = mdev; 194 mq->dev = mdev;
252 mq->recvbufdcsp = kmem_cache_zalloc(maple_queue_cache, GFP_KERNEL); 195 mq->recvbuf = kmem_cache_zalloc(maple_queue_cache, GFP_KERNEL);
253 mq->recvbuf = (void *) P2SEGADDR(mq->recvbufdcsp);
254 if (!mq->recvbuf) 196 if (!mq->recvbuf)
255 goto failed_p2; 197 goto failed_p2;
256 /* 198 mq->recvbuf->buf = &((mq->recvbuf->bufx)[0]);
257 * most devices do not need the mutex - but
258 * anything that injects block reads or writes
259 * will rely on it
260 */
261 mutex_init(&mq->mutex);
262 199
263 return mq; 200 return mq;
264 201
265failed_p2: 202failed_p2:
266 kfree(mq); 203 kfree(mq);
267failed_nomem: 204failed_nomem:
205 dev_err(&mdev->dev, "could not allocate memory for device (%d, %d)\n",
206 mdev->port, mdev->unit);
268 return NULL; 207 return NULL;
269} 208}
270 209
@@ -272,12 +211,16 @@ static struct maple_device *maple_alloc_dev(int port, int unit)
272{ 211{
273 struct maple_device *mdev; 212 struct maple_device *mdev;
274 213
214 /* zero this out to avoid kobj subsystem
215 * thinking it has already been registered */
216
275 mdev = kzalloc(sizeof(*mdev), GFP_KERNEL); 217 mdev = kzalloc(sizeof(*mdev), GFP_KERNEL);
276 if (!mdev) 218 if (!mdev)
277 return NULL; 219 return NULL;
278 220
279 mdev->port = port; 221 mdev->port = port;
280 mdev->unit = unit; 222 mdev->unit = unit;
223
281 mdev->mq = maple_allocq(mdev); 224 mdev->mq = maple_allocq(mdev);
282 225
283 if (!mdev->mq) { 226 if (!mdev->mq) {
@@ -286,19 +229,14 @@ static struct maple_device *maple_alloc_dev(int port, int unit)
286 } 229 }
287 mdev->dev.bus = &maple_bus_type; 230 mdev->dev.bus = &maple_bus_type;
288 mdev->dev.parent = &maple_bus; 231 mdev->dev.parent = &maple_bus;
232 init_waitqueue_head(&mdev->maple_wait);
289 return mdev; 233 return mdev;
290} 234}
291 235
292static void maple_free_dev(struct maple_device *mdev) 236static void maple_free_dev(struct maple_device *mdev)
293{ 237{
294 if (!mdev) 238 kmem_cache_free(maple_queue_cache, mdev->mq->recvbuf);
295 return; 239 kfree(mdev->mq);
296 if (mdev->mq) {
297 if (mdev->mq->recvbufdcsp)
298 kmem_cache_free(maple_queue_cache,
299 mdev->mq->recvbufdcsp);
300 kfree(mdev->mq);
301 }
302 kfree(mdev); 240 kfree(mdev);
303} 241}
304 242
@@ -320,7 +258,7 @@ static void maple_build_block(struct mapleq *mq)
320 maple_lastptr = maple_sendptr; 258 maple_lastptr = maple_sendptr;
321 259
322 *maple_sendptr++ = (port << 16) | len | 0x80000000; 260 *maple_sendptr++ = (port << 16) | len | 0x80000000;
323 *maple_sendptr++ = PHYSADDR(mq->recvbuf); 261 *maple_sendptr++ = PHYSADDR(mq->recvbuf->buf);
324 *maple_sendptr++ = 262 *maple_sendptr++ =
325 mq->command | (to << 8) | (from << 16) | (len << 24); 263 mq->command | (to << 8) | (from << 16) | (len << 24);
326 while (len-- > 0) 264 while (len-- > 0)
@@ -333,20 +271,28 @@ static void maple_send(void)
333 int i, maple_packets = 0; 271 int i, maple_packets = 0;
334 struct mapleq *mq, *nmq; 272 struct mapleq *mq, *nmq;
335 273
336 if (!list_empty(&maple_sentq)) 274 if (!maple_dma_done())
337 return; 275 return;
276
277 /* disable DMA */
278 ctrl_outl(0, MAPLE_ENABLE);
279
280 if (!list_empty(&maple_sentq))
281 goto finish;
282
338 mutex_lock(&maple_wlist_lock); 283 mutex_lock(&maple_wlist_lock);
339 if (list_empty(&maple_waitq) || !maple_dma_done()) { 284 if (list_empty(&maple_waitq)) {
340 mutex_unlock(&maple_wlist_lock); 285 mutex_unlock(&maple_wlist_lock);
341 return; 286 goto finish;
342 } 287 }
343 mutex_unlock(&maple_wlist_lock); 288
344 maple_lastptr = maple_sendbuf; 289 maple_lastptr = maple_sendbuf;
345 maple_sendptr = maple_sendbuf; 290 maple_sendptr = maple_sendbuf;
346 mutex_lock(&maple_wlist_lock); 291
347 list_for_each_entry_safe(mq, nmq, &maple_waitq, list) { 292 list_for_each_entry_safe(mq, nmq, &maple_waitq, list) {
348 maple_build_block(mq); 293 maple_build_block(mq);
349 list_move(&mq->list, &maple_sentq); 294 list_del_init(&mq->list);
295 list_add_tail(&mq->list, &maple_sentq);
350 if (maple_packets++ > MAPLE_MAXPACKETS) 296 if (maple_packets++ > MAPLE_MAXPACKETS)
351 break; 297 break;
352 } 298 }
@@ -356,10 +302,13 @@ static void maple_send(void)
356 dma_cache_sync(0, maple_sendbuf + i * PAGE_SIZE, 302 dma_cache_sync(0, maple_sendbuf + i * PAGE_SIZE,
357 PAGE_SIZE, DMA_BIDIRECTIONAL); 303 PAGE_SIZE, DMA_BIDIRECTIONAL);
358 } 304 }
305
306finish:
307 maple_dma_reset();
359} 308}
360 309
361/* check if there is a driver registered likely to match this device */ 310/* check if there is a driver registered likely to match this device */
362static int check_matching_maple_driver(struct device_driver *driver, 311static int maple_check_matching_driver(struct device_driver *driver,
363 void *devptr) 312 void *devptr)
364{ 313{
365 struct maple_driver *maple_drv; 314 struct maple_driver *maple_drv;
@@ -374,10 +323,7 @@ static int check_matching_maple_driver(struct device_driver *driver,
374 323
375static void maple_detach_driver(struct maple_device *mdev) 324static void maple_detach_driver(struct maple_device *mdev)
376{ 325{
377 if (!mdev)
378 return;
379 device_unregister(&mdev->dev); 326 device_unregister(&mdev->dev);
380 mdev = NULL;
381} 327}
382 328
383/* process initial MAPLE_COMMAND_DEVINFO for each device or port */ 329/* process initial MAPLE_COMMAND_DEVINFO for each device or port */
@@ -385,9 +331,9 @@ static void maple_attach_driver(struct maple_device *mdev)
385{ 331{
386 char *p, *recvbuf; 332 char *p, *recvbuf;
387 unsigned long function; 333 unsigned long function;
388 int matched, retval; 334 int matched, error;
389 335
390 recvbuf = mdev->mq->recvbuf; 336 recvbuf = mdev->mq->recvbuf->buf;
391 /* copy the data as individual elements in 337 /* copy the data as individual elements in
392 * case of memory optimisation */ 338 * case of memory optimisation */
393 memcpy(&mdev->devinfo.function, recvbuf + 4, 4); 339 memcpy(&mdev->devinfo.function, recvbuf + 4, 4);
@@ -395,7 +341,6 @@ static void maple_attach_driver(struct maple_device *mdev)
395 memcpy(&mdev->devinfo.area_code, recvbuf + 20, 1); 341 memcpy(&mdev->devinfo.area_code, recvbuf + 20, 1);
396 memcpy(&mdev->devinfo.connector_direction, recvbuf + 21, 1); 342 memcpy(&mdev->devinfo.connector_direction, recvbuf + 21, 1);
397 memcpy(&mdev->devinfo.product_name[0], recvbuf + 22, 30); 343 memcpy(&mdev->devinfo.product_name[0], recvbuf + 22, 30);
398 memcpy(&mdev->devinfo.product_licence[0], recvbuf + 52, 60);
399 memcpy(&mdev->devinfo.standby_power, recvbuf + 112, 2); 344 memcpy(&mdev->devinfo.standby_power, recvbuf + 112, 2);
400 memcpy(&mdev->devinfo.max_power, recvbuf + 114, 2); 345 memcpy(&mdev->devinfo.max_power, recvbuf + 114, 2);
401 memcpy(mdev->product_name, mdev->devinfo.product_name, 30); 346 memcpy(mdev->product_name, mdev->devinfo.product_name, 30);
@@ -414,43 +359,40 @@ static void maple_attach_driver(struct maple_device *mdev)
414 else 359 else
415 break; 360 break;
416 361
417 printk(KERN_INFO "Maple device detected: %s\n",
418 mdev->product_name);
419 printk(KERN_INFO "Maple device: %s\n", mdev->product_licence);
420
421 function = be32_to_cpu(mdev->devinfo.function); 362 function = be32_to_cpu(mdev->devinfo.function);
422 363
364 dev_info(&mdev->dev, "detected %s: function 0x%lX: at (%d, %d)\n",
365 mdev->product_name, function, mdev->port, mdev->unit);
366
423 if (function > 0x200) { 367 if (function > 0x200) {
424 /* Do this silently - as not a real device */ 368 /* Do this silently - as not a real device */
425 function = 0; 369 function = 0;
426 mdev->driver = &maple_dummy_driver; 370 mdev->driver = &maple_unsupported_device;
427 sprintf(mdev->dev.bus_id, "%d:0.port", mdev->port); 371 dev_set_name(&mdev->dev, "%d:0.port", mdev->port);
428 } else { 372 } else {
429 printk(KERN_INFO
430 "Maple bus at (%d, %d): Function 0x%lX\n",
431 mdev->port, mdev->unit, function);
432
433 matched = 373 matched =
434 bus_for_each_drv(&maple_bus_type, NULL, mdev, 374 bus_for_each_drv(&maple_bus_type, NULL, mdev,
435 check_matching_maple_driver); 375 maple_check_matching_driver);
436 376
437 if (matched == 0) { 377 if (matched == 0) {
438 /* Driver does not exist yet */ 378 /* Driver does not exist yet */
439 printk(KERN_INFO 379 dev_info(&mdev->dev, "no driver found\n");
440 "No maple driver found.\n"); 380 mdev->driver = &maple_unsupported_device;
441 mdev->driver = &maple_dummy_driver;
442 } 381 }
443 sprintf(mdev->dev.bus_id, "%d:0%d.%lX", mdev->port, 382
444 mdev->unit, function); 383 dev_set_name(&mdev->dev, "%d:0%d.%lX", mdev->port,
384 mdev->unit, function);
445 } 385 }
386
446 mdev->function = function; 387 mdev->function = function;
447 mdev->dev.release = &maple_release_device; 388 mdev->dev.release = &maple_release_device;
448 retval = device_register(&mdev->dev); 389
449 if (retval) { 390 atomic_set(&mdev->busy, 0);
450 printk(KERN_INFO 391 error = device_register(&mdev->dev);
451 "Maple bus: Attempt to register device" 392 if (error) {
452 " (%x, %x) failed.\n", 393 dev_warn(&mdev->dev, "could not register device at"
453 mdev->port, mdev->unit); 394 " (%d, %d), with error 0x%X\n", mdev->unit,
395 mdev->port, error);
454 maple_free_dev(mdev); 396 maple_free_dev(mdev);
455 mdev = NULL; 397 mdev = NULL;
456 return; 398 return;
@@ -462,7 +404,7 @@ static void maple_attach_driver(struct maple_device *mdev)
462 * port and unit then return 1 - allows identification 404 * port and unit then return 1 - allows identification
463 * of which devices need to be attached or detached 405 * of which devices need to be attached or detached
464 */ 406 */
465static int detach_maple_device(struct device *device, void *portptr) 407static int check_maple_device(struct device *device, void *portptr)
466{ 408{
467 struct maple_device_specify *ds; 409 struct maple_device_specify *ds;
468 struct maple_device *mdev; 410 struct maple_device *mdev;
@@ -477,21 +419,25 @@ static int detach_maple_device(struct device *device, void *portptr)
477static int setup_maple_commands(struct device *device, void *ignored) 419static int setup_maple_commands(struct device *device, void *ignored)
478{ 420{
479 int add; 421 int add;
480 struct maple_device *maple_dev = to_maple_dev(device); 422 struct maple_device *mdev = to_maple_dev(device);
481 423 if (mdev->interval > 0 && atomic_read(&mdev->busy) == 0 &&
482 if ((maple_dev->interval > 0) 424 time_after(jiffies, mdev->when)) {
483 && time_after(jiffies, maple_dev->when)) { 425 /* bounce if we cannot add */
484 /* bounce if we cannot lock */ 426 add = maple_add_packet(mdev,
485 add = maple_add_packet(maple_dev, 427 be32_to_cpu(mdev->devinfo.function),
486 be32_to_cpu(maple_dev->devinfo.function),
487 MAPLE_COMMAND_GETCOND, 1, NULL); 428 MAPLE_COMMAND_GETCOND, 1, NULL);
488 if (!add) 429 if (!add)
489 maple_dev->when = jiffies + maple_dev->interval; 430 mdev->when = jiffies + mdev->interval;
490 } else { 431 } else {
491 if (time_after(jiffies, maple_pnp_time)) 432 if (time_after(jiffies, maple_pnp_time))
492 /* This will also bounce */ 433 /* Ensure we don't have block reads and devinfo
493 maple_add_packet(maple_dev, 0, 434 * calls interfering with one another - so flag the
494 MAPLE_COMMAND_DEVINFO, 0, NULL); 435 * device as busy */
436 if (atomic_read(&mdev->busy) == 0) {
437 atomic_set(&mdev->busy, 1);
438 maple_add_packet(mdev, 0,
439 MAPLE_COMMAND_DEVINFO, 0, NULL);
440 }
495 } 441 }
496 return 0; 442 return 0;
497} 443}
@@ -499,29 +445,50 @@ static int setup_maple_commands(struct device *device, void *ignored)
499/* VBLANK bottom half - implemented via workqueue */ 445/* VBLANK bottom half - implemented via workqueue */
500static void maple_vblank_handler(struct work_struct *work) 446static void maple_vblank_handler(struct work_struct *work)
501{ 447{
502 if (!list_empty(&maple_sentq) || !maple_dma_done()) 448 int x, locking;
449 struct maple_device *mdev;
450
451 if (!maple_dma_done())
503 return; 452 return;
504 453
505 ctrl_outl(0, MAPLE_ENABLE); 454 ctrl_outl(0, MAPLE_ENABLE);
506 455
456 if (!list_empty(&maple_sentq))
457 goto finish;
458
459 /*
460 * Set up essential commands - to fetch data and
461 * check devices are still present
462 */
507 bus_for_each_dev(&maple_bus_type, NULL, NULL, 463 bus_for_each_dev(&maple_bus_type, NULL, NULL,
508 setup_maple_commands); 464 setup_maple_commands);
465
466 if (time_after(jiffies, maple_pnp_time)) {
467 /*
468 * Scan the empty ports - bus is flakey and may have
469 * mis-reported emptyness
470 */
471 for (x = 0; x < MAPLE_PORTS; x++) {
472 if (checked[x] && empty[x]) {
473 mdev = baseunits[x];
474 if (!mdev)
475 break;
476 atomic_set(&mdev->busy, 1);
477 locking = maple_add_packet(mdev, 0,
478 MAPLE_COMMAND_DEVINFO, 0, NULL);
479 if (!locking)
480 break;
481 }
482 }
509 483
510 if (time_after(jiffies, maple_pnp_time))
511 maple_pnp_time = jiffies + MAPLE_PNP_INTERVAL; 484 maple_pnp_time = jiffies + MAPLE_PNP_INTERVAL;
512
513 mutex_lock(&maple_wlist_lock);
514 if (!list_empty(&maple_waitq) && list_empty(&maple_sentq)) {
515 mutex_unlock(&maple_wlist_lock);
516 maple_send();
517 } else {
518 mutex_unlock(&maple_wlist_lock);
519 } 485 }
520 486
521 maplebus_dma_reset(); 487finish:
488 maple_send();
522} 489}
523 490
524/* handle devices added via hotplugs - placing them on queue for DEVINFO*/ 491/* handle devices added via hotplugs - placing them on queue for DEVINFO */
525static void maple_map_subunits(struct maple_device *mdev, int submask) 492static void maple_map_subunits(struct maple_device *mdev, int submask)
526{ 493{
527 int retval, k, devcheck; 494 int retval, k, devcheck;
@@ -533,7 +500,7 @@ static void maple_map_subunits(struct maple_device *mdev, int submask)
533 ds.unit = k + 1; 500 ds.unit = k + 1;
534 retval = 501 retval =
535 bus_for_each_dev(&maple_bus_type, NULL, &ds, 502 bus_for_each_dev(&maple_bus_type, NULL, &ds,
536 detach_maple_device); 503 check_maple_device);
537 if (retval) { 504 if (retval) {
538 submask = submask >> 1; 505 submask = submask >> 1;
539 continue; 506 continue;
@@ -543,6 +510,7 @@ static void maple_map_subunits(struct maple_device *mdev, int submask)
543 mdev_add = maple_alloc_dev(mdev->port, k + 1); 510 mdev_add = maple_alloc_dev(mdev->port, k + 1);
544 if (!mdev_add) 511 if (!mdev_add)
545 return; 512 return;
513 atomic_set(&mdev_add->busy, 1);
546 maple_add_packet(mdev_add, 0, MAPLE_COMMAND_DEVINFO, 514 maple_add_packet(mdev_add, 0, MAPLE_COMMAND_DEVINFO,
547 0, NULL); 515 0, NULL);
548 /* mark that we are checking sub devices */ 516 /* mark that we are checking sub devices */
@@ -564,27 +532,45 @@ static void maple_clean_submap(struct maple_device *mdev)
564} 532}
565 533
566/* handle empty port or hotplug removal */ 534/* handle empty port or hotplug removal */
567static void maple_response_none(struct maple_device *mdev, 535static void maple_response_none(struct maple_device *mdev)
568 struct mapleq *mq) 536{
569{ 537 maple_clean_submap(mdev);
570 if (mdev->unit != 0) { 538
571 list_del(&mq->list); 539 if (likely(mdev->unit != 0)) {
572 maple_clean_submap(mdev); 540 /*
573 printk(KERN_INFO 541 * Block devices play up
574 "Maple bus device detaching at (%d, %d)\n", 542 * and give the impression they have
575 mdev->port, mdev->unit); 543 * been removed even when still in place or
544 * trip the mtd layer when they have
545 * really gone - this code traps that eventuality
546 * and ensures we aren't overloaded with useless
547 * error messages
548 */
549 if (mdev->can_unload) {
550 if (!mdev->can_unload(mdev)) {
551 atomic_set(&mdev->busy, 2);
552 wake_up(&mdev->maple_wait);
553 return;
554 }
555 }
556
557 dev_info(&mdev->dev, "detaching device at (%d, %d)\n",
558 mdev->port, mdev->unit);
576 maple_detach_driver(mdev); 559 maple_detach_driver(mdev);
577 return; 560 return;
578 } 561 } else {
579 if (!started || !fullscan) { 562 if (!started || !fullscan) {
580 if (checked[mdev->port] == false) { 563 if (checked[mdev->port] == false) {
581 checked[mdev->port] = true; 564 checked[mdev->port] = true;
582 printk(KERN_INFO "No maple devices attached" 565 empty[mdev->port] = true;
583 " to port %d\n", mdev->port); 566 dev_info(&mdev->dev, "no devices"
567 " to port %d\n", mdev->port);
568 }
569 return;
584 } 570 }
585 return;
586 } 571 }
587 maple_clean_submap(mdev); 572 /* Some hardware devices generate false detach messages on unit 0 */
573 atomic_set(&mdev->busy, 0);
588} 574}
589 575
590/* preprocess hotplugs or scans */ 576/* preprocess hotplugs or scans */
@@ -599,8 +585,11 @@ static void maple_response_devinfo(struct maple_device *mdev,
599 } else { 585 } else {
600 if (mdev->unit != 0) 586 if (mdev->unit != 0)
601 maple_attach_driver(mdev); 587 maple_attach_driver(mdev);
588 if (mdev->unit == 0) {
589 empty[mdev->port] = false;
590 maple_attach_driver(mdev);
591 }
602 } 592 }
603 return;
604 } 593 }
605 if (mdev->unit == 0) { 594 if (mdev->unit == 0) {
606 submask = recvbuf[2] & 0x1F; 595 submask = recvbuf[2] & 0x1F;
@@ -611,6 +600,17 @@ static void maple_response_devinfo(struct maple_device *mdev,
611 } 600 }
612} 601}
613 602
603static void maple_response_fileerr(struct maple_device *mdev, void *recvbuf)
604{
605 if (mdev->fileerr_handler) {
606 mdev->fileerr_handler(mdev, recvbuf);
607 return;
608 } else
609 dev_warn(&mdev->dev, "device at (%d, %d) reports"
610 "file error 0x%X\n", mdev->port, mdev->unit,
611 ((int *)recvbuf)[1]);
612}
613
614static void maple_port_rescan(void) 614static void maple_port_rescan(void)
615{ 615{
616 int i; 616 int i;
@@ -621,12 +621,6 @@ static void maple_port_rescan(void)
621 if (checked[i] == false) { 621 if (checked[i] == false) {
622 fullscan = 0; 622 fullscan = 0;
623 mdev = baseunits[i]; 623 mdev = baseunits[i];
624 /*
625 * test lock in case scan has failed
626 * but device is still locked
627 */
628 if (mutex_is_locked(&mdev->mq->mutex))
629 mutex_unlock(&mdev->mq->mutex);
630 maple_add_packet(mdev, 0, MAPLE_COMMAND_DEVINFO, 624 maple_add_packet(mdev, 0, MAPLE_COMMAND_DEVINFO,
631 0, NULL); 625 0, NULL);
632 } 626 }
@@ -637,7 +631,7 @@ static void maple_port_rescan(void)
637static void maple_dma_handler(struct work_struct *work) 631static void maple_dma_handler(struct work_struct *work)
638{ 632{
639 struct mapleq *mq, *nmq; 633 struct mapleq *mq, *nmq;
640 struct maple_device *dev; 634 struct maple_device *mdev;
641 char *recvbuf; 635 char *recvbuf;
642 enum maple_code code; 636 enum maple_code code;
643 637
@@ -646,43 +640,56 @@ static void maple_dma_handler(struct work_struct *work)
646 ctrl_outl(0, MAPLE_ENABLE); 640 ctrl_outl(0, MAPLE_ENABLE);
647 if (!list_empty(&maple_sentq)) { 641 if (!list_empty(&maple_sentq)) {
648 list_for_each_entry_safe(mq, nmq, &maple_sentq, list) { 642 list_for_each_entry_safe(mq, nmq, &maple_sentq, list) {
649 recvbuf = mq->recvbuf; 643 mdev = mq->dev;
644 recvbuf = mq->recvbuf->buf;
645 dma_cache_sync(&mdev->dev, recvbuf, 0x400,
646 DMA_FROM_DEVICE);
650 code = recvbuf[0]; 647 code = recvbuf[0];
651 dev = mq->dev;
652 kfree(mq->sendbuf); 648 kfree(mq->sendbuf);
653 mutex_unlock(&mq->mutex);
654 list_del_init(&mq->list); 649 list_del_init(&mq->list);
655
656 switch (code) { 650 switch (code) {
657 case MAPLE_RESPONSE_NONE: 651 case MAPLE_RESPONSE_NONE:
658 maple_response_none(dev, mq); 652 maple_response_none(mdev);
659 break; 653 break;
660 654
661 case MAPLE_RESPONSE_DEVINFO: 655 case MAPLE_RESPONSE_DEVINFO:
662 maple_response_devinfo(dev, recvbuf); 656 maple_response_devinfo(mdev, recvbuf);
657 atomic_set(&mdev->busy, 0);
663 break; 658 break;
664 659
665 case MAPLE_RESPONSE_DATATRF: 660 case MAPLE_RESPONSE_DATATRF:
666 if (dev->callback) 661 if (mdev->callback)
667 dev->callback(mq); 662 mdev->callback(mq);
663 atomic_set(&mdev->busy, 0);
664 wake_up(&mdev->maple_wait);
668 break; 665 break;
669 666
670 case MAPLE_RESPONSE_FILEERR: 667 case MAPLE_RESPONSE_FILEERR:
668 maple_response_fileerr(mdev, recvbuf);
669 atomic_set(&mdev->busy, 0);
670 wake_up(&mdev->maple_wait);
671 break;
672
671 case MAPLE_RESPONSE_AGAIN: 673 case MAPLE_RESPONSE_AGAIN:
672 case MAPLE_RESPONSE_BADCMD: 674 case MAPLE_RESPONSE_BADCMD:
673 case MAPLE_RESPONSE_BADFUNC: 675 case MAPLE_RESPONSE_BADFUNC:
674 printk(KERN_DEBUG 676 dev_warn(&mdev->dev, "non-fatal error"
675 "Maple non-fatal error 0x%X\n", 677 " 0x%X at (%d, %d)\n", code,
676 code); 678 mdev->port, mdev->unit);
679 atomic_set(&mdev->busy, 0);
677 break; 680 break;
678 681
679 case MAPLE_RESPONSE_ALLINFO: 682 case MAPLE_RESPONSE_ALLINFO:
680 printk(KERN_DEBUG 683 dev_notice(&mdev->dev, "extended"
681 "Maple - extended device information" 684 " device information request for (%d, %d)"
682 " not supported\n"); 685 " but call is not supported\n", mdev->port,
686 mdev->unit);
687 atomic_set(&mdev->busy, 0);
683 break; 688 break;
684 689
685 case MAPLE_RESPONSE_OK: 690 case MAPLE_RESPONSE_OK:
691 atomic_set(&mdev->busy, 0);
692 wake_up(&mdev->maple_wait);
686 break; 693 break;
687 694
688 default: 695 default:
@@ -699,20 +706,19 @@ static void maple_dma_handler(struct work_struct *work)
699 if (!fullscan) 706 if (!fullscan)
700 maple_port_rescan(); 707 maple_port_rescan();
701 /* mark that we have been through the first scan */ 708 /* mark that we have been through the first scan */
702 if (started == 0) 709 started = 1;
703 started = 1;
704 } 710 }
705 maplebus_dma_reset(); 711 maple_send();
706} 712}
707 713
708static irqreturn_t maplebus_dma_interrupt(int irq, void *dev_id) 714static irqreturn_t maple_dma_interrupt(int irq, void *dev_id)
709{ 715{
710 /* Load everything into the bottom half */ 716 /* Load everything into the bottom half */
711 schedule_work(&maple_dma_process); 717 schedule_work(&maple_dma_process);
712 return IRQ_HANDLED; 718 return IRQ_HANDLED;
713} 719}
714 720
715static irqreturn_t maplebus_vblank_interrupt(int irq, void *dev_id) 721static irqreturn_t maple_vblank_interrupt(int irq, void *dev_id)
716{ 722{
717 schedule_work(&maple_vblank_process); 723 schedule_work(&maple_vblank_process);
718 return IRQ_HANDLED; 724 return IRQ_HANDLED;
@@ -720,14 +726,14 @@ static irqreturn_t maplebus_vblank_interrupt(int irq, void *dev_id)
720 726
721static int maple_set_dma_interrupt_handler(void) 727static int maple_set_dma_interrupt_handler(void)
722{ 728{
723 return request_irq(HW_EVENT_MAPLE_DMA, maplebus_dma_interrupt, 729 return request_irq(HW_EVENT_MAPLE_DMA, maple_dma_interrupt,
724 IRQF_SHARED, "maple bus DMA", &maple_dummy_driver); 730 IRQF_SHARED, "maple bus DMA", &maple_unsupported_device);
725} 731}
726 732
727static int maple_set_vblank_interrupt_handler(void) 733static int maple_set_vblank_interrupt_handler(void)
728{ 734{
729 return request_irq(HW_EVENT_VSYNC, maplebus_vblank_interrupt, 735 return request_irq(HW_EVENT_VSYNC, maple_vblank_interrupt,
730 IRQF_SHARED, "maple bus VBLANK", &maple_dummy_driver); 736 IRQF_SHARED, "maple bus VBLANK", &maple_unsupported_device);
731} 737}
732 738
733static int maple_get_dma_buffer(void) 739static int maple_get_dma_buffer(void)
@@ -740,7 +746,7 @@ static int maple_get_dma_buffer(void)
740 return 0; 746 return 0;
741} 747}
742 748
743static int match_maple_bus_driver(struct device *devptr, 749static int maple_match_bus_driver(struct device *devptr,
744 struct device_driver *drvptr) 750 struct device_driver *drvptr)
745{ 751{
746 struct maple_driver *maple_drv = to_maple_driver(drvptr); 752 struct maple_driver *maple_drv = to_maple_driver(drvptr);
@@ -765,22 +771,24 @@ static void maple_bus_release(struct device *dev)
765{ 771{
766} 772}
767 773
768static struct maple_driver maple_dummy_driver = { 774static struct maple_driver maple_unsupported_device = {
769 .drv = { 775 .drv = {
770 .name = "maple_dummy_driver", 776 .name = "maple_unsupported_device",
771 .bus = &maple_bus_type, 777 .bus = &maple_bus_type,
772 }, 778 },
773}; 779};
774 780/**
781 * maple_bus_type - core maple bus structure
782 */
775struct bus_type maple_bus_type = { 783struct bus_type maple_bus_type = {
776 .name = "maple", 784 .name = "maple",
777 .match = match_maple_bus_driver, 785 .match = maple_match_bus_driver,
778 .uevent = maple_bus_uevent, 786 .uevent = maple_bus_uevent,
779}; 787};
780EXPORT_SYMBOL_GPL(maple_bus_type); 788EXPORT_SYMBOL_GPL(maple_bus_type);
781 789
782static struct device maple_bus = { 790static struct device maple_bus = {
783 .bus_id = "maple", 791 .init_name = "maple",
784 .release = maple_bus_release, 792 .release = maple_bus_release,
785}; 793};
786 794
@@ -788,7 +796,8 @@ static int __init maple_bus_init(void)
788{ 796{
789 int retval, i; 797 int retval, i;
790 struct maple_device *mdev[MAPLE_PORTS]; 798 struct maple_device *mdev[MAPLE_PORTS];
791 ctrl_outl(0, MAPLE_STATE); 799
800 ctrl_outl(0, MAPLE_ENABLE);
792 801
793 retval = device_register(&maple_bus); 802 retval = device_register(&maple_bus);
794 if (retval) 803 if (retval)
@@ -798,36 +807,33 @@ static int __init maple_bus_init(void)
798 if (retval) 807 if (retval)
799 goto cleanup_device; 808 goto cleanup_device;
800 809
801 retval = driver_register(&maple_dummy_driver.drv); 810 retval = driver_register(&maple_unsupported_device.drv);
802 if (retval) 811 if (retval)
803 goto cleanup_bus; 812 goto cleanup_bus;
804 813
805 /* allocate memory for maple bus dma */ 814 /* allocate memory for maple bus dma */
806 retval = maple_get_dma_buffer(); 815 retval = maple_get_dma_buffer();
807 if (retval) { 816 if (retval) {
808 printk(KERN_INFO 817 dev_err(&maple_bus, "failed to allocate DMA buffers\n");
809 "Maple bus: Failed to allocate Maple DMA buffers\n");
810 goto cleanup_basic; 818 goto cleanup_basic;
811 } 819 }
812 820
813 /* set up DMA interrupt handler */ 821 /* set up DMA interrupt handler */
814 retval = maple_set_dma_interrupt_handler(); 822 retval = maple_set_dma_interrupt_handler();
815 if (retval) { 823 if (retval) {
816 printk(KERN_INFO 824 dev_err(&maple_bus, "bus failed to grab maple "
817 "Maple bus: Failed to grab maple DMA IRQ\n"); 825 "DMA IRQ\n");
818 goto cleanup_dma; 826 goto cleanup_dma;
819 } 827 }
820 828
821 /* set up VBLANK interrupt handler */ 829 /* set up VBLANK interrupt handler */
822 retval = maple_set_vblank_interrupt_handler(); 830 retval = maple_set_vblank_interrupt_handler();
823 if (retval) { 831 if (retval) {
824 printk(KERN_INFO "Maple bus: Failed to grab VBLANK IRQ\n"); 832 dev_err(&maple_bus, "bus failed to grab VBLANK IRQ\n");
825 goto cleanup_irq; 833 goto cleanup_irq;
826 } 834 }
827 835
828 maple_queue_cache = 836 maple_queue_cache = KMEM_CACHE(maple_buffer, SLAB_HWCACHE_ALIGN);
829 kmem_cache_create("maple_queue_cache", 0x400, 0,
830 SLAB_HWCACHE_ALIGN, NULL);
831 837
832 if (!maple_queue_cache) 838 if (!maple_queue_cache)
833 goto cleanup_bothirqs; 839 goto cleanup_bothirqs;
@@ -838,23 +844,23 @@ static int __init maple_bus_init(void)
838 /* setup maple ports */ 844 /* setup maple ports */
839 for (i = 0; i < MAPLE_PORTS; i++) { 845 for (i = 0; i < MAPLE_PORTS; i++) {
840 checked[i] = false; 846 checked[i] = false;
847 empty[i] = false;
841 mdev[i] = maple_alloc_dev(i, 0); 848 mdev[i] = maple_alloc_dev(i, 0);
842 baseunits[i] = mdev[i];
843 if (!mdev[i]) { 849 if (!mdev[i]) {
844 while (i-- > 0) 850 while (i-- > 0)
845 maple_free_dev(mdev[i]); 851 maple_free_dev(mdev[i]);
846 goto cleanup_cache; 852 goto cleanup_cache;
847 } 853 }
854 baseunits[i] = mdev[i];
855 atomic_set(&mdev[i]->busy, 1);
848 maple_add_packet(mdev[i], 0, MAPLE_COMMAND_DEVINFO, 0, NULL); 856 maple_add_packet(mdev[i], 0, MAPLE_COMMAND_DEVINFO, 0, NULL);
849 subdevice_map[i] = 0; 857 subdevice_map[i] = 0;
850 } 858 }
851 859
852 /* setup maplebus hardware */ 860 maple_pnp_time = jiffies + HZ;
853 maplebus_dma_reset(); 861 /* prepare initial queue */
854 /* initial detection */
855 maple_send(); 862 maple_send();
856 maple_pnp_time = jiffies; 863 dev_info(&maple_bus, "bus core now registered\n");
857 printk(KERN_INFO "Maple bus core now registered.\n");
858 864
859 return 0; 865 return 0;
860 866
@@ -871,7 +877,7 @@ cleanup_dma:
871 free_pages((unsigned long) maple_sendbuf, MAPLE_DMA_PAGES); 877 free_pages((unsigned long) maple_sendbuf, MAPLE_DMA_PAGES);
872 878
873cleanup_basic: 879cleanup_basic:
874 driver_unregister(&maple_dummy_driver.drv); 880 driver_unregister(&maple_unsupported_device.drv);
875 881
876cleanup_bus: 882cleanup_bus:
877 bus_unregister(&maple_bus_type); 883 bus_unregister(&maple_bus_type);
@@ -880,7 +886,7 @@ cleanup_device:
880 device_unregister(&maple_bus); 886 device_unregister(&maple_bus);
881 887
882cleanup: 888cleanup:
883 printk(KERN_INFO "Maple bus registration failed\n"); 889 printk(KERN_ERR "Maple bus registration failed\n");
884 return retval; 890 return retval;
885} 891}
886/* Push init to later to ensure hardware gets detected */ 892/* Push init to later to ensure hardware gets detected */
diff --git a/drivers/sh/superhyway/superhyway.c b/drivers/sh/superhyway/superhyway.c
index 4d0282b821b5..2d9e7f3d5611 100644
--- a/drivers/sh/superhyway/superhyway.c
+++ b/drivers/sh/superhyway/superhyway.c
@@ -22,7 +22,7 @@
22static int superhyway_devices; 22static int superhyway_devices;
23 23
24static struct device superhyway_bus_device = { 24static struct device superhyway_bus_device = {
25 .bus_id = "superhyway", 25 .init_name = "superhyway",
26}; 26};
27 27
28static void superhyway_device_release(struct device *dev) 28static void superhyway_device_release(struct device *dev)
@@ -83,7 +83,7 @@ int superhyway_add_device(unsigned long base, struct superhyway_device *sdev,
83 dev->id.id = dev->vcr.mod_id; 83 dev->id.id = dev->vcr.mod_id;
84 84
85 sprintf(dev->name, "SuperHyway device %04x", dev->id.id); 85 sprintf(dev->name, "SuperHyway device %04x", dev->id.id);
86 sprintf(dev->dev.bus_id, "%02x", superhyway_devices); 86 dev_set_name(&dev->dev, "%02x", superhyway_devices);
87 87
88 superhyway_devices++; 88 superhyway_devices++;
89 89
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 83babb0a1df7..c6c816b7ecb5 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -47,6 +47,7 @@ config USB_ARCH_HAS_OHCI
47 default y if CPU_SUBTYPE_SH7720 47 default y if CPU_SUBTYPE_SH7720
48 default y if CPU_SUBTYPE_SH7721 48 default y if CPU_SUBTYPE_SH7721
49 default y if CPU_SUBTYPE_SH7763 49 default y if CPU_SUBTYPE_SH7763
50 default y if CPU_SUBTYPE_SH7786
50 # more: 51 # more:
51 default PCI 52 default PCI
52 53
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 5cf5f1eca4f4..7658589edb1c 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1049,7 +1049,8 @@ MODULE_LICENSE ("GPL");
1049 1049
1050#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 1050#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
1051 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 1051 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
1052 defined(CONFIG_CPU_SUBTYPE_SH7763) 1052 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1053 defined(CONFIG_CPU_SUBTYPE_SH7786)
1053#include "ohci-sh.c" 1054#include "ohci-sh.c"
1054#define PLATFORM_DRIVER ohci_hcd_sh_driver 1055#define PLATFORM_DRIVER ohci_hcd_sh_driver
1055#endif 1056#endif
diff --git a/drivers/video/pvr2fb.c b/drivers/video/pvr2fb.c
index 0a0fd48a8566..53f8f1100e81 100644
--- a/drivers/video/pvr2fb.c
+++ b/drivers/video/pvr2fb.c
@@ -61,7 +61,7 @@
61#include <mach-dreamcast/mach/sysasic.h> 61#include <mach-dreamcast/mach/sysasic.h>
62#endif 62#endif
63 63
64#ifdef CONFIG_SH_DMA 64#ifdef CONFIG_PVR2_DMA
65#include <linux/pagemap.h> 65#include <linux/pagemap.h>
66#include <mach/dma.h> 66#include <mach/dma.h>
67#include <asm/dma.h> 67#include <asm/dma.h>
@@ -188,7 +188,7 @@ static unsigned int is_blanked = 0; /* Is the screen blanked? */
188static unsigned long pvr2fb_map; 188static unsigned long pvr2fb_map;
189#endif 189#endif
190 190
191#ifdef CONFIG_SH_DMA 191#ifdef CONFIG_PVR2_DMA
192static unsigned int shdma = PVR2_CASCADE_CHAN; 192static unsigned int shdma = PVR2_CASCADE_CHAN;
193static unsigned int pvr2dma = ONCHIP_NR_DMA_CHANNELS; 193static unsigned int pvr2dma = ONCHIP_NR_DMA_CHANNELS;
194#endif 194#endif
@@ -207,7 +207,7 @@ static irqreturn_t pvr2fb_interrupt(int irq, void *dev_id);
207static int pvr2_init_cable(void); 207static int pvr2_init_cable(void);
208static int pvr2_get_param(const struct pvr2_params *p, const char *s, 208static int pvr2_get_param(const struct pvr2_params *p, const char *s,
209 int val, int size); 209 int val, int size);
210#ifdef CONFIG_SH_DMA 210#ifdef CONFIG_PVR2_DMA
211static ssize_t pvr2fb_write(struct fb_info *info, const char *buf, 211static ssize_t pvr2fb_write(struct fb_info *info, const char *buf,
212 size_t count, loff_t *ppos); 212 size_t count, loff_t *ppos);
213#endif 213#endif
@@ -218,7 +218,7 @@ static struct fb_ops pvr2fb_ops = {
218 .fb_blank = pvr2fb_blank, 218 .fb_blank = pvr2fb_blank,
219 .fb_check_var = pvr2fb_check_var, 219 .fb_check_var = pvr2fb_check_var,
220 .fb_set_par = pvr2fb_set_par, 220 .fb_set_par = pvr2fb_set_par,
221#ifdef CONFIG_SH_DMA 221#ifdef CONFIG_PVR2_DMA
222 .fb_write = pvr2fb_write, 222 .fb_write = pvr2fb_write,
223#endif 223#endif
224 .fb_fillrect = cfb_fillrect, 224 .fb_fillrect = cfb_fillrect,
@@ -671,7 +671,7 @@ static int pvr2_init_cable(void)
671 return cable_type; 671 return cable_type;
672} 672}
673 673
674#ifdef CONFIG_SH_DMA 674#ifdef CONFIG_PVR2_DMA
675static ssize_t pvr2fb_write(struct fb_info *info, const char *buf, 675static ssize_t pvr2fb_write(struct fb_info *info, const char *buf,
676 size_t count, loff_t *ppos) 676 size_t count, loff_t *ppos)
677{ 677{
@@ -743,7 +743,7 @@ out_unmap:
743 743
744 return ret; 744 return ret;
745} 745}
746#endif /* CONFIG_SH_DMA */ 746#endif /* CONFIG_PVR2_DMA */
747 747
748/** 748/**
749 * pvr2fb_common_init 749 * pvr2fb_common_init
@@ -893,7 +893,7 @@ static int __init pvr2fb_dc_init(void)
893 return -EBUSY; 893 return -EBUSY;
894 } 894 }
895 895
896#ifdef CONFIG_SH_DMA 896#ifdef CONFIG_PVR2_DMA
897 if (request_dma(pvr2dma, "pvr2") != 0) { 897 if (request_dma(pvr2dma, "pvr2") != 0) {
898 free_irq(HW_EVENT_VSYNC, 0); 898 free_irq(HW_EVENT_VSYNC, 0);
899 return -EBUSY; 899 return -EBUSY;
@@ -915,7 +915,7 @@ static void __exit pvr2fb_dc_exit(void)
915 } 915 }
916 916
917 free_irq(HW_EVENT_VSYNC, 0); 917 free_irq(HW_EVENT_VSYNC, 0);
918#ifdef CONFIG_SH_DMA 918#ifdef CONFIG_PVR2_DMA
919 free_dma(pvr2dma); 919 free_dma(pvr2dma);
920#endif 920#endif
921} 921}
diff --git a/drivers/video/sh_mobile_lcdcfb.c b/drivers/video/sh_mobile_lcdcfb.c
index 2c5d069e5f06..b433b8ac76d9 100644
--- a/drivers/video/sh_mobile_lcdcfb.c
+++ b/drivers/video/sh_mobile_lcdcfb.c
@@ -33,6 +33,8 @@ struct sh_mobile_lcdc_chan {
33 struct fb_info info; 33 struct fb_info info;
34 dma_addr_t dma_handle; 34 dma_addr_t dma_handle;
35 struct fb_deferred_io defio; 35 struct fb_deferred_io defio;
36 unsigned long frame_end;
37 wait_queue_head_t frame_end_wait;
36}; 38};
37 39
38struct sh_mobile_lcdc_priv { 40struct sh_mobile_lcdc_priv {
@@ -226,7 +228,10 @@ static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
226static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data) 228static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
227{ 229{
228 struct sh_mobile_lcdc_priv *priv = data; 230 struct sh_mobile_lcdc_priv *priv = data;
231 struct sh_mobile_lcdc_chan *ch;
229 unsigned long tmp; 232 unsigned long tmp;
233 int is_sub;
234 int k;
230 235
231 /* acknowledge interrupt */ 236 /* acknowledge interrupt */
232 tmp = lcdc_read(priv, _LDINTR); 237 tmp = lcdc_read(priv, _LDINTR);
@@ -234,8 +239,24 @@ static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
234 tmp |= 0x000000ff ^ LDINTR_FS; /* status in low 8 */ 239 tmp |= 0x000000ff ^ LDINTR_FS; /* status in low 8 */
235 lcdc_write(priv, _LDINTR, tmp); 240 lcdc_write(priv, _LDINTR, tmp);
236 241
237 /* disable clocks */ 242 /* figure out if this interrupt is for main or sub lcd */
238 sh_mobile_lcdc_clk_off(priv); 243 is_sub = (lcdc_read(priv, _LDSR) & (1 << 10)) ? 1 : 0;
244
245 /* wake up channel and disable clocks*/
246 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
247 ch = &priv->ch[k];
248
249 if (!ch->enabled)
250 continue;
251
252 if (is_sub == lcdc_chan_is_sublcd(ch)) {
253 ch->frame_end = 1;
254 wake_up(&ch->frame_end_wait);
255
256 sh_mobile_lcdc_clk_off(priv);
257 }
258 }
259
239 return IRQ_HANDLED; 260 return IRQ_HANDLED;
240} 261}
241 262
@@ -448,18 +469,27 @@ static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
448 struct sh_mobile_lcdc_board_cfg *board_cfg; 469 struct sh_mobile_lcdc_board_cfg *board_cfg;
449 int k; 470 int k;
450 471
451 /* tell the board code to disable the panel */ 472 /* clean up deferred io and ask board code to disable panel */
452 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { 473 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
453 ch = &priv->ch[k]; 474 ch = &priv->ch[k];
454 board_cfg = &ch->cfg.board_cfg;
455 if (board_cfg->display_off)
456 board_cfg->display_off(board_cfg->board_data);
457 475
458 /* cleanup deferred io if enabled */ 476 /* deferred io mode:
477 * flush frame, and wait for frame end interrupt
478 * clean up deferred io and enable clock
479 */
459 if (ch->info.fbdefio) { 480 if (ch->info.fbdefio) {
481 ch->frame_end = 0;
482 schedule_delayed_work(&ch->info.deferred_work, 0);
483 wait_event(ch->frame_end_wait, ch->frame_end);
460 fb_deferred_io_cleanup(&ch->info); 484 fb_deferred_io_cleanup(&ch->info);
461 ch->info.fbdefio = NULL; 485 ch->info.fbdefio = NULL;
486 sh_mobile_lcdc_clk_on(priv);
462 } 487 }
488
489 board_cfg = &ch->cfg.board_cfg;
490 if (board_cfg->display_off)
491 board_cfg->display_off(board_cfg->board_data);
492
463 } 493 }
464 494
465 /* stop the lcdc */ 495 /* stop the lcdc */
@@ -652,6 +682,26 @@ static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
652 return 0; 682 return 0;
653} 683}
654 684
685static int sh_mobile_lcdc_suspend(struct device *dev)
686{
687 struct platform_device *pdev = to_platform_device(dev);
688
689 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
690 return 0;
691}
692
693static int sh_mobile_lcdc_resume(struct device *dev)
694{
695 struct platform_device *pdev = to_platform_device(dev);
696
697 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
698}
699
700static struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
701 .suspend = sh_mobile_lcdc_suspend,
702 .resume = sh_mobile_lcdc_resume,
703};
704
655static int sh_mobile_lcdc_remove(struct platform_device *pdev); 705static int sh_mobile_lcdc_remove(struct platform_device *pdev);
656 706
657static int __init sh_mobile_lcdc_probe(struct platform_device *pdev) 707static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
@@ -707,6 +757,7 @@ static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
707 dev_err(&pdev->dev, "unsupported interface type\n"); 757 dev_err(&pdev->dev, "unsupported interface type\n");
708 goto err1; 758 goto err1;
709 } 759 }
760 init_waitqueue_head(&priv->ch[i].frame_end_wait);
710 761
711 switch (pdata->ch[i].chan) { 762 switch (pdata->ch[i].chan) {
712 case LCDC_CHAN_MAINLCD: 763 case LCDC_CHAN_MAINLCD:
@@ -860,6 +911,7 @@ static struct platform_driver sh_mobile_lcdc_driver = {
860 .driver = { 911 .driver = {
861 .name = "sh_mobile_lcdc_fb", 912 .name = "sh_mobile_lcdc_fb",
862 .owner = THIS_MODULE, 913 .owner = THIS_MODULE,
914 .pm = &sh_mobile_lcdc_dev_pm_ops,
863 }, 915 },
864 .probe = sh_mobile_lcdc_probe, 916 .probe = sh_mobile_lcdc_probe,
865 .remove = sh_mobile_lcdc_remove, 917 .remove = sh_mobile_lcdc_remove,
diff --git a/include/linux/maple.h b/include/linux/maple.h
index c23d3f51ba40..d9a51b9b3300 100644
--- a/include/linux/maple.h
+++ b/include/linux/maple.h
@@ -8,33 +8,49 @@ extern struct bus_type maple_bus_type;
8 8
9/* Maple Bus command and response codes */ 9/* Maple Bus command and response codes */
10enum maple_code { 10enum maple_code {
11 MAPLE_RESPONSE_FILEERR = -5, 11 MAPLE_RESPONSE_FILEERR = -5,
12 MAPLE_RESPONSE_AGAIN = -4, /* request should be retransmitted */ 12 MAPLE_RESPONSE_AGAIN, /* retransmit */
13 MAPLE_RESPONSE_BADCMD = -3, 13 MAPLE_RESPONSE_BADCMD,
14 MAPLE_RESPONSE_BADFUNC = -2, 14 MAPLE_RESPONSE_BADFUNC,
15 MAPLE_RESPONSE_NONE = -1, /* unit didn't respond at all */ 15 MAPLE_RESPONSE_NONE, /* unit didn't respond*/
16 MAPLE_COMMAND_DEVINFO = 1, 16 MAPLE_COMMAND_DEVINFO = 1,
17 MAPLE_COMMAND_ALLINFO = 2, 17 MAPLE_COMMAND_ALLINFO,
18 MAPLE_COMMAND_RESET = 3, 18 MAPLE_COMMAND_RESET,
19 MAPLE_COMMAND_KILL = 4, 19 MAPLE_COMMAND_KILL,
20 MAPLE_RESPONSE_DEVINFO = 5, 20 MAPLE_RESPONSE_DEVINFO,
21 MAPLE_RESPONSE_ALLINFO = 6, 21 MAPLE_RESPONSE_ALLINFO,
22 MAPLE_RESPONSE_OK = 7, 22 MAPLE_RESPONSE_OK,
23 MAPLE_RESPONSE_DATATRF = 8, 23 MAPLE_RESPONSE_DATATRF,
24 MAPLE_COMMAND_GETCOND = 9, 24 MAPLE_COMMAND_GETCOND,
25 MAPLE_COMMAND_GETMINFO = 10, 25 MAPLE_COMMAND_GETMINFO,
26 MAPLE_COMMAND_BREAD = 11, 26 MAPLE_COMMAND_BREAD,
27 MAPLE_COMMAND_BWRITE = 12, 27 MAPLE_COMMAND_BWRITE,
28 MAPLE_COMMAND_SETCOND = 14 28 MAPLE_COMMAND_BSYNC,
29 MAPLE_COMMAND_SETCOND,
30 MAPLE_COMMAND_MICCONTROL
31};
32
33enum maple_file_errors {
34 MAPLE_FILEERR_INVALID_PARTITION = 0x01000000,
35 MAPLE_FILEERR_PHASE_ERROR = 0x02000000,
36 MAPLE_FILEERR_INVALID_BLOCK = 0x04000000,
37 MAPLE_FILEERR_WRITE_ERROR = 0x08000000,
38 MAPLE_FILEERR_INVALID_WRITE_LENGTH = 0x10000000,
39 MAPLE_FILEERR_BAD_CRC = 0x20000000
40};
41
42struct maple_buffer {
43 char bufx[0x400];
44 void *buf;
29}; 45};
30 46
31struct mapleq { 47struct mapleq {
32 struct list_head list; 48 struct list_head list;
33 struct maple_device *dev; 49 struct maple_device *dev;
34 void *sendbuf, *recvbuf, *recvbufdcsp; 50 struct maple_buffer *recvbuf;
51 void *sendbuf, *recvbuf_p2;
35 unsigned char length; 52 unsigned char length;
36 enum maple_code command; 53 enum maple_code command;
37 struct mutex mutex;
38}; 54};
39 55
40struct maple_devinfo { 56struct maple_devinfo {
@@ -52,11 +68,15 @@ struct maple_device {
52 struct maple_driver *driver; 68 struct maple_driver *driver;
53 struct mapleq *mq; 69 struct mapleq *mq;
54 void (*callback) (struct mapleq * mq); 70 void (*callback) (struct mapleq * mq);
71 void (*fileerr_handler)(struct maple_device *mdev, void *recvbuf);
72 int (*can_unload)(struct maple_device *mdev);
55 unsigned long when, interval, function; 73 unsigned long when, interval, function;
56 struct maple_devinfo devinfo; 74 struct maple_devinfo devinfo;
57 unsigned char port, unit; 75 unsigned char port, unit;
58 char product_name[32]; 76 char product_name[32];
59 char product_licence[64]; 77 char product_licence[64];
78 atomic_t busy;
79 wait_queue_head_t maple_wait;
60 struct device dev; 80 struct device dev;
61}; 81};
62 82
@@ -72,7 +92,7 @@ void maple_getcond_callback(struct maple_device *dev,
72int maple_driver_register(struct maple_driver *); 92int maple_driver_register(struct maple_driver *);
73void maple_driver_unregister(struct maple_driver *); 93void maple_driver_unregister(struct maple_driver *);
74 94
75int maple_add_packet_sleeps(struct maple_device *mdev, u32 function, 95int maple_add_packet(struct maple_device *mdev, u32 function,
76 u32 command, u32 length, void *data); 96 u32 command, u32 length, void *data);
77void maple_clear_dev(struct maple_device *mdev); 97void maple_clear_dev(struct maple_device *mdev);
78 98
diff --git a/include/linux/sh_cmt.h b/include/linux/sh_cmt.h
new file mode 100644
index 000000000000..68cacde5954f
--- /dev/null
+++ b/include/linux/sh_cmt.h
@@ -0,0 +1,13 @@
1#ifndef __SH_CMT_H__
2#define __SH_CMT_H__
3
4struct sh_cmt_config {
5 char *name;
6 unsigned long channel_offset;
7 int timer_bit;
8 char *clk;
9 unsigned long clockevent_rating;
10 unsigned long clocksource_rating;
11};
12
13#endif /* __SH_CMT_H__ */
diff --git a/include/linux/sh_intc.h b/include/linux/sh_intc.h
index 68e212ff9dde..eb1423a0078d 100644
--- a/include/linux/sh_intc.h
+++ b/include/linux/sh_intc.h
@@ -85,6 +85,7 @@ struct intc_desc symbol __initdata = { \
85} 85}
86#endif 86#endif
87 87
88unsigned int intc_evt2irq(unsigned int vector);
88void __init register_intc_controller(struct intc_desc *desc); 89void __init register_intc_controller(struct intc_desc *desc);
89int intc_set_priority(unsigned int irq, unsigned int prio); 90int intc_set_priority(unsigned int irq, unsigned int prio);
90 91
diff --git a/sound/sh/Kconfig b/sound/sh/Kconfig
index cfc143985802..aed0f90c3919 100644
--- a/sound/sh/Kconfig
+++ b/sound/sh/Kconfig
@@ -15,6 +15,7 @@ config SND_AICA
15 tristate "Dreamcast Yamaha AICA sound" 15 tristate "Dreamcast Yamaha AICA sound"
16 depends on SH_DREAMCAST 16 depends on SH_DREAMCAST
17 select SND_PCM 17 select SND_PCM
18 select G2_DMA
18 help 19 help
19 ALSA Sound driver for the SEGA Dreamcast console. 20 ALSA Sound driver for the SEGA Dreamcast console.
20 21
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 03:53:28 -0500