diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2005-04-17 10:36:55 -0400 |
---|---|---|
committer | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2005-04-17 10:36:55 -0400 |
commit | 336eb02b9171d132a9abe575317fee4cca965af4 (patch) | |
tree | bcdd3c61fa4341a20de81dafdfd681d8872f0eb9 | |
parent | a757e64cfa400391041ed7953f0290c34a820c93 (diff) |
[PATCH] ARM: footbridge rtc init
The footbridge ISA RTC was being initialised before we had setup the
kernel timer. This caused a divide by zero error when the current
time of day is set. Resolve this by initialising the RTC after
the kernel timer has been initialised.
Signed-off-by: Russell King <rmk@arm.linux.org.uk>
-rw-r--r-- | arch/arm/mach-footbridge/dc21285-timer.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c index 580e1d4bce08..da5b9b7623ca 100644 --- a/arch/arm/mach-footbridge/dc21285-timer.c +++ b/arch/arm/mach-footbridge/dc21285-timer.c | |||
@@ -51,8 +51,6 @@ static struct irqaction footbridge_timer_irq = { | |||
51 | */ | 51 | */ |
52 | static void __init footbridge_timer_init(void) | 52 | static void __init footbridge_timer_init(void) |
53 | { | 53 | { |
54 | isa_rtc_init(); | ||
55 | |||
56 | timer1_latch = (mem_fclk_21285 + 8 * HZ) / (16 * HZ); | 54 | timer1_latch = (mem_fclk_21285 + 8 * HZ) / (16 * HZ); |
57 | 55 | ||
58 | *CSR_TIMER1_CLR = 0; | 56 | *CSR_TIMER1_CLR = 0; |
@@ -60,6 +58,8 @@ static void __init footbridge_timer_init(void) | |||
60 | *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD | TIMER_CNTL_DIV16; | 58 | *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD | TIMER_CNTL_DIV16; |
61 | 59 | ||
62 | setup_irq(IRQ_TIMER1, &footbridge_timer_irq); | 60 | setup_irq(IRQ_TIMER1, &footbridge_timer_irq); |
61 | |||
62 | isa_rtc_init(); | ||
63 | } | 63 | } |
64 | 64 | ||
65 | struct sys_timer footbridge_timer = { | 65 | struct sys_timer footbridge_timer = { |