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authorYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>2007-09-13 10:51:26 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-10-11 18:46:04 -0400
commitd5ab1a6910fe850fa092888f210cf6c43136a7ab (patch)
tree142f9f35f0d9fc6e675caf42a1cd8a82b56aa8e9
parent718f05f6ddc171a90fb7a277be6f6f65b4ca82be (diff)
[MIPS] Add GT641xx IRQ routines.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/Kconfig4
-rw-r--r--arch/mips/cobalt/irq.c118
-rw-r--r--arch/mips/cobalt/rtc.c5
-rw-r--r--arch/mips/cobalt/serial.c7
-rw-r--r--arch/mips/cobalt/setup.c9
-rw-r--r--arch/mips/kernel/Makefile1
-rw-r--r--arch/mips/kernel/irq-gt641xx.c131
-rw-r--r--arch/mips/pci/fixup-cobalt.c23
-rw-r--r--include/asm-mips/irq_gt641xx.h60
-rw-r--r--include/asm-mips/mach-cobalt/cobalt.h26
-rw-r--r--include/asm-mips/mach-cobalt/irq.h58
11 files changed, 307 insertions, 135 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ebc7b4b45c84..90b409d06153 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -64,6 +64,7 @@ config MIPS_COBALT
64 select HW_HAS_PCI 64 select HW_HAS_PCI
65 select I8259 65 select I8259
66 select IRQ_CPU 66 select IRQ_CPU
67 select IRQ_GT641XX
67 select PCI_GT64XXX_PCI0 68 select PCI_GT64XXX_PCI0
68 select SYS_HAS_CPU_NEVADA 69 select SYS_HAS_CPU_NEVADA
69 select SYS_HAS_EARLY_PRINTK 70 select SYS_HAS_EARLY_PRINTK
@@ -806,6 +807,9 @@ config IRQ_MSP_CIC
806config IRQ_TXX9 807config IRQ_TXX9
807 bool 808 bool
808 809
810config IRQ_GT641XX
811 bool
812
809config MIPS_BOARDS_GEN 813config MIPS_BOARDS_GEN
810 bool 814 bool
811 815
diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c
index 48763cd10eaa..ac4fb912649d 100644
--- a/arch/mips/cobalt/irq.c
+++ b/arch/mips/cobalt/irq.c
@@ -15,104 +15,48 @@
15 15
16#include <asm/i8259.h> 16#include <asm/i8259.h>
17#include <asm/irq_cpu.h> 17#include <asm/irq_cpu.h>
18#include <asm/irq_gt641xx.h>
18#include <asm/gt64120.h> 19#include <asm/gt64120.h>
19 20
20#include <cobalt.h> 21#include <irq.h>
21
22/*
23 * We have two types of interrupts that we handle, ones that come in through
24 * the CPU interrupt lines, and ones that come in on the via chip. The CPU
25 * mappings are:
26 *
27 * 16 - Software interrupt 0 (unused) IE_SW0
28 * 17 - Software interrupt 1 (unused) IE_SW1
29 * 18 - Galileo chip (timer) IE_IRQ0
30 * 19 - Tulip 0 + NCR SCSI IE_IRQ1
31 * 20 - Tulip 1 IE_IRQ2
32 * 21 - 16550 UART IE_IRQ3
33 * 22 - VIA southbridge PIC IE_IRQ4
34 * 23 - unused IE_IRQ5
35 *
36 * The VIA chip is a master/slave 8259 setup and has the following interrupts:
37 *
38 * 8 - RTC
39 * 9 - PCI
40 * 14 - IDE0
41 * 15 - IDE1
42 */
43
44static inline void galileo_irq(void)
45{
46 unsigned int mask, pending, devfn;
47
48 mask = GT_READ(GT_INTRMASK_OFS);
49 pending = GT_READ(GT_INTRCAUSE_OFS) & mask;
50
51 if (pending & GT_INTR_T0EXP_MSK) {
52 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK);
53 do_IRQ(COBALT_GALILEO_IRQ);
54 } else if (pending & GT_INTR_RETRYCTR0_MSK) {
55 devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8;
56 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK);
57 printk(KERN_WARNING
58 "Galileo: PCI retry count exceeded (%02x.%u)\n",
59 PCI_SLOT(devfn), PCI_FUNC(devfn));
60 } else {
61 GT_WRITE(GT_INTRMASK_OFS, mask & ~pending);
62 printk(KERN_WARNING
63 "Galileo: masking unexpected interrupt %08x\n", pending);
64 }
65}
66
67static inline void via_pic_irq(void)
68{
69 int irq;
70
71 irq = i8259_irq();
72 if (irq >= 0)
73 do_IRQ(irq);
74}
75 22
76asmlinkage void plat_irq_dispatch(void) 23asmlinkage void plat_irq_dispatch(void)
77{ 24{
78 unsigned pending = read_c0_status() & read_c0_cause(); 25 unsigned pending = read_c0_status() & read_c0_cause() & ST0_IM;
26 int irq;
79 27
80 if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */ 28 if (pending & CAUSEF_IP2)
81 galileo_irq(); 29 gt641xx_irq_dispatch();
82 else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */ 30 else if (pending & CAUSEF_IP6) {
83 via_pic_irq(); 31 irq = i8259_irq();
84 else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */ 32 if (irq < 0)
85 do_IRQ(COBALT_CPU_IRQ + 3); 33 spurious_interrupt();
86 else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */ 34 else
87 do_IRQ(COBALT_CPU_IRQ + 4); 35 do_IRQ(irq);
88 else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */ 36 } else if (pending & CAUSEF_IP3)
89 do_IRQ(COBALT_CPU_IRQ + 5); 37 do_IRQ(MIPS_CPU_IRQ_BASE + 3);
90 else if (pending & CAUSEF_IP7) /* IRQ 23 */ 38 else if (pending & CAUSEF_IP4)
91 do_IRQ(COBALT_CPU_IRQ + 7); 39 do_IRQ(MIPS_CPU_IRQ_BASE + 4);
40 else if (pending & CAUSEF_IP5)
41 do_IRQ(MIPS_CPU_IRQ_BASE + 5);
42 else if (pending & CAUSEF_IP7)
43 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
44 else
45 spurious_interrupt();
92} 46}
93 47
94static struct irqaction irq_via = { 48static struct irqaction cascade = {
95 .handler = no_action, 49 .handler = no_action,
96 .mask = CPU_MASK_NONE, 50 .mask = CPU_MASK_NONE,
97 .name = "cascade" 51 .name = "cascade",
98}; 52};
99 53
100void __init arch_init_irq(void) 54void __init arch_init_irq(void)
101{ 55{
102 /* 56 mips_cpu_irq_init();
103 * Mask all Galileo interrupts. The Galileo 57 gt641xx_irq_init();
104 * handler is set in cobalt_timer_setup() 58 init_i8259_irqs();
105 */
106 GT_WRITE(GT_INTRMASK_OFS, 0);
107
108 init_i8259_irqs(); /* 0 ... 15 */
109 mips_cpu_irq_init(); /* 16 ... 23 */
110
111 /*
112 * Mask all cpu interrupts
113 * (except IE4, we already masked those at VIA level)
114 */
115 change_c0_status(ST0_IM, IE_IRQ4);
116 59
117 setup_irq(COBALT_VIA_IRQ, &irq_via); 60 setup_irq(GT641XX_CASCADE_IRQ, &cascade);
61 setup_irq(I8259_CASCADE_IRQ, &cascade);
118} 62}
diff --git a/arch/mips/cobalt/rtc.c b/arch/mips/cobalt/rtc.c
index 284daefc5c55..e70794b8bcba 100644
--- a/arch/mips/cobalt/rtc.c
+++ b/arch/mips/cobalt/rtc.c
@@ -20,6 +20,7 @@
20#include <linux/errno.h> 20#include <linux/errno.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/ioport.h> 22#include <linux/ioport.h>
23#include <linux/mc146818rtc.h>
23#include <linux/platform_device.h> 24#include <linux/platform_device.h>
24 25
25static struct resource cobalt_rtc_resource[] __initdata = { 26static struct resource cobalt_rtc_resource[] __initdata = {
@@ -29,8 +30,8 @@ static struct resource cobalt_rtc_resource[] __initdata = {
29 .flags = IORESOURCE_IO, 30 .flags = IORESOURCE_IO,
30 }, 31 },
31 { 32 {
32 .start = 8, 33 .start = RTC_IRQ,
33 .end = 8, 34 .end = RTC_IRQ,
34 .flags = IORESOURCE_IRQ, 35 .flags = IORESOURCE_IRQ,
35 }, 36 },
36}; 37};
diff --git a/arch/mips/cobalt/serial.c b/arch/mips/cobalt/serial.c
index 08e739704cc9..53b8d0d6da90 100644
--- a/arch/mips/cobalt/serial.c
+++ b/arch/mips/cobalt/serial.c
@@ -24,6 +24,7 @@
24#include <linux/serial_8250.h> 24#include <linux/serial_8250.h>
25 25
26#include <cobalt.h> 26#include <cobalt.h>
27#include <irq.h>
27 28
28static struct resource cobalt_uart_resource[] __initdata = { 29static struct resource cobalt_uart_resource[] __initdata = {
29 { 30 {
@@ -32,15 +33,15 @@ static struct resource cobalt_uart_resource[] __initdata = {
32 .flags = IORESOURCE_MEM, 33 .flags = IORESOURCE_MEM,
33 }, 34 },
34 { 35 {
35 .start = COBALT_SERIAL_IRQ, 36 .start = SERIAL_IRQ,
36 .end = COBALT_SERIAL_IRQ, 37 .end = SERIAL_IRQ,
37 .flags = IORESOURCE_IRQ, 38 .flags = IORESOURCE_IRQ,
38 }, 39 },
39}; 40};
40 41
41static struct plat_serial8250_port cobalt_serial8250_port[] = { 42static struct plat_serial8250_port cobalt_serial8250_port[] = {
42 { 43 {
43 .irq = COBALT_SERIAL_IRQ, 44 .irq = SERIAL_IRQ,
44 .uartclk = 18432000, 45 .uartclk = 18432000,
45 .iotype = UPIO_MEM, 46 .iotype = UPIO_MEM,
46 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, 47 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c
index 7abe45e78425..fc9cbb251edc 100644
--- a/arch/mips/cobalt/setup.c
+++ b/arch/mips/cobalt/setup.c
@@ -20,6 +20,7 @@
20#include <asm/gt64120.h> 20#include <asm/gt64120.h>
21 21
22#include <cobalt.h> 22#include <cobalt.h>
23#include <irq.h>
23 24
24extern void cobalt_machine_restart(char *command); 25extern void cobalt_machine_restart(char *command);
25extern void cobalt_machine_halt(void); 26extern void cobalt_machine_halt(void);
@@ -45,14 +46,10 @@ void __init plat_timer_setup(struct irqaction *irq)
45 /* Load timer value for HZ (TCLK is 50MHz) */ 46 /* Load timer value for HZ (TCLK is 50MHz) */
46 GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ); 47 GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
47 48
48 /* Enable timer */ 49 /* Enable timer0 */
49 GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); 50 GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
50 51
51 /* Register interrupt */ 52 setup_irq(GT641XX_TIMER0_IRQ, irq);
52 setup_irq(COBALT_GALILEO_IRQ, irq);
53
54 /* Enable interrupt */
55 GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));
56} 53}
57 54
58/* 55/*
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 2fd96d95a39c..7851b4b447d0 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o
51obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o 51obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o
52obj-$(CONFIG_MIPS_BOARDS_GEN) += irq-msc01.o 52obj-$(CONFIG_MIPS_BOARDS_GEN) += irq-msc01.o
53obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o 53obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o
54obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o
54 55
55obj-$(CONFIG_32BIT) += scall32-o32.o 56obj-$(CONFIG_32BIT) += scall32-o32.o
56obj-$(CONFIG_64BIT) += scall64-64.o 57obj-$(CONFIG_64BIT) += scall64-64.o
diff --git a/arch/mips/kernel/irq-gt641xx.c b/arch/mips/kernel/irq-gt641xx.c
new file mode 100644
index 000000000000..1b81b131f43c
--- /dev/null
+++ b/arch/mips/kernel/irq-gt641xx.c
@@ -0,0 +1,131 @@
1/*
2 * GT641xx IRQ routines.
3 *
4 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/hardirq.h>
21#include <linux/init.h>
22#include <linux/irq.h>
23#include <linux/spinlock.h>
24#include <linux/types.h>
25
26#include <asm/gt64120.h>
27
28#define GT641XX_IRQ_TO_BIT(irq) (1U << (irq - GT641XX_IRQ_BASE))
29
30static DEFINE_SPINLOCK(gt641xx_irq_lock);
31
32static void ack_gt641xx_irq(unsigned int irq)
33{
34 unsigned long flags;
35 u32 cause;
36
37 spin_lock_irqsave(&gt641xx_irq_lock, flags);
38 cause = GT_READ(GT_INTRCAUSE_OFS);
39 cause &= ~GT641XX_IRQ_TO_BIT(irq);
40 GT_WRITE(GT_INTRCAUSE_OFS, cause);
41 spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
42}
43
44static void mask_gt641xx_irq(unsigned int irq)
45{
46 unsigned long flags;
47 u32 mask;
48
49 spin_lock_irqsave(&gt641xx_irq_lock, flags);
50 mask = GT_READ(GT_INTRMASK_OFS);
51 mask &= ~GT641XX_IRQ_TO_BIT(irq);
52 GT_WRITE(GT_INTRMASK_OFS, mask);
53 spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
54}
55
56static void mask_ack_gt641xx_irq(unsigned int irq)
57{
58 unsigned long flags;
59 u32 cause, mask;
60
61 spin_lock_irqsave(&gt641xx_irq_lock, flags);
62 mask = GT_READ(GT_INTRMASK_OFS);
63 mask &= ~GT641XX_IRQ_TO_BIT(irq);
64 GT_WRITE(GT_INTRMASK_OFS, mask);
65
66 cause = GT_READ(GT_INTRCAUSE_OFS);
67 cause &= ~GT641XX_IRQ_TO_BIT(irq);
68 GT_WRITE(GT_INTRCAUSE_OFS, cause);
69 spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
70}
71
72static void unmask_gt641xx_irq(unsigned int irq)
73{
74 unsigned long flags;
75 u32 mask;
76
77 spin_lock_irqsave(&gt641xx_irq_lock, flags);
78 mask = GT_READ(GT_INTRMASK_OFS);
79 mask |= GT641XX_IRQ_TO_BIT(irq);
80 GT_WRITE(GT_INTRMASK_OFS, mask);
81 spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
82}
83
84static struct irq_chip gt641xx_irq_chip = {
85 .name = "GT641xx",
86 .ack = ack_gt641xx_irq,
87 .mask = mask_gt641xx_irq,
88 .mask_ack = mask_ack_gt641xx_irq,
89 .unmask = unmask_gt641xx_irq,
90};
91
92void gt641xx_irq_dispatch(void)
93{
94 u32 cause, mask;
95 int i;
96
97 cause = GT_READ(GT_INTRCAUSE_OFS);
98 mask = GT_READ(GT_INTRMASK_OFS);
99 cause &= mask;
100
101 /*
102 * bit0 : logical or of all the interrupt bits.
103 * bit30: logical or of bits[29:26,20:1].
104 * bit31: logical or of bits[25:1].
105 */
106 for (i = 1; i < 30; i++) {
107 if (cause & (1U << i)) {
108 do_IRQ(GT641XX_IRQ_BASE + i);
109 return;
110 }
111 }
112
113 atomic_inc(&irq_err_count);
114}
115
116void __init gt641xx_irq_init(void)
117{
118 int i;
119
120 GT_WRITE(GT_INTRMASK_OFS, 0);
121 GT_WRITE(GT_INTRCAUSE_OFS, 0);
122
123 /*
124 * bit0 : logical or of all the interrupt bits.
125 * bit30: logical or of bits[29:26,20:1].
126 * bit31: logical or of bits[25:1].
127 */
128 for (i = 1; i < 30; i++)
129 set_irq_chip_and_handler(GT641XX_IRQ_BASE + i,
130 &gt641xx_irq_chip, handle_level_irq);
131}
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 76b4f0ffb1e5..4eb5410f842a 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -18,6 +18,7 @@
18#include <asm/gt64120.h> 18#include <asm/gt64120.h>
19 19
20#include <cobalt.h> 20#include <cobalt.h>
21#include <irq.h>
21 22
22static void qube_raq_galileo_early_fixup(struct pci_dev *dev) 23static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
23{ 24{
@@ -132,29 +133,29 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
132 133
133static char irq_tab_qube1[] __initdata = { 134static char irq_tab_qube1[] __initdata = {
134 [COBALT_PCICONF_CPU] = 0, 135 [COBALT_PCICONF_CPU] = 0,
135 [COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ, 136 [COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ,
136 [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ, 137 [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
137 [COBALT_PCICONF_VIA] = 0, 138 [COBALT_PCICONF_VIA] = 0,
138 [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, 139 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
139 [COBALT_PCICONF_ETH1] = 0 140 [COBALT_PCICONF_ETH1] = 0
140}; 141};
141 142
142static char irq_tab_cobalt[] __initdata = { 143static char irq_tab_cobalt[] __initdata = {
143 [COBALT_PCICONF_CPU] = 0, 144 [COBALT_PCICONF_CPU] = 0,
144 [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ, 145 [COBALT_PCICONF_ETH0] = ETH0_IRQ,
145 [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ, 146 [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
146 [COBALT_PCICONF_VIA] = 0, 147 [COBALT_PCICONF_VIA] = 0,
147 [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, 148 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
148 [COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ 149 [COBALT_PCICONF_ETH1] = ETH1_IRQ
149}; 150};
150 151
151static char irq_tab_raq2[] __initdata = { 152static char irq_tab_raq2[] __initdata = {
152 [COBALT_PCICONF_CPU] = 0, 153 [COBALT_PCICONF_CPU] = 0,
153 [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ, 154 [COBALT_PCICONF_ETH0] = ETH0_IRQ,
154 [COBALT_PCICONF_RAQSCSI] = COBALT_RAQ_SCSI_IRQ, 155 [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
155 [COBALT_PCICONF_VIA] = 0, 156 [COBALT_PCICONF_VIA] = 0,
156 [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, 157 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
157 [COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ 158 [COBALT_PCICONF_ETH1] = ETH1_IRQ
158}; 159};
159 160
160int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 161int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
diff --git a/include/asm-mips/irq_gt641xx.h b/include/asm-mips/irq_gt641xx.h
new file mode 100644
index 000000000000..f9a7c3ac2e66
--- /dev/null
+++ b/include/asm-mips/irq_gt641xx.h
@@ -0,0 +1,60 @@
1/*
2 * Galileo/Marvell GT641xx IRQ definitions.
3 *
4 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#ifndef _ASM_IRQ_GT641XX_H
21#define _ASM_IRQ_GT641XX_H
22
23#ifndef GT641XX_IRQ_BASE
24#define GT641XX_IRQ_BASE 8
25#endif
26
27#define GT641XX_MEMORY_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 1)
28#define GT641XX_DMA_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 2)
29#define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 3)
30#define GT641XX_DMA0_IRQ (GT641XX_IRQ_BASE + 4)
31#define GT641XX_DMA1_IRQ (GT641XX_IRQ_BASE + 5)
32#define GT641XX_DMA2_IRQ (GT641XX_IRQ_BASE + 6)
33#define GT641XX_DMA3_IRQ (GT641XX_IRQ_BASE + 7)
34#define GT641XX_TIMER0_IRQ (GT641XX_IRQ_BASE + 8)
35#define GT641XX_TIMER1_IRQ (GT641XX_IRQ_BASE + 9)
36#define GT641XX_TIMER2_IRQ (GT641XX_IRQ_BASE + 10)
37#define GT641XX_TIMER3_IRQ (GT641XX_IRQ_BASE + 11)
38#define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 12)
39#define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 13)
40#define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 14)
41#define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 15)
42#define GT641XX_PCI_0_ADDRESS_ERROR_IRQ (GT641XX_IRQ_BASE + 16)
43#define GT641XX_MEMORY_ERROR_IRQ (GT641XX_IRQ_BASE + 17)
44#define GT641XX_PCI_0_MASTER_ABORT_IRQ (GT641XX_IRQ_BASE + 18)
45#define GT641XX_PCI_0_TARGET_ABORT_IRQ (GT641XX_IRQ_BASE + 19)
46#define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ (GT641XX_IRQ_BASE + 20)
47#define GT641XX_CPU_INT0_IRQ (GT641XX_IRQ_BASE + 21)
48#define GT641XX_CPU_INT1_IRQ (GT641XX_IRQ_BASE + 22)
49#define GT641XX_CPU_INT2_IRQ (GT641XX_IRQ_BASE + 23)
50#define GT641XX_CPU_INT3_IRQ (GT641XX_IRQ_BASE + 24)
51#define GT641XX_CPU_INT4_IRQ (GT641XX_IRQ_BASE + 25)
52#define GT641XX_PCI_INT0_IRQ (GT641XX_IRQ_BASE + 26)
53#define GT641XX_PCI_INT1_IRQ (GT641XX_IRQ_BASE + 27)
54#define GT641XX_PCI_INT2_IRQ (GT641XX_IRQ_BASE + 28)
55#define GT641XX_PCI_INT3_IRQ (GT641XX_IRQ_BASE + 29)
56
57extern void gt641xx_irq_dispatch(void);
58extern void gt641xx_irq_init(void);
59
60#endif /* _ASM_IRQ_GT641XX_H */
diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h
index 9c9d2b998ca4..408eeccbe512 100644
--- a/include/asm-mips/mach-cobalt/cobalt.h
+++ b/include/asm-mips/mach-cobalt/cobalt.h
@@ -12,32 +12,6 @@
12#ifndef __ASM_COBALT_H 12#ifndef __ASM_COBALT_H
13#define __ASM_COBALT_H 13#define __ASM_COBALT_H
14 14
15#include <irq.h>
16
17/*
18 * i8259 legacy interrupts used on Cobalt:
19 *
20 * 8 - RTC
21 * 9 - PCI
22 * 14 - IDE0
23 * 15 - IDE1
24 */
25#define COBALT_QUBE_SLOT_IRQ 9
26
27/*
28 * CPU IRQs are 16 ... 23
29 */
30#define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE
31
32#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2)
33#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3)
34#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3)
35#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4)
36#define COBALT_ETH1_IRQ (COBALT_CPU_IRQ + 4)
37#define COBALT_SERIAL_IRQ (COBALT_CPU_IRQ + 5)
38#define COBALT_SCSI_IRQ (COBALT_CPU_IRQ + 5)
39#define COBALT_VIA_IRQ (COBALT_CPU_IRQ + 6) /* Chained to VIA ISA bridge */
40
41/* 15/*
42 * PCI configuration space manifest constants. These are wired into 16 * PCI configuration space manifest constants. These are wired into
43 * the board layout according to the PCI spec to enable the software 17 * the board layout according to the PCI spec to enable the software
diff --git a/include/asm-mips/mach-cobalt/irq.h b/include/asm-mips/mach-cobalt/irq.h
new file mode 100644
index 000000000000..179d0e850b59
--- /dev/null
+++ b/include/asm-mips/mach-cobalt/irq.h
@@ -0,0 +1,58 @@
1/*
2 * Cobalt IRQ definitions.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1997 Cobalt Microserver
9 * Copyright (C) 1997, 2003 Ralf Baechle
10 * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv)
11 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
12 */
13#ifndef _ASM_COBALT_IRQ_H
14#define _ASM_COBALT_IRQ_H
15
16/*
17 * i8259 interrupts used on Cobalt:
18 *
19 * 8 - RTC
20 * 9 - PCI slot
21 * 14 - IDE0
22 * 15 - IDE1(no connector on board)
23 */
24#define I8259A_IRQ_BASE 0
25
26#define PCISLOT_IRQ (I8259A_IRQ_BASE + 9)
27
28/*
29 * CPU interrupts used on Cobalt:
30 *
31 * 0 - Software interrupt 0 (unused)
32 * 1 - Software interrupt 0 (unused)
33 * 2 - cascade GT64111
34 * 3 - ethernet or SCSI host controller
35 * 4 - ethernet
36 * 5 - 16550 UART
37 * 6 - cascade i8259
38 * 7 - CP0 counter (unused)
39 */
40#define MIPS_CPU_IRQ_BASE 16
41
42#define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2)
43#define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3)
44#define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3)
45#define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4)
46#define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4)
47#define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5)
48#define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5)
49#define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6)
50
51
52#define GT641XX_IRQ_BASE 24
53
54#include <asm/irq_gt641xx.h>
55
56#define NR_IRQS (GT641XX_PCI_INT3_IRQ + 1)
57
58#endif /* _ASM_COBALT_IRQ_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 11:25:53 -0500