diff options
| author | Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> | 2007-09-12 10:19:45 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 18:46:04 -0400 |
| commit | 718f05f6ddc171a90fb7a277be6f6f65b4ca82be (patch) | |
| tree | 0f742721dd06f438489e9bf2babb55413baaaf63 | |
| parent | d80c1c0b2207ba326b2c06249dfebddf8ac863bd (diff) | |
[MIPS] GT64120: Remove unused definitions
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | include/asm-mips/mach-mips/mach-gt64120.h | 9 | ||||
| -rw-r--r-- | include/asm-mips/mach-wrppmc/mach-gt64120.h | 1 |
2 files changed, 0 insertions, 10 deletions
diff --git a/include/asm-mips/mach-mips/mach-gt64120.h b/include/asm-mips/mach-mips/mach-gt64120.h index 511f7cf3a6be..0f863148f3b6 100644 --- a/include/asm-mips/mach-mips/mach-gt64120.h +++ b/include/asm-mips/mach-mips/mach-gt64120.h | |||
| @@ -16,13 +16,4 @@ extern unsigned long _pcictrl_gt64120; | |||
| 16 | */ | 16 | */ |
| 17 | #define GT64120_BASE _pcictrl_gt64120 | 17 | #define GT64120_BASE _pcictrl_gt64120 |
| 18 | 18 | ||
| 19 | /* | ||
| 20 | * PCI Bus allocation | ||
| 21 | */ | ||
| 22 | #define GT_PCI_MEM_BASE 0x12000000UL | ||
| 23 | #define GT_PCI_MEM_SIZE 0x02000000UL | ||
| 24 | #define GT_PCI_IO_BASE 0x10000000UL | ||
| 25 | #define GT_PCI_IO_SIZE 0x02000000UL | ||
| 26 | #define GT_ISA_IO_BASE PCI_IO_BASE | ||
| 27 | |||
| 28 | #endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */ | 19 | #endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */ |
diff --git a/include/asm-mips/mach-wrppmc/mach-gt64120.h b/include/asm-mips/mach-wrppmc/mach-gt64120.h index ba9205a04582..00d8bf6164a9 100644 --- a/include/asm-mips/mach-wrppmc/mach-gt64120.h +++ b/include/asm-mips/mach-wrppmc/mach-gt64120.h | |||
| @@ -43,7 +43,6 @@ | |||
| 43 | #define GT_PCI_MEM_SIZE 0x02000000UL | 43 | #define GT_PCI_MEM_SIZE 0x02000000UL |
| 44 | #define GT_PCI_IO_BASE 0x11000000UL | 44 | #define GT_PCI_IO_BASE 0x11000000UL |
| 45 | #define GT_PCI_IO_SIZE 0x02000000UL | 45 | #define GT_PCI_IO_SIZE 0x02000000UL |
| 46 | #define GT_ISA_IO_BASE PCI_IO_BASE | ||
| 47 | 46 | ||
| 48 | /* | 47 | /* |
| 49 | * PCI interrupts will come in on either the INTA or INTD interrups lines, | 48 | * PCI interrupts will come in on either the INTA or INTD interrups lines, |
