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authorRalf Baechle <ralf@linux-mips.org>2007-10-11 18:46:15 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-10-11 18:46:15 -0400
commit49a89efbbbcc178a39555c43bd59a7593c429664 (patch)
tree93ab78ec340d3f2fe23f9f853edd0bd62dcc64bb
parent10cc3529072d5415fb040018a8a99aa7a60190b6 (diff)
[MIPS] Fix "no space between function name and open parenthesis" warnings.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/au1000/common/dbdma.c2
-rw-r--r--arch/mips/au1000/common/reset.c2
-rw-r--r--arch/mips/au1000/common/time.c2
-rw-r--r--arch/mips/au1000/db1x00/board_setup.c2
-rw-r--r--arch/mips/au1000/db1x00/init.c6
-rw-r--r--arch/mips/au1000/mtx-1/board_setup.c2
-rw-r--r--arch/mips/au1000/pb1000/board_setup.c2
-rw-r--r--arch/mips/au1000/pb1100/board_setup.c2
-rw-r--r--arch/mips/au1000/pb1200/board_setup.c8
-rw-r--r--arch/mips/au1000/pb1500/board_setup.c2
-rw-r--r--arch/mips/au1000/pb1550/board_setup.c2
-rw-r--r--arch/mips/au1000/xxs1500/board_setup.c2
-rw-r--r--arch/mips/basler/excite/excite_setup.c12
-rw-r--r--arch/mips/boot/addinitrd.c52
-rw-r--r--arch/mips/fw/arc/memory.c6
-rw-r--r--arch/mips/jazz/reset.c4
-rw-r--r--arch/mips/jazz/setup.c6
-rw-r--r--arch/mips/kernel/cpu-bugs64.c2
-rw-r--r--arch/mips/kernel/gdb-stub.c4
-rw-r--r--arch/mips/kernel/i8259.c2
-rw-r--r--arch/mips/kernel/irixelf.c32
-rw-r--r--arch/mips/kernel/irixinv.c42
-rw-r--r--arch/mips/kernel/irixioctl.c2
-rw-r--r--arch/mips/kernel/irq-msc01.c4
-rw-r--r--arch/mips/kernel/kspd.c10
-rw-r--r--arch/mips/kernel/linux32.c14
-rw-r--r--arch/mips/kernel/mips-mt.c2
-rw-r--r--arch/mips/kernel/process.c4
-rw-r--r--arch/mips/kernel/ptrace.c50
-rw-r--r--arch/mips/kernel/ptrace32.c16
-rw-r--r--arch/mips/kernel/signal32.c44
-rw-r--r--arch/mips/kernel/signal_n32.c4
-rw-r--r--arch/mips/kernel/smp-mt.c2
-rw-r--r--arch/mips/kernel/smtc.c4
-rw-r--r--arch/mips/kernel/syscall.c58
-rw-r--r--arch/mips/kernel/sysirix.c20
-rw-r--r--arch/mips/kernel/time.c2
-rw-r--r--arch/mips/kernel/traps.c26
-rw-r--r--arch/mips/kernel/unaligned.c2
-rw-r--r--arch/mips/lib/ucmpdi2.c2
-rw-r--r--arch/mips/math-emu/cp1emu.c8
-rw-r--r--arch/mips/mips-boards/atlas/atlas_int.c22
-rw-r--r--arch/mips/mips-boards/atlas/atlas_setup.c2
-rw-r--r--arch/mips/mips-boards/generic/init.c12
-rw-r--r--arch/mips/mips-boards/generic/memory.c4
-rw-r--r--arch/mips/mips-boards/generic/pci.c2
-rw-r--r--arch/mips/mips-boards/generic/time.c6
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c34
-rw-r--r--arch/mips/mips-boards/malta/malta_setup.c10
-rw-r--r--arch/mips/mips-boards/sead/sead_int.c2
-rw-r--r--arch/mips/mips-boards/sead/sead_setup.c2
-rw-r--r--arch/mips/mipssim/sim_int.c2
-rw-r--r--arch/mips/mipssim/sim_mem.c4
-rw-r--r--arch/mips/mipssim/sim_time.c2
-rw-r--r--arch/mips/mm/c-r3k.c12
-rw-r--r--arch/mips/mm/sc-mips.c2
-rw-r--r--arch/mips/mm/tlb-r4k.c2
-rw-r--r--arch/mips/oprofile/op_model_mipsxx.c2
-rw-r--r--arch/mips/oprofile/op_model_rm9000.c2
-rw-r--r--arch/mips/pci/fixup-atlas.c6
-rw-r--r--arch/mips/pci/ops-au1000.c2
-rw-r--r--arch/mips/pci/ops-sni.c22
-rw-r--r--arch/mips/philips/pnx8550/common/proc.c4
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_usb.c8
-rw-r--r--arch/mips/qemu/q-firmware.c2
-rw-r--r--arch/mips/sgi-ip22/ip22-eisa.c2
-rw-r--r--arch/mips/sgi-ip22/ip22-int.c2
-rw-r--r--arch/mips/sgi-ip32/crime.c6
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c26
-rw-r--r--arch/mips/sgi-ip32/ip32-memory.c4
-rw-r--r--arch/mips/sibyte/common/sb_tbprof.c4
-rw-r--r--arch/mips/sni/a20r.c6
-rw-r--r--arch/mips/sni/pcimt.c4
-rw-r--r--arch/mips/sni/pcit.c26
-rw-r--r--arch/mips/sni/rm200.c10
-rw-r--r--arch/mips/sni/setup.c6
-rw-r--r--arch/mips/sni/sniprom.c6
-rw-r--r--arch/mips/sni/time.c16
-rw-r--r--include/asm-mips/asmmacro.h12
-rw-r--r--include/asm-mips/bitops.h12
-rw-r--r--include/asm-mips/byteorder.h4
-rw-r--r--include/asm-mips/elf.h2
-rw-r--r--include/asm-mips/fixmap.h4
-rw-r--r--include/asm-mips/futex.h2
-rw-r--r--include/asm-mips/inventory.h4
-rw-r--r--include/asm-mips/irqflags.h10
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h622
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_ide.h2
-rw-r--r--include/asm-mips/mach-ip32/kmalloc.h2
-rw-r--r--include/asm-mips/mach-pb1x00/pb1000.h56
-rw-r--r--include/asm-mips/mach-pb1x00/pb1100.h60
-rw-r--r--include/asm-mips/mach-pnx8550/kernel-entry-init.h24
-rw-r--r--include/asm-mips/parport.h6
-rw-r--r--include/asm-mips/prctl.h2
-rw-r--r--include/asm-mips/semaphore.h6
-rw-r--r--include/asm-mips/sim.h4
-rw-r--r--include/asm-mips/sn/addrs.h44
-rw-r--r--include/asm-mips/sn/io.h2
-rw-r--r--include/asm-mips/sn/kldir.h2
-rw-r--r--include/asm-mips/sn/sn0/addrs.h8
-rw-r--r--include/asm-mips/sni.h18
-rw-r--r--include/asm-mips/system.h6
-rw-r--r--include/asm-mips/timex.h2
-rw-r--r--include/asm-mips/uaccess.h18
104 files changed, 845 insertions, 845 deletions
diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/au1000/common/dbdma.c
index 626de44bd888..d15b047d480d 100644
--- a/arch/mips/au1000/common/dbdma.c
+++ b/arch/mips/au1000/common/dbdma.c
@@ -184,7 +184,7 @@ static dbdev_tab_t dbdev_tab[] = {
184static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; 184static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
185 185
186static dbdev_tab_t * 186static dbdev_tab_t *
187find_dbdev_id (u32 id) 187find_dbdev_id(u32 id)
188{ 188{
189 int i; 189 int i;
190 dbdev_tab_t *p; 190 dbdev_tab_t *p;
diff --git a/arch/mips/au1000/common/reset.c b/arch/mips/au1000/common/reset.c
index de5447e83849..b8638d293cf9 100644
--- a/arch/mips/au1000/common/reset.c
+++ b/arch/mips/au1000/common/reset.c
@@ -42,7 +42,7 @@ extern void (*flush_cache_all)(void);
42void au1000_restart(char *command) 42void au1000_restart(char *command)
43{ 43{
44 /* Set all integrated peripherals to disabled states */ 44 /* Set all integrated peripherals to disabled states */
45 extern void board_reset (void); 45 extern void board_reset(void);
46 u32 prid = read_c0_prid(); 46 u32 prid = read_c0_prid();
47 47
48 printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n"); 48 printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n");
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index 726c340460b6..2556399708ba 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -200,7 +200,7 @@ unsigned long cal_r4koff(void)
200 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); 200 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
201 201
202 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); 202 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
203 au_writel (0, SYS_TOYWRITE); 203 au_writel(0, SYS_TOYWRITE);
204 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); 204 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
205 205
206 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * 206 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
diff --git a/arch/mips/au1000/db1x00/board_setup.c b/arch/mips/au1000/db1x00/board_setup.c
index 8b08edb977be..99eafeada518 100644
--- a/arch/mips/au1000/db1x00/board_setup.c
+++ b/arch/mips/au1000/db1x00/board_setup.c
@@ -46,7 +46,7 @@
46 46
47static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; 47static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
48 48
49void board_reset (void) 49void board_reset(void)
50{ 50{
51 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 51 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
52 bcsr->swreset = 0x0000; 52 bcsr->swreset = 0x0000;
diff --git a/arch/mips/au1000/db1x00/init.c b/arch/mips/au1000/db1x00/init.c
index e6bdd07cc093..4d7bcfc8cf73 100644
--- a/arch/mips/au1000/db1x00/init.c
+++ b/arch/mips/au1000/db1x00/init.c
@@ -60,11 +60,11 @@ void __init prom_init(void)
60 prom_envp = (char **) fw_arg2; 60 prom_envp = (char **) fw_arg2;
61 61
62 /* Set the platform # */ 62 /* Set the platform # */
63#if defined (CONFIG_MIPS_DB1550) 63#if defined(CONFIG_MIPS_DB1550)
64 mips_machtype = MACH_DB1550; 64 mips_machtype = MACH_DB1550;
65#elif defined (CONFIG_MIPS_DB1500) 65#elif defined(CONFIG_MIPS_DB1500)
66 mips_machtype = MACH_DB1500; 66 mips_machtype = MACH_DB1500;
67#elif defined (CONFIG_MIPS_DB1100) 67#elif defined(CONFIG_MIPS_DB1100)
68 mips_machtype = MACH_DB1100; 68 mips_machtype = MACH_DB1100;
69#else 69#else
70 mips_machtype = MACH_DB1000; 70 mips_machtype = MACH_DB1000;
diff --git a/arch/mips/au1000/mtx-1/board_setup.c b/arch/mips/au1000/mtx-1/board_setup.c
index 2c460c116570..abfc4bcddf7a 100644
--- a/arch/mips/au1000/mtx-1/board_setup.c
+++ b/arch/mips/au1000/mtx-1/board_setup.c
@@ -46,7 +46,7 @@
46extern int (*board_pci_idsel)(unsigned int devsel, int assert); 46extern int (*board_pci_idsel)(unsigned int devsel, int assert);
47int mtx1_pci_idsel(unsigned int devsel, int assert); 47int mtx1_pci_idsel(unsigned int devsel, int assert);
48 48
49void board_reset (void) 49void board_reset(void)
50{ 50{
51 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 51 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
52 au_writel(0x00000000, 0xAE00001C); 52 au_writel(0x00000000, 0xAE00001C);
diff --git a/arch/mips/au1000/pb1000/board_setup.c b/arch/mips/au1000/pb1000/board_setup.c
index 0aed89114bfc..5198c4f98b43 100644
--- a/arch/mips/au1000/pb1000/board_setup.c
+++ b/arch/mips/au1000/pb1000/board_setup.c
@@ -39,7 +39,7 @@
39#include <asm/mach-au1x00/au1000.h> 39#include <asm/mach-au1x00/au1000.h>
40#include <asm/mach-pb1x00/pb1000.h> 40#include <asm/mach-pb1x00/pb1000.h>
41 41
42void board_reset (void) 42void board_reset(void)
43{ 43{
44} 44}
45 45
diff --git a/arch/mips/au1000/pb1100/board_setup.c b/arch/mips/au1000/pb1100/board_setup.c
index 259ca05860c3..42874a6b31d1 100644
--- a/arch/mips/au1000/pb1100/board_setup.c
+++ b/arch/mips/au1000/pb1100/board_setup.c
@@ -39,7 +39,7 @@
39#include <asm/mach-au1x00/au1000.h> 39#include <asm/mach-au1x00/au1000.h>
40#include <asm/mach-pb1x00/pb1100.h> 40#include <asm/mach-pb1x00/pb1100.h>
41 41
42void board_reset (void) 42void board_reset(void)
43{ 43{
44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
45 au_writel(0x00000000, 0xAE00001C); 45 au_writel(0x00000000, 0xAE00001C);
diff --git a/arch/mips/au1000/pb1200/board_setup.c b/arch/mips/au1000/pb1200/board_setup.c
index eea2092bde8d..2122515f79d7 100644
--- a/arch/mips/au1000/pb1200/board_setup.c
+++ b/arch/mips/au1000/pb1200/board_setup.c
@@ -57,7 +57,7 @@
57extern void _board_init_irq(void); 57extern void _board_init_irq(void);
58extern void (*board_init_irq)(void); 58extern void (*board_init_irq)(void);
59 59
60void board_reset (void) 60void board_reset(void)
61{ 61{
62 bcsr->resets = 0; 62 bcsr->resets = 0;
63 bcsr->system = 0; 63 bcsr->system = 0;
@@ -148,7 +148,7 @@ void __init board_setup(void)
148} 148}
149 149
150int 150int
151board_au1200fb_panel (void) 151board_au1200fb_panel(void)
152{ 152{
153 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; 153 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
154 int p; 154 int p;
@@ -160,7 +160,7 @@ board_au1200fb_panel (void)
160} 160}
161 161
162int 162int
163board_au1200fb_panel_init (void) 163board_au1200fb_panel_init(void)
164{ 164{
165 /* Apply power */ 165 /* Apply power */
166 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; 166 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
@@ -170,7 +170,7 @@ board_au1200fb_panel_init (void)
170} 170}
171 171
172int 172int
173board_au1200fb_panel_shutdown (void) 173board_au1200fb_panel_shutdown(void)
174{ 174{
175 /* Remove power */ 175 /* Remove power */
176 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; 176 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
diff --git a/arch/mips/au1000/pb1500/board_setup.c b/arch/mips/au1000/pb1500/board_setup.c
index a2d850db8902..5446836869d6 100644
--- a/arch/mips/au1000/pb1500/board_setup.c
+++ b/arch/mips/au1000/pb1500/board_setup.c
@@ -39,7 +39,7 @@
39#include <asm/mach-au1x00/au1000.h> 39#include <asm/mach-au1x00/au1000.h>
40#include <asm/mach-pb1x00/pb1500.h> 40#include <asm/mach-pb1x00/pb1500.h>
41 41
42void board_reset (void) 42void board_reset(void)
43{ 43{
44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
45 au_writel(0x00000000, 0xAE00001C); 45 au_writel(0x00000000, 0xAE00001C);
diff --git a/arch/mips/au1000/pb1550/board_setup.c b/arch/mips/au1000/pb1550/board_setup.c
index 05fd27dc24e6..e3cfb0d73180 100644
--- a/arch/mips/au1000/pb1550/board_setup.c
+++ b/arch/mips/au1000/pb1550/board_setup.c
@@ -44,7 +44,7 @@
44#include <asm/mach-au1x00/au1000.h> 44#include <asm/mach-au1x00/au1000.h>
45#include <asm/mach-pb1x00/pb1550.h> 45#include <asm/mach-pb1x00/pb1550.h>
46 46
47void board_reset (void) 47void board_reset(void)
48{ 48{
49 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 49 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
50 au_writew(au_readw(0xAF00001C) & ~(1<<15), 0xAF00001C); 50 au_writew(au_readw(0xAF00001C) & ~(1<<15), 0xAF00001C);
diff --git a/arch/mips/au1000/xxs1500/board_setup.c b/arch/mips/au1000/xxs1500/board_setup.c
index ae3d6b19e94d..a9237f41933d 100644
--- a/arch/mips/au1000/xxs1500/board_setup.c
+++ b/arch/mips/au1000/xxs1500/board_setup.c
@@ -39,7 +39,7 @@
39#include <asm/pgtable.h> 39#include <asm/pgtable.h>
40#include <asm/au1000.h> 40#include <asm/au1000.h>
41 41
42void board_reset (void) 42void board_reset(void)
43{ 43{
44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
45 au_writel(0x00000000, 0xAE00001C); 45 au_writel(0x00000000, 0xAE00001C);
diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c
index 68be19d1802e..404ca9284b30 100644
--- a/arch/mips/basler/excite/excite_setup.c
+++ b/arch/mips/basler/excite/excite_setup.c
@@ -216,7 +216,7 @@ static int __init excite_platform_init(void)
216 titan_writel(0x80021dff, GXCFG); /* XDMA reset */ 216 titan_writel(0x80021dff, GXCFG); /* XDMA reset */
217 titan_writel(0x00000000, CPXCISRA); 217 titan_writel(0x00000000, CPXCISRA);
218 titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */ 218 titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */
219#if defined (CONFIG_HIGHMEM) 219#if defined(CONFIG_HIGHMEM)
220# error change for HIGHMEM support! 220# error change for HIGHMEM support!
221#else 221#else
222 titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */ 222 titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */
@@ -262,12 +262,12 @@ void __init plat_mem_setup(void)
262 add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); 262 add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
263 263
264 /* Set up the peripheral address map */ 264 /* Set up the peripheral address map */
265 *(boot_ocd_base + (LKB9 / sizeof (u32))) = 0; 265 *(boot_ocd_base + (LKB9 / sizeof(u32))) = 0;
266 *(boot_ocd_base + (LKB10 / sizeof (u32))) = 0; 266 *(boot_ocd_base + (LKB10 / sizeof(u32))) = 0;
267 *(boot_ocd_base + (LKB11 / sizeof (u32))) = 0; 267 *(boot_ocd_base + (LKB11 / sizeof(u32))) = 0;
268 *(boot_ocd_base + (LKB12 / sizeof (u32))) = 0; 268 *(boot_ocd_base + (LKB12 / sizeof(u32))) = 0;
269 wmb(); 269 wmb();
270 *(boot_ocd_base + (LKB0 / sizeof (u32))) = EXCITE_PHYS_OCD >> 4; 270 *(boot_ocd_base + (LKB0 / sizeof(u32))) = EXCITE_PHYS_OCD >> 4;
271 wmb(); 271 wmb();
272 272
273 ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5); 273 ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
diff --git a/arch/mips/boot/addinitrd.c b/arch/mips/boot/addinitrd.c
index 8b3033304770..193e4be52e79 100644
--- a/arch/mips/boot/addinitrd.c
+++ b/arch/mips/boot/addinitrd.c
@@ -32,13 +32,13 @@
32 32
33#define SWAB(a) (swab ? swab32(a) : (a)) 33#define SWAB(a) (swab ? swab32(a) : (a))
34 34
35void die (char *s) 35void die(char *s)
36{ 36{
37 perror (s); 37 perror(s);
38 exit (1); 38 exit(1);
39} 39}
40 40
41int main (int argc, char *argv[]) 41int main(int argc, char *argv[])
42{ 42{
43 int fd_vmlinux,fd_initrd,fd_outfile; 43 int fd_vmlinux,fd_initrd,fd_outfile;
44 FILHDR efile; 44 FILHDR efile;
@@ -52,18 +52,18 @@ int main (int argc, char *argv[])
52 int swab = 0; 52 int swab = 0;
53 53
54 if (argc != 4) { 54 if (argc != 4) {
55 printf ("Usage: %s <vmlinux> <initrd> <outfile>\n",argv[0]); 55 printf("Usage: %s <vmlinux> <initrd> <outfile>\n",argv[0]);
56 exit (1); 56 exit(1);
57 } 57 }
58 58
59 if ((fd_vmlinux = open (argv[1],O_RDONLY)) < 0) 59 if ((fd_vmlinux = open (argv[1],O_RDONLY)) < 0)
60 die ("open vmlinux"); 60 die("open vmlinux");
61 if (read (fd_vmlinux, &efile, sizeof efile) != sizeof efile) 61 if (read (fd_vmlinux, &efile, sizeof efile) != sizeof efile)
62 die ("read file header"); 62 die("read file header");
63 if (read (fd_vmlinux, &eaout, sizeof eaout) != sizeof eaout) 63 if (read (fd_vmlinux, &eaout, sizeof eaout) != sizeof eaout)
64 die ("read aout header"); 64 die("read aout header");
65 if (read (fd_vmlinux, esecs, sizeof esecs) != sizeof esecs) 65 if (read (fd_vmlinux, esecs, sizeof esecs) != sizeof esecs)
66 die ("read section headers"); 66 die("read section headers");
67 /* 67 /*
68 * check whether the file is good for us 68 * check whether the file is good for us
69 */ 69 */
@@ -82,13 +82,13 @@ int main (int argc, char *argv[])
82 82
83 /* make sure we have an empty data segment for the initrd */ 83 /* make sure we have an empty data segment for the initrd */
84 if (eaout.dsize || esecs[1].s_size) { 84 if (eaout.dsize || esecs[1].s_size) {
85 fprintf (stderr, "Data segment not empty. Giving up!\n"); 85 fprintf(stderr, "Data segment not empty. Giving up!\n");
86 exit (1); 86 exit(1);
87 } 87 }
88 if ((fd_initrd = open (argv[2], O_RDONLY)) < 0) 88 if ((fd_initrd = open (argv[2], O_RDONLY)) < 0)
89 die ("open initrd"); 89 die("open initrd");
90 if (fstat (fd_initrd, &st) < 0) 90 if (fstat (fd_initrd, &st) < 0)
91 die ("fstat initrd"); 91 die("fstat initrd");
92 loadaddr = ((SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size) 92 loadaddr = ((SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)
93 + MIPS_PAGE_SIZE-1) & ~MIPS_PAGE_MASK) - 8; 93 + MIPS_PAGE_SIZE-1) & ~MIPS_PAGE_MASK) - 8;
94 if (loadaddr < (SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size))) 94 if (loadaddr < (SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)))
@@ -99,33 +99,33 @@ int main (int argc, char *argv[])
99 eaout.data_start = esecs[1].s_vaddr = esecs[1].s_paddr = SWAB(loadaddr); 99 eaout.data_start = esecs[1].s_vaddr = esecs[1].s_paddr = SWAB(loadaddr);
100 100
101 if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC,0666)) < 0) 101 if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC,0666)) < 0)
102 die ("open outfile"); 102 die("open outfile");
103 if (write (fd_outfile, &efile, sizeof efile) != sizeof efile) 103 if (write (fd_outfile, &efile, sizeof efile) != sizeof efile)
104 die ("write file header"); 104 die("write file header");
105 if (write (fd_outfile, &eaout, sizeof eaout) != sizeof eaout) 105 if (write (fd_outfile, &eaout, sizeof eaout) != sizeof eaout)
106 die ("write aout header"); 106 die("write aout header");
107 if (write (fd_outfile, esecs, sizeof esecs) != sizeof esecs) 107 if (write (fd_outfile, esecs, sizeof esecs) != sizeof esecs)
108 die ("write section headers"); 108 die("write section headers");
109 /* skip padding */ 109 /* skip padding */
110 if(lseek(fd_vmlinux, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1) 110 if(lseek(fd_vmlinux, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
111 die ("lseek vmlinux"); 111 die("lseek vmlinux");
112 if(lseek(fd_outfile, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1) 112 if(lseek(fd_outfile, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
113 die ("lseek outfile"); 113 die("lseek outfile");
114 /* copy text segment */ 114 /* copy text segment */
115 cnt = SWAB(eaout.tsize); 115 cnt = SWAB(eaout.tsize);
116 while (cnt) { 116 while (cnt) {
117 if ((i = read (fd_vmlinux, buf, sizeof buf)) <= 0) 117 if ((i = read (fd_vmlinux, buf, sizeof buf)) <= 0)
118 die ("read vmlinux"); 118 die("read vmlinux");
119 if (write (fd_outfile, buf, i) != i) 119 if (write (fd_outfile, buf, i) != i)
120 die ("write vmlinux"); 120 die("write vmlinux");
121 cnt -= i; 121 cnt -= i;
122 } 122 }
123 if (write (fd_outfile, initrd_header, sizeof initrd_header) != sizeof initrd_header) 123 if (write (fd_outfile, initrd_header, sizeof initrd_header) != sizeof initrd_header)
124 die ("write initrd header"); 124 die("write initrd header");
125 while ((i = read (fd_initrd, buf, sizeof buf)) > 0) 125 while ((i = read (fd_initrd, buf, sizeof buf)) > 0)
126 if (write (fd_outfile, buf, i) != i) 126 if (write (fd_outfile, buf, i) != i)
127 die ("write initrd"); 127 die("write initrd");
128 close (fd_vmlinux); 128 close(fd_vmlinux);
129 close (fd_initrd); 129 close(fd_initrd);
130 return 0; 130 return 0;
131} 131}
diff --git a/arch/mips/fw/arc/memory.c b/arch/mips/fw/arc/memory.c
index 83d15791ef6a..8b8eea2b6cf6 100644
--- a/arch/mips/fw/arc/memory.c
+++ b/arch/mips/fw/arc/memory.c
@@ -63,7 +63,7 @@ static char *arc_mtypes[8] = {
63 : arc_mtypes[a.arc] 63 : arc_mtypes[a.arc]
64#endif 64#endif
65 65
66static inline int memtype_classify_arcs (union linux_memtypes type) 66static inline int memtype_classify_arcs(union linux_memtypes type)
67{ 67{
68 switch (type.arcs) { 68 switch (type.arcs) {
69 case arcs_fcontig: 69 case arcs_fcontig:
@@ -83,7 +83,7 @@ static inline int memtype_classify_arcs (union linux_memtypes type)
83 while(1); /* Nuke warning. */ 83 while(1); /* Nuke warning. */
84} 84}
85 85
86static inline int memtype_classify_arc (union linux_memtypes type) 86static inline int memtype_classify_arc(union linux_memtypes type)
87{ 87{
88 switch (type.arc) { 88 switch (type.arc) {
89 case arc_free: 89 case arc_free:
@@ -103,7 +103,7 @@ static inline int memtype_classify_arc (union linux_memtypes type)
103 while(1); /* Nuke warning. */ 103 while(1); /* Nuke warning. */
104} 104}
105 105
106static int __init prom_memtype_classify (union linux_memtypes type) 106static int __init prom_memtype_classify(union linux_memtypes type)
107{ 107{
108 if (prom_flags & PROM_FLAG_ARCS) /* SGI is ``different'' ... */ 108 if (prom_flags & PROM_FLAG_ARCS) /* SGI is ``different'' ... */
109 return memtype_classify_arcs(type); 109 return memtype_classify_arcs(type);
diff --git a/arch/mips/jazz/reset.c b/arch/mips/jazz/reset.c
index d8ade85060b3..dd889fe86bd1 100644
--- a/arch/mips/jazz/reset.c
+++ b/arch/mips/jazz/reset.c
@@ -49,8 +49,8 @@ void jazz_machine_restart(char *command)
49{ 49{
50 while(1) { 50 while(1) {
51 kb_wait(); 51 kb_wait();
52 jazz_write_command (0xd1); 52 jazz_write_command(0xd1);
53 kb_wait(); 53 kb_wait();
54 jazz_write_output (0x00); 54 jazz_write_output(0x00);
55 } 55 }
56} 56}
diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c
index 2a7ec08b6bad..cfc7dce78dab 100644
--- a/arch/mips/jazz/setup.c
+++ b/arch/mips/jazz/setup.c
@@ -74,11 +74,11 @@ void __init plat_mem_setup(void)
74 int i; 74 int i;
75 75
76 /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */ 76 /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */
77 add_wired_entry (0x02000017, 0x03c00017, 0xe0000000, PM_64K); 77 add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K);
78 /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */ 78 /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */
79 add_wired_entry (0x02400017, 0x02440017, 0xe2000000, PM_16M); 79 add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M);
80 /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */ 80 /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */
81 add_wired_entry (0x01800017, 0x01000017, 0xe4000000, PM_4M); 81 add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M);
82 82
83 set_io_port_base(JAZZ_PORT_BASE); 83 set_io_port_base(JAZZ_PORT_BASE);
84#ifdef CONFIG_EISA 84#ifdef CONFIG_EISA
diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c
index 6648fde20b96..af78456d4138 100644
--- a/arch/mips/kernel/cpu-bugs64.c
+++ b/arch/mips/kernel/cpu-bugs64.c
@@ -29,7 +29,7 @@ static inline void align_mod(const int align, const int mod)
29 ".endr\n\t" 29 ".endr\n\t"
30 ".set pop" 30 ".set pop"
31 : 31 :
32 : GCC_IMM_ASM (align), GCC_IMM_ASM (mod)); 32 : GCC_IMM_ASM(align), GCC_IMM_ASM(mod));
33} 33}
34 34
35static inline void mult_sh_align_mod(long *v1, long *v2, long *w, 35static inline void mult_sh_align_mod(long *v1, long *v2, long *w,
diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c
index cb5623aad552..989d06c3827b 100644
--- a/arch/mips/kernel/gdb-stub.c
+++ b/arch/mips/kernel/gdb-stub.c
@@ -733,7 +733,7 @@ static int kgdb_smp_call_kgdb_wait(void)
733 * returns 1 if you should skip the instruction at the trap address, 0 733 * returns 1 if you should skip the instruction at the trap address, 0
734 * otherwise. 734 * otherwise.
735 */ 735 */
736void handle_exception (struct gdb_regs *regs) 736void handle_exception(struct gdb_regs *regs)
737{ 737{
738 int trap; /* Trap type */ 738 int trap; /* Trap type */
739 int sigval; 739 int sigval;
@@ -917,7 +917,7 @@ void handle_exception (struct gdb_regs *regs)
917 && hexToInt(&ptr, &length)) { 917 && hexToInt(&ptr, &length)) {
918 if (mem2hex((char *)addr, output_buffer, length, 1)) 918 if (mem2hex((char *)addr, output_buffer, length, 1))
919 break; 919 break;
920 strcpy (output_buffer, "E03"); 920 strcpy(output_buffer, "E03");
921 } else 921 } else
922 strcpy(output_buffer,"E01"); 922 strcpy(output_buffer,"E01");
923 break; 923 break;
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index b6e5bb41b06b..a860b21e63e9 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -329,7 +329,7 @@ static struct resource pic2_io_resource = {
329 * driver compatibility reasons interrupts 0 - 15 to be the i8259 329 * driver compatibility reasons interrupts 0 - 15 to be the i8259
330 * interrupts even if the hardware uses a different interrupt numbering. 330 * interrupts even if the hardware uses a different interrupt numbering.
331 */ 331 */
332void __init init_i8259_irqs (void) 332void __init init_i8259_irqs(void)
333{ 333{
334 int i; 334 int i;
335 335
diff --git a/arch/mips/kernel/irixelf.c b/arch/mips/kernel/irixelf.c
index 403d96f99e77..e3b4b547a822 100644
--- a/arch/mips/kernel/irixelf.c
+++ b/arch/mips/kernel/irixelf.c
@@ -203,8 +203,8 @@ static unsigned long * create_irix_tables(char * p, int argc, int envc,
203 * Put the ELF interpreter info on the stack 203 * Put the ELF interpreter info on the stack
204 */ 204 */
205#define NEW_AUX_ENT(nr, id, val) \ 205#define NEW_AUX_ENT(nr, id, val) \
206 __put_user ((id), sp+(nr*2)); \ 206 __put_user((id), sp+(nr*2)); \
207 __put_user ((val), sp+(nr*2+1)); \ 207 __put_user((val), sp+(nr*2+1)); \
208 208
209 sp -= 2; 209 sp -= 2;
210 NEW_AUX_ENT(0, AT_NULL, 0); 210 NEW_AUX_ENT(0, AT_NULL, 0);
@@ -212,17 +212,17 @@ static unsigned long * create_irix_tables(char * p, int argc, int envc,
212 if (exec) { 212 if (exec) {
213 sp -= 11*2; 213 sp -= 11*2;
214 214
215 NEW_AUX_ENT (0, AT_PHDR, load_addr + exec->e_phoff); 215 NEW_AUX_ENT(0, AT_PHDR, load_addr + exec->e_phoff);
216 NEW_AUX_ENT (1, AT_PHENT, sizeof (struct elf_phdr)); 216 NEW_AUX_ENT(1, AT_PHENT, sizeof(struct elf_phdr));
217 NEW_AUX_ENT (2, AT_PHNUM, exec->e_phnum); 217 NEW_AUX_ENT(2, AT_PHNUM, exec->e_phnum);
218 NEW_AUX_ENT (3, AT_PAGESZ, ELF_EXEC_PAGESIZE); 218 NEW_AUX_ENT(3, AT_PAGESZ, ELF_EXEC_PAGESIZE);
219 NEW_AUX_ENT (4, AT_BASE, interp_load_addr); 219 NEW_AUX_ENT(4, AT_BASE, interp_load_addr);
220 NEW_AUX_ENT (5, AT_FLAGS, 0); 220 NEW_AUX_ENT(5, AT_FLAGS, 0);
221 NEW_AUX_ENT (6, AT_ENTRY, (elf_addr_t) exec->e_entry); 221 NEW_AUX_ENT(6, AT_ENTRY, (elf_addr_t) exec->e_entry);
222 NEW_AUX_ENT (7, AT_UID, (elf_addr_t) current->uid); 222 NEW_AUX_ENT(7, AT_UID, (elf_addr_t) current->uid);
223 NEW_AUX_ENT (8, AT_EUID, (elf_addr_t) current->euid); 223 NEW_AUX_ENT(8, AT_EUID, (elf_addr_t) current->euid);
224 NEW_AUX_ENT (9, AT_GID, (elf_addr_t) current->gid); 224 NEW_AUX_ENT(9, AT_GID, (elf_addr_t) current->gid);
225 NEW_AUX_ENT (10, AT_EGID, (elf_addr_t) current->egid); 225 NEW_AUX_ENT(10, AT_EGID, (elf_addr_t) current->egid);
226 } 226 }
227#undef NEW_AUX_ENT 227#undef NEW_AUX_ENT
228 228
@@ -581,7 +581,7 @@ static void irix_map_prda_page(void)
581 struct prda *pp; 581 struct prda *pp;
582 582
583 down_write(&current->mm->mmap_sem); 583 down_write(&current->mm->mmap_sem);
584 v = do_brk (PRDA_ADDRESS, PAGE_SIZE); 584 v = do_brk(PRDA_ADDRESS, PAGE_SIZE);
585 up_write(&current->mm->mmap_sem); 585 up_write(&current->mm->mmap_sem);
586 586
587 if (v < 0) 587 if (v < 0)
@@ -815,7 +815,7 @@ out_free_interp:
815 kfree(elf_interpreter); 815 kfree(elf_interpreter);
816out_free_file: 816out_free_file:
817out_free_ph: 817out_free_ph:
818 kfree (elf_phdata); 818 kfree(elf_phdata);
819 goto out; 819 goto out;
820} 820}
821 821
@@ -1232,7 +1232,7 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file)
1232 strlcpy(psinfo.pr_fname, current->comm, sizeof(psinfo.pr_fname)); 1232 strlcpy(psinfo.pr_fname, current->comm, sizeof(psinfo.pr_fname));
1233 1233
1234 /* Try to dump the FPU. */ 1234 /* Try to dump the FPU. */
1235 prstatus.pr_fpvalid = dump_fpu (regs, &fpu); 1235 prstatus.pr_fpvalid = dump_fpu(regs, &fpu);
1236 if (!prstatus.pr_fpvalid) { 1236 if (!prstatus.pr_fpvalid) {
1237 numnote--; 1237 numnote--;
1238 } else { 1238 } else {
diff --git a/arch/mips/kernel/irixinv.c b/arch/mips/kernel/irixinv.c
index de8584f62311..cf2dcd3d6a93 100644
--- a/arch/mips/kernel/irixinv.c
+++ b/arch/mips/kernel/irixinv.c
@@ -14,7 +14,7 @@ int inventory_items = 0;
14 14
15static inventory_t inventory [MAX_INVENTORY]; 15static inventory_t inventory [MAX_INVENTORY];
16 16
17void add_to_inventory (int class, int type, int controller, int unit, int state) 17void add_to_inventory(int class, int type, int controller, int unit, int state)
18{ 18{
19 inventory_t *ni = &inventory [inventory_items]; 19 inventory_t *ni = &inventory [inventory_items];
20 20
@@ -30,7 +30,7 @@ void add_to_inventory (int class, int type, int controller, int unit, int state)
30 inventory_items++; 30 inventory_items++;
31} 31}
32 32
33int dump_inventory_to_user (void __user *userbuf, int size) 33int dump_inventory_to_user(void __user *userbuf, int size)
34{ 34{
35 inventory_t *inv = &inventory [0]; 35 inventory_t *inv = &inventory [0];
36 inventory_t __user *user = userbuf; 36 inventory_t __user *user = userbuf;
@@ -45,7 +45,7 @@ int dump_inventory_to_user (void __user *userbuf, int size)
45 return -EFAULT; 45 return -EFAULT;
46 user++; 46 user++;
47 } 47 }
48 return inventory_items * sizeof (inventory_t); 48 return inventory_items * sizeof(inventory_t);
49} 49}
50 50
51int __init init_inventory(void) 51int __init init_inventory(void)
@@ -55,24 +55,24 @@ int __init init_inventory(void)
55 * most likely this will not let just anyone run the X server 55 * most likely this will not let just anyone run the X server
56 * until we put the right values all over the place 56 * until we put the right values all over the place
57 */ 57 */
58 add_to_inventory (10, 3, 0, 0, 16400); 58 add_to_inventory(10, 3, 0, 0, 16400);
59 add_to_inventory (1, 1, 150, -1, 12); 59 add_to_inventory(1, 1, 150, -1, 12);
60 add_to_inventory (1, 3, 0, 0, 8976); 60 add_to_inventory(1, 3, 0, 0, 8976);
61 add_to_inventory (1, 2, 0, 0, 8976); 61 add_to_inventory(1, 2, 0, 0, 8976);
62 add_to_inventory (4, 8, 0, 0, 2); 62 add_to_inventory(4, 8, 0, 0, 2);
63 add_to_inventory (5, 5, 0, 0, 1); 63 add_to_inventory(5, 5, 0, 0, 1);
64 add_to_inventory (3, 3, 0, 0, 32768); 64 add_to_inventory(3, 3, 0, 0, 32768);
65 add_to_inventory (3, 4, 0, 0, 32768); 65 add_to_inventory(3, 4, 0, 0, 32768);
66 add_to_inventory (3, 8, 0, 0, 524288); 66 add_to_inventory(3, 8, 0, 0, 524288);
67 add_to_inventory (3, 9, 0, 0, 64); 67 add_to_inventory(3, 9, 0, 0, 64);
68 add_to_inventory (3, 1, 0, 0, 67108864); 68 add_to_inventory(3, 1, 0, 0, 67108864);
69 add_to_inventory (12, 3, 0, 0, 16); 69 add_to_inventory(12, 3, 0, 0, 16);
70 add_to_inventory (8, 7, 17, 0, 16777472); 70 add_to_inventory(8, 7, 17, 0, 16777472);
71 add_to_inventory (8, 0, 0, 0, 1); 71 add_to_inventory(8, 0, 0, 0, 1);
72 add_to_inventory (2, 1, 0, 13, 2); 72 add_to_inventory(2, 1, 0, 13, 2);
73 add_to_inventory (2, 2, 0, 2, 0); 73 add_to_inventory(2, 2, 0, 2, 0);
74 add_to_inventory (2, 2, 0, 1, 0); 74 add_to_inventory(2, 2, 0, 1, 0);
75 add_to_inventory (7, 14, 0, 0, 6); 75 add_to_inventory(7, 14, 0, 0, 6);
76 76
77 return 0; 77 return 0;
78} 78}
diff --git a/arch/mips/kernel/irixioctl.c b/arch/mips/kernel/irixioctl.c
index 30f9eb09db3f..2bde200d5ad0 100644
--- a/arch/mips/kernel/irixioctl.c
+++ b/arch/mips/kernel/irixioctl.c
@@ -238,7 +238,7 @@ asmlinkage int irix_ioctl(int fd, unsigned long cmd, unsigned long arg)
238 current->comm, current->pid, cmd); 238 current->comm, current->pid, cmd);
239 do_exit(255); 239 do_exit(255);
240#else 240#else
241 error = sys_ioctl (fd, cmd, arg); 241 error = sys_ioctl(fd, cmd, arg);
242#endif 242#endif
243 } 243 }
244 244
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index 1ecdd50bfc60..4edc7e451d91 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -99,7 +99,7 @@ void ll_msc_irq(void)
99} 99}
100 100
101void 101void
102msc_bind_eic_interrupt (unsigned int irq, unsigned int set) 102msc_bind_eic_interrupt(unsigned int irq, unsigned int set)
103{ 103{
104 MSCIC_WRITE(MSC01_IC_RAMW, 104 MSCIC_WRITE(MSC01_IC_RAMW,
105 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF)); 105 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
@@ -130,7 +130,7 @@ void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqma
130{ 130{
131 extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset); 131 extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset);
132 132
133 _icctrl_msc = (unsigned long) ioremap (icubase, 0x40000); 133 _icctrl_msc = (unsigned long) ioremap(icubase, 0x40000);
134 134
135 /* Reset interrupt controller - initialises all registers to 0 */ 135 /* Reset interrupt controller - initialises all registers to 0 */
136 MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT); 136 MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c
index cb9a14a1ca5b..1ed176606548 100644
--- a/arch/mips/kernel/kspd.c
+++ b/arch/mips/kernel/kspd.c
@@ -118,11 +118,11 @@ struct apsp_table syscall_command_table[] = {
118 118
119static int sp_syscall(int num, int arg0, int arg1, int arg2, int arg3) 119static int sp_syscall(int num, int arg0, int arg1, int arg2, int arg3)
120{ 120{
121 register long int _num __asm__ ("$2") = num; 121 register long int _num __asm__("$2") = num;
122 register long int _arg0 __asm__ ("$4") = arg0; 122 register long int _arg0 __asm__("$4") = arg0;
123 register long int _arg1 __asm__ ("$5") = arg1; 123 register long int _arg1 __asm__("$5") = arg1;
124 register long int _arg2 __asm__ ("$6") = arg2; 124 register long int _arg2 __asm__("$6") = arg2;
125 register long int _arg3 __asm__ ("$7") = arg3; 125 register long int _arg3 __asm__("$7") = arg3;
126 126
127 mm_segment_t old_fs; 127 mm_segment_t old_fs;
128 128
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 135d9a5fe337..a6de17081cad 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -300,13 +300,13 @@ asmlinkage int sys32_sched_rr_get_interval(compat_pid_t pid,
300{ 300{
301 struct timespec t; 301 struct timespec t;
302 int ret; 302 int ret;
303 mm_segment_t old_fs = get_fs (); 303 mm_segment_t old_fs = get_fs();
304 304
305 set_fs (KERNEL_DS); 305 set_fs(KERNEL_DS);
306 ret = sys_sched_rr_get_interval(pid, (struct timespec __user *)&t); 306 ret = sys_sched_rr_get_interval(pid, (struct timespec __user *)&t);
307 set_fs (old_fs); 307 set_fs(old_fs);
308 if (put_user (t.tv_sec, &interval->tv_sec) || 308 if (put_user (t.tv_sec, &interval->tv_sec) ||
309 __put_user (t.tv_nsec, &interval->tv_nsec)) 309 __put_user(t.tv_nsec, &interval->tv_nsec))
310 return -EFAULT; 310 return -EFAULT;
311 return ret; 311 return ret;
312} 312}
@@ -314,7 +314,7 @@ asmlinkage int sys32_sched_rr_get_interval(compat_pid_t pid,
314#ifdef CONFIG_SYSVIPC 314#ifdef CONFIG_SYSVIPC
315 315
316asmlinkage long 316asmlinkage long
317sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth) 317sys32_ipc(u32 call, int first, int second, int third, u32 ptr, u32 fifth)
318{ 318{
319 int version, err; 319 int version, err;
320 320
@@ -373,7 +373,7 @@ sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth)
373#else 373#else
374 374
375asmlinkage long 375asmlinkage long
376sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth) 376sys32_ipc(u32 call, int first, int second, int third, u32 ptr, u32 fifth)
377{ 377{
378 return -ENOSYS; 378 return -ENOSYS;
379} 379}
@@ -505,7 +505,7 @@ asmlinkage int sys32_ustat(dev_t dev, struct ustat32 __user * ubuf32)
505 505
506 set_fs(KERNEL_DS); 506 set_fs(KERNEL_DS);
507 err = sys_ustat(dev, (struct ustat __user *)&tmp); 507 err = sys_ustat(dev, (struct ustat __user *)&tmp);
508 set_fs (old_fs); 508 set_fs(old_fs);
509 509
510 if (err) 510 if (err)
511 goto out; 511 goto out;
diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c
index 56750b02ab40..3d6b1ec1f328 100644
--- a/arch/mips/kernel/mips-mt.c
+++ b/arch/mips/kernel/mips-mt.c
@@ -236,7 +236,7 @@ void mips_mt_set_cpuoptions(void)
236 if (oconfig7 != nconfig7) { 236 if (oconfig7 != nconfig7) {
237 __asm__ __volatile("sync"); 237 __asm__ __volatile("sync");
238 write_c0_config7(nconfig7); 238 write_c0_config7(nconfig7);
239 ehb (); 239 ehb();
240 printk("Config7: 0x%08x\n", read_c0_config7()); 240 printk("Config7: 0x%08x\n", read_c0_config7());
241 } 241 }
242 242
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index f99bb4085430..11cb264f59ce 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -202,13 +202,13 @@ void elf_dump_regs(elf_greg_t *gp, struct pt_regs *regs)
202#endif 202#endif
203} 203}
204 204
205int dump_task_regs (struct task_struct *tsk, elf_gregset_t *regs) 205int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs)
206{ 206{
207 elf_dump_regs(*regs, task_pt_regs(tsk)); 207 elf_dump_regs(*regs, task_pt_regs(tsk));
208 return 1; 208 return 1;
209} 209}
210 210
211int dump_task_fpu (struct task_struct *t, elf_fpregset_t *fpr) 211int dump_task_fpu(struct task_struct *t, elf_fpregset_t *fpr)
212{ 212{
213 memcpy(fpr, &t->thread.fpu, sizeof(current->thread.fpu)); 213 memcpy(fpr, &t->thread.fpu, sizeof(current->thread.fpu));
214 214
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index bbd57b20b43e..58aa6fec1146 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -54,7 +54,7 @@ void ptrace_disable(struct task_struct *child)
54 * for 32-bit kernels and for 32-bit processes on a 64-bit kernel. 54 * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
55 * Registers are sign extended to fill the available space. 55 * Registers are sign extended to fill the available space.
56 */ 56 */
57int ptrace_getregs (struct task_struct *child, __s64 __user *data) 57int ptrace_getregs(struct task_struct *child, __s64 __user *data)
58{ 58{
59 struct pt_regs *regs; 59 struct pt_regs *regs;
60 int i; 60 int i;
@@ -65,13 +65,13 @@ int ptrace_getregs (struct task_struct *child, __s64 __user *data)
65 regs = task_pt_regs(child); 65 regs = task_pt_regs(child);
66 66
67 for (i = 0; i < 32; i++) 67 for (i = 0; i < 32; i++)
68 __put_user (regs->regs[i], data + i); 68 __put_user(regs->regs[i], data + i);
69 __put_user (regs->lo, data + EF_LO - EF_R0); 69 __put_user(regs->lo, data + EF_LO - EF_R0);
70 __put_user (regs->hi, data + EF_HI - EF_R0); 70 __put_user(regs->hi, data + EF_HI - EF_R0);
71 __put_user (regs->cp0_epc, data + EF_CP0_EPC - EF_R0); 71 __put_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
72 __put_user (regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0); 72 __put_user(regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
73 __put_user (regs->cp0_status, data + EF_CP0_STATUS - EF_R0); 73 __put_user(regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
74 __put_user (regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0); 74 __put_user(regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);
75 75
76 return 0; 76 return 0;
77} 77}
@@ -81,7 +81,7 @@ int ptrace_getregs (struct task_struct *child, __s64 __user *data)
81 * the 64-bit format. On a 32-bit kernel only the lower order half 81 * the 64-bit format. On a 32-bit kernel only the lower order half
82 * (according to endianness) will be used. 82 * (according to endianness) will be used.
83 */ 83 */
84int ptrace_setregs (struct task_struct *child, __s64 __user *data) 84int ptrace_setregs(struct task_struct *child, __s64 __user *data)
85{ 85{
86 struct pt_regs *regs; 86 struct pt_regs *regs;
87 int i; 87 int i;
@@ -92,17 +92,17 @@ int ptrace_setregs (struct task_struct *child, __s64 __user *data)
92 regs = task_pt_regs(child); 92 regs = task_pt_regs(child);
93 93
94 for (i = 0; i < 32; i++) 94 for (i = 0; i < 32; i++)
95 __get_user (regs->regs[i], data + i); 95 __get_user(regs->regs[i], data + i);
96 __get_user (regs->lo, data + EF_LO - EF_R0); 96 __get_user(regs->lo, data + EF_LO - EF_R0);
97 __get_user (regs->hi, data + EF_HI - EF_R0); 97 __get_user(regs->hi, data + EF_HI - EF_R0);
98 __get_user (regs->cp0_epc, data + EF_CP0_EPC - EF_R0); 98 __get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
99 99
100 /* badvaddr, status, and cause may not be written. */ 100 /* badvaddr, status, and cause may not be written. */
101 101
102 return 0; 102 return 0;
103} 103}
104 104
105int ptrace_getfpregs (struct task_struct *child, __u32 __user *data) 105int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
106{ 106{
107 int i; 107 int i;
108 unsigned int tmp; 108 unsigned int tmp;
@@ -113,13 +113,13 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data)
113 if (tsk_used_math(child)) { 113 if (tsk_used_math(child)) {
114 fpureg_t *fregs = get_fpu_regs(child); 114 fpureg_t *fregs = get_fpu_regs(child);
115 for (i = 0; i < 32; i++) 115 for (i = 0; i < 32; i++)
116 __put_user (fregs[i], i + (__u64 __user *) data); 116 __put_user(fregs[i], i + (__u64 __user *) data);
117 } else { 117 } else {
118 for (i = 0; i < 32; i++) 118 for (i = 0; i < 32; i++)
119 __put_user ((__u64) -1, i + (__u64 __user *) data); 119 __put_user((__u64) -1, i + (__u64 __user *) data);
120 } 120 }
121 121
122 __put_user (child->thread.fpu.fcr31, data + 64); 122 __put_user(child->thread.fpu.fcr31, data + 64);
123 123
124 preempt_disable(); 124 preempt_disable();
125 if (cpu_has_fpu) { 125 if (cpu_has_fpu) {
@@ -142,12 +142,12 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data)
142 tmp = 0; 142 tmp = 0;
143 } 143 }
144 preempt_enable(); 144 preempt_enable();
145 __put_user (tmp, data + 65); 145 __put_user(tmp, data + 65);
146 146
147 return 0; 147 return 0;
148} 148}
149 149
150int ptrace_setfpregs (struct task_struct *child, __u32 __user *data) 150int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
151{ 151{
152 fpureg_t *fregs; 152 fpureg_t *fregs;
153 int i; 153 int i;
@@ -158,9 +158,9 @@ int ptrace_setfpregs (struct task_struct *child, __u32 __user *data)
158 fregs = get_fpu_regs(child); 158 fregs = get_fpu_regs(child);
159 159
160 for (i = 0; i < 32; i++) 160 for (i = 0; i < 32; i++)
161 __get_user (fregs[i], i + (__u64 __user *) data); 161 __get_user(fregs[i], i + (__u64 __user *) data);
162 162
163 __get_user (child->thread.fpu.fcr31, data + 64); 163 __get_user(child->thread.fpu.fcr31, data + 64);
164 164
165 /* FIR may not be written. */ 165 /* FIR may not be written. */
166 166
@@ -390,19 +390,19 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
390 } 390 }
391 391
392 case PTRACE_GETREGS: 392 case PTRACE_GETREGS:
393 ret = ptrace_getregs (child, (__u64 __user *) data); 393 ret = ptrace_getregs(child, (__u64 __user *) data);
394 break; 394 break;
395 395
396 case PTRACE_SETREGS: 396 case PTRACE_SETREGS:
397 ret = ptrace_setregs (child, (__u64 __user *) data); 397 ret = ptrace_setregs(child, (__u64 __user *) data);
398 break; 398 break;
399 399
400 case PTRACE_GETFPREGS: 400 case PTRACE_GETFPREGS:
401 ret = ptrace_getfpregs (child, (__u32 __user *) data); 401 ret = ptrace_getfpregs(child, (__u32 __user *) data);
402 break; 402 break;
403 403
404 case PTRACE_SETFPREGS: 404 case PTRACE_SETFPREGS:
405 ret = ptrace_setfpregs (child, (__u32 __user *) data); 405 ret = ptrace_setfpregs(child, (__u32 __user *) data);
406 break; 406 break;
407 407
408 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ 408 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index d9a39c169450..f2bffed94fa3 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -36,11 +36,11 @@
36#include <asm/uaccess.h> 36#include <asm/uaccess.h>
37#include <asm/bootinfo.h> 37#include <asm/bootinfo.h>
38 38
39int ptrace_getregs (struct task_struct *child, __s64 __user *data); 39int ptrace_getregs(struct task_struct *child, __s64 __user *data);
40int ptrace_setregs (struct task_struct *child, __s64 __user *data); 40int ptrace_setregs(struct task_struct *child, __s64 __user *data);
41 41
42int ptrace_getfpregs (struct task_struct *child, __u32 __user *data); 42int ptrace_getfpregs(struct task_struct *child, __u32 __user *data);
43int ptrace_setfpregs (struct task_struct *child, __u32 __user *data); 43int ptrace_setfpregs(struct task_struct *child, __u32 __user *data);
44 44
45/* 45/*
46 * Tracing a 32-bit process with a 64-bit strace and vice versa will not 46 * Tracing a 32-bit process with a 64-bit strace and vice versa will not
@@ -346,19 +346,19 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
346 } 346 }
347 347
348 case PTRACE_GETREGS: 348 case PTRACE_GETREGS:
349 ret = ptrace_getregs (child, (__u64 __user *) (__u64) data); 349 ret = ptrace_getregs(child, (__u64 __user *) (__u64) data);
350 break; 350 break;
351 351
352 case PTRACE_SETREGS: 352 case PTRACE_SETREGS:
353 ret = ptrace_setregs (child, (__u64 __user *) (__u64) data); 353 ret = ptrace_setregs(child, (__u64 __user *) (__u64) data);
354 break; 354 break;
355 355
356 case PTRACE_GETFPREGS: 356 case PTRACE_GETFPREGS:
357 ret = ptrace_getfpregs (child, (__u32 __user *) (__u64) data); 357 ret = ptrace_getfpregs(child, (__u32 __user *) (__u64) data);
358 break; 358 break;
359 359
360 case PTRACE_SETFPREGS: 360 case PTRACE_SETFPREGS:
361 ret = ptrace_setfpregs (child, (__u32 __user *) (__u64) data); 361 ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data);
362 break; 362 break;
363 363
364 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ 364 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 64b612a0a622..572c610db1b1 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -261,11 +261,11 @@ static inline int put_sigset(const sigset_t *kbuf, compat_sigset_t __user *ubuf)
261 default: 261 default:
262 __put_sigset_unknown_nsig(); 262 __put_sigset_unknown_nsig();
263 case 2: 263 case 2:
264 err |= __put_user (kbuf->sig[1] >> 32, &ubuf->sig[3]); 264 err |= __put_user(kbuf->sig[1] >> 32, &ubuf->sig[3]);
265 err |= __put_user (kbuf->sig[1] & 0xffffffff, &ubuf->sig[2]); 265 err |= __put_user(kbuf->sig[1] & 0xffffffff, &ubuf->sig[2]);
266 case 1: 266 case 1:
267 err |= __put_user (kbuf->sig[0] >> 32, &ubuf->sig[1]); 267 err |= __put_user(kbuf->sig[0] >> 32, &ubuf->sig[1]);
268 err |= __put_user (kbuf->sig[0] & 0xffffffff, &ubuf->sig[0]); 268 err |= __put_user(kbuf->sig[0] & 0xffffffff, &ubuf->sig[0]);
269 } 269 }
270 270
271 return err; 271 return err;
@@ -283,12 +283,12 @@ static inline int get_sigset(sigset_t *kbuf, const compat_sigset_t __user *ubuf)
283 default: 283 default:
284 __get_sigset_unknown_nsig(); 284 __get_sigset_unknown_nsig();
285 case 2: 285 case 2:
286 err |= __get_user (sig[3], &ubuf->sig[3]); 286 err |= __get_user(sig[3], &ubuf->sig[3]);
287 err |= __get_user (sig[2], &ubuf->sig[2]); 287 err |= __get_user(sig[2], &ubuf->sig[2]);
288 kbuf->sig[1] = sig[2] | (sig[3] << 32); 288 kbuf->sig[1] = sig[2] | (sig[3] << 32);
289 case 1: 289 case 1:
290 err |= __get_user (sig[1], &ubuf->sig[1]); 290 err |= __get_user(sig[1], &ubuf->sig[1]);
291 err |= __get_user (sig[0], &ubuf->sig[0]); 291 err |= __get_user(sig[0], &ubuf->sig[0]);
292 kbuf->sig[0] = sig[0] | (sig[1] << 32); 292 kbuf->sig[0] = sig[0] | (sig[1] << 32);
293 } 293 }
294 294
@@ -412,10 +412,10 @@ asmlinkage int sys32_sigaltstack(nabi_no_regargs struct pt_regs regs)
412 return -EFAULT; 412 return -EFAULT;
413 } 413 }
414 414
415 set_fs (KERNEL_DS); 415 set_fs(KERNEL_DS);
416 ret = do_sigaltstack(uss ? (stack_t __user *)&kss : NULL, 416 ret = do_sigaltstack(uss ? (stack_t __user *)&kss : NULL,
417 uoss ? (stack_t __user *)&koss : NULL, usp); 417 uoss ? (stack_t __user *)&koss : NULL, usp);
418 set_fs (old_fs); 418 set_fs(old_fs);
419 419
420 if (!ret && uoss) { 420 if (!ret && uoss) {
421 if (!access_ok(VERIFY_WRITE, uoss, sizeof(*uoss))) 421 if (!access_ok(VERIFY_WRITE, uoss, sizeof(*uoss)))
@@ -559,9 +559,9 @@ asmlinkage void sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
559 /* It is more difficult to avoid calling this function than to 559 /* It is more difficult to avoid calling this function than to
560 call it and ignore errors. */ 560 call it and ignore errors. */
561 old_fs = get_fs(); 561 old_fs = get_fs();
562 set_fs (KERNEL_DS); 562 set_fs(KERNEL_DS);
563 do_sigaltstack((stack_t __user *)&st, NULL, regs.regs[29]); 563 do_sigaltstack((stack_t __user *)&st, NULL, regs.regs[29]);
564 set_fs (old_fs); 564 set_fs(old_fs);
565 565
566 /* 566 /*
567 * Don't let your children do this ... 567 * Don't let your children do this ...
@@ -746,11 +746,11 @@ asmlinkage int sys32_rt_sigprocmask(int how, compat_sigset_t __user *set,
746 if (set && get_sigset(&new_set, set)) 746 if (set && get_sigset(&new_set, set))
747 return -EFAULT; 747 return -EFAULT;
748 748
749 set_fs (KERNEL_DS); 749 set_fs(KERNEL_DS);
750 ret = sys_rt_sigprocmask(how, set ? (sigset_t __user *)&new_set : NULL, 750 ret = sys_rt_sigprocmask(how, set ? (sigset_t __user *)&new_set : NULL,
751 oset ? (sigset_t __user *)&old_set : NULL, 751 oset ? (sigset_t __user *)&old_set : NULL,
752 sigsetsize); 752 sigsetsize);
753 set_fs (old_fs); 753 set_fs(old_fs);
754 754
755 if (!ret && oset && put_sigset(&old_set, oset)) 755 if (!ret && oset && put_sigset(&old_set, oset))
756 return -EFAULT; 756 return -EFAULT;
@@ -765,9 +765,9 @@ asmlinkage int sys32_rt_sigpending(compat_sigset_t __user *uset,
765 sigset_t set; 765 sigset_t set;
766 mm_segment_t old_fs = get_fs(); 766 mm_segment_t old_fs = get_fs();
767 767
768 set_fs (KERNEL_DS); 768 set_fs(KERNEL_DS);
769 ret = sys_rt_sigpending((sigset_t __user *)&set, sigsetsize); 769 ret = sys_rt_sigpending((sigset_t __user *)&set, sigsetsize);
770 set_fs (old_fs); 770 set_fs(old_fs);
771 771
772 if (!ret && put_sigset(&set, uset)) 772 if (!ret && put_sigset(&set, uset))
773 return -EFAULT; 773 return -EFAULT;
@@ -781,12 +781,12 @@ asmlinkage int sys32_rt_sigqueueinfo(int pid, int sig, compat_siginfo_t __user *
781 int ret; 781 int ret;
782 mm_segment_t old_fs = get_fs(); 782 mm_segment_t old_fs = get_fs();
783 783
784 if (copy_from_user (&info, uinfo, 3*sizeof(int)) || 784 if (copy_from_user(&info, uinfo, 3*sizeof(int)) ||
785 copy_from_user (info._sifields._pad, uinfo->_sifields._pad, SI_PAD_SIZE)) 785 copy_from_user(info._sifields._pad, uinfo->_sifields._pad, SI_PAD_SIZE))
786 return -EFAULT; 786 return -EFAULT;
787 set_fs (KERNEL_DS); 787 set_fs(KERNEL_DS);
788 ret = sys_rt_sigqueueinfo(pid, sig, (siginfo_t __user *)&info); 788 ret = sys_rt_sigqueueinfo(pid, sig, (siginfo_t __user *)&info);
789 set_fs (old_fs); 789 set_fs(old_fs);
790 return ret; 790 return ret;
791} 791}
792 792
@@ -801,10 +801,10 @@ sys32_waitid(int which, compat_pid_t pid,
801 mm_segment_t old_fs = get_fs(); 801 mm_segment_t old_fs = get_fs();
802 802
803 info.si_signo = 0; 803 info.si_signo = 0;
804 set_fs (KERNEL_DS); 804 set_fs(KERNEL_DS);
805 ret = sys_waitid(which, pid, (siginfo_t __user *) &info, options, 805 ret = sys_waitid(which, pid, (siginfo_t __user *) &info, options,
806 uru ? (struct rusage __user *) &ru : NULL); 806 uru ? (struct rusage __user *) &ru : NULL);
807 set_fs (old_fs); 807 set_fs(old_fs);
808 808
809 if (ret < 0 || info.si_signo == 0) 809 if (ret < 0 || info.si_signo == 0)
810 return ret; 810 return ret;
diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c
index eb7e05926ebe..bb277e82d421 100644
--- a/arch/mips/kernel/signal_n32.c
+++ b/arch/mips/kernel/signal_n32.c
@@ -88,7 +88,7 @@ struct rt_sigframe_n32 {
88 88
89#endif /* !ICACHE_REFILLS_WORKAROUND_WAR */ 89#endif /* !ICACHE_REFILLS_WORKAROUND_WAR */
90 90
91extern void sigset_from_compat (sigset_t *set, compat_sigset_t *compat); 91extern void sigset_from_compat(sigset_t *set, compat_sigset_t *compat);
92 92
93asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs) 93asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
94{ 94{
@@ -105,7 +105,7 @@ asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
105 unewset = (compat_sigset_t __user *) regs.regs[4]; 105 unewset = (compat_sigset_t __user *) regs.regs[4];
106 if (copy_from_user(&uset, unewset, sizeof(uset))) 106 if (copy_from_user(&uset, unewset, sizeof(uset)))
107 return -EFAULT; 107 return -EFAULT;
108 sigset_from_compat (&newset, &uset); 108 sigset_from_compat(&newset, &uset);
109 sigdelsetmask(&newset, ~_BLOCKABLE); 109 sigdelsetmask(&newset, ~_BLOCKABLE);
110 110
111 spin_lock_irq(&current->sighand->siglock); 111 spin_lock_irq(&current->sighand->siglock);
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 05dcce416325..94e210cc6cb6 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -353,7 +353,7 @@ void core_send_ipi(int cpu, unsigned int action)
353 unsigned long flags; 353 unsigned long flags;
354 int vpflags; 354 int vpflags;
355 355
356 local_irq_save (flags); 356 local_irq_save(flags);
357 357
358 vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */ 358 vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */
359 359
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 4d1ac9692dcd..770182887c5b 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -372,7 +372,7 @@ void mipsmt_prepare_cpus(void)
372 cpu++; 372 cpu++;
373 373
374 /* Report on boot-time options */ 374 /* Report on boot-time options */
375 mips_mt_set_cpuoptions (); 375 mips_mt_set_cpuoptions();
376 if (vpelimit > 0) 376 if (vpelimit > 0)
377 printk("Limit of %d VPEs set\n", vpelimit); 377 printk("Limit of %d VPEs set\n", vpelimit);
378 if (tclimit > 0) 378 if (tclimit > 0)
@@ -572,7 +572,7 @@ void smtc_init_secondary(void)
572 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && 572 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
573 ((read_c0_tcbind() & TCBIND_CURVPE) 573 ((read_c0_tcbind() & TCBIND_CURVPE)
574 != cpu_data[smp_processor_id() - 1].vpe_id)){ 574 != cpu_data[smp_processor_id() - 1].vpe_id)){
575 write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); 575 write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
576 } 576 }
577 577
578 local_irq_enable(); 578 local_irq_enable();
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index 7c800ec3ff55..ef2c6360d052 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -314,8 +314,8 @@ asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3)
314 * 314 *
315 * This is really horribly ugly. 315 * This is really horribly ugly.
316 */ 316 */
317asmlinkage int sys_ipc (unsigned int call, int first, int second, 317asmlinkage int sys_ipc(unsigned int call, int first, int second,
318 unsigned long third, void __user *ptr, long fifth) 318 unsigned long third, void __user *ptr, long fifth)
319{ 319{
320 int version, ret; 320 int version, ret;
321 321
@@ -324,26 +324,26 @@ asmlinkage int sys_ipc (unsigned int call, int first, int second,
324 324
325 switch (call) { 325 switch (call) {
326 case SEMOP: 326 case SEMOP:
327 return sys_semtimedop (first, (struct sembuf __user *)ptr, 327 return sys_semtimedop(first, (struct sembuf __user *)ptr,
328 second, NULL); 328 second, NULL);
329 case SEMTIMEDOP: 329 case SEMTIMEDOP:
330 return sys_semtimedop (first, (struct sembuf __user *)ptr, 330 return sys_semtimedop(first, (struct sembuf __user *)ptr,
331 second, 331 second,
332 (const struct timespec __user *)fifth); 332 (const struct timespec __user *)fifth);
333 case SEMGET: 333 case SEMGET:
334 return sys_semget (first, second, third); 334 return sys_semget(first, second, third);
335 case SEMCTL: { 335 case SEMCTL: {
336 union semun fourth; 336 union semun fourth;
337 if (!ptr) 337 if (!ptr)
338 return -EINVAL; 338 return -EINVAL;
339 if (get_user(fourth.__pad, (void __user *__user *) ptr)) 339 if (get_user(fourth.__pad, (void __user *__user *) ptr))
340 return -EFAULT; 340 return -EFAULT;
341 return sys_semctl (first, second, third, fourth); 341 return sys_semctl(first, second, third, fourth);
342 } 342 }
343 343
344 case MSGSND: 344 case MSGSND:
345 return sys_msgsnd (first, (struct msgbuf __user *) ptr, 345 return sys_msgsnd(first, (struct msgbuf __user *) ptr,
346 second, third); 346 second, third);
347 case MSGRCV: 347 case MSGRCV:
348 switch (version) { 348 switch (version) {
349 case 0: { 349 case 0: {
@@ -353,45 +353,45 @@ asmlinkage int sys_ipc (unsigned int call, int first, int second,
353 353
354 if (copy_from_user(&tmp, 354 if (copy_from_user(&tmp,
355 (struct ipc_kludge __user *) ptr, 355 (struct ipc_kludge __user *) ptr,
356 sizeof (tmp))) 356 sizeof(tmp)))
357 return -EFAULT; 357 return -EFAULT;
358 return sys_msgrcv (first, tmp.msgp, second, 358 return sys_msgrcv(first, tmp.msgp, second,
359 tmp.msgtyp, third); 359 tmp.msgtyp, third);
360 } 360 }
361 default: 361 default:
362 return sys_msgrcv (first, 362 return sys_msgrcv(first,
363 (struct msgbuf __user *) ptr, 363 (struct msgbuf __user *) ptr,
364 second, fifth, third); 364 second, fifth, third);
365 } 365 }
366 case MSGGET: 366 case MSGGET:
367 return sys_msgget ((key_t) first, second); 367 return sys_msgget((key_t) first, second);
368 case MSGCTL: 368 case MSGCTL:
369 return sys_msgctl (first, second, 369 return sys_msgctl(first, second,
370 (struct msqid_ds __user *) ptr); 370 (struct msqid_ds __user *) ptr);
371 371
372 case SHMAT: 372 case SHMAT:
373 switch (version) { 373 switch (version) {
374 default: { 374 default: {
375 unsigned long raddr; 375 unsigned long raddr;
376 ret = do_shmat (first, (char __user *) ptr, second, 376 ret = do_shmat(first, (char __user *) ptr, second,
377 &raddr); 377 &raddr);
378 if (ret) 378 if (ret)
379 return ret; 379 return ret;
380 return put_user (raddr, (unsigned long __user *) third); 380 return put_user(raddr, (unsigned long __user *) third);
381 } 381 }
382 case 1: /* iBCS2 emulator entry point */ 382 case 1: /* iBCS2 emulator entry point */
383 if (!segment_eq(get_fs(), get_ds())) 383 if (!segment_eq(get_fs(), get_ds()))
384 return -EINVAL; 384 return -EINVAL;
385 return do_shmat (first, (char __user *) ptr, second, 385 return do_shmat(first, (char __user *) ptr, second,
386 (unsigned long *) third); 386 (unsigned long *) third);
387 } 387 }
388 case SHMDT: 388 case SHMDT:
389 return sys_shmdt ((char __user *)ptr); 389 return sys_shmdt((char __user *)ptr);
390 case SHMGET: 390 case SHMGET:
391 return sys_shmget (first, second, third); 391 return sys_shmget(first, second, third);
392 case SHMCTL: 392 case SHMCTL:
393 return sys_shmctl (first, second, 393 return sys_shmctl(first, second,
394 (struct shmid_ds __user *) ptr); 394 (struct shmid_ds __user *) ptr);
395 default: 395 default:
396 return -ENOSYS; 396 return -ENOSYS;
397 } 397 }
diff --git a/arch/mips/kernel/sysirix.c b/arch/mips/kernel/sysirix.c
index 93a148486f88..b50239574c95 100644
--- a/arch/mips/kernel/sysirix.c
+++ b/arch/mips/kernel/sysirix.c
@@ -486,10 +486,10 @@ asmlinkage int irix_syssgi(struct pt_regs *regs)
486 486
487 switch (arg1) { 487 switch (arg1) {
488 case SGI_INV_SIZEOF: 488 case SGI_INV_SIZEOF:
489 retval = sizeof (inventory_t); 489 retval = sizeof(inventory_t);
490 break; 490 break;
491 case SGI_INV_READ: 491 case SGI_INV_READ:
492 retval = dump_inventory_to_user (buffer, count); 492 retval = dump_inventory_to_user(buffer, count);
493 break; 493 break;
494 default: 494 default:
495 retval = -EINVAL; 495 retval = -EINVAL;
@@ -1042,9 +1042,9 @@ asmlinkage unsigned long irix_mmap32(unsigned long addr, size_t len, int prot,
1042 long max_size = offset + len; 1042 long max_size = offset + len;
1043 1043
1044 if (max_size > file->f_path.dentry->d_inode->i_size) { 1044 if (max_size > file->f_path.dentry->d_inode->i_size) {
1045 old_pos = sys_lseek (fd, max_size - 1, 0); 1045 old_pos = sys_lseek(fd, max_size - 1, 0);
1046 sys_write (fd, (void __user *) "", 1); 1046 sys_write(fd, (void __user *) "", 1);
1047 sys_lseek (fd, old_pos, 0); 1047 sys_lseek(fd, old_pos, 0);
1048 } 1048 }
1049 } 1049 }
1050 } 1050 }
@@ -1176,7 +1176,7 @@ static int irix_xstat32_xlate(struct kstat *stat, void __user *ubuf)
1176 ub.st_ctime1 = stat->atime.tv_nsec; 1176 ub.st_ctime1 = stat->atime.tv_nsec;
1177 ub.st_blksize = stat->blksize; 1177 ub.st_blksize = stat->blksize;
1178 ub.st_blocks = stat->blocks; 1178 ub.st_blocks = stat->blocks;
1179 strcpy (ub.st_fstype, "efs"); 1179 strcpy(ub.st_fstype, "efs");
1180 1180
1181 return copy_to_user(ubuf, &ub, sizeof(ub)) ? -EFAULT : 0; 1181 return copy_to_user(ubuf, &ub, sizeof(ub)) ? -EFAULT : 0;
1182} 1182}
@@ -1208,7 +1208,7 @@ static int irix_xstat64_xlate(struct kstat *stat, void __user *ubuf)
1208 ks.st_nlink = (u32) stat->nlink; 1208 ks.st_nlink = (u32) stat->nlink;
1209 ks.st_uid = (s32) stat->uid; 1209 ks.st_uid = (s32) stat->uid;
1210 ks.st_gid = (s32) stat->gid; 1210 ks.st_gid = (s32) stat->gid;
1211 ks.st_rdev = sysv_encode_dev (stat->rdev); 1211 ks.st_rdev = sysv_encode_dev(stat->rdev);
1212 ks.st_pad2[0] = ks.st_pad2[1] = 0; 1212 ks.st_pad2[0] = ks.st_pad2[1] = 0;
1213 ks.st_size = (long long) stat->size; 1213 ks.st_size = (long long) stat->size;
1214 ks.st_pad3 = 0; 1214 ks.st_pad3 = 0;
@@ -1527,9 +1527,9 @@ asmlinkage int irix_mmap64(struct pt_regs *regs)
1527 long max_size = off2 + len; 1527 long max_size = off2 + len;
1528 1528
1529 if (max_size > file->f_path.dentry->d_inode->i_size) { 1529 if (max_size > file->f_path.dentry->d_inode->i_size) {
1530 old_pos = sys_lseek (fd, max_size - 1, 0); 1530 old_pos = sys_lseek(fd, max_size - 1, 0);
1531 sys_write (fd, (void __user *) "", 1); 1531 sys_write(fd, (void __user *) "", 1);
1532 sys_lseek (fd, old_pos, 0); 1532 sys_lseek(fd, old_pos, 0);
1533 } 1533 }
1534 } 1534 }
1535 } 1535 }
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 369a5f9ad268..5892491b40eb 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -149,7 +149,7 @@ EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
149 * Possibly handle a performance counter interrupt. 149 * Possibly handle a performance counter interrupt.
150 * Return true if the timer interrupt should not be checked 150 * Return true if the timer interrupt should not be checked
151 */ 151 */
152static inline int handle_perf_irq (int r2) 152static inline int handle_perf_irq(int r2)
153{ 153{
154 /* 154 /*
155 * The performance counter overflow interrupt may be shared with the 155 * The performance counter overflow interrupt may be shared with the
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index ac762d8d802d..b3e408b54c24 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -627,7 +627,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
627 lose_fpu(1); 627 lose_fpu(1);
628 628
629 /* Run the emulator */ 629 /* Run the emulator */
630 sig = fpu_emulator_cop1Handler (regs, &current->thread.fpu, 1); 630 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1);
631 631
632 /* 632 /*
633 * We can't allow the emulated instruction to leave any of 633 * We can't allow the emulated instruction to leave any of
@@ -1165,11 +1165,11 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1165 1165
1166 if (cpu_has_veic) { 1166 if (cpu_has_veic) {
1167 if (board_bind_eic_interrupt) 1167 if (board_bind_eic_interrupt)
1168 board_bind_eic_interrupt (n, srs); 1168 board_bind_eic_interrupt(n, srs);
1169 } else if (cpu_has_vint) { 1169 } else if (cpu_has_vint) {
1170 /* SRSMap is only defined if shadow sets are implemented */ 1170 /* SRSMap is only defined if shadow sets are implemented */
1171 if (mips_srs_max() > 1) 1171 if (mips_srs_max() > 1)
1172 change_c0_srsmap (0xf << n*4, srs << n*4); 1172 change_c0_srsmap(0xf << n*4, srs << n*4);
1173 } 1173 }
1174 1174
1175 if (srs == 0) { 1175 if (srs == 0) {
@@ -1198,10 +1198,10 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1198 * Sigh... panicing won't help as the console 1198 * Sigh... panicing won't help as the console
1199 * is probably not configured :( 1199 * is probably not configured :(
1200 */ 1200 */
1201 panic ("VECTORSPACING too small"); 1201 panic("VECTORSPACING too small");
1202 } 1202 }
1203 1203
1204 memcpy (b, &except_vec_vi, handler_len); 1204 memcpy(b, &except_vec_vi, handler_len);
1205#ifdef CONFIG_MIPS_MT_SMTC 1205#ifdef CONFIG_MIPS_MT_SMTC
1206 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ 1206 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1207 1207
@@ -1370,9 +1370,9 @@ void __init per_cpu_trap_init(void)
1370#endif /* CONFIG_MIPS_MT_SMTC */ 1370#endif /* CONFIG_MIPS_MT_SMTC */
1371 1371
1372 if (cpu_has_veic || cpu_has_vint) { 1372 if (cpu_has_veic || cpu_has_vint) {
1373 write_c0_ebase (ebase); 1373 write_c0_ebase(ebase);
1374 /* Setting vector spacing enables EI/VI mode */ 1374 /* Setting vector spacing enables EI/VI mode */
1375 change_c0_intctl (0x3e0, VECTORSPACING); 1375 change_c0_intctl(0x3e0, VECTORSPACING);
1376 } 1376 }
1377 if (cpu_has_divec) { 1377 if (cpu_has_divec) {
1378 if (cpu_has_mipsmt) { 1378 if (cpu_has_mipsmt) {
@@ -1390,8 +1390,8 @@ void __init per_cpu_trap_init(void)
1390 * o read IntCtl.IPPCI to determine the performance counter interrupt 1390 * o read IntCtl.IPPCI to determine the performance counter interrupt
1391 */ 1391 */
1392 if (cpu_has_mips_r2) { 1392 if (cpu_has_mips_r2) {
1393 cp0_compare_irq = (read_c0_intctl () >> 29) & 7; 1393 cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
1394 cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7; 1394 cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
1395 if (cp0_perfcount_irq == cp0_compare_irq) 1395 if (cp0_perfcount_irq == cp0_compare_irq)
1396 cp0_perfcount_irq = -1; 1396 cp0_perfcount_irq = -1;
1397 } else { 1397 } else {
@@ -1429,7 +1429,7 @@ void __init per_cpu_trap_init(void)
1429} 1429}
1430 1430
1431/* Install CPU exception handler */ 1431/* Install CPU exception handler */
1432void __init set_handler (unsigned long offset, void *addr, unsigned long size) 1432void __init set_handler(unsigned long offset, void *addr, unsigned long size)
1433{ 1433{
1434 memcpy((void *)(ebase + offset), addr, size); 1434 memcpy((void *)(ebase + offset), addr, size);
1435 flush_icache_range(ebase + offset, ebase + offset + size); 1435 flush_icache_range(ebase + offset, ebase + offset + size);
@@ -1439,7 +1439,7 @@ static char panic_null_cerr[] __initdata =
1439 "Trying to set NULL cache error exception handler"; 1439 "Trying to set NULL cache error exception handler";
1440 1440
1441/* Install uncached CPU exception handler */ 1441/* Install uncached CPU exception handler */
1442void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size) 1442void __init set_uncached_handler(unsigned long offset, void *addr, unsigned long size)
1443{ 1443{
1444#ifdef CONFIG_32BIT 1444#ifdef CONFIG_32BIT
1445 unsigned long uncached_ebase = KSEG1ADDR(ebase); 1445 unsigned long uncached_ebase = KSEG1ADDR(ebase);
@@ -1470,7 +1470,7 @@ void __init trap_init(void)
1470 unsigned long i; 1470 unsigned long i;
1471 1471
1472 if (cpu_has_veic || cpu_has_vint) 1472 if (cpu_has_veic || cpu_has_vint)
1473 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64); 1473 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);
1474 else 1474 else
1475 ebase = CAC_BASE; 1475 ebase = CAC_BASE;
1476 1476
@@ -1496,7 +1496,7 @@ void __init trap_init(void)
1496 * destination. 1496 * destination.
1497 */ 1497 */
1498 if (cpu_has_ejtag && board_ejtag_handler_setup) 1498 if (cpu_has_ejtag && board_ejtag_handler_setup)
1499 board_ejtag_handler_setup (); 1499 board_ejtag_handler_setup();
1500 1500
1501 /* 1501 /*
1502 * Only some CPUs have the watch exceptions. 1502 * Only some CPUs have the watch exceptions.
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index d34b1fb3665d..c327b21bca81 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -481,7 +481,7 @@ fault:
481 if (fixup_exception(regs)) 481 if (fixup_exception(regs))
482 return; 482 return;
483 483
484 die_if_kernel ("Unhandled kernel unaligned access", regs); 484 die_if_kernel("Unhandled kernel unaligned access", regs);
485 send_sig(SIGSEGV, current, 1); 485 send_sig(SIGSEGV, current, 1);
486 486
487 return; 487 return;
diff --git a/arch/mips/lib/ucmpdi2.c b/arch/mips/lib/ucmpdi2.c
index e2ff6072b5a3..b33d8569bcb0 100644
--- a/arch/mips/lib/ucmpdi2.c
+++ b/arch/mips/lib/ucmpdi2.c
@@ -2,7 +2,7 @@
2 2
3#include "libgcc.h" 3#include "libgcc.h"
4 4
5word_type __ucmpdi2 (unsigned long long a, unsigned long long b) 5word_type __ucmpdi2(unsigned long long a, unsigned long long b)
6{ 6{
7 const DWunion au = {.ll = a}; 7 const DWunion au = {.ll = a};
8 const DWunion bu = {.ll = b}; 8 const DWunion bu = {.ll = b};
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 17419e11ecad..c44e9cc2b19c 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -549,16 +549,16 @@ static const unsigned char cmptab[8] = {
549 */ 549 */
550 550
551#define DEF3OP(name, p, f1, f2, f3) \ 551#define DEF3OP(name, p, f1, f2, f3) \
552static ieee754##p fpemu_##p##_##name (ieee754##p r, ieee754##p s, \ 552static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \
553 ieee754##p t) \ 553 ieee754##p t) \
554{ \ 554{ \
555 struct _ieee754_csr ieee754_csr_save; \ 555 struct _ieee754_csr ieee754_csr_save; \
556 s = f1 (s, t); \ 556 s = f1(s, t); \
557 ieee754_csr_save = ieee754_csr; \ 557 ieee754_csr_save = ieee754_csr; \
558 s = f2 (s, r); \ 558 s = f2(s, r); \
559 ieee754_csr_save.cx |= ieee754_csr.cx; \ 559 ieee754_csr_save.cx |= ieee754_csr.cx; \
560 ieee754_csr_save.sx |= ieee754_csr.sx; \ 560 ieee754_csr_save.sx |= ieee754_csr.sx; \
561 s = f3 (s); \ 561 s = f3(s); \
562 ieee754_csr.cx |= ieee754_csr_save.cx; \ 562 ieee754_csr.cx |= ieee754_csr_save.cx; \
563 ieee754_csr.sx |= ieee754_csr_save.sx; \ 563 ieee754_csr.sx |= ieee754_csr_save.sx; \
564 return s; \ 564 return s; \
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index 3c692abc2553..6fb29c3ff62d 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -112,7 +112,7 @@ static inline void atlas_hw0_irqdispatch(void)
112 112
113static inline int clz(unsigned long x) 113static inline int clz(unsigned long x)
114{ 114{
115 __asm__ ( 115 __asm__(
116 " .set push \n" 116 " .set push \n"
117 " .set mips32 \n" 117 " .set mips32 \n"
118 " clz %0, %1 \n" 118 " clz %0, %1 \n"
@@ -194,7 +194,7 @@ asmlinkage void plat_irq_dispatch(void)
194 spurious_interrupt(); 194 spurious_interrupt();
195} 195}
196 196
197static inline void init_atlas_irqs (int base) 197static inline void init_atlas_irqs(int base)
198{ 198{
199 int i; 199 int i;
200 200
@@ -249,21 +249,21 @@ void __init arch_init_irq(void)
249 case MIPS_REVISION_CORID_CORE_24K: 249 case MIPS_REVISION_CORID_CORE_24K:
250 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 250 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
251 if (cpu_has_veic) 251 if (cpu_has_veic)
252 init_msc_irqs (MSC01E_INT_BASE, MSC01E_INT_BASE, 252 init_msc_irqs(MSC01E_INT_BASE, MSC01E_INT_BASE,
253 msc_eicirqmap, msc_nr_eicirqs); 253 msc_eicirqmap, msc_nr_eicirqs);
254 else 254 else
255 init_msc_irqs (MSC01E_INT_BASE, MSC01C_INT_BASE, 255 init_msc_irqs(MSC01E_INT_BASE, MSC01C_INT_BASE,
256 msc_irqmap, msc_nr_irqs); 256 msc_irqmap, msc_nr_irqs);
257 } 257 }
258 258
259 if (cpu_has_veic) { 259 if (cpu_has_veic) {
260 set_vi_handler (MSC01E_INT_ATLAS, atlas_hw0_irqdispatch); 260 set_vi_handler(MSC01E_INT_ATLAS, atlas_hw0_irqdispatch);
261 setup_irq (MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq); 261 setup_irq(MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq);
262 } else if (cpu_has_vint) { 262 } else if (cpu_has_vint) {
263 set_vi_handler (MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch); 263 set_vi_handler(MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch);
264#ifdef CONFIG_MIPS_MT_SMTC 264#ifdef CONFIG_MIPS_MT_SMTC
265 setup_irq_smtc (MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, 265 setup_irq_smtc(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS,
266 &atlasirq, (0x100 << MIPSCPU_INT_ATLAS)); 266 &atlasirq, (0x100 << MIPSCPU_INT_ATLAS));
267#else /* Not SMTC */ 267#else /* Not SMTC */
268 setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq); 268 setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
269#endif /* CONFIG_MIPS_MT_SMTC */ 269#endif /* CONFIG_MIPS_MT_SMTC */
diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c
index 86bfc0548164..e405d112a067 100644
--- a/arch/mips/mips-boards/atlas/atlas_setup.c
+++ b/arch/mips/mips-boards/atlas/atlas_setup.c
@@ -55,7 +55,7 @@ void __init plat_mem_setup(void)
55 55
56 ioport_resource.end = 0x7fffffff; 56 ioport_resource.end = 0x7fffffff;
57 57
58 serial_init (); 58 serial_init();
59 59
60#ifdef CONFIG_KGDB 60#ifdef CONFIG_KGDB
61 kgdb_config(); 61 kgdb_config();
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index e2c7147fedf7..30f1f54cb68b 100644
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -166,15 +166,15 @@ static void __init console_config(void)
166 bits = '8'; 166 bits = '8';
167 if (flow == '\0') 167 if (flow == '\0')
168 flow = 'r'; 168 flow = 'r';
169 sprintf (console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); 169 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow);
170 strcat (prom_getcmdline(), console_string); 170 strcat(prom_getcmdline(), console_string);
171 pr_info("Config serial console:%s\n", console_string); 171 pr_info("Config serial console:%s\n", console_string);
172 } 172 }
173} 173}
174#endif 174#endif
175 175
176#ifdef CONFIG_KGDB 176#ifdef CONFIG_KGDB
177void __init kgdb_config (void) 177void __init kgdb_config(void)
178{ 178{
179 extern int (*generic_putDebugChar)(char); 179 extern int (*generic_putDebugChar)(char);
180 extern char (*generic_getDebugChar)(void); 180 extern char (*generic_getDebugChar)(void);
@@ -218,7 +218,7 @@ void __init kgdb_config (void)
218 { 218 {
219 char *s; 219 char *s;
220 for (s = "Please connect GDB to this port\r\n"; *s; ) 220 for (s = "Please connect GDB to this port\r\n"; *s; )
221 generic_putDebugChar (*s++); 221 generic_putDebugChar(*s++);
222 } 222 }
223 223
224 /* Breakpoint is invoked after interrupts are initialised */ 224 /* Breakpoint is invoked after interrupts are initialised */
@@ -226,7 +226,7 @@ void __init kgdb_config (void)
226} 226}
227#endif 227#endif
228 228
229void __init mips_nmi_setup (void) 229void __init mips_nmi_setup(void)
230{ 230{
231 void *base; 231 void *base;
232 extern char except_vec_nmi; 232 extern char except_vec_nmi;
@@ -238,7 +238,7 @@ void __init mips_nmi_setup (void)
238 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 238 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
239} 239}
240 240
241void __init mips_ejtag_setup (void) 241void __init mips_ejtag_setup(void)
242{ 242{
243 void *base; 243 void *base;
244 extern char except_vec_ejtag_debug; 244 extern char except_vec_ejtag_debug;
diff --git a/arch/mips/mips-boards/generic/memory.c b/arch/mips/mips-boards/generic/memory.c
index ae39953da2c4..dc272c188233 100644
--- a/arch/mips/mips-boards/generic/memory.c
+++ b/arch/mips/mips-boards/generic/memory.c
@@ -125,7 +125,7 @@ struct prom_pmemblock * __init prom_getmdesc(void)
125 return &mdesc[0]; 125 return &mdesc[0];
126} 126}
127 127
128static int __init prom_memtype_classify (unsigned int type) 128static int __init prom_memtype_classify(unsigned int type)
129{ 129{
130 switch (type) { 130 switch (type) {
131 case yamon_free: 131 case yamon_free:
@@ -158,7 +158,7 @@ void __init prom_meminit(void)
158 long type; 158 long type;
159 unsigned long base, size; 159 unsigned long base, size;
160 160
161 type = prom_memtype_classify (p->type); 161 type = prom_memtype_classify(p->type);
162 base = p->base; 162 base = p->base;
163 size = p->size; 163 size = p->size;
164 164
diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c
index c9852206890a..b9743190609a 100644
--- a/arch/mips/mips-boards/generic/pci.c
+++ b/arch/mips/mips-boards/generic/pci.c
@@ -239,5 +239,5 @@ void __init mips_pcibios_init(void)
239 iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ 239 iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
240 ioport_resource.end = controller->io_resource->end; 240 ioport_resource.end = controller->io_resource->end;
241 241
242 register_pci_controller (controller); 242 register_pci_controller(controller);
243} 243}
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index 4fab3b2e8736..1d00b778ff1e 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -134,7 +134,7 @@ void __init plat_time_init(void)
134 /* Set Data mode - binary. */ 134 /* Set Data mode - binary. */
135 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); 135 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
136 136
137 est_freq = estimate_cpu_frequency (); 137 est_freq = estimate_cpu_frequency();
138 138
139 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, 139 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
140 (est_freq%1000000)*100/1000000); 140 (est_freq%1000000)*100/1000000);
@@ -166,7 +166,7 @@ void __init plat_perf_setup(void)
166 166
167#ifdef MSC01E_INT_BASE 167#ifdef MSC01E_INT_BASE
168 if (cpu_has_veic) { 168 if (cpu_has_veic) {
169 set_vi_handler (MSC01E_INT_PERFCTR, mips_perf_dispatch); 169 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
170 cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; 170 cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
171 } else 171 } else
172#endif 172#endif
@@ -183,7 +183,7 @@ void __init plat_timer_setup(struct irqaction *irq)
183{ 183{
184#ifdef MSC01E_INT_BASE 184#ifdef MSC01E_INT_BASE
185 if (cpu_has_veic) { 185 if (cpu_has_veic) {
186 set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); 186 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
187 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; 187 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
188 } 188 }
189 else 189 else
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index b73f21823c5e..8232392750a8 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -178,7 +178,7 @@ static void corehi_irqdispatch(void)
178 178
179static inline int clz(unsigned long x) 179static inline int clz(unsigned long x)
180{ 180{
181 __asm__ ( 181 __asm__(
182 " .set push \n" 182 " .set push \n"
183 " .set mips32 \n" 183 " .set mips32 \n"
184 " clz %0, %1 \n" 184 " clz %0, %1 \n"
@@ -303,32 +303,32 @@ void __init arch_init_irq(void)
303 case MIPS_REVISION_SCON_SOCIT: 303 case MIPS_REVISION_SCON_SOCIT:
304 case MIPS_REVISION_SCON_ROCIT: 304 case MIPS_REVISION_SCON_ROCIT:
305 if (cpu_has_veic) 305 if (cpu_has_veic)
306 init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); 306 init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
307 else 307 else
308 init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); 308 init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
309 break; 309 break;
310 310
311 case MIPS_REVISION_SCON_SOCITSC: 311 case MIPS_REVISION_SCON_SOCITSC:
312 case MIPS_REVISION_SCON_SOCITSCP: 312 case MIPS_REVISION_SCON_SOCITSCP:
313 if (cpu_has_veic) 313 if (cpu_has_veic)
314 init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); 314 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
315 else 315 else
316 init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); 316 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
317 } 317 }
318 318
319 if (cpu_has_veic) { 319 if (cpu_has_veic) {
320 set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch); 320 set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch);
321 set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch); 321 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
322 setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); 322 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
323 setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); 323 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
324 } 324 }
325 else if (cpu_has_vint) { 325 else if (cpu_has_vint) {
326 set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); 326 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
327 set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch); 327 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
328#ifdef CONFIG_MIPS_MT_SMTC 328#ifdef CONFIG_MIPS_MT_SMTC
329 setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq, 329 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
330 (0x100 << MIPSCPU_INT_I8259A)); 330 (0x100 << MIPSCPU_INT_I8259A));
331 setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, 331 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
332 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); 332 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
333 /* 333 /*
334 * Temporary hack to ensure that the subsidiary device 334 * Temporary hack to ensure that the subsidiary device
@@ -343,12 +343,12 @@ void __init arch_init_irq(void)
343 irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A); 343 irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
344 } 344 }
345#else /* Not SMTC */ 345#else /* Not SMTC */
346 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); 346 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
347 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); 347 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
348#endif /* CONFIG_MIPS_MT_SMTC */ 348#endif /* CONFIG_MIPS_MT_SMTC */
349 } 349 }
350 else { 350 else {
351 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); 351 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
352 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); 352 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
353 } 353 }
354} 354}
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index a5a5a43a1984..e243d5efcb38 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -99,7 +99,7 @@ void __init plat_mem_setup(void)
99 enable_dma(4); 99 enable_dma(4);
100 100
101#ifdef CONFIG_KGDB 101#ifdef CONFIG_KGDB
102 kgdb_config (); 102 kgdb_config();
103#endif 103#endif
104 104
105 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { 105 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
@@ -108,7 +108,7 @@ void __init plat_mem_setup(void)
108 argptr = prom_getcmdline(); 108 argptr = prom_getcmdline();
109 if (strstr(argptr, "debug")) { 109 if (strstr(argptr, "debug")) {
110 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; 110 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
111 printk ("Enabled Bonito debug mode\n"); 111 printk("Enabled Bonito debug mode\n");
112 } 112 }
113 else 113 else
114 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; 114 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
@@ -159,14 +159,14 @@ void __init plat_mem_setup(void)
159 if (pciclock != 33 && !strstr (argptr, "idebus=")) { 159 if (pciclock != 33 && !strstr (argptr, "idebus=")) {
160 printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock); 160 printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock);
161 argptr += strlen(argptr); 161 argptr += strlen(argptr);
162 sprintf (argptr, " idebus=%d", pciclock); 162 sprintf(argptr, " idebus=%d", pciclock);
163 if (pciclock < 20 || pciclock > 66) 163 if (pciclock < 20 || pciclock > 66)
164 printk ("WARNING: IDE timing calculations will be incorrect\n"); 164 printk("WARNING: IDE timing calculations will be incorrect\n");
165 } 165 }
166 } 166 }
167#endif 167#endif
168#ifdef CONFIG_BLK_DEV_FD 168#ifdef CONFIG_BLK_DEV_FD
169 fd_activate (); 169 fd_activate();
170#endif 170#endif
171#ifdef CONFIG_VT 171#ifdef CONFIG_VT
172#if defined(CONFIG_VGA_CONSOLE) 172#if defined(CONFIG_VGA_CONSOLE)
diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c
index 9ca0f82f1360..ec6dd194c14a 100644
--- a/arch/mips/mips-boards/sead/sead_int.c
+++ b/arch/mips/mips-boards/sead/sead_int.c
@@ -31,7 +31,7 @@
31 31
32static inline int clz(unsigned long x) 32static inline int clz(unsigned long x)
33{ 33{
34 __asm__ ( 34 __asm__(
35 " .set push \n" 35 " .set push \n"
36 " .set mips32 \n" 36 " .set mips32 \n"
37 " clz %0, %1 \n" 37 " clz %0, %1 \n"
diff --git a/arch/mips/mips-boards/sead/sead_setup.c b/arch/mips/mips-boards/sead/sead_setup.c
index fad58972f3ac..1fb61b852304 100644
--- a/arch/mips/mips-boards/sead/sead_setup.c
+++ b/arch/mips/mips-boards/sead/sead_setup.c
@@ -49,7 +49,7 @@ void __init plat_mem_setup(void)
49{ 49{
50 ioport_resource.end = 0x7fffffff; 50 ioport_resource.end = 0x7fffffff;
51 51
52 serial_init (); 52 serial_init();
53 53
54 mips_reboot_setup(); 54 mips_reboot_setup();
55} 55}
diff --git a/arch/mips/mipssim/sim_int.c b/arch/mips/mipssim/sim_int.c
index 5cbc3509ab52..46067ad542dc 100644
--- a/arch/mips/mipssim/sim_int.c
+++ b/arch/mips/mipssim/sim_int.c
@@ -25,7 +25,7 @@
25 25
26static inline int clz(unsigned long x) 26static inline int clz(unsigned long x)
27{ 27{
28 __asm__ ( 28 __asm__(
29 " .set push \n" 29 " .set push \n"
30 " .set mips32 \n" 30 " .set mips32 \n"
31 " clz %0, %1 \n" 31 " clz %0, %1 \n"
diff --git a/arch/mips/mipssim/sim_mem.c b/arch/mips/mipssim/sim_mem.c
index 2312483eb838..953d836a7713 100644
--- a/arch/mips/mipssim/sim_mem.c
+++ b/arch/mips/mipssim/sim_mem.c
@@ -69,7 +69,7 @@ struct prom_pmemblock * __init prom_getmdesc(void)
69 return &mdesc[0]; 69 return &mdesc[0];
70} 70}
71 71
72static int __init prom_memtype_classify (unsigned int type) 72static int __init prom_memtype_classify(unsigned int type)
73{ 73{
74 switch (type) { 74 switch (type) {
75 case simmem_free: 75 case simmem_free:
@@ -90,7 +90,7 @@ void __init prom_meminit(void)
90 long type; 90 long type;
91 unsigned long base, size; 91 unsigned long base, size;
92 92
93 type = prom_memtype_classify (p->type); 93 type = prom_memtype_classify(p->type);
94 base = p->base; 94 base = p->base;
95 size = p->size; 95 size = p->size;
96 96
diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c
index 3625f7d49035..e7fa0d1078a3 100644
--- a/arch/mips/mipssim/sim_time.c
+++ b/arch/mips/mipssim/sim_time.c
@@ -84,7 +84,7 @@ void __init plat_time_init(void)
84 /* Set Data mode - binary. */ 84 /* Set Data mode - binary. */
85 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); 85 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
86 86
87 est_freq = estimate_cpu_frequency (); 87 est_freq = estimate_cpu_frequency();
88 88
89 printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000, 89 printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000,
90 (est_freq % 1000000) * 100 / 1000000); 90 (est_freq % 1000000) * 100 / 1000000);
diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index 59868a1edf66..c55312f6fd3a 100644
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -121,7 +121,7 @@ static void r3k_flush_icache_range(unsigned long start, unsigned long end)
121 write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC); 121 write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
122 122
123 for (i = 0; i < size; i += 0x080) { 123 for (i = 0; i < size; i += 0x080) {
124 asm ( "sb\t$0, 0x000(%0)\n\t" 124 asm( "sb\t$0, 0x000(%0)\n\t"
125 "sb\t$0, 0x004(%0)\n\t" 125 "sb\t$0, 0x004(%0)\n\t"
126 "sb\t$0, 0x008(%0)\n\t" 126 "sb\t$0, 0x008(%0)\n\t"
127 "sb\t$0, 0x00c(%0)\n\t" 127 "sb\t$0, 0x00c(%0)\n\t"
@@ -178,7 +178,7 @@ static void r3k_flush_dcache_range(unsigned long start, unsigned long end)
178 write_c0_status((ST0_ISC|flags)&~ST0_IEC); 178 write_c0_status((ST0_ISC|flags)&~ST0_IEC);
179 179
180 for (i = 0; i < size; i += 0x080) { 180 for (i = 0; i < size; i += 0x080) {
181 asm ( "sb\t$0, 0x000(%0)\n\t" 181 asm( "sb\t$0, 0x000(%0)\n\t"
182 "sb\t$0, 0x004(%0)\n\t" 182 "sb\t$0, 0x004(%0)\n\t"
183 "sb\t$0, 0x008(%0)\n\t" 183 "sb\t$0, 0x008(%0)\n\t"
184 "sb\t$0, 0x00c(%0)\n\t" 184 "sb\t$0, 0x00c(%0)\n\t"
@@ -217,8 +217,8 @@ static void r3k_flush_dcache_range(unsigned long start, unsigned long end)
217 write_c0_status(flags); 217 write_c0_status(flags);
218} 218}
219 219
220static inline unsigned long get_phys_page (unsigned long addr, 220static inline unsigned long get_phys_page(unsigned long addr,
221 struct mm_struct *mm) 221 struct mm_struct *mm)
222{ 222{
223 pgd_t *pgd; 223 pgd_t *pgd;
224 pud_t *pud; 224 pud_t *pud;
@@ -281,13 +281,13 @@ static void r3k_flush_cache_sigtramp(unsigned long addr)
281 write_c0_status(flags&~ST0_IEC); 281 write_c0_status(flags&~ST0_IEC);
282 282
283 /* Fill the TLB to avoid an exception with caches isolated. */ 283 /* Fill the TLB to avoid an exception with caches isolated. */
284 asm ( "lw\t$0, 0x000(%0)\n\t" 284 asm( "lw\t$0, 0x000(%0)\n\t"
285 "lw\t$0, 0x004(%0)\n\t" 285 "lw\t$0, 0x004(%0)\n\t"
286 : : "r" (addr) ); 286 : : "r" (addr) );
287 287
288 write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC); 288 write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
289 289
290 asm ( "sb\t$0, 0x000(%0)\n\t" 290 asm( "sb\t$0, 0x000(%0)\n\t"
291 "sb\t$0, 0x004(%0)\n\t" 291 "sb\t$0, 0x004(%0)\n\t"
292 : : "r" (addr) ); 292 : : "r" (addr) );
293 293
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 42b50964c644..c13170bc675c 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -102,7 +102,7 @@ static inline int __init mips_sc_probe(void)
102 102
103int __init mips_sc_init(void) 103int __init mips_sc_init(void)
104{ 104{
105 int found = mips_sc_probe (); 105 int found = mips_sc_probe();
106 if (found) { 106 if (found) {
107 mips_sc_enable(); 107 mips_sc_enable();
108 bcops = &mips_sc_ops; 108 bcops = &mips_sc_ops;
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index dcd6913dc1ff..74ae0348cc92 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -491,7 +491,7 @@ void __init tlb_init(void)
491 int wired = current_cpu_data.tlbsize - ntlb; 491 int wired = current_cpu_data.tlbsize - ntlb;
492 write_c0_wired(wired); 492 write_c0_wired(wired);
493 write_c0_index(wired-1); 493 write_c0_index(wired-1);
494 printk ("Restricting TLB to %d entries\n", ntlb); 494 printk("Restricting TLB to %d entries\n", ntlb);
495 } else 495 } else
496 printk("Ignoring invalid argument ntlb=%d\n", ntlb); 496 printk("Ignoring invalid argument ntlb=%d\n", ntlb);
497 } 497 }
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 6383000422ab..423bc2c473df 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -118,7 +118,7 @@ static void mipsxx_reg_setup(struct op_counter_config *ctr)
118 118
119/* Program all of the registers in preparation for enabling profiling. */ 119/* Program all of the registers in preparation for enabling profiling. */
120 120
121static void mipsxx_cpu_setup (void *args) 121static void mipsxx_cpu_setup(void *args)
122{ 122{
123 unsigned int counters = op_model_mipsxx_ops.num_counters; 123 unsigned int counters = op_model_mipsxx_ops.num_counters;
124 124
diff --git a/arch/mips/oprofile/op_model_rm9000.c b/arch/mips/oprofile/op_model_rm9000.c
index d29040a56aea..a45d3202894f 100644
--- a/arch/mips/oprofile/op_model_rm9000.c
+++ b/arch/mips/oprofile/op_model_rm9000.c
@@ -60,7 +60,7 @@ static void rm9000_reg_setup(struct op_counter_config *ctr)
60 60
61/* Program all of the registers in preparation for enabling profiling. */ 61/* Program all of the registers in preparation for enabling profiling. */
62 62
63static void rm9000_cpu_setup (void *args) 63static void rm9000_cpu_setup(void *args)
64{ 64{
65 uint64_t perfcount; 65 uint64_t perfcount;
66 66
diff --git a/arch/mips/pci/fixup-atlas.c b/arch/mips/pci/fixup-atlas.c
index 45224fd2c7ba..506e883a8c71 100644
--- a/arch/mips/pci/fixup-atlas.c
+++ b/arch/mips/pci/fixup-atlas.c
@@ -77,12 +77,12 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
77 * code, but it is better than nothing... 77 * code, but it is better than nothing...
78 */ 78 */
79 79
80static void atlas_saa9730_base_fixup (struct pci_dev *pdev) 80static void atlas_saa9730_base_fixup(struct pci_dev *pdev)
81{ 81{
82 extern void *saa9730_base; 82 extern void *saa9730_base;
83 if (pdev->bus == 0 && PCI_SLOT(pdev->devfn) == 19) 83 if (pdev->bus == 0 && PCI_SLOT(pdev->devfn) == 19)
84 (void) pci_read_config_dword (pdev, 0x14, (u32 *)&saa9730_base); 84 (void) pci_read_config_dword(pdev, 0x14, (u32 *)&saa9730_base);
85 printk ("saa9730_base = %x\n", saa9730_base); 85 printk("saa9730_base = %x\n", saa9730_base);
86} 86}
87 87
88DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA9730, 88DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA9730,
diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c
index 7932dfe5eb9b..6b29904acf45 100644
--- a/arch/mips/pci/ops-au1000.c
+++ b/arch/mips/pci/ops-au1000.c
@@ -112,7 +112,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
112 first_cfg = 0; 112 first_cfg = 0;
113 pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); 113 pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
114 if (!pci_cfg_vm) 114 if (!pci_cfg_vm)
115 panic (KERN_ERR "PCI unable to get vm area\n"); 115 panic(KERN_ERR "PCI unable to get vm area\n");
116 pci_cfg_wired_entry = read_c0_wired(); 116 pci_cfg_wired_entry = read_c0_wired();
117 add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K); 117 add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K);
118 last_entryLo0 = last_entryLo1 = 0xffffffff; 118 last_entryLo0 = last_entryLo1 = 0xffffffff;
diff --git a/arch/mips/pci/ops-sni.c b/arch/mips/pci/ops-sni.c
index fa2d2c60f797..97ed25b92edf 100644
--- a/arch/mips/pci/ops-sni.c
+++ b/arch/mips/pci/ops-sni.c
@@ -70,13 +70,13 @@ static int pcimt_write(struct pci_bus *bus, unsigned int devfn, int reg,
70 70
71 switch (size) { 71 switch (size) {
72 case 1: 72 case 1:
73 outb (val, PCIMT_CONFIG_DATA + (reg & 3)); 73 outb(val, PCIMT_CONFIG_DATA + (reg & 3));
74 break; 74 break;
75 case 2: 75 case 2:
76 outw (val, PCIMT_CONFIG_DATA + (reg & 2)); 76 outw(val, PCIMT_CONFIG_DATA + (reg & 2));
77 break; 77 break;
78 case 4: 78 case 4:
79 outl (val, PCIMT_CONFIG_DATA); 79 outl(val, PCIMT_CONFIG_DATA);
80 break; 80 break;
81 } 81 }
82 82
@@ -93,7 +93,7 @@ static int pcit_set_config_address(unsigned int busno, unsigned int devfn, int r
93 if ((devfn > 255) || (reg > 255) || (busno > 255)) 93 if ((devfn > 255) || (reg > 255) || (busno > 255))
94 return PCIBIOS_BAD_REGISTER_NUMBER; 94 return PCIBIOS_BAD_REGISTER_NUMBER;
95 95
96 outl ((1 << 31) | ((busno & 0xff) << 16) | ((devfn & 0xff) << 8) | (reg & 0xfc), 0xcf8); 96 outl((1 << 31) | ((busno & 0xff) << 16) | ((devfn & 0xff) << 8) | (reg & 0xfc), 0xcf8);
97 return PCIBIOS_SUCCESSFUL; 97 return PCIBIOS_SUCCESSFUL;
98} 98}
99 99
@@ -108,12 +108,12 @@ static int pcit_read(struct pci_bus *bus, unsigned int devfn, int reg,
108 * we don't do it, we will get a data bus error 108 * we don't do it, we will get a data bus error
109 */ 109 */
110 if (bus->number == 0) { 110 if (bus->number == 0) {
111 pcit_set_config_address (0, 0, 0x68); 111 pcit_set_config_address(0, 0, 0x68);
112 outl (inl (0xcfc) | 0xc0000000, 0xcfc); 112 outl(inl(0xcfc) | 0xc0000000, 0xcfc);
113 if ((res = pcit_set_config_address(0, devfn, 0))) 113 if ((res = pcit_set_config_address(0, devfn, 0)))
114 return res; 114 return res;
115 outl (0xffffffff, 0xcfc); 115 outl(0xffffffff, 0xcfc);
116 pcit_set_config_address (0, 0, 0x68); 116 pcit_set_config_address(0, 0, 0x68);
117 if (inl(0xcfc) & 0x100000) 117 if (inl(0xcfc) & 0x100000)
118 return PCIBIOS_DEVICE_NOT_FOUND; 118 return PCIBIOS_DEVICE_NOT_FOUND;
119 } 119 }
@@ -144,13 +144,13 @@ static int pcit_write(struct pci_bus *bus, unsigned int devfn, int reg,
144 144
145 switch (size) { 145 switch (size) {
146 case 1: 146 case 1:
147 outb (val, PCIMT_CONFIG_DATA + (reg & 3)); 147 outb(val, PCIMT_CONFIG_DATA + (reg & 3));
148 break; 148 break;
149 case 2: 149 case 2:
150 outw (val, PCIMT_CONFIG_DATA + (reg & 2)); 150 outw(val, PCIMT_CONFIG_DATA + (reg & 2));
151 break; 151 break;
152 case 4: 152 case 4:
153 outl (val, PCIMT_CONFIG_DATA); 153 outl(val, PCIMT_CONFIG_DATA);
154 break; 154 break;
155 } 155 }
156 156
diff --git a/arch/mips/philips/pnx8550/common/proc.c b/arch/mips/philips/pnx8550/common/proc.c
index 92311e95b700..416f834784bc 100644
--- a/arch/mips/philips/pnx8550/common/proc.c
+++ b/arch/mips/philips/pnx8550/common/proc.c
@@ -27,7 +27,7 @@
27#include <uart.h> 27#include <uart.h>
28 28
29 29
30static int pnx8550_timers_read (char* page, char** start, off_t offset, int count, int* eof, void* data) 30static int pnx8550_timers_read(char* page, char** start, off_t offset, int count, int* eof, void* data)
31{ 31{
32 int len = 0; 32 int len = 0;
33 int configPR = read_c0_config7(); 33 int configPR = read_c0_config7();
@@ -48,7 +48,7 @@ static int pnx8550_timers_read (char* page, char** start, off_t offset, int coun
48 return len; 48 return len;
49} 49}
50 50
51static int pnx8550_registers_read (char* page, char** start, off_t offset, int count, int* eof, void* data) 51static int pnx8550_registers_read(char* page, char** start, off_t offset, int count, int* eof, void* data)
52{ 52{
53 int len = 0; 53 int len = 0;
54 54
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_usb.c b/arch/mips/pmc-sierra/msp71xx/msp_usb.c
index 21f9c70b6923..f7ca4f582331 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_usb.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_usb.c
@@ -58,7 +58,7 @@ static struct platform_device msp_usbhost_device = {
58 .dma_mask = &msp_usbhost_dma_mask, 58 .dma_mask = &msp_usbhost_dma_mask,
59 .coherent_dma_mask = DMA_32BIT_MASK, 59 .coherent_dma_mask = DMA_32BIT_MASK,
60 }, 60 },
61 .num_resources = ARRAY_SIZE (msp_usbhost_resources), 61 .num_resources = ARRAY_SIZE(msp_usbhost_resources),
62 .resource = msp_usbhost_resources, 62 .resource = msp_usbhost_resources,
63}; 63};
64#endif /* CONFIG_USB_EHCI_HCD */ 64#endif /* CONFIG_USB_EHCI_HCD */
@@ -86,7 +86,7 @@ static struct platform_device msp_usbdev_device = {
86 .dma_mask = &msp_usbdev_dma_mask, 86 .dma_mask = &msp_usbdev_dma_mask,
87 .coherent_dma_mask = DMA_32BIT_MASK, 87 .coherent_dma_mask = DMA_32BIT_MASK,
88 }, 88 },
89 .num_resources = ARRAY_SIZE (msp_usbdev_resources), 89 .num_resources = ARRAY_SIZE(msp_usbdev_resources),
90 .resource = msp_usbdev_resources, 90 .resource = msp_usbdev_resources,
91}; 91};
92#endif /* CONFIG_USB_GADGET */ 92#endif /* CONFIG_USB_GADGET */
@@ -129,7 +129,7 @@ static int __init msp_usb_setup(void)
129 ppfinit("platform add USB HOST done %s.\n", 129 ppfinit("platform add USB HOST done %s.\n",
130 msp_devs[0]->name); 130 msp_devs[0]->name);
131 131
132 result = platform_add_devices(msp_devs, ARRAY_SIZE (msp_devs)); 132 result = platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs));
133#endif /* CONFIG_USB_EHCI_HCD */ 133#endif /* CONFIG_USB_EHCI_HCD */
134 } 134 }
135#if defined(CONFIG_USB_GADGET) 135#if defined(CONFIG_USB_GADGET)
@@ -139,7 +139,7 @@ static int __init msp_usb_setup(void)
139 ppfinit("platform add USB DEVICE done %s.\n", 139 ppfinit("platform add USB DEVICE done %s.\n",
140 msp_devs[0]->name); 140 msp_devs[0]->name);
141 141
142 result = platform_add_devices(msp_devs, ARRAY_SIZE (msp_devs)); 142 result = platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs));
143 } 143 }
144#endif /* CONFIG_USB_GADGET */ 144#endif /* CONFIG_USB_GADGET */
145#endif /* CONFIG_USB_EHCI_HCD || CONFIG_USB_GADGET */ 145#endif /* CONFIG_USB_EHCI_HCD || CONFIG_USB_GADGET */
diff --git a/arch/mips/qemu/q-firmware.c b/arch/mips/qemu/q-firmware.c
index fb2a8673a6bf..c2239b417587 100644
--- a/arch/mips/qemu/q-firmware.c
+++ b/arch/mips/qemu/q-firmware.c
@@ -10,7 +10,7 @@ void __init prom_init(void)
10 cmdline = (int *) (CKSEG0 + (0x10 << 20) - 260); 10 cmdline = (int *) (CKSEG0 + (0x10 << 20) - 260);
11 if (*cmdline == 0x12345678) { 11 if (*cmdline == 0x12345678) {
12 if (*(char *)(cmdline + 1)) 12 if (*(char *)(cmdline + 1))
13 strcpy (arcs_cmdline, (char *)(cmdline + 1)); 13 strcpy(arcs_cmdline, (char *)(cmdline + 1));
14 add_memory_region(0x0<<20, cmdline[-1], BOOT_MEM_RAM); 14 add_memory_region(0x0<<20, cmdline[-1], BOOT_MEM_RAM);
15 } else { 15 } else {
16 add_memory_region(0x0<<20, 0x10<<20, BOOT_MEM_RAM); 16 add_memory_region(0x0<<20, 0x10<<20, BOOT_MEM_RAM);
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index 6b6e97b90c6e..26854fb11e7c 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -55,7 +55,7 @@ static char __init *decode_eisa_sig(unsigned long addr)
55 int i; 55 int i;
56 56
57 for (i = 0; i < 4; i++) { 57 for (i = 0; i < 4; i++) {
58 sig[i] = inb (addr + i); 58 sig[i] = inb(addr + i);
59 59
60 if (!i && (sig[0] & 0x80)) 60 if (!i && (sig[0] & 0x80))
61 return NULL; 61 return NULL;
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index f199da7e49cf..f6d9bf4b26e7 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -344,6 +344,6 @@ void __init arch_init_irq(void)
344 344
345#ifdef CONFIG_EISA 345#ifdef CONFIG_EISA
346 if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */ 346 if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */
347 ip22_eisa_init (); 347 ip22_eisa_init();
348#endif 348#endif
349} 349}
diff --git a/arch/mips/sgi-ip32/crime.c b/arch/mips/sgi-ip32/crime.c
index bff508704d03..563c614ad021 100644
--- a/arch/mips/sgi-ip32/crime.c
+++ b/arch/mips/sgi-ip32/crime.c
@@ -35,8 +35,8 @@ void __init crime_init(void)
35 id = crime->id; 35 id = crime->id;
36 rev = id & CRIME_ID_REV; 36 rev = id & CRIME_ID_REV;
37 id = (id & CRIME_ID_IDBITS) >> 4; 37 id = (id & CRIME_ID_IDBITS) >> 4;
38 printk (KERN_INFO "CRIME id %1x rev %d at 0x%0*lx\n", 38 printk(KERN_INFO "CRIME id %1x rev %d at 0x%0*lx\n",
39 id, rev, field, (unsigned long) CRIME_BASE); 39 id, rev, field, (unsigned long) CRIME_BASE);
40} 40}
41 41
42irqreturn_t crime_memerr_intr(unsigned int irq, void *dev_id) 42irqreturn_t crime_memerr_intr(unsigned int irq, void *dev_id)
@@ -96,7 +96,7 @@ irqreturn_t crime_cpuerr_intr(unsigned int irq, void *dev_id)
96 unsigned long addr = crime->cpu_error_addr & CRIME_CPU_ERROR_ADDR_MASK; 96 unsigned long addr = crime->cpu_error_addr & CRIME_CPU_ERROR_ADDR_MASK;
97 97
98 addr <<= 2; 98 addr <<= 2;
99 printk ("CRIME CPU error at 0x%09lx status 0x%08lx\n", addr, stat); 99 printk("CRIME CPU error at 0x%09lx status 0x%08lx\n", addr, stat);
100 crime->cpu_error_stat = 0; 100 crime->cpu_error_stat = 0;
101 101
102 return IRQ_HANDLED; 102 return IRQ_HANDLED;
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index 002095b364a3..7f4b793c3df3 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -148,7 +148,7 @@ static void disable_cpu_irq(unsigned int irq)
148static void end_cpu_irq(unsigned int irq) 148static void end_cpu_irq(unsigned int irq)
149{ 149{
150 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 150 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
151 enable_cpu_irq (irq); 151 enable_cpu_irq(irq);
152} 152}
153 153
154static struct irq_chip ip32_cpu_interrupt = { 154static struct irq_chip ip32_cpu_interrupt = {
@@ -289,11 +289,11 @@ static struct irq_chip ip32_macepci_interrupt = {
289 289
290static unsigned long maceisa_mask; 290static unsigned long maceisa_mask;
291 291
292static void enable_maceisa_irq (unsigned int irq) 292static void enable_maceisa_irq(unsigned int irq)
293{ 293{
294 unsigned int crime_int = 0; 294 unsigned int crime_int = 0;
295 295
296 DBG ("maceisa enable: %u\n", irq); 296 DBG("maceisa enable: %u\n", irq);
297 297
298 switch (irq) { 298 switch (irq) {
299 case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ: 299 case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
@@ -306,7 +306,7 @@ static void enable_maceisa_irq (unsigned int irq)
306 crime_int = MACE_SUPERIO_INT; 306 crime_int = MACE_SUPERIO_INT;
307 break; 307 break;
308 } 308 }
309 DBG ("crime_int %08x enabled\n", crime_int); 309 DBG("crime_int %08x enabled\n", crime_int);
310 crime_mask |= crime_int; 310 crime_mask |= crime_int;
311 crime->imask = crime_mask; 311 crime->imask = crime_mask;
312 maceisa_mask |= 1 << (irq - 33); 312 maceisa_mask |= 1 << (irq - 33);
@@ -397,15 +397,15 @@ static struct irq_chip ip32_mace_interrupt = {
397 397
398static void ip32_unknown_interrupt(void) 398static void ip32_unknown_interrupt(void)
399{ 399{
400 printk ("Unknown interrupt occurred!\n"); 400 printk("Unknown interrupt occurred!\n");
401 printk ("cp0_status: %08x\n", read_c0_status()); 401 printk("cp0_status: %08x\n", read_c0_status());
402 printk ("cp0_cause: %08x\n", read_c0_cause()); 402 printk("cp0_cause: %08x\n", read_c0_cause());
403 printk ("CRIME intr mask: %016lx\n", crime->imask); 403 printk("CRIME intr mask: %016lx\n", crime->imask);
404 printk ("CRIME intr status: %016lx\n", crime->istat); 404 printk("CRIME intr status: %016lx\n", crime->istat);
405 printk ("CRIME hardware intr register: %016lx\n", crime->hard_int); 405 printk("CRIME hardware intr register: %016lx\n", crime->hard_int);
406 printk ("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask); 406 printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
407 printk ("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat); 407 printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
408 printk ("MACE PCI control register: %08x\n", mace->pci.control); 408 printk("MACE PCI control register: %08x\n", mace->pci.control);
409 409
410 printk("Register dump:\n"); 410 printk("Register dump:\n");
411 show_regs(get_irq_regs()); 411 show_regs(get_irq_regs());
diff --git a/arch/mips/sgi-ip32/ip32-memory.c b/arch/mips/sgi-ip32/ip32-memory.c
index 849d392a0013..ca93ecf825ae 100644
--- a/arch/mips/sgi-ip32/ip32-memory.c
+++ b/arch/mips/sgi-ip32/ip32-memory.c
@@ -19,7 +19,7 @@
19 19
20extern void crime_init(void); 20extern void crime_init(void);
21 21
22void __init prom_meminit (void) 22void __init prom_meminit(void)
23{ 23{
24 u64 base, size; 24 u64 base, size;
25 int bank; 25 int bank;
@@ -38,7 +38,7 @@ void __init prom_meminit (void)
38 38
39 printk("CRIME MC: bank %u base 0x%016lx size %luMiB\n", 39 printk("CRIME MC: bank %u base 0x%016lx size %luMiB\n",
40 bank, base, size >> 20); 40 bank, base, size >> 20);
41 add_memory_region (base, size, BOOT_MEM_RAM); 41 add_memory_region(base, size, BOOT_MEM_RAM);
42 } 42 }
43} 43}
44 44
diff --git a/arch/mips/sibyte/common/sb_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c
index 4fcdaa8ba514..63b444eaf01e 100644
--- a/arch/mips/sibyte/common/sb_tbprof.c
+++ b/arch/mips/sibyte/common/sb_tbprof.c
@@ -276,8 +276,8 @@ static int sbprof_zbprof_start(struct file *filp)
276 sbp.next_tb_sample = 0; 276 sbp.next_tb_sample = 0;
277 filp->f_pos = 0; 277 filp->f_pos = 0;
278 278
279 err = request_irq (K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, 279 err = request_irq(K_INT_TRACE_FREEZE, sbprof_tb_intr, 0,
280 DEVNAME " trace freeze", &sbp); 280 DEVNAME " trace freeze", &sbp);
281 if (err) 281 if (err)
282 return -EBUSY; 282 return -EBUSY;
283 283
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index acc9ba76c1a9..b74607599971 100644
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -127,7 +127,7 @@ static u32 a20r_ack_hwint(void)
127{ 127{
128 u32 status = read_c0_status(); 128 u32 status = read_c0_status();
129 129
130 write_c0_status (status | 0x00010000); 130 write_c0_status(status | 0x00010000);
131 asm volatile( 131 asm volatile(
132 " .set push \n" 132 " .set push \n"
133 " .set noat \n" 133 " .set noat \n"
@@ -195,7 +195,7 @@ static void a20r_hwint(void)
195 u32 cause, status; 195 u32 cause, status;
196 int irq; 196 int irq;
197 197
198 clear_c0_status (IE_IRQ0); 198 clear_c0_status(IE_IRQ0);
199 status = a20r_ack_hwint(); 199 status = a20r_ack_hwint();
200 cause = read_c0_cause(); 200 cause = read_c0_cause();
201 201
@@ -213,7 +213,7 @@ void __init sni_a20r_irq_init(void)
213 set_irq_chip(i, &a20r_irq_type); 213 set_irq_chip(i, &a20r_irq_type);
214 sni_hwint = a20r_hwint; 214 sni_hwint = a20r_hwint;
215 change_c0_status(ST0_IM, IE_IRQ0); 215 change_c0_status(ST0_IM, IE_IRQ0);
216 setup_irq (SNI_A20R_IRQ_BASE + 3, &sni_isa_irq); 216 setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq);
217} 217}
218 218
219void sni_a20r_init(void) 219void sni_a20r_init(void)
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index 25cf646329ae..39bb15f1f2a6 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -284,9 +284,9 @@ static void sni_pcimt_hwint(void)
284 u32 pending = read_c0_cause() & read_c0_status(); 284 u32 pending = read_c0_cause() & read_c0_status();
285 285
286 if (pending & C_IRQ5) 286 if (pending & C_IRQ5)
287 do_IRQ (MIPS_CPU_IRQ_BASE + 7); 287 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
288 else if (pending & C_IRQ4) 288 else if (pending & C_IRQ4)
289 do_IRQ (MIPS_CPU_IRQ_BASE + 6); 289 do_IRQ(MIPS_CPU_IRQ_BASE + 6);
290 else if (pending & C_IRQ3) 290 else if (pending & C_IRQ3)
291 pcimt_hwint3(); 291 pcimt_hwint3();
292 else if (pending & C_IRQ1) 292 else if (pending & C_IRQ1)
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index 3361bdd240e6..416f397c768b 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -188,8 +188,8 @@ static void pcit_hwint1(void)
188 irq = ffs((pending >> 16) & 0x7f); 188 irq = ffs((pending >> 16) & 0x7f);
189 189
190 if (likely(irq > 0)) 190 if (likely(irq > 0))
191 do_IRQ (irq + SNI_PCIT_INT_START - 1); 191 do_IRQ(irq + SNI_PCIT_INT_START - 1);
192 set_c0_status (IE_IRQ1); 192 set_c0_status(IE_IRQ1);
193} 193}
194 194
195static void pcit_hwint0(void) 195static void pcit_hwint0(void)
@@ -201,8 +201,8 @@ static void pcit_hwint0(void)
201 irq = ffs((pending >> 16) & 0x3f); 201 irq = ffs((pending >> 16) & 0x3f);
202 202
203 if (likely(irq > 0)) 203 if (likely(irq > 0))
204 do_IRQ (irq + SNI_PCIT_INT_START - 1); 204 do_IRQ(irq + SNI_PCIT_INT_START - 1);
205 set_c0_status (IE_IRQ0); 205 set_c0_status(IE_IRQ0);
206} 206}
207 207
208static void sni_pcit_hwint(void) 208static void sni_pcit_hwint(void)
@@ -212,11 +212,11 @@ static void sni_pcit_hwint(void)
212 if (pending & C_IRQ1) 212 if (pending & C_IRQ1)
213 pcit_hwint1(); 213 pcit_hwint1();
214 else if (pending & C_IRQ2) 214 else if (pending & C_IRQ2)
215 do_IRQ (MIPS_CPU_IRQ_BASE + 4); 215 do_IRQ(MIPS_CPU_IRQ_BASE + 4);
216 else if (pending & C_IRQ3) 216 else if (pending & C_IRQ3)
217 do_IRQ (MIPS_CPU_IRQ_BASE + 5); 217 do_IRQ(MIPS_CPU_IRQ_BASE + 5);
218 else if (pending & C_IRQ5) 218 else if (pending & C_IRQ5)
219 do_IRQ (MIPS_CPU_IRQ_BASE + 7); 219 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
220} 220}
221 221
222static void sni_pcit_hwint_cplus(void) 222static void sni_pcit_hwint_cplus(void)
@@ -226,13 +226,13 @@ static void sni_pcit_hwint_cplus(void)
226 if (pending & C_IRQ0) 226 if (pending & C_IRQ0)
227 pcit_hwint0(); 227 pcit_hwint0();
228 else if (pending & C_IRQ1) 228 else if (pending & C_IRQ1)
229 do_IRQ (MIPS_CPU_IRQ_BASE + 3); 229 do_IRQ(MIPS_CPU_IRQ_BASE + 3);
230 else if (pending & C_IRQ2) 230 else if (pending & C_IRQ2)
231 do_IRQ (MIPS_CPU_IRQ_BASE + 4); 231 do_IRQ(MIPS_CPU_IRQ_BASE + 4);
232 else if (pending & C_IRQ3) 232 else if (pending & C_IRQ3)
233 do_IRQ (MIPS_CPU_IRQ_BASE + 5); 233 do_IRQ(MIPS_CPU_IRQ_BASE + 5);
234 else if (pending & C_IRQ5) 234 else if (pending & C_IRQ5)
235 do_IRQ (MIPS_CPU_IRQ_BASE + 7); 235 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
236} 236}
237 237
238void __init sni_pcit_irq_init(void) 238void __init sni_pcit_irq_init(void)
@@ -245,7 +245,7 @@ void __init sni_pcit_irq_init(void)
245 *(volatile u32 *)SNI_PCIT_INT_REG = 0; 245 *(volatile u32 *)SNI_PCIT_INT_REG = 0;
246 sni_hwint = sni_pcit_hwint; 246 sni_hwint = sni_pcit_hwint;
247 change_c0_status(ST0_IM, IE_IRQ1); 247 change_c0_status(ST0_IM, IE_IRQ1);
248 setup_irq (SNI_PCIT_INT_START + 6, &sni_isa_irq); 248 setup_irq(SNI_PCIT_INT_START + 6, &sni_isa_irq);
249} 249}
250 250
251void __init sni_pcit_cplus_irq_init(void) 251void __init sni_pcit_cplus_irq_init(void)
@@ -258,7 +258,7 @@ void __init sni_pcit_cplus_irq_init(void)
258 *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000; 258 *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
259 sni_hwint = sni_pcit_hwint_cplus; 259 sni_hwint = sni_pcit_hwint_cplus;
260 change_c0_status(ST0_IM, IE_IRQ0); 260 change_c0_status(ST0_IM, IE_IRQ0);
261 setup_irq (MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq); 261 setup_irq(MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq);
262} 262}
263 263
264void __init sni_pcit_init(void) 264void __init sni_pcit_init(void)
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index 94f115c6b2e0..67b061eef6cd 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -162,16 +162,16 @@ static void sni_rm200_hwint(void)
162 int irq; 162 int irq;
163 163
164 if (pending & C_IRQ5) 164 if (pending & C_IRQ5)
165 do_IRQ (MIPS_CPU_IRQ_BASE + 7); 165 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
166 else if (pending & C_IRQ0) { 166 else if (pending & C_IRQ0) {
167 clear_c0_status (IE_IRQ0); 167 clear_c0_status(IE_IRQ0);
168 mask = *(volatile u8 *)SNI_RM200_INT_ENA_REG ^ 0x1f; 168 mask = *(volatile u8 *)SNI_RM200_INT_ENA_REG ^ 0x1f;
169 stat = *(volatile u8 *)SNI_RM200_INT_STAT_REG ^ 0x14; 169 stat = *(volatile u8 *)SNI_RM200_INT_STAT_REG ^ 0x14;
170 irq = ffs(stat & mask & 0x1f); 170 irq = ffs(stat & mask & 0x1f);
171 171
172 if (likely(irq > 0)) 172 if (likely(irq > 0))
173 do_IRQ (irq + SNI_RM200_INT_START - 1); 173 do_IRQ(irq + SNI_RM200_INT_START - 1);
174 set_c0_status (IE_IRQ0); 174 set_c0_status(IE_IRQ0);
175 } 175 }
176} 176}
177 177
@@ -187,7 +187,7 @@ void __init sni_rm200_irq_init(void)
187 set_irq_chip(i, &rm200_irq_type); 187 set_irq_chip(i, &rm200_irq_type);
188 sni_hwint = sni_rm200_hwint; 188 sni_hwint = sni_rm200_hwint;
189 change_c0_status(ST0_IM, IE_IRQ0); 189 change_c0_status(ST0_IM, IE_IRQ0);
190 setup_irq (SNI_RM200_INT_START + 0, &sni_isa_irq); 190 setup_irq(SNI_RM200_INT_START + 0, &sni_isa_irq);
191} 191}
192 192
193void __init sni_rm200_init(void) 193void __init sni_rm200_init(void)
diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c
index 883e35ea4e82..e8b26bdee24c 100644
--- a/arch/mips/sni/setup.c
+++ b/arch/mips/sni/setup.c
@@ -106,11 +106,11 @@ static void __devinit quirk_cirrus_ram_size(struct pci_dev *dev)
106 * need to do it here, otherwise we get screen corruption 106 * need to do it here, otherwise we get screen corruption
107 * on older Cirrus chips 107 * on older Cirrus chips
108 */ 108 */
109 pci_read_config_word (dev, PCI_COMMAND, &cmd); 109 pci_read_config_word(dev, PCI_COMMAND, &cmd);
110 if ((cmd & (PCI_COMMAND_IO|PCI_COMMAND_MEMORY)) 110 if ((cmd & (PCI_COMMAND_IO|PCI_COMMAND_MEMORY))
111 == (PCI_COMMAND_IO|PCI_COMMAND_MEMORY)) { 111 == (PCI_COMMAND_IO|PCI_COMMAND_MEMORY)) {
112 vga_wseq (NULL, CL_SEQR6, 0x12); /* unlock all extension registers */ 112 vga_wseq(NULL, CL_SEQR6, 0x12); /* unlock all extension registers */
113 vga_wseq (NULL, CL_SEQRF, 0x18); 113 vga_wseq(NULL, CL_SEQRF, 0x18);
114 } 114 }
115} 115}
116 116
diff --git a/arch/mips/sni/sniprom.c b/arch/mips/sni/sniprom.c
index db544a6e23f3..11eddd43458d 100644
--- a/arch/mips/sni/sniprom.c
+++ b/arch/mips/sni/sniprom.c
@@ -45,7 +45,7 @@ void prom_putchar(char c)
45static char *(*__prom_getenv)(char *) = (char *(*)(char *))PROM_ENTRY(PROM_GETENV); 45static char *(*__prom_getenv)(char *) = (char *(*)(char *))PROM_ENTRY(PROM_GETENV);
46static void (*__prom_get_memconf)(void *) = (void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF); 46static void (*__prom_get_memconf)(void *) = (void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF);
47 47
48char *prom_getenv (char *s) 48char *prom_getenv(char *s)
49{ 49{
50 return __prom_getenv(s); 50 return __prom_getenv(s);
51} 51}
@@ -131,9 +131,9 @@ static void __init sni_console_setup(void)
131 int port; 131 int port;
132 static char options[8]; 132 static char options[8];
133 133
134 cdev = prom_getenv ("console_dev"); 134 cdev = prom_getenv("console_dev");
135 if (strncmp (cdev, "tty", 3) == 0) { 135 if (strncmp (cdev, "tty", 3) == 0) {
136 ctype = prom_getenv ("console"); 136 ctype = prom_getenv("console");
137 switch (*ctype) { 137 switch (*ctype) {
138 default: 138 default:
139 case 'l': 139 case 'l':
diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c
index 153f065434ea..b80877349d38 100644
--- a/arch/mips/sni/time.c
+++ b/arch/mips/sni/time.c
@@ -44,23 +44,23 @@ static __init unsigned long dosample(void)
44 volatile u8 msb, lsb; 44 volatile u8 msb, lsb;
45 45
46 /* Start the counter. */ 46 /* Start the counter. */
47 outb_p (0x34, 0x43); 47 outb_p(0x34, 0x43);
48 outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40); 48 outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40);
49 outb (SNI_8254_TCSAMP_COUNTER >> 8, 0x40); 49 outb(SNI_8254_TCSAMP_COUNTER >> 8, 0x40);
50 50
51 /* Get initial counter invariant */ 51 /* Get initial counter invariant */
52 ct0 = read_c0_count(); 52 ct0 = read_c0_count();
53 53
54 /* Latch and spin until top byte of counter0 is zero */ 54 /* Latch and spin until top byte of counter0 is zero */
55 do { 55 do {
56 outb (0x00, 0x43); 56 outb(0x00, 0x43);
57 lsb = inb (0x40); 57 lsb = inb(0x40);
58 msb = inb (0x40); 58 msb = inb(0x40);
59 ct1 = read_c0_count(); 59 ct1 = read_c0_count();
60 } while (msb); 60 } while (msb);
61 61
62 /* Stop the counter. */ 62 /* Stop the counter. */
63 outb (0x38, 0x43); 63 outb(0x38, 0x43);
64 /* 64 /*
65 * Return the difference, this is how far the r4k counter increments 65 * Return the difference, this is how far the r4k counter increments
66 * for every 1/HZ seconds. We round off the nearest 1 MHz of master 66 * for every 1/HZ seconds. We round off the nearest 1 MHz of master
@@ -137,7 +137,7 @@ void __init plat_timer_setup(struct irqaction *irq)
137 case SNI_BRD_10NEW: 137 case SNI_BRD_10NEW:
138 case SNI_BRD_TOWER_OASIC: 138 case SNI_BRD_TOWER_OASIC:
139 case SNI_BRD_MINITOWER: 139 case SNI_BRD_MINITOWER:
140 sni_a20r_timer_setup (irq); 140 sni_a20r_timer_setup(irq);
141 break; 141 break;
142 142
143 case SNI_BRD_PCI_TOWER: 143 case SNI_BRD_PCI_TOWER:
@@ -146,7 +146,7 @@ void __init plat_timer_setup(struct irqaction *irq)
146 case SNI_BRD_PCI_DESKTOP: 146 case SNI_BRD_PCI_DESKTOP:
147 case SNI_BRD_PCI_TOWER_CPLUS: 147 case SNI_BRD_PCI_TOWER_CPLUS:
148 case SNI_BRD_PCI_MTOWER_CPLUS: 148 case SNI_BRD_PCI_MTOWER_CPLUS:
149 sni_cpu_timer_setup (irq); 149 sni_cpu_timer_setup(irq);
150 break; 150 break;
151 } 151 }
152} 152}
diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h
index c5f20df780e9..7a881755800f 100644
--- a/include/asm-mips/asmmacro.h
+++ b/include/asm-mips/asmmacro.h
@@ -56,27 +56,27 @@
56 * Temporary until all gas have MT ASE support 56 * Temporary until all gas have MT ASE support
57 */ 57 */
58 .macro DMT reg=0 58 .macro DMT reg=0
59 .word (0x41600bc1 | (\reg << 16)) 59 .word 0x41600bc1 | (\reg << 16)
60 .endm 60 .endm
61 61
62 .macro EMT reg=0 62 .macro EMT reg=0
63 .word (0x41600be1 | (\reg << 16)) 63 .word 0x41600be1 | (\reg << 16)
64 .endm 64 .endm
65 65
66 .macro DVPE reg=0 66 .macro DVPE reg=0
67 .word (0x41600001 | (\reg << 16)) 67 .word 0x41600001 | (\reg << 16)
68 .endm 68 .endm
69 69
70 .macro EVPE reg=0 70 .macro EVPE reg=0
71 .word (0x41600021 | (\reg << 16)) 71 .word 0x41600021 | (\reg << 16)
72 .endm 72 .endm
73 73
74 .macro MFTR rt=0, rd=0, u=0, sel=0 74 .macro MFTR rt=0, rd=0, u=0, sel=0
75 .word (0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)) 75 .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
76 .endm 76 .endm
77 77
78 .macro MTTR rt=0, rd=0, u=0, sel=0 78 .macro MTTR rt=0, rd=0, u=0, sel=0
79 .word (0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)) 79 .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
80 .endm 80 .endm
81 81
82#endif /* _ASM_ASMMACRO_H */ 82#endif /* _ASM_ASMMACRO_H */
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 148bc79557f1..899357a72ac4 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -19,14 +19,14 @@
19#include <asm/sgidefs.h> 19#include <asm/sgidefs.h>
20#include <asm/war.h> 20#include <asm/war.h>
21 21
22#if (_MIPS_SZLONG == 32) 22#if _MIPS_SZLONG == 32
23#define SZLONG_LOG 5 23#define SZLONG_LOG 5
24#define SZLONG_MASK 31UL 24#define SZLONG_MASK 31UL
25#define __LL "ll " 25#define __LL "ll "
26#define __SC "sc " 26#define __SC "sc "
27#define __INS "ins " 27#define __INS "ins "
28#define __EXT "ext " 28#define __EXT "ext "
29#elif (_MIPS_SZLONG == 64) 29#elif _MIPS_SZLONG == 64
30#define SZLONG_LOG 6 30#define SZLONG_LOG 6
31#define SZLONG_MASK 63UL 31#define SZLONG_MASK 63UL
32#define __LL "lld " 32#define __LL "lld "
@@ -461,7 +461,7 @@ static inline int __ilog2(unsigned long x)
461 int lz; 461 int lz;
462 462
463 if (sizeof(x) == 4) { 463 if (sizeof(x) == 4) {
464 __asm__ ( 464 __asm__(
465 " .set push \n" 465 " .set push \n"
466 " .set mips32 \n" 466 " .set mips32 \n"
467 " clz %0, %1 \n" 467 " clz %0, %1 \n"
@@ -474,7 +474,7 @@ static inline int __ilog2(unsigned long x)
474 474
475 BUG_ON(sizeof(x) != 8); 475 BUG_ON(sizeof(x) != 8);
476 476
477 __asm__ ( 477 __asm__(
478 " .set push \n" 478 " .set push \n"
479 " .set mips64 \n" 479 " .set mips64 \n"
480 " dclz %0, %1 \n" 480 " dclz %0, %1 \n"
@@ -508,7 +508,7 @@ static inline unsigned long __ffs(unsigned long word)
508 */ 508 */
509static inline int fls(int word) 509static inline int fls(int word)
510{ 510{
511 __asm__ ("clz %0, %1" : "=r" (word) : "r" (word)); 511 __asm__("clz %0, %1" : "=r" (word) : "r" (word));
512 512
513 return 32 - word; 513 return 32 - word;
514} 514}
@@ -516,7 +516,7 @@ static inline int fls(int word)
516#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64) 516#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64)
517static inline int fls64(__u64 word) 517static inline int fls64(__u64 word)
518{ 518{
519 __asm__ ("dclz %0, %1" : "=r" (word) : "r" (word)); 519 __asm__("dclz %0, %1" : "=r" (word) : "r" (word));
520 520
521 return 64 - word; 521 return 64 - word;
522} 522}
diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h
index eee83cbdf2b0..fe7dc2d59b69 100644
--- a/include/asm-mips/byteorder.h
+++ b/include/asm-mips/byteorder.h
@@ -65,9 +65,9 @@ static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
65 65
66#endif /* __GNUC__ */ 66#endif /* __GNUC__ */
67 67
68#if defined (__MIPSEB__) 68#if defined(__MIPSEB__)
69# include <linux/byteorder/big_endian.h> 69# include <linux/byteorder/big_endian.h>
70#elif defined (__MIPSEL__) 70#elif defined(__MIPSEL__)
71# include <linux/byteorder/little_endian.h> 71# include <linux/byteorder/little_endian.h>
72#else 72#else
73# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" 73# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h
index e7d95d48177d..766f91ad5cd3 100644
--- a/include/asm-mips/elf.h
+++ b/include/asm-mips/elf.h
@@ -319,7 +319,7 @@ do { \
319struct task_struct; 319struct task_struct;
320 320
321extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs); 321extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs);
322extern int dump_task_regs (struct task_struct *, elf_gregset_t *); 322extern int dump_task_regs(struct task_struct *, elf_gregset_t *);
323extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); 323extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
324 324
325#define ELF_CORE_COPY_REGS(elf_regs, regs) \ 325#define ELF_CORE_COPY_REGS(elf_regs, regs) \
diff --git a/include/asm-mips/fixmap.h b/include/asm-mips/fixmap.h
index 02c8a13fc894..f27b96cfac2e 100644
--- a/include/asm-mips/fixmap.h
+++ b/include/asm-mips/fixmap.h
@@ -60,8 +60,8 @@ enum fixed_addresses {
60 __end_of_fixed_addresses 60 __end_of_fixed_addresses
61}; 61};
62 62
63extern void __set_fixmap (enum fixed_addresses idx, 63extern void __set_fixmap(enum fixed_addresses idx,
64 unsigned long phys, pgprot_t flags); 64 unsigned long phys, pgprot_t flags);
65 65
66#define set_fixmap(idx, phys) \ 66#define set_fixmap(idx, phys) \
67 __set_fixmap(idx, phys, PAGE_KERNEL) 67 __set_fixmap(idx, phys, PAGE_KERNEL)
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h
index b623882bce19..3e7e30d4f418 100644
--- a/include/asm-mips/futex.h
+++ b/include/asm-mips/futex.h
@@ -75,7 +75,7 @@
75} 75}
76 76
77static inline int 77static inline int
78futex_atomic_op_inuser (int encoded_op, int __user *uaddr) 78futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
79{ 79{
80 int op = (encoded_op >> 28) & 7; 80 int op = (encoded_op >> 28) & 7;
81 int cmp = (encoded_op >> 24) & 15; 81 int cmp = (encoded_op >> 24) & 15;
diff --git a/include/asm-mips/inventory.h b/include/asm-mips/inventory.h
index 92d90f75a636..cc88aed23f0f 100644
--- a/include/asm-mips/inventory.h
+++ b/include/asm-mips/inventory.h
@@ -17,8 +17,8 @@ typedef struct inventory_s {
17 17
18extern int inventory_items; 18extern int inventory_items;
19 19
20extern void add_to_inventory (int class, int type, int controller, int unit, int state); 20extern void add_to_inventory(int class, int type, int controller, int unit, int state);
21extern int dump_inventory_to_user (void __user *userbuf, int size); 21extern int dump_inventory_to_user(void __user *userbuf, int size);
22extern int __init init_inventory(void); 22extern int __init init_inventory(void);
23 23
24#endif /* __ASM_INVENTORY_H */ 24#endif /* __ASM_INVENTORY_H */
diff --git a/include/asm-mips/irqflags.h b/include/asm-mips/irqflags.h
index e459fa05db83..881e8866501d 100644
--- a/include/asm-mips/irqflags.h
+++ b/include/asm-mips/irqflags.h
@@ -16,7 +16,7 @@
16#include <linux/compiler.h> 16#include <linux/compiler.h>
17#include <asm/hazards.h> 17#include <asm/hazards.h>
18 18
19__asm__ ( 19__asm__(
20 " .macro raw_local_irq_enable \n" 20 " .macro raw_local_irq_enable \n"
21 " .set push \n" 21 " .set push \n"
22 " .set reorder \n" 22 " .set reorder \n"
@@ -65,7 +65,7 @@ static inline void raw_local_irq_enable(void)
65 * 65 *
66 * Workaround: mask EXL bit of the result or place a nop before mfc0. 66 * Workaround: mask EXL bit of the result or place a nop before mfc0.
67 */ 67 */
68__asm__ ( 68__asm__(
69 " .macro raw_local_irq_disable\n" 69 " .macro raw_local_irq_disable\n"
70 " .set push \n" 70 " .set push \n"
71 " .set noat \n" 71 " .set noat \n"
@@ -96,7 +96,7 @@ static inline void raw_local_irq_disable(void)
96 : "memory"); 96 : "memory");
97} 97}
98 98
99__asm__ ( 99__asm__(
100 " .macro raw_local_save_flags flags \n" 100 " .macro raw_local_save_flags flags \n"
101 " .set push \n" 101 " .set push \n"
102 " .set reorder \n" 102 " .set reorder \n"
@@ -113,7 +113,7 @@ __asm__ __volatile__( \
113 "raw_local_save_flags %0" \ 113 "raw_local_save_flags %0" \
114 : "=r" (x)) 114 : "=r" (x))
115 115
116__asm__ ( 116__asm__(
117 " .macro raw_local_irq_save result \n" 117 " .macro raw_local_irq_save result \n"
118 " .set push \n" 118 " .set push \n"
119 " .set reorder \n" 119 " .set reorder \n"
@@ -145,7 +145,7 @@ __asm__ __volatile__( \
145 : /* no inputs */ \ 145 : /* no inputs */ \
146 : "memory") 146 : "memory")
147 147
148__asm__ ( 148__asm__(
149 " .macro raw_local_irq_restore flags \n" 149 " .macro raw_local_irq_restore flags \n"
150 " .set push \n" 150 " .set push \n"
151 " .set noreorder \n" 151 " .set noreorder \n"
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 58fca8a5a9a6..10f613f23c33 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -951,25 +951,25 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
951/* Programmable Counters 0 and 1 */ 951/* Programmable Counters 0 and 1 */
952#define SYS_BASE 0xB1900000 952#define SYS_BASE 0xB1900000
953#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) 953#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
954 #define SYS_CNTRL_E1S (1<<23) 954# define SYS_CNTRL_E1S (1<<23)
955 #define SYS_CNTRL_T1S (1<<20) 955# define SYS_CNTRL_T1S (1<<20)
956 #define SYS_CNTRL_M21 (1<<19) 956# define SYS_CNTRL_M21 (1<<19)
957 #define SYS_CNTRL_M11 (1<<18) 957# define SYS_CNTRL_M11 (1<<18)
958 #define SYS_CNTRL_M01 (1<<17) 958# define SYS_CNTRL_M01 (1<<17)
959 #define SYS_CNTRL_C1S (1<<16) 959# define SYS_CNTRL_C1S (1<<16)
960 #define SYS_CNTRL_BP (1<<14) 960# define SYS_CNTRL_BP (1<<14)
961 #define SYS_CNTRL_EN1 (1<<13) 961# define SYS_CNTRL_EN1 (1<<13)
962 #define SYS_CNTRL_BT1 (1<<12) 962# define SYS_CNTRL_BT1 (1<<12)
963 #define SYS_CNTRL_EN0 (1<<11) 963# define SYS_CNTRL_EN0 (1<<11)
964 #define SYS_CNTRL_BT0 (1<<10) 964# define SYS_CNTRL_BT0 (1<<10)
965 #define SYS_CNTRL_E0 (1<<8) 965# define SYS_CNTRL_E0 (1<<8)
966 #define SYS_CNTRL_E0S (1<<7) 966# define SYS_CNTRL_E0S (1<<7)
967 #define SYS_CNTRL_32S (1<<5) 967# define SYS_CNTRL_32S (1<<5)
968 #define SYS_CNTRL_T0S (1<<4) 968# define SYS_CNTRL_T0S (1<<4)
969 #define SYS_CNTRL_M20 (1<<3) 969# define SYS_CNTRL_M20 (1<<3)
970 #define SYS_CNTRL_M10 (1<<2) 970# define SYS_CNTRL_M10 (1<<2)
971 #define SYS_CNTRL_M00 (1<<1) 971# define SYS_CNTRL_M00 (1<<1)
972 #define SYS_CNTRL_C0S (1<<0) 972# define SYS_CNTRL_C0S (1<<0)
973 973
974/* Programmable Counter 0 Registers */ 974/* Programmable Counter 0 Registers */
975#define SYS_TOYTRIM (SYS_BASE + 0) 975#define SYS_TOYTRIM (SYS_BASE + 0)
@@ -989,34 +989,34 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
989 989
990/* I2S Controller */ 990/* I2S Controller */
991#define I2S_DATA 0xB1000000 991#define I2S_DATA 0xB1000000
992 #define I2S_DATA_MASK (0xffffff) 992# define I2S_DATA_MASK (0xffffff)
993#define I2S_CONFIG 0xB1000004 993#define I2S_CONFIG 0xB1000004
994 #define I2S_CONFIG_XU (1<<25) 994# define I2S_CONFIG_XU (1<<25)
995 #define I2S_CONFIG_XO (1<<24) 995# define I2S_CONFIG_XO (1<<24)
996 #define I2S_CONFIG_RU (1<<23) 996# define I2S_CONFIG_RU (1<<23)
997 #define I2S_CONFIG_RO (1<<22) 997# define I2S_CONFIG_RO (1<<22)
998 #define I2S_CONFIG_TR (1<<21) 998# define I2S_CONFIG_TR (1<<21)
999 #define I2S_CONFIG_TE (1<<20) 999# define I2S_CONFIG_TE (1<<20)
1000 #define I2S_CONFIG_TF (1<<19) 1000# define I2S_CONFIG_TF (1<<19)
1001 #define I2S_CONFIG_RR (1<<18) 1001# define I2S_CONFIG_RR (1<<18)
1002 #define I2S_CONFIG_RE (1<<17) 1002# define I2S_CONFIG_RE (1<<17)
1003 #define I2S_CONFIG_RF (1<<16) 1003# define I2S_CONFIG_RF (1<<16)
1004 #define I2S_CONFIG_PD (1<<11) 1004# define I2S_CONFIG_PD (1<<11)
1005 #define I2S_CONFIG_LB (1<<10) 1005# define I2S_CONFIG_LB (1<<10)
1006 #define I2S_CONFIG_IC (1<<9) 1006# define I2S_CONFIG_IC (1<<9)
1007 #define I2S_CONFIG_FM_BIT 7 1007# define I2S_CONFIG_FM_BIT 7
1008 #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) 1008# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1009 #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) 1009# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1010 #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) 1010# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1011 #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) 1011# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
1012 #define I2S_CONFIG_TN (1<<6) 1012# define I2S_CONFIG_TN (1<<6)
1013 #define I2S_CONFIG_RN (1<<5) 1013# define I2S_CONFIG_RN (1<<5)
1014 #define I2S_CONFIG_SZ_BIT 0 1014# define I2S_CONFIG_SZ_BIT 0
1015 #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) 1015# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1016 1016
1017#define I2S_CONTROL 0xB1000008 1017#define I2S_CONTROL 0xB1000008
1018 #define I2S_CONTROL_D (1<<1) 1018# define I2S_CONTROL_D (1<<1)
1019 #define I2S_CONTROL_CE (1<<0) 1019# define I2S_CONTROL_CE (1<<0)
1020 1020
1021/* USB Host Controller */ 1021/* USB Host Controller */
1022#ifndef USB_OHCI_LEN 1022#ifndef USB_OHCI_LEN
@@ -1034,38 +1034,38 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1034#define USBD_EP5RD 0xB0200014 1034#define USBD_EP5RD 0xB0200014
1035#define USBD_INTEN 0xB0200018 1035#define USBD_INTEN 0xB0200018
1036#define USBD_INTSTAT 0xB020001C 1036#define USBD_INTSTAT 0xB020001C
1037 #define USBDEV_INT_SOF (1<<12) 1037# define USBDEV_INT_SOF (1<<12)
1038 #define USBDEV_INT_HF_BIT 6 1038# define USBDEV_INT_HF_BIT 6
1039 #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) 1039# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
1040 #define USBDEV_INT_CMPLT_BIT 0 1040# define USBDEV_INT_CMPLT_BIT 0
1041 #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) 1041# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
1042#define USBD_CONFIG 0xB0200020 1042#define USBD_CONFIG 0xB0200020
1043#define USBD_EP0CS 0xB0200024 1043#define USBD_EP0CS 0xB0200024
1044#define USBD_EP2CS 0xB0200028 1044#define USBD_EP2CS 0xB0200028
1045#define USBD_EP3CS 0xB020002C 1045#define USBD_EP3CS 0xB020002C
1046#define USBD_EP4CS 0xB0200030 1046#define USBD_EP4CS 0xB0200030
1047#define USBD_EP5CS 0xB0200034 1047#define USBD_EP5CS 0xB0200034
1048 #define USBDEV_CS_SU (1<<14) 1048# define USBDEV_CS_SU (1<<14)
1049 #define USBDEV_CS_NAK (1<<13) 1049# define USBDEV_CS_NAK (1<<13)
1050 #define USBDEV_CS_ACK (1<<12) 1050# define USBDEV_CS_ACK (1<<12)
1051 #define USBDEV_CS_BUSY (1<<11) 1051# define USBDEV_CS_BUSY (1<<11)
1052 #define USBDEV_CS_TSIZE_BIT 1 1052# define USBDEV_CS_TSIZE_BIT 1
1053 #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) 1053# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
1054 #define USBDEV_CS_STALL (1<<0) 1054# define USBDEV_CS_STALL (1<<0)
1055#define USBD_EP0RDSTAT 0xB0200040 1055#define USBD_EP0RDSTAT 0xB0200040
1056#define USBD_EP0WRSTAT 0xB0200044 1056#define USBD_EP0WRSTAT 0xB0200044
1057#define USBD_EP2WRSTAT 0xB0200048 1057#define USBD_EP2WRSTAT 0xB0200048
1058#define USBD_EP3WRSTAT 0xB020004C 1058#define USBD_EP3WRSTAT 0xB020004C
1059#define USBD_EP4RDSTAT 0xB0200050 1059#define USBD_EP4RDSTAT 0xB0200050
1060#define USBD_EP5RDSTAT 0xB0200054 1060#define USBD_EP5RDSTAT 0xB0200054
1061 #define USBDEV_FSTAT_FLUSH (1<<6) 1061# define USBDEV_FSTAT_FLUSH (1<<6)
1062 #define USBDEV_FSTAT_UF (1<<5) 1062# define USBDEV_FSTAT_UF (1<<5)
1063 #define USBDEV_FSTAT_OF (1<<4) 1063# define USBDEV_FSTAT_OF (1<<4)
1064 #define USBDEV_FSTAT_FCNT_BIT 0 1064# define USBDEV_FSTAT_FCNT_BIT 0
1065 #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) 1065# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
1066#define USBD_ENABLE 0xB0200058 1066#define USBD_ENABLE 0xB0200058
1067 #define USBDEV_ENABLE (1<<1) 1067# define USBDEV_ENABLE (1<<1)
1068 #define USBDEV_CE (1<<0) 1068# define USBDEV_CE (1<<0)
1069 1069
1070#endif /* !CONFIG_SOC_AU1200 */ 1070#endif /* !CONFIG_SOC_AU1200 */
1071 1071
@@ -1073,55 +1073,55 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1073 1073
1074/* 4 byte offsets from AU1000_ETH_BASE */ 1074/* 4 byte offsets from AU1000_ETH_BASE */
1075#define MAC_CONTROL 0x0 1075#define MAC_CONTROL 0x0
1076 #define MAC_RX_ENABLE (1<<2) 1076# define MAC_RX_ENABLE (1<<2)
1077 #define MAC_TX_ENABLE (1<<3) 1077# define MAC_TX_ENABLE (1<<3)
1078 #define MAC_DEF_CHECK (1<<5) 1078# define MAC_DEF_CHECK (1<<5)
1079 #define MAC_SET_BL(X) (((X)&0x3)<<6) 1079# define MAC_SET_BL(X) (((X)&0x3)<<6)
1080 #define MAC_AUTO_PAD (1<<8) 1080# define MAC_AUTO_PAD (1<<8)
1081 #define MAC_DISABLE_RETRY (1<<10) 1081# define MAC_DISABLE_RETRY (1<<10)
1082 #define MAC_DISABLE_BCAST (1<<11) 1082# define MAC_DISABLE_BCAST (1<<11)
1083 #define MAC_LATE_COL (1<<12) 1083# define MAC_LATE_COL (1<<12)
1084 #define MAC_HASH_MODE (1<<13) 1084# define MAC_HASH_MODE (1<<13)
1085 #define MAC_HASH_ONLY (1<<15) 1085# define MAC_HASH_ONLY (1<<15)
1086 #define MAC_PASS_ALL (1<<16) 1086# define MAC_PASS_ALL (1<<16)
1087 #define MAC_INVERSE_FILTER (1<<17) 1087# define MAC_INVERSE_FILTER (1<<17)
1088 #define MAC_PROMISCUOUS (1<<18) 1088# define MAC_PROMISCUOUS (1<<18)
1089 #define MAC_PASS_ALL_MULTI (1<<19) 1089# define MAC_PASS_ALL_MULTI (1<<19)
1090 #define MAC_FULL_DUPLEX (1<<20) 1090# define MAC_FULL_DUPLEX (1<<20)
1091 #define MAC_NORMAL_MODE 0 1091# define MAC_NORMAL_MODE 0
1092 #define MAC_INT_LOOPBACK (1<<21) 1092# define MAC_INT_LOOPBACK (1<<21)
1093 #define MAC_EXT_LOOPBACK (1<<22) 1093# define MAC_EXT_LOOPBACK (1<<22)
1094 #define MAC_DISABLE_RX_OWN (1<<23) 1094# define MAC_DISABLE_RX_OWN (1<<23)
1095 #define MAC_BIG_ENDIAN (1<<30) 1095# define MAC_BIG_ENDIAN (1<<30)
1096 #define MAC_RX_ALL (1<<31) 1096# define MAC_RX_ALL (1<<31)
1097#define MAC_ADDRESS_HIGH 0x4 1097#define MAC_ADDRESS_HIGH 0x4
1098#define MAC_ADDRESS_LOW 0x8 1098#define MAC_ADDRESS_LOW 0x8
1099#define MAC_MCAST_HIGH 0xC 1099#define MAC_MCAST_HIGH 0xC
1100#define MAC_MCAST_LOW 0x10 1100#define MAC_MCAST_LOW 0x10
1101#define MAC_MII_CNTRL 0x14 1101#define MAC_MII_CNTRL 0x14
1102 #define MAC_MII_BUSY (1<<0) 1102# define MAC_MII_BUSY (1<<0)
1103 #define MAC_MII_READ 0 1103# define MAC_MII_READ 0
1104 #define MAC_MII_WRITE (1<<1) 1104# define MAC_MII_WRITE (1<<1)
1105 #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) 1105# define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
1106 #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) 1106# define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
1107#define MAC_MII_DATA 0x18 1107#define MAC_MII_DATA 0x18
1108#define MAC_FLOW_CNTRL 0x1C 1108#define MAC_FLOW_CNTRL 0x1C
1109 #define MAC_FLOW_CNTRL_BUSY (1<<0) 1109# define MAC_FLOW_CNTRL_BUSY (1<<0)
1110 #define MAC_FLOW_CNTRL_ENABLE (1<<1) 1110# define MAC_FLOW_CNTRL_ENABLE (1<<1)
1111 #define MAC_PASS_CONTROL (1<<2) 1111# define MAC_PASS_CONTROL (1<<2)
1112 #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) 1112# define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
1113#define MAC_VLAN1_TAG 0x20 1113#define MAC_VLAN1_TAG 0x20
1114#define MAC_VLAN2_TAG 0x24 1114#define MAC_VLAN2_TAG 0x24
1115 1115
1116/* Ethernet Controller Enable */ 1116/* Ethernet Controller Enable */
1117 1117
1118 #define MAC_EN_CLOCK_ENABLE (1<<0) 1118# define MAC_EN_CLOCK_ENABLE (1<<0)
1119 #define MAC_EN_RESET0 (1<<1) 1119# define MAC_EN_RESET0 (1<<1)
1120 #define MAC_EN_TOSS (0<<2) 1120# define MAC_EN_TOSS (0<<2)
1121 #define MAC_EN_CACHEABLE (1<<3) 1121# define MAC_EN_CACHEABLE (1<<3)
1122 #define MAC_EN_RESET1 (1<<4) 1122# define MAC_EN_RESET1 (1<<4)
1123 #define MAC_EN_RESET2 (1<<5) 1123# define MAC_EN_RESET2 (1<<5)
1124 #define MAC_DMA_RESET (1<<6) 1124# define MAC_DMA_RESET (1<<6)
1125 1125
1126/* Ethernet Controller DMA Channels */ 1126/* Ethernet Controller DMA Channels */
1127 1127
@@ -1129,22 +1129,22 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1129#define MAC1_TX_DMA_ADDR 0xB4004200 1129#define MAC1_TX_DMA_ADDR 0xB4004200
1130/* offsets from MAC_TX_RING_ADDR address */ 1130/* offsets from MAC_TX_RING_ADDR address */
1131#define MAC_TX_BUFF0_STATUS 0x0 1131#define MAC_TX_BUFF0_STATUS 0x0
1132 #define TX_FRAME_ABORTED (1<<0) 1132# define TX_FRAME_ABORTED (1<<0)
1133 #define TX_JAB_TIMEOUT (1<<1) 1133# define TX_JAB_TIMEOUT (1<<1)
1134 #define TX_NO_CARRIER (1<<2) 1134# define TX_NO_CARRIER (1<<2)
1135 #define TX_LOSS_CARRIER (1<<3) 1135# define TX_LOSS_CARRIER (1<<3)
1136 #define TX_EXC_DEF (1<<4) 1136# define TX_EXC_DEF (1<<4)
1137 #define TX_LATE_COLL_ABORT (1<<5) 1137# define TX_LATE_COLL_ABORT (1<<5)
1138 #define TX_EXC_COLL (1<<6) 1138# define TX_EXC_COLL (1<<6)
1139 #define TX_UNDERRUN (1<<7) 1139# define TX_UNDERRUN (1<<7)
1140 #define TX_DEFERRED (1<<8) 1140# define TX_DEFERRED (1<<8)
1141 #define TX_LATE_COLL (1<<9) 1141# define TX_LATE_COLL (1<<9)
1142 #define TX_COLL_CNT_MASK (0xF<<10) 1142# define TX_COLL_CNT_MASK (0xF<<10)
1143 #define TX_PKT_RETRY (1<<31) 1143# define TX_PKT_RETRY (1<<31)
1144#define MAC_TX_BUFF0_ADDR 0x4 1144#define MAC_TX_BUFF0_ADDR 0x4
1145 #define TX_DMA_ENABLE (1<<0) 1145# define TX_DMA_ENABLE (1<<0)
1146 #define TX_T_DONE (1<<1) 1146# define TX_T_DONE (1<<1)
1147 #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) 1147# define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
1148#define MAC_TX_BUFF0_LEN 0x8 1148#define MAC_TX_BUFF0_LEN 0x8
1149#define MAC_TX_BUFF1_STATUS 0x10 1149#define MAC_TX_BUFF1_STATUS 0x10
1150#define MAC_TX_BUFF1_ADDR 0x14 1150#define MAC_TX_BUFF1_ADDR 0x14
@@ -1160,34 +1160,34 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1160#define MAC1_RX_DMA_ADDR 0xB4004300 1160#define MAC1_RX_DMA_ADDR 0xB4004300
1161/* offsets from MAC_RX_RING_ADDR */ 1161/* offsets from MAC_RX_RING_ADDR */
1162#define MAC_RX_BUFF0_STATUS 0x0 1162#define MAC_RX_BUFF0_STATUS 0x0
1163 #define RX_FRAME_LEN_MASK 0x3fff 1163# define RX_FRAME_LEN_MASK 0x3fff
1164 #define RX_WDOG_TIMER (1<<14) 1164# define RX_WDOG_TIMER (1<<14)
1165 #define RX_RUNT (1<<15) 1165# define RX_RUNT (1<<15)
1166 #define RX_OVERLEN (1<<16) 1166# define RX_OVERLEN (1<<16)
1167 #define RX_COLL (1<<17) 1167# define RX_COLL (1<<17)
1168 #define RX_ETHER (1<<18) 1168# define RX_ETHER (1<<18)
1169 #define RX_MII_ERROR (1<<19) 1169# define RX_MII_ERROR (1<<19)
1170 #define RX_DRIBBLING (1<<20) 1170# define RX_DRIBBLING (1<<20)
1171 #define RX_CRC_ERROR (1<<21) 1171# define RX_CRC_ERROR (1<<21)
1172 #define RX_VLAN1 (1<<22) 1172# define RX_VLAN1 (1<<22)
1173 #define RX_VLAN2 (1<<23) 1173# define RX_VLAN2 (1<<23)
1174 #define RX_LEN_ERROR (1<<24) 1174# define RX_LEN_ERROR (1<<24)
1175 #define RX_CNTRL_FRAME (1<<25) 1175# define RX_CNTRL_FRAME (1<<25)
1176 #define RX_U_CNTRL_FRAME (1<<26) 1176# define RX_U_CNTRL_FRAME (1<<26)
1177 #define RX_MCAST_FRAME (1<<27) 1177# define RX_MCAST_FRAME (1<<27)
1178 #define RX_BCAST_FRAME (1<<28) 1178# define RX_BCAST_FRAME (1<<28)
1179 #define RX_FILTER_FAIL (1<<29) 1179# define RX_FILTER_FAIL (1<<29)
1180 #define RX_PACKET_FILTER (1<<30) 1180# define RX_PACKET_FILTER (1<<30)
1181 #define RX_MISSED_FRAME (1<<31) 1181# define RX_MISSED_FRAME (1<<31)
1182 1182
1183 #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ 1183# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1184 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ 1184 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1185 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) 1185 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1186#define MAC_RX_BUFF0_ADDR 0x4 1186#define MAC_RX_BUFF0_ADDR 0x4
1187 #define RX_DMA_ENABLE (1<<0) 1187# define RX_DMA_ENABLE (1<<0)
1188 #define RX_T_DONE (1<<1) 1188# define RX_T_DONE (1<<1)
1189 #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) 1189# define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
1190 #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) 1190# define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
1191#define MAC_RX_BUFF1_STATUS 0x10 1191#define MAC_RX_BUFF1_STATUS 0x10
1192#define MAC_RX_BUFF1_ADDR 0x14 1192#define MAC_RX_BUFF1_ADDR 0x14
1193#define MAC_RX_BUFF2_STATUS 0x20 1193#define MAC_RX_BUFF2_STATUS 0x20
@@ -1298,44 +1298,44 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1298 1298
1299/* SSIO */ 1299/* SSIO */
1300#define SSI0_STATUS 0xB1600000 1300#define SSI0_STATUS 0xB1600000
1301 #define SSI_STATUS_BF (1<<4) 1301# define SSI_STATUS_BF (1<<4)
1302 #define SSI_STATUS_OF (1<<3) 1302# define SSI_STATUS_OF (1<<3)
1303 #define SSI_STATUS_UF (1<<2) 1303# define SSI_STATUS_UF (1<<2)
1304 #define SSI_STATUS_D (1<<1) 1304# define SSI_STATUS_D (1<<1)
1305 #define SSI_STATUS_B (1<<0) 1305# define SSI_STATUS_B (1<<0)
1306#define SSI0_INT 0xB1600004 1306#define SSI0_INT 0xB1600004
1307 #define SSI_INT_OI (1<<3) 1307# define SSI_INT_OI (1<<3)
1308 #define SSI_INT_UI (1<<2) 1308# define SSI_INT_UI (1<<2)
1309 #define SSI_INT_DI (1<<1) 1309# define SSI_INT_DI (1<<1)
1310#define SSI0_INT_ENABLE 0xB1600008 1310#define SSI0_INT_ENABLE 0xB1600008
1311 #define SSI_INTE_OIE (1<<3) 1311# define SSI_INTE_OIE (1<<3)
1312 #define SSI_INTE_UIE (1<<2) 1312# define SSI_INTE_UIE (1<<2)
1313 #define SSI_INTE_DIE (1<<1) 1313# define SSI_INTE_DIE (1<<1)
1314#define SSI0_CONFIG 0xB1600020 1314#define SSI0_CONFIG 0xB1600020
1315 #define SSI_CONFIG_AO (1<<24) 1315# define SSI_CONFIG_AO (1<<24)
1316 #define SSI_CONFIG_DO (1<<23) 1316# define SSI_CONFIG_DO (1<<23)
1317 #define SSI_CONFIG_ALEN_BIT 20 1317# define SSI_CONFIG_ALEN_BIT 20
1318 #define SSI_CONFIG_ALEN_MASK (0x7<<20) 1318# define SSI_CONFIG_ALEN_MASK (0x7<<20)
1319 #define SSI_CONFIG_DLEN_BIT 16 1319# define SSI_CONFIG_DLEN_BIT 16
1320 #define SSI_CONFIG_DLEN_MASK (0x7<<16) 1320# define SSI_CONFIG_DLEN_MASK (0x7<<16)
1321 #define SSI_CONFIG_DD (1<<11) 1321# define SSI_CONFIG_DD (1<<11)
1322 #define SSI_CONFIG_AD (1<<10) 1322# define SSI_CONFIG_AD (1<<10)
1323 #define SSI_CONFIG_BM_BIT 8 1323# define SSI_CONFIG_BM_BIT 8
1324 #define SSI_CONFIG_BM_MASK (0x3<<8) 1324# define SSI_CONFIG_BM_MASK (0x3<<8)
1325 #define SSI_CONFIG_CE (1<<7) 1325# define SSI_CONFIG_CE (1<<7)
1326 #define SSI_CONFIG_DP (1<<6) 1326# define SSI_CONFIG_DP (1<<6)
1327 #define SSI_CONFIG_DL (1<<5) 1327# define SSI_CONFIG_DL (1<<5)
1328 #define SSI_CONFIG_EP (1<<4) 1328# define SSI_CONFIG_EP (1<<4)
1329#define SSI0_ADATA 0xB1600024 1329#define SSI0_ADATA 0xB1600024
1330 #define SSI_AD_D (1<<24) 1330# define SSI_AD_D (1<<24)
1331 #define SSI_AD_ADDR_BIT 16 1331# define SSI_AD_ADDR_BIT 16
1332 #define SSI_AD_ADDR_MASK (0xff<<16) 1332# define SSI_AD_ADDR_MASK (0xff<<16)
1333 #define SSI_AD_DATA_BIT 0 1333# define SSI_AD_DATA_BIT 0
1334 #define SSI_AD_DATA_MASK (0xfff<<0) 1334# define SSI_AD_DATA_MASK (0xfff<<0)
1335#define SSI0_CLKDIV 0xB1600028 1335#define SSI0_CLKDIV 0xB1600028
1336#define SSI0_CONTROL 0xB1600100 1336#define SSI0_CONTROL 0xB1600100
1337 #define SSI_CONTROL_CD (1<<1) 1337# define SSI_CONTROL_CD (1<<1)
1338 #define SSI_CONTROL_E (1<<0) 1338# define SSI_CONTROL_E (1<<0)
1339 1339
1340/* SSI1 */ 1340/* SSI1 */
1341#define SSI1_STATUS 0xB1680000 1341#define SSI1_STATUS 0xB1680000
@@ -1401,75 +1401,75 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1401#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) 1401#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)
1402#define IR_INT_CLEAR (IRDA_BASE+0x18) 1402#define IR_INT_CLEAR (IRDA_BASE+0x18)
1403#define IR_CONFIG_1 (IRDA_BASE+0x20) 1403#define IR_CONFIG_1 (IRDA_BASE+0x20)
1404 #define IR_RX_INVERT_LED (1<<0) 1404# define IR_RX_INVERT_LED (1<<0)
1405 #define IR_TX_INVERT_LED (1<<1) 1405# define IR_TX_INVERT_LED (1<<1)
1406 #define IR_ST (1<<2) 1406# define IR_ST (1<<2)
1407 #define IR_SF (1<<3) 1407# define IR_SF (1<<3)
1408 #define IR_SIR (1<<4) 1408# define IR_SIR (1<<4)
1409 #define IR_MIR (1<<5) 1409# define IR_MIR (1<<5)
1410 #define IR_FIR (1<<6) 1410# define IR_FIR (1<<6)
1411 #define IR_16CRC (1<<7) 1411# define IR_16CRC (1<<7)
1412 #define IR_TD (1<<8) 1412# define IR_TD (1<<8)
1413 #define IR_RX_ALL (1<<9) 1413# define IR_RX_ALL (1<<9)
1414 #define IR_DMA_ENABLE (1<<10) 1414# define IR_DMA_ENABLE (1<<10)
1415 #define IR_RX_ENABLE (1<<11) 1415# define IR_RX_ENABLE (1<<11)
1416 #define IR_TX_ENABLE (1<<12) 1416# define IR_TX_ENABLE (1<<12)
1417 #define IR_LOOPBACK (1<<14) 1417# define IR_LOOPBACK (1<<14)
1418 #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ 1418# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1419 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) 1419 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1420#define IR_SIR_FLAGS (IRDA_BASE+0x24) 1420#define IR_SIR_FLAGS (IRDA_BASE+0x24)
1421#define IR_ENABLE (IRDA_BASE+0x28) 1421#define IR_ENABLE (IRDA_BASE+0x28)
1422 #define IR_RX_STATUS (1<<9) 1422# define IR_RX_STATUS (1<<9)
1423 #define IR_TX_STATUS (1<<10) 1423# define IR_TX_STATUS (1<<10)
1424#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) 1424#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)
1425#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) 1425#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)
1426#define IR_MAX_PKT_LEN (IRDA_BASE+0x34) 1426#define IR_MAX_PKT_LEN (IRDA_BASE+0x34)
1427#define IR_RX_BYTE_CNT (IRDA_BASE+0x38) 1427#define IR_RX_BYTE_CNT (IRDA_BASE+0x38)
1428#define IR_CONFIG_2 (IRDA_BASE+0x3C) 1428#define IR_CONFIG_2 (IRDA_BASE+0x3C)
1429 #define IR_MODE_INV (1<<0) 1429# define IR_MODE_INV (1<<0)
1430 #define IR_ONE_PIN (1<<1) 1430# define IR_ONE_PIN (1<<1)
1431#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) 1431#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)
1432 1432
1433/* GPIO */ 1433/* GPIO */
1434#define SYS_PINFUNC 0xB190002C 1434#define SYS_PINFUNC 0xB190002C
1435 #define SYS_PF_USB (1<<15) /* 2nd USB device/host */ 1435# define SYS_PF_USB (1<<15) /* 2nd USB device/host */
1436 #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ 1436# define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */
1437 #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ 1437# define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */
1438 #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ 1438# define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */
1439 #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ 1439# define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */
1440 #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ 1440# define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */
1441 #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ 1441# define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */
1442 #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ 1442# define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */
1443 #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ 1443# define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */
1444 #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ 1444# define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */
1445 #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ 1445# define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */
1446 #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ 1446# define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */
1447 #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ 1447# define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */
1448 #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ 1448# define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */
1449 #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ 1449# define SYS_PF_A97 (1<<1) /* AC97/SSL1 */
1450 #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ 1450# define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */
1451 1451
1452/* Au1100 Only */ 1452/* Au1100 Only */
1453 #define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ 1453# define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */
1454 #define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ 1454# define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */
1455 #define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ 1455# define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */
1456 #define SYS_PF_EX0 (1<<9) /* gpio2/clock */ 1456# define SYS_PF_EX0 (1<<9) /* gpio2/clock */
1457 1457
1458/* Au1550 Only. Redefines lots of pins */ 1458/* Au1550 Only. Redefines lots of pins */
1459 #define SYS_PF_PSC2_MASK (7 << 17) 1459# define SYS_PF_PSC2_MASK (7 << 17)
1460 #define SYS_PF_PSC2_AC97 (0) 1460# define SYS_PF_PSC2_AC97 (0)
1461 #define SYS_PF_PSC2_SPI (0) 1461# define SYS_PF_PSC2_SPI (0)
1462 #define SYS_PF_PSC2_I2S (1 << 17) 1462# define SYS_PF_PSC2_I2S (1 << 17)
1463 #define SYS_PF_PSC2_SMBUS (3 << 17) 1463# define SYS_PF_PSC2_SMBUS (3 << 17)
1464 #define SYS_PF_PSC2_GPIO (7 << 17) 1464# define SYS_PF_PSC2_GPIO (7 << 17)
1465 #define SYS_PF_PSC3_MASK (7 << 20) 1465# define SYS_PF_PSC3_MASK (7 << 20)
1466 #define SYS_PF_PSC3_AC97 (0) 1466# define SYS_PF_PSC3_AC97 (0)
1467 #define SYS_PF_PSC3_SPI (0) 1467# define SYS_PF_PSC3_SPI (0)
1468 #define SYS_PF_PSC3_I2S (1 << 20) 1468# define SYS_PF_PSC3_I2S (1 << 20)
1469 #define SYS_PF_PSC3_SMBUS (3 << 20) 1469# define SYS_PF_PSC3_SMBUS (3 << 20)
1470 #define SYS_PF_PSC3_GPIO (7 << 20) 1470# define SYS_PF_PSC3_GPIO (7 << 20)
1471 #define SYS_PF_PSC1_S1 (1 << 1) 1471# define SYS_PF_PSC1_S1 (1 << 1)
1472 #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) 1472# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1473 1473
1474/* Au1200 Only */ 1474/* Au1200 Only */
1475#ifdef CONFIG_SOC_AU1200 1475#ifdef CONFIG_SOC_AU1200
@@ -1530,104 +1530,104 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1530 1530
1531/* Clock Controller */ 1531/* Clock Controller */
1532#define SYS_FREQCTRL0 0xB1900020 1532#define SYS_FREQCTRL0 0xB1900020
1533 #define SYS_FC_FRDIV2_BIT 22 1533# define SYS_FC_FRDIV2_BIT 22
1534 #define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) 1534# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1535 #define SYS_FC_FE2 (1<<21) 1535# define SYS_FC_FE2 (1<<21)
1536 #define SYS_FC_FS2 (1<<20) 1536# define SYS_FC_FS2 (1<<20)
1537 #define SYS_FC_FRDIV1_BIT 12 1537# define SYS_FC_FRDIV1_BIT 12
1538 #define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) 1538# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1539 #define SYS_FC_FE1 (1<<11) 1539# define SYS_FC_FE1 (1<<11)
1540 #define SYS_FC_FS1 (1<<10) 1540# define SYS_FC_FS1 (1<<10)
1541 #define SYS_FC_FRDIV0_BIT 2 1541# define SYS_FC_FRDIV0_BIT 2
1542 #define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) 1542# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1543 #define SYS_FC_FE0 (1<<1) 1543# define SYS_FC_FE0 (1<<1)
1544 #define SYS_FC_FS0 (1<<0) 1544# define SYS_FC_FS0 (1<<0)
1545#define SYS_FREQCTRL1 0xB1900024 1545#define SYS_FREQCTRL1 0xB1900024
1546 #define SYS_FC_FRDIV5_BIT 22 1546# define SYS_FC_FRDIV5_BIT 22
1547 #define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) 1547# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1548 #define SYS_FC_FE5 (1<<21) 1548# define SYS_FC_FE5 (1<<21)
1549 #define SYS_FC_FS5 (1<<20) 1549# define SYS_FC_FS5 (1<<20)
1550 #define SYS_FC_FRDIV4_BIT 12 1550# define SYS_FC_FRDIV4_BIT 12
1551 #define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) 1551# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1552 #define SYS_FC_FE4 (1<<11) 1552# define SYS_FC_FE4 (1<<11)
1553 #define SYS_FC_FS4 (1<<10) 1553# define SYS_FC_FS4 (1<<10)
1554 #define SYS_FC_FRDIV3_BIT 2 1554# define SYS_FC_FRDIV3_BIT 2
1555 #define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) 1555# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1556 #define SYS_FC_FE3 (1<<1) 1556# define SYS_FC_FE3 (1<<1)
1557 #define SYS_FC_FS3 (1<<0) 1557# define SYS_FC_FS3 (1<<0)
1558#define SYS_CLKSRC 0xB1900028 1558#define SYS_CLKSRC 0xB1900028
1559 #define SYS_CS_ME1_BIT 27 1559# define SYS_CS_ME1_BIT 27
1560 #define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT) 1560# define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT)
1561 #define SYS_CS_DE1 (1<<26) 1561# define SYS_CS_DE1 (1<<26)
1562 #define SYS_CS_CE1 (1<<25) 1562# define SYS_CS_CE1 (1<<25)
1563 #define SYS_CS_ME0_BIT 22 1563# define SYS_CS_ME0_BIT 22
1564 #define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT) 1564# define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT)
1565 #define SYS_CS_DE0 (1<<21) 1565# define SYS_CS_DE0 (1<<21)
1566 #define SYS_CS_CE0 (1<<20) 1566# define SYS_CS_CE0 (1<<20)
1567 #define SYS_CS_MI2_BIT 17 1567# define SYS_CS_MI2_BIT 17
1568 #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT) 1568# define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT)
1569 #define SYS_CS_DI2 (1<<16) 1569# define SYS_CS_DI2 (1<<16)
1570 #define SYS_CS_CI2 (1<<15) 1570# define SYS_CS_CI2 (1<<15)
1571#ifdef CONFIG_SOC_AU1100 1571#ifdef CONFIG_SOC_AU1100
1572 #define SYS_CS_ML_BIT 7 1572# define SYS_CS_ML_BIT 7
1573 #define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT) 1573# define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT)
1574 #define SYS_CS_DL (1<<6) 1574# define SYS_CS_DL (1<<6)
1575 #define SYS_CS_CL (1<<5) 1575# define SYS_CS_CL (1<<5)
1576#else 1576#else
1577 #define SYS_CS_MUH_BIT 12 1577# define SYS_CS_MUH_BIT 12
1578 #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT) 1578# define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT)
1579 #define SYS_CS_DUH (1<<11) 1579# define SYS_CS_DUH (1<<11)
1580 #define SYS_CS_CUH (1<<10) 1580# define SYS_CS_CUH (1<<10)
1581 #define SYS_CS_MUD_BIT 7 1581# define SYS_CS_MUD_BIT 7
1582 #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT) 1582# define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT)
1583 #define SYS_CS_DUD (1<<6) 1583# define SYS_CS_DUD (1<<6)
1584 #define SYS_CS_CUD (1<<5) 1584# define SYS_CS_CUD (1<<5)
1585#endif 1585#endif
1586 #define SYS_CS_MIR_BIT 2 1586# define SYS_CS_MIR_BIT 2
1587 #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT) 1587# define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT)
1588 #define SYS_CS_DIR (1<<1) 1588# define SYS_CS_DIR (1<<1)
1589 #define SYS_CS_CIR (1<<0) 1589# define SYS_CS_CIR (1<<0)
1590 1590
1591 #define SYS_CS_MUX_AUX 0x1 1591# define SYS_CS_MUX_AUX 0x1
1592 #define SYS_CS_MUX_FQ0 0x2 1592# define SYS_CS_MUX_FQ0 0x2
1593 #define SYS_CS_MUX_FQ1 0x3 1593# define SYS_CS_MUX_FQ1 0x3
1594 #define SYS_CS_MUX_FQ2 0x4 1594# define SYS_CS_MUX_FQ2 0x4
1595 #define SYS_CS_MUX_FQ3 0x5 1595# define SYS_CS_MUX_FQ3 0x5
1596 #define SYS_CS_MUX_FQ4 0x6 1596# define SYS_CS_MUX_FQ4 0x6
1597 #define SYS_CS_MUX_FQ5 0x7 1597# define SYS_CS_MUX_FQ5 0x7
1598#define SYS_CPUPLL 0xB1900060 1598#define SYS_CPUPLL 0xB1900060
1599#define SYS_AUXPLL 0xB1900064 1599#define SYS_AUXPLL 0xB1900064
1600 1600
1601/* AC97 Controller */ 1601/* AC97 Controller */
1602#define AC97C_CONFIG 0xB0000000 1602#define AC97C_CONFIG 0xB0000000
1603 #define AC97C_RECV_SLOTS_BIT 13 1603# define AC97C_RECV_SLOTS_BIT 13
1604 #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) 1604# define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1605 #define AC97C_XMIT_SLOTS_BIT 3 1605# define AC97C_XMIT_SLOTS_BIT 3
1606 #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) 1606# define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1607 #define AC97C_SG (1<<2) 1607# define AC97C_SG (1<<2)
1608 #define AC97C_SYNC (1<<1) 1608# define AC97C_SYNC (1<<1)
1609 #define AC97C_RESET (1<<0) 1609# define AC97C_RESET (1<<0)
1610#define AC97C_STATUS 0xB0000004 1610#define AC97C_STATUS 0xB0000004
1611 #define AC97C_XU (1<<11) 1611# define AC97C_XU (1<<11)
1612 #define AC97C_XO (1<<10) 1612# define AC97C_XO (1<<10)
1613 #define AC97C_RU (1<<9) 1613# define AC97C_RU (1<<9)
1614 #define AC97C_RO (1<<8) 1614# define AC97C_RO (1<<8)
1615 #define AC97C_READY (1<<7) 1615# define AC97C_READY (1<<7)
1616 #define AC97C_CP (1<<6) 1616# define AC97C_CP (1<<6)
1617 #define AC97C_TR (1<<5) 1617# define AC97C_TR (1<<5)
1618 #define AC97C_TE (1<<4) 1618# define AC97C_TE (1<<4)
1619 #define AC97C_TF (1<<3) 1619# define AC97C_TF (1<<3)
1620 #define AC97C_RR (1<<2) 1620# define AC97C_RR (1<<2)
1621 #define AC97C_RE (1<<1) 1621# define AC97C_RE (1<<1)
1622 #define AC97C_RF (1<<0) 1622# define AC97C_RF (1<<0)
1623#define AC97C_DATA 0xB0000008 1623#define AC97C_DATA 0xB0000008
1624#define AC97C_CMD 0xB000000C 1624#define AC97C_CMD 0xB000000C
1625 #define AC97C_WD_BIT 16 1625# define AC97C_WD_BIT 16
1626 #define AC97C_READ (1<<7) 1626# define AC97C_READ (1<<7)
1627 #define AC97C_INDEX_MASK 0x7f 1627# define AC97C_INDEX_MASK 0x7f
1628#define AC97C_CNTRL 0xB0000010 1628#define AC97C_CNTRL 0xB0000010
1629 #define AC97C_RS (1<<1) 1629# define AC97C_RS (1<<1)
1630 #define AC97C_CE (1<<0) 1630# define AC97C_CE (1<<0)
1631 1631
1632 1632
1633/* Secure Digital (SD) Controller */ 1633/* Secure Digital (SD) Controller */
@@ -1636,12 +1636,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1636#define SD1_XMIT_FIFO 0xB0680000 1636#define SD1_XMIT_FIFO 0xB0680000
1637#define SD1_RECV_FIFO 0xB0680004 1637#define SD1_RECV_FIFO 0xB0680004
1638 1638
1639#if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) 1639#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1640/* Au1500 PCI Controller */ 1640/* Au1500 PCI Controller */
1641#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr 1641#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr
1642#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) 1642#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1643#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) 1643#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1644 #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27)) 1644# define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
1645#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) 1645#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1646#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) 1646#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1647#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) 1647#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h
index 4663e8b415c9..aef0edbfe4c6 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_ide.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h
@@ -136,7 +136,7 @@ void auide_outl(u32 addr, unsigned long port);
136void auide_outsw(unsigned long port, void *addr, u32 count); 136void auide_outsw(unsigned long port, void *addr, u32 count);
137void auide_outsl(unsigned long port, void *addr, u32 count); 137void auide_outsl(unsigned long port, void *addr, u32 count);
138static void auide_tune_drive(ide_drive_t *drive, byte pio); 138static void auide_tune_drive(ide_drive_t *drive, byte pio);
139static int auide_tune_chipset (ide_drive_t *drive, u8 speed); 139static int auide_tune_chipset(ide_drive_t *drive, u8 speed);
140static int auide_ddma_init( _auide_hwif *auide ); 140static int auide_ddma_init( _auide_hwif *auide );
141static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif); 141static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif);
142int __init auide_probe(void); 142int __init auide_probe(void);
diff --git a/include/asm-mips/mach-ip32/kmalloc.h b/include/asm-mips/mach-ip32/kmalloc.h
index f6198a21fba1..b1e0be60f720 100644
--- a/include/asm-mips/mach-ip32/kmalloc.h
+++ b/include/asm-mips/mach-ip32/kmalloc.h
@@ -2,7 +2,7 @@
2#define __ASM_MACH_IP32_KMALLOC_H 2#define __ASM_MACH_IP32_KMALLOC_H
3 3
4 4
5#if defined(CONFIG_CPU_R5000) || defined (CONFIG_CPU_RM7000) 5#if defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_RM7000)
6#define ARCH_KMALLOC_MINALIGN 32 6#define ARCH_KMALLOC_MINALIGN 32
7#else 7#else
8#define ARCH_KMALLOC_MINALIGN 128 8#define ARCH_KMALLOC_MINALIGN 128
diff --git a/include/asm-mips/mach-pb1x00/pb1000.h b/include/asm-mips/mach-pb1x00/pb1000.h
index 50c1e413a688..b52e0e7ee3fb 100644
--- a/include/asm-mips/mach-pb1x00/pb1000.h
+++ b/include/asm-mips/mach-pb1x00/pb1000.h
@@ -32,38 +32,38 @@
32#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) 32#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
33 33
34#define PB1000_PCR 0xBE000000 34#define PB1000_PCR 0xBE000000
35 #define PCR_SLOT_0_VPP0 (1<<0) 35# define PCR_SLOT_0_VPP0 (1<<0)
36 #define PCR_SLOT_0_VPP1 (1<<1) 36# define PCR_SLOT_0_VPP1 (1<<1)
37 #define PCR_SLOT_0_VCC0 (1<<2) 37# define PCR_SLOT_0_VCC0 (1<<2)
38 #define PCR_SLOT_0_VCC1 (1<<3) 38# define PCR_SLOT_0_VCC1 (1<<3)
39 #define PCR_SLOT_0_RST (1<<4) 39# define PCR_SLOT_0_RST (1<<4)
40 40
41 #define PCR_SLOT_1_VPP0 (1<<8) 41# define PCR_SLOT_1_VPP0 (1<<8)
42 #define PCR_SLOT_1_VPP1 (1<<9) 42# define PCR_SLOT_1_VPP1 (1<<9)
43 #define PCR_SLOT_1_VCC0 (1<<10) 43# define PCR_SLOT_1_VCC0 (1<<10)
44 #define PCR_SLOT_1_VCC1 (1<<11) 44# define PCR_SLOT_1_VCC1 (1<<11)
45 #define PCR_SLOT_1_RST (1<<12) 45# define PCR_SLOT_1_RST (1<<12)
46 46
47#define PB1000_MDR 0xBE000004 47#define PB1000_MDR 0xBE000004
48 #define MDR_PI (1<<5) /* pcmcia int latch */ 48# define MDR_PI (1<<5) /* pcmcia int latch */
49 #define MDR_EPI (1<<14) /* enable pcmcia int */ 49# define MDR_EPI (1<<14) /* enable pcmcia int */
50 #define MDR_CPI (1<<15) /* clear pcmcia int */ 50# define MDR_CPI (1<<15) /* clear pcmcia int */
51 51
52#define PB1000_ACR1 0xBE000008 52#define PB1000_ACR1 0xBE000008
53 #define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */ 53# define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */
54 #define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */ 54# define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */
55 #define ACR1_SLOT_0_READY (1<<2) /* ready */ 55# define ACR1_SLOT_0_READY (1<<2) /* ready */
56 #define ACR1_SLOT_0_STATUS (1<<3) /* status change */ 56# define ACR1_SLOT_0_STATUS (1<<3) /* status change */
57 #define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */ 57# define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */
58 #define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */ 58# define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */
59 #define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */ 59# define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */
60 #define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */ 60# define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */
61 #define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */ 61# define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */
62 #define ACR1_SLOT_1_READY (1<<10) /* ready */ 62# define ACR1_SLOT_1_READY (1<<10) /* ready */
63 #define ACR1_SLOT_1_STATUS (1<<11) /* status change */ 63# define ACR1_SLOT_1_STATUS (1<<11) /* status change */
64 #define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */ 64# define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */
65 #define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */ 65# define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */
66 #define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */ 66# define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */
67 67
68#define CPLD_AUX0 0xBE00000C 68#define CPLD_AUX0 0xBE00000C
69#define CPLD_AUX1 0xBE000010 69#define CPLD_AUX1 0xBE000010
diff --git a/include/asm-mips/mach-pb1x00/pb1100.h b/include/asm-mips/mach-pb1x00/pb1100.h
index 4c5a1cd01841..63aa3926b297 100644
--- a/include/asm-mips/mach-pb1x00/pb1100.h
+++ b/include/asm-mips/mach-pb1x00/pb1100.h
@@ -29,44 +29,44 @@
29 29
30#define PB1100_IDENT 0xAE000000 30#define PB1100_IDENT 0xAE000000
31#define BOARD_STATUS_REG 0xAE000004 31#define BOARD_STATUS_REG 0xAE000004
32 #define PB1100_ROM_SEL (1<<15) 32# define PB1100_ROM_SEL (1<<15)
33 #define PB1100_ROM_SIZ (1<<14) 33# define PB1100_ROM_SIZ (1<<14)
34 #define PB1100_SWAP_BOOT (1<<13) 34# define PB1100_SWAP_BOOT (1<<13)
35 #define PB1100_FLASH_WP (1<<12) 35# define PB1100_FLASH_WP (1<<12)
36 #define PB1100_ROM_H_STS (1<<11) 36# define PB1100_ROM_H_STS (1<<11)
37 #define PB1100_ROM_L_STS (1<<10) 37# define PB1100_ROM_L_STS (1<<10)
38 #define PB1100_FLASH_H_STS (1<<9) 38# define PB1100_FLASH_H_STS (1<<9)
39 #define PB1100_FLASH_L_STS (1<<8) 39# define PB1100_FLASH_L_STS (1<<8)
40 #define PB1100_SRAM_SIZ (1<<7) 40# define PB1100_SRAM_SIZ (1<<7)
41 #define PB1100_TSC_BUSY (1<<6) 41# define PB1100_TSC_BUSY (1<<6)
42 #define PB1100_PCMCIA_VS_MASK (3<<4) 42# define PB1100_PCMCIA_VS_MASK (3<<4)
43 #define PB1100_RS232_CD (1<<3) 43# define PB1100_RS232_CD (1<<3)
44 #define PB1100_RS232_CTS (1<<2) 44# define PB1100_RS232_CTS (1<<2)
45 #define PB1100_RS232_DSR (1<<1) 45# define PB1100_RS232_DSR (1<<1)
46 #define PB1100_RS232_RI (1<<0) 46# define PB1100_RS232_RI (1<<0)
47 47
48#define PB1100_IRDA_RS232 0xAE00000C 48#define PB1100_IRDA_RS232 0xAE00000C
49 #define PB1100_IRDA_FULL (0<<14) /* full power */ 49# define PB1100_IRDA_FULL (0<<14) /* full power */
50 #define PB1100_IRDA_SHUTDOWN (1<<14) 50# define PB1100_IRDA_SHUTDOWN (1<<14)
51 #define PB1100_IRDA_TT (2<<14) /* 2/3 power */ 51# define PB1100_IRDA_TT (2<<14) /* 2/3 power */
52 #define PB1100_IRDA_OT (3<<14) /* 1/3 power */ 52# define PB1100_IRDA_OT (3<<14) /* 1/3 power */
53 #define PB1100_IRDA_FIR (1<<13) 53# define PB1100_IRDA_FIR (1<<13)
54 54
55#define PCMCIA_BOARD_REG 0xAE000010 55#define PCMCIA_BOARD_REG 0xAE000010
56 #define PB1100_SD_WP1_RO (1<<15) /* read only */ 56# define PB1100_SD_WP1_RO (1<<15) /* read only */
57 #define PB1100_SD_WP0_RO (1<<14) /* read only */ 57# define PB1100_SD_WP0_RO (1<<14) /* read only */
58 #define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */ 58# define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */
59 #define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */ 59# define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */
60 #define PB1100_SEL_SD_CONN1 (1<<9) 60# define PB1100_SEL_SD_CONN1 (1<<9)
61 #define PB1100_SEL_SD_CONN0 (1<<8) 61# define PB1100_SEL_SD_CONN0 (1<<8)
62 #define PC_DEASSERT_RST (1<<7) 62# define PC_DEASSERT_RST (1<<7)
63 #define PC_DRV_EN (1<<4) 63# define PC_DRV_EN (1<<4)
64 64
65#define PB1100_G_CONTROL 0xAE000014 /* graphics control */ 65#define PB1100_G_CONTROL 0xAE000014 /* graphics control */
66 66
67#define PB1100_RST_VDDI 0xAE00001C 67#define PB1100_RST_VDDI 0xAE00001C
68 #define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */ 68# define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */
69 #define PB1100_VDDI_MASK (0x1F) 69# define PB1100_VDDI_MASK (0x1F)
70 70
71#define PB1100_LEDS 0xAE000018 71#define PB1100_LEDS 0xAE000018
72 72
diff --git a/include/asm-mips/mach-pnx8550/kernel-entry-init.h b/include/asm-mips/mach-pnx8550/kernel-entry-init.h
index 57102fa9da51..982079f410b5 100644
--- a/include/asm-mips/mach-pnx8550/kernel-entry-init.h
+++ b/include/asm-mips/mach-pnx8550/kernel-entry-init.h
@@ -200,10 +200,10 @@ pr4450_instr_cache_invalidated:
200 200
201 icache_invd_loop: 201 icache_invd_loop:
202 /* 9 == register t1 */ 202 /* 9 == register t1 */
203 .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ 203 .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
204 (0 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY0 */ 204 (0 * ICACHE_SET_SIZE) /* invalidate inst cache WAY0 */
205 .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \ 205 .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
206 (1 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY1 */ 206 (1 * ICACHE_SET_SIZE) /* invalidate inst cache WAY1 */
207 207
208 addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */ 208 addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */
209 bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */ 209 bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
@@ -235,14 +235,14 @@ pr4450_instr_cache_invalidated:
235 235
236 dcache_wbinvd_loop: 236 dcache_wbinvd_loop:
237 /* 9 == register t1 */ 237 /* 9 == register t1 */
238 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ 238 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
239 (0 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY0 */ 239 (0 * DCACHE_SET_SIZE) /* writeback/invalidate WAY0 */
240 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ 240 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
241 (1 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY1 */ 241 (1 * DCACHE_SET_SIZE) /* writeback/invalidate WAY1 */
242 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ 242 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
243 (2 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY2 */ 243 (2 * DCACHE_SET_SIZE) /* writeback/invalidate WAY2 */
244 .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \ 244 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
245 (3 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY3 */ 245 (3 * DCACHE_SET_SIZE) /* writeback/invalidate WAY3 */
246 246
247 addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */ 247 addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */
248 bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */ 248 bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */
diff --git a/include/asm-mips/parport.h b/include/asm-mips/parport.h
index a742e04e82de..f52656826cce 100644
--- a/include/asm-mips/parport.h
+++ b/include/asm-mips/parport.h
@@ -6,10 +6,10 @@
6#ifndef _ASM_PARPORT_H 6#ifndef _ASM_PARPORT_H
7#define _ASM_PARPORT_H 7#define _ASM_PARPORT_H
8 8
9static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma); 9static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma);
10static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma) 10static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma)
11{ 11{
12 return parport_pc_find_isa_ports (autoirq, autodma); 12 return parport_pc_find_isa_ports(autoirq, autodma);
13} 13}
14 14
15#endif /* _ASM_PARPORT_H */ 15#endif /* _ASM_PARPORT_H */
diff --git a/include/asm-mips/prctl.h b/include/asm-mips/prctl.h
index 4aaaff670361..8121a9a75bfd 100644
--- a/include/asm-mips/prctl.h
+++ b/include/asm-mips/prctl.h
@@ -36,6 +36,6 @@ struct prda {
36 36
37#define t_sys prda_sys 37#define t_sys prda_sys
38 38
39ptrdiff_t prctl (int op, int v1, int v2); 39ptrdiff_t prctl(int op, int v1, int v2);
40 40
41#endif 41#endif
diff --git a/include/asm-mips/semaphore.h b/include/asm-mips/semaphore.h
index 3d6aa7c7ea81..ea2413c58e78 100644
--- a/include/asm-mips/semaphore.h
+++ b/include/asm-mips/semaphore.h
@@ -51,18 +51,18 @@ struct semaphore {
51#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1) 51#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1)
52#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name, 0) 52#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name, 0)
53 53
54static inline void sema_init (struct semaphore *sem, int val) 54static inline void sema_init(struct semaphore *sem, int val)
55{ 55{
56 atomic_set(&sem->count, val); 56 atomic_set(&sem->count, val);
57 init_waitqueue_head(&sem->wait); 57 init_waitqueue_head(&sem->wait);
58} 58}
59 59
60static inline void init_MUTEX (struct semaphore *sem) 60static inline void init_MUTEX(struct semaphore *sem)
61{ 61{
62 sema_init(sem, 1); 62 sema_init(sem, 1);
63} 63}
64 64
65static inline void init_MUTEX_LOCKED (struct semaphore *sem) 65static inline void init_MUTEX_LOCKED(struct semaphore *sem)
66{ 66{
67 sema_init(sem, 0); 67 sema_init(sem, 0);
68} 68}
diff --git a/include/asm-mips/sim.h b/include/asm-mips/sim.h
index 67c4fe52bb42..0cd719fabb51 100644
--- a/include/asm-mips/sim.h
+++ b/include/asm-mips/sim.h
@@ -18,7 +18,7 @@
18#ifdef CONFIG_32BIT 18#ifdef CONFIG_32BIT
19 19
20#define save_static_function(symbol) \ 20#define save_static_function(symbol) \
21__asm__ ( \ 21__asm__( \
22 ".text\n\t" \ 22 ".text\n\t" \
23 ".globl\t" #symbol "\n\t" \ 23 ".globl\t" #symbol "\n\t" \
24 ".align\t2\n\t" \ 24 ".align\t2\n\t" \
@@ -46,7 +46,7 @@ __asm__ ( \
46#ifdef CONFIG_64BIT 46#ifdef CONFIG_64BIT
47 47
48#define save_static_function(symbol) \ 48#define save_static_function(symbol) \
49__asm__ ( \ 49__asm__( \
50 ".text\n\t" \ 50 ".text\n\t" \
51 ".globl\t" #symbol "\n\t" \ 51 ".globl\t" #symbol "\n\t" \
52 ".align\t2\n\t" \ 52 ".align\t2\n\t" \
diff --git a/include/asm-mips/sn/addrs.h b/include/asm-mips/sn/addrs.h
index 8fa0af6b68d2..6aa086868249 100644
--- a/include/asm-mips/sn/addrs.h
+++ b/include/asm-mips/sn/addrs.h
@@ -50,7 +50,7 @@
50#define TO_NODE_ADDRSPACE(_pa) (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK) 50#define TO_NODE_ADDRSPACE(_pa) (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK)
51 51
52#define CHANGE_ADDR_NASID(_pa, _nasid) \ 52#define CHANGE_ADDR_NASID(_pa, _nasid) \
53 ((UINT64_CAST (_pa) & ~NASID_MASK) | \ 53 ((UINT64_CAST(_pa) & ~NASID_MASK) | \
54 (UINT64_CAST(_nasid) << NASID_SHFT)) 54 (UINT64_CAST(_nasid) << NASID_SHFT))
55 55
56 56
@@ -75,7 +75,7 @@
75 75
76 76
77#define RAW_NODE_SWIN_BASE(nasid, widget) \ 77#define RAW_NODE_SWIN_BASE(nasid, widget) \
78 (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) 78 (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
79 79
80#define WIDGETID_GET(addr) ((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff)) 80#define WIDGETID_GET(addr) ((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff))
81 81
@@ -192,21 +192,21 @@
192#define BDDIR_ENTRY_LO(_pa) ((HSPEC_BASE + \ 192#define BDDIR_ENTRY_LO(_pa) ((HSPEC_BASE + \
193 NODE_ADDRSPACE_SIZE * 3 / 4 + \ 193 NODE_ADDRSPACE_SIZE * 3 / 4 + \
194 0x200) | \ 194 0x200) | \
195 UINT64_CAST (_pa) & NASID_MASK | \ 195 UINT64_CAST(_pa) & NASID_MASK | \
196 UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \ 196 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \
197 UINT64_CAST (_pa) >> 3 & 0x1f << 4) 197 UINT64_CAST(_pa) >> 3 & 0x1f << 4)
198 198
199#define BDDIR_ENTRY_HI(_pa) ((HSPEC_BASE + \ 199#define BDDIR_ENTRY_HI(_pa) ((HSPEC_BASE + \
200 NODE_ADDRSPACE_SIZE * 3 / 4 + \ 200 NODE_ADDRSPACE_SIZE * 3 / 4 + \
201 0x208) | \ 201 0x208) | \
202 UINT64_CAST (_pa) & NASID_MASK | \ 202 UINT64_CAST(_pa) & NASID_MASK | \
203 UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \ 203 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \
204 UINT64_CAST (_pa) >> 3 & 0x1f << 4) 204 UINT64_CAST(_pa) >> 3 & 0x1f << 4)
205 205
206#define BDPRT_ENTRY(_pa, _rgn) ((HSPEC_BASE + \ 206#define BDPRT_ENTRY(_pa, _rgn) ((HSPEC_BASE + \
207 NODE_ADDRSPACE_SIZE * 3 / 4) | \ 207 NODE_ADDRSPACE_SIZE * 3 / 4) | \
208 UINT64_CAST (_pa) & NASID_MASK | \ 208 UINT64_CAST(_pa) & NASID_MASK | \
209 UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \ 209 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \
210 (_rgn) << 3) 210 (_rgn) << 3)
211#define BDPRT_ENTRY_ADDR(_pa,_rgn) (BDPRT_ENTRY((_pa),(_rgn))) 211#define BDPRT_ENTRY_ADDR(_pa,_rgn) (BDPRT_ENTRY((_pa),(_rgn)))
212#define BDPRT_ENTRY_S(_pa,_rgn,_val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn))=(_val)) 212#define BDPRT_ENTRY_S(_pa,_rgn,_val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn))=(_val))
@@ -214,9 +214,9 @@
214 214
215#define BDECC_ENTRY(_pa) ((HSPEC_BASE + \ 215#define BDECC_ENTRY(_pa) ((HSPEC_BASE + \
216 NODE_ADDRSPACE_SIZE / 2) | \ 216 NODE_ADDRSPACE_SIZE / 2) | \
217 UINT64_CAST (_pa) & NASID_MASK | \ 217 UINT64_CAST(_pa) & NASID_MASK | \
218 UINT64_CAST (_pa) >> 2 & BDECC_UPPER_MASK | \ 218 UINT64_CAST(_pa) >> 2 & BDECC_UPPER_MASK | \
219 UINT64_CAST (_pa) >> 3 & 3) 219 UINT64_CAST(_pa) >> 3 & 3)
220 220
221/* 221/*
222 * Macro to convert a back door directory or protection address into the 222 * Macro to convert a back door directory or protection address into the
@@ -225,16 +225,16 @@
225#define BDADDR_IS_DIR(_ba) ((UINT64_CAST (_ba) & 0x200) != 0) 225#define BDADDR_IS_DIR(_ba) ((UINT64_CAST (_ba) & 0x200) != 0)
226#define BDADDR_IS_PRT(_ba) ((UINT64_CAST (_ba) & 0x200) == 0) 226#define BDADDR_IS_PRT(_ba) ((UINT64_CAST (_ba) & 0x200) == 0)
227 227
228#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ 228#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
229 (UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2 | \ 229 (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2 | \
230 (UINT64_CAST (_ba) & 0x1f << 4) << 3) 230 (UINT64_CAST(_ba) & 0x1f << 4) << 3)
231 231
232#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ 232#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
233 (UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2) 233 (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2)
234 234
235#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ 235#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
236 (UINT64_CAST (_ba) & BDECC_UPPER_MASK)<<2 | \ 236 (UINT64_CAST(_ba) & BDECC_UPPER_MASK)<<2 | \
237 (UINT64_CAST (_ba) & 3) << 3) 237 (UINT64_CAST(_ba) & 3) << 3)
238#endif /* CONFIG_SGI_IP27 */ 238#endif /* CONFIG_SGI_IP27 */
239 239
240 240
@@ -282,7 +282,7 @@
282 * the base of the register space. 282 * the base of the register space.
283 */ 283 */
284#define HUB_REG_PTR(_base, _off) \ 284#define HUB_REG_PTR(_base, _off) \
285 (HUBREG_CAST ((__psunsigned_t)(_base) + (__psunsigned_t)(_off))) 285 (HUBREG_CAST((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
286 286
287#define HUB_REG_PTR_L(_base, _off) \ 287#define HUB_REG_PTR_L(_base, _off) \
288 HUB_L(HUB_REG_PTR((_base), (_off))) 288 HUB_L(HUB_REG_PTR((_base), (_off)))
diff --git a/include/asm-mips/sn/io.h b/include/asm-mips/sn/io.h
index ab2fa8cd2627..24c6775fbb0f 100644
--- a/include/asm-mips/sn/io.h
+++ b/include/asm-mips/sn/io.h
@@ -9,7 +9,7 @@
9#ifndef _ASM_SN_IO_H 9#ifndef _ASM_SN_IO_H
10#define _ASM_SN_IO_H 10#define _ASM_SN_IO_H
11 11
12#if defined (CONFIG_SGI_IP27) 12#if defined(CONFIG_SGI_IP27)
13#include <asm/sn/sn0/hubio.h> 13#include <asm/sn/sn0/hubio.h>
14#endif 14#endif
15 15
diff --git a/include/asm-mips/sn/kldir.h b/include/asm-mips/sn/kldir.h
index 0573cbffc104..1327e12e9645 100644
--- a/include/asm-mips/sn/kldir.h
+++ b/include/asm-mips/sn/kldir.h
@@ -140,7 +140,7 @@
140 */ 140 */
141#define SYMMON_STACK_SIZE 0x8000 141#define SYMMON_STACK_SIZE 0x8000
142 142
143#if defined (PROM) 143#if defined(PROM)
144 144
145/* 145/*
146 * These defines are prom version dependent. No code other than the IP27 146 * These defines are prom version dependent. No code other than the IP27
diff --git a/include/asm-mips/sn/sn0/addrs.h b/include/asm-mips/sn/sn0/addrs.h
index 9e8cc52910f6..b06190093bbc 100644
--- a/include/asm-mips/sn/sn0/addrs.h
+++ b/include/asm-mips/sn/sn0/addrs.h
@@ -91,7 +91,7 @@
91 : RAW_NODE_SWIN_BASE(nasid, widget)) 91 : RAW_NODE_SWIN_BASE(nasid, widget))
92#else /* __ASSEMBLY__ */ 92#else /* __ASSEMBLY__ */
93#define NODE_SWIN_BASE(nasid, widget) \ 93#define NODE_SWIN_BASE(nasid, widget) \
94 (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) 94 (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
95#endif /* __ASSEMBLY__ */ 95#endif /* __ASSEMBLY__ */
96 96
97/* 97/*
@@ -106,7 +106,7 @@
106#define BWIN_WIDGET_MASK 0x7 106#define BWIN_WIDGET_MASK 0x7
107#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE) 107#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE)
108#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ 108#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \
109 (UINT64_CAST (bigwin) << BWIN_SIZE_BITS)) 109 (UINT64_CAST(bigwin) << BWIN_SIZE_BITS))
110 110
111#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) 111#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK)
112#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) 112#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
@@ -259,7 +259,7 @@
259 * CACHE_ERR_SP_PTR could either contain an address to the stack, or 259 * CACHE_ERR_SP_PTR could either contain an address to the stack, or
260 * the stack could start at CACHE_ERR_SP_PTR 260 * the stack could start at CACHE_ERR_SP_PTR
261 */ 261 */
262#if defined (HUB_ERR_STS_WAR) 262#if defined(HUB_ERR_STS_WAR)
263#define CACHE_ERR_EFRAME 0x480 263#define CACHE_ERR_EFRAME 0x480
264#else /* HUB_ERR_STS_WAR */ 264#else /* HUB_ERR_STS_WAR */
265#define CACHE_ERR_EFRAME 0x400 265#define CACHE_ERR_EFRAME 0x400
@@ -275,7 +275,7 @@
275 275
276#define _ARCSPROM 276#define _ARCSPROM
277 277
278#if defined (HUB_ERR_STS_WAR) 278#if defined(HUB_ERR_STS_WAR)
279 279
280#define ERR_STS_WAR_REGISTER IIO_IIBUSERR 280#define ERR_STS_WAR_REGISTER IIO_IIBUSERR
281#define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR) 281#define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR)
diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h
index ddaf36a1e389..4d43dbb7f8b8 100644
--- a/include/asm-mips/sni.h
+++ b/include/asm-mips/sni.h
@@ -194,17 +194,17 @@ extern unsigned int sni_brd_type;
194#define PCIMT_INT_ACKNOWLEDGE 0xba000000 194#define PCIMT_INT_ACKNOWLEDGE 0xba000000
195 195
196/* board specific init functions */ 196/* board specific init functions */
197extern void sni_a20r_init (void); 197extern void sni_a20r_init(void);
198extern void sni_pcit_init (void); 198extern void sni_pcit_init(void);
199extern void sni_rm200_init (void); 199extern void sni_rm200_init(void);
200extern void sni_pcimt_init (void); 200extern void sni_pcimt_init(void);
201 201
202/* board specific irq init functions */ 202/* board specific irq init functions */
203extern void sni_a20r_irq_init (void); 203extern void sni_a20r_irq_init(void);
204extern void sni_pcit_irq_init (void); 204extern void sni_pcit_irq_init(void);
205extern void sni_pcit_cplus_irq_init (void); 205extern void sni_pcit_cplus_irq_init(void);
206extern void sni_rm200_irq_init (void); 206extern void sni_rm200_irq_init(void);
207extern void sni_pcimt_irq_init (void); 207extern void sni_pcimt_irq_init(void);
208 208
209/* timer inits */ 209/* timer inits */
210extern void sni_cpu_time_init(void); 210extern void sni_cpu_time_init(void);
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 480b574e2483..862f161e88b6 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -195,11 +195,11 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
195 195
196#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) 196#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
197 197
198extern void set_handler (unsigned long offset, void *addr, unsigned long len); 198extern void set_handler(unsigned long offset, void *addr, unsigned long len);
199extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len); 199extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
200 200
201typedef void (*vi_handler_t)(void); 201typedef void (*vi_handler_t)(void);
202extern void *set_vi_handler (int n, vi_handler_t addr); 202extern void *set_vi_handler(int n, vi_handler_t addr);
203 203
204extern void *set_except_vector(int n, void *addr); 204extern void *set_except_vector(int n, void *addr);
205extern unsigned long ebase; 205extern unsigned long ebase;
diff --git a/include/asm-mips/timex.h b/include/asm-mips/timex.h
index b80de8e0fbbd..87c68ae76ff8 100644
--- a/include/asm-mips/timex.h
+++ b/include/asm-mips/timex.h
@@ -48,7 +48,7 @@
48 48
49typedef unsigned int cycles_t; 49typedef unsigned int cycles_t;
50 50
51static inline cycles_t get_cycles (void) 51static inline cycles_t get_cycles(void)
52{ 52{
53 return read_c0_count(); 53 return read_c0_count();
54} 54}
diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h
index b25511787ee0..017dfb0d75c3 100644
--- a/include/asm-mips/uaccess.h
+++ b/include/asm-mips/uaccess.h
@@ -391,9 +391,9 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
391 391
392#define __invoke_copy_to_user(to,from,n) \ 392#define __invoke_copy_to_user(to,from,n) \
393({ \ 393({ \
394 register void __user *__cu_to_r __asm__ ("$4"); \ 394 register void __user *__cu_to_r __asm__("$4"); \
395 register const void *__cu_from_r __asm__ ("$5"); \ 395 register const void *__cu_from_r __asm__("$5"); \
396 register long __cu_len_r __asm__ ("$6"); \ 396 register long __cu_len_r __asm__("$6"); \
397 \ 397 \
398 __cu_to_r = (to); \ 398 __cu_to_r = (to); \
399 __cu_from_r = (from); \ 399 __cu_from_r = (from); \
@@ -495,9 +495,9 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
495 495
496#define __invoke_copy_from_user(to,from,n) \ 496#define __invoke_copy_from_user(to,from,n) \
497({ \ 497({ \
498 register void *__cu_to_r __asm__ ("$4"); \ 498 register void *__cu_to_r __asm__("$4"); \
499 register const void __user *__cu_from_r __asm__ ("$5"); \ 499 register const void __user *__cu_from_r __asm__("$5"); \
500 register long __cu_len_r __asm__ ("$6"); \ 500 register long __cu_len_r __asm__("$6"); \
501 \ 501 \
502 __cu_to_r = (to); \ 502 __cu_to_r = (to); \
503 __cu_from_r = (from); \ 503 __cu_from_r = (from); \
@@ -518,9 +518,9 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
518 518
519#define __invoke_copy_from_user_inatomic(to,from,n) \ 519#define __invoke_copy_from_user_inatomic(to,from,n) \
520({ \ 520({ \
521 register void *__cu_to_r __asm__ ("$4"); \ 521 register void *__cu_to_r __asm__("$4"); \
522 register const void __user *__cu_from_r __asm__ ("$5"); \ 522 register const void __user *__cu_from_r __asm__("$5"); \
523 register long __cu_len_r __asm__ ("$6"); \ 523 register long __cu_len_r __asm__("$6"); \
524 \ 524 \
525 __cu_to_r = (to); \ 525 __cu_to_r = (to); \
526 __cu_from_r = (from); \ 526 __cu_from_r = (from); \